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RTL code refactoring

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This commit is contained in:
Blaise Tine
2020-04-20 06:47:24 -04:00
parent 5671b08a5e
commit 07135263f5
22 changed files with 334 additions and 474 deletions
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69
hw/rtl/VX_back_end.v
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@@ -32,53 +32,53 @@ assign writeback_if.wb_pc = writeback_temp_if.wb_pc;
// assign VX_writeback_if(writeback_temp_if);
wire no_slot_mem;
wire no_slot_exec;
wire no_slot_mem;
wire no_slot_exec;
// LSU input + output
VX_lsu_req_if lsu_req_if();
VX_inst_mem_wb_if mem_wb_if();
VX_lsu_req_if lsu_req_if();
VX_inst_mem_wb_if mem_wb_if();
// Exec unit input + output
VX_exec_unit_req_if exec_unit_req_if();
VX_inst_exec_wb_if inst_exec_wb_if();
VX_exec_unit_req_if exec_unit_req_if();
VX_inst_exec_wb_if inst_exec_wb_if();
// GPU unit input
VX_gpu_inst_req_if gpu_inst_req_if();
VX_gpu_inst_req_if gpu_inst_req_if();
// CSR unit inputs
VX_csr_req_if csr_req_if();
VX_csr_wb_if csr_wb_if();
wire no_slot_csr;
wire stall_gpr_csr;
VX_csr_req_if csr_req_if();
VX_csr_wb_if csr_wb_if();
wire no_slot_csr;
wire stall_gpr_csr;
VX_gpr_stage gpr_stage (
.clk (clk),
.reset (reset),
.schedule_delay (schedule_delay),
.writeback_if (writeback_temp_if),
.bckE_req_if (bckE_req_if),
.clk (clk),
.reset (reset),
.schedule_delay (schedule_delay),
.writeback_if (writeback_temp_if),
.bckE_req_if (bckE_req_if),
// New
.exec_unit_req_if(exec_unit_req_if),
.lsu_req_if (lsu_req_if),
.gpu_inst_req_if (gpu_inst_req_if),
.csr_req_if (csr_req_if),
.stall_gpr_csr (stall_gpr_csr),
.exec_unit_req_if (exec_unit_req_if),
.lsu_req_if (lsu_req_if),
.gpu_inst_req_if (gpu_inst_req_if),
.csr_req_if (csr_req_if),
.stall_gpr_csr (stall_gpr_csr),
// End new
.memory_delay (out_mem_delay),
.exec_delay (out_exec_delay),
.gpr_stage_delay (gpr_stage_delay)
.memory_delay (out_mem_delay),
.exec_delay (out_exec_delay),
.gpr_stage_delay (gpr_stage_delay)
);
VX_lsu load_store_unit (
.clk (clk),
.reset (reset),
.lsu_req_if (lsu_req_if),
.mem_wb_if (mem_wb_if),
.dcache_rsp_if(dcache_rsp_if),
.dcache_req_if(dcache_req_if),
.out_delay (out_mem_delay),
.no_slot_mem (no_slot_mem)
.clk (clk),
.reset (reset),
.lsu_req_if (lsu_req_if),
.mem_wb_if (mem_wb_if),
.dcache_rsp_if (dcache_rsp_if),
.dcache_req_if (dcache_req_if),
.out_delay (out_mem_delay),
.no_slot_mem (no_slot_mem)
);
VX_execute_unit execUnit (
@@ -97,11 +97,6 @@ VX_gpgpu_inst gpgpu_inst (
.warp_ctl_if (warp_ctl_if)
);
// VX_csr_wrapper csr_wrapper(
// .csr_req_if(csr_req_if),
// .csr_wb_if (csr_wb_if)
// );
VX_csr_pipe #(
.CORE_ID(CORE_ID)
) csr_pipe (