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fixed l2/l3 caches related bugs

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This commit is contained in:
Blaise Tine
2021-01-09 16:32:55 -08:00
parent 5c83c594c1
commit 06945533cf
13 changed files with 354 additions and 274 deletions
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25
hw/rtl/libs/VX_fifo_queue.v
View File

@@ -30,11 +30,13 @@ module VX_fifo_queue #(
head_r <= 0;
size_r <= 0;
end else begin
if (push && !pop) begin
assert(!full);
size_r <= 1;
end else if (pop && !push) begin
assert(!empty);
assert(!push || !full);
assert(!pop || !empty);
if (push) begin
if (!pop) begin
size_r <= 1;
end
end else if (pop) begin
size_r <= 0;
end
if (push) begin
@@ -62,13 +64,14 @@ module VX_fifo_queue #(
end else begin
assert(!push || !full);
assert(!pop || !empty);
if (push && !pop) begin
empty_r <= 0;
if (used_r == ADDRW'(SIZE-1)) begin
full_r <= 1;
if (push) begin
if (!pop) begin
empty_r <= 0;
if (used_r == ADDRW'(SIZE-1)) begin
full_r <= 1;
end
end
end
if (pop && !push) begin
end else if (pop) begin
full_r <= 0;
if (used_r == ADDRW'(1)) begin
empty_r <= 1;

35
hw/rtl/libs/VX_pending_size.v Normal file
View File

@@ -0,0 +1,35 @@
`include "VX_platform.vh"
module VX_pending_size #(
parameter SIZE = 1
) (
input wire clk,
input wire reset,
input wire push,
input wire pop,
output wire full
);
localparam ADDRW = $clog2(SIZE);
reg [ADDRW-1:0] size_r;
reg full_r;
always @(posedge clk) begin
if (reset) begin
size_r <= 0;
full_r <= 0;
end else begin
assert(!push || !full);
if (push) begin
if (!pop && (used_r == ADDRW'(SIZE-1)))
full_r <= 1;
end else if (pop) begin
full_r <= 0;
end
size_r <= size_r + ADDRW'($signed(2'(push && !pop) - 2'(pop && !push)));
end
end
assign full = full_r;
endmodule