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Still giving sc_time_stamp error

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This commit is contained in:
felsabbagh3
2019-10-16 19:45:21 -04:00
parent 8bc3b8b0a5
commit 0690043a43
11 changed files with 375 additions and 905 deletions
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12
models/memory/cln28hpc/rf2_32x128_wm1/Makefile Normal file
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@@ -0,0 +1,12 @@
all: RUNFILE
# -LDFLAGS '-lsystemc'
VERILATOR:
verilator rf2_32x128_wm1_rtl.v -cc --exe testbench.cpp --Wno-UNOPTFLAT --Wno-WIDTH --Wno-STMTDLY --Wno-UNSIGNED
RUNFILE: VERILATOR
(cd obj_dir && make -j -f Vrf2_32x128_wm1_rtl.mk)
clean:
rm obj_dir/*

289
models/memory/cln28hpc/rf2_32x128_wm1/obj_dir/Vrf2_32x128_wm1.cpp
View File

@@ -1,289 +0,0 @@
// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Design implementation internals
// See Vrf2_32x128_wm1.h for the primary calling header
#include "Vrf2_32x128_wm1.h"
#include "Vrf2_32x128_wm1__Syms.h"
//--------------------
// STATIC VARIABLES
//--------------------
VL_CTOR_IMP(Vrf2_32x128_wm1) {
Vrf2_32x128_wm1__Syms* __restrict vlSymsp = __VlSymsp = new Vrf2_32x128_wm1__Syms(this, name());
Vrf2_32x128_wm1* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
// Reset internal values
// Reset structure values
_ctor_var_reset();
}
void Vrf2_32x128_wm1::__Vconfigure(Vrf2_32x128_wm1__Syms* vlSymsp, bool first) {
if (0 && first) {} // Prevent unused
this->__VlSymsp = vlSymsp;
}
Vrf2_32x128_wm1::~Vrf2_32x128_wm1() {
delete __VlSymsp; __VlSymsp=NULL;
}
//--------------------
void Vrf2_32x128_wm1::eval() {
VL_DEBUG_IF(VL_DBG_MSGF("+++++TOP Evaluate Vrf2_32x128_wm1::eval\n"); );
Vrf2_32x128_wm1__Syms* __restrict vlSymsp = this->__VlSymsp; // Setup global symbol table
Vrf2_32x128_wm1* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
#ifdef VL_DEBUG
// Debug assertions
_eval_debug_assertions();
#endif // VL_DEBUG
// Initialize
if (VL_UNLIKELY(!vlSymsp->__Vm_didInit)) _eval_initial_loop(vlSymsp);
// Evaluate till stable
int __VclockLoop = 0;
QData __Vchange = 1;
do {
VL_DEBUG_IF(VL_DBG_MSGF("+ Clock loop\n"););
_eval(vlSymsp);
if (VL_UNLIKELY(++__VclockLoop > 100)) {
// About to fail, so enable debug to see what's not settling.
// Note you must run make with OPT=-DVL_DEBUG for debug prints.
int __Vsaved_debug = Verilated::debug();
Verilated::debug(1);
__Vchange = _change_request(vlSymsp);
Verilated::debug(__Vsaved_debug);
VL_FATAL_MT(__FILE__,__LINE__,__FILE__,"Verilated model didn't converge");
} else {
__Vchange = _change_request(vlSymsp);
}
} while (VL_UNLIKELY(__Vchange));
}
void Vrf2_32x128_wm1::_eval_initial_loop(Vrf2_32x128_wm1__Syms* __restrict vlSymsp) {
vlSymsp->__Vm_didInit = true;
_eval_initial(vlSymsp);
// Evaluate till stable
int __VclockLoop = 0;
QData __Vchange = 1;
do {
_eval_settle(vlSymsp);
_eval(vlSymsp);
if (VL_UNLIKELY(++__VclockLoop > 100)) {
// About to fail, so enable debug to see what's not settling.
// Note you must run make with OPT=-DVL_DEBUG for debug prints.
int __Vsaved_debug = Verilated::debug();
Verilated::debug(1);
__Vchange = _change_request(vlSymsp);
Verilated::debug(__Vsaved_debug);
VL_FATAL_MT(__FILE__,__LINE__,__FILE__,"Verilated model didn't DC converge");
} else {
__Vchange = _change_request(vlSymsp);
}
} while (VL_UNLIKELY(__Vchange));
}
//--------------------
// Internal Methods
VL_INLINE_OPT void Vrf2_32x128_wm1::_combo__TOP__1(Vrf2_32x128_wm1__Syms* __restrict vlSymsp) {
VL_DEBUG_IF(VL_DBG_MSGF("+ Vrf2_32x128_wm1::_combo__TOP__1\n"); );
Vrf2_32x128_wm1* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
// Body
// ALWAYS at rf2_32x128_wm1.v:15356
if ((1U & (((~ (IData)(vlTOPp->CEN)) & (~ (IData)(vlTOPp->DFTRAMBYP)))
& (~ (IData)(vlTOPp->SE))))) {
vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__list_complete = 0U;
vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__i = 0U;
vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__Q_output[0U]
= vlTOPp->Q_in[0U];
vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__Q_output[1U]
= vlTOPp->Q_in[1U];
vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__Q_output[2U]
= vlTOPp->Q_in[2U];
vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__Q_output[3U]
= vlTOPp->Q_in[3U];
while ((1U & (~ (IData)(vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__list_complete)))) {
vlTOPp->rf2_32x128_wm1_error_injection__DOT__fault_entry
= vlTOPp->rf2_32x128_wm1_error_injection__DOT__fault_table
[(0xfU & vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__i)];
vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__row_address
= (0xfU & (vlTOPp->rf2_32x128_wm1_error_injection__DOT__fault_entry
>> 0xdU));
vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__column_address
= (1U & (vlTOPp->rf2_32x128_wm1_error_injection__DOT__fault_entry
>> 0xcU));
vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__bitPlace
= (0x7fU & (vlTOPp->rf2_32x128_wm1_error_injection__DOT__fault_entry
>> 5U));
vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__fault_type
= (3U & (vlTOPp->rf2_32x128_wm1_error_injection__DOT__fault_entry
>> 3U));
vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__red_fault
= (3U & (vlTOPp->rf2_32x128_wm1_error_injection__DOT__fault_entry
>> 1U));
vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__valid
= (1U & vlTOPp->rf2_32x128_wm1_error_injection__DOT__fault_entry);
vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__i
= ((IData)(1U) + vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__i);
if (vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__valid) {
if ((0U == (IData)(vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__red_fault))) {
if ((((IData)(vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__row_address)
== (0xfU & ((IData)(vlTOPp->A)
>> 1U))) & ((IData)(vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__column_address)
==
(1U
& (IData)(vlTOPp->A))))) {
if ((0x40U > (IData)(vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__bitPlace))) {
// Function: bit_error at rf2_32x128_wm1.v:15345
vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__bit_error__1__bitLoc
= vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__bitPlace;
vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__bit_error__1__fault_type
= vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__fault_type;
vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__Q_output[((IData)(vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__bit_error__1__bitLoc)
>> 5U)]
= (((~ ((IData)(1U)
<< (0x1fU & (IData)(vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__bit_error__1__bitLoc))))
& vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__Q_output[
((IData)(vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__bit_error__1__bitLoc)
>> 5U)]) | (((0U
!= (IData)(vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__bit_error__1__fault_type))
& ((1U
== (IData)(vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__bit_error__1__fault_type))
| (~
(vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__Q_output[
((IData)(vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__bit_error__1__bitLoc)
>> 5U)]
>>
(0x1fU
& (IData)(vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__bit_error__1__bitLoc))))))
<<
(0x1fU
& (IData)(vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__bit_error__1__bitLoc))));
} else {
if ((0x40U <= (IData)(vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__bitPlace))) {
// Function: bit_error at rf2_32x128_wm1.v:15347
vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__bit_error__2__bitLoc
= vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__bitPlace;
vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__bit_error__2__fault_type
= vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__fault_type;
vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__Q_output[((IData)(vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__bit_error__2__bitLoc)
>> 5U)]
= (((~ ((IData)(1U)
<< (0x1fU
& (IData)(vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__bit_error__2__bitLoc))))
& vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__Q_output[
((IData)(vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__bit_error__2__bitLoc)
>> 5U)]) |
(((0U != (IData)(vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__bit_error__2__fault_type))
& ((1U == (IData)(vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__bit_error__2__fault_type))
| (~ (vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__Q_output[
((IData)(vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__bit_error__2__bitLoc)
>> 5U)]
>>
(0x1fU
& (IData)(vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__bit_error__2__bitLoc))))))
<< (0x1fU & (IData)(vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__bit_error__2__bitLoc))));
}
}
}
}
} else {
vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__list_complete = 1U;
}
}
vlTOPp->Q_out[0U] = vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__Q_output[0U];
vlTOPp->Q_out[1U] = vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__Q_output[1U];
vlTOPp->Q_out[2U] = vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__Q_output[2U];
vlTOPp->Q_out[3U] = vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__Q_output[3U];
} else {
vlTOPp->Q_out[0U] = vlTOPp->Q_in[0U];
vlTOPp->Q_out[1U] = vlTOPp->Q_in[1U];
vlTOPp->Q_out[2U] = vlTOPp->Q_in[2U];
vlTOPp->Q_out[3U] = vlTOPp->Q_in[3U];
}
}
void Vrf2_32x128_wm1::_eval(Vrf2_32x128_wm1__Syms* __restrict vlSymsp) {
VL_DEBUG_IF(VL_DBG_MSGF("+ Vrf2_32x128_wm1::_eval\n"); );
Vrf2_32x128_wm1* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
// Body
vlTOPp->_combo__TOP__1(vlSymsp);
}
void Vrf2_32x128_wm1::_eval_initial(Vrf2_32x128_wm1__Syms* __restrict vlSymsp) {
VL_DEBUG_IF(VL_DBG_MSGF("+ Vrf2_32x128_wm1::_eval_initial\n"); );
Vrf2_32x128_wm1* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
}
void Vrf2_32x128_wm1::final() {
VL_DEBUG_IF(VL_DBG_MSGF("+ Vrf2_32x128_wm1::final\n"); );
// Variables
Vrf2_32x128_wm1__Syms* __restrict vlSymsp = this->__VlSymsp;
Vrf2_32x128_wm1* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
}
void Vrf2_32x128_wm1::_eval_settle(Vrf2_32x128_wm1__Syms* __restrict vlSymsp) {
VL_DEBUG_IF(VL_DBG_MSGF("+ Vrf2_32x128_wm1::_eval_settle\n"); );
Vrf2_32x128_wm1* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
// Body
vlTOPp->_combo__TOP__1(vlSymsp);
}
VL_INLINE_OPT QData Vrf2_32x128_wm1::_change_request(Vrf2_32x128_wm1__Syms* __restrict vlSymsp) {
VL_DEBUG_IF(VL_DBG_MSGF("+ Vrf2_32x128_wm1::_change_request\n"); );
Vrf2_32x128_wm1* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
// Body
// Change detection
QData __req = false; // Logically a bool
return __req;
}
#ifdef VL_DEBUG
void Vrf2_32x128_wm1::_eval_debug_assertions() {
VL_DEBUG_IF(VL_DBG_MSGF("+ Vrf2_32x128_wm1::_eval_debug_assertions\n"); );
// Body
if (VL_UNLIKELY((CLK & 0xfeU))) {
Verilated::overWidthError("CLK");}
if (VL_UNLIKELY((A & 0xe0U))) {
Verilated::overWidthError("A");}
if (VL_UNLIKELY((CEN & 0xfeU))) {
Verilated::overWidthError("CEN");}
if (VL_UNLIKELY((DFTRAMBYP & 0xfeU))) {
Verilated::overWidthError("DFTRAMBYP");}
if (VL_UNLIKELY((SE & 0xfeU))) {
Verilated::overWidthError("SE");}
}
#endif // VL_DEBUG
void Vrf2_32x128_wm1::_ctor_var_reset() {
VL_DEBUG_IF(VL_DBG_MSGF("+ Vrf2_32x128_wm1::_ctor_var_reset\n"); );
// Body
VL_RAND_RESET_W(128,Q_out);
VL_RAND_RESET_W(128,Q_in);
CLK = VL_RAND_RESET_I(1);
A = VL_RAND_RESET_I(5);
CEN = VL_RAND_RESET_I(1);
DFTRAMBYP = VL_RAND_RESET_I(1);
SE = VL_RAND_RESET_I(1);
{ int __Vi0=0; for (; __Vi0<16; ++__Vi0) {
rf2_32x128_wm1_error_injection__DOT__fault_table[__Vi0] = VL_RAND_RESET_I(17);
}}
rf2_32x128_wm1_error_injection__DOT__fault_entry = VL_RAND_RESET_I(17);
VL_RAND_RESET_W(128,__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__Q_output);
__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__list_complete = VL_RAND_RESET_I(1);
__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__i = VL_RAND_RESET_I(32);
__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__row_address = VL_RAND_RESET_I(4);
__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__column_address = VL_RAND_RESET_I(1);
__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__bitPlace = VL_RAND_RESET_I(7);
__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__fault_type = VL_RAND_RESET_I(2);
__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__red_fault = VL_RAND_RESET_I(2);
__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__valid = VL_RAND_RESET_I(1);
__Vtask_rf2_32x128_wm1_error_injection__DOT__bit_error__1__fault_type = VL_RAND_RESET_I(2);
__Vtask_rf2_32x128_wm1_error_injection__DOT__bit_error__1__bitLoc = VL_RAND_RESET_I(7);
__Vtask_rf2_32x128_wm1_error_injection__DOT__bit_error__2__fault_type = VL_RAND_RESET_I(2);
__Vtask_rf2_32x128_wm1_error_injection__DOT__bit_error__2__bitLoc = VL_RAND_RESET_I(7);
}

101
models/memory/cln28hpc/rf2_32x128_wm1/obj_dir/Vrf2_32x128_wm1.h
View File

@@ -1,101 +0,0 @@
// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Primary design header
//
// This header should be included by all source files instantiating the design.
// The class here is then constructed to instantiate the design.
// See the Verilator manual for examples.
#ifndef _Vrf2_32x128_wm1_H_
#define _Vrf2_32x128_wm1_H_
#include "verilated.h"
class Vrf2_32x128_wm1__Syms;
//----------
VL_MODULE(Vrf2_32x128_wm1) {
public:
// PORTS
// The application code writes and reads these signals to
// propagate new values into/out from the Verilated model.
// Begin mtask footprint all:
VL_IN8(CLK,0,0);
VL_IN8(A,4,0);
VL_IN8(CEN,0,0);
VL_IN8(DFTRAMBYP,0,0);
VL_IN8(SE,0,0);
VL_OUTW(Q_out,127,0,4);
VL_INW(Q_in,127,0,4);
// LOCAL SIGNALS
// Internals; generally not touched by application code
// Begin mtask footprint all:
VL_SIG(rf2_32x128_wm1_error_injection__DOT__fault_entry,16,0);
VL_SIG(rf2_32x128_wm1_error_injection__DOT__fault_table[16],16,0);
// LOCAL VARIABLES
// Internals; generally not touched by application code
// Begin mtask footprint all:
VL_SIG8(__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__list_complete,0,0);
VL_SIG8(__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__row_address,3,0);
VL_SIG8(__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__column_address,0,0);
VL_SIG8(__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__bitPlace,6,0);
VL_SIG8(__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__fault_type,1,0);
VL_SIG8(__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__red_fault,1,0);
VL_SIG8(__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__valid,0,0);
VL_SIG8(__Vtask_rf2_32x128_wm1_error_injection__DOT__bit_error__1__fault_type,1,0);
VL_SIG8(__Vtask_rf2_32x128_wm1_error_injection__DOT__bit_error__1__bitLoc,6,0);
VL_SIG8(__Vtask_rf2_32x128_wm1_error_injection__DOT__bit_error__2__fault_type,1,0);
VL_SIG8(__Vtask_rf2_32x128_wm1_error_injection__DOT__bit_error__2__bitLoc,6,0);
VL_SIGW(__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__Q_output,127,0,4);
VL_SIG(__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__i,31,0);
// INTERNAL VARIABLES
// Internals; generally not touched by application code
Vrf2_32x128_wm1__Syms* __VlSymsp; // Symbol table
// PARAMETERS
// Parameters marked /*verilator public*/ for use by application code
// CONSTRUCTORS
private:
VL_UNCOPYABLE(Vrf2_32x128_wm1); ///< Copying not allowed
public:
/// Construct the model; called by application code
/// The special name may be used to make a wrapper with a
/// single model invisible with respect to DPI scope names.
Vrf2_32x128_wm1(const char* name="TOP");
/// Destroy the model; called (often implicitly) by application code
~Vrf2_32x128_wm1();
// API METHODS
/// Evaluate the model. Application must call when inputs change.
void eval();
/// Simulation complete, run final blocks. Application must call on completion.
void final();
// INTERNAL METHODS
private:
static void _eval_initial_loop(Vrf2_32x128_wm1__Syms* __restrict vlSymsp);
public:
void __Vconfigure(Vrf2_32x128_wm1__Syms* symsp, bool first);
private:
static QData _change_request(Vrf2_32x128_wm1__Syms* __restrict vlSymsp);
public:
static void _combo__TOP__1(Vrf2_32x128_wm1__Syms* __restrict vlSymsp);
private:
void _ctor_var_reset() VL_ATTR_COLD;
public:
static void _eval(Vrf2_32x128_wm1__Syms* __restrict vlSymsp);
private:
#ifdef VL_DEBUG
void _eval_debug_assertions();
#endif // VL_DEBUG
public:
static void _eval_initial(Vrf2_32x128_wm1__Syms* __restrict vlSymsp) VL_ATTR_COLD;
static void _eval_settle(Vrf2_32x128_wm1__Syms* __restrict vlSymsp) VL_ATTR_COLD;
} VL_ATTR_ALIGNED(128);
#endif // guard

53
models/memory/cln28hpc/rf2_32x128_wm1/obj_dir/Vrf2_32x128_wm1.mk
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@@ -1,53 +0,0 @@
# Verilated -*- Makefile -*-
# DESCRIPTION: Verilator output: Makefile for building Verilated archive or executable
#
# Execute this makefile from the object directory:
# make -f Vrf2_32x128_wm1.mk
default: Vrf2_32x128_wm1__ALL.a
### Constants...
# Perl executable (from $PERL)
PERL = perl
# Path to Verilator kit (from $VERILATOR_ROOT)
VERILATOR_ROOT = /usr/local/share/verilator
# SystemC include directory with systemc.h (from $SYSTEMC_INCLUDE)
SYSTEMC_INCLUDE ?=
# SystemC library directory with libsystemc.a (from $SYSTEMC_LIBDIR)
SYSTEMC_LIBDIR ?=
### Switches...
# SystemC output mode? 0/1 (from --sc)
VM_SC = 0
# Legacy or SystemC output mode? 0/1 (from --sc)
VM_SP_OR_SC = $(VM_SC)
# Deprecated
VM_PCLI = 1
# Deprecated: SystemC architecture to find link library path (from $SYSTEMC_ARCH)
VM_SC_TARGET_ARCH = linux
### Vars...
# Design prefix (from --prefix)
VM_PREFIX = Vrf2_32x128_wm1
# Module prefix (from --prefix)
VM_MODPREFIX = Vrf2_32x128_wm1
# User CFLAGS (from -CFLAGS on Verilator command line)
VM_USER_CFLAGS = \
# User LDLIBS (from -LDFLAGS on Verilator command line)
VM_USER_LDLIBS = \
# User .cpp files (from .cpp's on Verilator command line)
VM_USER_CLASSES = \
# User .cpp directories (from .cpp's on Verilator command line)
VM_USER_DIR = \
### Default rules...
# Include list of all generated classes
include Vrf2_32x128_wm1_classes.mk
# Include global rules
include $(VERILATOR_ROOT)/include/verilated.mk
# Verilated -*- Makefile -*-

19
models/memory/cln28hpc/rf2_32x128_wm1/obj_dir/Vrf2_32x128_wm1__Syms.cpp
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@@ -1,19 +0,0 @@
// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Symbol table implementation internals
#include "Vrf2_32x128_wm1__Syms.h"
#include "Vrf2_32x128_wm1.h"
// FUNCTIONS
Vrf2_32x128_wm1__Syms::Vrf2_32x128_wm1__Syms(Vrf2_32x128_wm1* topp, const char* namep)
// Setup locals
: __Vm_namep(namep)
, __Vm_didInit(false)
// Setup submodule names
{
// Pointer to top level
TOPp = topp;
// Setup each module's pointers to their submodules
// Setup each module's pointer back to symbol table (for public functions)
TOPp->__Vconfigure(this, true);
}

35
models/memory/cln28hpc/rf2_32x128_wm1/obj_dir/Vrf2_32x128_wm1__Syms.h
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@@ -1,35 +0,0 @@
// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Symbol table internal header
//
// Internal details; most calling programs do not need this header,
// unless using verilator public meta comments.
#ifndef _Vrf2_32x128_wm1__Syms_H_
#define _Vrf2_32x128_wm1__Syms_H_
#include "verilated.h"
// INCLUDE MODULE CLASSES
#include "Vrf2_32x128_wm1.h"
// SYMS CLASS
class Vrf2_32x128_wm1__Syms : public VerilatedSyms {
public:
// LOCAL STATE
const char* __Vm_namep;
bool __Vm_didInit;
// SUBCELL STATE
Vrf2_32x128_wm1* TOPp;
// CREATORS
Vrf2_32x128_wm1__Syms(Vrf2_32x128_wm1* topp, const char* namep);
~Vrf2_32x128_wm1__Syms() {}
// METHODS
inline const char* name() { return __Vm_namep; }
} VL_ATTR_ALIGNED(64);
#endif // guard

1
models/memory/cln28hpc/rf2_32x128_wm1/obj_dir/Vrf2_32x128_wm1__ver.d
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@@ -1 +0,0 @@
obj_dir/Vrf2_32x128_wm1.cpp obj_dir/Vrf2_32x128_wm1.h obj_dir/Vrf2_32x128_wm1.mk obj_dir/Vrf2_32x128_wm1__Syms.cpp obj_dir/Vrf2_32x128_wm1__Syms.h obj_dir/Vrf2_32x128_wm1__ver.d obj_dir/Vrf2_32x128_wm1_classes.mk : /usr/local/bin/verilator_bin /usr/local/bin/verilator_bin rf2_32x128_wm1.v

12
models/memory/cln28hpc/rf2_32x128_wm1/obj_dir/Vrf2_32x128_wm1__verFiles.dat
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@@ -1,12 +0,0 @@
# DESCRIPTION: Verilator output: Timestamp data for --skip-identical. Delete at will.
C "-cc rf2_32x128_wm1.v"
S 6746612 12892413243 1567548409 0 1567548409 0 "/usr/local/bin/verilator_bin"
T 14325 1013347 1571096194 0 1571096194 0 "obj_dir/Vrf2_32x128_wm1.cpp"
T 4125 1013346 1571096194 0 1571096194 0 "obj_dir/Vrf2_32x128_wm1.h"
T 1478 1013349 1571096194 0 1571096194 0 "obj_dir/Vrf2_32x128_wm1.mk"
T 570 1013345 1571096194 0 1571096194 0 "obj_dir/Vrf2_32x128_wm1__Syms.cpp"
T 817 1013344 1571096194 0 1571096194 0 "obj_dir/Vrf2_32x128_wm1__Syms.h"
T 292 1013350 1571096194 0 1571096194 0 "obj_dir/Vrf2_32x128_wm1__ver.d"
T 0 0 1571096194 0 1571096194 0 "obj_dir/Vrf2_32x128_wm1__verFiles.dat"
T 1269 1013348 1571096194 0 1571096194 0 "obj_dir/Vrf2_32x128_wm1_classes.mk"
S 1252191 1011852 1571096122 0 1571096122 0 "rf2_32x128_wm1.v"

40
models/memory/cln28hpc/rf2_32x128_wm1/obj_dir/Vrf2_32x128_wm1_classes.mk
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@@ -1,40 +0,0 @@
# Verilated -*- Makefile -*-
# DESCRIPTION: Verilator output: Make include file with class lists
#
# This file lists generated Verilated files, for including in higher level makefiles.
# See Vrf2_32x128_wm1.mk for the caller.
### Switches...
# Coverage output mode? 0/1 (from --coverage)
VM_COVERAGE = 0
# Threaded output mode? 0/1/N threads (from --threads)
VM_THREADS = 0
# Tracing output mode? 0/1 (from --trace)
VM_TRACE = 0
# Tracing threadeds output mode? 0/1 (from --trace-fst-thread)
VM_TRACE_THREADED = 0
### Object file lists...
# Generated module classes, fast-path, compile with highest optimization
VM_CLASSES_FAST += \
Vrf2_32x128_wm1 \
# Generated module classes, non-fast-path, compile with low/medium optimization
VM_CLASSES_SLOW += \
# Generated support classes, fast-path, compile with highest optimization
VM_SUPPORT_FAST += \
# Generated support classes, non-fast-path, compile with low/medium optimization
VM_SUPPORT_SLOW += \
Vrf2_32x128_wm1__Syms \
# Global classes, need linked once per executable, fast-path, compile with highest optimization
VM_GLOBAL_FAST += \
verilated \
# Global classes, need linked once per executable, non-fast-path, compile with low/medium optimization
VM_GLOBAL_SLOW += \
# Verilated -*- Makefile -*-

445
models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v
View File

@@ -56,12 +56,6 @@
`define ARM_MEM_HOLD 0.500 `define ARM_MEM_HOLD 0.500
`define ARM_MEM_COLLISION 3.000 `define ARM_MEM_COLLISION 3.000
`define REALTIME 1
`undef POWER_PINS
`undef ARM_MESSAGES
/* verilator lint_off UNUSED */
module datapath_latch_rf2_32x128_wm1 (CLK,Q_update,SE,SI,D,DFTRAMBYP,mem_path,XQ,Q); module datapath_latch_rf2_32x128_wm1 (CLK,Q_update,SE,SI,D,DFTRAMBYP,mem_path,XQ,Q);
input CLK,Q_update,SE,SI,D,DFTRAMBYP,mem_path,XQ; input CLK,Q_update,SE,SI,D,DFTRAMBYP,mem_path,XQ;
output Q; output Q;
@@ -83,7 +77,7 @@ module datapath_latch_rf2_32x128_wm1 (CLK,Q_update,SE,SI,D,DFTRAMBYP,mem_path,XQ
// model output side of RAM latch // model output side of RAM latch
always @(posedge Q_update or posedge XQ) begin always @(posedge Q_update or posedge XQ) begin
//#0; #0;
if (XQ===1'b0) begin if (XQ===1'b0) begin
if (DFTRAMBYP===1'b1) if (DFTRAMBYP===1'b1)
Q=D_int; Q=D_int;
@@ -103,7 +97,7 @@ endmodule // datapath_latch_rf2_32x128_wm1
// ARM_UD_DP Defines the delay through Data Paths, for Memory Models it represents BIST MUX output delays. // ARM_UD_DP Defines the delay through Data Paths, for Memory Models it represents BIST MUX output delays.
`ifdef ARM_UD_DP `ifdef ARM_UD_DP
`else `else
`define ARM_UD_DP //#0.001 `define ARM_UD_DP #0.001
`endif `endif
// ARM_UD_CP Defines the delay through Clock Path Cells, for Memory Models it is not used. // ARM_UD_CP Defines the delay through Clock Path Cells, for Memory Models it is not used.
`ifdef ARM_UD_CP `ifdef ARM_UD_CP
@@ -113,7 +107,7 @@ endmodule // datapath_latch_rf2_32x128_wm1
// ARM_UD_SEQ Defines the delay through the Memory, for Memory Models it is used for CLK->Q delays. // ARM_UD_SEQ Defines the delay through the Memory, for Memory Models it is used for CLK->Q delays.
`ifdef ARM_UD_SEQ `ifdef ARM_UD_SEQ
`else `else
`define ARM_UD_SEQ //#0.01 `define ARM_UD_SEQ #0.01
`endif `endif
`celldefine `celldefine
@@ -1131,23 +1125,23 @@ module rf2_32x128_wm1 (CENYA, AYA, CENYB, WENYB, AYB, QA, SOA, SOB, CLKA, CENA,
`ifdef INITIALIZE_MEMORY `ifdef INITIALIZE_MEMORY
integer i; integer i;
initial begin initial begin
//#0; #0;
for (i = 0; i < MEM_HEIGHT; i = i + 1) for (i = 0; i < MEM_HEIGHT; i = i + 1)
mem[i] = {MEM_WIDTH{1'b0}}; mem[i] = {MEM_WIDTH{1'b0}};
end end
`endif `endif
// always @ (EMAA_) begin always @ (EMAA_) begin
// if(EMAA_ < 3) if(EMAA_ < 3)
// //$display("Warning: Set Value for EMAA doesn't match Default value 3 in %m at %0t", 0); $display("Warning: Set Value for EMAA doesn't match Default value 3 in %m at %0t", $time);
// end end
// always @ (EMASA_) begin always @ (EMASA_) begin
// if(EMASA_ < 0) if(EMASA_ < 0)
// //$display("Warning: Set Value for EMASA doesn't match Default value 0 in %m at %0t", 0); $display("Warning: Set Value for EMASA doesn't match Default value 0 in %m at %0t", $time);
// end end
// always @ (EMAB_) begin always @ (EMAB_) begin
// if(EMAB_ < 3) if(EMAB_ < 3)
// //$display("Warning: Set Value for EMAB doesn't match Default value 3 in %m at %0t", 0); $display("Warning: Set Value for EMAB doesn't match Default value 3 in %m at %0t", $time);
// end end
task failedWrite; task failedWrite;
input port_f; input port_f;
@@ -1660,24 +1654,24 @@ task dumpaddr;
end end
end end
// `ifdef POWER_PINS `ifdef POWER_PINS
// always @ (VDDCE) begin always @ (VDDCE) begin
// if (VDDCE != 1'b1) begin if (VDDCE != 1'b1) begin
// if (VDDPE == 1'b1) begin if (VDDPE == 1'b1) begin
// //$display("VDDCE should be powered down after VDDPE, Illegal power down sequencing in %m at %0t", 0); $display("VDDCE should be powered down after VDDPE, Illegal power down sequencing in %m at %0t", $time);
// end end
// //$display("In PowerDown Mode in %m at %0t", 0); $display("In PowerDown Mode in %m at %0t", $time);
// failedWrite(0); failedWrite(0);
// end end
// if (VDDCE == 1'b1) begin if (VDDCE == 1'b1) begin
// if (VDDPE == 1'b1) begin if (VDDPE == 1'b1) begin
// //$display("VDDPE should be powered up after VDDCE in %m at %0t", 0); $display("VDDPE should be powered up after VDDCE in %m at %0t", $time);
// //$display("Illegal power up sequencing in %m at %0t", 0); $display("Illegal power up sequencing in %m at %0t", $time);
// end end
// failedWrite(0); failedWrite(0);
// end end
// end end
// `endif `endif
`ifdef POWER_PINS `ifdef POWER_PINS
always @ (RET1N_ or VDDPE or VDDCE) begin always @ (RET1N_ or VDDPE or VDDCE) begin
`else `else
@@ -1754,13 +1748,13 @@ task dumpaddr;
COLLDISN_int = 1'bx; COLLDISN_int = 1'bx;
end end
RET1N_int = RET1N_; RET1N_int = RET1N_;
//#0; #0;
QA_update = 1'b0; QA_update = 1'b0;
//#0;//#0; XQA = 1'b0; #0;#0; XQA = 1'b0;
end end
always @ (CLKB_ or DFTRAMBYP_p2) begin always @ (CLKB_ or DFTRAMBYP_p2) begin
//#0; #0;
if(CLKB_ == 1'b1 && (DFTRAMBYP_int === 1'b1 || CENB_int != 1'b1)) begin if(CLKB_ == 1'b1 && (DFTRAMBYP_int === 1'b1 || CENB_int != 1'b1)) begin
if (RET1N_ == 1'b1) begin if (RET1N_ == 1'b1) begin
DB_sh_update = 1'b1; DB_sh_update = 1'b1;
@@ -1770,14 +1764,14 @@ task dumpaddr;
always @ CLKA_ begin always @ CLKA_ begin
// If POWER_PINS is defined at Simulator Command Line, it selects the module definition with Power Ports // If POWER_PINS is defined at Simulator Command Line, it selects the module definition with Power Ports
// `ifdef POWER_PINS `ifdef POWER_PINS
// if (VDDCE === 1'bx || VDDCE === 1'bz) if (VDDCE === 1'bx || VDDCE === 1'bz)
// //$display("Warning: Unknown value for VDDCE %b in %m at %0t", VDDCE, 0); $display("Warning: Unknown value for VDDCE %b in %m at %0t", VDDCE, $time);
// if (VDDPE === 1'bx || VDDPE === 1'bz) if (VDDPE === 1'bx || VDDPE === 1'bz)
// //$display("Warning: Unknown value for VDDPE %b in %m at %0t", VDDPE, 0); $display("Warning: Unknown value for VDDPE %b in %m at %0t", VDDPE, $time);
// if (VSSE === 1'bx || VSSE === 1'bz) if (VSSE === 1'bx || VSSE === 1'bz)
// //$display("Warning: Unknown value for VSSE %b in %m at %0t", VSSE, 0); $display("Warning: Unknown value for VSSE %b in %m at %0t", VSSE, $time);
// `endif `endif
`ifdef POWER_PINS `ifdef POWER_PINS
if (RET1N_ == 1'b0 && VDDPE == 1'b0) begin if (RET1N_ == 1'b0 && VDDPE == 1'b0) begin
`else `else
@@ -1842,12 +1836,12 @@ task dumpaddr;
end end
clk0_int = 1'b0; clk0_int = 1'b0;
ReadA; ReadA;
if (CENA_int === 1'b0) previous_CLKA = `REALTIME; if (CENA_int === 1'b0) previous_CLKA = $realtime;
//#0; #0;
if (((previous_CLKA == previous_CLKB)) && (CENA_int !== 1'b1 && CENB_int !== 1'b1 && DFTRAMBYP_ !== 1'b1) && COLLDISN_int === 1'b1 && is_contention(AA_int, if (((previous_CLKA == previous_CLKB)) && (CENA_int !== 1'b1 && CENB_int !== 1'b1 && DFTRAMBYP_ !== 1'b1) && COLLDISN_int === 1'b1 && is_contention(AA_int,
AB_int, 1'b1, 1'b0)) begin AB_int, 1'b1, 1'b0)) begin
if((|WENB_int) == 1'b1) begin if((|WENB_int) == 1'b1) begin
//$display("%s contention: write B partially, read A partially in %m at %0t",ASSERT_PREFIX, 0); $display("%s contention: write B partially, read A partially in %m at %0t",ASSERT_PREFIX, $time);
ROW_CC = 1; ROW_CC = 1;
COL_CC = 1; COL_CC = 1;
READ_WRITE = 1; READ_WRITE = 1;
@@ -1877,12 +1871,12 @@ task dumpaddr;
WENB_int[8], WENB_int[7], WENB_int[6], WENB_int[5], WENB_int[4], WENB_int[3], WENB_int[8], WENB_int[7], WENB_int[6], WENB_int[5], WENB_int[4], WENB_int[3],
WENB_int[2], WENB_int[1], WENB_int[0]}; WENB_int[2], WENB_int[1], WENB_int[0]};
mem_path = (partial_mask & {128{1'bx}}) | (~partial_mask & mem_path); mem_path = (partial_mask & {128{1'bx}}) | (~partial_mask & mem_path);
//#0; #0;
QA_update = 1'b0; QA_update = 1'b0;
//#0; #0;
QA_update = 1'b1; QA_update = 1'b1;
end else begin end else begin
//$display("%s contention: write B succeeds, read A fails in %m at %0t",ASSERT_PREFIX, 0); $display("%s contention: write B succeeds, read A fails in %m at %0t",ASSERT_PREFIX, $time);
ROW_CC = 1; ROW_CC = 1;
COL_CC = 1; COL_CC = 1;
READ_WRITE = 1; READ_WRITE = 1;
@@ -1890,30 +1884,30 @@ task dumpaddr;
end end
end else if (((previous_CLKA == previous_CLKB)) && (CENA_int !== 1'b1 && CENB_int !== 1'b1 && DFTRAMBYP_ !== 1'b1) && COLLDISN_int === 1'b1 && row_contention(AA_int, end else if (((previous_CLKA == previous_CLKB)) && (CENA_int !== 1'b1 && CENB_int !== 1'b1 && DFTRAMBYP_ !== 1'b1) && COLLDISN_int === 1'b1 && row_contention(AA_int,
AB_int, 1'b1, 1'b0)) begin AB_int, 1'b1, 1'b0)) begin
// `ifdef ARM_MESSAGES `ifdef ARM_MESSAGES
// //$display("%s row contention: in %m at %0t",ASSERT_PREFIX, 0); $display("%s row contention: in %m at %0t",ASSERT_PREFIX, $time);
// `endif `endif
ROW_CC = 1; ROW_CC = 1;
// `ifdef ARM_MESSAGES `ifdef ARM_MESSAGES
// //$display("%s contention: write B succeeds, read A succeeds in %m at %0t",ASSERT_PREFIX, 0); $display("%s contention: write B succeeds, read A succeeds in %m at %0t",ASSERT_PREFIX, $time);
// `endif `endif
READ_WRITE = 1; READ_WRITE = 1;
end else if (((previous_CLKA == previous_CLKB)) && (CENA_int !== 1'b1 && CENB_int !== 1'b1 && DFTRAMBYP_ !== 1'b1) && (COLLDISN_int === 1'b0 || COLLDISN_int end else if (((previous_CLKA == previous_CLKB)) && (CENA_int !== 1'b1 && CENB_int !== 1'b1 && DFTRAMBYP_ !== 1'b1) && (COLLDISN_int === 1'b0 || COLLDISN_int
=== 1'bx) && row_contention(AA_int, AB_int, 1'b1, 1'b0)) begin === 1'bx) && row_contention(AA_int, AB_int, 1'b1, 1'b0)) begin
ROW_CC = 1; ROW_CC = 1;
//$display("%s contention: write B fails in %m at %0t",ASSERT_PREFIX, 0); $display("%s contention: write B fails in %m at %0t",ASSERT_PREFIX, $time);
READ_WRITE = 1; READ_WRITE = 1;
DB_int = {128{1'bx}}; DB_int = {128{1'bx}};
WriteB; WriteB;
if (col_contention(AA_int,AB_int)) begin if (col_contention(AA_int,AB_int)) begin
//$display("%s contention: read A fails in %m at %0t",ASSERT_PREFIX, 0); $display("%s contention: read A fails in %m at %0t",ASSERT_PREFIX, $time);
COL_CC = 1; COL_CC = 1;
READ_WRITE = 1; READ_WRITE = 1;
XQA = 1'b1; QA_update = 1'b1; XQA = 1'b1; QA_update = 1'b1;
end else begin end else begin
// `ifdef ARM_MESSAGES `ifdef ARM_MESSAGES
// //$display("%s contention: read A succeeds in %m at %0t",ASSERT_PREFIX, 0); $display("%s contention: read A succeeds in %m at %0t",ASSERT_PREFIX, $time);
// `endif `endif
READ_WRITE = 1; READ_WRITE = 1;
end end
end end
@@ -2150,22 +2144,22 @@ task dumpaddr;
COLLDISN_int = 1'bx; COLLDISN_int = 1'bx;
end end
RET1N_int = RET1N_; RET1N_int = RET1N_;
//#0; #0;
QA_update = 1'b0; QA_update = 1'b0;
DB_sh_update = 1'b0; DB_sh_update = 1'b0;
//#0;//#0; XDB_sh = 1'b0; #0;#0; XDB_sh = 1'b0;
end end
always @ CLKB_ begin always @ CLKB_ begin
// If POWER_PINS is defined at Simulator Command Line, it selects the module definition with Power Ports // If POWER_PINS is defined at Simulator Command Line, it selects the module definition with Power Ports
// `ifdef POWER_PINS `ifdef POWER_PINS
// if (VDDCE === 1'bx || VDDCE === 1'bz) if (VDDCE === 1'bx || VDDCE === 1'bz)
// //$display("Warning: Unknown value for VDDCE %b in %m at %0t", VDDCE, 0); $display("Warning: Unknown value for VDDCE %b in %m at %0t", VDDCE, $time);
// if (VDDPE === 1'bx || VDDPE === 1'bz) if (VDDPE === 1'bx || VDDPE === 1'bz)
// //$display("Warning: Unknown value for VDDPE %b in %m at %0t", VDDPE, 0); $display("Warning: Unknown value for VDDPE %b in %m at %0t", VDDPE, $time);
// if (VSSE === 1'bx || VSSE === 1'bz) if (VSSE === 1'bx || VSSE === 1'bz)
// //$display("Warning: Unknown value for VSSE %b in %m at %0t", VSSE, 0); $display("Warning: Unknown value for VSSE %b in %m at %0t", VSSE, $time);
// `endif `endif
`ifdef POWER_PINS `ifdef POWER_PINS
if (RET1N_ == 1'b0 && VDDPE == 1'b0) begin if (RET1N_ == 1'b0 && VDDPE == 1'b0) begin
`else `else
@@ -2232,12 +2226,12 @@ task dumpaddr;
end else begin end else begin
WriteB; WriteB;
end end
if (CENB_int === 1'b0) previous_CLKB = `REALTIME; if (CENB_int === 1'b0) previous_CLKB = $realtime;
//#0; #0;
if (((previous_CLKA == previous_CLKB)) && COLLDISN_int === 1'b1 && (CENA_int !== 1'b1 && CENB_int !== 1'b1 && DFTRAMBYP_ !== 1'b1) && is_contention(AA_int, if (((previous_CLKA == previous_CLKB)) && COLLDISN_int === 1'b1 && (CENA_int !== 1'b1 && CENB_int !== 1'b1 && DFTRAMBYP_ !== 1'b1) && is_contention(AA_int,
AB_int, 1'b1, 1'b0)) begin AB_int, 1'b1, 1'b0)) begin
if((|WENB_int) == 1'b1) begin if((|WENB_int) == 1'b1) begin
//$display("%s contention: write B partially, read A partially in %m at %0t",ASSERT_PREFIX, 0); $display("%s contention: write B partially, read A partially in %m at %0t",ASSERT_PREFIX, $time);
ROW_CC = 1; ROW_CC = 1;
COL_CC = 1; COL_CC = 1;
READ_WRITE = 1; READ_WRITE = 1;
@@ -2267,12 +2261,12 @@ task dumpaddr;
WENB_int[8], WENB_int[7], WENB_int[6], WENB_int[5], WENB_int[4], WENB_int[3], WENB_int[8], WENB_int[7], WENB_int[6], WENB_int[5], WENB_int[4], WENB_int[3],
WENB_int[2], WENB_int[1], WENB_int[0]}; WENB_int[2], WENB_int[1], WENB_int[0]};
mem_path = (partial_mask & {128{1'bx}}) | (~partial_mask & mem_path); mem_path = (partial_mask & {128{1'bx}}) | (~partial_mask & mem_path);
//#0; #0;
QA_update = 1'b0; QA_update = 1'b0;
//#0; #0;
QA_update = 1'b1; QA_update = 1'b1;
end else begin end else begin
//$display("%s contention: write B succeeds, read A fails in %m at %0t",ASSERT_PREFIX, 0); $display("%s contention: write B succeeds, read A fails in %m at %0t",ASSERT_PREFIX, $time);
ROW_CC = 1; ROW_CC = 1;
COL_CC = 1; COL_CC = 1;
READ_WRITE = 1; READ_WRITE = 1;
@@ -2280,30 +2274,30 @@ task dumpaddr;
end end
end else if (((previous_CLKA == previous_CLKB)) && COLLDISN_int === 1'b1 && (CENA_int !== 1'b1 && CENB_int !== 1'b1 && DFTRAMBYP_ !== 1'b1) && row_contention(AA_int, end else if (((previous_CLKA == previous_CLKB)) && COLLDISN_int === 1'b1 && (CENA_int !== 1'b1 && CENB_int !== 1'b1 && DFTRAMBYP_ !== 1'b1) && row_contention(AA_int,
AB_int, 1'b1, 1'b0)) begin AB_int, 1'b1, 1'b0)) begin
// `ifdef ARM_MESSAGES `ifdef ARM_MESSAGES
// //$display("%s row contention: in %m at %0t",ASSERT_PREFIX, 0); $display("%s row contention: in %m at %0t",ASSERT_PREFIX, $time);
// `endif `endif
ROW_CC = 1; ROW_CC = 1;
// `ifdef ARM_MESSAGES `ifdef ARM_MESSAGES
// //$display("%s contention: write B succeeds, read A succeeds in %m at %0t",ASSERT_PREFIX, 0); $display("%s contention: write B succeeds, read A succeeds in %m at %0t",ASSERT_PREFIX, $time);
// `endif `endif
READ_WRITE = 1; READ_WRITE = 1;
end else if (((previous_CLKA == previous_CLKB)) && (CENA_int !== 1'b1 && CENB_int !== 1'b1 && DFTRAMBYP_ !== 1'b1) && (COLLDISN_int === 1'b0 || COLLDISN_int end else if (((previous_CLKA == previous_CLKB)) && (CENA_int !== 1'b1 && CENB_int !== 1'b1 && DFTRAMBYP_ !== 1'b1) && (COLLDISN_int === 1'b0 || COLLDISN_int
=== 1'bx) && row_contention(AA_int, AB_int,1'b1, 1'b0)) begin === 1'bx) && row_contention(AA_int, AB_int,1'b1, 1'b0)) begin
ROW_CC = 1; ROW_CC = 1;
//$display("%s contention: write B fails in %m at %0t",ASSERT_PREFIX, 0); $display("%s contention: write B fails in %m at %0t",ASSERT_PREFIX, $time);
READ_WRITE = 1; READ_WRITE = 1;
DB_int = {128{1'bx}}; DB_int = {128{1'bx}};
WriteB; WriteB;
if (col_contention(AA_int,AB_int)) begin if (col_contention(AA_int,AB_int)) begin
//$display("%s contention: read A fails in %m at %0t",ASSERT_PREFIX, 0); $display("%s contention: read A fails in %m at %0t",ASSERT_PREFIX, $time);
COL_CC = 1; COL_CC = 1;
READ_WRITE = 1; READ_WRITE = 1;
XQA = 1'b1; QA_update = 1'b1; XQA = 1'b1; QA_update = 1'b1;
end else begin end else begin
// `ifdef ARM_MESSAGES `ifdef ARM_MESSAGES
// //$display("%s contention: read A succeeds in %m at %0t",ASSERT_PREFIX, 0); $display("%s contention: read A succeeds in %m at %0t",ASSERT_PREFIX, $time);
// `endif `endif
READ_WRITE = 1; READ_WRITE = 1;
end end
end end
@@ -2450,16 +2444,16 @@ task dumpaddr;
// If POWER_PINS is defined at Simulator Command Line, it selects the module definition with Power Ports // If POWER_PINS is defined at Simulator Command Line, it selects the module definition with Power Ports
// `ifdef POWER_PINS `ifdef POWER_PINS
// always @ (VDDCE or VDDPE or VSSE) begin always @ (VDDCE or VDDPE or VSSE) begin
// if (VDDCE === 1'bx || VDDCE === 1'bz) if (VDDCE === 1'bx || VDDCE === 1'bz)
// //$display("Warning: Unknown value for VDDCE %b in %m at %0t", VDDCE, 0); $display("Warning: Unknown value for VDDCE %b in %m at %0t", VDDCE, $time);
// if (VDDPE === 1'bx || VDDPE === 1'bz) if (VDDPE === 1'bx || VDDPE === 1'bz)
// //$display("Warning: Unknown value for VDDPE %b in %m at %0t", VDDPE, 0); $display("Warning: Unknown value for VDDPE %b in %m at %0t", VDDPE, $time);
// if (VSSE === 1'bx || VSSE === 1'bz) if (VSSE === 1'bx || VSSE === 1'bz)
// //$display("Warning: Unknown value for VSSE %b in %m at %0t", VSSE, 0); $display("Warning: Unknown value for VSSE %b in %m at %0t", VSSE, $time);
// end end
// `endif `endif
function row_contention; function row_contention;
input [4:0] aa; input [4:0] aa;
@@ -3618,23 +3612,23 @@ module rf2_32x128_wm1 (CENYA, AYA, CENYB, WENYB, AYB, QA, SOA, SOB, CLKA, CENA,
`ifdef INITIALIZE_MEMORY `ifdef INITIALIZE_MEMORY
integer i; integer i;
initial begin initial begin
//#0; #0;
for (i = 0; i < MEM_HEIGHT; i = i + 1) for (i = 0; i < MEM_HEIGHT; i = i + 1)
mem[i] = {MEM_WIDTH{1'b0}}; mem[i] = {MEM_WIDTH{1'b0}};
end end
`endif `endif
// always @ (EMAA_) begin always @ (EMAA_) begin
// if(EMAA_ < 3) if(EMAA_ < 3)
// //$display("Warning: Set Value for EMAA doesn't match Default value 3 in %m at %0t", 0); $display("Warning: Set Value for EMAA doesn't match Default value 3 in %m at %0t", $time);
// end end
// always @ (EMASA_) begin always @ (EMASA_) begin
// if(EMASA_ < 0) if(EMASA_ < 0)
// //$display("Warning: Set Value for EMASA doesn't match Default value 0 in %m at %0t", 0); $display("Warning: Set Value for EMASA doesn't match Default value 0 in %m at %0t", $time);
// end end
// always @ (EMAB_) begin always @ (EMAB_) begin
// if(EMAB_ < 3) if(EMAB_ < 3)
// //$display("Warning: Set Value for EMAB doesn't match Default value 3 in %m at %0t", 0); $display("Warning: Set Value for EMAB doesn't match Default value 3 in %m at %0t", $time);
// end end
task failedWrite; task failedWrite;
input port_f; input port_f;
@@ -4147,24 +4141,24 @@ task dumpaddr;
end end
end end
// `ifdef POWER_PINS `ifdef POWER_PINS
// always @ (VDDCE) begin always @ (VDDCE) begin
// if (VDDCE != 1'b1) begin if (VDDCE != 1'b1) begin
// if (VDDPE == 1'b1) begin if (VDDPE == 1'b1) begin
// //$display("VDDCE should be powered down after VDDPE, Illegal power down sequencing in %m at %0t", 0); $display("VDDCE should be powered down after VDDPE, Illegal power down sequencing in %m at %0t", $time);
// end end
// //$display("In PowerDown Mode in %m at %0t", 0); $display("In PowerDown Mode in %m at %0t", $time);
// failedWrite(0); failedWrite(0);
// end end
// if (VDDCE == 1'b1) begin if (VDDCE == 1'b1) begin
// if (VDDPE == 1'b1) begin if (VDDPE == 1'b1) begin
// //$display("VDDPE should be powered up after VDDCE in %m at %0t", 0); $display("VDDPE should be powered up after VDDCE in %m at %0t", $time);
// //$display("Illegal power up sequencing in %m at %0t", 0); $display("Illegal power up sequencing in %m at %0t", $time);
// end end
// failedWrite(0); failedWrite(0);
// end end
// end end
// `endif `endif
`ifdef POWER_PINS `ifdef POWER_PINS
always @ (RET1N_ or VDDPE or VDDCE) begin always @ (RET1N_ or VDDPE or VDDCE) begin
`else `else
@@ -4241,13 +4235,13 @@ task dumpaddr;
COLLDISN_int = 1'bx; COLLDISN_int = 1'bx;
end end
RET1N_int = RET1N_; RET1N_int = RET1N_;
//#0; #0;
QA_update = 1'b0; QA_update = 1'b0;
//#0;//#0; XQA = 1'b0; #0;#0; XQA = 1'b0;
end end
always @ (CLKB_ or DFTRAMBYP_p2) begin always @ (CLKB_ or DFTRAMBYP_p2) begin
//#0; #0;
if(CLKB_ == 1'b1 && (DFTRAMBYP_int === 1'b1 || CENB_int != 1'b1)) begin if(CLKB_ == 1'b1 && (DFTRAMBYP_int === 1'b1 || CENB_int != 1'b1)) begin
if (RET1N_ == 1'b1) begin if (RET1N_ == 1'b1) begin
DB_sh_update = 1'b1; DB_sh_update = 1'b1;
@@ -4257,14 +4251,14 @@ task dumpaddr;
always @ CLKA_ begin always @ CLKA_ begin
// If POWER_PINS is defined at Simulator Command Line, it selects the module definition with Power Ports // If POWER_PINS is defined at Simulator Command Line, it selects the module definition with Power Ports
// `ifdef POWER_PINS `ifdef POWER_PINS
// if (VDDCE === 1'bx || VDDCE === 1'bz) if (VDDCE === 1'bx || VDDCE === 1'bz)
// //$display("Warning: Unknown value for VDDCE %b in %m at %0t", VDDCE, 0); $display("Warning: Unknown value for VDDCE %b in %m at %0t", VDDCE, $time);
// if (VDDPE === 1'bx || VDDPE === 1'bz) if (VDDPE === 1'bx || VDDPE === 1'bz)
// //$display("Warning: Unknown value for VDDPE %b in %m at %0t", VDDPE, 0); $display("Warning: Unknown value for VDDPE %b in %m at %0t", VDDPE, $time);
// if (VSSE === 1'bx || VSSE === 1'bz) if (VSSE === 1'bx || VSSE === 1'bz)
// //$display("Warning: Unknown value for VSSE %b in %m at %0t", VSSE, 0); $display("Warning: Unknown value for VSSE %b in %m at %0t", VSSE, $time);
// `endif `endif
`ifdef POWER_PINS `ifdef POWER_PINS
if (RET1N_ == 1'b0 && VDDPE == 1'b0) begin if (RET1N_ == 1'b0 && VDDPE == 1'b0) begin
`else `else
@@ -4329,12 +4323,12 @@ task dumpaddr;
end end
clk0_int = 1'b0; clk0_int = 1'b0;
ReadA; ReadA;
if (CENA_int === 1'b0) previous_CLKA = `REALTIME; if (CENA_int === 1'b0) previous_CLKA = $realtime;
//#0; #0;
if (((previous_CLKA == previous_CLKB)) && (CENA_int !== 1'b1 && CENB_int !== 1'b1 && DFTRAMBYP_ !== 1'b1) && COLLDISN_int === 1'b1 && is_contention(AA_int, if (((previous_CLKA == previous_CLKB)) && (CENA_int !== 1'b1 && CENB_int !== 1'b1 && DFTRAMBYP_ !== 1'b1) && COLLDISN_int === 1'b1 && is_contention(AA_int,
AB_int, 1'b1, 1'b0)) begin AB_int, 1'b1, 1'b0)) begin
if((|WENB_int) == 1'b1) begin if((|WENB_int) == 1'b1) begin
//$display("%s contention: write B partially, read A partially in %m at %0t",ASSERT_PREFIX, 0); $display("%s contention: write B partially, read A partially in %m at %0t",ASSERT_PREFIX, $time);
ROW_CC = 1; ROW_CC = 1;
COL_CC = 1; COL_CC = 1;
READ_WRITE = 1; READ_WRITE = 1;
@@ -4364,12 +4358,12 @@ task dumpaddr;
WENB_int[8], WENB_int[7], WENB_int[6], WENB_int[5], WENB_int[4], WENB_int[3], WENB_int[8], WENB_int[7], WENB_int[6], WENB_int[5], WENB_int[4], WENB_int[3],
WENB_int[2], WENB_int[1], WENB_int[0]}; WENB_int[2], WENB_int[1], WENB_int[0]};
mem_path = (partial_mask & {128{1'bx}}) | (~partial_mask & mem_path); mem_path = (partial_mask & {128{1'bx}}) | (~partial_mask & mem_path);
//#0; #0;
QA_update = 1'b0; QA_update = 1'b0;
//#0; #0;
QA_update = 1'b1; QA_update = 1'b1;
end else begin end else begin
//$display("%s contention: write B succeeds, read A fails in %m at %0t",ASSERT_PREFIX, 0); $display("%s contention: write B succeeds, read A fails in %m at %0t",ASSERT_PREFIX, $time);
ROW_CC = 1; ROW_CC = 1;
COL_CC = 1; COL_CC = 1;
READ_WRITE = 1; READ_WRITE = 1;
@@ -4377,30 +4371,30 @@ task dumpaddr;
end end
end else if (((previous_CLKA == previous_CLKB)) && (CENA_int !== 1'b1 && CENB_int !== 1'b1 && DFTRAMBYP_ !== 1'b1) && COLLDISN_int === 1'b1 && row_contention(AA_int, end else if (((previous_CLKA == previous_CLKB)) && (CENA_int !== 1'b1 && CENB_int !== 1'b1 && DFTRAMBYP_ !== 1'b1) && COLLDISN_int === 1'b1 && row_contention(AA_int,
AB_int, 1'b1, 1'b0)) begin AB_int, 1'b1, 1'b0)) begin
// `ifdef ARM_MESSAGES `ifdef ARM_MESSAGES
// //$display("%s row contention: in %m at %0t",ASSERT_PREFIX, 0); $display("%s row contention: in %m at %0t",ASSERT_PREFIX, $time);
// `endif `endif
ROW_CC = 1; ROW_CC = 1;
// `ifdef ARM_MESSAGES `ifdef ARM_MESSAGES
// //$display("%s contention: write B succeeds, read A succeeds in %m at %0t",ASSERT_PREFIX, 0); $display("%s contention: write B succeeds, read A succeeds in %m at %0t",ASSERT_PREFIX, $time);
// `endif `endif
READ_WRITE = 1; READ_WRITE = 1;
end else if (((previous_CLKA == previous_CLKB)) && (CENA_int !== 1'b1 && CENB_int !== 1'b1 && DFTRAMBYP_ !== 1'b1) && (COLLDISN_int === 1'b0 || COLLDISN_int end else if (((previous_CLKA == previous_CLKB)) && (CENA_int !== 1'b1 && CENB_int !== 1'b1 && DFTRAMBYP_ !== 1'b1) && (COLLDISN_int === 1'b0 || COLLDISN_int
=== 1'bx) && row_contention(AA_int, AB_int, 1'b1, 1'b0)) begin === 1'bx) && row_contention(AA_int, AB_int, 1'b1, 1'b0)) begin
ROW_CC = 1; ROW_CC = 1;
//$display("%s contention: write B fails in %m at %0t",ASSERT_PREFIX, 0); $display("%s contention: write B fails in %m at %0t",ASSERT_PREFIX, $time);
READ_WRITE = 1; READ_WRITE = 1;
DB_int = {128{1'bx}}; DB_int = {128{1'bx}};
WriteB; WriteB;
if (col_contention(AA_int,AB_int)) begin if (col_contention(AA_int,AB_int)) begin
//$display("%s contention: read A fails in %m at %0t",ASSERT_PREFIX, 0); $display("%s contention: read A fails in %m at %0t",ASSERT_PREFIX, $time);
COL_CC = 1; COL_CC = 1;
READ_WRITE = 1; READ_WRITE = 1;
XQA = 1'b1; QA_update = 1'b1; XQA = 1'b1; QA_update = 1'b1;
end else begin end else begin
// `ifdef ARM_MESSAGES `ifdef ARM_MESSAGES
// //$display("%s contention: read A succeeds in %m at %0t",ASSERT_PREFIX, 0); $display("%s contention: read A succeeds in %m at %0t",ASSERT_PREFIX, $time);
// `endif `endif
READ_WRITE = 1; READ_WRITE = 1;
end end
end end
@@ -4419,7 +4413,7 @@ task dumpaddr;
initial cont_flag0_int = 1'b0; initial cont_flag0_int = 1'b0;
always @ globalNotifier0 begin always @ globalNotifier0 begin
if (`REALTIME == 0) begin if ($realtime == 0) begin
end else if ((EMAA_int[0] === 1'bx & DFTRAMBYP_int === 1'b1) || (EMAA_int[1] === 1'bx & DFTRAMBYP_int === 1'b1) || end else if ((EMAA_int[0] === 1'bx & DFTRAMBYP_int === 1'b1) || (EMAA_int[1] === 1'bx & DFTRAMBYP_int === 1'b1) ||
(EMAA_int[2] === 1'bx & DFTRAMBYP_int === 1'b1) || (EMASA_int === 1'bx & DFTRAMBYP_int === 1'b1) (EMAA_int[2] === 1'bx & DFTRAMBYP_int === 1'b1) || (EMASA_int === 1'bx & DFTRAMBYP_int === 1'b1)
) begin ) begin
@@ -4442,7 +4436,7 @@ task dumpaddr;
AB_int, 1'b1, 1'b0)) begin AB_int, 1'b1, 1'b0)) begin
cont_flag0_int = 1'b0; cont_flag0_int = 1'b0;
if((|WENB_int) == 1'b1) begin if((|WENB_int) == 1'b1) begin
//$display("%s contention: write B partially, read A partially in %m at %0t",ASSERT_PREFIX, 0); $display("%s contention: write B partially, read A partially in %m at %0t",ASSERT_PREFIX, $time);
ROW_CC = 1; ROW_CC = 1;
COL_CC = 1; COL_CC = 1;
READ_WRITE = 1; READ_WRITE = 1;
@@ -4471,12 +4465,12 @@ task dumpaddr;
WENB_int[8], WENB_int[7], WENB_int[6], WENB_int[5], WENB_int[4], WENB_int[3], WENB_int[8], WENB_int[7], WENB_int[6], WENB_int[5], WENB_int[4], WENB_int[3],
WENB_int[2], WENB_int[1], WENB_int[0]}; WENB_int[2], WENB_int[1], WENB_int[0]};
mem_path = (partial_mask & {128{1'bx}}) | (~partial_mask & mem_path); mem_path = (partial_mask & {128{1'bx}}) | (~partial_mask & mem_path);
//#0; #0;
QA_update = 1'b0; QA_update = 1'b0;
//#0; #0;
QA_update = 1'b1; QA_update = 1'b1;
end else begin end else begin
//$display("%s contention: write B succeeds, read A fails in %m at %0t",ASSERT_PREFIX, 0); $display("%s contention: write B succeeds, read A fails in %m at %0t",ASSERT_PREFIX, $time);
ROW_CC = 1; ROW_CC = 1;
COL_CC = 1; COL_CC = 1;
READ_WRITE = 1; READ_WRITE = 1;
@@ -4486,26 +4480,26 @@ task dumpaddr;
1'bx) && row_contention(AA_int, AB_int,1'b1, 1'b0)) begin 1'bx) && row_contention(AA_int, AB_int,1'b1, 1'b0)) begin
cont_flag0_int = 1'b0; cont_flag0_int = 1'b0;
ROW_CC = 1; ROW_CC = 1;
//$display("%s contention: write B fails in %m at %0t",ASSERT_PREFIX, 0); $display("%s contention: write B fails in %m at %0t",ASSERT_PREFIX, $time);
READ_WRITE = 1; READ_WRITE = 1;
DB_int = {128{1'bx}}; DB_int = {128{1'bx}};
WriteB; WriteB;
if (col_contention(AA_int,AB_int)) begin if (col_contention(AA_int,AB_int)) begin
//$display("%s contention: read A fails in %m at %0t",ASSERT_PREFIX, 0); $display("%s contention: read A fails in %m at %0t",ASSERT_PREFIX, $time);
COL_CC = 1; COL_CC = 1;
READ_WRITE = 1; READ_WRITE = 1;
XQA = 1'b1; QA_update = 1'b1; XQA = 1'b1; QA_update = 1'b1;
end else begin end else begin
// `ifdef ARM_MESSAGES `ifdef ARM_MESSAGES
// //$display("%s contention: read A succeeds in %m at %0t",ASSERT_PREFIX, 0); $display("%s contention: read A succeeds in %m at %0t",ASSERT_PREFIX, $time);
// `endif `endif
READ_WRITE = 1; READ_WRITE = 1;
end end
end else begin end else begin
//#0;//#0; #0;#0;
ReadA; ReadA;
end end
//#0; #0;
QA_update = 1'b0; QA_update = 1'b0;
globalNotifier0 = 1'b0; globalNotifier0 = 1'b0;
end end
@@ -4733,22 +4727,22 @@ task dumpaddr;
COLLDISN_int = 1'bx; COLLDISN_int = 1'bx;
end end
RET1N_int = RET1N_; RET1N_int = RET1N_;
//#0; #0;
QA_update = 1'b0; QA_update = 1'b0;
DB_sh_update = 1'b0; DB_sh_update = 1'b0;
//#0;//#0; XDB_sh = 1'b0; #0;#0; XDB_sh = 1'b0;
end end
always @ CLKB_ begin always @ CLKB_ begin
// If POWER_PINS is defined at Simulator Command Line, it selects the module definition with Power Ports // If POWER_PINS is defined at Simulator Command Line, it selects the module definition with Power Ports
// `ifdef POWER_PINS `ifdef POWER_PINS
// if (VDDCE === 1'bx || VDDCE === 1'bz) if (VDDCE === 1'bx || VDDCE === 1'bz)
// //$display("Warning: Unknown value for VDDCE %b in %m at %0t", VDDCE, 0); $display("Warning: Unknown value for VDDCE %b in %m at %0t", VDDCE, $time);
// if (VDDPE === 1'bx || VDDPE === 1'bz) if (VDDPE === 1'bx || VDDPE === 1'bz)
// //$display("Warning: Unknown value for VDDPE %b in %m at %0t", VDDPE, 0); $display("Warning: Unknown value for VDDPE %b in %m at %0t", VDDPE, $time);
// if (VSSE === 1'bx || VSSE === 1'bz) if (VSSE === 1'bx || VSSE === 1'bz)
// //$display("Warning: Unknown value for VSSE %b in %m at %0t", VSSE, 0); $display("Warning: Unknown value for VSSE %b in %m at %0t", VSSE, $time);
// `endif `endif
`ifdef POWER_PINS `ifdef POWER_PINS
if (RET1N_ == 1'b0 && VDDPE == 1'b0) begin if (RET1N_ == 1'b0 && VDDPE == 1'b0) begin
`else `else
@@ -4815,12 +4809,12 @@ task dumpaddr;
end else begin end else begin
WriteB; WriteB;
end end
if (CENB_int === 1'b0) previous_CLKB = `REALTIME; if (CENB_int === 1'b0) previous_CLKB = $realtime;
//#0; #0;
if (((previous_CLKA == previous_CLKB)) && COLLDISN_int === 1'b1 && (CENA_int !== 1'b1 && CENB_int !== 1'b1 && DFTRAMBYP_ !== 1'b1) && is_contention(AA_int, if (((previous_CLKA == previous_CLKB)) && COLLDISN_int === 1'b1 && (CENA_int !== 1'b1 && CENB_int !== 1'b1 && DFTRAMBYP_ !== 1'b1) && is_contention(AA_int,
AB_int, 1'b1, 1'b0)) begin AB_int, 1'b1, 1'b0)) begin
if((|WENB_int) == 1'b1) begin if((|WENB_int) == 1'b1) begin
//$display("%s contention: write B partially, read A partially in %m at %0t",ASSERT_PREFIX, 0); $display("%s contention: write B partially, read A partially in %m at %0t",ASSERT_PREFIX, $time);
ROW_CC = 1; ROW_CC = 1;
COL_CC = 1; COL_CC = 1;
READ_WRITE = 1; READ_WRITE = 1;
@@ -4850,12 +4844,12 @@ task dumpaddr;
WENB_int[8], WENB_int[7], WENB_int[6], WENB_int[5], WENB_int[4], WENB_int[3], WENB_int[8], WENB_int[7], WENB_int[6], WENB_int[5], WENB_int[4], WENB_int[3],
WENB_int[2], WENB_int[1], WENB_int[0]}; WENB_int[2], WENB_int[1], WENB_int[0]};
mem_path = (partial_mask & {128{1'bx}}) | (~partial_mask & mem_path); mem_path = (partial_mask & {128{1'bx}}) | (~partial_mask & mem_path);
//#0; #0;
QA_update = 1'b0; QA_update = 1'b0;
//#0; #0;
QA_update = 1'b1; QA_update = 1'b1;
end else begin end else begin
//$display("%s contention: write B succeeds, read A fails in %m at %0t",ASSERT_PREFIX, 0); $display("%s contention: write B succeeds, read A fails in %m at %0t",ASSERT_PREFIX, $time);
ROW_CC = 1; ROW_CC = 1;
COL_CC = 1; COL_CC = 1;
READ_WRITE = 1; READ_WRITE = 1;
@@ -4863,30 +4857,30 @@ task dumpaddr;
end end
end else if (((previous_CLKA == previous_CLKB)) && COLLDISN_int === 1'b1 && (CENA_int !== 1'b1 && CENB_int !== 1'b1 && DFTRAMBYP_ !== 1'b1) && row_contention(AA_int, end else if (((previous_CLKA == previous_CLKB)) && COLLDISN_int === 1'b1 && (CENA_int !== 1'b1 && CENB_int !== 1'b1 && DFTRAMBYP_ !== 1'b1) && row_contention(AA_int,
AB_int, 1'b1, 1'b0)) begin AB_int, 1'b1, 1'b0)) begin
// `ifdef ARM_MESSAGES `ifdef ARM_MESSAGES
// //$display("%s row contention: in %m at %0t",ASSERT_PREFIX, 0); $display("%s row contention: in %m at %0t",ASSERT_PREFIX, $time);
// `endif `endif
ROW_CC = 1; ROW_CC = 1;
// `ifdef ARM_MESSAGES `ifdef ARM_MESSAGES
// //$display("%s contention: write B succeeds, read A succeeds in %m at %0t",ASSERT_PREFIX, 0); $display("%s contention: write B succeeds, read A succeeds in %m at %0t",ASSERT_PREFIX, $time);
// `endif `endif
READ_WRITE = 1; READ_WRITE = 1;
end else if (((previous_CLKA == previous_CLKB)) && (CENA_int !== 1'b1 && CENB_int !== 1'b1 && DFTRAMBYP_ !== 1'b1) && (COLLDISN_int === 1'b0 || COLLDISN_int end else if (((previous_CLKA == previous_CLKB)) && (CENA_int !== 1'b1 && CENB_int !== 1'b1 && DFTRAMBYP_ !== 1'b1) && (COLLDISN_int === 1'b0 || COLLDISN_int
=== 1'bx) && row_contention(AA_int, AB_int,1'b1, 1'b0)) begin === 1'bx) && row_contention(AA_int, AB_int,1'b1, 1'b0)) begin
ROW_CC = 1; ROW_CC = 1;
//$display("%s contention: write B fails in %m at %0t",ASSERT_PREFIX, 0); $display("%s contention: write B fails in %m at %0t",ASSERT_PREFIX, $time);
READ_WRITE = 1; READ_WRITE = 1;
DB_int = {128{1'bx}}; DB_int = {128{1'bx}};
WriteB; WriteB;
if (col_contention(AA_int,AB_int)) begin if (col_contention(AA_int,AB_int)) begin
//$display("%s contention: read A fails in %m at %0t",ASSERT_PREFIX, 0); $display("%s contention: read A fails in %m at %0t",ASSERT_PREFIX, $time);
COL_CC = 1; COL_CC = 1;
READ_WRITE = 1; READ_WRITE = 1;
XQA = 1'b1; QA_update = 1'b1; XQA = 1'b1; QA_update = 1'b1;
end else begin end else begin
// `ifdef ARM_MESSAGES `ifdef ARM_MESSAGES
// //$display("%s contention: read A succeeds in %m at %0t",ASSERT_PREFIX, 0); $display("%s contention: read A succeeds in %m at %0t",ASSERT_PREFIX, $time);
// `endif `endif
READ_WRITE = 1; READ_WRITE = 1;
end end
end end
@@ -4904,7 +4898,7 @@ task dumpaddr;
initial cont_flag1_int = 1'b0; initial cont_flag1_int = 1'b0;
always @ globalNotifier1 begin always @ globalNotifier1 begin
if (`REALTIME == 0) begin if ($realtime == 0) begin
end else if ((EMAB_int[0] === 1'bx & DFTRAMBYP_int === 1'b1) || (EMAB_int[1] === 1'bx & DFTRAMBYP_int === 1'b1) || end else if ((EMAB_int[0] === 1'bx & DFTRAMBYP_int === 1'b1) || (EMAB_int[1] === 1'bx & DFTRAMBYP_int === 1'b1) ||
(EMAB_int[2] === 1'bx & DFTRAMBYP_int === 1'b1)) begin (EMAB_int[2] === 1'bx & DFTRAMBYP_int === 1'b1)) begin
XDB_sh = 1'b1; XDB_sh = 1'b1;
@@ -4930,7 +4924,7 @@ task dumpaddr;
AB_int, 1'b1, 1'b0)) begin AB_int, 1'b1, 1'b0)) begin
cont_flag1_int = 1'b0; cont_flag1_int = 1'b0;
if((|WENB_int) == 1'b1) begin if((|WENB_int) == 1'b1) begin
//$display("%s contention: write B partially, read A partially in %m at %0t",ASSERT_PREFIX, 0); $display("%s contention: write B partially, read A partially in %m at %0t",ASSERT_PREFIX, $time);
ROW_CC = 1; ROW_CC = 1;
COL_CC = 1; COL_CC = 1;
READ_WRITE = 1; READ_WRITE = 1;
@@ -4959,12 +4953,12 @@ task dumpaddr;
WENB_int[8], WENB_int[7], WENB_int[6], WENB_int[5], WENB_int[4], WENB_int[3], WENB_int[8], WENB_int[7], WENB_int[6], WENB_int[5], WENB_int[4], WENB_int[3],
WENB_int[2], WENB_int[1], WENB_int[0]}; WENB_int[2], WENB_int[1], WENB_int[0]};
mem_path = (partial_mask & {128{1'bx}}) | (~partial_mask & mem_path); mem_path = (partial_mask & {128{1'bx}}) | (~partial_mask & mem_path);
//#0; #0;
QA_update = 1'b0; QA_update = 1'b0;
//#0; #0;
QA_update = 1'b1; QA_update = 1'b1;
end else begin end else begin
//$display("%s contention: write B succeeds, read A fails in %m at %0t",ASSERT_PREFIX, 0); $display("%s contention: write B succeeds, read A fails in %m at %0t",ASSERT_PREFIX, $time);
ROW_CC = 1; ROW_CC = 1;
COL_CC = 1; COL_CC = 1;
READ_WRITE = 1; READ_WRITE = 1;
@@ -4974,26 +4968,26 @@ task dumpaddr;
1'bx) && row_contention(AA_int, AB_int,1'b1, 1'b0)) begin 1'bx) && row_contention(AA_int, AB_int,1'b1, 1'b0)) begin
cont_flag1_int = 1'b0; cont_flag1_int = 1'b0;
ROW_CC = 1; ROW_CC = 1;
//$display("%s contention: write B fails in %m at %0t",ASSERT_PREFIX, 0); $display("%s contention: write B fails in %m at %0t",ASSERT_PREFIX, $time);
READ_WRITE = 1; READ_WRITE = 1;
DB_int = {128{1'bx}}; DB_int = {128{1'bx}};
WriteB; WriteB;
if (col_contention(AA_int,AB_int)) begin if (col_contention(AA_int,AB_int)) begin
//$display("%s contention: read A fails in %m at %0t",ASSERT_PREFIX, 0); $display("%s contention: read A fails in %m at %0t",ASSERT_PREFIX, $time);
COL_CC = 1; COL_CC = 1;
READ_WRITE = 1; READ_WRITE = 1;
XQA = 1'b1; QA_update = 1'b1; XQA = 1'b1; QA_update = 1'b1;
end else begin end else begin
`ifdef ARM_MESSAGES `ifdef ARM_MESSAGES
//$display("%s contention: read A succeeds in %m at %0t",ASSERT_PREFIX, 0); $display("%s contention: read A succeeds in %m at %0t",ASSERT_PREFIX, $time);
`endif `endif
READ_WRITE = 1; READ_WRITE = 1;
end end
end else begin end else begin
//#0;//#0; #0;#0;
WriteB; WriteB;
end end
//#0; #0;
DB_sh_update = 1'b0; DB_sh_update = 1'b0;
globalNotifier1 = 1'b0; globalNotifier1 = 1'b0;
end end
@@ -5132,16 +5126,16 @@ task dumpaddr;
// If POWER_PINS is defined at Simulator Command Line, it selects the module definition with Power Ports // If POWER_PINS is defined at Simulator Command Line, it selects the module definition with Power Ports
// `ifdef POWER_PINS `ifdef POWER_PINS
// always @ (VDDCE or VDDPE or VSSE) begin always @ (VDDCE or VDDPE or VSSE) begin
// if (VDDCE === 1'bx || VDDCE === 1'bz) if (VDDCE === 1'bx || VDDCE === 1'bz)
// //$display("Warning: Unknown value for VDDCE %b in %m at %0t", VDDCE, 0); $display("Warning: Unknown value for VDDCE %b in %m at %0t", VDDCE, $time);
// if (VDDPE === 1'bx || VDDPE === 1'bz) if (VDDPE === 1'bx || VDDPE === 1'bz)
// //$display("Warning: Unknown value for VDDPE %b in %m at %0t", VDDPE, 0); $display("Warning: Unknown value for VDDPE %b in %m at %0t", VDDPE, $time);
// if (VSSE === 1'bx || VSSE === 1'bz) if (VSSE === 1'bx || VSSE === 1'bz)
// //$display("Warning: Unknown value for VSSE %b in %m at %0t", VSSE, 0); $display("Warning: Unknown value for VSSE %b in %m at %0t", VSSE, $time);
// end end
// `endif `endif
function row_contention; function row_contention;
input [4:0] aa; input [4:0] aa;
@@ -15365,8 +15359,3 @@ begin
Q_out = Q_in; Q_out = Q_in;
end end
endmodule endmodule
/* verilator lint_on UNUSED */

19
models/memory/cln28hpc/rf2_32x128_wm1/testbench.cpp Normal file
View File

@@ -0,0 +1,19 @@
#include "Vrf2_32x128_wm1_rtl.h"
#include "verilated.h"
int main()
{
Vrf2_32x128_wm1_rtl module;
for (int i = 0; i < 10; i++)
{
// module.clk = 0;
module.eval();
// module.clk = 1;
module.eval();
}
return 0;
}