diff --git a/hw/rtl/cache/VX_bank.v b/hw/rtl/cache/VX_bank.v index 1302f5ca..26a32689 100644 --- a/hw/rtl/cache/VX_bank.v +++ b/hw/rtl/cache/VX_bank.v @@ -154,12 +154,12 @@ module VX_bank #( wire [NUM_PORTS-1:0][WORD_SIZE-1:0] byteen_st0, byteen_st1; wire [NUM_PORTS-1:0][`REQS_BITS-1:0] req_tid_st0, req_tid_st1; wire [NUM_PORTS-1:0] pmask_st0, pmask_st1; - wire [`CACHE_LINE_WIDTH-1:0] data_st0, data_st1; + wire [`CACHE_LINE_WIDTH-1:0] wdata_st0, wdata_st1; + wire [`CACHE_LINE_WIDTH-1:0] rdata_st1; wire [CORE_TAG_WIDTH-1:0] tag_st0, tag_st1; wire valid_st0, valid_st1; wire is_fill_st0, is_fill_st1; - wire is_mshr_st0, is_mshr_st1; - wire [`CACHE_LINE_WIDTH-1:0] readdata_st1; + wire is_mshr_st0, is_mshr_st1; wire miss_st0, miss_st1; wire prev_miss_dep_st0, prev_miss_dep_st1; wire force_miss_st0, force_miss_st1; @@ -258,7 +258,7 @@ module VX_bank #( mshr_pop_unqual, drsq_pop_unqual || flush_enable, mshr_pop_unqual ? 1'b0 : creq_rw, - flush_enable ? (`LINE_ADDR_WIDTH'(flush_addr)) : (mshr_pop_unqual ? mshr_addr : (dram_rsp_valid ? dram_rsp_addr_qual : creq_addr)), + mshr_pop_unqual ? mshr_addr : (dram_rsp_valid ? dram_rsp_addr_qual : (flush_enable ? `LINE_ADDR_WIDTH'(flush_addr) : creq_addr)), dram_rsp_valid ? dram_rsp_data : creq_line_data, mshr_pop_unqual ? mshr_wsel : creq_wsel, mshr_pop_unqual ? mshr_byteen : creq_byteen, @@ -267,7 +267,7 @@ module VX_bank #( mshr_pop_unqual ? mshr_tag : creq_tag, mshr_pending_sel }), - .data_out ({valid_st0, is_flush_st0, is_mshr_st0, is_fill_st0, mem_rw_st0, addr_st0, data_st0, wsel_st0, byteen_st0, req_tid_st0, pmask_st0, tag_st0, mshr_pending_st0}) + .data_out ({valid_st0, is_flush_st0, is_mshr_st0, is_fill_st0, mem_rw_st0, addr_st0, wdata_st0, wsel_st0, byteen_st0, req_tid_st0, pmask_st0, tag_st0, mshr_pending_st0}) ); `ifdef DBG_CACHE_REQ_INFO @@ -330,8 +330,8 @@ module VX_bank #( .clk (clk), .reset (reset), .enable (1'b1), - .data_in ({valid_st0, is_mshr_st0, is_fill_st0, writeen_unqual_st0, prev_miss_dep_st0, incoming_fill_st0, miss_st0, force_miss_st0, mem_rw_st0, addr_st0, data_st0, wsel_st0, byteen_st0, req_tid_st0, pmask_st0, tag_st0}), - .data_out ({valid_st1, is_mshr_st1, is_fill_st1, writeen_unqual_st1, prev_miss_dep_st1, incoming_fill_st1, miss_st1, force_miss_st1, mem_rw_st1, addr_st1, data_st1, wsel_st1, byteen_st1, req_tid_st1, pmask_st1, tag_st1}) + .data_in ({valid_st0, is_mshr_st0, is_fill_st0, writeen_unqual_st0, prev_miss_dep_st0, incoming_fill_st0, miss_st0, force_miss_st0, mem_rw_st0, addr_st0, wdata_st0, wsel_st0, byteen_st0, req_tid_st0, pmask_st0, tag_st0}), + .data_out ({valid_st1, is_mshr_st1, is_fill_st1, writeen_unqual_st1, prev_miss_dep_st1, incoming_fill_st1, miss_st1, force_miss_st1, mem_rw_st1, addr_st1, wdata_st1, wsel_st1, byteen_st1, req_tid_st1, pmask_st1, tag_st1}) ); `ifdef DBG_CACHE_REQ_INFO @@ -381,13 +381,13 @@ module VX_bank #( end VX_data_access #( - .BANK_ID (BANK_ID), - .CACHE_ID (CACHE_ID), - .CACHE_SIZE (CACHE_SIZE), - .CACHE_LINE_SIZE (CACHE_LINE_SIZE), - .NUM_BANKS (NUM_BANKS), - .WORD_SIZE (WORD_SIZE), - .WRITE_ENABLE (WRITE_ENABLE) + .BANK_ID (BANK_ID), + .CACHE_ID (CACHE_ID), + .CACHE_SIZE (CACHE_SIZE), + .CACHE_LINE_SIZE(CACHE_LINE_SIZE), + .NUM_BANKS (NUM_BANKS), + .WORD_SIZE (WORD_SIZE), + .WRITE_ENABLE (WRITE_ENABLE) ) data_access ( .clk (clk), .reset (reset), @@ -401,13 +401,13 @@ module VX_bank #( // reading .readen (valid_st1 && !mem_rw_st1 && !is_fill_st1), - .rddata (readdata_st1), + .rddata (rdata_st1), // writing .writeen (valid_st1 && writeen_st1), .is_fill (is_fill_st1), .byteen (line_byteen_st1), - .wrdata (data_st1) + .wrdata (wdata_st1) ); assign mshr_push = valid_st1 && mshr_push_st1; @@ -482,10 +482,10 @@ module VX_bank #( if (`WORD_SELECT_BITS != 0) begin for (genvar p = 0; p < NUM_PORTS; ++p) begin - assign crsq_data[p] = readdata_st1[wsel_st1[p] * `WORD_WIDTH +: `WORD_WIDTH]; + assign crsq_data[p] = rdata_st1[wsel_st1[p] * `WORD_WIDTH +: `WORD_WIDTH]; end end else begin - assign crsq_data = readdata_st1; + assign crsq_data = rdata_st1; end assign crsq_pmask = pmask_st1; @@ -528,7 +528,7 @@ module VX_bank #( assign dreq_byteen = writeback ? line_byteen_st1 : {CACHE_LINE_SIZE{1'b1}}; assign dreq_addr = addr_st1; - assign dreq_data = data_st1; + assign dreq_data = wdata_st1; VX_fifo_queue #( .DATAW (1 + CACHE_LINE_SIZE + `LINE_ADDR_WIDTH + `CACHE_LINE_WIDTH), diff --git a/hw/rtl/cache/VX_data_access.v b/hw/rtl/cache/VX_data_access.v index 881e5018..85767949 100644 --- a/hw/rtl/cache/VX_data_access.v +++ b/hw/rtl/cache/VX_data_access.v @@ -27,7 +27,7 @@ module VX_data_access #( `endif `IGNORE_WARNINGS_BEGIN - input wire[`LINE_ADDR_WIDTH-1:0] addr, + input wire[`LINE_ADDR_WIDTH-1:0] addr, `IGNORE_WARNINGS_END // reading @@ -41,10 +41,13 @@ module VX_data_access #( input wire [`CACHE_LINE_WIDTH-1:0] wrdata ); `UNUSED_VAR (reset) + `UNUSED_VAR (readen) + wire [`LINE_SELECT_BITS-1:0] line_addr; wire [CACHE_LINE_SIZE-1:0] byte_enable; - - wire [`LINE_SELECT_BITS-1:0] line_addr = addr[`LINE_SELECT_BITS-1:0]; + + assign line_addr = addr[`LINE_SELECT_BITS-1:0]; + assign byte_enable = is_fill ? {CACHE_LINE_SIZE{1'b1}} : byteen; VX_sp_ram #( .DATAW(CACHE_LINE_SIZE * 8), @@ -52,7 +55,7 @@ module VX_data_access #( .BYTEENW(CACHE_LINE_SIZE), .RWCHECK(1) ) data_store ( - .clk(clk), + .clk(clk), .addr(line_addr), .wren(writeen), .byteen(byte_enable), @@ -60,10 +63,6 @@ module VX_data_access #( .din(wrdata), .dout(rddata) ); - - assign byte_enable = is_fill ? {CACHE_LINE_SIZE{1'b1}} : byteen; - - `UNUSED_VAR (readen) `ifdef DBG_PRINT_CACHE_DATA always @(posedge clk) begin diff --git a/hw/syn/opae/vortex_afu.json b/hw/syn/opae/vortex_afu.json index 04700701..1f361d1e 100644 --- a/hw/syn/opae/vortex_afu.json +++ b/hw/syn/opae/vortex_afu.json @@ -2,8 +2,8 @@ "version": 1, "afu-image": { "power": 0, - "clock-frequency-high": "auto-200", - "clock-frequency-low": "auto-200", + "clock-frequency-high": "auto-210", + "clock-frequency-low": "auto-210", "cmd-mem-read": 1, "cmd-mem-write": 2, diff --git a/hw/syn/opae/vortex_afu.qsf b/hw/syn/opae/vortex_afu.qsf index bb90d95c..817252b5 100644 --- a/hw/syn/opae/vortex_afu.qsf +++ b/hw/syn/opae/vortex_afu.qsf @@ -12,6 +12,8 @@ set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING ON set_global_assignment -name OPTIMIZATION_TECHNIQUE SPEED set_global_assignment -name OPTIMIZATION_MODE "AGGRESSIVE PERFORMANCE" +set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION ALWAYS +set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 2.0 set_global_assignment -name FITTER_EFFORT "STANDARD FIT" set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS" set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON diff --git a/hw/syn/quartus/project.tcl b/hw/syn/quartus/project.tcl index f8ba436c..f581bf90 100644 --- a/hw/syn/quartus/project.tcl +++ b/hw/syn/quartus/project.tcl @@ -47,6 +47,8 @@ set_global_assignment -name MUX_RESTRUCTURE ON set_global_assignment -name OPTIMIZATION_TECHNIQUE SPEED set_global_assignment -name OPTIMIZATION_MODE "AGGRESSIVE PERFORMANCE" +set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION ALWAYS +set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 2.0 set_global_assignment -name FITTER_EFFORT "STANDARD FIT" set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS" set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON