minor update

hw/syn/quartus/top/Makefile

@@ -1,6 +1,6 @@
-PROJECT = Vortex_Socket
-TOP_LEVEL_ENTITY = Vortex_Socket
-SRC_FILE = Vortex_Socket.v
+PROJECT = vortex_afu
+TOP_LEVEL_ENTITY = vortex_afu
+SRC_FILE = vortex_afu.sv
 PROJECT_FILES = $(PROJECT).qpf $(PROJECT).qsf
 
 # Part, Family
@@ -49,7 +49,7 @@ smart.log: $(PROJECT_FILES)
 
 # Project initialization
 $(PROJECT_FILES):
-	quartus_sh -t project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src $(SRC_FILE) -sdc project.sdc -inc "../../../rtl;../../../rtl/libs;../../../rtl/interfaces;../../../rtl/pipe_regs;../../../rtl/cache"
+	quartus_sh -t project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src $(SRC_FILE) -sdc project.sdc -inc "../../../rtl;../../../rtl/libs;../../../rtl/interfaces;../../../rtl/pipe_regs;../../../rtl/cache;../../../opae"
 	
 syn.chg:
 	$(STAMP) syn.chg

hw/syn/quartus/vortex/Makefile

@@ -1,6 +1,6 @@
-PROJECT = Vortex
-TOP_LEVEL_ENTITY = Vortex
-SRC_FILE = Vortex.v
+PROJECT = Vortex_Socket
+TOP_LEVEL_ENTITY = Vortex_Socket
+SRC_FILE = Vortex_Socket.v
 PROJECT_FILES = $(PROJECT).qpf $(PROJECT).qsf
 
 # Part, Family

hw/syn/quartus/vortex/timing.tcl

@@ -1,4 +1,4 @@
-project_open Vortex
+project_open Vortex_Socket
 
 set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
 
@@ -6,7 +6,6 @@ create_timing_netlist
 read_sdc
 update_timing_netlist
 
-
 foreach_in_collection op [get_available_operating_conditions] {
   set_operating_conditions $op