minor update
This commit is contained in:
6
hw/rtl/cache/VX_cache.v
vendored
6
hw/rtl/cache/VX_cache.v
vendored
@@ -125,13 +125,13 @@ module VX_cache #(
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`DEBUG_BLOCK(
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wire[31:0] debug_core_req_use_pc;
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wire[1:0] debug_core_req_wb;
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wire[2:0] debug_core_req_rmask;
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wire[1:0] debug_core_req_wb;
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wire[4:0] debug_core_req_rd;
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wire[`NW_BITS-1:0] debug_core_req_warp_num;
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wire[`LOG2UP(CREQ_SIZE)-1:0] debug_core_req_idx;
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if (WORD_SIZE != `GLOBAL_BLOCK_SIZE) begin
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assign {debug_core_req_use_pc, debug_core_req_wb, debug_core_req_rmask, debug_core_req_rd, debug_core_req_warp_num} = core_req_tag[0];
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assign {debug_core_req_use_pc, debug_core_req_wb, debug_core_req_rd, debug_core_req_warp_num, debug_core_req_idx} = core_req_tag[0];
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end
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)
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wire [NUM_BANKS-1:0][NUM_REQUESTS-1:0] per_bank_valid;
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4
hw/rtl/cache/VX_cache_miss_resrv.v
vendored
4
hw/rtl/cache/VX_cache_miss_resrv.v
vendored
@@ -64,8 +64,10 @@ module VX_cache_miss_resrv #(
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reg [`LOG2UP(MRVQ_SIZE+1)-1:0] size;
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`STATIC_ASSERT(MRVQ_SIZE > 5, "invalid size");
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assign miss_resrv_full = (size == $bits(size)'(MRVQ_SIZE));
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assign miss_resrv_stop = (size > $bits(size)'(MRVQ_SIZE-5));
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assign miss_resrv_stop = (size > $bits(size)'(MRVQ_SIZE-1));
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wire enqueue_possible = !miss_resrv_full;
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wire [`LOG2UP(MRVQ_SIZE)-1:0] enqueue_index = tail_ptr;
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