minor update

hw/rtl/cache/VX_cache.v

@@ -168,8 +168,7 @@ module VX_cache #(
         .NUM_BANKS  (NUM_BANKS)
     ) flush_ctrl (
         .clk       (clk),
-        .reset     (reset),
-        .flush     (flush),        
+        .reset     (reset || flush),
         .addr_out  (flush_addr),
         .valid_out (flush_enable)
     );

hw/rtl/cache/VX_flush_ctrl.v

@@ -9,8 +9,7 @@ module VX_flush_ctrl #(
     parameter NUM_BANKS         = 1
 ) (
     input wire  clk,
-    input wire  reset,
-    input wire  flush,    
+    input wire  reset,    
     output wire [`LINE_SELECT_BITS-1:0] addr_out,
     output wire valid_out
 );
@@ -18,7 +17,7 @@ module VX_flush_ctrl #(
     reg [`LINE_SELECT_BITS-1:0] flush_ctr;
 
     always @(posedge clk) begin
-        if (reset || flush) begin
+        if (reset) begin
             flush_enable <= 1;
             flush_ctr    <= 0;
         end else begin