code refactoring for Vivado compatibility
This commit is contained in:
Blaise Tine
258
hw/rtl/VX_pipeline.sv
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258
hw/rtl/VX_pipeline.sv
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`include "VX_define.vh"
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module VX_pipeline #(
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parameter CORE_ID = 0
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) (
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`SCOPE_IO_VX_pipeline
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// Clock
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input wire clk,
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input wire reset,
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// Dcache core request
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output wire [`NUM_THREADS-1:0] dcache_req_valid,
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output wire [`NUM_THREADS-1:0] dcache_req_rw,
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output wire [`NUM_THREADS-1:0][3:0] dcache_req_byteen,
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output wire [`NUM_THREADS-1:0][29:0] dcache_req_addr,
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output wire [`NUM_THREADS-1:0][31:0] dcache_req_data,
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output wire [`NUM_THREADS-1:0][`DCACHE_CORE_TAG_WIDTH-1:0] dcache_req_tag,
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input wire [`NUM_THREADS-1:0] dcache_req_ready,
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// Dcache core reponse
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input wire dcache_rsp_valid,
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input wire [`NUM_THREADS-1:0] dcache_rsp_tmask,
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input wire [`NUM_THREADS-1:0][31:0] dcache_rsp_data,
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input wire [`DCACHE_CORE_TAG_WIDTH-1:0] dcache_rsp_tag,
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output wire dcache_rsp_ready,
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// Icache core request
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output wire icache_req_valid,
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output wire [29:0] icache_req_addr,
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output wire [`ICACHE_CORE_TAG_WIDTH-1:0] icache_req_tag,
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input wire icache_req_ready,
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// Icache core response
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input wire icache_rsp_valid,
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input wire [31:0] icache_rsp_data,
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input wire [`ICACHE_CORE_TAG_WIDTH-1:0] icache_rsp_tag,
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output wire icache_rsp_ready,
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`ifdef PERF_ENABLE
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VX_perf_memsys_if.slave perf_memsys_if,
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`endif
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// Status
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output wire busy
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);
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//
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// Dcache request
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//
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VX_dcache_req_if #(
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.NUM_REQS (`NUM_THREADS),
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.WORD_SIZE (4),
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.TAG_WIDTH (`DCACHE_CORE_TAG_WIDTH)
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) dcache_req_if();
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assign dcache_req_valid = dcache_req_if.valid;
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assign dcache_req_rw = dcache_req_if.rw;
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assign dcache_req_byteen = dcache_req_if.byteen;
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assign dcache_req_addr = dcache_req_if.addr;
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assign dcache_req_data = dcache_req_if.data;
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assign dcache_req_tag = dcache_req_if.tag;
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assign dcache_req_if.ready = dcache_req_ready;
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//
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// Dcache response
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//
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VX_dcache_rsp_if #(
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.NUM_REQS (`NUM_THREADS),
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.WORD_SIZE (4),
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.TAG_WIDTH (`DCACHE_CORE_TAG_WIDTH)
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) dcache_rsp_if();
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assign dcache_rsp_if.valid = dcache_rsp_valid;
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assign dcache_rsp_if.tmask = dcache_rsp_tmask;
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assign dcache_rsp_if.data = dcache_rsp_data;
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assign dcache_rsp_if.tag = dcache_rsp_tag;
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assign dcache_rsp_ready = dcache_rsp_if.ready;
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//
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// Icache request
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//
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VX_icache_req_if #(
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.WORD_SIZE (4),
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.TAG_WIDTH (`ICACHE_CORE_TAG_WIDTH)
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) icache_req_if();
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assign icache_req_valid = icache_req_if.valid;
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assign icache_req_addr = icache_req_if.addr;
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assign icache_req_tag = icache_req_if.tag;
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assign icache_req_if.ready = icache_req_ready;
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//
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// Icache response
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//
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VX_icache_rsp_if #(
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.WORD_SIZE (4),
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.TAG_WIDTH (`ICACHE_CORE_TAG_WIDTH)
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) icache_rsp_if();
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assign icache_rsp_if.valid = icache_rsp_valid;
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assign icache_rsp_if.data = icache_rsp_data;
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assign icache_rsp_if.tag = icache_rsp_tag;
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assign icache_rsp_ready = icache_rsp_if.ready;
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///////////////////////////////////////////////////////////////////////////
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VX_fetch_to_csr_if fetch_to_csr_if();
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VX_cmt_to_csr_if cmt_to_csr_if();
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VX_decode_if decode_if();
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VX_branch_ctl_if branch_ctl_if();
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VX_warp_ctl_if warp_ctl_if();
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VX_ifetch_rsp_if ifetch_rsp_if();
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VX_alu_req_if alu_req_if();
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VX_lsu_req_if lsu_req_if();
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VX_csr_req_if csr_req_if();
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`ifdef EXT_F_ENABLE
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VX_fpu_req_if fpu_req_if();
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`endif
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VX_gpu_req_if gpu_req_if();
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VX_writeback_if writeback_if();
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VX_wstall_if wstall_if();
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VX_join_if join_if();
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VX_commit_if alu_commit_if();
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VX_commit_if ld_commit_if();
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VX_commit_if st_commit_if();
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VX_commit_if csr_commit_if();
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`ifdef EXT_F_ENABLE
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VX_commit_if fpu_commit_if();
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`endif
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VX_commit_if gpu_commit_if();
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`ifdef PERF_ENABLE
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VX_perf_pipeline_if perf_pipeline_if();
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`endif
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`RESET_RELAY (fetch_reset);
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`RESET_RELAY (decode_reset);
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`RESET_RELAY (issue_reset);
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`RESET_RELAY (execute_reset);
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`RESET_RELAY (commit_reset);
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VX_fetch #(
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.CORE_ID(CORE_ID)
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) fetch (
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`SCOPE_BIND_VX_pipeline_fetch
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.clk (clk),
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.reset (fetch_reset),
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.icache_req_if (icache_req_if),
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.icache_rsp_if (icache_rsp_if),
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.wstall_if (wstall_if),
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.join_if (join_if),
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.warp_ctl_if (warp_ctl_if),
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.branch_ctl_if (branch_ctl_if),
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.ifetch_rsp_if (ifetch_rsp_if),
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.fetch_to_csr_if(fetch_to_csr_if),
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.busy (busy)
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);
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VX_decode #(
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.CORE_ID(CORE_ID)
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) decode (
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.clk (clk),
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.reset (decode_reset),
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.ifetch_rsp_if (ifetch_rsp_if),
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.decode_if (decode_if),
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.wstall_if (wstall_if),
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.join_if (join_if)
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);
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VX_issue #(
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.CORE_ID(CORE_ID)
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) issue (
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`SCOPE_BIND_VX_pipeline_issue
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.clk (clk),
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.reset (issue_reset),
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`ifdef PERF_ENABLE
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.perf_pipeline_if (perf_pipeline_if),
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`endif
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.decode_if (decode_if),
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.writeback_if (writeback_if),
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.alu_req_if (alu_req_if),
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.lsu_req_if (lsu_req_if),
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.csr_req_if (csr_req_if),
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`ifdef EXT_F_ENABLE
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.fpu_req_if (fpu_req_if),
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`endif
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.gpu_req_if (gpu_req_if)
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);
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VX_execute #(
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.CORE_ID(CORE_ID)
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) execute (
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`SCOPE_BIND_VX_pipeline_execute
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.clk (clk),
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.reset (execute_reset),
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`ifdef PERF_ENABLE
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.perf_memsys_if (perf_memsys_if),
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.perf_pipeline_if (perf_pipeline_if),
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`endif
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.dcache_req_if (dcache_req_if),
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.dcache_rsp_if (dcache_rsp_if),
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.cmt_to_csr_if (cmt_to_csr_if),
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.fetch_to_csr_if(fetch_to_csr_if),
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.alu_req_if (alu_req_if),
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.lsu_req_if (lsu_req_if),
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.csr_req_if (csr_req_if),
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`ifdef EXT_F_ENABLE
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.fpu_req_if (fpu_req_if),
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`endif
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.gpu_req_if (gpu_req_if),
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.warp_ctl_if (warp_ctl_if),
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.branch_ctl_if (branch_ctl_if),
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.alu_commit_if (alu_commit_if),
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.ld_commit_if (ld_commit_if),
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.st_commit_if (st_commit_if),
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.csr_commit_if (csr_commit_if),
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`ifdef EXT_F_ENABLE
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.fpu_commit_if (fpu_commit_if),
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`endif
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.gpu_commit_if (gpu_commit_if),
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.busy (busy)
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);
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VX_commit #(
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.CORE_ID(CORE_ID)
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) commit (
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.clk (clk),
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.reset (commit_reset),
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.alu_commit_if (alu_commit_if),
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.ld_commit_if (ld_commit_if),
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.st_commit_if (st_commit_if),
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.csr_commit_if (csr_commit_if),
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`ifdef EXT_F_ENABLE
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.fpu_commit_if (fpu_commit_if),
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`endif
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.gpu_commit_if (gpu_commit_if),
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.writeback_if (writeback_if),
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.cmt_to_csr_if (cmt_to_csr_if)
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);
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endmodule
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