From 039f5eb733b70dd1c6a305b9e625e5bd4642908a Mon Sep 17 00:00:00 2001 From: Santosh Srivatsan Date: Mon, 13 Dec 2021 20:21:51 -0500 Subject: [PATCH] Moved 64-bit riscv-tests to tests/riscv/isa from tests/riscv/isa64 --- tests/riscv/isa/Makefile | 17 +- tests/riscv/isa/ramulator.ddr4.log | 278 ++++++++++++++++++ tests/riscv/{isa64 => isa}/rv64ud-p-fadd.hex | 0 .../riscv/{isa64 => isa}/rv64ud-p-fclass.hex | 0 tests/riscv/{isa64 => isa}/rv64ud-p-fcmp.hex | 0 tests/riscv/{isa64 => isa}/rv64ud-p-fcvt.hex | 0 .../riscv/{isa64 => isa}/rv64ud-p-fcvt_w.hex | 0 tests/riscv/{isa64 => isa}/rv64ud-p-fdiv.hex | 0 tests/riscv/{isa64 => isa}/rv64ud-p-fmadd.hex | 0 tests/riscv/{isa64 => isa}/rv64ud-p-fmin.hex | 0 tests/riscv/{isa64 => isa}/rv64ud-p-ldst.hex | 0 tests/riscv/{isa64 => isa}/rv64ud-p-move.hex | 0 .../{isa64 => isa}/rv64ud-p-recoding.hex | 0 .../{isa64 => isa}/rv64ud-p-structural.hex | 0 tests/riscv/{isa64 => isa}/rv64uf-p-fadd.hex | 0 .../riscv/{isa64 => isa}/rv64uf-p-fclass.hex | 0 tests/riscv/{isa64 => isa}/rv64uf-p-fcmp.hex | 0 tests/riscv/{isa64 => isa}/rv64uf-p-fcvt.hex | 0 .../riscv/{isa64 => isa}/rv64uf-p-fcvt_w.hex | 0 tests/riscv/{isa64 => isa}/rv64uf-p-fdiv.hex | 0 tests/riscv/{isa64 => isa}/rv64uf-p-fmadd.hex | 0 tests/riscv/{isa64 => isa}/rv64uf-p-fmin.hex | 0 tests/riscv/{isa64 => isa}/rv64uf-p-ldst.hex | 0 tests/riscv/{isa64 => isa}/rv64uf-p-move.hex | 0 .../{isa64 => isa}/rv64uf-p-recoding.hex | 0 tests/riscv/{isa64 => isa}/rv64ui-p-add.hex | 0 tests/riscv/{isa64 => isa}/rv64ui-p-addi.hex | 0 tests/riscv/{isa64 => isa}/rv64ui-p-addiw.hex | 0 tests/riscv/{isa64 => isa}/rv64ui-p-addw.hex | 0 tests/riscv/{isa64 => isa}/rv64ui-p-and.hex | 0 tests/riscv/{isa64 => isa}/rv64ui-p-andi.hex | 0 tests/riscv/{isa64 => isa}/rv64ui-p-auipc.hex | 0 tests/riscv/{isa64 => isa}/rv64ui-p-beq.hex | 0 tests/riscv/{isa64 => isa}/rv64ui-p-bge.hex | 0 tests/riscv/{isa64 => isa}/rv64ui-p-bgeu.hex | 0 tests/riscv/{isa64 => isa}/rv64ui-p-blt.hex | 0 tests/riscv/{isa64 => isa}/rv64ui-p-bltu.hex | 0 tests/riscv/{isa64 => isa}/rv64ui-p-bne.hex | 0 .../riscv/{isa64 => isa}/rv64ui-p-fence_i.hex | 0 tests/riscv/{isa64 => isa}/rv64ui-p-jal.hex | 0 tests/riscv/{isa64 => isa}/rv64ui-p-jalr.hex | 0 tests/riscv/{isa64 => isa}/rv64ui-p-lb.hex | 0 tests/riscv/{isa64 => isa}/rv64ui-p-lbu.hex | 0 tests/riscv/{isa64 => isa}/rv64ui-p-ld.hex | 0 tests/riscv/{isa64 => isa}/rv64ui-p-lh.hex | 0 tests/riscv/{isa64 => isa}/rv64ui-p-lhu.hex | 0 tests/riscv/{isa64 => isa}/rv64ui-p-lui.hex | 0 tests/riscv/{isa64 => isa}/rv64ui-p-lw.hex | 0 tests/riscv/{isa64 => isa}/rv64ui-p-lwu.hex | 0 tests/riscv/{isa64 => isa}/rv64ui-p-or.hex | 0 tests/riscv/{isa64 => isa}/rv64ui-p-ori.hex | 0 tests/riscv/{isa64 => isa}/rv64ui-p-sb.hex | 0 tests/riscv/{isa64 => isa}/rv64ui-p-sd.hex | 0 tests/riscv/{isa64 => isa}/rv64ui-p-sh.hex | 0 .../riscv/{isa64 => isa}/rv64ui-p-simple.hex | 0 tests/riscv/{isa64 => isa}/rv64ui-p-sll.hex | 0 tests/riscv/{isa64 => isa}/rv64ui-p-slli.hex | 0 tests/riscv/{isa64 => isa}/rv64ui-p-slliw.hex | 0 tests/riscv/{isa64 => isa}/rv64ui-p-sllw.hex | 0 tests/riscv/{isa64 => isa}/rv64ui-p-slt.hex | 0 tests/riscv/{isa64 => isa}/rv64ui-p-slti.hex | 0 tests/riscv/{isa64 => isa}/rv64ui-p-sltiu.hex | 0 tests/riscv/{isa64 => isa}/rv64ui-p-sltu.hex | 0 tests/riscv/{isa64 => isa}/rv64ui-p-sra.hex | 0 tests/riscv/{isa64 => isa}/rv64ui-p-srai.hex | 0 tests/riscv/{isa64 => isa}/rv64ui-p-sraiw.hex | 0 tests/riscv/{isa64 => isa}/rv64ui-p-sraw.hex | 0 tests/riscv/{isa64 => isa}/rv64ui-p-srl.hex | 0 tests/riscv/{isa64 => isa}/rv64ui-p-srli.hex | 0 tests/riscv/{isa64 => isa}/rv64ui-p-srliw.hex | 0 tests/riscv/{isa64 => isa}/rv64ui-p-srlw.hex | 0 tests/riscv/{isa64 => isa}/rv64ui-p-sub.hex | 0 tests/riscv/{isa64 => isa}/rv64ui-p-subw.hex | 0 tests/riscv/{isa64 => isa}/rv64ui-p-sw.hex | 0 tests/riscv/{isa64 => isa}/rv64ui-p-xor.hex | 0 tests/riscv/{isa64 => isa}/rv64ui-p-xori.hex | 0 tests/riscv/{isa64 => isa}/rv64um-p-div.hex | 0 tests/riscv/{isa64 => isa}/rv64um-p-divu.hex | 0 tests/riscv/{isa64 => isa}/rv64um-p-divuw.hex | 0 tests/riscv/{isa64 => isa}/rv64um-p-divw.hex | 0 tests/riscv/{isa64 => isa}/rv64um-p-mul.hex | 0 tests/riscv/{isa64 => isa}/rv64um-p-mulh.hex | 0 .../riscv/{isa64 => isa}/rv64um-p-mulhsu.hex | 0 tests/riscv/{isa64 => isa}/rv64um-p-mulhu.hex | 0 tests/riscv/{isa64 => isa}/rv64um-p-mulw.hex | 0 tests/riscv/{isa64 => isa}/rv64um-p-rem.hex | 0 tests/riscv/{isa64 => isa}/rv64um-p-remu.hex | 0 tests/riscv/{isa64 => isa}/rv64um-p-remuw.hex | 0 tests/riscv/{isa64 => isa}/rv64um-p-remw.hex | 0 tests/riscv/isa64/Makefile | 32 -- 90 files changed, 290 insertions(+), 37 deletions(-) create mode 100644 tests/riscv/isa/ramulator.ddr4.log rename tests/riscv/{isa64 => isa}/rv64ud-p-fadd.hex (100%) rename tests/riscv/{isa64 => isa}/rv64ud-p-fclass.hex (100%) rename tests/riscv/{isa64 => isa}/rv64ud-p-fcmp.hex (100%) rename tests/riscv/{isa64 => isa}/rv64ud-p-fcvt.hex (100%) rename tests/riscv/{isa64 => isa}/rv64ud-p-fcvt_w.hex (100%) rename tests/riscv/{isa64 => isa}/rv64ud-p-fdiv.hex (100%) rename tests/riscv/{isa64 => isa}/rv64ud-p-fmadd.hex (100%) rename tests/riscv/{isa64 => isa}/rv64ud-p-fmin.hex (100%) rename tests/riscv/{isa64 => isa}/rv64ud-p-ldst.hex (100%) rename tests/riscv/{isa64 => isa}/rv64ud-p-move.hex (100%) rename tests/riscv/{isa64 => isa}/rv64ud-p-recoding.hex (100%) rename tests/riscv/{isa64 => isa}/rv64ud-p-structural.hex (100%) rename tests/riscv/{isa64 => isa}/rv64uf-p-fadd.hex (100%) rename tests/riscv/{isa64 => isa}/rv64uf-p-fclass.hex (100%) rename tests/riscv/{isa64 => isa}/rv64uf-p-fcmp.hex (100%) rename tests/riscv/{isa64 => isa}/rv64uf-p-fcvt.hex (100%) rename tests/riscv/{isa64 => isa}/rv64uf-p-fcvt_w.hex (100%) rename tests/riscv/{isa64 => isa}/rv64uf-p-fdiv.hex (100%) rename tests/riscv/{isa64 => isa}/rv64uf-p-fmadd.hex (100%) rename tests/riscv/{isa64 => isa}/rv64uf-p-fmin.hex (100%) rename tests/riscv/{isa64 => isa}/rv64uf-p-ldst.hex (100%) rename tests/riscv/{isa64 => isa}/rv64uf-p-move.hex (100%) rename tests/riscv/{isa64 => isa}/rv64uf-p-recoding.hex (100%) rename tests/riscv/{isa64 => isa}/rv64ui-p-add.hex (100%) rename tests/riscv/{isa64 => isa}/rv64ui-p-addi.hex (100%) rename tests/riscv/{isa64 => isa}/rv64ui-p-addiw.hex (100%) rename tests/riscv/{isa64 => isa}/rv64ui-p-addw.hex (100%) rename tests/riscv/{isa64 => isa}/rv64ui-p-and.hex (100%) rename tests/riscv/{isa64 => isa}/rv64ui-p-andi.hex (100%) rename tests/riscv/{isa64 => isa}/rv64ui-p-auipc.hex (100%) rename tests/riscv/{isa64 => isa}/rv64ui-p-beq.hex (100%) rename tests/riscv/{isa64 => isa}/rv64ui-p-bge.hex (100%) rename tests/riscv/{isa64 => isa}/rv64ui-p-bgeu.hex (100%) rename tests/riscv/{isa64 => isa}/rv64ui-p-blt.hex (100%) rename tests/riscv/{isa64 => isa}/rv64ui-p-bltu.hex (100%) rename tests/riscv/{isa64 => isa}/rv64ui-p-bne.hex (100%) rename tests/riscv/{isa64 => isa}/rv64ui-p-fence_i.hex (100%) rename tests/riscv/{isa64 => isa}/rv64ui-p-jal.hex (100%) rename tests/riscv/{isa64 => isa}/rv64ui-p-jalr.hex (100%) rename tests/riscv/{isa64 => isa}/rv64ui-p-lb.hex (100%) rename tests/riscv/{isa64 => isa}/rv64ui-p-lbu.hex (100%) rename tests/riscv/{isa64 => isa}/rv64ui-p-ld.hex (100%) rename tests/riscv/{isa64 => isa}/rv64ui-p-lh.hex (100%) rename tests/riscv/{isa64 => isa}/rv64ui-p-lhu.hex (100%) rename tests/riscv/{isa64 => isa}/rv64ui-p-lui.hex (100%) rename tests/riscv/{isa64 => isa}/rv64ui-p-lw.hex (100%) rename tests/riscv/{isa64 => isa}/rv64ui-p-lwu.hex (100%) rename tests/riscv/{isa64 => isa}/rv64ui-p-or.hex (100%) rename tests/riscv/{isa64 => isa}/rv64ui-p-ori.hex (100%) rename tests/riscv/{isa64 => isa}/rv64ui-p-sb.hex (100%) rename tests/riscv/{isa64 => isa}/rv64ui-p-sd.hex (100%) rename tests/riscv/{isa64 => isa}/rv64ui-p-sh.hex (100%) rename tests/riscv/{isa64 => isa}/rv64ui-p-simple.hex (100%) rename tests/riscv/{isa64 => isa}/rv64ui-p-sll.hex (100%) rename tests/riscv/{isa64 => isa}/rv64ui-p-slli.hex (100%) rename tests/riscv/{isa64 => isa}/rv64ui-p-slliw.hex (100%) rename tests/riscv/{isa64 => isa}/rv64ui-p-sllw.hex (100%) rename tests/riscv/{isa64 => isa}/rv64ui-p-slt.hex (100%) rename tests/riscv/{isa64 => isa}/rv64ui-p-slti.hex (100%) rename tests/riscv/{isa64 => isa}/rv64ui-p-sltiu.hex (100%) rename tests/riscv/{isa64 => isa}/rv64ui-p-sltu.hex (100%) rename tests/riscv/{isa64 => isa}/rv64ui-p-sra.hex (100%) rename tests/riscv/{isa64 => isa}/rv64ui-p-srai.hex (100%) rename tests/riscv/{isa64 => isa}/rv64ui-p-sraiw.hex (100%) rename tests/riscv/{isa64 => isa}/rv64ui-p-sraw.hex (100%) rename tests/riscv/{isa64 => isa}/rv64ui-p-srl.hex (100%) rename tests/riscv/{isa64 => isa}/rv64ui-p-srli.hex (100%) rename tests/riscv/{isa64 => isa}/rv64ui-p-srliw.hex (100%) rename tests/riscv/{isa64 => isa}/rv64ui-p-srlw.hex (100%) rename tests/riscv/{isa64 => isa}/rv64ui-p-sub.hex (100%) rename tests/riscv/{isa64 => isa}/rv64ui-p-subw.hex (100%) rename tests/riscv/{isa64 => isa}/rv64ui-p-sw.hex (100%) rename tests/riscv/{isa64 => isa}/rv64ui-p-xor.hex (100%) rename tests/riscv/{isa64 => isa}/rv64ui-p-xori.hex (100%) rename tests/riscv/{isa64 => isa}/rv64um-p-div.hex (100%) rename tests/riscv/{isa64 => isa}/rv64um-p-divu.hex (100%) rename tests/riscv/{isa64 => isa}/rv64um-p-divuw.hex (100%) rename tests/riscv/{isa64 => isa}/rv64um-p-divw.hex (100%) rename tests/riscv/{isa64 => isa}/rv64um-p-mul.hex (100%) rename tests/riscv/{isa64 => isa}/rv64um-p-mulh.hex (100%) rename tests/riscv/{isa64 => isa}/rv64um-p-mulhsu.hex (100%) rename tests/riscv/{isa64 => isa}/rv64um-p-mulhu.hex (100%) rename tests/riscv/{isa64 => isa}/rv64um-p-mulw.hex (100%) rename tests/riscv/{isa64 => isa}/rv64um-p-rem.hex (100%) rename tests/riscv/{isa64 => isa}/rv64um-p-remu.hex (100%) rename tests/riscv/{isa64 => isa}/rv64um-p-remuw.hex (100%) rename tests/riscv/{isa64 => isa}/rv64um-p-remw.hex (100%) delete mode 100644 tests/riscv/isa64/Makefile diff --git a/tests/riscv/isa/Makefile b/tests/riscv/isa/Makefile index de35c0d0..5f4f1cfa 100644 --- a/tests/riscv/isa/Makefile +++ b/tests/riscv/isa/Makefile @@ -1,16 +1,23 @@ -ALL_TESTS := $(wildcard *.hex) +ALL_TESTS := $(wildcard *.hex) +ALL_TESTS_32 := $(wildcard rv32*.hex) +ALL_TESTS_64 := $(wildcard rv64*.hex) D_TESTS := $(wildcard *ud-p-*.hex) V_TESTS := $(wildcard *-v-*.hex) -EXCLUDED_TESTS := $(V_TESTS) $(D_TESTS) rv32si-p-scall.hex rv32si-p-sbreak.hex rv32mi-p-breakpoint.hex rv32ua-p-amomax_w.hex rv32ua-p-amoxor_w.hex rv32ua-p-amoor_w.hex rv32mi-p-ma_addr.hex rv32mi-p-mcsr.hex rv32ua-p-amoswap_w.hex rv32mi-p-ma_fetch.hex rv32mi-p-csr.hex rv32ua-p-amoadd_w.hex rv32si-p-dirty.hex rv32ui-p-fence_i.hex rv32si-p-csr.hex rv32mi-p-shamt.hex rv32ua-p-amomin_w.hex rv32ua-p-lrsc.hex rv32si-p-wfi.hex rv32ua-p-amomaxu_w.hex rv32si-p-ma_fetch.hex rv32mi-p-illegal.hex rv32uc-p-rvc.hex rv32mi-p-sbreak.hex rv32ua-p-amominu_w.hex rv32ua-p-amoand_w.hex +EXCLUDED_TESTS_32 := $(V_TESTS) $(D_TESTS) rv32si-p-scall.hex rv32si-p-sbreak.hex rv32mi-p-breakpoint.hex rv32ua-p-amomax_w.hex rv32ua-p-amoxor_w.hex rv32ua-p-amoor_w.hex rv32mi-p-ma_addr.hex rv32mi-p-mcsr.hex rv32ua-p-amoswap_w.hex rv32mi-p-ma_fetch.hex rv32mi-p-csr.hex rv32ua-p-amoadd_w.hex rv32si-p-dirty.hex rv32ui-p-fence_i.hex rv32si-p-csr.hex rv32mi-p-shamt.hex rv32ua-p-amomin_w.hex rv32ua-p-lrsc.hex rv32si-p-wfi.hex rv32ua-p-amomaxu_w.hex rv32si-p-ma_fetch.hex rv32mi-p-illegal.hex rv32uc-p-rvc.hex rv32mi-p-sbreak.hex rv32ua-p-amominu_w.hex rv32ua-p-amoand_w.hex +EXCLUDED_TESTS_64 := rv64ud-p-move.hex -TESTS := $(filter-out $(EXCLUDED_TESTS), $(ALL_TESTS)) +TESTS_32 := $(filter-out $(EXCLUDED_TESTS_32), $(ALL_TESTS_32)) +TESTS_64 := $(filter-out $(EXCLUDED_TESTS_64), $(ALL_TESTS_64)) all: -run-simx: - $(foreach test, $(TESTS), ../../../sim/simx/simx -r -a rv32i -c 1 -i $(test) || exit;) +run-simx-32: + $(foreach test, $(TESTS_32), ../../../sim/simx/simx -r -a rv32i -c 1 -i $(test) || exit;) + +run-simx-64: + $(foreach test, $(TESTS_64), ../../../sim/simx/simx -r -a rv64imfd -c 1 -i $(test) || exit;) run-rtlsim: $(foreach test, $(TESTS), ../../../sim/rtlsim/rtlsim -r $(test) || exit;) diff --git a/tests/riscv/isa/ramulator.ddr4.log b/tests/riscv/isa/ramulator.ddr4.log new file mode 100644 index 00000000..7a4efe9c --- /dev/null +++ b/tests/riscv/isa/ramulator.ddr4.log @@ -0,0 +1,278 @@ + ramulator.active_cycles_0 76 # Total active cycles for level _0 + ramulator.busy_cycles_0 76 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0 + ramulator.serving_requests_0 76 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0 + ramulator.average_serving_requests_0 0.056130 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0 + ramulator.active_cycles_0_0 76 # Total active cycles for level _0_0 + ramulator.busy_cycles_0_0 76 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0 + ramulator.serving_requests_0_0 76 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0 + ramulator.average_serving_requests_0_0 0.056130 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0 + ramulator.active_cycles_0_0_0 76 # Total active cycles for level _0_0_0 + ramulator.busy_cycles_0_0_0 76 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_0 + ramulator.serving_requests_0_0_0 76 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0 +ramulator.average_serving_requests_0_0_0 0.056130 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0 + ramulator.active_cycles_0_0_0_0 76 # Total active cycles for level _0_0_0_0 + ramulator.busy_cycles_0_0_0_0 76 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_0_0 + ramulator.serving_requests_0_0_0_0 76 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_0 +ramulator.average_serving_requests_0_0_0_0 0.056130 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_0 + ramulator.active_cycles_0_0_0_1 0 # Total active cycles for level _0_0_0_1 + ramulator.busy_cycles_0_0_0_1 0 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_0_1 + ramulator.serving_requests_0_0_0_1 0 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_1 +ramulator.average_serving_requests_0_0_0_1 0.000000 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_1 + ramulator.active_cycles_0_0_0_2 0 # Total active cycles for level _0_0_0_2 + ramulator.busy_cycles_0_0_0_2 0 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_0_2 + ramulator.serving_requests_0_0_0_2 0 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_2 +ramulator.average_serving_requests_0_0_0_2 0.000000 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_2 + ramulator.active_cycles_0_0_0_3 0 # Total active cycles for level _0_0_0_3 + ramulator.busy_cycles_0_0_0_3 0 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_0_3 + ramulator.serving_requests_0_0_0_3 0 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_3 +ramulator.average_serving_requests_0_0_0_3 0.000000 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_3 + ramulator.active_cycles_0_0_1 0 # Total active cycles for level _0_0_1 + ramulator.busy_cycles_0_0_1 0 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_1 + ramulator.serving_requests_0_0_1 0 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1 +ramulator.average_serving_requests_0_0_1 0.000000 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1 + ramulator.active_cycles_0_0_1_0 0 # Total active cycles for level _0_0_1_0 + ramulator.busy_cycles_0_0_1_0 0 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_1_0 + ramulator.serving_requests_0_0_1_0 0 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_0 +ramulator.average_serving_requests_0_0_1_0 0.000000 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_0 + ramulator.active_cycles_0_0_1_1 0 # Total active cycles for level _0_0_1_1 + ramulator.busy_cycles_0_0_1_1 0 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_1_1 + ramulator.serving_requests_0_0_1_1 0 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_1 +ramulator.average_serving_requests_0_0_1_1 0.000000 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_1 + ramulator.active_cycles_0_0_1_2 0 # Total active cycles for level _0_0_1_2 + ramulator.busy_cycles_0_0_1_2 0 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_1_2 + ramulator.serving_requests_0_0_1_2 0 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_2 +ramulator.average_serving_requests_0_0_1_2 0.000000 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_2 + ramulator.active_cycles_0_0_1_3 0 # Total active cycles for level _0_0_1_3 + ramulator.busy_cycles_0_0_1_3 0 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_1_3 + ramulator.serving_requests_0_0_1_3 0 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_3 +ramulator.average_serving_requests_0_0_1_3 0.000000 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_3 + ramulator.active_cycles_0_0_2 0 # Total active cycles for level _0_0_2 + ramulator.busy_cycles_0_0_2 0 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_2 + ramulator.serving_requests_0_0_2 0 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2 +ramulator.average_serving_requests_0_0_2 0.000000 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2 + ramulator.active_cycles_0_0_2_0 0 # Total active cycles for level _0_0_2_0 + ramulator.busy_cycles_0_0_2_0 0 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_2_0 + ramulator.serving_requests_0_0_2_0 0 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_0 +ramulator.average_serving_requests_0_0_2_0 0.000000 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_0 + ramulator.active_cycles_0_0_2_1 0 # Total active cycles for level _0_0_2_1 + ramulator.busy_cycles_0_0_2_1 0 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_2_1 + ramulator.serving_requests_0_0_2_1 0 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_1 +ramulator.average_serving_requests_0_0_2_1 0.000000 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_1 + ramulator.active_cycles_0_0_2_2 0 # Total active cycles for level _0_0_2_2 + ramulator.busy_cycles_0_0_2_2 0 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_2_2 + ramulator.serving_requests_0_0_2_2 0 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_2 +ramulator.average_serving_requests_0_0_2_2 0.000000 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_2 + ramulator.active_cycles_0_0_2_3 0 # Total active cycles for level _0_0_2_3 + ramulator.busy_cycles_0_0_2_3 0 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_2_3 + ramulator.serving_requests_0_0_2_3 0 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_3 +ramulator.average_serving_requests_0_0_2_3 0.000000 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_3 + ramulator.active_cycles_0_0_3 0 # Total active cycles for level _0_0_3 + ramulator.busy_cycles_0_0_3 0 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_3 + ramulator.serving_requests_0_0_3 0 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3 +ramulator.average_serving_requests_0_0_3 0.000000 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3 + ramulator.active_cycles_0_0_3_0 0 # Total active cycles for level _0_0_3_0 + ramulator.busy_cycles_0_0_3_0 0 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_3_0 + ramulator.serving_requests_0_0_3_0 0 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_0 +ramulator.average_serving_requests_0_0_3_0 0.000000 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_0 + ramulator.active_cycles_0_0_3_1 0 # Total active cycles for level _0_0_3_1 + ramulator.busy_cycles_0_0_3_1 0 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_3_1 + ramulator.serving_requests_0_0_3_1 0 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_1 +ramulator.average_serving_requests_0_0_3_1 0.000000 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_1 + ramulator.active_cycles_0_0_3_2 0 # Total active cycles for level _0_0_3_2 + ramulator.busy_cycles_0_0_3_2 0 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_3_2 + ramulator.serving_requests_0_0_3_2 0 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_2 +ramulator.average_serving_requests_0_0_3_2 0.000000 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_2 + ramulator.active_cycles_0_0_3_3 0 # Total active cycles for level _0_0_3_3 + ramulator.busy_cycles_0_0_3_3 0 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_3_3 + ramulator.serving_requests_0_0_3_3 0 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_3 +ramulator.average_serving_requests_0_0_3_3 0.000000 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_3 + ramulator.read_transaction_bytes_0 192 # The total byte of read transaction per channel + ramulator.write_transaction_bytes_0 0 # The total byte of write transaction per channel + ramulator.row_hits_channel_0_core 2 # Number of row hits per channel per core + ramulator.row_misses_channel_0_core 1 # Number of row misses per channel per core + ramulator.row_conflicts_channel_0_core 0 # Number of row conflicts per channel per core + ramulator.read_row_hits_channel_0_core 2 # Number of row hits for read requests per channel per core + [0] 2.0 # +ramulator.read_row_misses_channel_0_core 1 # Number of row misses for read requests per channel per core + [0] 1.0 # +ramulator.read_row_conflicts_channel_0_core 0 # Number of row conflicts for read requests per channel per core + [0] 0.0 # + ramulator.write_row_hits_channel_0_core 0 # Number of row hits for write requests per channel per core + [0] 0.0 # +ramulator.write_row_misses_channel_0_core 0 # Number of row misses for write requests per channel per core + [0] 0.0 # +ramulator.write_row_conflicts_channel_0_core 0 # Number of row conflicts for write requests per channel per core + [0] 0.0 # + ramulator.useless_activates_0_core 0 # Number of useless activations. E.g, ACT -> PRE w/o RD or WR + ramulator.read_latency_avg_0 26.333333 # The average memory latency cycles (in memory time domain) per request for all read requests in this channel + ramulator.read_latency_sum_0 79 # The memory latency cycles (in memory time domain) sum for all read requests in this channel + ramulator.req_queue_length_avg_0 0.046529 # Average of read and write queue length per memory cycle per channel. + ramulator.req_queue_length_sum_0 63 # Sum of read and write queue length per memory cycle per channel. + ramulator.read_req_queue_length_avg_0 0.046529 # Read queue length average per memory cycle per channel. + ramulator.read_req_queue_length_sum_0 63 # Read queue length sum per memory cycle per channel. + ramulator.write_req_queue_length_avg_0 0.000000 # Write queue length average per memory cycle per channel. + ramulator.write_req_queue_length_sum_0 0 # Write queue length sum per memory cycle per channel. + ramulator.record_read_hits 0.0 # record read hit count for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.record_read_misses 0.0 # record_read_miss count for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.record_read_conflicts 0.0 # record read conflict count for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.record_write_hits 0.0 # record write hit count for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.record_write_misses 0.0 # record write miss count for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.record_write_conflicts 0.0 # record write conflict for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.active_cycles_1 76 # Total active cycles for level _1 + ramulator.busy_cycles_1 76 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _1 + ramulator.serving_requests_1 76 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _1 + ramulator.average_serving_requests_1 0.056130 # The average of read and write requests that are served in this DRAM element per memory cycle for level _1 + ramulator.active_cycles_1_0 76 # Total active cycles for level _1_0 + ramulator.busy_cycles_1_0 76 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _1_0 + ramulator.serving_requests_1_0 76 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _1_0 + ramulator.average_serving_requests_1_0 0.056130 # The average of read and write requests that are served in this DRAM element per memory cycle for level _1_0 + ramulator.active_cycles_1_0_0 76 # Total active cycles for level _1_0_0 + ramulator.busy_cycles_1_0_0 76 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _1_0_0 + ramulator.serving_requests_1_0_0 76 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _1_0_0 +ramulator.average_serving_requests_1_0_0 0.056130 # The average of read and write requests that are served in this DRAM element per memory cycle for level _1_0_0 + ramulator.active_cycles_1_0_0_0 76 # Total active cycles for level _1_0_0_0 + ramulator.busy_cycles_1_0_0_0 76 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _1_0_0_0 + ramulator.serving_requests_1_0_0_0 76 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _1_0_0_0 +ramulator.average_serving_requests_1_0_0_0 0.056130 # The average of read and write requests that are served in this DRAM element per memory cycle for level _1_0_0_0 + ramulator.active_cycles_1_0_0_1 0 # Total active cycles for level _1_0_0_1 + ramulator.busy_cycles_1_0_0_1 0 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _1_0_0_1 + ramulator.serving_requests_1_0_0_1 0 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _1_0_0_1 +ramulator.average_serving_requests_1_0_0_1 0.000000 # The average of read and write requests that are served in this DRAM element per memory cycle for level _1_0_0_1 + ramulator.active_cycles_1_0_0_2 0 # Total active cycles for level _1_0_0_2 + ramulator.busy_cycles_1_0_0_2 0 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _1_0_0_2 + ramulator.serving_requests_1_0_0_2 0 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _1_0_0_2 +ramulator.average_serving_requests_1_0_0_2 0.000000 # The average of read and write requests that are served in this DRAM element per memory cycle for level _1_0_0_2 + ramulator.active_cycles_1_0_0_3 0 # Total active cycles for level _1_0_0_3 + ramulator.busy_cycles_1_0_0_3 0 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _1_0_0_3 + ramulator.serving_requests_1_0_0_3 0 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _1_0_0_3 +ramulator.average_serving_requests_1_0_0_3 0.000000 # The average of read and write requests that are served in this DRAM element per memory cycle for level _1_0_0_3 + ramulator.active_cycles_1_0_1 0 # Total active cycles for level _1_0_1 + ramulator.busy_cycles_1_0_1 0 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _1_0_1 + ramulator.serving_requests_1_0_1 0 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _1_0_1 +ramulator.average_serving_requests_1_0_1 0.000000 # The average of read and write requests that are served in this DRAM element per memory cycle for level _1_0_1 + ramulator.active_cycles_1_0_1_0 0 # Total active cycles for level _1_0_1_0 + ramulator.busy_cycles_1_0_1_0 0 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _1_0_1_0 + ramulator.serving_requests_1_0_1_0 0 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _1_0_1_0 +ramulator.average_serving_requests_1_0_1_0 0.000000 # The average of read and write requests that are served in this DRAM element per memory cycle for level _1_0_1_0 + ramulator.active_cycles_1_0_1_1 0 # Total active cycles for level _1_0_1_1 + ramulator.busy_cycles_1_0_1_1 0 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _1_0_1_1 + ramulator.serving_requests_1_0_1_1 0 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _1_0_1_1 +ramulator.average_serving_requests_1_0_1_1 0.000000 # The average of read and write requests that are served in this DRAM element per memory cycle for level _1_0_1_1 + ramulator.active_cycles_1_0_1_2 0 # Total active cycles for level _1_0_1_2 + ramulator.busy_cycles_1_0_1_2 0 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _1_0_1_2 + ramulator.serving_requests_1_0_1_2 0 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _1_0_1_2 +ramulator.average_serving_requests_1_0_1_2 0.000000 # The average of read and write requests that are served in this DRAM element per memory cycle for level _1_0_1_2 + ramulator.active_cycles_1_0_1_3 0 # Total active cycles for level _1_0_1_3 + ramulator.busy_cycles_1_0_1_3 0 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _1_0_1_3 + ramulator.serving_requests_1_0_1_3 0 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _1_0_1_3 +ramulator.average_serving_requests_1_0_1_3 0.000000 # The average of read and write requests that are served in this DRAM element per memory cycle for level _1_0_1_3 + ramulator.active_cycles_1_0_2 0 # Total active cycles for level _1_0_2 + ramulator.busy_cycles_1_0_2 0 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _1_0_2 + ramulator.serving_requests_1_0_2 0 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _1_0_2 +ramulator.average_serving_requests_1_0_2 0.000000 # The average of read and write requests that are served in this DRAM element per memory cycle for level _1_0_2 + ramulator.active_cycles_1_0_2_0 0 # Total active cycles for level _1_0_2_0 + ramulator.busy_cycles_1_0_2_0 0 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _1_0_2_0 + ramulator.serving_requests_1_0_2_0 0 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _1_0_2_0 +ramulator.average_serving_requests_1_0_2_0 0.000000 # The average of read and write requests that are served in this DRAM element per memory cycle for level _1_0_2_0 + ramulator.active_cycles_1_0_2_1 0 # Total active cycles for level _1_0_2_1 + ramulator.busy_cycles_1_0_2_1 0 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _1_0_2_1 + ramulator.serving_requests_1_0_2_1 0 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _1_0_2_1 +ramulator.average_serving_requests_1_0_2_1 0.000000 # The average of read and write requests that are served in this DRAM element per memory cycle for level _1_0_2_1 + ramulator.active_cycles_1_0_2_2 0 # Total active cycles for level _1_0_2_2 + ramulator.busy_cycles_1_0_2_2 0 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _1_0_2_2 + ramulator.serving_requests_1_0_2_2 0 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _1_0_2_2 +ramulator.average_serving_requests_1_0_2_2 0.000000 # The average of read and write requests that are served in this DRAM element per memory cycle for level _1_0_2_2 + ramulator.active_cycles_1_0_2_3 0 # Total active cycles for level _1_0_2_3 + ramulator.busy_cycles_1_0_2_3 0 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _1_0_2_3 + ramulator.serving_requests_1_0_2_3 0 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _1_0_2_3 +ramulator.average_serving_requests_1_0_2_3 0.000000 # The average of read and write requests that are served in this DRAM element per memory cycle for level _1_0_2_3 + ramulator.active_cycles_1_0_3 0 # Total active cycles for level _1_0_3 + ramulator.busy_cycles_1_0_3 0 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _1_0_3 + ramulator.serving_requests_1_0_3 0 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _1_0_3 +ramulator.average_serving_requests_1_0_3 0.000000 # The average of read and write requests that are served in this DRAM element per memory cycle for level _1_0_3 + ramulator.active_cycles_1_0_3_0 0 # Total active cycles for level _1_0_3_0 + ramulator.busy_cycles_1_0_3_0 0 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _1_0_3_0 + ramulator.serving_requests_1_0_3_0 0 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _1_0_3_0 +ramulator.average_serving_requests_1_0_3_0 0.000000 # The average of read and write requests that are served in this DRAM element per memory cycle for level _1_0_3_0 + ramulator.active_cycles_1_0_3_1 0 # Total active cycles for level _1_0_3_1 + ramulator.busy_cycles_1_0_3_1 0 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _1_0_3_1 + ramulator.serving_requests_1_0_3_1 0 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _1_0_3_1 +ramulator.average_serving_requests_1_0_3_1 0.000000 # The average of read and write requests that are served in this DRAM element per memory cycle for level _1_0_3_1 + ramulator.active_cycles_1_0_3_2 0 # Total active cycles for level _1_0_3_2 + ramulator.busy_cycles_1_0_3_2 0 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _1_0_3_2 + ramulator.serving_requests_1_0_3_2 0 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _1_0_3_2 +ramulator.average_serving_requests_1_0_3_2 0.000000 # The average of read and write requests that are served in this DRAM element per memory cycle for level _1_0_3_2 + ramulator.active_cycles_1_0_3_3 0 # Total active cycles for level _1_0_3_3 + ramulator.busy_cycles_1_0_3_3 0 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _1_0_3_3 + ramulator.serving_requests_1_0_3_3 0 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _1_0_3_3 +ramulator.average_serving_requests_1_0_3_3 0.000000 # The average of read and write requests that are served in this DRAM element per memory cycle for level _1_0_3_3 + ramulator.read_transaction_bytes_1 192 # The total byte of read transaction per channel + ramulator.write_transaction_bytes_1 0 # The total byte of write transaction per channel + ramulator.row_hits_channel_1_core 2 # Number of row hits per channel per core + ramulator.row_misses_channel_1_core 1 # Number of row misses per channel per core + ramulator.row_conflicts_channel_1_core 0 # Number of row conflicts per channel per core + ramulator.read_row_hits_channel_1_core 2 # Number of row hits for read requests per channel per core + [0] 2.0 # +ramulator.read_row_misses_channel_1_core 1 # Number of row misses for read requests per channel per core + [0] 1.0 # +ramulator.read_row_conflicts_channel_1_core 0 # Number of row conflicts for read requests per channel per core + [0] 0.0 # + ramulator.write_row_hits_channel_1_core 0 # Number of row hits for write requests per channel per core + [0] 0.0 # +ramulator.write_row_misses_channel_1_core 0 # Number of row misses for write requests per channel per core + [0] 0.0 # +ramulator.write_row_conflicts_channel_1_core 0 # Number of row conflicts for write requests per channel per core + [0] 0.0 # + ramulator.useless_activates_1_core 0 # Number of useless activations. E.g, ACT -> PRE w/o RD or WR + ramulator.read_latency_avg_1 26.333333 # The average memory latency cycles (in memory time domain) per request for all read requests in this channel + ramulator.read_latency_sum_1 79 # The memory latency cycles (in memory time domain) sum for all read requests in this channel + ramulator.req_queue_length_avg_1 0.046529 # Average of read and write queue length per memory cycle per channel. + ramulator.req_queue_length_sum_1 63 # Sum of read and write queue length per memory cycle per channel. + ramulator.read_req_queue_length_avg_1 0.046529 # Read queue length average per memory cycle per channel. + ramulator.read_req_queue_length_sum_1 63 # Read queue length sum per memory cycle per channel. + ramulator.write_req_queue_length_avg_1 0.000000 # Write queue length average per memory cycle per channel. + ramulator.write_req_queue_length_sum_1 0 # Write queue length sum per memory cycle per channel. + ramulator.record_read_hits 0.0 # record read hit count for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.record_read_misses 0.0 # record_read_miss count for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.record_read_conflicts 0.0 # record read conflict count for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.record_write_hits 0.0 # record write hit count for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.record_write_misses 0.0 # record write miss count for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.record_write_conflicts 0.0 # record write conflict for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.dram_capacity 8589934592 # Number of bytes in simulated DRAM + ramulator.dram_cycles 1354 # Number of DRAM cycles simulated + ramulator.incoming_requests 6 # Number of incoming requests to DRAM + ramulator.read_requests 6 # Number of incoming read requests to DRAM per core + [0] 6.0 # + ramulator.write_requests 0 # Number of incoming write requests to DRAM per core + [0] 0.0 # + ramulator.ramulator_active_cycles 152 # The total number of cycles that the DRAM part is active (serving R/W) + ramulator.incoming_requests_per_channel 6.0 # Number of incoming requests to each DRAM channel + [0] 3.0 # + [1] 3.0 # +ramulator.incoming_read_reqs_per_channel 6.0 # Number of incoming read requests to each DRAM channel + [0] 3.0 # + [1] 3.0 # + ramulator.physical_page_replacement 0 # The number of times that physical page replacement happens. + ramulator.maximum_bandwidth 38400000000 # The theoretical maximum bandwidth (Bps) + ramulator.in_queue_req_num_sum 126 # Sum of read/write queue length + ramulator.in_queue_read_req_num_sum 126 # Sum of read queue length + ramulator.in_queue_write_req_num_sum 0 # Sum of write queue length + ramulator.in_queue_req_num_avg 0.093058 # Average of read/write queue length per memory cycle + ramulator.in_queue_read_req_num_avg 0.093058 # Average of read queue length per memory cycle + ramulator.in_queue_write_req_num_avg 0.000000 # Average of write queue length per memory cycle + ramulator.record_read_requests 0.0 # record read requests for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.record_write_requests 0.0 # record write requests for this core when it reaches request limit or to the end + [0] 0.0 # diff --git a/tests/riscv/isa64/rv64ud-p-fadd.hex b/tests/riscv/isa/rv64ud-p-fadd.hex similarity index 100% rename from tests/riscv/isa64/rv64ud-p-fadd.hex rename to tests/riscv/isa/rv64ud-p-fadd.hex diff --git a/tests/riscv/isa64/rv64ud-p-fclass.hex b/tests/riscv/isa/rv64ud-p-fclass.hex similarity index 100% rename from tests/riscv/isa64/rv64ud-p-fclass.hex rename to tests/riscv/isa/rv64ud-p-fclass.hex diff --git a/tests/riscv/isa64/rv64ud-p-fcmp.hex b/tests/riscv/isa/rv64ud-p-fcmp.hex similarity index 100% rename from tests/riscv/isa64/rv64ud-p-fcmp.hex rename to tests/riscv/isa/rv64ud-p-fcmp.hex diff --git a/tests/riscv/isa64/rv64ud-p-fcvt.hex b/tests/riscv/isa/rv64ud-p-fcvt.hex similarity index 100% rename from tests/riscv/isa64/rv64ud-p-fcvt.hex rename to tests/riscv/isa/rv64ud-p-fcvt.hex diff --git a/tests/riscv/isa64/rv64ud-p-fcvt_w.hex b/tests/riscv/isa/rv64ud-p-fcvt_w.hex similarity index 100% rename from tests/riscv/isa64/rv64ud-p-fcvt_w.hex rename to tests/riscv/isa/rv64ud-p-fcvt_w.hex diff --git a/tests/riscv/isa64/rv64ud-p-fdiv.hex b/tests/riscv/isa/rv64ud-p-fdiv.hex similarity index 100% rename from tests/riscv/isa64/rv64ud-p-fdiv.hex rename to tests/riscv/isa/rv64ud-p-fdiv.hex diff --git a/tests/riscv/isa64/rv64ud-p-fmadd.hex b/tests/riscv/isa/rv64ud-p-fmadd.hex similarity index 100% rename from tests/riscv/isa64/rv64ud-p-fmadd.hex rename to tests/riscv/isa/rv64ud-p-fmadd.hex diff --git a/tests/riscv/isa64/rv64ud-p-fmin.hex b/tests/riscv/isa/rv64ud-p-fmin.hex similarity index 100% rename from tests/riscv/isa64/rv64ud-p-fmin.hex rename to tests/riscv/isa/rv64ud-p-fmin.hex diff --git a/tests/riscv/isa64/rv64ud-p-ldst.hex b/tests/riscv/isa/rv64ud-p-ldst.hex similarity index 100% rename from tests/riscv/isa64/rv64ud-p-ldst.hex rename to tests/riscv/isa/rv64ud-p-ldst.hex diff --git a/tests/riscv/isa64/rv64ud-p-move.hex b/tests/riscv/isa/rv64ud-p-move.hex similarity index 100% rename from tests/riscv/isa64/rv64ud-p-move.hex rename to tests/riscv/isa/rv64ud-p-move.hex diff --git a/tests/riscv/isa64/rv64ud-p-recoding.hex b/tests/riscv/isa/rv64ud-p-recoding.hex similarity index 100% rename from tests/riscv/isa64/rv64ud-p-recoding.hex rename to tests/riscv/isa/rv64ud-p-recoding.hex diff --git a/tests/riscv/isa64/rv64ud-p-structural.hex b/tests/riscv/isa/rv64ud-p-structural.hex similarity index 100% rename from tests/riscv/isa64/rv64ud-p-structural.hex rename to tests/riscv/isa/rv64ud-p-structural.hex diff --git a/tests/riscv/isa64/rv64uf-p-fadd.hex b/tests/riscv/isa/rv64uf-p-fadd.hex similarity index 100% rename from tests/riscv/isa64/rv64uf-p-fadd.hex rename to tests/riscv/isa/rv64uf-p-fadd.hex diff --git a/tests/riscv/isa64/rv64uf-p-fclass.hex b/tests/riscv/isa/rv64uf-p-fclass.hex similarity index 100% rename from tests/riscv/isa64/rv64uf-p-fclass.hex rename to tests/riscv/isa/rv64uf-p-fclass.hex diff --git a/tests/riscv/isa64/rv64uf-p-fcmp.hex b/tests/riscv/isa/rv64uf-p-fcmp.hex similarity index 100% rename from tests/riscv/isa64/rv64uf-p-fcmp.hex rename to tests/riscv/isa/rv64uf-p-fcmp.hex diff --git a/tests/riscv/isa64/rv64uf-p-fcvt.hex b/tests/riscv/isa/rv64uf-p-fcvt.hex similarity index 100% rename from tests/riscv/isa64/rv64uf-p-fcvt.hex rename to tests/riscv/isa/rv64uf-p-fcvt.hex diff --git a/tests/riscv/isa64/rv64uf-p-fcvt_w.hex b/tests/riscv/isa/rv64uf-p-fcvt_w.hex similarity index 100% rename from tests/riscv/isa64/rv64uf-p-fcvt_w.hex rename to tests/riscv/isa/rv64uf-p-fcvt_w.hex diff --git a/tests/riscv/isa64/rv64uf-p-fdiv.hex b/tests/riscv/isa/rv64uf-p-fdiv.hex similarity index 100% rename from tests/riscv/isa64/rv64uf-p-fdiv.hex rename to tests/riscv/isa/rv64uf-p-fdiv.hex diff --git a/tests/riscv/isa64/rv64uf-p-fmadd.hex b/tests/riscv/isa/rv64uf-p-fmadd.hex similarity index 100% rename from tests/riscv/isa64/rv64uf-p-fmadd.hex rename to tests/riscv/isa/rv64uf-p-fmadd.hex diff --git a/tests/riscv/isa64/rv64uf-p-fmin.hex b/tests/riscv/isa/rv64uf-p-fmin.hex similarity index 100% rename from tests/riscv/isa64/rv64uf-p-fmin.hex rename to tests/riscv/isa/rv64uf-p-fmin.hex diff --git a/tests/riscv/isa64/rv64uf-p-ldst.hex b/tests/riscv/isa/rv64uf-p-ldst.hex similarity index 100% rename from tests/riscv/isa64/rv64uf-p-ldst.hex rename to tests/riscv/isa/rv64uf-p-ldst.hex diff --git a/tests/riscv/isa64/rv64uf-p-move.hex b/tests/riscv/isa/rv64uf-p-move.hex similarity index 100% rename from tests/riscv/isa64/rv64uf-p-move.hex rename to tests/riscv/isa/rv64uf-p-move.hex diff --git a/tests/riscv/isa64/rv64uf-p-recoding.hex b/tests/riscv/isa/rv64uf-p-recoding.hex similarity index 100% rename from tests/riscv/isa64/rv64uf-p-recoding.hex rename to tests/riscv/isa/rv64uf-p-recoding.hex diff --git a/tests/riscv/isa64/rv64ui-p-add.hex b/tests/riscv/isa/rv64ui-p-add.hex similarity index 100% rename from tests/riscv/isa64/rv64ui-p-add.hex rename to tests/riscv/isa/rv64ui-p-add.hex diff --git a/tests/riscv/isa64/rv64ui-p-addi.hex b/tests/riscv/isa/rv64ui-p-addi.hex similarity index 100% rename from tests/riscv/isa64/rv64ui-p-addi.hex rename to tests/riscv/isa/rv64ui-p-addi.hex diff --git a/tests/riscv/isa64/rv64ui-p-addiw.hex b/tests/riscv/isa/rv64ui-p-addiw.hex similarity index 100% rename from tests/riscv/isa64/rv64ui-p-addiw.hex rename to tests/riscv/isa/rv64ui-p-addiw.hex diff --git a/tests/riscv/isa64/rv64ui-p-addw.hex b/tests/riscv/isa/rv64ui-p-addw.hex similarity index 100% rename from tests/riscv/isa64/rv64ui-p-addw.hex rename to tests/riscv/isa/rv64ui-p-addw.hex diff --git a/tests/riscv/isa64/rv64ui-p-and.hex b/tests/riscv/isa/rv64ui-p-and.hex similarity index 100% rename from tests/riscv/isa64/rv64ui-p-and.hex rename to tests/riscv/isa/rv64ui-p-and.hex diff --git a/tests/riscv/isa64/rv64ui-p-andi.hex b/tests/riscv/isa/rv64ui-p-andi.hex similarity index 100% rename from tests/riscv/isa64/rv64ui-p-andi.hex rename to tests/riscv/isa/rv64ui-p-andi.hex diff --git a/tests/riscv/isa64/rv64ui-p-auipc.hex b/tests/riscv/isa/rv64ui-p-auipc.hex similarity index 100% rename from tests/riscv/isa64/rv64ui-p-auipc.hex rename to tests/riscv/isa/rv64ui-p-auipc.hex diff --git a/tests/riscv/isa64/rv64ui-p-beq.hex b/tests/riscv/isa/rv64ui-p-beq.hex similarity index 100% rename from tests/riscv/isa64/rv64ui-p-beq.hex rename to tests/riscv/isa/rv64ui-p-beq.hex diff --git a/tests/riscv/isa64/rv64ui-p-bge.hex b/tests/riscv/isa/rv64ui-p-bge.hex similarity index 100% rename from tests/riscv/isa64/rv64ui-p-bge.hex rename to tests/riscv/isa/rv64ui-p-bge.hex diff --git a/tests/riscv/isa64/rv64ui-p-bgeu.hex b/tests/riscv/isa/rv64ui-p-bgeu.hex similarity index 100% rename from tests/riscv/isa64/rv64ui-p-bgeu.hex rename to tests/riscv/isa/rv64ui-p-bgeu.hex diff --git a/tests/riscv/isa64/rv64ui-p-blt.hex b/tests/riscv/isa/rv64ui-p-blt.hex similarity index 100% rename from tests/riscv/isa64/rv64ui-p-blt.hex rename to tests/riscv/isa/rv64ui-p-blt.hex diff --git a/tests/riscv/isa64/rv64ui-p-bltu.hex b/tests/riscv/isa/rv64ui-p-bltu.hex similarity index 100% rename from tests/riscv/isa64/rv64ui-p-bltu.hex rename to tests/riscv/isa/rv64ui-p-bltu.hex diff --git a/tests/riscv/isa64/rv64ui-p-bne.hex b/tests/riscv/isa/rv64ui-p-bne.hex similarity index 100% rename from tests/riscv/isa64/rv64ui-p-bne.hex rename to tests/riscv/isa/rv64ui-p-bne.hex diff --git a/tests/riscv/isa64/rv64ui-p-fence_i.hex b/tests/riscv/isa/rv64ui-p-fence_i.hex similarity index 100% rename from tests/riscv/isa64/rv64ui-p-fence_i.hex rename to tests/riscv/isa/rv64ui-p-fence_i.hex diff --git a/tests/riscv/isa64/rv64ui-p-jal.hex b/tests/riscv/isa/rv64ui-p-jal.hex similarity index 100% rename from tests/riscv/isa64/rv64ui-p-jal.hex rename to tests/riscv/isa/rv64ui-p-jal.hex diff --git a/tests/riscv/isa64/rv64ui-p-jalr.hex b/tests/riscv/isa/rv64ui-p-jalr.hex similarity index 100% rename from tests/riscv/isa64/rv64ui-p-jalr.hex rename to tests/riscv/isa/rv64ui-p-jalr.hex diff --git a/tests/riscv/isa64/rv64ui-p-lb.hex b/tests/riscv/isa/rv64ui-p-lb.hex similarity index 100% rename from tests/riscv/isa64/rv64ui-p-lb.hex rename to tests/riscv/isa/rv64ui-p-lb.hex diff --git a/tests/riscv/isa64/rv64ui-p-lbu.hex b/tests/riscv/isa/rv64ui-p-lbu.hex similarity index 100% rename from tests/riscv/isa64/rv64ui-p-lbu.hex rename to tests/riscv/isa/rv64ui-p-lbu.hex diff --git a/tests/riscv/isa64/rv64ui-p-ld.hex b/tests/riscv/isa/rv64ui-p-ld.hex similarity index 100% rename from tests/riscv/isa64/rv64ui-p-ld.hex rename to tests/riscv/isa/rv64ui-p-ld.hex diff --git a/tests/riscv/isa64/rv64ui-p-lh.hex b/tests/riscv/isa/rv64ui-p-lh.hex similarity index 100% rename from tests/riscv/isa64/rv64ui-p-lh.hex rename to tests/riscv/isa/rv64ui-p-lh.hex diff --git a/tests/riscv/isa64/rv64ui-p-lhu.hex b/tests/riscv/isa/rv64ui-p-lhu.hex similarity index 100% rename from tests/riscv/isa64/rv64ui-p-lhu.hex rename to tests/riscv/isa/rv64ui-p-lhu.hex diff --git a/tests/riscv/isa64/rv64ui-p-lui.hex b/tests/riscv/isa/rv64ui-p-lui.hex similarity index 100% rename from tests/riscv/isa64/rv64ui-p-lui.hex rename to tests/riscv/isa/rv64ui-p-lui.hex diff --git a/tests/riscv/isa64/rv64ui-p-lw.hex b/tests/riscv/isa/rv64ui-p-lw.hex similarity index 100% rename from tests/riscv/isa64/rv64ui-p-lw.hex rename to tests/riscv/isa/rv64ui-p-lw.hex diff --git a/tests/riscv/isa64/rv64ui-p-lwu.hex b/tests/riscv/isa/rv64ui-p-lwu.hex similarity index 100% rename from tests/riscv/isa64/rv64ui-p-lwu.hex rename to tests/riscv/isa/rv64ui-p-lwu.hex diff --git a/tests/riscv/isa64/rv64ui-p-or.hex b/tests/riscv/isa/rv64ui-p-or.hex similarity index 100% rename from tests/riscv/isa64/rv64ui-p-or.hex rename to tests/riscv/isa/rv64ui-p-or.hex diff --git a/tests/riscv/isa64/rv64ui-p-ori.hex b/tests/riscv/isa/rv64ui-p-ori.hex similarity index 100% rename from tests/riscv/isa64/rv64ui-p-ori.hex rename to tests/riscv/isa/rv64ui-p-ori.hex diff --git a/tests/riscv/isa64/rv64ui-p-sb.hex b/tests/riscv/isa/rv64ui-p-sb.hex similarity index 100% rename from tests/riscv/isa64/rv64ui-p-sb.hex rename to tests/riscv/isa/rv64ui-p-sb.hex diff --git a/tests/riscv/isa64/rv64ui-p-sd.hex b/tests/riscv/isa/rv64ui-p-sd.hex similarity index 100% rename from tests/riscv/isa64/rv64ui-p-sd.hex rename to tests/riscv/isa/rv64ui-p-sd.hex diff --git a/tests/riscv/isa64/rv64ui-p-sh.hex b/tests/riscv/isa/rv64ui-p-sh.hex similarity index 100% rename from tests/riscv/isa64/rv64ui-p-sh.hex rename to tests/riscv/isa/rv64ui-p-sh.hex diff --git a/tests/riscv/isa64/rv64ui-p-simple.hex b/tests/riscv/isa/rv64ui-p-simple.hex similarity index 100% rename from tests/riscv/isa64/rv64ui-p-simple.hex rename to tests/riscv/isa/rv64ui-p-simple.hex diff --git a/tests/riscv/isa64/rv64ui-p-sll.hex b/tests/riscv/isa/rv64ui-p-sll.hex similarity index 100% rename from tests/riscv/isa64/rv64ui-p-sll.hex rename to tests/riscv/isa/rv64ui-p-sll.hex diff --git a/tests/riscv/isa64/rv64ui-p-slli.hex b/tests/riscv/isa/rv64ui-p-slli.hex similarity index 100% rename from tests/riscv/isa64/rv64ui-p-slli.hex rename to tests/riscv/isa/rv64ui-p-slli.hex diff --git a/tests/riscv/isa64/rv64ui-p-slliw.hex b/tests/riscv/isa/rv64ui-p-slliw.hex similarity index 100% rename from tests/riscv/isa64/rv64ui-p-slliw.hex rename to tests/riscv/isa/rv64ui-p-slliw.hex diff --git a/tests/riscv/isa64/rv64ui-p-sllw.hex b/tests/riscv/isa/rv64ui-p-sllw.hex similarity index 100% rename from tests/riscv/isa64/rv64ui-p-sllw.hex rename to tests/riscv/isa/rv64ui-p-sllw.hex diff --git a/tests/riscv/isa64/rv64ui-p-slt.hex b/tests/riscv/isa/rv64ui-p-slt.hex similarity index 100% rename from tests/riscv/isa64/rv64ui-p-slt.hex rename to tests/riscv/isa/rv64ui-p-slt.hex diff --git a/tests/riscv/isa64/rv64ui-p-slti.hex b/tests/riscv/isa/rv64ui-p-slti.hex similarity index 100% rename from tests/riscv/isa64/rv64ui-p-slti.hex rename to tests/riscv/isa/rv64ui-p-slti.hex diff --git a/tests/riscv/isa64/rv64ui-p-sltiu.hex b/tests/riscv/isa/rv64ui-p-sltiu.hex similarity index 100% rename from tests/riscv/isa64/rv64ui-p-sltiu.hex rename to tests/riscv/isa/rv64ui-p-sltiu.hex diff --git a/tests/riscv/isa64/rv64ui-p-sltu.hex b/tests/riscv/isa/rv64ui-p-sltu.hex similarity index 100% rename from tests/riscv/isa64/rv64ui-p-sltu.hex rename to tests/riscv/isa/rv64ui-p-sltu.hex diff --git a/tests/riscv/isa64/rv64ui-p-sra.hex b/tests/riscv/isa/rv64ui-p-sra.hex similarity index 100% rename from tests/riscv/isa64/rv64ui-p-sra.hex rename to tests/riscv/isa/rv64ui-p-sra.hex diff --git a/tests/riscv/isa64/rv64ui-p-srai.hex b/tests/riscv/isa/rv64ui-p-srai.hex similarity index 100% rename from tests/riscv/isa64/rv64ui-p-srai.hex rename to tests/riscv/isa/rv64ui-p-srai.hex diff --git a/tests/riscv/isa64/rv64ui-p-sraiw.hex b/tests/riscv/isa/rv64ui-p-sraiw.hex similarity index 100% rename from tests/riscv/isa64/rv64ui-p-sraiw.hex rename to tests/riscv/isa/rv64ui-p-sraiw.hex diff --git a/tests/riscv/isa64/rv64ui-p-sraw.hex b/tests/riscv/isa/rv64ui-p-sraw.hex similarity index 100% rename from tests/riscv/isa64/rv64ui-p-sraw.hex rename to tests/riscv/isa/rv64ui-p-sraw.hex diff --git a/tests/riscv/isa64/rv64ui-p-srl.hex b/tests/riscv/isa/rv64ui-p-srl.hex similarity index 100% rename from tests/riscv/isa64/rv64ui-p-srl.hex rename to tests/riscv/isa/rv64ui-p-srl.hex diff --git a/tests/riscv/isa64/rv64ui-p-srli.hex b/tests/riscv/isa/rv64ui-p-srli.hex similarity index 100% rename from tests/riscv/isa64/rv64ui-p-srli.hex rename to tests/riscv/isa/rv64ui-p-srli.hex diff --git a/tests/riscv/isa64/rv64ui-p-srliw.hex b/tests/riscv/isa/rv64ui-p-srliw.hex similarity index 100% rename from tests/riscv/isa64/rv64ui-p-srliw.hex rename to tests/riscv/isa/rv64ui-p-srliw.hex diff --git a/tests/riscv/isa64/rv64ui-p-srlw.hex b/tests/riscv/isa/rv64ui-p-srlw.hex similarity index 100% rename from tests/riscv/isa64/rv64ui-p-srlw.hex rename to tests/riscv/isa/rv64ui-p-srlw.hex diff --git a/tests/riscv/isa64/rv64ui-p-sub.hex b/tests/riscv/isa/rv64ui-p-sub.hex similarity index 100% rename from tests/riscv/isa64/rv64ui-p-sub.hex rename to tests/riscv/isa/rv64ui-p-sub.hex diff --git a/tests/riscv/isa64/rv64ui-p-subw.hex b/tests/riscv/isa/rv64ui-p-subw.hex similarity index 100% rename from tests/riscv/isa64/rv64ui-p-subw.hex rename to tests/riscv/isa/rv64ui-p-subw.hex diff --git a/tests/riscv/isa64/rv64ui-p-sw.hex b/tests/riscv/isa/rv64ui-p-sw.hex similarity index 100% rename from tests/riscv/isa64/rv64ui-p-sw.hex rename to tests/riscv/isa/rv64ui-p-sw.hex diff --git a/tests/riscv/isa64/rv64ui-p-xor.hex b/tests/riscv/isa/rv64ui-p-xor.hex similarity index 100% rename from tests/riscv/isa64/rv64ui-p-xor.hex rename to tests/riscv/isa/rv64ui-p-xor.hex diff --git a/tests/riscv/isa64/rv64ui-p-xori.hex b/tests/riscv/isa/rv64ui-p-xori.hex similarity index 100% rename from tests/riscv/isa64/rv64ui-p-xori.hex rename to tests/riscv/isa/rv64ui-p-xori.hex diff --git a/tests/riscv/isa64/rv64um-p-div.hex b/tests/riscv/isa/rv64um-p-div.hex similarity index 100% rename from tests/riscv/isa64/rv64um-p-div.hex rename to tests/riscv/isa/rv64um-p-div.hex diff --git a/tests/riscv/isa64/rv64um-p-divu.hex b/tests/riscv/isa/rv64um-p-divu.hex similarity index 100% rename from tests/riscv/isa64/rv64um-p-divu.hex rename to tests/riscv/isa/rv64um-p-divu.hex diff --git a/tests/riscv/isa64/rv64um-p-divuw.hex b/tests/riscv/isa/rv64um-p-divuw.hex similarity index 100% rename from tests/riscv/isa64/rv64um-p-divuw.hex rename to tests/riscv/isa/rv64um-p-divuw.hex diff --git a/tests/riscv/isa64/rv64um-p-divw.hex b/tests/riscv/isa/rv64um-p-divw.hex similarity index 100% rename from tests/riscv/isa64/rv64um-p-divw.hex rename to tests/riscv/isa/rv64um-p-divw.hex diff --git a/tests/riscv/isa64/rv64um-p-mul.hex b/tests/riscv/isa/rv64um-p-mul.hex similarity index 100% rename from tests/riscv/isa64/rv64um-p-mul.hex rename to tests/riscv/isa/rv64um-p-mul.hex diff --git a/tests/riscv/isa64/rv64um-p-mulh.hex b/tests/riscv/isa/rv64um-p-mulh.hex similarity index 100% rename from tests/riscv/isa64/rv64um-p-mulh.hex rename to tests/riscv/isa/rv64um-p-mulh.hex diff --git a/tests/riscv/isa64/rv64um-p-mulhsu.hex b/tests/riscv/isa/rv64um-p-mulhsu.hex similarity index 100% rename from tests/riscv/isa64/rv64um-p-mulhsu.hex rename to tests/riscv/isa/rv64um-p-mulhsu.hex diff --git a/tests/riscv/isa64/rv64um-p-mulhu.hex b/tests/riscv/isa/rv64um-p-mulhu.hex similarity index 100% rename from tests/riscv/isa64/rv64um-p-mulhu.hex rename to tests/riscv/isa/rv64um-p-mulhu.hex diff --git a/tests/riscv/isa64/rv64um-p-mulw.hex b/tests/riscv/isa/rv64um-p-mulw.hex similarity index 100% rename from tests/riscv/isa64/rv64um-p-mulw.hex rename to tests/riscv/isa/rv64um-p-mulw.hex diff --git a/tests/riscv/isa64/rv64um-p-rem.hex b/tests/riscv/isa/rv64um-p-rem.hex similarity index 100% rename from tests/riscv/isa64/rv64um-p-rem.hex rename to tests/riscv/isa/rv64um-p-rem.hex diff --git a/tests/riscv/isa64/rv64um-p-remu.hex b/tests/riscv/isa/rv64um-p-remu.hex similarity index 100% rename from tests/riscv/isa64/rv64um-p-remu.hex rename to tests/riscv/isa/rv64um-p-remu.hex diff --git a/tests/riscv/isa64/rv64um-p-remuw.hex b/tests/riscv/isa/rv64um-p-remuw.hex similarity index 100% rename from tests/riscv/isa64/rv64um-p-remuw.hex rename to tests/riscv/isa/rv64um-p-remuw.hex diff --git a/tests/riscv/isa64/rv64um-p-remw.hex b/tests/riscv/isa/rv64um-p-remw.hex similarity index 100% rename from tests/riscv/isa64/rv64um-p-remw.hex rename to tests/riscv/isa/rv64um-p-remw.hex diff --git a/tests/riscv/isa64/Makefile b/tests/riscv/isa64/Makefile deleted file mode 100644 index 33ececfe..00000000 --- a/tests/riscv/isa64/Makefile +++ /dev/null @@ -1,32 +0,0 @@ -ALL_TESTS := $(wildcard *.hex) - -EXCLUDED_TESTS := rv64ud-p-move.hex - -I_TESTS := $(wildcard *ui-p-*.hex) -M_TESTS := $(wildcard *um-p-*.hex) -F_TESTS := $(wildcard *uf-p-*.hex) -D_TESTS := $(filter-out $(EXCLUDED_TESTS), $(wildcard *ud-p-*.hex)) - -TESTS := $(I_TESTS) $(M_TESTS) $(F_TESTS) $(D_TESTS) - -all: - -run-simx-i: - $(foreach test, $(I_TESTS), ../../../sim/simx/simx -r -a rv64i -c 1 -i $(test) || exit;) - -run-simx-m: - $(foreach test, $(M_TESTS), ../../../sim/simx/simx -r -a rv64im -c 1 -i $(test) || exit;) - -run-simx-f: - $(foreach test, $(F_TESTS), ../../../sim/simx/simx -r -a rv64imf -c 1 -i $(test) || exit;) - -run-simx-d: - $(foreach test, $(D_TESTS), ../../../sim/simx/simx -r -a rv64imfd -c 1 -i $(test) || exit;) - -run-simx: - $(foreach test, $(TESTS), ../../../sim/simx/simx -r -a rv64i -c 1 -i $(test) || exit;) - -run-rtlsim: - $(foreach test, $(TESTS), ../../../sim/rtlsim/rtlsim -r $(test) || exit;) - -clean: \ No newline at end of file