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project tests refactoring

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This commit is contained in:
Blaise Tine
2021-06-13 17:42:04 -07:00
parent 47c3234659
commit 03406c0a3f
631 changed files with 394471 additions and 653511 deletions
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44
simX/test_rv32f.sh
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@@ -4,35 +4,35 @@ set -e
make
echo ../benchmarks/riscv_tests/isa/rv32uf-p-fadd.hex
./simX -a rv32i -r -i ../benchmarks/riscv_tests/isa/rv32uf-p-fadd.hex
echo ../tests/riscv/isa/rv32uf-p-fadd.hex
./simX -a rv32i -r -i ../tests/riscv/isa/rv32uf-p-fadd.hex
echo ../benchmarks/riscv_tests/isa/rv32uf-p-fmadd.hex
./simX -a rv32i -r -i ../benchmarks/riscv_tests/isa/rv32uf-p-fmadd.hex
echo ../tests/riscv/isa/rv32uf-p-fmadd.hex
./simX -a rv32i -r -i ../tests/riscv/isa/rv32uf-p-fmadd.hex
echo ../benchmarks/riscv_tests/isa/rv32uf-p-fmin.hex
./simX -a rv32i -r -i ../benchmarks/riscv_tests/isa/rv32uf-p-fmin.hex
echo ../tests/riscv/isa/rv32uf-p-fmin.hex
./simX -a rv32i -r -i ../tests/riscv/isa/rv32uf-p-fmin.hex
echo ../benchmarks/riscv_tests/isa/rv32uf-p-fcmp.hex
./simX -a rv32i -r -i ../benchmarks/riscv_tests/isa/rv32uf-p-fcmp.hex
echo ../tests/riscv/isa/rv32uf-p-fcmp.hex
./simX -a rv32i -r -i ../tests/riscv/isa/rv32uf-p-fcmp.hex
echo ../benchmarks/riscv_tests/isa/rv32uf-p-fdst.hex
./simX -a rv32i -r -i ../benchmarks/riscv_tests/isa/rv32uf-p-ldst.hex
echo ../tests/riscv/isa/rv32uf-p-fdst.hex
./simX -a rv32i -r -i ../tests/riscv/isa/rv32uf-p-ldst.hex
echo ../benchmarks/riscv_tests/isa/rv32uf-p-fcvt.hex
./simX -a rv32i -r -i ../benchmarks/riscv_tests/isa/rv32uf-p-fcvt.hex
echo ../tests/riscv/isa/rv32uf-p-fcvt.hex
./simX -a rv32i -r -i ../tests/riscv/isa/rv32uf-p-fcvt.hex
echo ../benchmarks/riscv_tests/isa/rv32uf-p-fcvt_w.hex
./simX -a rv32i -r -i ../benchmarks/riscv_tests/isa/rv32uf-p-fcvt_w.hex
echo ../tests/riscv/isa/rv32uf-p-fcvt_w.hex
./simX -a rv32i -r -i ../tests/riscv/isa/rv32uf-p-fcvt_w.hex
echo ../benchmarks/riscv_tests/isa/rv32uf-p-move.hex
./simX -a rv32i -r -i ../benchmarks/riscv_tests/isa/rv32uf-p-move.hex
echo ../tests/riscv/isa/rv32uf-p-move.hex
./simX -a rv32i -r -i ../tests/riscv/isa/rv32uf-p-move.hex
echo ../benchmarks/riscv_tests/isa/rv32uf-p-recording.hex
./simX -a rv32i -r -i ../benchmarks/riscv_tests/isa/rv32uf-p-recoding.hex
echo ../tests/riscv/isa/rv32uf-p-recording.hex
./simX -a rv32i -r -i ../tests/riscv/isa/rv32uf-p-recoding.hex
echo ../benchmarks/riscv_tests/isa/rv32uf-p-fdiv.hex
./simX -a rv32i -r -i ../benchmarks/riscv_tests/isa/rv32uf-p-fdiv.hex
echo ../tests/riscv/isa/rv32uf-p-fdiv.hex
./simX -a rv32i -r -i ../tests/riscv/isa/rv32uf-p-fdiv.hex
echo ../benchmarks/riscv_tests/isa/rv32uf-p-fclass.hex
./simX -a rv32i -r -i ../benchmarks/riscv_tests/isa/rv32uf-p-fclass.hex
echo ../tests/riscv/isa/rv32uf-p-fclass.hex
./simX -a rv32i -r -i ../tests/riscv/isa/rv32uf-p-fclass.hex