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project tests refactoring

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This commit is contained in:
Blaise Tine
2021-06-13 17:42:04 -07:00
parent 47c3234659
commit 03406c0a3f
631 changed files with 394471 additions and 653511 deletions
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2
hw/rtl/VX_mem_unit.v
View File

@@ -282,7 +282,7 @@ module VX_mem_unit # (
.ADDR_WIDTH (`DMEM_ADDR_WIDTH),
.TAG_IN_WIDTH (`DMEM_TAG_WIDTH),
.BUFFERED_REQ (1),
.BUFFERED_RSP (1)
.BUFFERED_RSP (0)
) mem_arb (
.clk (clk),
.reset (reset),

116
hw/simulate/testbench.cpp
View File

@@ -39,69 +39,69 @@ int main(int argc, char **argv) {
if (argc == 1) {
#ifdef ALL_TESTS
std::string tests[] = {
"../../../benchmarks/riscv_tests/isa/rv32ui-p-add.hex",
"../../../benchmarks/riscv_tests/isa/rv32ui-p-addi.hex",
"../../../benchmarks/riscv_tests/isa/rv32ui-p-and.hex",
"../../../benchmarks/riscv_tests/isa/rv32ui-p-andi.hex",
"../../../benchmarks/riscv_tests/isa/rv32ui-p-auipc.hex",
"../../../benchmarks/riscv_tests/isa/rv32ui-p-beq.hex",
"../../../benchmarks/riscv_tests/isa/rv32ui-p-bge.hex",
"../../../benchmarks/riscv_tests/isa/rv32ui-p-bgeu.hex",
"../../../benchmarks/riscv_tests/isa/rv32ui-p-blt.hex",
"../../../benchmarks/riscv_tests/isa/rv32ui-p-bltu.hex",
"../../../benchmarks/riscv_tests/isa/rv32ui-p-bne.hex",
"../../../benchmarks/riscv_tests/isa/rv32ui-p-jal.hex",
"../../../benchmarks/riscv_tests/isa/rv32ui-p-jalr.hex",
"../../../benchmarks/riscv_tests/isa/rv32ui-p-lb.hex",
"../../../benchmarks/riscv_tests/isa/rv32ui-p-lbu.hex",
"../../../benchmarks/riscv_tests/isa/rv32ui-p-lh.hex",
"../../../benchmarks/riscv_tests/isa/rv32ui-p-lhu.hex",
"../../../benchmarks/riscv_tests/isa/rv32ui-p-lui.hex",
"../../../benchmarks/riscv_tests/isa/rv32ui-p-lw.hex",
"../../../benchmarks/riscv_tests/isa/rv32ui-p-or.hex",
"../../../benchmarks/riscv_tests/isa/rv32ui-p-ori.hex",
"../../../benchmarks/riscv_tests/isa/rv32ui-p-sb.hex",
"../../../benchmarks/riscv_tests/isa/rv32ui-p-sh.hex",
"../../../benchmarks/riscv_tests/isa/rv32ui-p-simple.hex",
"../../../benchmarks/riscv_tests/isa/rv32ui-p-sll.hex",
"../../../benchmarks/riscv_tests/isa/rv32ui-p-slli.hex",
"../../../benchmarks/riscv_tests/isa/rv32ui-p-slt.hex",
"../../../benchmarks/riscv_tests/isa/rv32ui-p-slti.hex",
"../../../benchmarks/riscv_tests/isa/rv32ui-p-sltiu.hex",
"../../../benchmarks/riscv_tests/isa/rv32ui-p-sltu.hex",
"../../../benchmarks/riscv_tests/isa/rv32ui-p-sra.hex",
"../../../benchmarks/riscv_tests/isa/rv32ui-p-srai.hex",
"../../../benchmarks/riscv_tests/isa/rv32ui-p-srl.hex",
"../../../benchmarks/riscv_tests/isa/rv32ui-p-srli.hex",
"../../../benchmarks/riscv_tests/isa/rv32ui-p-sub.hex",
"../../../benchmarks/riscv_tests/isa/rv32ui-p-sw.hex",
"../../../benchmarks/riscv_tests/isa/rv32ui-p-xor.hex",
"../../../benchmarks/riscv_tests/isa/rv32ui-p-xori.hex",
"../../../tests/riscv/isa/rv32ui-p-add.hex",
"../../../tests/riscv/isa/rv32ui-p-addi.hex",
"../../../tests/riscv/isa/rv32ui-p-and.hex",
"../../../tests/riscv/isa/rv32ui-p-andi.hex",
"../../../tests/riscv/isa/rv32ui-p-auipc.hex",
"../../../tests/riscv/isa/rv32ui-p-beq.hex",
"../../../tests/riscv/isa/rv32ui-p-bge.hex",
"../../../tests/riscv/isa/rv32ui-p-bgeu.hex",
"../../../tests/riscv/isa/rv32ui-p-blt.hex",
"../../../tests/riscv/isa/rv32ui-p-bltu.hex",
"../../../tests/riscv/isa/rv32ui-p-bne.hex",
"../../../tests/riscv/isa/rv32ui-p-jal.hex",
"../../../tests/riscv/isa/rv32ui-p-jalr.hex",
"../../../tests/riscv/isa/rv32ui-p-lb.hex",
"../../../tests/riscv/isa/rv32ui-p-lbu.hex",
"../../../tests/riscv/isa/rv32ui-p-lh.hex",
"../../../tests/riscv/isa/rv32ui-p-lhu.hex",
"../../../tests/riscv/isa/rv32ui-p-lui.hex",
"../../../tests/riscv/isa/rv32ui-p-lw.hex",
"../../../tests/riscv/isa/rv32ui-p-or.hex",
"../../../tests/riscv/isa/rv32ui-p-ori.hex",
"../../../tests/riscv/isa/rv32ui-p-sb.hex",
"../../../tests/riscv/isa/rv32ui-p-sh.hex",
"../../../tests/riscv/isa/rv32ui-p-simple.hex",
"../../../tests/riscv/isa/rv32ui-p-sll.hex",
"../../../tests/riscv/isa/rv32ui-p-slli.hex",
"../../../tests/riscv/isa/rv32ui-p-slt.hex",
"../../../tests/riscv/isa/rv32ui-p-slti.hex",
"../../../tests/riscv/isa/rv32ui-p-sltiu.hex",
"../../../tests/riscv/isa/rv32ui-p-sltu.hex",
"../../../tests/riscv/isa/rv32ui-p-sra.hex",
"../../../tests/riscv/isa/rv32ui-p-srai.hex",
"../../../tests/riscv/isa/rv32ui-p-srl.hex",
"../../../tests/riscv/isa/rv32ui-p-srli.hex",
"../../../tests/riscv/isa/rv32ui-p-sub.hex",
"../../../tests/riscv/isa/rv32ui-p-sw.hex",
"../../../tests/riscv/isa/rv32ui-p-xor.hex",
"../../../tests/riscv/isa/rv32ui-p-xori.hex",
#ifdef EXT_M_ENABLE
"../../../benchmarks/riscv_tests/isa/rv32um-p-div.hex",
"../../../benchmarks/riscv_tests/isa/rv32um-p-divu.hex",
"../../../benchmarks/riscv_tests/isa/rv32um-p-mul.hex",
"../../../benchmarks/riscv_tests/isa/rv32um-p-mulh.hex",
"../../../benchmarks/riscv_tests/isa/rv32um-p-mulhsu.hex",
"../../../benchmarks/riscv_tests/isa/rv32um-p-mulhu.hex",
"../../../benchmarks/riscv_tests/isa/rv32um-p-rem.hex",
"../../../benchmarks/riscv_tests/isa/rv32um-p-remu.hex",
"../../../tests/riscv/isa/rv32um-p-div.hex",
"../../../tests/riscv/isa/rv32um-p-divu.hex",
"../../../tests/riscv/isa/rv32um-p-mul.hex",
"../../../tests/riscv/isa/rv32um-p-mulh.hex",
"../../../tests/riscv/isa/rv32um-p-mulhsu.hex",
"../../../tests/riscv/isa/rv32um-p-mulhu.hex",
"../../../tests/riscv/isa/rv32um-p-rem.hex",
"../../../tests/riscv/isa/rv32um-p-remu.hex",
#endif
};
std::string tests_fp[] = {
#ifdef EXT_F_ENABLE
"../../../benchmarks/riscv_tests/isa/rv32uf-p-fadd.hex",
"../../../benchmarks/riscv_tests/isa/rv32uf-p-fmadd.hex",
"../../../benchmarks/riscv_tests/isa/rv32uf-p-fmin.hex",
"../../../benchmarks/riscv_tests/isa/rv32uf-p-fcmp.hex",
"../../../benchmarks/riscv_tests/isa/rv32uf-p-ldst.hex",
"../../../benchmarks/riscv_tests/isa/rv32uf-p-fcvt.hex",
"../../../benchmarks/riscv_tests/isa/rv32uf-p-fcvt_w.hex",
"../../../benchmarks/riscv_tests/isa/rv32uf-p-move.hex",
"../../../benchmarks/riscv_tests/isa/rv32uf-p-recoding.hex",
"../../../benchmarks/riscv_tests/isa/rv32uf-p-fdiv.hex",
"../../../benchmarks/riscv_tests/isa/rv32uf-p-fclass.hex",
"../../../tests/riscv/isa/rv32uf-p-fadd.hex",
"../../../tests/riscv/isa/rv32uf-p-fmadd.hex",
"../../../tests/riscv/isa/rv32uf-p-fmin.hex",
"../../../tests/riscv/isa/rv32uf-p-fcmp.hex",
"../../../tests/riscv/isa/rv32uf-p-ldst.hex",
"../../../tests/riscv/isa/rv32uf-p-fcvt.hex",
"../../../tests/riscv/isa/rv32uf-p-fcvt_w.hex",
"../../../tests/riscv/isa/rv32uf-p-move.hex",
"../../../tests/riscv/isa/rv32uf-p-recoding.hex",
"../../../tests/riscv/isa/rv32uf-p-fdiv.hex",
"../../../tests/riscv/isa/rv32uf-p-fclass.hex",
#endif
};
@@ -152,7 +152,7 @@ int main(int argc, char **argv) {
#else
char test[] = "../../../runtime/tests/simple/vx_simple.hex";
char test[] = "../../../tests/runtime/simple/vx_simple.hex";
std::cout << test << std::endl;

42
hw/syn/quartus/project.tcl
View File

@@ -41,29 +41,29 @@ set_global_assignment -name VERILOG_MACRO NDEBUG
set_global_assignment -name MESSAGE_DISABLE 16818
set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING ON
set_global_assignment -name OPTIMIZATION_TECHNIQUE SPEED
set_global_assignment -name OPTIMIZATION_MODE "AGGRESSIVE PERFORMANCE"
set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION ALWAYS
set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 2.0
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON
set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL MAXIMUM
set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS ON
set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION ON
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
#set_global_assignment -name OPTIMIZATION_TECHNIQUE SPEED
#set_global_assignment -name OPTIMIZATION_MODE "AGGRESSIVE PERFORMANCE"
#set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION ALWAYS
#set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 2.0
#set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
#set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
#set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON
#set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL MAXIMUM
#set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS ON
#set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION ON
#set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON
#set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
set_global_assignment -name USE_HIGH_SPEED_ADDER ON
set_global_assignment -name MUX_RESTRUCTURE ON
set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP ON
set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING "FORCE ALL TILES WITH FAILING TIMING PATHS TO HIGH SPEED"
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON
#set_global_assignment -name USE_HIGH_SPEED_ADDER ON
#set_global_assignment -name MUX_RESTRUCTURE ON
#set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP ON
#set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING "FORCE ALL TILES WITH FAILING TIMING PATHS TO HIGH SPEED"
#set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON
#set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100
set_global_assignment -name SEED 1
#set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
#set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100
#set_global_assignment -name SEED 1
switch $opts(family) {
"Arria 10" {