diff --git a/.codecov.yml b/.codecov.yml new file mode 100644 index 00000000..80ff2d61 --- /dev/null +++ b/.codecov.yml @@ -0,0 +1,3 @@ +ignore: + - "./examples/*" + - "./tests/*" diff --git a/.gitmodules b/.gitmodules new file mode 100644 index 00000000..dd60e98f --- /dev/null +++ b/.gitmodules @@ -0,0 +1,3 @@ +[submodule "hw/rtl/fp_cores/fpnew"] + path = hw/rtl/fp_cores/fpnew + url = https://github.com/pulp-platform/fpnew.git diff --git a/.travis.yml b/.travis.yml new file mode 100644 index 00000000..254f2567 --- /dev/null +++ b/.travis.yml @@ -0,0 +1,38 @@ +language: cpp +dist: bionic +os: linux +compiler: gcc +addons: + apt: + sources: + - ubuntu-toolchain-r-test + packages: + - build-essential + - valgrind + - verilator + - yosys + +install: + # TOOLCHAIN + - ci/toolchain_install.sh + - export RISCV_TOOLCHAIN_PATH=$PWD/riscv-gnu-toolchain + - export VERILATOR_ROOT=$PWD/verilator + - export PATH=$VERILATOR_ROOT/bin:$PATH + + # VORTEX + - git clone --recursive https://github.com/vortexgpgpu/vortex.git + - cd vortex + - make -j`nproc` + +script: + - ci/test_runtime.sh + - ci/test_driver.sh + - ci/test_riscv_isa.sh + - ci/test_opencl.sh + +after_success: + # Gather code coverage + - lcov --directory . --capture --output-file coverage.info # capture trace + - lcov --list coverage.info # trace report + # Upload coverage report + - bash <(curl -s https://codecov.io/bash) diff --git a/Makefile b/Makefile index c9fc76e2..9962e007 100644 --- a/Makefile +++ b/Makefile @@ -2,5 +2,12 @@ all: $(MAKE) -C hw $(MAKE) -C driver + $(MAKE) -C simX $(MAKE) -C runtime - $(MAKE) -C simX \ No newline at end of file + +clean: + $(MAKE) -C hw clean + $(MAKE) -C driver clean + $(MAKE) -C simX clean + $(MAKE) -C runtime clean + diff --git a/README.md b/README.md index e4f27ad7..71ba041e 100644 --- a/README.md +++ b/README.md @@ -1,3 +1,6 @@ +[![Build Status](https://travis-ci.org/vortexgpgpu/vortex.svg?branch=master)](https://travis-ci.org/vortexgpgpu/vortex) +[![codecov](https://codecov.io/gh/vortexgpgpu/vortex/branch/master/graph/badge.svg)](https://codecov.io/gh/vortexgpgpu/vortex) + # Vortex RISC-V GPGPU Vortex is a full-system RISCV-based GPGPU processor. @@ -37,7 +40,7 @@ Install development tools Install gnu-riscv-tools - $ export RISC_GNU_TOOLS_PATH=/opt/riscv-gnu-toolchain + $ export RISCV_TOOLCHAIN_PATH=/opt/riscv-gnu-toolchain $ sudo apt-get -y install \ binutils build-essential libtool texinfo \ @@ -51,7 +54,7 @@ Install gnu-riscv-tools $ git submodule update --init --recursive $ mkdir build $ cd build - $ ../configure --prefix=$RISC_GNU_TOOLS_PATH --with-arch=rv32im --with-abi=ilp32 + $ ../configure --prefix=$RISCV_TOOLCHAIN_PATH --with-arch=rv32im --with-abi=ilp32 $ make -j`nproc` $ make -j`nproc` build-qemu @@ -62,12 +65,12 @@ Install Verilator Install Vortex - $ git clone https://github.gatech.edu/casl/Vortex.git + $ git clone --recursive https://github.com/vortexgpgpu/vortex.git $ cd Vortex $ make -Quick Test running SGEMM kernel +Quick Test running OpenCL vecadd program - $ cd /Vortex/benchmarks/opencl/sgemm + $ cd /Vortex/benchmarks/opencl/vecadd $ make - $ make run + $ make run-rtlsim diff --git a/benchmarks/opencl/Makefile b/benchmarks/opencl/Makefile new file mode 100644 index 00000000..432461dd --- /dev/null +++ b/benchmarks/opencl/Makefile @@ -0,0 +1,30 @@ +all: + $(MAKE) -C vecadd + $(MAKE) -C sgemm + $(MAKE) -C saxpy + $(MAKE) -C sfilter + $(MAKE) -C nearn + $(MAKE) -C guassian + $(MAKE) -C bfs +run: + $(MAKE) -C vecadd run-rtlsim + $(MAKE) -C vecadd run-simx + $(MAKE) -C sgemm run-rtlsim + $(MAKE) -C sgemm run-simx + $(MAKE) -C saxpy run-rtlsim + $(MAKE) -C saxpy run-simx + $(MAKE) -C sfilter run-rtlsim + $(MAKE) -C nearn run-rtlsim + $(MAKE) -C nearn run-simx + $(MAKE) -C guassian run-rtlsim + $(MAKE) -C guassian run-simx + $(MAKE) -C bfs run-rtlsim + $(MAKE) -C bfs run-simx +clean: + $(MAKE) -C vecadd clean + $(MAKE) -C sgemm clean + $(MAKE) -C saxpy clean + $(MAKE) -C sfilter clean + $(MAKE) -C nearn clean + $(MAKE) -C guassian clean + $(MAKE) -C bfs clean diff --git a/benchmarks/opencl/lib/libOpenCL.so b/benchmarks/opencl/lib/libOpenCL.so deleted file mode 100644 index 522ea2bc..00000000 Binary files a/benchmarks/opencl/lib/libOpenCL.so and /dev/null differ diff --git a/benchmarks/opencl/lib/libOpenCL.so.2 b/benchmarks/opencl/lib/libOpenCL.so.2 deleted file mode 100644 index 522ea2bc..00000000 Binary files a/benchmarks/opencl/lib/libOpenCL.so.2 and /dev/null differ diff --git a/benchmarks/opencl/lib/libOpenCL.so.2.5.0 b/benchmarks/opencl/lib/libOpenCL.so.2.5.0 deleted file mode 100644 index 522ea2bc..00000000 Binary files a/benchmarks/opencl/lib/libOpenCL.so.2.5.0 and /dev/null differ diff --git a/benchmarks/opencl/runtime/lib/libOpenCL.so.2.5.0 b/benchmarks/opencl/runtime/lib/libOpenCL.so.2.5.0 index e5f1a692..e693c28f 100644 Binary files a/benchmarks/opencl/runtime/lib/libOpenCL.so.2.5.0 and b/benchmarks/opencl/runtime/lib/libOpenCL.so.2.5.0 differ diff --git a/benchmarks/opencl/sgemm/main.cc b/benchmarks/opencl/sgemm/main.cc index 2b72d1e5..bb37767a 100644 --- a/benchmarks/opencl/sgemm/main.cc +++ b/benchmarks/opencl/sgemm/main.cc @@ -34,25 +34,27 @@ #define NUM_DATA 64 -#define CL_CHECK(_expr) \ - do { \ - cl_int _err = _expr; \ - if (_err == CL_SUCCESS) \ - break; \ - fprintf(stderr, "OpenCL Error: '%s' returned %d!\n", #_expr, (int)_err); \ - abort(); \ - } while (0) +#define CL_CHECK(_expr) \ + do { \ + cl_int _err = _expr; \ + if (_err == CL_SUCCESS) \ + break; \ + printf("OpenCL Error: '%s' returned %d!\n", #_expr, (int)_err); \ + cleanup(); \ + exit(-1); \ + } while (0) -#define CL_CHECK_ERR(_expr) \ - ({ \ - cl_int _err = CL_INVALID_VALUE; \ - decltype(_expr) _ret = _expr; \ - if (_err != CL_SUCCESS) { \ - fprintf(stderr, "OpenCL Error: '%s' returned %d!\n", #_expr, (int)_err); \ - abort(); \ - } \ - _ret; \ - }) +#define CL_CHECK2(_expr) \ + ({ \ + cl_int _err = CL_INVALID_VALUE; \ + decltype(_expr) _ret = _expr; \ + if (_err != CL_SUCCESS) { \ + printf("OpenCL Error: '%s' returned %d!\n", #_expr, (int)_err); \ + cleanup(); \ + exit(-1); \ + } \ + _ret; \ + }) void pfn_notify(const char *errinfo, const void *private_info, size_t cb, void *user_data) { @@ -80,37 +82,34 @@ static int read_kernel_file(const char* filename, uint8_t** data, size_t* size) return 0; } +cl_device_id device_id = NULL; uint8_t *kernel_bin = NULL; +cl_context context = 0; +cl_kernel kernel = 0; +cl_command_queue queue = 0; +cl_program program = 0; +cl_mem memObjects[3] = {0, 0, 0}; /// // Cleanup any created OpenCL resources // -void Cleanup(cl_context context, cl_command_queue commandQueue, - cl_program program, cl_kernel kernel, cl_mem memObjects[3]) { +void cleanup() { for (int i = 0; i < 3; i++) { - if (memObjects[i] != 0) - clReleaseMemObject(memObjects[i]); + if (memObjects[i]) clReleaseMemObject(memObjects[i]); } - if (commandQueue != 0) - clReleaseCommandQueue(commandQueue); - - if (kernel != 0) - clReleaseKernel(kernel); - - if (program != 0) - clReleaseProgram(program); - - if (context != 0) - clReleaseContext(context); - + if (queue) clReleaseCommandQueue(queue); + if (kernel) clReleaseKernel(kernel); + if (program) clReleaseProgram(program); + if (context) clReleaseContext(context); + if (device_id) clReleaseDevice(device_id); + if (kernel_bin) free(kernel_bin); } int main(int argc, char **argv) { printf("enter demo main\n"); - cl_platform_id platform_id; - cl_device_id device_id; + cl_platform_id platform_id; size_t kernel_size; cl_int binary_status = 0; int i; @@ -122,17 +121,11 @@ int main(int argc, char **argv) { // Getting platform and device information CL_CHECK(clGetPlatformIDs(1, &platform_id, NULL)); CL_CHECK(clGetDeviceIDs(platform_id, CL_DEVICE_TYPE_DEFAULT, 1, &device_id, NULL)); - - cl_context context; - context = CL_CHECK_ERR( - clCreateContext(NULL, 1, &device_id, &pfn_notify, NULL, &_err)); - - cl_command_queue queue; - queue = CL_CHECK_ERR(clCreateCommandQueue(context, device_id, - CL_QUEUE_PROFILING_ENABLE, &_err)); - - cl_kernel kernel = 0; - cl_mem memObjects[3] = {0, 0, 0}; + + context = CL_CHECK2(clCreateContext(NULL, 1, &device_id, &pfn_notify, NULL, &_err)); + + queue = CL_CHECK2(clCreateCommandQueue(context, device_id, + CL_QUEUE_PROFILING_ENABLE, &_err)); // Create OpenCL program - first attempt to load cached binary. // If that is not available, then create the program from source @@ -140,15 +133,13 @@ int main(int argc, char **argv) { std::cout << "Attempting to create program from binary..." << std::endl; // cl_program program = CreateProgramFromBinary(context, device_id, // "kernel.cl.bin"); - cl_program program = CL_CHECK_ERR(clCreateProgramWithBinary( + program = CL_CHECK2(clCreateProgramWithBinary( context, 1, &device_id, &kernel_size, &kernel_bin, &binary_status, &_err)); if (program == NULL) { - std::cerr << "Failed to write program binary" << std::endl; - Cleanup(context, queue, program, kernel, memObjects); - return 1; - } else { - std::cout << "Read program from binary." << std::endl; - } + printf("clCreateProgramWithBinary() failed\n"); + cleanup(); + return -1; + } // Build program CL_CHECK(clBuildProgram(program, 1, &device_id, NULL, NULL, NULL)); @@ -156,19 +147,19 @@ int main(int argc, char **argv) { printf("attempting to create input buffer\n"); fflush(stdout); cl_mem input_bufferA; - input_bufferA = CL_CHECK_ERR( + input_bufferA = CL_CHECK2( clCreateBuffer(context, CL_MEM_READ_ONLY, sizeof(float) * NUM_DATA * NUM_DATA, NULL, &_err)); cl_mem input_bufferB; - input_bufferB = CL_CHECK_ERR( + input_bufferB = CL_CHECK2( clCreateBuffer(context, CL_MEM_READ_ONLY, sizeof(float) * NUM_DATA * NUM_DATA, NULL, &_err)); printf("attempting to create output buffer\n"); fflush(stdout); cl_mem output_buffer; - output_buffer = CL_CHECK_ERR( + output_buffer = CL_CHECK2( clCreateBuffer(context, CL_MEM_WRITE_ONLY, sizeof(float) * NUM_DATA * NUM_DATA, NULL, &_err)); @@ -180,7 +171,7 @@ int main(int argc, char **argv) { printf("attempting to create kernel\n"); fflush(stdout); - kernel = CL_CHECK_ERR(clCreateKernel(program, "sgemm", &_err)); + kernel = CL_CHECK2(clCreateKernel(program, "sgemm", &_err)); CL_CHECK(clSetKernelArg(kernel, 0, sizeof(input_bufferA), &input_bufferA)); CL_CHECK(clSetKernelArg(kernel, 1, sizeof(input_bufferB), &input_bufferB)); CL_CHECK(clSetKernelArg(kernel, 2, sizeof(output_buffer), &output_buffer)); @@ -209,7 +200,7 @@ int main(int argc, char **argv) { CL_CHECK(clEnqueueNDRangeKernel(queue, kernel, 3, NULL, global_work_size, local_work_size, 0, NULL, &kernel_completion)); - printf("Enqueue'd kerenel\n"); + printf("Enqueue'd kernel\n"); fflush(stdout); cl_ulong time_start, time_end; CL_CHECK(clWaitForEvents(1, &kernel_completion)); @@ -231,13 +222,8 @@ int main(int argc, char **argv) { } printf("\n"); - CL_CHECK(clReleaseMemObject(memObjects[0])); - CL_CHECK(clReleaseMemObject(memObjects[1])); - CL_CHECK(clReleaseMemObject(memObjects[2])); - - CL_CHECK(clReleaseKernel(kernel)); - CL_CHECK(clReleaseProgram(program)); - CL_CHECK(clReleaseContext(context)); + // Clean up + cleanup(); return 0; } diff --git a/benchmarks/opencl/sgemm/sgemm b/benchmarks/opencl/sgemm/sgemm index d75ee3bd..955b1c79 100755 Binary files a/benchmarks/opencl/sgemm/sgemm and b/benchmarks/opencl/sgemm/sgemm differ diff --git a/benchmarks/opencl/vecadd/main.cc b/benchmarks/opencl/vecadd/main.cc index 3b6f889b..96567db1 100644 --- a/benchmarks/opencl/vecadd/main.cc +++ b/benchmarks/opencl/vecadd/main.cc @@ -31,6 +31,7 @@ }) int exitcode = 0; +cl_device_id device_id = NULL; cl_context context = NULL; cl_command_queue commandQueue = NULL; cl_program program = NULL; @@ -72,6 +73,8 @@ static void cleanup() { if (b_memobj) clReleaseMemObject(b_memobj); if (c_memobj) clReleaseMemObject(c_memobj); if (context) clReleaseContext(context); + if (device_id) clReleaseDevice(device_id); + if (kernel_bin) free(kernel_bin); if (A) free(A); if (B) free(B); @@ -104,7 +107,6 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:= $(wildcard *-v-*.hex) +TESTS := $(filter-out $(VTESTS) rv32si-p-scall.hex rv32si-p-sbreak.hex rv32mi-p-breakpoint.hex rv32ud-p-fclass.hex rv32ua-p-amomax_w.hex rv32ua-p-amoxor_w.hex rv32ud-p-ldst.hex rv32ua-p-amoor_w.hex rv32mi-p-ma_addr.hex rv32ud-p-fdiv.hex rv32ud-p-fcmp.hex rv32mi-p-mcsr.hex rv32ua-p-amoswap_w.hex rv32mi-p-ma_fetch.hex rv32mi-p-csr.hex rv32ua-p-amoadd_w.hex rv32si-p-dirty.hex rv32ud-p-fcvt.hex rv32ui-p-fence_i.hex rv32si-p-csr.hex rv32mi-p-shamt.hex rv32ua-p-amomin_w.hex rv32ua-p-lrsc.hex rv32ud-p-fmadd.hex rv32ud-p-fadd.hex rv32si-p-wfi.hex rv32ua-p-amomaxu_w.hex rv32si-p-ma_fetch.hex rv32ud-p-fmin.hex rv32mi-p-illegal.hex rv32uc-p-rvc.hex rv32mi-p-sbreak.hex rv32ua-p-amominu_w.hex rv32ua-p-amoand_w.hex, $(TESTS)) + +run: + cd ../../../hw/simulate/obj_dir && ./VVortex -f $(foreach test,$(TESTS),../../../benchmarks/riscv_tests/isa/$(test)) diff --git a/benchmarks/riscv_tests/isa/rv32mi-p-breakpoint.hex b/benchmarks/riscv_tests/isa/rv32mi-p-breakpoint.hex new file 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100644 index 15f55d92..00000000 --- a/benchmarks/riscv_tests/rv32mi-p-csr.dump +++ /dev/null @@ -1,262 +0,0 @@ - -rv32mi-p-csr: file format elf32-littleriscv - - -Disassembly of section .text.init: - -80000000 <_start>: -80000000: 04c0006f j 8000004c - -80000004 : -80000004: 34202f73 csrr t5,mcause -80000008: 00800f93 li t6,8 -8000000c: 03ff0a63 beq t5,t6,80000040 -80000010: 00900f93 li t6,9 -80000014: 03ff0663 beq t5,t6,80000040 -80000018: 00b00f93 li t6,11 -8000001c: 03ff0263 beq t5,t6,80000040 -80000020: 00000f17 auipc t5,0x0 -80000024: 26cf0f13 addi t5,t5,620 # 8000028c -80000028: 000f0463 beqz t5,80000030 -8000002c: 000f0067 jr t5 -80000030: 34202f73 csrr t5,mcause -80000034: 000f5463 bgez t5,8000003c -80000038: 0040006f j 8000003c - -8000003c : -8000003c: 5391e193 ori gp,gp,1337 - -80000040 : -80000040: 00001f17 auipc t5,0x1 -80000044: fc3f2023 sw gp,-64(t5) # 80001000 -80000048: ff9ff06f j 80000040 - -8000004c : -8000004c: f1402573 csrr a0,mhartid -80000050: 00051063 bnez a0,80000050 -80000054: 00000297 auipc t0,0x0 -80000058: 01028293 addi t0,t0,16 # 80000064 -8000005c: 30529073 csrw mtvec,t0 -80000060: 18005073 csrwi satp,0 -80000064: 00000297 auipc t0,0x0 -80000068: 02028293 addi t0,t0,32 # 80000084 -8000006c: 30529073 csrw mtvec,t0 -80000070: 800002b7 lui t0,0x80000 -80000074: fff28293 addi t0,t0,-1 # 7fffffff <_end+0xffffdfef> -80000078: 3b029073 csrw pmpaddr0,t0 -8000007c: 01f00293 li t0,31 -80000080: 3a029073 csrw pmpcfg0,t0 -80000084: 00000297 auipc t0,0x0 -80000088: 01828293 addi t0,t0,24 # 8000009c -8000008c: 30529073 csrw mtvec,t0 -80000090: 30205073 csrwi medeleg,0 -80000094: 30305073 csrwi mideleg,0 -80000098: 30405073 csrwi mie,0 -8000009c: 00000193 li gp,0 -800000a0: 00000297 auipc t0,0x0 -800000a4: f6428293 addi t0,t0,-156 # 80000004 -800000a8: 30529073 csrw mtvec,t0 -800000ac: 00100513 li a0,1 -800000b0: 01f51513 slli a0,a0,0x1f -800000b4: 00054c63 bltz a0,800000cc -800000b8: 0ff0000f fence -800000bc: 00100193 li gp,1 -800000c0: 05d00893 li a7,93 -800000c4: 00000513 li a0,0 -800000c8: 00000073 ecall -800000cc: 80000297 auipc t0,0x80000 -800000d0: f3428293 addi t0,t0,-204 # 0 <_start-0x80000000> -800000d4: 00028e63 beqz t0,800000f0 -800000d8: 10529073 csrw stvec,t0 -800000dc: 0000b2b7 lui t0,0xb -800000e0: 10928293 addi t0,t0,265 # b109 <_start-0x7fff4ef7> -800000e4: 30229073 csrw medeleg,t0 -800000e8: 30202373 csrr t1,medeleg -800000ec: f46298e3 bne t0,t1,8000003c -800000f0: 30005073 csrwi mstatus,0 -800000f4: 00002537 lui a0,0x2 -800000f8: 80050513 addi a0,a0,-2048 # 1800 <_start-0x7fffe800> -800000fc: 30052073 csrs mstatus,a0 -80000100: 00000297 auipc t0,0x0 -80000104: 01428293 addi t0,t0,20 # 80000114 -80000108: 34129073 csrw mepc,t0 -8000010c: f1402573 csrr a0,mhartid -80000110: 30200073 mret -80000114: 3401d073 csrwi mscratch,3 - -80000118 : -80000118: 34002573 csrr a0,mscratch -8000011c: 00300e93 li t4,3 -80000120: 00200193 li gp,2 -80000124: 13d51c63 bne a0,t4,8000025c - -80000128 : -80000128: 3400f5f3 csrrci a1,mscratch,1 -8000012c: 00300e93 li t4,3 -80000130: 00300193 li gp,3 -80000134: 13d59463 bne a1,t4,8000025c - -80000138 : -80000138: 34026673 csrrsi a2,mscratch,4 -8000013c: 00200e93 li t4,2 -80000140: 00400193 li gp,4 -80000144: 11d61c63 bne a2,t4,8000025c - -80000148 : -80000148: 340156f3 csrrwi a3,mscratch,2 -8000014c: 00600e93 li t4,6 -80000150: 00500193 li gp,5 -80000154: 11d69463 bne a3,t4,8000025c - -80000158 : -80000158: 0bad2537 lui a0,0xbad2 -8000015c: dea50513 addi a0,a0,-534 # bad1dea <_start-0x7452e216> -80000160: 340515f3 csrrw a1,mscratch,a0 -80000164: 00200e93 li t4,2 -80000168: 00600193 li gp,6 -8000016c: 0fd59863 bne a1,t4,8000025c - -80000170 : -80000170: 00002537 lui a0,0x2 -80000174: dea50513 addi a0,a0,-534 # 1dea <_start-0x7fffe216> -80000178: 34053573 csrrc a0,mscratch,a0 -8000017c: 0bad2eb7 lui t4,0xbad2 -80000180: deae8e93 addi t4,t4,-534 # bad1dea <_start-0x7452e216> -80000184: 00700193 li gp,7 -80000188: 0dd51a63 bne a0,t4,8000025c - -8000018c : -8000018c: 0000c537 lui a0,0xc -80000190: eef50513 addi a0,a0,-273 # beef <_start-0x7fff4111> -80000194: 34052573 csrrs a0,mscratch,a0 -80000198: 0bad0eb7 lui t4,0xbad0 -8000019c: 00800193 li gp,8 -800001a0: 0bd51e63 bne a0,t4,8000025c - -800001a4 : -800001a4: 34002573 csrr a0,mscratch -800001a8: 0badceb7 lui t4,0xbadc -800001ac: eefe8e93 addi t4,t4,-273 # badbeef <_start-0x74524111> -800001b0: 00900193 li gp,9 -800001b4: 0bd51463 bne a0,t4,8000025c -800001b8: 30102573 csrr a0,misa -800001bc: 02057513 andi a0,a0,32 -800001c0: 02050863 beqz a0,800001f0 -800001c4: 000065b7 lui a1,0x6 -800001c8: 3005a073 csrs mstatus,a1 -800001cc: f0000053 fmv.w.x ft0,zero -800001d0: 3005b073 csrc mstatus,a1 -800001d4: 00002597 auipc a1,0x2 -800001d8: e2c58593 addi a1,a1,-468 # 80002000 - -800001dc : -800001dc: 0005a027 fsw ft0,0(a1) -800001e0: 0005a503 lw a0,0(a1) -800001e4: 00100e93 li t4,1 -800001e8: 00a00193 li gp,10 -800001ec: 07d51863 bne a0,t4,8000025c -800001f0: 30102573 csrr a0,misa -800001f4: 01455513 srli a0,a0,0x14 -800001f8: 00157513 andi a0,a0,1 -800001fc: 04050463 beqz a0,80000244 -80000200: 000022b7 lui t0,0x2 -80000204: 80028293 addi t0,t0,-2048 # 1800 <_start-0x7fffe800> -80000208: 3002b073 csrc mstatus,t0 -8000020c: 00000297 auipc t0,0x0 -80000210: 01028293 addi t0,t0,16 # 8000021c -80000214: 34129073 csrw mepc,t0 -80000218: 30200073 mret - -8000021c : -8000021c: 0ff00513 li a0,255 -80000220: c0001573 csrrw a0,cycle,zero -80000224: 0ff00e93 li t4,255 -80000228: 00b00193 li gp,11 -8000022c: 03d51863 bne a0,t4,8000025c - -80000230 : -80000230: 0ff00513 li a0,255 -80000234: 30002573 csrr a0,mstatus -80000238: 0ff00e93 li t4,255 -8000023c: 00c00193 li gp,12 -80000240: 01d51e63 bne a0,t4,8000025c - -80000244 : -80000244: 0ff0000f fence -80000248: 00100193 li gp,1 -8000024c: 05d00893 li a7,93 -80000250: 00000513 li a0,0 -80000254: 00000073 ecall -80000258: 02301063 bne zero,gp,80000278 - -8000025c : -8000025c: 0ff0000f fence -80000260: 00018063 beqz gp,80000260 -80000264: 00119193 slli gp,gp,0x1 -80000268: 0011e193 ori gp,gp,1 -8000026c: 05d00893 li a7,93 -80000270: 00018513 mv a0,gp -80000274: 00000073 ecall - -80000278 : -80000278: 0ff0000f fence -8000027c: 00100193 li gp,1 -80000280: 05d00893 li a7,93 -80000284: 00000513 li a0,0 -80000288: 00000073 ecall - -8000028c : -8000028c: 00900293 li t0,9 -80000290: 0051e663 bltu gp,t0,8000029c -80000294: 00b00293 li t0,11 -80000298: 0232f263 bgeu t0,gp,800002bc -8000029c: 342022f3 csrr t0,mcause -800002a0: 00800313 li t1,8 -800002a4: fa629ce3 bne t0,t1,8000025c -800002a8: 0ff0000f fence -800002ac: 00100193 li gp,1 -800002b0: 05d00893 li a7,93 -800002b4: 00000513 li a0,0 -800002b8: 00000073 ecall - -800002bc : -800002bc: 342022f3 csrr t0,mcause -800002c0: 00200313 li t1,2 -800002c4: f8629ce3 bne t0,t1,8000025c -800002c8: 341022f3 csrr t0,mepc -800002cc: 00428293 addi t0,t0,4 -800002d0: 34129073 csrw mepc,t0 -800002d4: 30200073 mret -800002d8: c0001073 unimp -800002dc: 0000 unimp -800002de: 0000 unimp -800002e0: 0000 unimp -800002e2: 0000 unimp -800002e4: 0000 unimp -800002e6: 0000 unimp -800002e8: 0000 unimp -800002ea: 0000 unimp -800002ec: 0000 unimp -800002ee: 0000 unimp -800002f0: 0000 unimp -800002f2: 0000 unimp -800002f4: 0000 unimp -800002f6: 0000 unimp -800002f8: 0000 unimp -800002fa: 0000 unimp -800002fc: 0000 unimp -800002fe: 0000 unimp -80000300: 0000 unimp -80000302: 0000 unimp - -Disassembly of section .data: - -80002000 : -80002000: 0001 nop -80002002: 0000 unimp -80002004: 0000 unimp -80002006: 0000 unimp -80002008: 0000 unimp -8000200a: 0000 unimp -8000200c: 0000 unimp -8000200e: 0000 unimp diff --git a/benchmarks/riscv_tests/rv32mi-p-illegal.dump b/benchmarks/riscv_tests/rv32mi-p-illegal.dump deleted file mode 100644 index 714d800c..00000000 --- a/benchmarks/riscv_tests/rv32mi-p-illegal.dump +++ /dev/null @@ -1,368 +0,0 @@ - -rv32mi-p-illegal: file format elf32-littleriscv - - -Disassembly of section .text.init: - -80000000 <_start>: -80000000: 04c0006f j 8000004c - -80000004 : -80000004: 34202f73 csrr t5,mcause -80000008: 00800f93 li t6,8 -8000000c: 03ff0a63 beq t5,t6,80000040 -80000010: 00900f93 li t6,9 -80000014: 03ff0663 beq t5,t6,80000040 -80000018: 00b00f93 li t6,11 -8000001c: 03ff0263 beq t5,t6,80000040 -80000020: 00000f17 auipc t5,0x0 -80000024: 2e0f0f13 addi t5,t5,736 # 80000300 -80000028: 000f0463 beqz t5,80000030 -8000002c: 000f0067 jr t5 -80000030: 34202f73 csrr t5,mcause -80000034: 000f5463 bgez t5,8000003c -80000038: 0040006f j 8000003c - -8000003c : -8000003c: 5391e193 ori gp,gp,1337 - -80000040 : -80000040: 00001f17 auipc t5,0x1 -80000044: fc3f2023 sw gp,-64(t5) # 80001000 -80000048: ff9ff06f j 80000040 - -8000004c : -8000004c: f1402573 csrr a0,mhartid -80000050: 00051063 bnez a0,80000050 -80000054: 00000297 auipc t0,0x0 -80000058: 01028293 addi t0,t0,16 # 80000064 -8000005c: 30529073 csrw mtvec,t0 -80000060: 18005073 csrwi satp,0 -80000064: 00000297 auipc t0,0x0 -80000068: 02028293 addi t0,t0,32 # 80000084 -8000006c: 30529073 csrw mtvec,t0 -80000070: 800002b7 lui t0,0x80000 -80000074: fff28293 addi t0,t0,-1 # 7fffffff <_end+0xffffdfff> -80000078: 3b029073 csrw pmpaddr0,t0 -8000007c: 01f00293 li t0,31 -80000080: 3a029073 csrw pmpcfg0,t0 -80000084: 00000297 auipc t0,0x0 -80000088: 01828293 addi t0,t0,24 # 8000009c -8000008c: 30529073 csrw mtvec,t0 -80000090: 30205073 csrwi medeleg,0 -80000094: 30305073 csrwi mideleg,0 -80000098: 30405073 csrwi mie,0 -8000009c: 00000193 li gp,0 -800000a0: 00000297 auipc t0,0x0 -800000a4: f6428293 addi t0,t0,-156 # 80000004 -800000a8: 30529073 csrw mtvec,t0 -800000ac: 00100513 li a0,1 -800000b0: 01f51513 slli a0,a0,0x1f -800000b4: 00054c63 bltz a0,800000cc -800000b8: 0ff0000f fence -800000bc: 00100193 li gp,1 -800000c0: 05d00893 li a7,93 -800000c4: 00000513 li a0,0 -800000c8: 00000073 ecall -800000cc: 80000297 auipc t0,0x80000 -800000d0: f3428293 addi t0,t0,-204 # 0 <_start-0x80000000> -800000d4: 00028e63 beqz t0,800000f0 -800000d8: 10529073 csrw stvec,t0 -800000dc: 0000b2b7 lui t0,0xb -800000e0: 10928293 addi t0,t0,265 # b109 <_start-0x7fff4ef7> -800000e4: 30229073 csrw medeleg,t0 -800000e8: 30202373 csrr t1,medeleg -800000ec: f46298e3 bne t0,t1,8000003c -800000f0: 30005073 csrwi mstatus,0 -800000f4: 00002537 lui a0,0x2 -800000f8: 80050513 addi a0,a0,-2048 # 1800 <_start-0x7fffe800> -800000fc: 30052073 csrs mstatus,a0 -80000100: 00000297 auipc t0,0x0 -80000104: 01428293 addi t0,t0,20 # 80000114 -80000108: 34129073 csrw mepc,t0 -8000010c: f1402573 csrr a0,mhartid -80000110: 30200073 mret -80000114: 00200193 li gp,2 - -80000118 : -80000118: 0000 unimp -8000011a: 0000 unimp -8000011c: 0f40006f j 80000210 -80000120: 000022b7 lui t0,0x2 -80000124: 80028293 addi t0,t0,-2048 # 1800 <_start-0x7fffe800> -80000128: 3002b073 csrc mstatus,t0 -8000012c: 00001337 lui t1,0x1 -80000130: 80030313 addi t1,t1,-2048 # 800 <_start-0x7ffff800> -80000134: 30032073 csrs mstatus,t1 -80000138: 300023f3 csrr t2,mstatus -8000013c: 0053f3b3 and t2,t2,t0 -80000140: 0e731663 bne t1,t2,8000022c - -80000144 : -80000144: 34415073 csrwi mip,2 -80000148: 30415073 csrwi mie,2 -8000014c: 00000297 auipc t0,0x0 -80000150: 1b528293 addi t0,t0,437 # 80000301 -80000154: 30529473 csrrw s0,mtvec,t0 -80000158: 305022f3 csrr t0,mtvec -8000015c: 0012f293 andi t0,t0,1 -80000160: 00028663 beqz t0,8000016c -80000164: 30046073 csrsi mstatus,8 -80000168: 0000006f j 80000168 - -8000016c : -8000016c: 30541073 csrw mtvec,s0 -80000170: 30315073 csrwi mideleg,2 -80000174: 00000297 auipc t0,0x0 -80000178: 02828293 addi t0,t0,40 # 8000019c -8000017c: 34129073 csrw mepc,t0 -80000180: 000022b7 lui t0,0x2 -80000184: 80028293 addi t0,t0,-2048 # 1800 <_start-0x7fffe800> -80000188: 3002b073 csrc mstatus,t0 -8000018c: 00001337 lui t1,0x1 -80000190: 80030313 addi t1,t1,-2048 # 800 <_start-0x7ffff800> -80000194: 30032073 csrs mstatus,t1 -80000198: 30200073 mret -8000019c: 10500073 wfi - -800001a0 : -800001a0: 0000 unimp -800001a2: 0000 unimp -800001a4: 06c0006f j 80000210 - -800001a8 : -800001a8: 10500073 wfi -800001ac: 0640006f j 80000210 -800001b0: 12000073 sfence.vma -800001b4: 180022f3 csrr t0,satp - -800001b8 : -800001b8: 0000 unimp -800001ba: 0000 unimp -800001bc: 0540006f j 80000210 - -800001c0 : -800001c0: 12000073 sfence.vma -800001c4: 04c0006f j 80000210 - -800001c8 : -800001c8: 180022f3 csrr t0,satp -800001cc: 0440006f j 80000210 -800001d0: 00000297 auipc t0,0x0 -800001d4: 02028293 addi t0,t0,32 # 800001f0 -800001d8: 14129073 csrw sepc,t0 -800001dc: 10000293 li t0,256 -800001e0: 1002a073 csrs sstatus,t0 -800001e4: 02000293 li t0,32 -800001e8: 1002b073 csrc sstatus,t0 -800001ec: 10200073 sret - -800001f0 : -800001f0: 0000 unimp -800001f2: 0000 unimp -800001f4: 01c0006f j 80000210 -800001f8: 00000297 auipc t0,0x0 -800001fc: 01028293 addi t0,t0,16 # 80000208 -80000200: 14129073 csrw sepc,t0 - -80000204 : -80000204: 10200073 sret -80000208: 0080006f j 80000210 -8000020c: 02301063 bne zero,gp,8000022c - -80000210 : -80000210: 0ff0000f fence -80000214: 00018063 beqz gp,80000214 -80000218: 00119193 slli gp,gp,0x1 -8000021c: 0011e193 ori gp,gp,1 -80000220: 05d00893 li a7,93 -80000224: 00018513 mv a0,gp -80000228: 00000073 ecall - -8000022c : -8000022c: 0ff0000f fence -80000230: 00100193 li gp,1 -80000234: 05d00893 li a7,93 -80000238: 00000513 li a0,0 -8000023c: 00000073 ecall -80000240: 00000013 nop -80000244: 00000013 nop -80000248: 00000013 nop -8000024c: 00000013 nop -80000250: 00000013 nop -80000254: 00000013 nop -80000258: 00000013 nop -8000025c: 00000013 nop -80000260: 00000013 nop -80000264: 00000013 nop -80000268: 00000013 nop -8000026c: 00000013 nop -80000270: 00000013 nop -80000274: 00000013 nop -80000278: 00000013 nop -8000027c: 00000013 nop -80000280: 00000013 nop -80000284: 00000013 nop -80000288: 00000013 nop -8000028c: 00000013 nop -80000290: 00000013 nop -80000294: 00000013 nop -80000298: 00000013 nop -8000029c: 00000013 nop -800002a0: 00000013 nop -800002a4: 00000013 nop -800002a8: 00000013 nop -800002ac: 00000013 nop -800002b0: 00000013 nop -800002b4: 00000013 nop -800002b8: 00000013 nop -800002bc: 00000013 nop -800002c0: 00000013 nop -800002c4: 00000013 nop -800002c8: 00000013 nop -800002cc: 00000013 nop -800002d0: 00000013 nop -800002d4: 00000013 nop -800002d8: 00000013 nop -800002dc: 00000013 nop -800002e0: 00000013 nop -800002e4: 00000013 nop -800002e8: 00000013 nop -800002ec: 00000013 nop -800002f0: 00000013 nop -800002f4: 00000013 nop -800002f8: 00000013 nop -800002fc: 00000013 nop - -80000300 : -80000300: 0400006f j 80000340 -80000304: e69ff06f j 8000016c -80000308: f09ff06f j 80000210 -8000030c: f05ff06f j 80000210 -80000310: f01ff06f j 80000210 -80000314: efdff06f j 80000210 -80000318: ef9ff06f j 80000210 -8000031c: ef5ff06f j 80000210 -80000320: ef1ff06f j 80000210 -80000324: eedff06f j 80000210 -80000328: ee9ff06f j 80000210 -8000032c: ee5ff06f j 80000210 -80000330: ee1ff06f j 80000210 -80000334: eddff06f j 80000210 -80000338: ed9ff06f j 80000210 -8000033c: ed5ff06f j 80000210 - -80000340 : -80000340: 00200313 li t1,2 -80000344: 342022f3 csrr t0,mcause -80000348: ec6294e3 bne t0,t1,80000210 -8000034c: 341022f3 csrr t0,mepc -80000350: 343023f3 csrr t2,mtval -80000354: 00038e63 beqz t2,80000370 -80000358: 0002d303 lhu t1,0(t0) -8000035c: 0063c3b3 xor t2,t2,t1 -80000360: 0022d303 lhu t1,2(t0) -80000364: 01031313 slli t1,t1,0x10 -80000368: 0063c3b3 xor t2,t2,t1 -8000036c: ea0392e3 bnez t2,80000210 -80000370: 00000317 auipc t1,0x0 -80000374: da830313 addi t1,t1,-600 # 80000118 -80000378: 04628e63 beq t0,t1,800003d4 -8000037c: 00000317 auipc t1,0x0 -80000380: e2430313 addi t1,t1,-476 # 800001a0 -80000384: 04628e63 beq t0,t1,800003e0 -80000388: 00000317 auipc t1,0x0 -8000038c: e2030313 addi t1,t1,-480 # 800001a8 -80000390: 04628263 beq t0,t1,800003d4 -80000394: 00000317 auipc t1,0x0 -80000398: e2430313 addi t1,t1,-476 # 800001b8 -8000039c: 04628863 beq t0,t1,800003ec -800003a0: 00000317 auipc t1,0x0 -800003a4: e2030313 addi t1,t1,-480 # 800001c0 -800003a8: 02628663 beq t0,t1,800003d4 -800003ac: 00000317 auipc t1,0x0 -800003b0: e1c30313 addi t1,t1,-484 # 800001c8 -800003b4: 02628063 beq t0,t1,800003d4 -800003b8: 00000317 auipc t1,0x0 -800003bc: e3830313 addi t1,t1,-456 # 800001f0 -800003c0: 02628c63 beq t0,t1,800003f8 -800003c4: 00000317 auipc t1,0x0 -800003c8: e4030313 addi t1,t1,-448 # 80000204 -800003cc: 02628c63 beq t0,t1,80000404 -800003d0: e41ff06f j 80000210 -800003d4: 00828293 addi t0,t0,8 -800003d8: 34129073 csrw mepc,t0 -800003dc: 30200073 mret -800003e0: 00200337 lui t1,0x200 -800003e4: 30032073 csrs mstatus,t1 -800003e8: fedff06f j 800003d4 -800003ec: 00100337 lui t1,0x100 -800003f0: 30032073 csrs mstatus,t1 -800003f4: fe1ff06f j 800003d4 -800003f8: 00400337 lui t1,0x400 -800003fc: 30032073 csrs mstatus,t1 -80000400: fd5ff06f j 800003d4 -80000404: fd1ff06f j 800003d4 -80000408: c0001073 unimp -8000040c: 0000 unimp -8000040e: 0000 unimp -80000410: 0000 unimp -80000412: 0000 unimp -80000414: 0000 unimp -80000416: 0000 unimp -80000418: 0000 unimp -8000041a: 0000 unimp -8000041c: 0000 unimp -8000041e: 0000 unimp -80000420: 0000 unimp -80000422: 0000 unimp -80000424: 0000 unimp -80000426: 0000 unimp -80000428: 0000 unimp -8000042a: 0000 unimp -8000042c: 0000 unimp -8000042e: 0000 unimp -80000430: 0000 unimp -80000432: 0000 unimp -80000434: 0000 unimp -80000436: 0000 unimp -80000438: 0000 unimp -8000043a: 0000 unimp -8000043c: 0000 unimp -8000043e: 0000 unimp -80000440: 0000 unimp -80000442: 0000 unimp -80000444: 0000 unimp -80000446: 0000 unimp -80000448: 0000 unimp -8000044a: 0000 unimp -8000044c: 0000 unimp -8000044e: 0000 unimp -80000450: 0000 unimp -80000452: 0000 unimp -80000454: 0000 unimp -80000456: 0000 unimp -80000458: 0000 unimp -8000045a: 0000 unimp -8000045c: 0000 unimp -8000045e: 0000 unimp -80000460: 0000 unimp -80000462: 0000 unimp -80000464: 0000 unimp -80000466: 0000 unimp -80000468: 0000 unimp -8000046a: 0000 unimp -8000046c: 0000 unimp -8000046e: 0000 unimp -80000470: 0000 unimp -80000472: 0000 unimp -80000474: 0000 unimp -80000476: 0000 unimp -80000478: 0000 unimp -8000047a: 0000 unimp -8000047c: 0000 unimp -8000047e: 0000 unimp -80000480: 0000 unimp -80000482: 0000 unimp -80000484: 0000 unimp -80000486: 0000 unimp diff --git a/benchmarks/riscv_tests/rv32mi-p-sbreak.dump b/benchmarks/riscv_tests/rv32mi-p-sbreak.dump deleted file mode 100644 index 0ceef528..00000000 --- a/benchmarks/riscv_tests/rv32mi-p-sbreak.dump +++ /dev/null @@ -1,123 +0,0 @@ - -rv32mi-p-sbreak: file format elf32-littleriscv - - -Disassembly of section .text.init: - -80000000 <_start>: -80000000: 04c0006f j 8000004c - -80000004 : -80000004: 34202f73 csrr t5,mcause -80000008: 00800f93 li t6,8 -8000000c: 03ff0a63 beq t5,t6,80000040 -80000010: 00900f93 li t6,9 -80000014: 03ff0663 beq t5,t6,80000040 -80000018: 00b00f93 li t6,11 -8000001c: 03ff0263 beq t5,t6,80000040 -80000020: 00000f17 auipc t5,0x0 -80000024: 134f0f13 addi t5,t5,308 # 80000154 -80000028: 000f0463 beqz t5,80000030 -8000002c: 000f0067 jr t5 -80000030: 34202f73 csrr t5,mcause -80000034: 000f5463 bgez t5,8000003c -80000038: 0040006f j 8000003c - -8000003c : -8000003c: 5391e193 ori gp,gp,1337 - -80000040 : -80000040: 00001f17 auipc t5,0x1 -80000044: fc3f2023 sw gp,-64(t5) # 80001000 -80000048: ff9ff06f j 80000040 - -8000004c : -8000004c: f1402573 csrr a0,mhartid -80000050: 00051063 bnez a0,80000050 -80000054: 00000297 auipc t0,0x0 -80000058: 01028293 addi t0,t0,16 # 80000064 -8000005c: 30529073 csrw mtvec,t0 -80000060: 18005073 csrwi satp,0 -80000064: 00000297 auipc t0,0x0 -80000068: 02028293 addi t0,t0,32 # 80000084 -8000006c: 30529073 csrw mtvec,t0 -80000070: 800002b7 lui t0,0x80000 -80000074: fff28293 addi t0,t0,-1 # 7fffffff <_end+0xffffdfff> -80000078: 3b029073 csrw pmpaddr0,t0 -8000007c: 01f00293 li t0,31 -80000080: 3a029073 csrw pmpcfg0,t0 -80000084: 00000297 auipc t0,0x0 -80000088: 01828293 addi t0,t0,24 # 8000009c -8000008c: 30529073 csrw mtvec,t0 -80000090: 30205073 csrwi medeleg,0 -80000094: 30305073 csrwi mideleg,0 -80000098: 30405073 csrwi mie,0 -8000009c: 00000193 li gp,0 -800000a0: 00000297 auipc t0,0x0 -800000a4: f6428293 addi t0,t0,-156 # 80000004 -800000a8: 30529073 csrw mtvec,t0 -800000ac: 00100513 li a0,1 -800000b0: 01f51513 slli a0,a0,0x1f -800000b4: 00054c63 bltz a0,800000cc -800000b8: 0ff0000f fence -800000bc: 00100193 li gp,1 -800000c0: 05d00893 li a7,93 -800000c4: 00000513 li a0,0 -800000c8: 00000073 ecall -800000cc: 80000297 auipc t0,0x80000 -800000d0: f3428293 addi t0,t0,-204 # 0 <_start-0x80000000> -800000d4: 00028e63 beqz t0,800000f0 -800000d8: 10529073 csrw stvec,t0 -800000dc: 0000b2b7 lui t0,0xb -800000e0: 10928293 addi t0,t0,265 # b109 <_start-0x7fff4ef7> -800000e4: 30229073 csrw medeleg,t0 -800000e8: 30202373 csrr t1,medeleg -800000ec: f46298e3 bne t0,t1,8000003c -800000f0: 30005073 csrwi mstatus,0 -800000f4: 00002537 lui a0,0x2 -800000f8: 80050513 addi a0,a0,-2048 # 1800 <_start-0x7fffe800> -800000fc: 30052073 csrs mstatus,a0 -80000100: 00000297 auipc t0,0x0 -80000104: 01428293 addi t0,t0,20 # 80000114 -80000108: 34129073 csrw mepc,t0 -8000010c: f1402573 csrr a0,mhartid -80000110: 30200073 mret -80000114: 00200193 li gp,2 - -80000118 : -80000118: 00100073 ebreak -8000011c: 0080006f j 80000124 -80000120: 02301063 bne zero,gp,80000140 - -80000124 : -80000124: 0ff0000f fence -80000128: 00018063 beqz gp,80000128 -8000012c: 00119193 slli gp,gp,0x1 -80000130: 0011e193 ori gp,gp,1 -80000134: 05d00893 li a7,93 -80000138: 00018513 mv a0,gp -8000013c: 00000073 ecall - -80000140 : -80000140: 0ff0000f fence -80000144: 00100193 li gp,1 -80000148: 05d00893 li a7,93 -8000014c: 00000513 li a0,0 -80000150: 00000073 ecall - -80000154 : -80000154: 00300313 li t1,3 -80000158: 342022f3 csrr t0,mcause -8000015c: fc6294e3 bne t0,t1,80000124 -80000160: 00000317 auipc t1,0x0 -80000164: fb830313 addi t1,t1,-72 # 80000118 -80000168: 341022f3 csrr t0,mepc -8000016c: fa629ce3 bne t0,t1,80000124 -80000170: fd1ff06f j 80000140 -80000174: c0001073 unimp -80000178: 0000 unimp -8000017a: 0000 unimp -8000017c: 0000 unimp -8000017e: 0000 unimp -80000180: 0000 unimp -80000182: 0000 unimp diff --git a/benchmarks/riscv_tests/rv32mi-p-scall.dump b/benchmarks/riscv_tests/rv32mi-p-scall.dump deleted file mode 100644 index a76dc80a..00000000 --- a/benchmarks/riscv_tests/rv32mi-p-scall.dump +++ /dev/null @@ -1,140 +0,0 @@ - -rv32mi-p-scall: file format elf32-littleriscv - - -Disassembly of section .text.init: - -80000000 <_start>: -80000000: 04c0006f j 8000004c - -80000004 : -80000004: 34202f73 csrr t5,mcause -80000008: 00800f93 li t6,8 -8000000c: 03ff0a63 beq t5,t6,80000040 -80000010: 00900f93 li t6,9 -80000014: 03ff0663 beq t5,t6,80000040 -80000018: 00b00f93 li t6,11 -8000001c: 03ff0263 beq t5,t6,80000040 -80000020: 00000f17 auipc t5,0x0 -80000024: 174f0f13 addi t5,t5,372 # 80000194 -80000028: 000f0463 beqz t5,80000030 -8000002c: 000f0067 jr t5 -80000030: 34202f73 csrr t5,mcause -80000034: 000f5463 bgez t5,8000003c -80000038: 0040006f j 8000003c - -8000003c : -8000003c: 5391e193 ori gp,gp,1337 - -80000040 : -80000040: 00001f17 auipc t5,0x1 -80000044: fc3f2023 sw gp,-64(t5) # 80001000 -80000048: ff9ff06f j 80000040 - -8000004c : -8000004c: f1402573 csrr a0,mhartid -80000050: 00051063 bnez a0,80000050 -80000054: 00000297 auipc t0,0x0 -80000058: 01028293 addi t0,t0,16 # 80000064 -8000005c: 30529073 csrw mtvec,t0 -80000060: 18005073 csrwi satp,0 -80000064: 00000297 auipc t0,0x0 -80000068: 02028293 addi t0,t0,32 # 80000084 -8000006c: 30529073 csrw mtvec,t0 -80000070: 800002b7 lui t0,0x80000 -80000074: fff28293 addi t0,t0,-1 # 7fffffff <_end+0xffffdfff> -80000078: 3b029073 csrw pmpaddr0,t0 -8000007c: 01f00293 li t0,31 -80000080: 3a029073 csrw pmpcfg0,t0 -80000084: 00000297 auipc t0,0x0 -80000088: 01828293 addi t0,t0,24 # 8000009c -8000008c: 30529073 csrw mtvec,t0 -80000090: 30205073 csrwi medeleg,0 -80000094: 30305073 csrwi mideleg,0 -80000098: 30405073 csrwi mie,0 -8000009c: 00000193 li gp,0 -800000a0: 00000297 auipc t0,0x0 -800000a4: f6428293 addi t0,t0,-156 # 80000004 -800000a8: 30529073 csrw mtvec,t0 -800000ac: 00100513 li a0,1 -800000b0: 01f51513 slli a0,a0,0x1f -800000b4: 00054c63 bltz a0,800000cc -800000b8: 0ff0000f fence -800000bc: 00100193 li gp,1 -800000c0: 05d00893 li a7,93 -800000c4: 00000513 li a0,0 -800000c8: 00000073 ecall -800000cc: 80000297 auipc t0,0x80000 -800000d0: f3428293 addi t0,t0,-204 # 0 <_start-0x80000000> -800000d4: 00028e63 beqz t0,800000f0 -800000d8: 10529073 csrw stvec,t0 -800000dc: 0000b2b7 lui t0,0xb -800000e0: 10928293 addi t0,t0,265 # b109 <_start-0x7fff4ef7> -800000e4: 30229073 csrw medeleg,t0 -800000e8: 30202373 csrr t1,medeleg -800000ec: f46298e3 bne t0,t1,8000003c -800000f0: 30005073 csrwi mstatus,0 -800000f4: 00002537 lui a0,0x2 -800000f8: 80050513 addi a0,a0,-2048 # 1800 <_start-0x7fffe800> -800000fc: 30052073 csrs mstatus,a0 -80000100: 00000297 auipc t0,0x0 -80000104: 01428293 addi t0,t0,20 # 80000114 -80000108: 34129073 csrw mepc,t0 -8000010c: f1402573 csrr a0,mhartid -80000110: 30200073 mret -80000114: 00200193 li gp,2 -80000118: 00800313 li t1,8 -8000011c: 000022b7 lui t0,0x2 -80000120: 80028293 addi t0,t0,-2048 # 1800 <_start-0x7fffe800> -80000124: 3002b073 csrc mstatus,t0 -80000128: 300023f3 csrr t2,mstatus -8000012c: 0072f2b3 and t0,t0,t2 -80000130: 00028463 beqz t0,80000138 -80000134: 00b00313 li t1,11 -80000138: 000022b7 lui t0,0x2 -8000013c: 80028293 addi t0,t0,-2048 # 1800 <_start-0x7fffe800> -80000140: 3002b073 csrc mstatus,t0 -80000144: 00000297 auipc t0,0x0 -80000148: 01028293 addi t0,t0,16 # 80000154 -8000014c: 34129073 csrw mepc,t0 -80000150: 30200073 mret -80000154: 00100193 li gp,1 - -80000158 : -80000158: 00000073 ecall -8000015c: 0080006f j 80000164 -80000160: 02301063 bne zero,gp,80000180 - -80000164 : -80000164: 0ff0000f fence -80000168: 00018063 beqz gp,80000168 -8000016c: 00119193 slli gp,gp,0x1 -80000170: 0011e193 ori gp,gp,1 -80000174: 05d00893 li a7,93 -80000178: 00018513 mv a0,gp -8000017c: 00000073 ecall - -80000180 : -80000180: 0ff0000f fence -80000184: 00100193 li gp,1 -80000188: 05d00893 li a7,93 -8000018c: 00000513 li a0,0 -80000190: 00000073 ecall - -80000194 : -80000194: 342022f3 csrr t0,mcause -80000198: fc6296e3 bne t0,t1,80000164 -8000019c: 00000397 auipc t2,0x0 -800001a0: fbc38393 addi t2,t2,-68 # 80000158 -800001a4: 341022f3 csrr t0,mepc -800001a8: fa729ee3 bne t0,t2,80000164 -800001ac: fd5ff06f j 80000180 -800001b0: c0001073 unimp -800001b4: 0000 unimp -800001b6: 0000 unimp -800001b8: 0000 unimp -800001ba: 0000 unimp -800001bc: 0000 unimp -800001be: 0000 unimp -800001c0: 0000 unimp -800001c2: 0000 unimp diff --git a/benchmarks/riscv_tests/rv32ui-p-add.dump b/benchmarks/riscv_tests/rv32ui-p-add.dump deleted file mode 100644 index d1926a50..00000000 --- a/benchmarks/riscv_tests/rv32ui-p-add.dump +++ /dev/null @@ -1,504 +0,0 @@ - -rv32ui-p-add: file format elf32-littleriscv - - -Disassembly of section .text.init: - -80000000 <_start>: -80000000: 04c0006f j 8000004c - -80000004 : -80000004: 34202f73 csrr t5,mcause -80000008: 00800f93 li t6,8 -8000000c: 03ff0a63 beq t5,t6,80000040 -80000010: 00900f93 li t6,9 -80000014: 03ff0663 beq t5,t6,80000040 -80000018: 00b00f93 li t6,11 -8000001c: 03ff0263 beq t5,t6,80000040 -80000020: 80000f17 auipc t5,0x80000 -80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> -80000028: 000f0463 beqz t5,80000030 -8000002c: 000f0067 jr t5 -80000030: 34202f73 csrr t5,mcause -80000034: 000f5463 bgez t5,8000003c -80000038: 0040006f j 8000003c - -8000003c : -8000003c: 5391e193 ori gp,gp,1337 - -80000040 : -80000040: 00001f17 auipc t5,0x1 -80000044: fc3f2023 sw gp,-64(t5) # 80001000 -80000048: ff9ff06f j 80000040 - -8000004c : -8000004c: f1402573 csrr a0,mhartid -80000050: 00051063 bnez a0,80000050 -80000054: 00000297 auipc t0,0x0 -80000058: 01028293 addi t0,t0,16 # 80000064 -8000005c: 30529073 csrw mtvec,t0 -80000060: 18005073 csrwi satp,0 -80000064: 00000297 auipc t0,0x0 -80000068: 02028293 addi t0,t0,32 # 80000084 -8000006c: 30529073 csrw mtvec,t0 -80000070: 800002b7 lui t0,0x80000 -80000074: fff28293 addi t0,t0,-1 # 7fffffff <_end+0xffffdfff> -80000078: 3b029073 csrw pmpaddr0,t0 -8000007c: 01f00293 li t0,31 -80000080: 3a029073 csrw pmpcfg0,t0 -80000084: 00000297 auipc t0,0x0 -80000088: 01828293 addi t0,t0,24 # 8000009c -8000008c: 30529073 csrw mtvec,t0 -80000090: 30205073 csrwi medeleg,0 -80000094: 30305073 csrwi mideleg,0 -80000098: 30405073 csrwi mie,0 -8000009c: 00000193 li gp,0 -800000a0: 00000297 auipc t0,0x0 -800000a4: f6428293 addi t0,t0,-156 # 80000004 -800000a8: 30529073 csrw mtvec,t0 -800000ac: 00100513 li a0,1 -800000b0: 01f51513 slli a0,a0,0x1f -800000b4: 00054c63 bltz a0,800000cc -800000b8: 0ff0000f fence -800000bc: 00100193 li gp,1 -800000c0: 05d00893 li a7,93 -800000c4: 00000513 li a0,0 -800000c8: 00000073 ecall -800000cc: 80000297 auipc t0,0x80000 -800000d0: f3428293 addi t0,t0,-204 # 0 <_start-0x80000000> -800000d4: 00028e63 beqz t0,800000f0 -800000d8: 10529073 csrw stvec,t0 -800000dc: 0000b2b7 lui t0,0xb -800000e0: 10928293 addi t0,t0,265 # b109 <_start-0x7fff4ef7> -800000e4: 30229073 csrw medeleg,t0 -800000e8: 30202373 csrr t1,medeleg -800000ec: f46298e3 bne t0,t1,8000003c -800000f0: 30005073 csrwi mstatus,0 -800000f4: 00000297 auipc t0,0x0 -800000f8: 01428293 addi t0,t0,20 # 80000108 -800000fc: 34129073 csrw mepc,t0 -80000100: f1402573 csrr a0,mhartid -80000104: 30200073 mret - -80000108 : -80000108: 00000093 li ra,0 -8000010c: 00000113 li sp,0 -80000110: 00208733 add a4,ra,sp -80000114: 00000e93 li t4,0 -80000118: 00200193 li gp,2 -8000011c: 4dd71663 bne a4,t4,800005e8 - -80000120 : -80000120: 00100093 li ra,1 -80000124: 00100113 li sp,1 -80000128: 00208733 add a4,ra,sp -8000012c: 00200e93 li t4,2 -80000130: 00300193 li gp,3 -80000134: 4bd71a63 bne a4,t4,800005e8 - -80000138 : -80000138: 00300093 li ra,3 -8000013c: 00700113 li sp,7 -80000140: 00208733 add a4,ra,sp -80000144: 00a00e93 li t4,10 -80000148: 00400193 li gp,4 -8000014c: 49d71e63 bne a4,t4,800005e8 - -80000150 : -80000150: 00000093 li ra,0 -80000154: ffff8137 lui sp,0xffff8 -80000158: 00208733 add a4,ra,sp -8000015c: ffff8eb7 lui t4,0xffff8 -80000160: 00500193 li gp,5 -80000164: 49d71263 bne a4,t4,800005e8 - -80000168 : -80000168: 800000b7 lui ra,0x80000 -8000016c: 00000113 li sp,0 -80000170: 00208733 add a4,ra,sp -80000174: 80000eb7 lui t4,0x80000 -80000178: 00600193 li gp,6 -8000017c: 47d71663 bne a4,t4,800005e8 - -80000180 : -80000180: 800000b7 lui ra,0x80000 -80000184: ffff8137 lui sp,0xffff8 -80000188: 00208733 add a4,ra,sp -8000018c: 7fff8eb7 lui t4,0x7fff8 -80000190: 00700193 li gp,7 -80000194: 45d71a63 bne a4,t4,800005e8 - -80000198 : -80000198: 00000093 li ra,0 -8000019c: 00008137 lui sp,0x8 -800001a0: fff10113 addi sp,sp,-1 # 7fff <_start-0x7fff8001> -800001a4: 00208733 add a4,ra,sp -800001a8: 00008eb7 lui t4,0x8 -800001ac: fffe8e93 addi t4,t4,-1 # 7fff <_start-0x7fff8001> -800001b0: 00800193 li gp,8 -800001b4: 43d71a63 bne a4,t4,800005e8 - -800001b8 : -800001b8: 800000b7 lui ra,0x80000 -800001bc: fff08093 addi ra,ra,-1 # 7fffffff <_end+0xffffdfff> -800001c0: 00000113 li sp,0 -800001c4: 00208733 add a4,ra,sp -800001c8: 80000eb7 lui t4,0x80000 -800001cc: fffe8e93 addi t4,t4,-1 # 7fffffff <_end+0xffffdfff> -800001d0: 00900193 li gp,9 -800001d4: 41d71a63 bne a4,t4,800005e8 - -800001d8 : -800001d8: 800000b7 lui ra,0x80000 -800001dc: fff08093 addi ra,ra,-1 # 7fffffff <_end+0xffffdfff> -800001e0: 00008137 lui sp,0x8 -800001e4: fff10113 addi sp,sp,-1 # 7fff <_start-0x7fff8001> -800001e8: 00208733 add a4,ra,sp -800001ec: 80008eb7 lui t4,0x80008 -800001f0: ffee8e93 addi t4,t4,-2 # 80007ffe <_end+0x5ffe> -800001f4: 00a00193 li gp,10 -800001f8: 3fd71863 bne a4,t4,800005e8 - -800001fc : -800001fc: 800000b7 lui ra,0x80000 -80000200: 00008137 lui sp,0x8 -80000204: fff10113 addi sp,sp,-1 # 7fff <_start-0x7fff8001> -80000208: 00208733 add a4,ra,sp -8000020c: 80008eb7 lui t4,0x80008 -80000210: fffe8e93 addi t4,t4,-1 # 80007fff <_end+0x5fff> -80000214: 00b00193 li gp,11 -80000218: 3dd71863 bne a4,t4,800005e8 - -8000021c : -8000021c: 800000b7 lui ra,0x80000 -80000220: fff08093 addi ra,ra,-1 # 7fffffff <_end+0xffffdfff> -80000224: ffff8137 lui sp,0xffff8 -80000228: 00208733 add a4,ra,sp -8000022c: 7fff8eb7 lui t4,0x7fff8 -80000230: fffe8e93 addi t4,t4,-1 # 7fff7fff <_start-0x8001> -80000234: 00c00193 li gp,12 -80000238: 3bd71863 bne a4,t4,800005e8 - -8000023c : -8000023c: 00000093 li ra,0 -80000240: fff00113 li sp,-1 -80000244: 00208733 add a4,ra,sp -80000248: fff00e93 li t4,-1 -8000024c: 00d00193 li gp,13 -80000250: 39d71c63 bne a4,t4,800005e8 - -80000254 : -80000254: fff00093 li ra,-1 -80000258: 00100113 li sp,1 -8000025c: 00208733 add a4,ra,sp -80000260: 00000e93 li t4,0 -80000264: 00e00193 li gp,14 -80000268: 39d71063 bne a4,t4,800005e8 - -8000026c : -8000026c: fff00093 li ra,-1 -80000270: fff00113 li sp,-1 -80000274: 00208733 add a4,ra,sp -80000278: ffe00e93 li t4,-2 -8000027c: 00f00193 li gp,15 -80000280: 37d71463 bne a4,t4,800005e8 - -80000284 : -80000284: 00100093 li ra,1 -80000288: 80000137 lui sp,0x80000 -8000028c: fff10113 addi sp,sp,-1 # 7fffffff <_end+0xffffdfff> -80000290: 00208733 add a4,ra,sp -80000294: 80000eb7 lui t4,0x80000 -80000298: 01000193 li gp,16 -8000029c: 35d71663 bne a4,t4,800005e8 - -800002a0 : -800002a0: 00d00093 li ra,13 -800002a4: 00b00113 li sp,11 -800002a8: 002080b3 add ra,ra,sp -800002ac: 01800e93 li t4,24 -800002b0: 01100193 li gp,17 -800002b4: 33d09a63 bne ra,t4,800005e8 - -800002b8 : -800002b8: 00e00093 li ra,14 -800002bc: 00b00113 li sp,11 -800002c0: 00208133 add sp,ra,sp -800002c4: 01900e93 li t4,25 -800002c8: 01200193 li gp,18 -800002cc: 31d11e63 bne sp,t4,800005e8 - -800002d0 : -800002d0: 00d00093 li ra,13 -800002d4: 001080b3 add ra,ra,ra -800002d8: 01a00e93 li t4,26 -800002dc: 01300193 li gp,19 -800002e0: 31d09463 bne ra,t4,800005e8 - -800002e4 : -800002e4: 00000213 li tp,0 -800002e8: 00d00093 li ra,13 -800002ec: 00b00113 li sp,11 -800002f0: 00208733 add a4,ra,sp -800002f4: 00070313 mv t1,a4 -800002f8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -800002fc: 00200293 li t0,2 -80000300: fe5214e3 bne tp,t0,800002e8 -80000304: 01800e93 li t4,24 -80000308: 01400193 li gp,20 -8000030c: 2dd31e63 bne t1,t4,800005e8 - -80000310 : -80000310: 00000213 li tp,0 -80000314: 00e00093 li ra,14 -80000318: 00b00113 li sp,11 -8000031c: 00208733 add a4,ra,sp -80000320: 00000013 nop -80000324: 00070313 mv t1,a4 -80000328: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -8000032c: 00200293 li t0,2 -80000330: fe5212e3 bne tp,t0,80000314 -80000334: 01900e93 li t4,25 -80000338: 01500193 li gp,21 -8000033c: 2bd31663 bne t1,t4,800005e8 - -80000340 : -80000340: 00000213 li tp,0 -80000344: 00f00093 li ra,15 -80000348: 00b00113 li sp,11 -8000034c: 00208733 add a4,ra,sp -80000350: 00000013 nop -80000354: 00000013 nop -80000358: 00070313 mv t1,a4 -8000035c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000360: 00200293 li t0,2 -80000364: fe5210e3 bne tp,t0,80000344 -80000368: 01a00e93 li t4,26 -8000036c: 01600193 li gp,22 -80000370: 27d31c63 bne t1,t4,800005e8 - -80000374 : -80000374: 00000213 li tp,0 -80000378: 00d00093 li ra,13 -8000037c: 00b00113 li sp,11 -80000380: 00208733 add a4,ra,sp -80000384: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000388: 00200293 li t0,2 -8000038c: fe5216e3 bne tp,t0,80000378 -80000390: 01800e93 li t4,24 -80000394: 01700193 li gp,23 -80000398: 25d71863 bne a4,t4,800005e8 - -8000039c : -8000039c: 00000213 li tp,0 -800003a0: 00e00093 li ra,14 -800003a4: 00b00113 li sp,11 -800003a8: 00000013 nop -800003ac: 00208733 add a4,ra,sp -800003b0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -800003b4: 00200293 li t0,2 -800003b8: fe5214e3 bne tp,t0,800003a0 -800003bc: 01900e93 li t4,25 -800003c0: 01800193 li gp,24 -800003c4: 23d71263 bne a4,t4,800005e8 - -800003c8 : -800003c8: 00000213 li tp,0 -800003cc: 00f00093 li ra,15 -800003d0: 00b00113 li sp,11 -800003d4: 00000013 nop -800003d8: 00000013 nop -800003dc: 00208733 add a4,ra,sp -800003e0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -800003e4: 00200293 li t0,2 -800003e8: fe5212e3 bne tp,t0,800003cc -800003ec: 01a00e93 li t4,26 -800003f0: 01900193 li gp,25 -800003f4: 1fd71a63 bne a4,t4,800005e8 - -800003f8 : -800003f8: 00000213 li tp,0 -800003fc: 00d00093 li ra,13 -80000400: 00000013 nop -80000404: 00b00113 li sp,11 -80000408: 00208733 add a4,ra,sp -8000040c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000410: 00200293 li t0,2 -80000414: fe5214e3 bne tp,t0,800003fc -80000418: 01800e93 li t4,24 -8000041c: 01a00193 li gp,26 -80000420: 1dd71463 bne a4,t4,800005e8 - -80000424 : -80000424: 00000213 li tp,0 -80000428: 00e00093 li ra,14 -8000042c: 00000013 nop -80000430: 00b00113 li sp,11 -80000434: 00000013 nop -80000438: 00208733 add a4,ra,sp -8000043c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000440: 00200293 li t0,2 -80000444: fe5212e3 bne tp,t0,80000428 -80000448: 01900e93 li t4,25 -8000044c: 01b00193 li gp,27 -80000450: 19d71c63 bne a4,t4,800005e8 - -80000454 : -80000454: 00000213 li tp,0 -80000458: 00f00093 li ra,15 -8000045c: 00000013 nop -80000460: 00000013 nop -80000464: 00b00113 li sp,11 -80000468: 00208733 add a4,ra,sp -8000046c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000470: 00200293 li t0,2 -80000474: fe5212e3 bne tp,t0,80000458 -80000478: 01a00e93 li t4,26 -8000047c: 01c00193 li gp,28 -80000480: 17d71463 bne a4,t4,800005e8 - -80000484 : -80000484: 00000213 li tp,0 -80000488: 00b00113 li sp,11 -8000048c: 00d00093 li ra,13 -80000490: 00208733 add a4,ra,sp -80000494: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000498: 00200293 li t0,2 -8000049c: fe5216e3 bne tp,t0,80000488 -800004a0: 01800e93 li t4,24 -800004a4: 01d00193 li gp,29 -800004a8: 15d71063 bne a4,t4,800005e8 - -800004ac : -800004ac: 00000213 li tp,0 -800004b0: 00b00113 li sp,11 -800004b4: 00e00093 li ra,14 -800004b8: 00000013 nop -800004bc: 00208733 add a4,ra,sp -800004c0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -800004c4: 00200293 li t0,2 -800004c8: fe5214e3 bne tp,t0,800004b0 -800004cc: 01900e93 li t4,25 -800004d0: 01e00193 li gp,30 -800004d4: 11d71a63 bne a4,t4,800005e8 - -800004d8 : -800004d8: 00000213 li tp,0 -800004dc: 00b00113 li sp,11 -800004e0: 00f00093 li ra,15 -800004e4: 00000013 nop -800004e8: 00000013 nop -800004ec: 00208733 add a4,ra,sp -800004f0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -800004f4: 00200293 li t0,2 -800004f8: fe5212e3 bne tp,t0,800004dc -800004fc: 01a00e93 li t4,26 -80000500: 01f00193 li gp,31 -80000504: 0fd71263 bne a4,t4,800005e8 - -80000508 : -80000508: 00000213 li tp,0 -8000050c: 00b00113 li sp,11 -80000510: 00000013 nop -80000514: 00d00093 li ra,13 -80000518: 00208733 add a4,ra,sp -8000051c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000520: 00200293 li t0,2 -80000524: fe5214e3 bne tp,t0,8000050c -80000528: 01800e93 li t4,24 -8000052c: 02000193 li gp,32 -80000530: 0bd71c63 bne a4,t4,800005e8 - -80000534 : -80000534: 00000213 li tp,0 -80000538: 00b00113 li sp,11 -8000053c: 00000013 nop -80000540: 00e00093 li ra,14 -80000544: 00000013 nop -80000548: 00208733 add a4,ra,sp -8000054c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000550: 00200293 li t0,2 -80000554: fe5212e3 bne tp,t0,80000538 -80000558: 01900e93 li t4,25 -8000055c: 02100193 li gp,33 -80000560: 09d71463 bne a4,t4,800005e8 - -80000564 : -80000564: 00000213 li tp,0 -80000568: 00b00113 li sp,11 -8000056c: 00000013 nop -80000570: 00000013 nop -80000574: 00f00093 li ra,15 -80000578: 00208733 add a4,ra,sp -8000057c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000580: 00200293 li t0,2 -80000584: fe5212e3 bne tp,t0,80000568 -80000588: 01a00e93 li t4,26 -8000058c: 02200193 li gp,34 -80000590: 05d71c63 bne a4,t4,800005e8 - -80000594 : -80000594: 00f00093 li ra,15 -80000598: 00100133 add sp,zero,ra -8000059c: 00f00e93 li t4,15 -800005a0: 02300193 li gp,35 -800005a4: 05d11263 bne sp,t4,800005e8 - -800005a8 : -800005a8: 02000093 li ra,32 -800005ac: 00008133 add sp,ra,zero -800005b0: 02000e93 li t4,32 -800005b4: 02400193 li gp,36 -800005b8: 03d11863 bne sp,t4,800005e8 - -800005bc : -800005bc: 000000b3 add ra,zero,zero -800005c0: 00000e93 li t4,0 -800005c4: 02500193 li gp,37 -800005c8: 03d09063 bne ra,t4,800005e8 - -800005cc : -800005cc: 01000093 li ra,16 -800005d0: 01e00113 li sp,30 -800005d4: 00208033 add zero,ra,sp -800005d8: 00000e93 li t4,0 -800005dc: 02600193 li gp,38 -800005e0: 01d01463 bne zero,t4,800005e8 -800005e4: 02301063 bne zero,gp,80000604 - -800005e8 : -800005e8: 0ff0000f fence -800005ec: 00018063 beqz gp,800005ec -800005f0: 00119193 slli gp,gp,0x1 -800005f4: 0011e193 ori gp,gp,1 -800005f8: 05d00893 li a7,93 -800005fc: 00018513 mv a0,gp -80000600: 00000073 ecall - -80000604 : -80000604: 0ff0000f fence -80000608: 00100193 li gp,1 -8000060c: 05d00893 li a7,93 -80000610: 00000513 li a0,0 -80000614: 00000073 ecall -80000618: c0001073 unimp -8000061c: 0000 unimp -8000061e: 0000 unimp -80000620: 0000 unimp -80000622: 0000 unimp -80000624: 0000 unimp -80000626: 0000 unimp -80000628: 0000 unimp -8000062a: 0000 unimp -8000062c: 0000 unimp -8000062e: 0000 unimp -80000630: 0000 unimp -80000632: 0000 unimp -80000634: 0000 unimp -80000636: 0000 unimp -80000638: 0000 unimp -8000063a: 0000 unimp -8000063c: 0000 unimp -8000063e: 0000 unimp -80000640: 0000 unimp -80000642: 0000 unimp diff --git a/benchmarks/riscv_tests/rv32ui-p-add.hex b/benchmarks/riscv_tests/rv32ui-p-add.hex deleted file mode 100644 index 10331773..00000000 --- a/benchmarks/riscv_tests/rv32ui-p-add.hex +++ /dev/null @@ -1,101 +0,0 @@ -:0200000480007A -:100000006F00C004732F2034930F8000630AFF0336 -:10001000930F90006306FF03930FB0006302FF038A -:10002000170F0080130F0FFE63040F0067000F000F -:10003000732F203463540F006F004000136E9E53E3 -:10004000171F00002320CFFD6FF09FFF732540F1A5 -:100050006310050073251030635805000F00F00F82 -:10006000130E100073000000130E00009702000032 -:10007000938282F973905230735020307350303035 -:1000800073504030970200809382C2F7638C020065 -:10009000739052109302B01A739022307323203061 -:1000A000E39E62F873500030970200009382420191 -:1000B00073901234732540F17300203093000000D8 -:1000C00013010000B3812000930E0000130E2000E6 -:1000D0006396D14D9300100013011000B3812000EE -:1000E000930E2000130E3000639AD14B9300300022 -:1000F00013017000B3812000930EA000130E400086 -:10010000639ED149930000003781FFFFB381200037 -:10011000B78EFFFF130E50006392D149B7000080E5 -:1001200013010000B3812000B70E0080130E6000A1 -:100130006396D147B70000803781FFFFB38120006D -:10014000B78EFF7F130E7000639AD14593000000B5 -:10015000378100001301F1FFB3812000B78E00004A -:10016000938EFEFF130E8000639AD143B700008088 -:100170009380F0FF13010000B3812000B70E0080D0 -:10018000938EFEFF130E9000639AD141B70000805A -:100190009380F0FF378100001301F1FFB38120004D -:1001A000B78E0080938EEEFF130EA0006398D13FB0 -:1001B000B7000080378100001301F1FFB3812000F8 -:1001C000B78E0080938EFEFF130EB0006398D13D72 -:1001D000B70000809380F0FF3781FFFFB3812000DC -:1001E000B78EFF7F938EFEFF130EC0006398D13B46 -:1001F000930000001301F0FFB3812000930EF0FF85 -:10020000130ED000639CD1399300F0FF130110004E -:10021000B3812000930E0000130EE0006390D139EB -:100220009300F0FF1301F0FFB3812000930EE0FF75 -:10023000130EF0006394D137930010003701008053 -:100240001301F1FFB3812000B70E0080130E0001EF -:100250006396D1359300D0001301B000B380200025 -:10026000930E8001130E1001639AD0339300E000C7 -:100270001301B00033812000930E9001130E200172 -:10028000631ED1319300D000B3801000930EA00103 -:10029000130E30016394D031130200009300D0009C -:1002A0001301B000B3812000138301001302120078 -:1002B00093022000E31452FE930E8001130E4001BE -:1002C000631ED32D130200009300E0001301B00061 -:1002D000B3812000130000001383010013021200F9 -:1002E00093022000E31252FE930E9001130E500170 -:1002F0006316D32B130200009300F0001301B0002B -:10030000B3812000130000001300000013830100DC -:100310001302120093022000E31052FE930EA0017C -:10032000130E6001631CD327130200009300D0005A -:100330001301B000B38120001302120093022000C9 -:10034000E31652FE930E8001130E70016398D125BF -:10035000130200009300E0001301B000130000003E -:10036000B38120001302120093022000E31452FE16 -:10037000930E9001130E80016392D12313020000AB -:100380009300F0001301B000130000001300000000 -:10039000B38120001302120093022000E31252FEE8 -:1003A000930EA001130E9001639AD11F1302000057 -:1003B0009300D000130000001301B000B3812000AF -:1003C0001302120093022000E31452FE930E8001E8 -:1003D000130EA0016394D11D130200009300E000EE -:1003E000130000001301B00013000000B3812000CF -:1003F0001302120093022000E31252FE930E9001AA -:10040000130EB001639CD119130200009300F00099 -:1004100013000000130000001301B000B38120009E -:100420001302120093022000E31252FE930EA00169 -:10043000130EC0016394D117130200001301B00022 -:100440009300D000B3812000130212009302200019 -:10045000E31652FE930E8001130ED0016390D11566 -:10046000130200001301B0009300E000130000002D -:10047000B38120001302120093022000E31452FE05 -:10048000930E9001130EE001639AD1111302000044 -:100490001301B0009300F0001300000013000000EF -:1004A000B38120001302120093022000E31252FED7 -:1004B000930EA001130EF0016392D10F13020000FE -:1004C0001301B000130000009300D000B38120009E -:1004D0001302120093022000E31452FE930E8001D7 -:1004E000130E0002639CD10B130200001301B00035 -:1004F000130000009300E00013000000B38120000F -:100500001302120093022000E31252FE930E900198 -:10051000130E10026394D109130200001301B000FE -:1005200013000000130000009300F000B3812000CE -:100530001302120093022000E31252FE930EA00158 -:10054000130E2002639CD1059300F00033011000CC -:10055000930EF000130E30026312D10593000002D7 -:1005600033810000930E0002130E40026318D10382 -:10057000B3000000930E0000130E50026390D003EE -:10058000930000011301E00133802000930E00006E -:10059000130E60026314D001631CC0010F00F00F42 -:1005A00063000E00131E1E00136E1E007300000079 -:1005B0000F00F00F130E100073000000731000C046 -:0405C0000000000037 -:1010000000000000000000000000000000000000E0 -:1010100000000000000000000000000000000000D0 -:1010200000000000000000000000000000000000C0 -:1010300000000000000000000000000000000000B0 -:081040000000000000000000A8 -:040000058000200057 -:00000001FF diff --git a/benchmarks/riscv_tests/rv32ui-p-addi.dump b/benchmarks/riscv_tests/rv32ui-p-addi.dump deleted file mode 100644 index 64f6a99f..00000000 --- a/benchmarks/riscv_tests/rv32ui-p-addi.dump +++ /dev/null @@ -1,308 +0,0 @@ - -rv32ui-p-addi: file format elf32-littleriscv - - -Disassembly of section .text.init: - -80000000 <_start>: -80000000: 04c0006f j 8000004c - -80000004 : -80000004: 34202f73 csrr t5,mcause -80000008: 00800f93 li t6,8 -8000000c: 03ff0a63 beq t5,t6,80000040 -80000010: 00900f93 li t6,9 -80000014: 03ff0663 beq t5,t6,80000040 -80000018: 00b00f93 li t6,11 -8000001c: 03ff0263 beq t5,t6,80000040 -80000020: 80000f17 auipc t5,0x80000 -80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> -80000028: 000f0463 beqz t5,80000030 -8000002c: 000f0067 jr t5 -80000030: 34202f73 csrr t5,mcause -80000034: 000f5463 bgez t5,8000003c -80000038: 0040006f j 8000003c - -8000003c : -8000003c: 5391e193 ori gp,gp,1337 - -80000040 : -80000040: 00001f17 auipc t5,0x1 -80000044: fc3f2023 sw gp,-64(t5) # 80001000 -80000048: ff9ff06f j 80000040 - -8000004c : -8000004c: f1402573 csrr a0,mhartid -80000050: 00051063 bnez a0,80000050 -80000054: 00000297 auipc t0,0x0 -80000058: 01028293 addi t0,t0,16 # 80000064 -8000005c: 30529073 csrw mtvec,t0 -80000060: 18005073 csrwi satp,0 -80000064: 00000297 auipc t0,0x0 -80000068: 02028293 addi t0,t0,32 # 80000084 -8000006c: 30529073 csrw mtvec,t0 -80000070: 800002b7 lui t0,0x80000 -80000074: fff28293 addi t0,t0,-1 # 7fffffff <_end+0xffffdfff> -80000078: 3b029073 csrw pmpaddr0,t0 -8000007c: 01f00293 li t0,31 -80000080: 3a029073 csrw pmpcfg0,t0 -80000084: 00000297 auipc t0,0x0 -80000088: 01828293 addi t0,t0,24 # 8000009c -8000008c: 30529073 csrw mtvec,t0 -80000090: 30205073 csrwi medeleg,0 -80000094: 30305073 csrwi mideleg,0 -80000098: 30405073 csrwi mie,0 -8000009c: 00000193 li gp,0 -800000a0: 00000297 auipc t0,0x0 -800000a4: f6428293 addi t0,t0,-156 # 80000004 -800000a8: 30529073 csrw mtvec,t0 -800000ac: 00100513 li a0,1 -800000b0: 01f51513 slli a0,a0,0x1f -800000b4: 00054c63 bltz a0,800000cc -800000b8: 0ff0000f fence -800000bc: 00100193 li gp,1 -800000c0: 05d00893 li a7,93 -800000c4: 00000513 li a0,0 -800000c8: 00000073 ecall -800000cc: 80000297 auipc t0,0x80000 -800000d0: f3428293 addi t0,t0,-204 # 0 <_start-0x80000000> -800000d4: 00028e63 beqz t0,800000f0 -800000d8: 10529073 csrw stvec,t0 -800000dc: 0000b2b7 lui t0,0xb -800000e0: 10928293 addi t0,t0,265 # b109 <_start-0x7fff4ef7> -800000e4: 30229073 csrw medeleg,t0 -800000e8: 30202373 csrr t1,medeleg -800000ec: f46298e3 bne t0,t1,8000003c -800000f0: 30005073 csrwi mstatus,0 -800000f4: 00000297 auipc t0,0x0 -800000f8: 01428293 addi t0,t0,20 # 80000108 -800000fc: 34129073 csrw mepc,t0 -80000100: f1402573 csrr a0,mhartid -80000104: 30200073 mret - -80000108 : -80000108: 00000093 li ra,0 -8000010c: 00008713 mv a4,ra -80000110: 00000e93 li t4,0 -80000114: 00200193 li gp,2 -80000118: 27d71c63 bne a4,t4,80000390 - -8000011c : -8000011c: 00100093 li ra,1 -80000120: 00108713 addi a4,ra,1 -80000124: 00200e93 li t4,2 -80000128: 00300193 li gp,3 -8000012c: 27d71263 bne a4,t4,80000390 - -80000130 : -80000130: 00300093 li ra,3 -80000134: 00708713 addi a4,ra,7 -80000138: 00a00e93 li t4,10 -8000013c: 00400193 li gp,4 -80000140: 25d71863 bne a4,t4,80000390 - -80000144 : -80000144: 00000093 li ra,0 -80000148: 80008713 addi a4,ra,-2048 -8000014c: 80000e93 li t4,-2048 -80000150: 00500193 li gp,5 -80000154: 23d71e63 bne a4,t4,80000390 - -80000158 : -80000158: 800000b7 lui ra,0x80000 -8000015c: 00008713 mv a4,ra -80000160: 80000eb7 lui t4,0x80000 -80000164: 00600193 li gp,6 -80000168: 23d71463 bne a4,t4,80000390 - -8000016c : -8000016c: 800000b7 lui ra,0x80000 -80000170: 80008713 addi a4,ra,-2048 # 7ffff800 <_end+0xffffd800> -80000174: 80000eb7 lui t4,0x80000 -80000178: 800e8e93 addi t4,t4,-2048 # 7ffff800 <_end+0xffffd800> -8000017c: 00700193 li gp,7 -80000180: 21d71863 bne a4,t4,80000390 - -80000184 : -80000184: 00000093 li ra,0 -80000188: 7ff08713 addi a4,ra,2047 -8000018c: 7ff00e93 li t4,2047 -80000190: 00800193 li gp,8 -80000194: 1fd71e63 bne a4,t4,80000390 - -80000198 : -80000198: 800000b7 lui ra,0x80000 -8000019c: fff08093 addi ra,ra,-1 # 7fffffff <_end+0xffffdfff> -800001a0: 00008713 mv a4,ra -800001a4: 80000eb7 lui t4,0x80000 -800001a8: fffe8e93 addi t4,t4,-1 # 7fffffff <_end+0xffffdfff> -800001ac: 00900193 li gp,9 -800001b0: 1fd71063 bne a4,t4,80000390 - -800001b4 : -800001b4: 800000b7 lui ra,0x80000 -800001b8: fff08093 addi ra,ra,-1 # 7fffffff <_end+0xffffdfff> -800001bc: 7ff08713 addi a4,ra,2047 -800001c0: 80000eb7 lui t4,0x80000 -800001c4: 7fee8e93 addi t4,t4,2046 # 800007fe <_end+0xffffe7fe> -800001c8: 00a00193 li gp,10 -800001cc: 1dd71263 bne a4,t4,80000390 - -800001d0 : -800001d0: 800000b7 lui ra,0x80000 -800001d4: 7ff08713 addi a4,ra,2047 # 800007ff <_end+0xffffe7ff> -800001d8: 80000eb7 lui t4,0x80000 -800001dc: 7ffe8e93 addi t4,t4,2047 # 800007ff <_end+0xffffe7ff> -800001e0: 00b00193 li gp,11 -800001e4: 1bd71663 bne a4,t4,80000390 - -800001e8 : -800001e8: 800000b7 lui ra,0x80000 -800001ec: fff08093 addi ra,ra,-1 # 7fffffff <_end+0xffffdfff> -800001f0: 80008713 addi a4,ra,-2048 -800001f4: 7ffffeb7 lui t4,0x7ffff -800001f8: 7ffe8e93 addi t4,t4,2047 # 7ffff7ff <_start-0x801> -800001fc: 00c00193 li gp,12 -80000200: 19d71863 bne a4,t4,80000390 - -80000204 : -80000204: 00000093 li ra,0 -80000208: fff08713 addi a4,ra,-1 -8000020c: fff00e93 li t4,-1 -80000210: 00d00193 li gp,13 -80000214: 17d71e63 bne a4,t4,80000390 - -80000218 : -80000218: fff00093 li ra,-1 -8000021c: 00108713 addi a4,ra,1 -80000220: 00000e93 li t4,0 -80000224: 00e00193 li gp,14 -80000228: 17d71463 bne a4,t4,80000390 - -8000022c : -8000022c: fff00093 li ra,-1 -80000230: fff08713 addi a4,ra,-1 -80000234: ffe00e93 li t4,-2 -80000238: 00f00193 li gp,15 -8000023c: 15d71a63 bne a4,t4,80000390 - -80000240 : -80000240: 800000b7 lui ra,0x80000 -80000244: fff08093 addi ra,ra,-1 # 7fffffff <_end+0xffffdfff> -80000248: 00108713 addi a4,ra,1 -8000024c: 80000eb7 lui t4,0x80000 -80000250: 01000193 li gp,16 -80000254: 13d71e63 bne a4,t4,80000390 - -80000258 : -80000258: 00d00093 li ra,13 -8000025c: 00b08093 addi ra,ra,11 -80000260: 01800e93 li t4,24 -80000264: 01100193 li gp,17 -80000268: 13d09463 bne ra,t4,80000390 - -8000026c : -8000026c: 00000213 li tp,0 -80000270: 00d00093 li ra,13 -80000274: 00b08713 addi a4,ra,11 -80000278: 00070313 mv t1,a4 -8000027c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000280: 00200293 li t0,2 -80000284: fe5216e3 bne tp,t0,80000270 -80000288: 01800e93 li t4,24 -8000028c: 01200193 li gp,18 -80000290: 11d31063 bne t1,t4,80000390 - -80000294 : -80000294: 00000213 li tp,0 -80000298: 00d00093 li ra,13 -8000029c: 00a08713 addi a4,ra,10 -800002a0: 00000013 nop -800002a4: 00070313 mv t1,a4 -800002a8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -800002ac: 00200293 li t0,2 -800002b0: fe5214e3 bne tp,t0,80000298 -800002b4: 01700e93 li t4,23 -800002b8: 01300193 li gp,19 -800002bc: 0dd31a63 bne t1,t4,80000390 - -800002c0 : -800002c0: 00000213 li tp,0 -800002c4: 00d00093 li ra,13 -800002c8: 00908713 addi a4,ra,9 -800002cc: 00000013 nop -800002d0: 00000013 nop -800002d4: 00070313 mv t1,a4 -800002d8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -800002dc: 00200293 li t0,2 -800002e0: fe5212e3 bne tp,t0,800002c4 -800002e4: 01600e93 li t4,22 -800002e8: 01400193 li gp,20 -800002ec: 0bd31263 bne t1,t4,80000390 - -800002f0 : -800002f0: 00000213 li tp,0 -800002f4: 00d00093 li ra,13 -800002f8: 00b08713 addi a4,ra,11 -800002fc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000300: 00200293 li t0,2 -80000304: fe5218e3 bne tp,t0,800002f4 -80000308: 01800e93 li t4,24 -8000030c: 01500193 li gp,21 -80000310: 09d71063 bne a4,t4,80000390 - -80000314 : -80000314: 00000213 li tp,0 -80000318: 00d00093 li ra,13 -8000031c: 00000013 nop -80000320: 00a08713 addi a4,ra,10 -80000324: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000328: 00200293 li t0,2 -8000032c: fe5216e3 bne tp,t0,80000318 -80000330: 01700e93 li t4,23 -80000334: 01600193 li gp,22 -80000338: 05d71c63 bne a4,t4,80000390 - -8000033c : -8000033c: 00000213 li tp,0 -80000340: 00d00093 li ra,13 -80000344: 00000013 nop -80000348: 00000013 nop -8000034c: 00908713 addi a4,ra,9 -80000350: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000354: 00200293 li t0,2 -80000358: fe5214e3 bne tp,t0,80000340 -8000035c: 01600e93 li t4,22 -80000360: 01700193 li gp,23 -80000364: 03d71663 bne a4,t4,80000390 - -80000368 : -80000368: 02000093 li ra,32 -8000036c: 02000e93 li t4,32 -80000370: 01800193 li gp,24 -80000374: 01d09e63 bne ra,t4,80000390 - -80000378 : -80000378: 02100093 li ra,33 -8000037c: 03208013 addi zero,ra,50 -80000380: 00000e93 li t4,0 -80000384: 01900193 li gp,25 -80000388: 01d01463 bne zero,t4,80000390 -8000038c: 02301063 bne zero,gp,800003ac - -80000390 : -80000390: 0ff0000f fence -80000394: 00018063 beqz gp,80000394 -80000398: 00119193 slli gp,gp,0x1 -8000039c: 0011e193 ori gp,gp,1 -800003a0: 05d00893 li a7,93 -800003a4: 00018513 mv a0,gp -800003a8: 00000073 ecall - -800003ac : -800003ac: 0ff0000f fence -800003b0: 00100193 li gp,1 -800003b4: 05d00893 li a7,93 -800003b8: 00000513 li a0,0 -800003bc: 00000073 ecall -800003c0: c0001073 unimp diff --git a/benchmarks/riscv_tests/rv32ui-p-addi.hex b/benchmarks/riscv_tests/rv32ui-p-addi.hex deleted file mode 100644 index 988b3214..00000000 --- a/benchmarks/riscv_tests/rv32ui-p-addi.hex +++ /dev/null @@ -1,65 +0,0 @@ -:0200000480007A -:100000006F00C004732F2034930F8000630AFF0336 -:10001000930F90006306FF03930FB0006302FF038A -:10002000170F0080130F0FFE63040F0067000F000F -:10003000732F203463540F006F004000136E9E53E3 -:10004000171F00002320CFFD6FF09FFF732540F1A5 -:100050006310050073251030635805000F00F00F82 -:10006000130E100073000000130E00009702000032 -:10007000938282F973905230735020307350303035 -:1000800073504030970200809382C2F7638C020065 -:10009000739052109302B01A739022307323203061 -:1000A000E39E62F873500030970200009382420191 -:1000B00073901234732540F17300203093000000D8 -:1000C00093810000930E0000130E2000639CD12743 -:1000D0009300100093811000930E2000130E300047 -:1000E0006392D1279300300093817000930EA0009B -:1000F000130E40006398D125930000009381008087 -:10010000930E0080130E5000639ED123B700008031 -:1001100093810000B70E0080130E60006394D1231A -:10012000B700008093810080B70E0080938E0E8010 -:10013000130E70006398D121930000009381F07F2B -:10014000930EF07F130E8000639ED11FB7000080D6 -:100150009380F0FF93810000B70E0080938EFEFF26 -:10016000130E90006390D11FB70000809380F0FFC2 -:100170009381F07FB70E0080938EEE7F130EA00068 -:100180006392D11DB70000809381F07FB70E00808D -:10019000938EFE7F130EB0006396D11BB7000080D4 -:1001A0009380F0FF93810080B7FEFF7F938EFE7FE8 -:1001B000130EC0006398D119930000009381F0FFE3 -:1001C000930EF0FF130ED000639ED1179300F0FF43 -:1001D00093811000930E0000130EE0006394D1177A -:1001E0009300F0FF9381F0FF930EE0FF130EF000F9 -:1001F000639AD115B70000809380F0FF93811000BF -:10020000B70E0080130E0001639ED1139300D0003F -:100210009380B000930E8001130E10016394D013ED -:10022000130200009300D0009381B00013830100FB -:100230001302120093022000E31652FE930E800177 -:10024000130E20016310D311130200009300D0009D -:100250009381A00013000000138301001302120019 -:1002600093022000E31452FE930E7001130E30012E -:10027000631AD30D130200009300D0009381900005 -:10028000130000001300000013830100130212008A -:1002900093022000E31252FE930E6001130E400100 -:1002A0006312D30B130200009300D0009381B000BF -:1002B0001302120093022000E31852FE930E8001F5 -:1002C000130E50016390D109130200009300D00077 -:1002D000130000009381A00013021200930220007B -:1002E000E31652FE930E7001130E6001639CD1055C -:1002F000130200009300D000130000001300000060 -:10030000938190001302120093022000E31452FE26 -:10031000930E6001130E70016396D10393000002E7 -:10032000930E0002130E8001639ED0019300100211 -:1003300013802003930E0000130E90016314D0016C -:10034000631CC0010F00F00F63000E00131E1E009F -:10035000136E1E00730000000F00F00F130E10004C -:1003600073000000731000C00000000000000000D7 -:10037000000000000000000000000000000000007D -:040380000000000079 -:1010000000000000000000000000000000000000E0 -:1010100000000000000000000000000000000000D0 -:1010200000000000000000000000000000000000C0 -:1010300000000000000000000000000000000000B0 -:081040000000000000000000A8 -:040000058000200057 -:00000001FF diff --git a/benchmarks/riscv_tests/rv32ui-p-and.dump b/benchmarks/riscv_tests/rv32ui-p-and.dump deleted file mode 100644 index 0a63089f..00000000 --- a/benchmarks/riscv_tests/rv32ui-p-and.dump +++ /dev/null @@ -1,460 +0,0 @@ - -rv32ui-p-and: file format elf32-littleriscv - - -Disassembly of section .text.init: - -80000000 <_start>: -80000000: 04c0006f j 8000004c - -80000004 : -80000004: 34202f73 csrr t5,mcause -80000008: 00800f93 li t6,8 -8000000c: 03ff0a63 beq t5,t6,80000040 -80000010: 00900f93 li t6,9 -80000014: 03ff0663 beq t5,t6,80000040 -80000018: 00b00f93 li t6,11 -8000001c: 03ff0263 beq t5,t6,80000040 -80000020: 80000f17 auipc t5,0x80000 -80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> -80000028: 000f0463 beqz t5,80000030 -8000002c: 000f0067 jr t5 -80000030: 34202f73 csrr t5,mcause -80000034: 000f5463 bgez t5,8000003c -80000038: 0040006f j 8000003c - -8000003c : -8000003c: 5391e193 ori gp,gp,1337 - -80000040 : -80000040: 00001f17 auipc t5,0x1 -80000044: fc3f2023 sw gp,-64(t5) # 80001000 -80000048: ff9ff06f j 80000040 - -8000004c : -8000004c: f1402573 csrr a0,mhartid -80000050: 00051063 bnez a0,80000050 -80000054: 00000297 auipc t0,0x0 -80000058: 01028293 addi t0,t0,16 # 80000064 -8000005c: 30529073 csrw mtvec,t0 -80000060: 18005073 csrwi satp,0 -80000064: 00000297 auipc t0,0x0 -80000068: 02028293 addi t0,t0,32 # 80000084 -8000006c: 30529073 csrw mtvec,t0 -80000070: 800002b7 lui t0,0x80000 -80000074: fff28293 addi t0,t0,-1 # 7fffffff <_end+0xffffdfff> -80000078: 3b029073 csrw pmpaddr0,t0 -8000007c: 01f00293 li t0,31 -80000080: 3a029073 csrw pmpcfg0,t0 -80000084: 00000297 auipc t0,0x0 -80000088: 01828293 addi t0,t0,24 # 8000009c -8000008c: 30529073 csrw mtvec,t0 -80000090: 30205073 csrwi medeleg,0 -80000094: 30305073 csrwi mideleg,0 -80000098: 30405073 csrwi mie,0 -8000009c: 00000193 li gp,0 -800000a0: 00000297 auipc t0,0x0 -800000a4: f6428293 addi t0,t0,-156 # 80000004 -800000a8: 30529073 csrw mtvec,t0 -800000ac: 00100513 li a0,1 -800000b0: 01f51513 slli a0,a0,0x1f -800000b4: 00054c63 bltz a0,800000cc -800000b8: 0ff0000f fence -800000bc: 00100193 li gp,1 -800000c0: 05d00893 li a7,93 -800000c4: 00000513 li a0,0 -800000c8: 00000073 ecall -800000cc: 80000297 auipc t0,0x80000 -800000d0: f3428293 addi t0,t0,-204 # 0 <_start-0x80000000> -800000d4: 00028e63 beqz t0,800000f0 -800000d8: 10529073 csrw stvec,t0 -800000dc: 0000b2b7 lui t0,0xb -800000e0: 10928293 addi t0,t0,265 # b109 <_start-0x7fff4ef7> -800000e4: 30229073 csrw medeleg,t0 -800000e8: 30202373 csrr t1,medeleg -800000ec: f46298e3 bne t0,t1,8000003c -800000f0: 30005073 csrwi mstatus,0 -800000f4: 00000297 auipc t0,0x0 -800000f8: 01428293 addi t0,t0,20 # 80000108 -800000fc: 34129073 csrw mepc,t0 -80000100: f1402573 csrr a0,mhartid -80000104: 30200073 mret - -80000108 : -80000108: ff0100b7 lui ra,0xff010 -8000010c: f0008093 addi ra,ra,-256 # ff00ff00 <_end+0x7f00df00> -80000110: 0f0f1137 lui sp,0xf0f1 -80000114: f0f10113 addi sp,sp,-241 # f0f0f0f <_start-0x70f0f0f1> -80000118: 0020f733 and a4,ra,sp -8000011c: 0f001eb7 lui t4,0xf001 -80000120: f00e8e93 addi t4,t4,-256 # f000f00 <_start-0x70fff100> -80000124: 00200193 li gp,2 -80000128: 49d71c63 bne a4,t4,800005c0 - -8000012c : -8000012c: 0ff010b7 lui ra,0xff01 -80000130: ff008093 addi ra,ra,-16 # ff00ff0 <_start-0x700ff010> -80000134: f0f0f137 lui sp,0xf0f0f -80000138: 0f010113 addi sp,sp,240 # f0f0f0f0 <_end+0x70f0d0f0> -8000013c: 0020f733 and a4,ra,sp -80000140: 00f00eb7 lui t4,0xf00 -80000144: 0f0e8e93 addi t4,t4,240 # f000f0 <_start-0x7f0fff10> -80000148: 00300193 li gp,3 -8000014c: 47d71a63 bne a4,t4,800005c0 - -80000150 : -80000150: 00ff00b7 lui ra,0xff0 -80000154: 0ff08093 addi ra,ra,255 # ff00ff <_start-0x7f00ff01> -80000158: 0f0f1137 lui sp,0xf0f1 -8000015c: f0f10113 addi sp,sp,-241 # f0f0f0f <_start-0x70f0f0f1> -80000160: 0020f733 and a4,ra,sp -80000164: 000f0eb7 lui t4,0xf0 -80000168: 00fe8e93 addi t4,t4,15 # f000f <_start-0x7ff0fff1> -8000016c: 00400193 li gp,4 -80000170: 45d71863 bne a4,t4,800005c0 - -80000174 : -80000174: f00ff0b7 lui ra,0xf00ff -80000178: 00f08093 addi ra,ra,15 # f00ff00f <_end+0x700fd00f> -8000017c: f0f0f137 lui sp,0xf0f0f -80000180: 0f010113 addi sp,sp,240 # f0f0f0f0 <_end+0x70f0d0f0> -80000184: 0020f733 and a4,ra,sp -80000188: f000feb7 lui t4,0xf000f -8000018c: 00500193 li gp,5 -80000190: 43d71863 bne a4,t4,800005c0 - -80000194 : -80000194: ff0100b7 lui ra,0xff010 -80000198: f0008093 addi ra,ra,-256 # ff00ff00 <_end+0x7f00df00> -8000019c: 0f0f1137 lui sp,0xf0f1 -800001a0: f0f10113 addi sp,sp,-241 # f0f0f0f <_start-0x70f0f0f1> -800001a4: 0020f0b3 and ra,ra,sp -800001a8: 0f001eb7 lui t4,0xf001 -800001ac: f00e8e93 addi t4,t4,-256 # f000f00 <_start-0x70fff100> -800001b0: 00600193 li gp,6 -800001b4: 41d09663 bne ra,t4,800005c0 - -800001b8 : -800001b8: 0ff010b7 lui ra,0xff01 -800001bc: ff008093 addi ra,ra,-16 # ff00ff0 <_start-0x700ff010> -800001c0: f0f0f137 lui sp,0xf0f0f -800001c4: 0f010113 addi sp,sp,240 # f0f0f0f0 <_end+0x70f0d0f0> -800001c8: 0020f133 and sp,ra,sp -800001cc: 00f00eb7 lui t4,0xf00 -800001d0: 0f0e8e93 addi t4,t4,240 # f000f0 <_start-0x7f0fff10> -800001d4: 00700193 li gp,7 -800001d8: 3fd11463 bne sp,t4,800005c0 - -800001dc : -800001dc: ff0100b7 lui ra,0xff010 -800001e0: f0008093 addi ra,ra,-256 # ff00ff00 <_end+0x7f00df00> -800001e4: 0010f0b3 and ra,ra,ra -800001e8: ff010eb7 lui t4,0xff010 -800001ec: f00e8e93 addi t4,t4,-256 # ff00ff00 <_end+0x7f00df00> -800001f0: 00800193 li gp,8 -800001f4: 3dd09663 bne ra,t4,800005c0 - -800001f8 : -800001f8: 00000213 li tp,0 -800001fc: ff0100b7 lui ra,0xff010 -80000200: f0008093 addi ra,ra,-256 # ff00ff00 <_end+0x7f00df00> -80000204: 0f0f1137 lui sp,0xf0f1 -80000208: f0f10113 addi sp,sp,-241 # f0f0f0f <_start-0x70f0f0f1> -8000020c: 0020f733 and a4,ra,sp -80000210: 00070313 mv t1,a4 -80000214: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000218: 00200293 li t0,2 -8000021c: fe5210e3 bne tp,t0,800001fc -80000220: 0f001eb7 lui t4,0xf001 -80000224: f00e8e93 addi t4,t4,-256 # f000f00 <_start-0x70fff100> -80000228: 00900193 li gp,9 -8000022c: 39d31a63 bne t1,t4,800005c0 - -80000230 : -80000230: 00000213 li tp,0 -80000234: 0ff010b7 lui ra,0xff01 -80000238: ff008093 addi ra,ra,-16 # ff00ff0 <_start-0x700ff010> -8000023c: f0f0f137 lui sp,0xf0f0f -80000240: 0f010113 addi sp,sp,240 # f0f0f0f0 <_end+0x70f0d0f0> -80000244: 0020f733 and a4,ra,sp -80000248: 00000013 nop -8000024c: 00070313 mv t1,a4 -80000250: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000254: 00200293 li t0,2 -80000258: fc521ee3 bne tp,t0,80000234 -8000025c: 00f00eb7 lui t4,0xf00 -80000260: 0f0e8e93 addi t4,t4,240 # f000f0 <_start-0x7f0fff10> -80000264: 00a00193 li gp,10 -80000268: 35d31c63 bne t1,t4,800005c0 - -8000026c : -8000026c: 00000213 li tp,0 -80000270: 00ff00b7 lui ra,0xff0 -80000274: 0ff08093 addi ra,ra,255 # ff00ff <_start-0x7f00ff01> -80000278: 0f0f1137 lui sp,0xf0f1 -8000027c: f0f10113 addi sp,sp,-241 # f0f0f0f <_start-0x70f0f0f1> -80000280: 0020f733 and a4,ra,sp -80000284: 00000013 nop -80000288: 00000013 nop -8000028c: 00070313 mv t1,a4 -80000290: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000294: 00200293 li t0,2 -80000298: fc521ce3 bne tp,t0,80000270 -8000029c: 000f0eb7 lui t4,0xf0 -800002a0: 00fe8e93 addi t4,t4,15 # f000f <_start-0x7ff0fff1> -800002a4: 00b00193 li gp,11 -800002a8: 31d31c63 bne t1,t4,800005c0 - -800002ac : -800002ac: 00000213 li tp,0 -800002b0: ff0100b7 lui ra,0xff010 -800002b4: f0008093 addi ra,ra,-256 # ff00ff00 <_end+0x7f00df00> -800002b8: 0f0f1137 lui sp,0xf0f1 -800002bc: f0f10113 addi sp,sp,-241 # f0f0f0f <_start-0x70f0f0f1> -800002c0: 0020f733 and a4,ra,sp -800002c4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -800002c8: 00200293 li t0,2 -800002cc: fe5212e3 bne tp,t0,800002b0 -800002d0: 0f001eb7 lui t4,0xf001 -800002d4: f00e8e93 addi t4,t4,-256 # f000f00 <_start-0x70fff100> -800002d8: 00c00193 li gp,12 -800002dc: 2fd71263 bne a4,t4,800005c0 - -800002e0 : -800002e0: 00000213 li tp,0 -800002e4: 0ff010b7 lui ra,0xff01 -800002e8: ff008093 addi ra,ra,-16 # ff00ff0 <_start-0x700ff010> -800002ec: f0f0f137 lui sp,0xf0f0f -800002f0: 0f010113 addi sp,sp,240 # f0f0f0f0 <_end+0x70f0d0f0> -800002f4: 00000013 nop -800002f8: 0020f733 and a4,ra,sp -800002fc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000300: 00200293 li t0,2 -80000304: fe5210e3 bne tp,t0,800002e4 -80000308: 00f00eb7 lui t4,0xf00 -8000030c: 0f0e8e93 addi t4,t4,240 # f000f0 <_start-0x7f0fff10> -80000310: 00d00193 li gp,13 -80000314: 2bd71663 bne a4,t4,800005c0 - -80000318 : -80000318: 00000213 li tp,0 -8000031c: 00ff00b7 lui ra,0xff0 -80000320: 0ff08093 addi ra,ra,255 # ff00ff <_start-0x7f00ff01> -80000324: 0f0f1137 lui sp,0xf0f1 -80000328: f0f10113 addi sp,sp,-241 # f0f0f0f <_start-0x70f0f0f1> -8000032c: 00000013 nop -80000330: 00000013 nop -80000334: 0020f733 and a4,ra,sp -80000338: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -8000033c: 00200293 li t0,2 -80000340: fc521ee3 bne tp,t0,8000031c -80000344: 000f0eb7 lui t4,0xf0 -80000348: 00fe8e93 addi t4,t4,15 # f000f <_start-0x7ff0fff1> -8000034c: 00e00193 li gp,14 -80000350: 27d71863 bne a4,t4,800005c0 - -80000354 : -80000354: 00000213 li tp,0 -80000358: ff0100b7 lui ra,0xff010 -8000035c: f0008093 addi ra,ra,-256 # ff00ff00 <_end+0x7f00df00> -80000360: 00000013 nop -80000364: 0f0f1137 lui sp,0xf0f1 -80000368: f0f10113 addi sp,sp,-241 # f0f0f0f <_start-0x70f0f0f1> -8000036c: 0020f733 and a4,ra,sp -80000370: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000374: 00200293 li t0,2 -80000378: fe5210e3 bne tp,t0,80000358 -8000037c: 0f001eb7 lui t4,0xf001 -80000380: f00e8e93 addi t4,t4,-256 # f000f00 <_start-0x70fff100> -80000384: 00f00193 li gp,15 -80000388: 23d71c63 bne a4,t4,800005c0 - -8000038c : -8000038c: 00000213 li tp,0 -80000390: 0ff010b7 lui ra,0xff01 -80000394: ff008093 addi ra,ra,-16 # ff00ff0 <_start-0x700ff010> -80000398: 00000013 nop -8000039c: f0f0f137 lui sp,0xf0f0f -800003a0: 0f010113 addi sp,sp,240 # f0f0f0f0 <_end+0x70f0d0f0> -800003a4: 00000013 nop -800003a8: 0020f733 and a4,ra,sp -800003ac: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -800003b0: 00200293 li t0,2 -800003b4: fc521ee3 bne tp,t0,80000390 -800003b8: 00f00eb7 lui t4,0xf00 -800003bc: 0f0e8e93 addi t4,t4,240 # f000f0 <_start-0x7f0fff10> -800003c0: 01000193 li gp,16 -800003c4: 1fd71e63 bne a4,t4,800005c0 - -800003c8 : -800003c8: 00000213 li tp,0 -800003cc: 00ff00b7 lui ra,0xff0 -800003d0: 0ff08093 addi ra,ra,255 # ff00ff <_start-0x7f00ff01> -800003d4: 00000013 nop -800003d8: 00000013 nop -800003dc: 0f0f1137 lui sp,0xf0f1 -800003e0: f0f10113 addi sp,sp,-241 # f0f0f0f <_start-0x70f0f0f1> -800003e4: 0020f733 and a4,ra,sp -800003e8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -800003ec: 00200293 li t0,2 -800003f0: fc521ee3 bne tp,t0,800003cc -800003f4: 000f0eb7 lui t4,0xf0 -800003f8: 00fe8e93 addi t4,t4,15 # f000f <_start-0x7ff0fff1> -800003fc: 01100193 li gp,17 -80000400: 1dd71063 bne a4,t4,800005c0 - -80000404 : -80000404: 00000213 li tp,0 -80000408: 0f0f1137 lui sp,0xf0f1 -8000040c: f0f10113 addi sp,sp,-241 # f0f0f0f <_start-0x70f0f0f1> -80000410: ff0100b7 lui ra,0xff010 -80000414: f0008093 addi ra,ra,-256 # ff00ff00 <_end+0x7f00df00> -80000418: 0020f733 and a4,ra,sp -8000041c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000420: 00200293 li t0,2 -80000424: fe5212e3 bne tp,t0,80000408 -80000428: 0f001eb7 lui t4,0xf001 -8000042c: f00e8e93 addi t4,t4,-256 # f000f00 <_start-0x70fff100> -80000430: 01200193 li gp,18 -80000434: 19d71663 bne a4,t4,800005c0 - -80000438 : -80000438: 00000213 li tp,0 -8000043c: f0f0f137 lui sp,0xf0f0f -80000440: 0f010113 addi sp,sp,240 # f0f0f0f0 <_end+0x70f0d0f0> -80000444: 0ff010b7 lui ra,0xff01 -80000448: ff008093 addi ra,ra,-16 # ff00ff0 <_start-0x700ff010> -8000044c: 00000013 nop -80000450: 0020f733 and a4,ra,sp -80000454: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000458: 00200293 li t0,2 -8000045c: fe5210e3 bne tp,t0,8000043c -80000460: 00f00eb7 lui t4,0xf00 -80000464: 0f0e8e93 addi t4,t4,240 # f000f0 <_start-0x7f0fff10> -80000468: 01300193 li gp,19 -8000046c: 15d71a63 bne a4,t4,800005c0 - -80000470 : -80000470: 00000213 li tp,0 -80000474: 0f0f1137 lui sp,0xf0f1 -80000478: f0f10113 addi sp,sp,-241 # f0f0f0f <_start-0x70f0f0f1> -8000047c: 00ff00b7 lui ra,0xff0 -80000480: 0ff08093 addi ra,ra,255 # ff00ff <_start-0x7f00ff01> -80000484: 00000013 nop -80000488: 00000013 nop -8000048c: 0020f733 and a4,ra,sp -80000490: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000494: 00200293 li t0,2 -80000498: fc521ee3 bne tp,t0,80000474 -8000049c: 000f0eb7 lui t4,0xf0 -800004a0: 00fe8e93 addi t4,t4,15 # f000f <_start-0x7ff0fff1> -800004a4: 01400193 li gp,20 -800004a8: 11d71c63 bne a4,t4,800005c0 - -800004ac : -800004ac: 00000213 li tp,0 -800004b0: 0f0f1137 lui sp,0xf0f1 -800004b4: f0f10113 addi sp,sp,-241 # f0f0f0f <_start-0x70f0f0f1> -800004b8: 00000013 nop -800004bc: ff0100b7 lui ra,0xff010 -800004c0: f0008093 addi ra,ra,-256 # ff00ff00 <_end+0x7f00df00> -800004c4: 0020f733 and a4,ra,sp -800004c8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -800004cc: 00200293 li t0,2 -800004d0: fe5210e3 bne tp,t0,800004b0 -800004d4: 0f001eb7 lui t4,0xf001 -800004d8: f00e8e93 addi t4,t4,-256 # f000f00 <_start-0x70fff100> -800004dc: 01500193 li gp,21 -800004e0: 0fd71063 bne a4,t4,800005c0 - -800004e4 : -800004e4: 00000213 li tp,0 -800004e8: f0f0f137 lui sp,0xf0f0f -800004ec: 0f010113 addi sp,sp,240 # f0f0f0f0 <_end+0x70f0d0f0> -800004f0: 00000013 nop -800004f4: 0ff010b7 lui ra,0xff01 -800004f8: ff008093 addi ra,ra,-16 # ff00ff0 <_start-0x700ff010> -800004fc: 00000013 nop -80000500: 0020f733 and a4,ra,sp -80000504: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000508: 00200293 li t0,2 -8000050c: fc521ee3 bne tp,t0,800004e8 -80000510: 00f00eb7 lui t4,0xf00 -80000514: 0f0e8e93 addi t4,t4,240 # f000f0 <_start-0x7f0fff10> -80000518: 01600193 li gp,22 -8000051c: 0bd71263 bne a4,t4,800005c0 - -80000520 : -80000520: 00000213 li tp,0 -80000524: 0f0f1137 lui sp,0xf0f1 -80000528: f0f10113 addi sp,sp,-241 # f0f0f0f <_start-0x70f0f0f1> -8000052c: 00000013 nop -80000530: 00000013 nop -80000534: 00ff00b7 lui ra,0xff0 -80000538: 0ff08093 addi ra,ra,255 # ff00ff <_start-0x7f00ff01> -8000053c: 0020f733 and a4,ra,sp -80000540: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000544: 00200293 li t0,2 -80000548: fc521ee3 bne tp,t0,80000524 -8000054c: 000f0eb7 lui t4,0xf0 -80000550: 00fe8e93 addi t4,t4,15 # f000f <_start-0x7ff0fff1> -80000554: 01700193 li gp,23 -80000558: 07d71463 bne a4,t4,800005c0 - -8000055c : -8000055c: ff0100b7 lui ra,0xff010 -80000560: f0008093 addi ra,ra,-256 # ff00ff00 <_end+0x7f00df00> -80000564: 00107133 and sp,zero,ra -80000568: 00000e93 li t4,0 -8000056c: 01800193 li gp,24 -80000570: 05d11863 bne sp,t4,800005c0 - -80000574 : -80000574: 00ff00b7 lui ra,0xff0 -80000578: 0ff08093 addi ra,ra,255 # ff00ff <_start-0x7f00ff01> -8000057c: 0000f133 and sp,ra,zero -80000580: 00000e93 li t4,0 -80000584: 01900193 li gp,25 -80000588: 03d11c63 bne sp,t4,800005c0 - -8000058c : -8000058c: 000070b3 and ra,zero,zero -80000590: 00000e93 li t4,0 -80000594: 01a00193 li gp,26 -80000598: 03d09463 bne ra,t4,800005c0 - -8000059c : -8000059c: 111110b7 lui ra,0x11111 -800005a0: 11108093 addi ra,ra,273 # 11111111 <_start-0x6eeeeeef> -800005a4: 22222137 lui sp,0x22222 -800005a8: 22210113 addi sp,sp,546 # 22222222 <_start-0x5dddddde> -800005ac: 0020f033 and zero,ra,sp -800005b0: 00000e93 li t4,0 -800005b4: 01b00193 li gp,27 -800005b8: 01d01463 bne zero,t4,800005c0 -800005bc: 02301063 bne zero,gp,800005dc - -800005c0 : -800005c0: 0ff0000f fence -800005c4: 00018063 beqz gp,800005c4 -800005c8: 00119193 slli gp,gp,0x1 -800005cc: 0011e193 ori gp,gp,1 -800005d0: 05d00893 li a7,93 -800005d4: 00018513 mv a0,gp -800005d8: 00000073 ecall - -800005dc : -800005dc: 0ff0000f fence -800005e0: 00100193 li gp,1 -800005e4: 05d00893 li a7,93 -800005e8: 00000513 li a0,0 -800005ec: 00000073 ecall -800005f0: c0001073 unimp -800005f4: 0000 unimp -800005f6: 0000 unimp -800005f8: 0000 unimp -800005fa: 0000 unimp -800005fc: 0000 unimp -800005fe: 0000 unimp -80000600: 0000 unimp -80000602: 0000 unimp diff --git a/benchmarks/riscv_tests/rv32ui-p-and.hex b/benchmarks/riscv_tests/rv32ui-p-and.hex deleted file mode 100644 index 6ec06d92..00000000 --- a/benchmarks/riscv_tests/rv32ui-p-and.hex +++ /dev/null @@ -1,101 +0,0 @@ -:0200000480007A -:100000006F00C004732F2034930F8000630AFF0336 -:10001000930F90006306FF03930FB0006302FF038A -:10002000170F0080130F0FFE63040F0067000F000F -:10003000732F203463540F006F004000136E9E53E3 -:10004000171F00002320CFFD6FF09FFF732540F1A5 -:100050006310050073251030635805000F00F00F82 -:10006000130E100073000000130E00009702000032 -:10007000938282F973905230735020307350303035 -:1000800073504030970200809382C2F7638C020065 -:10009000739052109302B01A739022307323203061 -:1000A000E39E62F873500030970200009382420191 -:1000B00073901234732540F173002030B70001FFB4 -:1000C000938000F037110F0F1301F1F0B3F120000E -:1000D000B71E000F938E0EF0130E2000639CD149C3 -:1000E000B710F00F938000FF37F1F0F01301010F0C -:1000F000B3F12000B70EF000938E0E0F130E3000F8 -:10010000639AD147B700FF009380F00F37110F0FAC -:100110001301F1F0B3F12000B70E0F00938EFE0033 -:10012000130E40006398D145B7F00FF09380F000B4 -:1001300037F1F0F01301010FB3F12000B7FE00F02A -:10014000130E50006398D143B70001FF938000F075 -:1001500037110F0F1301F1F0B3F02000B71E000F9D -:10016000938E0EF0130E60006396D041B710F00F1F -:10017000938000FF37F1F0F01301010F33F12000FD -:10018000B70EF000938E0E0F130E70006314D13F64 -:10019000B70001FF938000F0B3F01000B70E01FF2D -:1001A000938E0EF0130E80006396D03D1302000074 -:1001B000B70001FF938000F037110F0F1301F1F02A -:1001C000B3F12000138301001302120093022000F8 -:1001D000E31052FEB71E000F938E0EF0130E900028 -:1001E000631AD33913020000B710F00F938000FF99 -:1001F00037F1F0F01301010FB3F1200013000000FC -:10020000138301001302120093022000E31E52FC2C -:10021000B70EF000938E0E0F130EA000631CD335A3 -:1002200013020000B700FF009380F00F37110F0F8B -:100230001301F1F0B3F120001300000013000000DF -:10024000138301001302120093022000E31C52FCEE -:10025000B70E0F00938EFE00130EB000631CD33157 -:1002600013020000B70001FF938000F037110F0F59 -:100270001301F1F0B3F120001302120093022000E9 -:10028000E31252FEB71E000F938E0EF0130EC00045 -:100290006392D12F13020000B710F00F938000FF7C -:1002A00037F1F0F01301010F13000000B3F120004B -:1002B0001302120093022000E31052FEB70EF0006A -:1002C000938E0E0F130ED0006396D12B13020000F5 -:1002D000B700FF009380F00F37110F0F1301F1F0FB -:1002E0001300000013000000B3F1200013021200FD -:1002F00093022000E31E52FCB70E0F00938EFE0007 -:10030000130EE0006398D12713020000B70001FF2D -:10031000938000F01300000037110F0F1301F1F06C -:10032000B3F120001302120093022000E31052FEEA -:10033000B71E000F938E0EF0130EF000639CD123B6 -:1003400013020000B710F00F938000FF13000000AD -:1003500037F1F0F01301010F13000000B3F120009A -:100360001302120093022000E31E52FCB70EF000AD -:10037000938E0E0F130E0001639ED11F1302000017 -:10038000B700FF009380F00F13000000130000007F -:1003900037110F0F1301F1F0B3F120001302120017 -:1003A00093022000E31E52FCB70E0F00938EFE0056 -:1003B000130E10016390D11D1302000037110F0FAF -:1003C0001301F1F0B70001FF938000F0B3F12000BA -:1003D0001302120093022000E31252FEB71E000F18 -:1003E000938E0EF0130E20016396D11913020000B4 -:1003F00037F1F0F01301010FB710F00F938000FFF9 -:1004000013000000B3F12000130212009302200039 -:10041000E31052FEB70EF000938E0E0F130E300154 -:10042000639AD1151302000037110F0F1301F1F079 -:10043000B700FF009380F00F1300000013000000CE -:10044000B3F120001302120093022000E31E52FCBD -:10045000B70E0F00938EFE00130E4001639CD11166 -:100460001302000037110F0F1301F1F01300000009 -:10047000B70001FF938000F0B3F1200013021200D7 -:1004800093022000E31052FEB71E000F938E0EF071 -:10049000130E50016390D10F1302000037F1F0F0FA -:1004A0001301010F13000000B710F00F938000FF3D -:1004B00013000000B3F12000130212009302200089 -:1004C000E31E52FCB70EF000938E0E0F130E600168 -:1004D0006392D10B1302000037110F0F1301F1F0DB -:1004E0001300000013000000B700FF009380F00F1E -:1004F000B3F120001302120093022000E31E52FC0D -:10050000B70E0F00938EFE00130E70016394D10797 -:10051000B70001FF938000F033711000930E0000CC -:10052000130E80016318D105B700FF009380F00F10 -:1005300033F10000930E0000130E9001631CD103F1 -:10054000B3700000930E0000130EA0016394D0035B -:10055000B71011119380101137212222130121228B -:1005600033F02000930E0000130EB0016314D0018D -:10057000631CC0010F00F00F63000E00131E1E006D -:10058000136E1E00730000000F00F00F130E10001A -:1005900073000000731000C00000000000000000A5 -:1005A000000000000000000000000000000000004B -:1005B000000000000000000000000000000000003B -:0405C0000000000037 -:1010000000000000000000000000000000000000E0 -:1010100000000000000000000000000000000000D0 -:1010200000000000000000000000000000000000C0 -:1010300000000000000000000000000000000000B0 -:081040000000000000000000A8 -:040000058000200057 -:00000001FF diff --git a/benchmarks/riscv_tests/rv32ui-p-andi.dump b/benchmarks/riscv_tests/rv32ui-p-andi.dump deleted file mode 100644 index 87e3441f..00000000 --- a/benchmarks/riscv_tests/rv32ui-p-andi.dump +++ /dev/null @@ -1,240 +0,0 @@ - -rv32ui-p-andi: file format elf32-littleriscv - - -Disassembly of section .text.init: - -80000000 <_start>: -80000000: 04c0006f j 8000004c - -80000004 : -80000004: 34202f73 csrr t5,mcause -80000008: 00800f93 li t6,8 -8000000c: 03ff0a63 beq t5,t6,80000040 -80000010: 00900f93 li t6,9 -80000014: 03ff0663 beq t5,t6,80000040 -80000018: 00b00f93 li t6,11 -8000001c: 03ff0263 beq t5,t6,80000040 -80000020: 80000f17 auipc t5,0x80000 -80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> -80000028: 000f0463 beqz t5,80000030 -8000002c: 000f0067 jr t5 -80000030: 34202f73 csrr t5,mcause -80000034: 000f5463 bgez t5,8000003c -80000038: 0040006f j 8000003c - -8000003c : -8000003c: 5391e193 ori gp,gp,1337 - -80000040 : -80000040: 00001f17 auipc t5,0x1 -80000044: fc3f2023 sw gp,-64(t5) # 80001000 -80000048: ff9ff06f j 80000040 - -8000004c : -8000004c: f1402573 csrr a0,mhartid -80000050: 00051063 bnez a0,80000050 -80000054: 00000297 auipc t0,0x0 -80000058: 01028293 addi t0,t0,16 # 80000064 -8000005c: 30529073 csrw mtvec,t0 -80000060: 18005073 csrwi satp,0 -80000064: 00000297 auipc t0,0x0 -80000068: 02028293 addi t0,t0,32 # 80000084 -8000006c: 30529073 csrw mtvec,t0 -80000070: 800002b7 lui t0,0x80000 -80000074: fff28293 addi t0,t0,-1 # 7fffffff <_end+0xffffdfff> -80000078: 3b029073 csrw pmpaddr0,t0 -8000007c: 01f00293 li t0,31 -80000080: 3a029073 csrw pmpcfg0,t0 -80000084: 00000297 auipc t0,0x0 -80000088: 01828293 addi t0,t0,24 # 8000009c -8000008c: 30529073 csrw mtvec,t0 -80000090: 30205073 csrwi medeleg,0 -80000094: 30305073 csrwi mideleg,0 -80000098: 30405073 csrwi mie,0 -8000009c: 00000193 li gp,0 -800000a0: 00000297 auipc t0,0x0 -800000a4: f6428293 addi t0,t0,-156 # 80000004 -800000a8: 30529073 csrw mtvec,t0 -800000ac: 00100513 li a0,1 -800000b0: 01f51513 slli a0,a0,0x1f -800000b4: 00054c63 bltz a0,800000cc -800000b8: 0ff0000f fence -800000bc: 00100193 li gp,1 -800000c0: 05d00893 li a7,93 -800000c4: 00000513 li a0,0 -800000c8: 00000073 ecall -800000cc: 80000297 auipc t0,0x80000 -800000d0: f3428293 addi t0,t0,-204 # 0 <_start-0x80000000> -800000d4: 00028e63 beqz t0,800000f0 -800000d8: 10529073 csrw stvec,t0 -800000dc: 0000b2b7 lui t0,0xb -800000e0: 10928293 addi t0,t0,265 # b109 <_start-0x7fff4ef7> -800000e4: 30229073 csrw medeleg,t0 -800000e8: 30202373 csrr t1,medeleg -800000ec: f46298e3 bne t0,t1,8000003c -800000f0: 30005073 csrwi mstatus,0 -800000f4: 00000297 auipc t0,0x0 -800000f8: 01428293 addi t0,t0,20 # 80000108 -800000fc: 34129073 csrw mepc,t0 -80000100: f1402573 csrr a0,mhartid -80000104: 30200073 mret - -80000108 : -80000108: ff0100b7 lui ra,0xff010 -8000010c: f0008093 addi ra,ra,-256 # ff00ff00 <_end+0x7f00df00> -80000110: f0f0f713 andi a4,ra,-241 -80000114: ff010eb7 lui t4,0xff010 -80000118: f00e8e93 addi t4,t4,-256 # ff00ff00 <_end+0x7f00df00> -8000011c: 00200193 li gp,2 -80000120: 1bd71463 bne a4,t4,800002c8 - -80000124 : -80000124: 0ff010b7 lui ra,0xff01 -80000128: ff008093 addi ra,ra,-16 # ff00ff0 <_start-0x700ff010> -8000012c: 0f00f713 andi a4,ra,240 -80000130: 0f000e93 li t4,240 -80000134: 00300193 li gp,3 -80000138: 19d71863 bne a4,t4,800002c8 - -8000013c : -8000013c: 00ff00b7 lui ra,0xff0 -80000140: 0ff08093 addi ra,ra,255 # ff00ff <_start-0x7f00ff01> -80000144: 70f0f713 andi a4,ra,1807 -80000148: 00f00e93 li t4,15 -8000014c: 00400193 li gp,4 -80000150: 17d71c63 bne a4,t4,800002c8 - -80000154 : -80000154: f00ff0b7 lui ra,0xf00ff -80000158: 00f08093 addi ra,ra,15 # f00ff00f <_end+0x700fd00f> -8000015c: 0f00f713 andi a4,ra,240 -80000160: 00000e93 li t4,0 -80000164: 00500193 li gp,5 -80000168: 17d71063 bne a4,t4,800002c8 - -8000016c : -8000016c: ff0100b7 lui ra,0xff010 -80000170: f0008093 addi ra,ra,-256 # ff00ff00 <_end+0x7f00df00> -80000174: 0f00f093 andi ra,ra,240 -80000178: 00000e93 li t4,0 -8000017c: 00600193 li gp,6 -80000180: 15d09463 bne ra,t4,800002c8 - -80000184 : -80000184: 00000213 li tp,0 -80000188: 0ff010b7 lui ra,0xff01 -8000018c: ff008093 addi ra,ra,-16 # ff00ff0 <_start-0x700ff010> -80000190: 70f0f713 andi a4,ra,1807 -80000194: 00070313 mv t1,a4 -80000198: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -8000019c: 00200293 li t0,2 -800001a0: fe5214e3 bne tp,t0,80000188 -800001a4: 70000e93 li t4,1792 -800001a8: 00700193 li gp,7 -800001ac: 11d31e63 bne t1,t4,800002c8 - -800001b0 : -800001b0: 00000213 li tp,0 -800001b4: 00ff00b7 lui ra,0xff0 -800001b8: 0ff08093 addi ra,ra,255 # ff00ff <_start-0x7f00ff01> -800001bc: 0f00f713 andi a4,ra,240 -800001c0: 00000013 nop -800001c4: 00070313 mv t1,a4 -800001c8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -800001cc: 00200293 li t0,2 -800001d0: fe5212e3 bne tp,t0,800001b4 -800001d4: 0f000e93 li t4,240 -800001d8: 00800193 li gp,8 -800001dc: 0fd31663 bne t1,t4,800002c8 - -800001e0 : -800001e0: 00000213 li tp,0 -800001e4: f00ff0b7 lui ra,0xf00ff -800001e8: 00f08093 addi ra,ra,15 # f00ff00f <_end+0x700fd00f> -800001ec: f0f0f713 andi a4,ra,-241 -800001f0: 00000013 nop -800001f4: 00000013 nop -800001f8: 00070313 mv t1,a4 -800001fc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000200: 00200293 li t0,2 -80000204: fe5210e3 bne tp,t0,800001e4 -80000208: f00ffeb7 lui t4,0xf00ff -8000020c: 00fe8e93 addi t4,t4,15 # f00ff00f <_end+0x700fd00f> -80000210: 00900193 li gp,9 -80000214: 0bd31a63 bne t1,t4,800002c8 - -80000218 : -80000218: 00000213 li tp,0 -8000021c: 0ff010b7 lui ra,0xff01 -80000220: ff008093 addi ra,ra,-16 # ff00ff0 <_start-0x700ff010> -80000224: 70f0f713 andi a4,ra,1807 -80000228: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -8000022c: 00200293 li t0,2 -80000230: fe5216e3 bne tp,t0,8000021c -80000234: 70000e93 li t4,1792 -80000238: 00a00193 li gp,10 -8000023c: 09d71663 bne a4,t4,800002c8 - -80000240 : -80000240: 00000213 li tp,0 -80000244: 00ff00b7 lui ra,0xff0 -80000248: 0ff08093 addi ra,ra,255 # ff00ff <_start-0x7f00ff01> -8000024c: 00000013 nop -80000250: 0f00f713 andi a4,ra,240 -80000254: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000258: 00200293 li t0,2 -8000025c: fe5214e3 bne tp,t0,80000244 -80000260: 0f000e93 li t4,240 -80000264: 00b00193 li gp,11 -80000268: 07d71063 bne a4,t4,800002c8 - -8000026c : -8000026c: 00000213 li tp,0 -80000270: f00ff0b7 lui ra,0xf00ff -80000274: 00f08093 addi ra,ra,15 # f00ff00f <_end+0x700fd00f> -80000278: 00000013 nop -8000027c: 00000013 nop -80000280: 70f0f713 andi a4,ra,1807 -80000284: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000288: 00200293 li t0,2 -8000028c: fe5212e3 bne tp,t0,80000270 -80000290: 00f00e93 li t4,15 -80000294: 00c00193 li gp,12 -80000298: 03d71863 bne a4,t4,800002c8 - -8000029c : -8000029c: 0f007093 andi ra,zero,240 -800002a0: 00000e93 li t4,0 -800002a4: 00d00193 li gp,13 -800002a8: 03d09063 bne ra,t4,800002c8 - -800002ac : -800002ac: 00ff00b7 lui ra,0xff0 -800002b0: 0ff08093 addi ra,ra,255 # ff00ff <_start-0x7f00ff01> -800002b4: 70f0f013 andi zero,ra,1807 -800002b8: 00000e93 li t4,0 -800002bc: 00e00193 li gp,14 -800002c0: 01d01463 bne zero,t4,800002c8 -800002c4: 02301063 bne zero,gp,800002e4 - -800002c8 : -800002c8: 0ff0000f fence -800002cc: 00018063 beqz gp,800002cc -800002d0: 00119193 slli gp,gp,0x1 -800002d4: 0011e193 ori gp,gp,1 -800002d8: 05d00893 li a7,93 -800002dc: 00018513 mv a0,gp -800002e0: 00000073 ecall - -800002e4 : -800002e4: 0ff0000f fence -800002e8: 00100193 li gp,1 -800002ec: 05d00893 li a7,93 -800002f0: 00000513 li a0,0 -800002f4: 00000073 ecall -800002f8: c0001073 unimp -800002fc: 0000 unimp -800002fe: 0000 unimp -80000300: 0000 unimp -80000302: 0000 unimp diff --git a/benchmarks/riscv_tests/rv32ui-p-andi.hex b/benchmarks/riscv_tests/rv32ui-p-andi.hex deleted file mode 100644 index 8a63aef3..00000000 --- a/benchmarks/riscv_tests/rv32ui-p-andi.hex +++ /dev/null @@ -1,53 +0,0 @@ -:0200000480007A -:100000006F00C004732F2034930F8000630AFF0336 -:10001000930F90006306FF03930FB0006302FF038A -:10002000170F0080130F0FFE63040F0067000F000F -:10003000732F203463540F006F004000136E9E53E3 -:10004000171F00002320CFFD6FF09FFF732540F1A5 -:100050006310050073251030635805000F00F00F82 -:10006000130E100073000000130E00009702000032 -:10007000938282F973905230735020307350303035 -:1000800073504030970200809382C2F7638C020065 -:10009000739052109302B01A739022307323203061 -:1000A000E39E62F873500030970200009382420191 -:1000B00073901234732540F173002030B70001FFB4 -:1000C000938000F093F1F0F0B70E01FF938E0EF0E5 -:1000D000130E20006394D11BB710F00F938000FF24 -:1000E00093F1000F930E000F130E30006398D11997 -:1000F000B700FF009380F00F93F1F070930EF000C3 -:10010000130E4000639CD117B7F00FF09380F000FE -:1001100093F1000F930E0000130E50006390D1175F -:10012000B70001FF938000F093F0000F930E0000E2 -:10013000130E60006394D01513020000B710F00F87 -:10014000938000FF93F1F0701383010013021200FB -:1001500093022000E31452FE930E0070130E700001 -:10016000631ED31113020000B700FF009380F00F4D -:1001700093F1000F1300000013830100130212001B -:1001800093022000E31252FE930E000F130E800024 -:100190006316D30F13020000B7F00FF09380F00046 -:1001A00093F1F0F01300000013000000138301002E -:1001B0001302120093022000E31052FEB7FE0FF06C -:1001C000938EFE00130E9000631AD30B13020000EF -:1001D000B710F00F938000FF93F1F070130212003C -:1001E00093022000E31652FE930E0070130EA0003F -:1001F0006396D10913020000B700FF009380F00F4F -:100200001300000093F1000F13021200930220006C -:10021000E31452FE930E000F130EB0006390D1074B -:1002200013020000B7F00FF09380F00013000000FD -:100230001300000093F1F0701302120093022000EB -:10024000E31252FE930EF000130EC0006398D10328 -:100250009370000F930E0000130ED0006390D00334 -:10026000B700FF009380F00F13F0F070930E0000C2 -:10027000130EE0006314D001631CC0010F00F00FE7 -:1002800063000E00131E1E00136E1E00730000009C -:100290000F00F00F130E100073000000731000C069 -:1002A000000000000000000000000000000000004E -:1002B000000000000000000000000000000000003E -:0402C000000000003A -:1010000000000000000000000000000000000000E0 -:1010100000000000000000000000000000000000D0 -:1010200000000000000000000000000000000000C0 -:1010300000000000000000000000000000000000B0 -:081040000000000000000000A8 -:040000058000200057 -:00000001FF diff --git a/benchmarks/riscv_tests/rv32ui-p-auipc.dump b/benchmarks/riscv_tests/rv32ui-p-auipc.dump deleted file mode 100644 index 9c86bd9f..00000000 --- a/benchmarks/riscv_tests/rv32ui-p-auipc.dump +++ /dev/null @@ -1,149 +0,0 @@ - -rv32ui-p-auipc: file format elf32-littleriscv - - -Disassembly of section .text.init: - -80000000 <_start>: -80000000: 04c0006f j 8000004c - -80000004 : -80000004: 34202f73 csrr t5,mcause -80000008: 00800f93 li t6,8 -8000000c: 03ff0a63 beq t5,t6,80000040 -80000010: 00900f93 li t6,9 -80000014: 03ff0663 beq t5,t6,80000040 -80000018: 00b00f93 li t6,11 -8000001c: 03ff0263 beq t5,t6,80000040 -80000020: 80000f17 auipc t5,0x80000 -80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> -80000028: 000f0463 beqz t5,80000030 -8000002c: 000f0067 jr t5 -80000030: 34202f73 csrr t5,mcause -80000034: 000f5463 bgez t5,8000003c -80000038: 0040006f j 8000003c - -8000003c : -8000003c: 5391e193 ori gp,gp,1337 - -80000040 : -80000040: 00001f17 auipc t5,0x1 -80000044: fc3f2023 sw gp,-64(t5) # 80001000 -80000048: ff9ff06f j 80000040 - -8000004c : -8000004c: f1402573 csrr a0,mhartid -80000050: 00051063 bnez a0,80000050 -80000054: 00000297 auipc t0,0x0 -80000058: 01028293 addi t0,t0,16 # 80000064 -8000005c: 30529073 csrw mtvec,t0 -80000060: 18005073 csrwi satp,0 -80000064: 00000297 auipc t0,0x0 -80000068: 02028293 addi t0,t0,32 # 80000084 -8000006c: 30529073 csrw mtvec,t0 -80000070: 800002b7 lui t0,0x80000 -80000074: fff28293 addi t0,t0,-1 # 7fffffff <_end+0xffffdfff> -80000078: 3b029073 csrw pmpaddr0,t0 -8000007c: 01f00293 li t0,31 -80000080: 3a029073 csrw pmpcfg0,t0 -80000084: 00000297 auipc t0,0x0 -80000088: 01828293 addi t0,t0,24 # 8000009c -8000008c: 30529073 csrw mtvec,t0 -80000090: 30205073 csrwi medeleg,0 -80000094: 30305073 csrwi mideleg,0 -80000098: 30405073 csrwi mie,0 -8000009c: 00000193 li gp,0 -800000a0: 00000297 auipc t0,0x0 -800000a4: f6428293 addi t0,t0,-156 # 80000004 -800000a8: 30529073 csrw mtvec,t0 -800000ac: 00100513 li a0,1 -800000b0: 01f51513 slli a0,a0,0x1f -800000b4: 00054c63 bltz a0,800000cc -800000b8: 0ff0000f fence -800000bc: 00100193 li gp,1 -800000c0: 05d00893 li a7,93 -800000c4: 00000513 li a0,0 -800000c8: 00000073 ecall -800000cc: 80000297 auipc t0,0x80000 -800000d0: f3428293 addi t0,t0,-204 # 0 <_start-0x80000000> -800000d4: 00028e63 beqz t0,800000f0 -800000d8: 10529073 csrw stvec,t0 -800000dc: 0000b2b7 lui t0,0xb -800000e0: 10928293 addi t0,t0,265 # b109 <_start-0x7fff4ef7> -800000e4: 30229073 csrw medeleg,t0 -800000e8: 30202373 csrr t1,medeleg -800000ec: f46298e3 bne t0,t1,8000003c -800000f0: 30005073 csrwi mstatus,0 -800000f4: 00000297 auipc t0,0x0 -800000f8: 01428293 addi t0,t0,20 # 80000108 -800000fc: 34129073 csrw mepc,t0 -80000100: f1402573 csrr a0,mhartid -80000104: 30200073 mret - -80000108 : -80000108: 00002517 auipc a0,0x2 -8000010c: 71c50513 addi a0,a0,1820 # 80002824 <_end+0x824> -80000110: 004005ef jal a1,80000114 -80000114: 40b50533 sub a0,a0,a1 -80000118: 00002eb7 lui t4,0x2 -8000011c: 710e8e93 addi t4,t4,1808 # 2710 <_start-0x7fffd8f0> -80000120: 00200193 li gp,2 -80000124: 03d51463 bne a0,t4,8000014c - -80000128 : -80000128: ffffe517 auipc a0,0xffffe -8000012c: 8fc50513 addi a0,a0,-1796 # 7fffda24 <_start-0x25dc> -80000130: 004005ef jal a1,80000134 -80000134: 40b50533 sub a0,a0,a1 -80000138: ffffeeb7 lui t4,0xffffe -8000013c: 8f0e8e93 addi t4,t4,-1808 # ffffd8f0 <_end+0x7fffb8f0> -80000140: 00300193 li gp,3 -80000144: 01d51463 bne a0,t4,8000014c -80000148: 02301063 bne zero,gp,80000168 - -8000014c : -8000014c: 0ff0000f fence -80000150: 00018063 beqz gp,80000150 -80000154: 00119193 slli gp,gp,0x1 -80000158: 0011e193 ori gp,gp,1 -8000015c: 05d00893 li a7,93 -80000160: 00018513 mv a0,gp -80000164: 00000073 ecall - -80000168 : -80000168: 0ff0000f fence -8000016c: 00100193 li gp,1 -80000170: 05d00893 li a7,93 -80000174: 00000513 li a0,0 -80000178: 00000073 ecall -8000017c: c0001073 unimp -80000180: 0000 unimp -80000182: 0000 unimp -80000184: 0000 unimp -80000186: 0000 unimp -80000188: 0000 unimp -8000018a: 0000 unimp -8000018c: 0000 unimp -8000018e: 0000 unimp -80000190: 0000 unimp -80000192: 0000 unimp -80000194: 0000 unimp -80000196: 0000 unimp -80000198: 0000 unimp -8000019a: 0000 unimp -8000019c: 0000 unimp -8000019e: 0000 unimp -800001a0: 0000 unimp -800001a2: 0000 unimp -800001a4: 0000 unimp -800001a6: 0000 unimp -800001a8: 0000 unimp -800001aa: 0000 unimp -800001ac: 0000 unimp -800001ae: 0000 unimp -800001b0: 0000 unimp -800001b2: 0000 unimp -800001b4: 0000 unimp -800001b6: 0000 unimp -800001b8: 0000 unimp -800001ba: 0000 unimp diff --git a/benchmarks/riscv_tests/rv32ui-p-auipc.hex b/benchmarks/riscv_tests/rv32ui-p-auipc.hex deleted file mode 100644 index 6d15d3d8..00000000 --- a/benchmarks/riscv_tests/rv32ui-p-auipc.hex +++ /dev/null @@ -1,28 +0,0 @@ -:0200000480007A -:100000006F00C004732F2034930F8000630AFF0336 -:10001000930F90006306FF03930FB0006302FF038A -:10002000170F0080130F0FFE63040F0067000F000F -:10003000732F203463540F006F004000136E9E53E3 -:10004000171F00002320CFFD6FF09FFF732540F1A5 -:100050006310050073251030635805000F00F00F82 -:10006000130E100073000000130E00009702000032 -:10007000938282F973905230735020307350303035 -:1000800073504030970200809382C2F7638C020065 -:10009000739052109302B01A739022307323203061 -:1000A000E39E62F873500030970200009382420191 -:1000B00073901234732540F1730020301300000058 -:1000C000172500001305C571EF0540003305B54045 -:1000D000B72E0000938E0E71130E20006314D5030B -:1000E00017E5FFFF1305C58FEF0540003305B54049 -:1000F000B7EEFFFF938E0E8F130E30006314D50101 -:10010000631CC0010F00F00F63000E00131E1E00E1 -:10011000136E1E00730000000F00F00F130E10008E -:1001200073000000731000C0000000000000000019 -:1001300000000000000000000000000000000000BF -:1010000000000000000000000000000000000000E0 -:1010100000000000000000000000000000000000D0 -:1010200000000000000000000000000000000000C0 -:1010300000000000000000000000000000000000B0 -:081040000000000000000000A8 -:040000058000200057 -:00000001FF diff --git a/benchmarks/riscv_tests/rv32ui-p-beq.dump b/benchmarks/riscv_tests/rv32ui-p-beq.dump deleted file mode 100644 index fcf03f41..00000000 --- a/benchmarks/riscv_tests/rv32ui-p-beq.dump +++ /dev/null @@ -1,318 +0,0 @@ - -rv32ui-p-beq: file format elf32-littleriscv - - -Disassembly of section .text.init: - -80000000 <_start>: -80000000: 04c0006f j 8000004c - -80000004 : -80000004: 34202f73 csrr t5,mcause -80000008: 00800f93 li t6,8 -8000000c: 03ff0a63 beq t5,t6,80000040 -80000010: 00900f93 li t6,9 -80000014: 03ff0663 beq t5,t6,80000040 -80000018: 00b00f93 li t6,11 -8000001c: 03ff0263 beq t5,t6,80000040 -80000020: 80000f17 auipc t5,0x80000 -80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> -80000028: 000f0463 beqz t5,80000030 -8000002c: 000f0067 jr t5 -80000030: 34202f73 csrr t5,mcause -80000034: 000f5463 bgez t5,8000003c -80000038: 0040006f j 8000003c - -8000003c : -8000003c: 5391e193 ori gp,gp,1337 - -80000040 : -80000040: 00001f17 auipc t5,0x1 -80000044: fc3f2023 sw gp,-64(t5) # 80001000 -80000048: ff9ff06f j 80000040 - -8000004c : -8000004c: f1402573 csrr a0,mhartid -80000050: 00051063 bnez a0,80000050 -80000054: 00000297 auipc t0,0x0 -80000058: 01028293 addi t0,t0,16 # 80000064 -8000005c: 30529073 csrw mtvec,t0 -80000060: 18005073 csrwi satp,0 -80000064: 00000297 auipc t0,0x0 -80000068: 02028293 addi t0,t0,32 # 80000084 -8000006c: 30529073 csrw mtvec,t0 -80000070: 800002b7 lui t0,0x80000 -80000074: fff28293 addi t0,t0,-1 # 7fffffff <_end+0xffffdfff> -80000078: 3b029073 csrw pmpaddr0,t0 -8000007c: 01f00293 li t0,31 -80000080: 3a029073 csrw pmpcfg0,t0 -80000084: 00000297 auipc t0,0x0 -80000088: 01828293 addi t0,t0,24 # 8000009c -8000008c: 30529073 csrw mtvec,t0 -80000090: 30205073 csrwi medeleg,0 -80000094: 30305073 csrwi mideleg,0 -80000098: 30405073 csrwi mie,0 -8000009c: 00000193 li gp,0 -800000a0: 00000297 auipc t0,0x0 -800000a4: f6428293 addi t0,t0,-156 # 80000004 -800000a8: 30529073 csrw mtvec,t0 -800000ac: 00100513 li a0,1 -800000b0: 01f51513 slli a0,a0,0x1f -800000b4: 00054c63 bltz a0,800000cc -800000b8: 0ff0000f fence -800000bc: 00100193 li gp,1 -800000c0: 05d00893 li a7,93 -800000c4: 00000513 li a0,0 -800000c8: 00000073 ecall -800000cc: 80000297 auipc t0,0x80000 -800000d0: f3428293 addi t0,t0,-204 # 0 <_start-0x80000000> -800000d4: 00028e63 beqz t0,800000f0 -800000d8: 10529073 csrw stvec,t0 -800000dc: 0000b2b7 lui t0,0xb -800000e0: 10928293 addi t0,t0,265 # b109 <_start-0x7fff4ef7> -800000e4: 30229073 csrw medeleg,t0 -800000e8: 30202373 csrr t1,medeleg -800000ec: f46298e3 bne t0,t1,8000003c -800000f0: 30005073 csrwi mstatus,0 -800000f4: 00000297 auipc t0,0x0 -800000f8: 01428293 addi t0,t0,20 # 80000108 -800000fc: 34129073 csrw mepc,t0 -80000100: f1402573 csrr a0,mhartid -80000104: 30200073 mret - -80000108 : -80000108: 00200193 li gp,2 -8000010c: 00000093 li ra,0 -80000110: 00000113 li sp,0 -80000114: 00208663 beq ra,sp,80000120 -80000118: 2a301863 bne zero,gp,800003c8 -8000011c: 00301663 bne zero,gp,80000128 -80000120: fe208ee3 beq ra,sp,8000011c -80000124: 2a301263 bne zero,gp,800003c8 - -80000128 : -80000128: 00300193 li gp,3 -8000012c: 00100093 li ra,1 -80000130: 00100113 li sp,1 -80000134: 00208663 beq ra,sp,80000140 -80000138: 28301863 bne zero,gp,800003c8 -8000013c: 00301663 bne zero,gp,80000148 -80000140: fe208ee3 beq ra,sp,8000013c -80000144: 28301263 bne zero,gp,800003c8 - -80000148 : -80000148: 00400193 li gp,4 -8000014c: fff00093 li ra,-1 -80000150: fff00113 li sp,-1 -80000154: 00208663 beq ra,sp,80000160 -80000158: 26301863 bne zero,gp,800003c8 -8000015c: 00301663 bne zero,gp,80000168 -80000160: fe208ee3 beq ra,sp,8000015c -80000164: 26301263 bne zero,gp,800003c8 - -80000168 : -80000168: 00500193 li gp,5 -8000016c: 00000093 li ra,0 -80000170: 00100113 li sp,1 -80000174: 00208463 beq ra,sp,8000017c -80000178: 00301463 bne zero,gp,80000180 -8000017c: 24301663 bne zero,gp,800003c8 -80000180: fe208ee3 beq ra,sp,8000017c - -80000184 : -80000184: 00600193 li gp,6 -80000188: 00100093 li ra,1 -8000018c: 00000113 li sp,0 -80000190: 00208463 beq ra,sp,80000198 -80000194: 00301463 bne zero,gp,8000019c -80000198: 22301863 bne zero,gp,800003c8 -8000019c: fe208ee3 beq ra,sp,80000198 - -800001a0 : -800001a0: 00700193 li gp,7 -800001a4: fff00093 li ra,-1 -800001a8: 00100113 li sp,1 -800001ac: 00208463 beq ra,sp,800001b4 -800001b0: 00301463 bne zero,gp,800001b8 -800001b4: 20301a63 bne zero,gp,800003c8 -800001b8: fe208ee3 beq ra,sp,800001b4 - -800001bc : -800001bc: 00800193 li gp,8 -800001c0: 00100093 li ra,1 -800001c4: fff00113 li sp,-1 -800001c8: 00208463 beq ra,sp,800001d0 -800001cc: 00301463 bne zero,gp,800001d4 -800001d0: 1e301c63 bne zero,gp,800003c8 -800001d4: fe208ee3 beq ra,sp,800001d0 - -800001d8 : -800001d8: 00900193 li gp,9 -800001dc: 00000213 li tp,0 -800001e0: 00000093 li ra,0 -800001e4: fff00113 li sp,-1 -800001e8: 1e208063 beq ra,sp,800003c8 -800001ec: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -800001f0: 00200293 li t0,2 -800001f4: fe5216e3 bne tp,t0,800001e0 - -800001f8 : -800001f8: 00a00193 li gp,10 -800001fc: 00000213 li tp,0 -80000200: 00000093 li ra,0 -80000204: fff00113 li sp,-1 -80000208: 00000013 nop -8000020c: 1a208e63 beq ra,sp,800003c8 -80000210: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000214: 00200293 li t0,2 -80000218: fe5214e3 bne tp,t0,80000200 - -8000021c : -8000021c: 00b00193 li gp,11 -80000220: 00000213 li tp,0 -80000224: 00000093 li ra,0 -80000228: fff00113 li sp,-1 -8000022c: 00000013 nop -80000230: 00000013 nop -80000234: 18208a63 beq ra,sp,800003c8 -80000238: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -8000023c: 00200293 li t0,2 -80000240: fe5212e3 bne tp,t0,80000224 - -80000244 : -80000244: 00c00193 li gp,12 -80000248: 00000213 li tp,0 -8000024c: 00000093 li ra,0 -80000250: 00000013 nop -80000254: fff00113 li sp,-1 -80000258: 16208863 beq ra,sp,800003c8 -8000025c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000260: 00200293 li t0,2 -80000264: fe5214e3 bne tp,t0,8000024c - -80000268 : -80000268: 00d00193 li gp,13 -8000026c: 00000213 li tp,0 -80000270: 00000093 li ra,0 -80000274: 00000013 nop -80000278: fff00113 li sp,-1 -8000027c: 00000013 nop -80000280: 14208463 beq ra,sp,800003c8 -80000284: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000288: 00200293 li t0,2 -8000028c: fe5212e3 bne tp,t0,80000270 - -80000290 : -80000290: 00e00193 li gp,14 -80000294: 00000213 li tp,0 -80000298: 00000093 li ra,0 -8000029c: 00000013 nop -800002a0: 00000013 nop -800002a4: fff00113 li sp,-1 -800002a8: 12208063 beq ra,sp,800003c8 -800002ac: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -800002b0: 00200293 li t0,2 -800002b4: fe5212e3 bne tp,t0,80000298 - -800002b8 : -800002b8: 00f00193 li gp,15 -800002bc: 00000213 li tp,0 -800002c0: 00000093 li ra,0 -800002c4: fff00113 li sp,-1 -800002c8: 10208063 beq ra,sp,800003c8 -800002cc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -800002d0: 00200293 li t0,2 -800002d4: fe5216e3 bne tp,t0,800002c0 - -800002d8 : -800002d8: 01000193 li gp,16 -800002dc: 00000213 li tp,0 -800002e0: 00000093 li ra,0 -800002e4: fff00113 li sp,-1 -800002e8: 00000013 nop -800002ec: 0c208e63 beq ra,sp,800003c8 -800002f0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -800002f4: 00200293 li t0,2 -800002f8: fe5214e3 bne tp,t0,800002e0 - -800002fc : -800002fc: 01100193 li gp,17 -80000300: 00000213 li tp,0 -80000304: 00000093 li ra,0 -80000308: fff00113 li sp,-1 -8000030c: 00000013 nop -80000310: 00000013 nop -80000314: 0a208a63 beq ra,sp,800003c8 -80000318: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -8000031c: 00200293 li t0,2 -80000320: fe5212e3 bne tp,t0,80000304 - -80000324 : -80000324: 01200193 li gp,18 -80000328: 00000213 li tp,0 -8000032c: 00000093 li ra,0 -80000330: 00000013 nop -80000334: fff00113 li sp,-1 -80000338: 08208863 beq ra,sp,800003c8 -8000033c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000340: 00200293 li t0,2 -80000344: fe5214e3 bne tp,t0,8000032c - -80000348 : -80000348: 01300193 li gp,19 -8000034c: 00000213 li tp,0 -80000350: 00000093 li ra,0 -80000354: 00000013 nop -80000358: fff00113 li sp,-1 -8000035c: 00000013 nop -80000360: 06208463 beq ra,sp,800003c8 -80000364: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000368: 00200293 li t0,2 -8000036c: fe5212e3 bne tp,t0,80000350 - -80000370 : -80000370: 01400193 li gp,20 -80000374: 00000213 li tp,0 -80000378: 00000093 li ra,0 -8000037c: 00000013 nop -80000380: 00000013 nop -80000384: fff00113 li sp,-1 -80000388: 04208063 beq ra,sp,800003c8 -8000038c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000390: 00200293 li t0,2 -80000394: fe5212e3 bne tp,t0,80000378 - -80000398 : -80000398: 00100093 li ra,1 -8000039c: 00000a63 beqz zero,800003b0 -800003a0: 00108093 addi ra,ra,1 -800003a4: 00108093 addi ra,ra,1 -800003a8: 00108093 addi ra,ra,1 -800003ac: 00108093 addi ra,ra,1 -800003b0: 00108093 addi ra,ra,1 -800003b4: 00108093 addi ra,ra,1 -800003b8: 00300e93 li t4,3 -800003bc: 01500193 li gp,21 -800003c0: 01d09463 bne ra,t4,800003c8 -800003c4: 02301063 bne zero,gp,800003e4 - -800003c8 : -800003c8: 0ff0000f fence -800003cc: 00018063 beqz gp,800003cc -800003d0: 00119193 slli gp,gp,0x1 -800003d4: 0011e193 ori gp,gp,1 -800003d8: 05d00893 li a7,93 -800003dc: 00018513 mv a0,gp -800003e0: 00000073 ecall - -800003e4 : -800003e4: 0ff0000f fence -800003e8: 00100193 li gp,1 -800003ec: 05d00893 li a7,93 -800003f0: 00000513 li a0,0 -800003f4: 00000073 ecall -800003f8: c0001073 unimp -800003fc: 0000 unimp -800003fe: 0000 unimp -80000400: 0000 unimp -80000402: 0000 unimp diff --git a/benchmarks/riscv_tests/rv32ui-p-beq.hex b/benchmarks/riscv_tests/rv32ui-p-beq.hex deleted file mode 100644 index 5983d718..00000000 --- a/benchmarks/riscv_tests/rv32ui-p-beq.hex +++ /dev/null @@ -1,69 +0,0 @@ -:0200000480007A -:100000006F00C004732F2034930F8000630AFF0336 -:10001000930F90006306FF03930FB0006302FF038A -:10002000170F0080130F0FFE63040F0067000F000F -:10003000732F203463540F006F004000136E9E53E3 -:10004000171F00002320CFFD6FF09FFF732540F1A5 -:100050006310050073251030635805000F00F00F82 -:10006000130E100073000000130E00009702000032 -:10007000938282F973905230735020307350303035 -:1000800073504030970200809382C2F7638C020065 -:10009000739052109302B01A739022307323203061 -:1000A000E39E62F873500030970200009382420191 -:1000B00073901234732540F173002030130E20002A -:1000C0009300000013010000638620006318C02B1A -:1000D0006316C001E38E20FE6312C02B130E3000A6 -:1000E0009300100013011000638620006318C029DC -:1000F0006316C001E38E20FE6312C029130E400078 -:100100009300F0FF1301F0FF638620006318C027FF -:100110006316C001E38E20FE6312C027130E500049 -:100120009300000013011000638420006314C001D9 -:100130006316C025E38E20FE130E600093001000AE -:1001400013010000638420006314C0016318C023FE -:10015000E38E20FE130E70009300F0FF13011000D9 -:10016000638420006314C001631AC021E38E20FE63 -:10017000130E8000930010001301F0FF6384200031 -:100180006314C001631CC01FE38E20FE130E900099 -:1001900013020000930000001301F0FF6380201E93 -:1001A0001302120093022000E31652FE130EA00069 -:1001B00013020000930000001301F0FF1300000081 -:1001C000638E201A1302120093022000E31452FEE1 -:1001D000130EB00013020000930000001301F0FFA3 -:1001E0001300000013000000638A2018130212009D -:1001F00093022000E31252FE130EC000130200000F -:1002000093000000130000001301F0FF6388201624 -:100210001302120093022000E31452FE130ED000CA -:100220001302000093000000130000001301F0FF10 -:1002300013000000638420141302120093022000B4 -:10024000E31252FE130EE0001302000093000000C0 -:1002500013000000130000001301F0FF6380201260 -:100260001302120093022000E31252FE130EF0005C -:1002700013020000930000001301F0FF63802010C0 -:100280001302120093022000E31652FE130E000127 -:1002900013020000930000001301F0FF13000000A0 -:1002A000638E200C1302120093022000E31452FE0E -:1002B000130E100113020000930000001301F0FF61 -:1002C0001300000013000000638A200A13021200CA -:1002D00093022000E31252FE130E200113020000CD -:1002E00093000000130000001301F0FF6388200852 -:1002F0001302120093022000E31452FE130E300189 -:100300001302000093000000130000001301F0FF2F -:1003100013000000638420061302120093022000E1 -:10032000E31252FE130E400113020000930000007E -:1003300013000000130000001301F0FF638020048D -:100340001302120093022000E31252FE93001000E9 -:10035000630A0000938010009380100093801000C7 -:10036000938010009380100093801000930E300053 -:10037000130E50016394D001631CC0010F00F00FF5 -:1003800063000E00131E1E00136E1E00730000009B -:100390000F00F00F130E100073000000731000C068 -:1003A000000000000000000000000000000000004D -:1003B000000000000000000000000000000000003D -:0403C0000000000039 -:1010000000000000000000000000000000000000E0 -:1010100000000000000000000000000000000000D0 -:1010200000000000000000000000000000000000C0 -:1010300000000000000000000000000000000000B0 -:081040000000000000000000A8 -:040000058000200057 -:00000001FF diff --git a/benchmarks/riscv_tests/rv32ui-p-bge.dump b/benchmarks/riscv_tests/rv32ui-p-bge.dump deleted file mode 100644 index 52dbf591..00000000 --- a/benchmarks/riscv_tests/rv32ui-p-bge.dump +++ /dev/null @@ -1,364 +0,0 @@ - -rv32ui-p-bge: file format elf32-littleriscv - - -Disassembly of section .text.init: - -80000000 <_start>: -80000000: 04c0006f j 8000004c - -80000004 : -80000004: 34202f73 csrr t5,mcause -80000008: 00800f93 li t6,8 -8000000c: 03ff0a63 beq t5,t6,80000040 -80000010: 00900f93 li t6,9 -80000014: 03ff0663 beq t5,t6,80000040 -80000018: 00b00f93 li t6,11 -8000001c: 03ff0263 beq t5,t6,80000040 -80000020: 80000f17 auipc t5,0x80000 -80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> -80000028: 000f0463 beqz t5,80000030 -8000002c: 000f0067 jr t5 -80000030: 34202f73 csrr t5,mcause -80000034: 000f5463 bgez t5,8000003c -80000038: 0040006f j 8000003c - -8000003c : -8000003c: 5391e193 ori gp,gp,1337 - -80000040 : -80000040: 00001f17 auipc t5,0x1 -80000044: fc3f2023 sw gp,-64(t5) # 80001000 -80000048: ff9ff06f j 80000040 - -8000004c : -8000004c: f1402573 csrr a0,mhartid -80000050: 00051063 bnez a0,80000050 -80000054: 00000297 auipc t0,0x0 -80000058: 01028293 addi t0,t0,16 # 80000064 -8000005c: 30529073 csrw mtvec,t0 -80000060: 18005073 csrwi satp,0 -80000064: 00000297 auipc t0,0x0 -80000068: 02028293 addi t0,t0,32 # 80000084 -8000006c: 30529073 csrw mtvec,t0 -80000070: 800002b7 lui t0,0x80000 -80000074: fff28293 addi t0,t0,-1 # 7fffffff <_end+0xffffdfff> -80000078: 3b029073 csrw pmpaddr0,t0 -8000007c: 01f00293 li t0,31 -80000080: 3a029073 csrw pmpcfg0,t0 -80000084: 00000297 auipc t0,0x0 -80000088: 01828293 addi t0,t0,24 # 8000009c -8000008c: 30529073 csrw mtvec,t0 -80000090: 30205073 csrwi medeleg,0 -80000094: 30305073 csrwi mideleg,0 -80000098: 30405073 csrwi mie,0 -8000009c: 00000193 li gp,0 -800000a0: 00000297 auipc t0,0x0 -800000a4: f6428293 addi t0,t0,-156 # 80000004 -800000a8: 30529073 csrw mtvec,t0 -800000ac: 00100513 li a0,1 -800000b0: 01f51513 slli a0,a0,0x1f -800000b4: 00054c63 bltz a0,800000cc -800000b8: 0ff0000f fence -800000bc: 00100193 li gp,1 -800000c0: 05d00893 li a7,93 -800000c4: 00000513 li a0,0 -800000c8: 00000073 ecall -800000cc: 80000297 auipc t0,0x80000 -800000d0: f3428293 addi t0,t0,-204 # 0 <_start-0x80000000> -800000d4: 00028e63 beqz t0,800000f0 -800000d8: 10529073 csrw stvec,t0 -800000dc: 0000b2b7 lui t0,0xb -800000e0: 10928293 addi t0,t0,265 # b109 <_start-0x7fff4ef7> -800000e4: 30229073 csrw medeleg,t0 -800000e8: 30202373 csrr t1,medeleg -800000ec: f46298e3 bne t0,t1,8000003c -800000f0: 30005073 csrwi mstatus,0 -800000f4: 00000297 auipc t0,0x0 -800000f8: 01428293 addi t0,t0,20 # 80000108 -800000fc: 34129073 csrw mepc,t0 -80000100: f1402573 csrr a0,mhartid -80000104: 30200073 mret - -80000108 : -80000108: 00200193 li gp,2 -8000010c: 00000093 li ra,0 -80000110: 00000113 li sp,0 -80000114: 0020d663 bge ra,sp,80000120 -80000118: 30301863 bne zero,gp,80000428 -8000011c: 00301663 bne zero,gp,80000128 -80000120: fe20dee3 bge ra,sp,8000011c -80000124: 30301263 bne zero,gp,80000428 - -80000128 : -80000128: 00300193 li gp,3 -8000012c: 00100093 li ra,1 -80000130: 00100113 li sp,1 -80000134: 0020d663 bge ra,sp,80000140 -80000138: 2e301863 bne zero,gp,80000428 -8000013c: 00301663 bne zero,gp,80000148 -80000140: fe20dee3 bge ra,sp,8000013c -80000144: 2e301263 bne zero,gp,80000428 - -80000148 : -80000148: 00400193 li gp,4 -8000014c: fff00093 li ra,-1 -80000150: fff00113 li sp,-1 -80000154: 0020d663 bge ra,sp,80000160 -80000158: 2c301863 bne zero,gp,80000428 -8000015c: 00301663 bne zero,gp,80000168 -80000160: fe20dee3 bge ra,sp,8000015c -80000164: 2c301263 bne zero,gp,80000428 - -80000168 : -80000168: 00500193 li gp,5 -8000016c: 00100093 li ra,1 -80000170: 00000113 li sp,0 -80000174: 0020d663 bge ra,sp,80000180 -80000178: 2a301863 bne zero,gp,80000428 -8000017c: 00301663 bne zero,gp,80000188 -80000180: fe20dee3 bge ra,sp,8000017c -80000184: 2a301263 bne zero,gp,80000428 - -80000188 : -80000188: 00600193 li gp,6 -8000018c: 00100093 li ra,1 -80000190: fff00113 li sp,-1 -80000194: 0020d663 bge ra,sp,800001a0 -80000198: 28301863 bne zero,gp,80000428 -8000019c: 00301663 bne zero,gp,800001a8 -800001a0: fe20dee3 bge ra,sp,8000019c -800001a4: 28301263 bne zero,gp,80000428 - -800001a8 : -800001a8: 00700193 li gp,7 -800001ac: fff00093 li ra,-1 -800001b0: ffe00113 li sp,-2 -800001b4: 0020d663 bge ra,sp,800001c0 -800001b8: 26301863 bne zero,gp,80000428 -800001bc: 00301663 bne zero,gp,800001c8 -800001c0: fe20dee3 bge ra,sp,800001bc -800001c4: 26301263 bne zero,gp,80000428 - -800001c8 : -800001c8: 00800193 li gp,8 -800001cc: 00000093 li ra,0 -800001d0: 00100113 li sp,1 -800001d4: 0020d463 bge ra,sp,800001dc -800001d8: 00301463 bne zero,gp,800001e0 -800001dc: 24301663 bne zero,gp,80000428 -800001e0: fe20dee3 bge ra,sp,800001dc - -800001e4 : -800001e4: 00900193 li gp,9 -800001e8: fff00093 li ra,-1 -800001ec: 00100113 li sp,1 -800001f0: 0020d463 bge ra,sp,800001f8 -800001f4: 00301463 bne zero,gp,800001fc -800001f8: 22301863 bne zero,gp,80000428 -800001fc: fe20dee3 bge ra,sp,800001f8 - -80000200 : -80000200: 00a00193 li gp,10 -80000204: ffe00093 li ra,-2 -80000208: fff00113 li sp,-1 -8000020c: 0020d463 bge ra,sp,80000214 -80000210: 00301463 bne zero,gp,80000218 -80000214: 20301a63 bne zero,gp,80000428 -80000218: fe20dee3 bge ra,sp,80000214 - -8000021c : -8000021c: 00b00193 li gp,11 -80000220: ffe00093 li ra,-2 -80000224: 00100113 li sp,1 -80000228: 0020d463 bge ra,sp,80000230 -8000022c: 00301463 bne zero,gp,80000234 -80000230: 1e301c63 bne zero,gp,80000428 -80000234: fe20dee3 bge ra,sp,80000230 - -80000238 : -80000238: 00c00193 li gp,12 -8000023c: 00000213 li tp,0 -80000240: fff00093 li ra,-1 -80000244: 00000113 li sp,0 -80000248: 1e20d063 bge ra,sp,80000428 -8000024c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000250: 00200293 li t0,2 -80000254: fe5216e3 bne tp,t0,80000240 - -80000258 : -80000258: 00d00193 li gp,13 -8000025c: 00000213 li tp,0 -80000260: fff00093 li ra,-1 -80000264: 00000113 li sp,0 -80000268: 00000013 nop -8000026c: 1a20de63 bge ra,sp,80000428 -80000270: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000274: 00200293 li t0,2 -80000278: fe5214e3 bne tp,t0,80000260 - -8000027c : -8000027c: 00e00193 li gp,14 -80000280: 00000213 li tp,0 -80000284: fff00093 li ra,-1 -80000288: 00000113 li sp,0 -8000028c: 00000013 nop -80000290: 00000013 nop -80000294: 1820da63 bge ra,sp,80000428 -80000298: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -8000029c: 00200293 li t0,2 -800002a0: fe5212e3 bne tp,t0,80000284 - -800002a4 : -800002a4: 00f00193 li gp,15 -800002a8: 00000213 li tp,0 -800002ac: fff00093 li ra,-1 -800002b0: 00000013 nop -800002b4: 00000113 li sp,0 -800002b8: 1620d863 bge ra,sp,80000428 -800002bc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -800002c0: 00200293 li t0,2 -800002c4: fe5214e3 bne tp,t0,800002ac - -800002c8 : -800002c8: 01000193 li gp,16 -800002cc: 00000213 li tp,0 -800002d0: fff00093 li ra,-1 -800002d4: 00000013 nop -800002d8: 00000113 li sp,0 -800002dc: 00000013 nop -800002e0: 1420d463 bge ra,sp,80000428 -800002e4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -800002e8: 00200293 li t0,2 -800002ec: fe5212e3 bne tp,t0,800002d0 - -800002f0 : -800002f0: 01100193 li gp,17 -800002f4: 00000213 li tp,0 -800002f8: fff00093 li ra,-1 -800002fc: 00000013 nop -80000300: 00000013 nop -80000304: 00000113 li sp,0 -80000308: 1220d063 bge ra,sp,80000428 -8000030c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000310: 00200293 li t0,2 -80000314: fe5212e3 bne tp,t0,800002f8 - -80000318 : -80000318: 01200193 li gp,18 -8000031c: 00000213 li tp,0 -80000320: fff00093 li ra,-1 -80000324: 00000113 li sp,0 -80000328: 1020d063 bge ra,sp,80000428 -8000032c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000330: 00200293 li t0,2 -80000334: fe5216e3 bne tp,t0,80000320 - -80000338 : -80000338: 01300193 li gp,19 -8000033c: 00000213 li tp,0 -80000340: fff00093 li ra,-1 -80000344: 00000113 li sp,0 -80000348: 00000013 nop -8000034c: 0c20de63 bge ra,sp,80000428 -80000350: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000354: 00200293 li t0,2 -80000358: fe5214e3 bne tp,t0,80000340 - -8000035c : -8000035c: 01400193 li gp,20 -80000360: 00000213 li tp,0 -80000364: fff00093 li ra,-1 -80000368: 00000113 li sp,0 -8000036c: 00000013 nop -80000370: 00000013 nop -80000374: 0a20da63 bge ra,sp,80000428 -80000378: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -8000037c: 00200293 li t0,2 -80000380: fe5212e3 bne tp,t0,80000364 - -80000384 : -80000384: 01500193 li gp,21 -80000388: 00000213 li tp,0 -8000038c: fff00093 li ra,-1 -80000390: 00000013 nop -80000394: 00000113 li sp,0 -80000398: 0820d863 bge ra,sp,80000428 -8000039c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -800003a0: 00200293 li t0,2 -800003a4: fe5214e3 bne tp,t0,8000038c - -800003a8 : -800003a8: 01600193 li gp,22 -800003ac: 00000213 li tp,0 -800003b0: fff00093 li ra,-1 -800003b4: 00000013 nop -800003b8: 00000113 li sp,0 -800003bc: 00000013 nop -800003c0: 0620d463 bge ra,sp,80000428 -800003c4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -800003c8: 00200293 li t0,2 -800003cc: fe5212e3 bne tp,t0,800003b0 - -800003d0 : -800003d0: 01700193 li gp,23 -800003d4: 00000213 li tp,0 -800003d8: fff00093 li ra,-1 -800003dc: 00000013 nop -800003e0: 00000013 nop -800003e4: 00000113 li sp,0 -800003e8: 0420d063 bge ra,sp,80000428 -800003ec: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -800003f0: 00200293 li t0,2 -800003f4: fe5212e3 bne tp,t0,800003d8 - -800003f8 : -800003f8: 00100093 li ra,1 -800003fc: 0000da63 bgez ra,80000410 -80000400: 00108093 addi ra,ra,1 -80000404: 00108093 addi ra,ra,1 -80000408: 00108093 addi ra,ra,1 -8000040c: 00108093 addi ra,ra,1 -80000410: 00108093 addi ra,ra,1 -80000414: 00108093 addi ra,ra,1 -80000418: 00300e93 li t4,3 -8000041c: 01800193 li gp,24 -80000420: 01d09463 bne ra,t4,80000428 -80000424: 02301063 bne zero,gp,80000444 - -80000428 : -80000428: 0ff0000f fence -8000042c: 00018063 beqz gp,8000042c -80000430: 00119193 slli gp,gp,0x1 -80000434: 0011e193 ori gp,gp,1 -80000438: 05d00893 li a7,93 -8000043c: 00018513 mv a0,gp -80000440: 00000073 ecall - -80000444 : -80000444: 0ff0000f fence -80000448: 00100193 li gp,1 -8000044c: 05d00893 li a7,93 -80000450: 00000513 li a0,0 -80000454: 00000073 ecall -80000458: c0001073 unimp -8000045c: 0000 unimp -8000045e: 0000 unimp -80000460: 0000 unimp -80000462: 0000 unimp -80000464: 0000 unimp -80000466: 0000 unimp -80000468: 0000 unimp -8000046a: 0000 unimp -8000046c: 0000 unimp -8000046e: 0000 unimp -80000470: 0000 unimp -80000472: 0000 unimp -80000474: 0000 unimp -80000476: 0000 unimp -80000478: 0000 unimp -8000047a: 0000 unimp -8000047c: 0000 unimp -8000047e: 0000 unimp -80000480: 0000 unimp -80000482: 0000 unimp diff --git a/benchmarks/riscv_tests/rv32ui-p-bge.hex b/benchmarks/riscv_tests/rv32ui-p-bge.hex deleted file mode 100644 index ea098af9..00000000 --- a/benchmarks/riscv_tests/rv32ui-p-bge.hex +++ /dev/null @@ -1,73 +0,0 @@ -:0200000480007A -:100000006F00C004732F2034930F8000630AFF0336 -:10001000930F90006306FF03930FB0006302FF038A -:10002000170F0080130F0FFE63040F0067000F000F -:10003000732F203463540F006F004000136E9E53E3 -:10004000171F00002320CFFD6FF09FFF732540F1A5 -:100050006310050073251030635805000F00F00F82 -:10006000130E100073000000130E00009702000032 -:10007000938282F973905230735020307350303035 -:1000800073504030970200809382C2F7638C020065 -:10009000739052109302B01A739022307323203061 -:1000A000E39E62F873500030970200009382420191 -:1000B00073901234732540F173002030130E20002A -:1000C000930000001301000063D620006318C031C4 -:1000D0006316C001E3DE20FE6312C031130E300050 -:1000E000930010001301100063D620006318C02F86 -:1000F0006316C001E3DE20FE6312C02F130E400022 -:100100009300F0FF1301F0FF63D620006318C02DA9 -:100110006316C001E3DE20FE6312C02D130E5000F3 -:10012000930010001301000063D620006318C02B59 -:100130006316C001E3DE20FE6312C02B130E6000C5 -:10014000930010001301F0FF63D620006318C0294C -:100150006316C001E3DE20FE6312C029130E700097 -:100160009300F0FF1301E0FF63D620006318C0275F -:100170006316C001E3DE20FE6312C027130E800069 -:10018000930000001301100063D420006314C00129 -:100190006316C025E3DE20FE130E90009300F0FFEF -:1001A0001301100063D420006314C0016318C0233E -:1001B000E3DE20FE130EA0009300E0FF1301F0FF2A -:1001C00063D420006314C001631AC021E3DE20FE63 -:1001D000130EB0009300E0FF1301100063D4200061 -:1001E0006314C001631CC01FE3DE20FE130EC000B9 -:1001F000130200009300F0FF1301000063D0201EE3 -:100200001302120093022000E31652FE130ED000D8 -:10021000130200009300F0FF130100001300000020 -:1002200063DE201A1302120093022000E31452FE30 -:10023000130EE000130200009300F0FF1301000012 -:10024000130000001300000063DA201813021200EC -:1002500093022000E31252FE130EF000130200007E -:100260009300F0FF130000001301000063D8201674 -:100270001302120093022000E31452FE130E000139 -:10028000130200009300F0FF1300000013010000B0 -:100290001300000063D42014130212009302200004 -:1002A000E31252FE130E1001130200009300F0FF40 -:1002B00013000000130000001301000063D020129F -:1002C0001302120093022000E31252FE130E2001CB -:1002D000130200009300F0FF1301000063D0201010 -:1002E0001302120093022000E31652FE130E300197 -:1002F000130200009300F0FF130100001300000040 -:1003000063DE200C1302120093022000E31452FE5D -:10031000130E4001130200009300F0FF13010000D0 -:10032000130000001300000063DA200A1302120019 -:1003300093022000E31252FE130E5001130200003C -:100340009300F0FF130000001301000063D82008A1 -:100350001302120093022000E31452FE130E6001F8 -:10036000130200009300F0FF1300000013010000CF -:100370001300000063D42006130212009302200031 -:10038000E31252FE130E7001130200009300F0FFFF -:1003900013000000130000001301000063D02004CC -:1003A0001302120093022000E31252FE9300100089 -:1003B00063DA000093801000938010009380100097 -:1003C000938010009380100093801000930E3000F3 -:1003D000130E80016394D001631CC0010F00F00F65 -:1003E00063000E00131E1E00136E1E00730000003B -:1003F0000F00F00F130E100073000000731000C008 -:0404000000000000F8 -:1010000000000000000000000000000000000000E0 -:1010100000000000000000000000000000000000D0 -:1010200000000000000000000000000000000000C0 -:1010300000000000000000000000000000000000B0 -:081040000000000000000000A8 -:040000058000200057 -:00000001FF diff --git a/benchmarks/riscv_tests/rv32ui-p-bgeu.dump b/benchmarks/riscv_tests/rv32ui-p-bgeu.dump deleted file mode 100644 index ed45ab9e..00000000 --- a/benchmarks/riscv_tests/rv32ui-p-bgeu.dump +++ /dev/null @@ -1,383 +0,0 @@ - -rv32ui-p-bgeu: file format elf32-littleriscv - - -Disassembly of section .text.init: - -80000000 <_start>: -80000000: 04c0006f j 8000004c - -80000004 : -80000004: 34202f73 csrr t5,mcause -80000008: 00800f93 li t6,8 -8000000c: 03ff0a63 beq t5,t6,80000040 -80000010: 00900f93 li t6,9 -80000014: 03ff0663 beq t5,t6,80000040 -80000018: 00b00f93 li t6,11 -8000001c: 03ff0263 beq t5,t6,80000040 -80000020: 80000f17 auipc t5,0x80000 -80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> -80000028: 000f0463 beqz t5,80000030 -8000002c: 000f0067 jr t5 -80000030: 34202f73 csrr t5,mcause -80000034: 000f5463 bgez t5,8000003c -80000038: 0040006f j 8000003c - -8000003c : -8000003c: 5391e193 ori gp,gp,1337 - -80000040 : -80000040: 00001f17 auipc t5,0x1 -80000044: fc3f2023 sw gp,-64(t5) # 80001000 -80000048: ff9ff06f j 80000040 - -8000004c : -8000004c: f1402573 csrr a0,mhartid -80000050: 00051063 bnez a0,80000050 -80000054: 00000297 auipc t0,0x0 -80000058: 01028293 addi t0,t0,16 # 80000064 -8000005c: 30529073 csrw mtvec,t0 -80000060: 18005073 csrwi satp,0 -80000064: 00000297 auipc t0,0x0 -80000068: 02028293 addi t0,t0,32 # 80000084 -8000006c: 30529073 csrw mtvec,t0 -80000070: 800002b7 lui t0,0x80000 -80000074: fff28293 addi t0,t0,-1 # 7fffffff <_end+0xffffdfff> -80000078: 3b029073 csrw pmpaddr0,t0 -8000007c: 01f00293 li t0,31 -80000080: 3a029073 csrw pmpcfg0,t0 -80000084: 00000297 auipc t0,0x0 -80000088: 01828293 addi t0,t0,24 # 8000009c -8000008c: 30529073 csrw mtvec,t0 -80000090: 30205073 csrwi medeleg,0 -80000094: 30305073 csrwi mideleg,0 -80000098: 30405073 csrwi mie,0 -8000009c: 00000193 li gp,0 -800000a0: 00000297 auipc t0,0x0 -800000a4: f6428293 addi t0,t0,-156 # 80000004 -800000a8: 30529073 csrw mtvec,t0 -800000ac: 00100513 li a0,1 -800000b0: 01f51513 slli a0,a0,0x1f -800000b4: 00054c63 bltz a0,800000cc -800000b8: 0ff0000f fence -800000bc: 00100193 li gp,1 -800000c0: 05d00893 li a7,93 -800000c4: 00000513 li a0,0 -800000c8: 00000073 ecall -800000cc: 80000297 auipc t0,0x80000 -800000d0: f3428293 addi t0,t0,-204 # 0 <_start-0x80000000> -800000d4: 00028e63 beqz t0,800000f0 -800000d8: 10529073 csrw stvec,t0 -800000dc: 0000b2b7 lui t0,0xb -800000e0: 10928293 addi t0,t0,265 # b109 <_start-0x7fff4ef7> -800000e4: 30229073 csrw medeleg,t0 -800000e8: 30202373 csrr t1,medeleg -800000ec: f46298e3 bne t0,t1,8000003c -800000f0: 30005073 csrwi mstatus,0 -800000f4: 00000297 auipc t0,0x0 -800000f8: 01428293 addi t0,t0,20 # 80000108 -800000fc: 34129073 csrw mepc,t0 -80000100: f1402573 csrr a0,mhartid -80000104: 30200073 mret - -80000108 : -80000108: 00200193 li gp,2 -8000010c: 00000093 li ra,0 -80000110: 00000113 li sp,0 -80000114: 0020f663 bgeu ra,sp,80000120 -80000118: 34301263 bne zero,gp,8000045c -8000011c: 00301663 bne zero,gp,80000128 -80000120: fe20fee3 bgeu ra,sp,8000011c -80000124: 32301c63 bne zero,gp,8000045c - -80000128 : -80000128: 00300193 li gp,3 -8000012c: 00100093 li ra,1 -80000130: 00100113 li sp,1 -80000134: 0020f663 bgeu ra,sp,80000140 -80000138: 32301263 bne zero,gp,8000045c -8000013c: 00301663 bne zero,gp,80000148 -80000140: fe20fee3 bgeu ra,sp,8000013c -80000144: 30301c63 bne zero,gp,8000045c - -80000148 : -80000148: 00400193 li gp,4 -8000014c: fff00093 li ra,-1 -80000150: fff00113 li sp,-1 -80000154: 0020f663 bgeu ra,sp,80000160 -80000158: 30301263 bne zero,gp,8000045c -8000015c: 00301663 bne zero,gp,80000168 -80000160: fe20fee3 bgeu ra,sp,8000015c -80000164: 2e301c63 bne zero,gp,8000045c - -80000168 : -80000168: 00500193 li gp,5 -8000016c: 00100093 li ra,1 -80000170: 00000113 li sp,0 -80000174: 0020f663 bgeu ra,sp,80000180 -80000178: 2e301263 bne zero,gp,8000045c -8000017c: 00301663 bne zero,gp,80000188 -80000180: fe20fee3 bgeu ra,sp,8000017c -80000184: 2c301c63 bne zero,gp,8000045c - -80000188 : -80000188: 00600193 li gp,6 -8000018c: fff00093 li ra,-1 -80000190: ffe00113 li sp,-2 -80000194: 0020f663 bgeu ra,sp,800001a0 -80000198: 2c301263 bne zero,gp,8000045c -8000019c: 00301663 bne zero,gp,800001a8 -800001a0: fe20fee3 bgeu ra,sp,8000019c -800001a4: 2a301c63 bne zero,gp,8000045c - -800001a8 : -800001a8: 00700193 li gp,7 -800001ac: fff00093 li ra,-1 -800001b0: 00000113 li sp,0 -800001b4: 0020f663 bgeu ra,sp,800001c0 -800001b8: 2a301263 bne zero,gp,8000045c -800001bc: 00301663 bne zero,gp,800001c8 -800001c0: fe20fee3 bgeu ra,sp,800001bc -800001c4: 28301c63 bne zero,gp,8000045c - -800001c8 : -800001c8: 00800193 li gp,8 -800001cc: 00000093 li ra,0 -800001d0: 00100113 li sp,1 -800001d4: 0020f463 bgeu ra,sp,800001dc -800001d8: 00301463 bne zero,gp,800001e0 -800001dc: 28301063 bne zero,gp,8000045c -800001e0: fe20fee3 bgeu ra,sp,800001dc - -800001e4 : -800001e4: 00900193 li gp,9 -800001e8: ffe00093 li ra,-2 -800001ec: fff00113 li sp,-1 -800001f0: 0020f463 bgeu ra,sp,800001f8 -800001f4: 00301463 bne zero,gp,800001fc -800001f8: 26301263 bne zero,gp,8000045c -800001fc: fe20fee3 bgeu ra,sp,800001f8 - -80000200 : -80000200: 00a00193 li gp,10 -80000204: 00000093 li ra,0 -80000208: fff00113 li sp,-1 -8000020c: 0020f463 bgeu ra,sp,80000214 -80000210: 00301463 bne zero,gp,80000218 -80000214: 24301463 bne zero,gp,8000045c -80000218: fe20fee3 bgeu ra,sp,80000214 - -8000021c : -8000021c: 00b00193 li gp,11 -80000220: 800000b7 lui ra,0x80000 -80000224: fff08093 addi ra,ra,-1 # 7fffffff <_end+0xffffdfff> -80000228: 80000137 lui sp,0x80000 -8000022c: 0020f463 bgeu ra,sp,80000234 -80000230: 00301463 bne zero,gp,80000238 -80000234: 22301463 bne zero,gp,8000045c -80000238: fe20fee3 bgeu ra,sp,80000234 - -8000023c : -8000023c: 00c00193 li gp,12 -80000240: 00000213 li tp,0 -80000244: f00000b7 lui ra,0xf0000 -80000248: fff08093 addi ra,ra,-1 # efffffff <_end+0x6fffdfff> -8000024c: f0000137 lui sp,0xf0000 -80000250: 2020f663 bgeu ra,sp,8000045c -80000254: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000258: 00200293 li t0,2 -8000025c: fe5214e3 bne tp,t0,80000244 - -80000260 : -80000260: 00d00193 li gp,13 -80000264: 00000213 li tp,0 -80000268: f00000b7 lui ra,0xf0000 -8000026c: fff08093 addi ra,ra,-1 # efffffff <_end+0x6fffdfff> -80000270: f0000137 lui sp,0xf0000 -80000274: 00000013 nop -80000278: 1e20f263 bgeu ra,sp,8000045c -8000027c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000280: 00200293 li t0,2 -80000284: fe5212e3 bne tp,t0,80000268 - -80000288 : -80000288: 00e00193 li gp,14 -8000028c: 00000213 li tp,0 -80000290: f00000b7 lui ra,0xf0000 -80000294: fff08093 addi ra,ra,-1 # efffffff <_end+0x6fffdfff> -80000298: f0000137 lui sp,0xf0000 -8000029c: 00000013 nop -800002a0: 00000013 nop -800002a4: 1a20fc63 bgeu ra,sp,8000045c -800002a8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -800002ac: 00200293 li t0,2 -800002b0: fe5210e3 bne tp,t0,80000290 - -800002b4 : -800002b4: 00f00193 li gp,15 -800002b8: 00000213 li tp,0 -800002bc: f00000b7 lui ra,0xf0000 -800002c0: fff08093 addi ra,ra,-1 # efffffff <_end+0x6fffdfff> -800002c4: 00000013 nop -800002c8: f0000137 lui sp,0xf0000 -800002cc: 1820f863 bgeu ra,sp,8000045c -800002d0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -800002d4: 00200293 li t0,2 -800002d8: fe5212e3 bne tp,t0,800002bc - -800002dc : -800002dc: 01000193 li gp,16 -800002e0: 00000213 li tp,0 -800002e4: f00000b7 lui ra,0xf0000 -800002e8: fff08093 addi ra,ra,-1 # efffffff <_end+0x6fffdfff> -800002ec: 00000013 nop -800002f0: f0000137 lui sp,0xf0000 -800002f4: 00000013 nop -800002f8: 1620f263 bgeu ra,sp,8000045c -800002fc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000300: 00200293 li t0,2 -80000304: fe5210e3 bne tp,t0,800002e4 - -80000308 : -80000308: 01100193 li gp,17 -8000030c: 00000213 li tp,0 -80000310: f00000b7 lui ra,0xf0000 -80000314: fff08093 addi ra,ra,-1 # efffffff <_end+0x6fffdfff> -80000318: 00000013 nop -8000031c: 00000013 nop -80000320: f0000137 lui sp,0xf0000 -80000324: 1220fc63 bgeu ra,sp,8000045c -80000328: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -8000032c: 00200293 li t0,2 -80000330: fe5210e3 bne tp,t0,80000310 - -80000334 : -80000334: 01200193 li gp,18 -80000338: 00000213 li tp,0 -8000033c: f00000b7 lui ra,0xf0000 -80000340: fff08093 addi ra,ra,-1 # efffffff <_end+0x6fffdfff> -80000344: f0000137 lui sp,0xf0000 -80000348: 1020fa63 bgeu ra,sp,8000045c -8000034c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000350: 00200293 li t0,2 -80000354: fe5214e3 bne tp,t0,8000033c - -80000358 : -80000358: 01300193 li gp,19 -8000035c: 00000213 li tp,0 -80000360: f00000b7 lui ra,0xf0000 -80000364: fff08093 addi ra,ra,-1 # efffffff <_end+0x6fffdfff> -80000368: f0000137 lui sp,0xf0000 -8000036c: 00000013 nop -80000370: 0e20f663 bgeu ra,sp,8000045c -80000374: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000378: 00200293 li t0,2 -8000037c: fe5212e3 bne tp,t0,80000360 - -80000380 : -80000380: 01400193 li gp,20 -80000384: 00000213 li tp,0 -80000388: f00000b7 lui ra,0xf0000 -8000038c: fff08093 addi ra,ra,-1 # efffffff <_end+0x6fffdfff> -80000390: f0000137 lui sp,0xf0000 -80000394: 00000013 nop -80000398: 00000013 nop -8000039c: 0c20f063 bgeu ra,sp,8000045c -800003a0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -800003a4: 00200293 li t0,2 -800003a8: fe5210e3 bne tp,t0,80000388 - -800003ac : -800003ac: 01500193 li gp,21 -800003b0: 00000213 li tp,0 -800003b4: f00000b7 lui ra,0xf0000 -800003b8: fff08093 addi ra,ra,-1 # efffffff <_end+0x6fffdfff> -800003bc: 00000013 nop -800003c0: f0000137 lui sp,0xf0000 -800003c4: 0820fc63 bgeu ra,sp,8000045c -800003c8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -800003cc: 00200293 li t0,2 -800003d0: fe5212e3 bne tp,t0,800003b4 - -800003d4 : -800003d4: 01600193 li gp,22 -800003d8: 00000213 li tp,0 -800003dc: f00000b7 lui ra,0xf0000 -800003e0: fff08093 addi ra,ra,-1 # efffffff <_end+0x6fffdfff> -800003e4: 00000013 nop -800003e8: f0000137 lui sp,0xf0000 -800003ec: 00000013 nop -800003f0: 0620f663 bgeu ra,sp,8000045c -800003f4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -800003f8: 00200293 li t0,2 -800003fc: fe5210e3 bne tp,t0,800003dc - -80000400 : -80000400: 01700193 li gp,23 -80000404: 00000213 li tp,0 -80000408: f00000b7 lui ra,0xf0000 -8000040c: fff08093 addi ra,ra,-1 # efffffff <_end+0x6fffdfff> -80000410: 00000013 nop -80000414: 00000013 nop -80000418: f0000137 lui sp,0xf0000 -8000041c: 0420f063 bgeu ra,sp,8000045c -80000420: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000424: 00200293 li t0,2 -80000428: fe5210e3 bne tp,t0,80000408 - -8000042c : -8000042c: 00100093 li ra,1 -80000430: 0000fa63 bgeu ra,zero,80000444 -80000434: 00108093 addi ra,ra,1 -80000438: 00108093 addi ra,ra,1 -8000043c: 00108093 addi ra,ra,1 -80000440: 00108093 addi ra,ra,1 -80000444: 00108093 addi ra,ra,1 -80000448: 00108093 addi ra,ra,1 -8000044c: 00300e93 li t4,3 -80000450: 01800193 li gp,24 -80000454: 01d09463 bne ra,t4,8000045c -80000458: 02301063 bne zero,gp,80000478 - -8000045c : -8000045c: 0ff0000f fence -80000460: 00018063 beqz gp,80000460 -80000464: 00119193 slli gp,gp,0x1 -80000468: 0011e193 ori gp,gp,1 -8000046c: 05d00893 li a7,93 -80000470: 00018513 mv a0,gp -80000474: 00000073 ecall - -80000478 : -80000478: 0ff0000f fence -8000047c: 00100193 li gp,1 -80000480: 05d00893 li a7,93 -80000484: 00000513 li a0,0 -80000488: 00000073 ecall -8000048c: c0001073 unimp -80000490: 0000 unimp -80000492: 0000 unimp -80000494: 0000 unimp -80000496: 0000 unimp -80000498: 0000 unimp -8000049a: 0000 unimp -8000049c: 0000 unimp -8000049e: 0000 unimp -800004a0: 0000 unimp -800004a2: 0000 unimp -800004a4: 0000 unimp -800004a6: 0000 unimp -800004a8: 0000 unimp -800004aa: 0000 unimp -800004ac: 0000 unimp -800004ae: 0000 unimp -800004b0: 0000 unimp -800004b2: 0000 unimp -800004b4: 0000 unimp -800004b6: 0000 unimp -800004b8: 0000 unimp -800004ba: 0000 unimp -800004bc: 0000 unimp -800004be: 0000 unimp -800004c0: 0000 unimp -800004c2: 0000 unimp diff --git a/benchmarks/riscv_tests/rv32ui-p-bgeu.hex b/benchmarks/riscv_tests/rv32ui-p-bgeu.hex deleted file mode 100644 index b7970cdb..00000000 --- a/benchmarks/riscv_tests/rv32ui-p-bgeu.hex +++ /dev/null @@ -1,77 +0,0 @@ -:0200000480007A -:100000006F00C004732F2034930F8000630AFF0336 -:10001000930F90006306FF03930FB0006302FF038A -:10002000170F0080130F0FFE63040F0067000F000F -:10003000732F203463540F006F004000136E9E53E3 -:10004000171F00002320CFFD6FF09FFF732540F1A5 -:100050006310050073251030635805000F00F00F82 -:10006000130E100073000000130E00009702000032 -:10007000938282F973905230735020307350303035 -:1000800073504030970200809382C2F7638C020065 -:10009000739052109302B01A739022307323203061 -:1000A000E39E62F873500030970200009382420191 -:1000B00073901234732540F173002030130E20002A -:1000C000930000001301000063F620006312C035A6 -:1000D0006316C001E3FE20FE631CC033130E300024 -:1000E000930010001301100063F620006312C03368 -:1000F0006316C001E3FE20FE631CC031130E4000F6 -:100100009300F0FF1301F0FF63F620006312C0318B -:100110006316C001E3FE20FE631CC02F130E5000C7 -:10012000930010001301000063F620006312C02F3B -:100130006316C001E3FE20FE631CC02D130E600099 -:100140009300F0FF1301E0FF63F620006312C02D5F -:100150006316C001E3FE20FE631CC02B130E70006B -:100160009300F0FF1301000063F620006312C02B20 -:100170006316C001E3FE20FE631CC029130E80003D -:10018000930000001301100063F420006314C00109 -:100190006310C029E3FE20FE130E90009300E0FFE1 -:1001A0001301F0FF63F420006314C0016312C02741 -:1001B000E3FE20FE130EA000930000001301F0FFE9 -:1001C00063F420006314C0016314C025E3FE20FE25 -:1001D000130EB000B70000809380F0FF370100805D -:1001E00063F420006314C0016314C023E3FE20FE07 -:1001F000130EC00013020000B70000F09380F0FF60 -:10020000370100F063F62020130212009302200051 -:10021000E31452FE130ED00013020000B70000F0EA -:100220009380F0FF370100F01300000063F2201EFE -:100230001302120093022000E31252FE130EE0009C -:1002400013020000B70000F09380F0FF370100F0C8 -:10025000130000001300000063FC201A13021200B8 -:1002600093022000E31052FE130EF0001302000070 -:10027000B70000F09380F0FF13000000370100F09A -:1002800063F820181302120093022000E31252FEBA -:10029000130E000113020000B70000F09380F0FF7E -:1002A00013000000370100F01300000063F2201675 -:1002B0001302120093022000E31052FE130E1001ED -:1002C00013020000B70000F09380F0FF130000005D -:1002D00013000000370100F063FC2012130212002B -:1002E00093022000E31052FE130E200113020000BF -:1002F000B70000F09380F0FF370100F063FA2010A0 -:100300001302120093022000E31452FE130E300178 -:1003100013020000B70000F09380F0FF370100F0F7 -:100320001300000063F6200E130212009302200057 -:10033000E31252FE130E400113020000B70000F05A -:100340009380F0FF370100F013000000130000005D -:1003500063F0200C1302120093022000E31052FEFF -:10036000130E500113020000B70000F09380F0FF5D -:1003700013000000370100F063FC20081302120094 -:1003800093022000E31252FE130E600113020000DC -:10039000B70000F09380F0FF13000000370100F079 -:1003A0001300000063F620061302120093022000DF -:1003B000E31052FE130E700113020000B70000F0AC -:1003C0009380F0FF1300000013000000370100F0DD -:1003D00063F020041302120093022000E31052FE87 -:1003E0009300100063FA00009380100093801000C7 -:1003F0009380100093801000938010009380100071 -:10040000930E3000130E80016394D001631CC00171 -:100410000F00F00F63000E00131E1E00136E1E006F -:10042000730000000F00F00F130E100073000000A7 -:10043000731000C000000000000000000000000079 -:0404400000000000B8 -:1010000000000000000000000000000000000000E0 -:1010100000000000000000000000000000000000D0 -:1010200000000000000000000000000000000000C0 -:1010300000000000000000000000000000000000B0 -:081040000000000000000000A8 -:040000058000200057 -:00000001FF diff --git a/benchmarks/riscv_tests/rv32ui-p-blt.dump b/benchmarks/riscv_tests/rv32ui-p-blt.dump deleted file mode 100644 index 95ce45de..00000000 --- a/benchmarks/riscv_tests/rv32ui-p-blt.dump +++ /dev/null @@ -1,318 +0,0 @@ - -rv32ui-p-blt: file format elf32-littleriscv - - -Disassembly of section .text.init: - -80000000 <_start>: -80000000: 04c0006f j 8000004c - -80000004 : -80000004: 34202f73 csrr t5,mcause -80000008: 00800f93 li t6,8 -8000000c: 03ff0a63 beq t5,t6,80000040 -80000010: 00900f93 li t6,9 -80000014: 03ff0663 beq t5,t6,80000040 -80000018: 00b00f93 li t6,11 -8000001c: 03ff0263 beq t5,t6,80000040 -80000020: 80000f17 auipc t5,0x80000 -80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> -80000028: 000f0463 beqz t5,80000030 -8000002c: 000f0067 jr t5 -80000030: 34202f73 csrr t5,mcause -80000034: 000f5463 bgez t5,8000003c -80000038: 0040006f j 8000003c - -8000003c : -8000003c: 5391e193 ori gp,gp,1337 - -80000040 : -80000040: 00001f17 auipc t5,0x1 -80000044: fc3f2023 sw gp,-64(t5) # 80001000 -80000048: ff9ff06f j 80000040 - -8000004c : -8000004c: f1402573 csrr a0,mhartid -80000050: 00051063 bnez a0,80000050 -80000054: 00000297 auipc t0,0x0 -80000058: 01028293 addi t0,t0,16 # 80000064 -8000005c: 30529073 csrw mtvec,t0 -80000060: 18005073 csrwi satp,0 -80000064: 00000297 auipc t0,0x0 -80000068: 02028293 addi t0,t0,32 # 80000084 -8000006c: 30529073 csrw mtvec,t0 -80000070: 800002b7 lui t0,0x80000 -80000074: fff28293 addi t0,t0,-1 # 7fffffff <_end+0xffffdfff> -80000078: 3b029073 csrw pmpaddr0,t0 -8000007c: 01f00293 li t0,31 -80000080: 3a029073 csrw pmpcfg0,t0 -80000084: 00000297 auipc t0,0x0 -80000088: 01828293 addi t0,t0,24 # 8000009c -8000008c: 30529073 csrw mtvec,t0 -80000090: 30205073 csrwi medeleg,0 -80000094: 30305073 csrwi mideleg,0 -80000098: 30405073 csrwi mie,0 -8000009c: 00000193 li gp,0 -800000a0: 00000297 auipc t0,0x0 -800000a4: f6428293 addi t0,t0,-156 # 80000004 -800000a8: 30529073 csrw mtvec,t0 -800000ac: 00100513 li a0,1 -800000b0: 01f51513 slli a0,a0,0x1f -800000b4: 00054c63 bltz a0,800000cc -800000b8: 0ff0000f fence -800000bc: 00100193 li gp,1 -800000c0: 05d00893 li a7,93 -800000c4: 00000513 li a0,0 -800000c8: 00000073 ecall -800000cc: 80000297 auipc t0,0x80000 -800000d0: f3428293 addi t0,t0,-204 # 0 <_start-0x80000000> -800000d4: 00028e63 beqz t0,800000f0 -800000d8: 10529073 csrw stvec,t0 -800000dc: 0000b2b7 lui t0,0xb -800000e0: 10928293 addi t0,t0,265 # b109 <_start-0x7fff4ef7> -800000e4: 30229073 csrw medeleg,t0 -800000e8: 30202373 csrr t1,medeleg -800000ec: f46298e3 bne t0,t1,8000003c -800000f0: 30005073 csrwi mstatus,0 -800000f4: 00000297 auipc t0,0x0 -800000f8: 01428293 addi t0,t0,20 # 80000108 -800000fc: 34129073 csrw mepc,t0 -80000100: f1402573 csrr a0,mhartid -80000104: 30200073 mret - -80000108 : -80000108: 00200193 li gp,2 -8000010c: 00000093 li ra,0 -80000110: 00100113 li sp,1 -80000114: 0020c663 blt ra,sp,80000120 -80000118: 2a301863 bne zero,gp,800003c8 -8000011c: 00301663 bne zero,gp,80000128 -80000120: fe20cee3 blt ra,sp,8000011c -80000124: 2a301263 bne zero,gp,800003c8 - -80000128 : -80000128: 00300193 li gp,3 -8000012c: fff00093 li ra,-1 -80000130: 00100113 li sp,1 -80000134: 0020c663 blt ra,sp,80000140 -80000138: 28301863 bne zero,gp,800003c8 -8000013c: 00301663 bne zero,gp,80000148 -80000140: fe20cee3 blt ra,sp,8000013c -80000144: 28301263 bne zero,gp,800003c8 - -80000148 : -80000148: 00400193 li gp,4 -8000014c: ffe00093 li ra,-2 -80000150: fff00113 li sp,-1 -80000154: 0020c663 blt ra,sp,80000160 -80000158: 26301863 bne zero,gp,800003c8 -8000015c: 00301663 bne zero,gp,80000168 -80000160: fe20cee3 blt ra,sp,8000015c -80000164: 26301263 bne zero,gp,800003c8 - -80000168 : -80000168: 00500193 li gp,5 -8000016c: 00100093 li ra,1 -80000170: 00000113 li sp,0 -80000174: 0020c463 blt ra,sp,8000017c -80000178: 00301463 bne zero,gp,80000180 -8000017c: 24301663 bne zero,gp,800003c8 -80000180: fe20cee3 blt ra,sp,8000017c - -80000184 : -80000184: 00600193 li gp,6 -80000188: 00100093 li ra,1 -8000018c: fff00113 li sp,-1 -80000190: 0020c463 blt ra,sp,80000198 -80000194: 00301463 bne zero,gp,8000019c -80000198: 22301863 bne zero,gp,800003c8 -8000019c: fe20cee3 blt ra,sp,80000198 - -800001a0 : -800001a0: 00700193 li gp,7 -800001a4: fff00093 li ra,-1 -800001a8: ffe00113 li sp,-2 -800001ac: 0020c463 blt ra,sp,800001b4 -800001b0: 00301463 bne zero,gp,800001b8 -800001b4: 20301a63 bne zero,gp,800003c8 -800001b8: fe20cee3 blt ra,sp,800001b4 - -800001bc : -800001bc: 00800193 li gp,8 -800001c0: 00100093 li ra,1 -800001c4: ffe00113 li sp,-2 -800001c8: 0020c463 blt ra,sp,800001d0 -800001cc: 00301463 bne zero,gp,800001d4 -800001d0: 1e301c63 bne zero,gp,800003c8 -800001d4: fe20cee3 blt ra,sp,800001d0 - -800001d8 : -800001d8: 00900193 li gp,9 -800001dc: 00000213 li tp,0 -800001e0: 00000093 li ra,0 -800001e4: fff00113 li sp,-1 -800001e8: 1e20c063 blt ra,sp,800003c8 -800001ec: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -800001f0: 00200293 li t0,2 -800001f4: fe5216e3 bne tp,t0,800001e0 - -800001f8 : -800001f8: 00a00193 li gp,10 -800001fc: 00000213 li tp,0 -80000200: 00000093 li ra,0 -80000204: fff00113 li sp,-1 -80000208: 00000013 nop -8000020c: 1a20ce63 blt ra,sp,800003c8 -80000210: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000214: 00200293 li t0,2 -80000218: fe5214e3 bne tp,t0,80000200 - -8000021c : -8000021c: 00b00193 li gp,11 -80000220: 00000213 li tp,0 -80000224: 00000093 li ra,0 -80000228: fff00113 li sp,-1 -8000022c: 00000013 nop -80000230: 00000013 nop -80000234: 1820ca63 blt ra,sp,800003c8 -80000238: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -8000023c: 00200293 li t0,2 -80000240: fe5212e3 bne tp,t0,80000224 - -80000244 : -80000244: 00c00193 li gp,12 -80000248: 00000213 li tp,0 -8000024c: 00000093 li ra,0 -80000250: 00000013 nop -80000254: fff00113 li sp,-1 -80000258: 1620c863 blt ra,sp,800003c8 -8000025c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000260: 00200293 li t0,2 -80000264: fe5214e3 bne tp,t0,8000024c - -80000268 : -80000268: 00d00193 li gp,13 -8000026c: 00000213 li tp,0 -80000270: 00000093 li ra,0 -80000274: 00000013 nop -80000278: fff00113 li sp,-1 -8000027c: 00000013 nop -80000280: 1420c463 blt ra,sp,800003c8 -80000284: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000288: 00200293 li t0,2 -8000028c: fe5212e3 bne tp,t0,80000270 - -80000290 : -80000290: 00e00193 li gp,14 -80000294: 00000213 li tp,0 -80000298: 00000093 li ra,0 -8000029c: 00000013 nop -800002a0: 00000013 nop -800002a4: fff00113 li sp,-1 -800002a8: 1220c063 blt ra,sp,800003c8 -800002ac: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -800002b0: 00200293 li t0,2 -800002b4: fe5212e3 bne tp,t0,80000298 - -800002b8 : -800002b8: 00f00193 li gp,15 -800002bc: 00000213 li tp,0 -800002c0: 00000093 li ra,0 -800002c4: fff00113 li sp,-1 -800002c8: 1020c063 blt ra,sp,800003c8 -800002cc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -800002d0: 00200293 li t0,2 -800002d4: fe5216e3 bne tp,t0,800002c0 - -800002d8 : -800002d8: 01000193 li gp,16 -800002dc: 00000213 li tp,0 -800002e0: 00000093 li ra,0 -800002e4: fff00113 li sp,-1 -800002e8: 00000013 nop -800002ec: 0c20ce63 blt ra,sp,800003c8 -800002f0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -800002f4: 00200293 li t0,2 -800002f8: fe5214e3 bne tp,t0,800002e0 - -800002fc : -800002fc: 01100193 li gp,17 -80000300: 00000213 li tp,0 -80000304: 00000093 li ra,0 -80000308: fff00113 li sp,-1 -8000030c: 00000013 nop -80000310: 00000013 nop -80000314: 0a20ca63 blt ra,sp,800003c8 -80000318: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -8000031c: 00200293 li t0,2 -80000320: fe5212e3 bne tp,t0,80000304 - -80000324 : -80000324: 01200193 li gp,18 -80000328: 00000213 li tp,0 -8000032c: 00000093 li ra,0 -80000330: 00000013 nop -80000334: fff00113 li sp,-1 -80000338: 0820c863 blt ra,sp,800003c8 -8000033c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000340: 00200293 li t0,2 -80000344: fe5214e3 bne tp,t0,8000032c - -80000348 : -80000348: 01300193 li gp,19 -8000034c: 00000213 li tp,0 -80000350: 00000093 li ra,0 -80000354: 00000013 nop -80000358: fff00113 li sp,-1 -8000035c: 00000013 nop -80000360: 0620c463 blt ra,sp,800003c8 -80000364: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000368: 00200293 li t0,2 -8000036c: fe5212e3 bne tp,t0,80000350 - -80000370 : -80000370: 01400193 li gp,20 -80000374: 00000213 li tp,0 -80000378: 00000093 li ra,0 -8000037c: 00000013 nop -80000380: 00000013 nop -80000384: fff00113 li sp,-1 -80000388: 0420c063 blt ra,sp,800003c8 -8000038c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000390: 00200293 li t0,2 -80000394: fe5212e3 bne tp,t0,80000378 - -80000398 : -80000398: 00100093 li ra,1 -8000039c: 00104a63 bgtz ra,800003b0 -800003a0: 00108093 addi ra,ra,1 -800003a4: 00108093 addi ra,ra,1 -800003a8: 00108093 addi ra,ra,1 -800003ac: 00108093 addi ra,ra,1 -800003b0: 00108093 addi ra,ra,1 -800003b4: 00108093 addi ra,ra,1 -800003b8: 00300e93 li t4,3 -800003bc: 01500193 li gp,21 -800003c0: 01d09463 bne ra,t4,800003c8 -800003c4: 02301063 bne zero,gp,800003e4 - -800003c8 : -800003c8: 0ff0000f fence -800003cc: 00018063 beqz gp,800003cc -800003d0: 00119193 slli gp,gp,0x1 -800003d4: 0011e193 ori gp,gp,1 -800003d8: 05d00893 li a7,93 -800003dc: 00018513 mv a0,gp -800003e0: 00000073 ecall - -800003e4 : -800003e4: 0ff0000f fence -800003e8: 00100193 li gp,1 -800003ec: 05d00893 li a7,93 -800003f0: 00000513 li a0,0 -800003f4: 00000073 ecall -800003f8: c0001073 unimp -800003fc: 0000 unimp -800003fe: 0000 unimp -80000400: 0000 unimp -80000402: 0000 unimp diff --git a/benchmarks/riscv_tests/rv32ui-p-blt.hex b/benchmarks/riscv_tests/rv32ui-p-blt.hex deleted file mode 100644 index 322ff1d0..00000000 --- a/benchmarks/riscv_tests/rv32ui-p-blt.hex +++ /dev/null @@ -1,69 +0,0 @@ -:0200000480007A -:100000006F00C004732F2034930F8000630AFF0336 -:10001000930F90006306FF03930FB0006302FF038A -:10002000170F0080130F0FFE63040F0067000F000F -:10003000732F203463540F006F004000136E9E53E3 -:10004000171F00002320CFFD6FF09FFF732540F1A5 -:100050006310050073251030635805000F00F00F82 -:10006000130E100073000000130E00009702000032 -:10007000938282F973905230735020307350303035 -:1000800073504030970200809382C2F7638C020065 -:10009000739052109302B01A739022307323203061 -:1000A000E39E62F873500030970200009382420191 -:1000B00073901234732540F173002030130E20002A -:1000C000930000001301100063C620006318C02BCA -:1000D0006316C001E3CE20FE6312C02B130E300066 -:1000E0009300F0FF1301100063C620006318C029BD -:1000F0006316C001E3CE20FE6312C029130E400038 -:100100009300E0FF1301F0FF63C620006318C027CF -:100110006316C001E3CE20FE6312C027130E500009 -:10012000930010001301000063C420006314C00199 -:100130006316C025E3CE20FE130E6000930010006E -:100140001301F0FF63C420006314C0016318C023CF -:10015000E3CE20FE130E70009300F0FF1301E0FFCA -:1001600063C420006314C001631AC021E3CE20FEE3 -:10017000130E8000930010001301E0FF63C4200001 -:100180006314C001631CC01FE3CE20FE130E900059 -:1001900013020000930000001301F0FF63C0201E53 -:1001A0001302120093022000E31652FE130EA00069 -:1001B00013020000930000001301F0FF1300000081 -:1001C00063CE201A1302120093022000E31452FEA1 -:1001D000130EB00013020000930000001301F0FFA3 -:1001E000130000001300000063CA2018130212005D -:1001F00093022000E31252FE130EC000130200000F -:1002000093000000130000001301F0FF63C82016E4 -:100210001302120093022000E31452FE130ED000CA -:100220001302000093000000130000001301F0FF10 -:100230001300000063C42014130212009302200074 -:10024000E31252FE130EE0001302000093000000C0 -:1002500013000000130000001301F0FF63C0201220 -:100260001302120093022000E31252FE130EF0005C -:1002700013020000930000001301F0FF63C0201080 -:100280001302120093022000E31652FE130E000127 -:1002900013020000930000001301F0FF13000000A0 -:1002A00063CE200C1302120093022000E31452FECE -:1002B000130E100113020000930000001301F0FF61 -:1002C000130000001300000063CA200A130212008A -:1002D00093022000E31252FE130E200113020000CD -:1002E00093000000130000001301F0FF63C8200812 -:1002F0001302120093022000E31452FE130E300189 -:100300001302000093000000130000001301F0FF2F -:100310001300000063C420061302120093022000A1 -:10032000E31252FE130E400113020000930000007E -:1003300013000000130000001301F0FF63C020044D -:100340001302120093022000E31252FE93001000E9 -:10035000634A100093801000938010009380100077 -:10036000938010009380100093801000930E300053 -:10037000130E50016394D001631CC0010F00F00FF5 -:1003800063000E00131E1E00136E1E00730000009B -:100390000F00F00F130E100073000000731000C068 -:1003A000000000000000000000000000000000004D -:1003B000000000000000000000000000000000003D -:0403C0000000000039 -:1010000000000000000000000000000000000000E0 -:1010100000000000000000000000000000000000D0 -:1010200000000000000000000000000000000000C0 -:1010300000000000000000000000000000000000B0 -:081040000000000000000000A8 -:040000058000200057 -:00000001FF diff --git a/benchmarks/riscv_tests/rv32ui-p-bltu.dump b/benchmarks/riscv_tests/rv32ui-p-bltu.dump deleted file mode 100644 index c392601b..00000000 --- a/benchmarks/riscv_tests/rv32ui-p-bltu.dump +++ /dev/null @@ -1,337 +0,0 @@ - -rv32ui-p-bltu: file format elf32-littleriscv - - -Disassembly of section .text.init: - -80000000 <_start>: -80000000: 04c0006f j 8000004c - -80000004 : -80000004: 34202f73 csrr t5,mcause -80000008: 00800f93 li t6,8 -8000000c: 03ff0a63 beq t5,t6,80000040 -80000010: 00900f93 li t6,9 -80000014: 03ff0663 beq t5,t6,80000040 -80000018: 00b00f93 li t6,11 -8000001c: 03ff0263 beq t5,t6,80000040 -80000020: 80000f17 auipc t5,0x80000 -80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> -80000028: 000f0463 beqz t5,80000030 -8000002c: 000f0067 jr t5 -80000030: 34202f73 csrr t5,mcause -80000034: 000f5463 bgez t5,8000003c -80000038: 0040006f j 8000003c - -8000003c : -8000003c: 5391e193 ori gp,gp,1337 - -80000040 : -80000040: 00001f17 auipc t5,0x1 -80000044: fc3f2023 sw gp,-64(t5) # 80001000 -80000048: ff9ff06f j 80000040 - -8000004c : -8000004c: f1402573 csrr a0,mhartid -80000050: 00051063 bnez a0,80000050 -80000054: 00000297 auipc t0,0x0 -80000058: 01028293 addi t0,t0,16 # 80000064 -8000005c: 30529073 csrw mtvec,t0 -80000060: 18005073 csrwi satp,0 -80000064: 00000297 auipc t0,0x0 -80000068: 02028293 addi t0,t0,32 # 80000084 -8000006c: 30529073 csrw mtvec,t0 -80000070: 800002b7 lui t0,0x80000 -80000074: fff28293 addi t0,t0,-1 # 7fffffff <_end+0xffffdfff> -80000078: 3b029073 csrw pmpaddr0,t0 -8000007c: 01f00293 li t0,31 -80000080: 3a029073 csrw pmpcfg0,t0 -80000084: 00000297 auipc t0,0x0 -80000088: 01828293 addi t0,t0,24 # 8000009c -8000008c: 30529073 csrw mtvec,t0 -80000090: 30205073 csrwi medeleg,0 -80000094: 30305073 csrwi mideleg,0 -80000098: 30405073 csrwi mie,0 -8000009c: 00000193 li gp,0 -800000a0: 00000297 auipc t0,0x0 -800000a4: f6428293 addi t0,t0,-156 # 80000004 -800000a8: 30529073 csrw mtvec,t0 -800000ac: 00100513 li a0,1 -800000b0: 01f51513 slli a0,a0,0x1f -800000b4: 00054c63 bltz a0,800000cc -800000b8: 0ff0000f fence -800000bc: 00100193 li gp,1 -800000c0: 05d00893 li a7,93 -800000c4: 00000513 li a0,0 -800000c8: 00000073 ecall -800000cc: 80000297 auipc t0,0x80000 -800000d0: f3428293 addi t0,t0,-204 # 0 <_start-0x80000000> -800000d4: 00028e63 beqz t0,800000f0 -800000d8: 10529073 csrw stvec,t0 -800000dc: 0000b2b7 lui t0,0xb -800000e0: 10928293 addi t0,t0,265 # b109 <_start-0x7fff4ef7> -800000e4: 30229073 csrw medeleg,t0 -800000e8: 30202373 csrr t1,medeleg -800000ec: f46298e3 bne t0,t1,8000003c -800000f0: 30005073 csrwi mstatus,0 -800000f4: 00000297 auipc t0,0x0 -800000f8: 01428293 addi t0,t0,20 # 80000108 -800000fc: 34129073 csrw mepc,t0 -80000100: f1402573 csrr a0,mhartid -80000104: 30200073 mret - -80000108 : -80000108: 00200193 li gp,2 -8000010c: 00000093 li ra,0 -80000110: 00100113 li sp,1 -80000114: 0020e663 bltu ra,sp,80000120 -80000118: 2e301263 bne zero,gp,800003fc -8000011c: 00301663 bne zero,gp,80000128 -80000120: fe20eee3 bltu ra,sp,8000011c -80000124: 2c301c63 bne zero,gp,800003fc - -80000128 : -80000128: 00300193 li gp,3 -8000012c: ffe00093 li ra,-2 -80000130: fff00113 li sp,-1 -80000134: 0020e663 bltu ra,sp,80000140 -80000138: 2c301263 bne zero,gp,800003fc -8000013c: 00301663 bne zero,gp,80000148 -80000140: fe20eee3 bltu ra,sp,8000013c -80000144: 2a301c63 bne zero,gp,800003fc - -80000148 : -80000148: 00400193 li gp,4 -8000014c: 00000093 li ra,0 -80000150: fff00113 li sp,-1 -80000154: 0020e663 bltu ra,sp,80000160 -80000158: 2a301263 bne zero,gp,800003fc -8000015c: 00301663 bne zero,gp,80000168 -80000160: fe20eee3 bltu ra,sp,8000015c -80000164: 28301c63 bne zero,gp,800003fc - -80000168 : -80000168: 00500193 li gp,5 -8000016c: 00100093 li ra,1 -80000170: 00000113 li sp,0 -80000174: 0020e463 bltu ra,sp,8000017c -80000178: 00301463 bne zero,gp,80000180 -8000017c: 28301063 bne zero,gp,800003fc -80000180: fe20eee3 bltu ra,sp,8000017c - -80000184 : -80000184: 00600193 li gp,6 -80000188: fff00093 li ra,-1 -8000018c: ffe00113 li sp,-2 -80000190: 0020e463 bltu ra,sp,80000198 -80000194: 00301463 bne zero,gp,8000019c -80000198: 26301263 bne zero,gp,800003fc -8000019c: fe20eee3 bltu ra,sp,80000198 - -800001a0 : -800001a0: 00700193 li gp,7 -800001a4: fff00093 li ra,-1 -800001a8: 00000113 li sp,0 -800001ac: 0020e463 bltu ra,sp,800001b4 -800001b0: 00301463 bne zero,gp,800001b8 -800001b4: 24301463 bne zero,gp,800003fc -800001b8: fe20eee3 bltu ra,sp,800001b4 - -800001bc : -800001bc: 00800193 li gp,8 -800001c0: 800000b7 lui ra,0x80000 -800001c4: 80000137 lui sp,0x80000 -800001c8: fff10113 addi sp,sp,-1 # 7fffffff <_end+0xffffdfff> -800001cc: 0020e463 bltu ra,sp,800001d4 -800001d0: 00301463 bne zero,gp,800001d8 -800001d4: 22301463 bne zero,gp,800003fc -800001d8: fe20eee3 bltu ra,sp,800001d4 - -800001dc : -800001dc: 00900193 li gp,9 -800001e0: 00000213 li tp,0 -800001e4: f00000b7 lui ra,0xf0000 -800001e8: f0000137 lui sp,0xf0000 -800001ec: fff10113 addi sp,sp,-1 # efffffff <_end+0x6fffdfff> -800001f0: 2020e663 bltu ra,sp,800003fc -800001f4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -800001f8: 00200293 li t0,2 -800001fc: fe5214e3 bne tp,t0,800001e4 - -80000200 : -80000200: 00a00193 li gp,10 -80000204: 00000213 li tp,0 -80000208: f00000b7 lui ra,0xf0000 -8000020c: f0000137 lui sp,0xf0000 -80000210: fff10113 addi sp,sp,-1 # efffffff <_end+0x6fffdfff> -80000214: 00000013 nop -80000218: 1e20e263 bltu ra,sp,800003fc -8000021c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000220: 00200293 li t0,2 -80000224: fe5212e3 bne tp,t0,80000208 - -80000228 : -80000228: 00b00193 li gp,11 -8000022c: 00000213 li tp,0 -80000230: f00000b7 lui ra,0xf0000 -80000234: f0000137 lui sp,0xf0000 -80000238: fff10113 addi sp,sp,-1 # efffffff <_end+0x6fffdfff> -8000023c: 00000013 nop -80000240: 00000013 nop -80000244: 1a20ec63 bltu ra,sp,800003fc -80000248: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -8000024c: 00200293 li t0,2 -80000250: fe5210e3 bne tp,t0,80000230 - -80000254 : -80000254: 00c00193 li gp,12 -80000258: 00000213 li tp,0 -8000025c: f00000b7 lui ra,0xf0000 -80000260: 00000013 nop -80000264: f0000137 lui sp,0xf0000 -80000268: fff10113 addi sp,sp,-1 # efffffff <_end+0x6fffdfff> -8000026c: 1820e863 bltu ra,sp,800003fc -80000270: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000274: 00200293 li t0,2 -80000278: fe5212e3 bne tp,t0,8000025c - -8000027c : -8000027c: 00d00193 li gp,13 -80000280: 00000213 li tp,0 -80000284: f00000b7 lui ra,0xf0000 -80000288: 00000013 nop -8000028c: f0000137 lui sp,0xf0000 -80000290: fff10113 addi sp,sp,-1 # efffffff <_end+0x6fffdfff> -80000294: 00000013 nop -80000298: 1620e263 bltu ra,sp,800003fc -8000029c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -800002a0: 00200293 li t0,2 -800002a4: fe5210e3 bne tp,t0,80000284 - -800002a8 : -800002a8: 00e00193 li gp,14 -800002ac: 00000213 li tp,0 -800002b0: f00000b7 lui ra,0xf0000 -800002b4: 00000013 nop -800002b8: 00000013 nop -800002bc: f0000137 lui sp,0xf0000 -800002c0: fff10113 addi sp,sp,-1 # efffffff <_end+0x6fffdfff> -800002c4: 1220ec63 bltu ra,sp,800003fc -800002c8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -800002cc: 00200293 li t0,2 -800002d0: fe5210e3 bne tp,t0,800002b0 - -800002d4 : -800002d4: 00f00193 li gp,15 -800002d8: 00000213 li tp,0 -800002dc: f00000b7 lui ra,0xf0000 -800002e0: f0000137 lui sp,0xf0000 -800002e4: fff10113 addi sp,sp,-1 # efffffff <_end+0x6fffdfff> -800002e8: 1020ea63 bltu ra,sp,800003fc -800002ec: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -800002f0: 00200293 li t0,2 -800002f4: fe5214e3 bne tp,t0,800002dc - -800002f8 : -800002f8: 01000193 li gp,16 -800002fc: 00000213 li tp,0 -80000300: f00000b7 lui ra,0xf0000 -80000304: f0000137 lui sp,0xf0000 -80000308: fff10113 addi sp,sp,-1 # efffffff <_end+0x6fffdfff> -8000030c: 00000013 nop -80000310: 0e20e663 bltu ra,sp,800003fc -80000314: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000318: 00200293 li t0,2 -8000031c: fe5212e3 bne tp,t0,80000300 - -80000320 : -80000320: 01100193 li gp,17 -80000324: 00000213 li tp,0 -80000328: f00000b7 lui ra,0xf0000 -8000032c: f0000137 lui sp,0xf0000 -80000330: fff10113 addi sp,sp,-1 # efffffff <_end+0x6fffdfff> -80000334: 00000013 nop -80000338: 00000013 nop -8000033c: 0c20e063 bltu ra,sp,800003fc -80000340: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000344: 00200293 li t0,2 -80000348: fe5210e3 bne tp,t0,80000328 - -8000034c : -8000034c: 01200193 li gp,18 -80000350: 00000213 li tp,0 -80000354: f00000b7 lui ra,0xf0000 -80000358: 00000013 nop -8000035c: f0000137 lui sp,0xf0000 -80000360: fff10113 addi sp,sp,-1 # efffffff <_end+0x6fffdfff> -80000364: 0820ec63 bltu ra,sp,800003fc -80000368: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -8000036c: 00200293 li t0,2 -80000370: fe5212e3 bne tp,t0,80000354 - -80000374 : -80000374: 01300193 li gp,19 -80000378: 00000213 li tp,0 -8000037c: f00000b7 lui ra,0xf0000 -80000380: 00000013 nop -80000384: f0000137 lui sp,0xf0000 -80000388: fff10113 addi sp,sp,-1 # efffffff <_end+0x6fffdfff> -8000038c: 00000013 nop -80000390: 0620e663 bltu ra,sp,800003fc -80000394: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000398: 00200293 li t0,2 -8000039c: fe5210e3 bne tp,t0,8000037c - -800003a0 : -800003a0: 01400193 li gp,20 -800003a4: 00000213 li tp,0 -800003a8: f00000b7 lui ra,0xf0000 -800003ac: 00000013 nop -800003b0: 00000013 nop -800003b4: f0000137 lui sp,0xf0000 -800003b8: fff10113 addi sp,sp,-1 # efffffff <_end+0x6fffdfff> -800003bc: 0420e063 bltu ra,sp,800003fc -800003c0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -800003c4: 00200293 li t0,2 -800003c8: fe5210e3 bne tp,t0,800003a8 - -800003cc : -800003cc: 00100093 li ra,1 -800003d0: 00106a63 bltu zero,ra,800003e4 -800003d4: 00108093 addi ra,ra,1 # f0000001 <_end+0x6fffe001> -800003d8: 00108093 addi ra,ra,1 -800003dc: 00108093 addi ra,ra,1 -800003e0: 00108093 addi ra,ra,1 -800003e4: 00108093 addi ra,ra,1 -800003e8: 00108093 addi ra,ra,1 -800003ec: 00300e93 li t4,3 -800003f0: 01500193 li gp,21 -800003f4: 01d09463 bne ra,t4,800003fc -800003f8: 02301063 bne zero,gp,80000418 - -800003fc : -800003fc: 0ff0000f fence -80000400: 00018063 beqz gp,80000400 -80000404: 00119193 slli gp,gp,0x1 -80000408: 0011e193 ori gp,gp,1 -8000040c: 05d00893 li a7,93 -80000410: 00018513 mv a0,gp -80000414: 00000073 ecall - -80000418 : -80000418: 0ff0000f fence -8000041c: 00100193 li gp,1 -80000420: 05d00893 li a7,93 -80000424: 00000513 li a0,0 -80000428: 00000073 ecall -8000042c: c0001073 unimp -80000430: 0000 unimp -80000432: 0000 unimp -80000434: 0000 unimp -80000436: 0000 unimp -80000438: 0000 unimp -8000043a: 0000 unimp -8000043c: 0000 unimp -8000043e: 0000 unimp -80000440: 0000 unimp -80000442: 0000 unimp diff --git a/benchmarks/riscv_tests/rv32ui-p-bltu.hex b/benchmarks/riscv_tests/rv32ui-p-bltu.hex deleted file mode 100644 index 783304b1..00000000 --- a/benchmarks/riscv_tests/rv32ui-p-bltu.hex +++ /dev/null @@ -1,73 +0,0 @@ -:0200000480007A -:100000006F00C004732F2034930F8000630AFF0336 -:10001000930F90006306FF03930FB0006302FF038A -:10002000170F0080130F0FFE63040F0067000F000F -:10003000732F203463540F006F004000136E9E53E3 -:10004000171F00002320CFFD6FF09FFF732540F1A5 -:100050006310050073251030635805000F00F00F82 -:10006000130E100073000000130E00009702000032 -:10007000938282F973905230735020307350303035 -:1000800073504030970200809382C2F7638C020065 -:10009000739052109302B01A739022307323203061 -:1000A000E39E62F873500030970200009382420191 -:1000B00073901234732540F173002030130E20002A -:1000C000930000001301100063E620006312C02FAC -:1000D0006316C001E3EE20FE631CC02D130E30003A -:1000E0009300E0FF1301F0FF63E620006312C02DD0 -:1000F0006316C001E3EE20FE631CC02B130E40000C -:10010000930000001301F0FF63E620006312C02B90 -:100110006316C001E3EE20FE631CC029130E5000DD -:10012000930010001301000063E420006314C00179 -:100130006310C029E3EE20FE130E60009300F0FF71 -:100140001301E0FF63E420006314C0016312C027C1 -:10015000E3EE20FE130E70009300F0FF1301000089 -:1001600063E420006314C0016314C025E3EE20FEA5 -:10017000130E8000B7000080370100801301F1FFEB -:1001800063E420006314C0016314C023E3EE20FE87 -:10019000130E900013020000B70000F0370100F0CA -:1001A0001301F1FF63E620201302120093022000E6 -:1001B000E31452FE130EA00013020000B70000F07B -:1001C000370100F01301F1FF1300000063E2201E6D -:1001D0001302120093022000E31252FE130EB0002D -:1001E00013020000B70000F0370100F01301F1FF27 -:1001F000130000001300000063EC201A1302120029 -:1002000093022000E31052FE130EC0001302000000 -:10021000B70000F013000000370100F01301F1FFF8 -:1002200063E820181302120093022000E31252FE2A -:10023000130ED00013020000B70000F013000000FE -:10024000370100F01301F1FF1300000063E22016F4 -:100250001302120093022000E31052FE130EE0007E -:1002600013020000B70000F01300000013000000AC -:10027000370100F01301F1FF63EC201213021200AA -:1002800093022000E31052FE130EF0001302000050 -:10029000B70000F0370100F01301F1FF63EA20100E -:1002A0001302120093022000E31452FE130E000109 -:1002B00013020000B70000F0370100F01301F1FF56 -:1002C0001300000063E6200E1302120093022000C8 -:1002D000E31252FE130E100113020000B70000F0EB -:1002E000370100F01301F1FF1300000013000000BC -:1002F00063E0200C1302120093022000E31052FE70 -:10030000130E200113020000B70000F013000000DC -:10031000370100F01301F1FF63EC20081302120013 -:1003200093022000E31252FE130E3001130200006C -:10033000B70000F013000000370100F01301F1FFD7 -:100340001300000063E6200613021200930220004F -:10035000E31052FE130E400113020000B70000F03C -:100360001300000013000000370100F01301F1FF3B -:1003700063E020041302120093022000E31052FEF7 -:1003800093001000636A10009380100093801000A7 -:1003900093801000938010009380100093801000D1 -:1003A000930E3000130E50016394D001631CC00102 -:1003B0000F00F00F63000E00131E1E00136E1E00D0 -:1003C000730000000F00F00F130E10007300000008 -:1003D000731000C0000000000000000000000000DA -:1003E000000000000000000000000000000000000D -:1003F00000000000000000000000000000000000FD -:0404000000000000F8 -:1010000000000000000000000000000000000000E0 -:1010100000000000000000000000000000000000D0 -:1010200000000000000000000000000000000000C0 -:1010300000000000000000000000000000000000B0 -:081040000000000000000000A8 -:040000058000200057 -:00000001FF diff --git a/benchmarks/riscv_tests/rv32ui-p-bne.dump b/benchmarks/riscv_tests/rv32ui-p-bne.dump deleted file mode 100644 index 226d3de4..00000000 --- a/benchmarks/riscv_tests/rv32ui-p-bne.dump +++ /dev/null @@ -1,317 +0,0 @@ - -rv32ui-p-bne: file format elf32-littleriscv - - -Disassembly of section .text.init: - -80000000 <_start>: -80000000: 04c0006f j 8000004c - -80000004 : -80000004: 34202f73 csrr t5,mcause -80000008: 00800f93 li t6,8 -8000000c: 03ff0a63 beq t5,t6,80000040 -80000010: 00900f93 li t6,9 -80000014: 03ff0663 beq t5,t6,80000040 -80000018: 00b00f93 li t6,11 -8000001c: 03ff0263 beq t5,t6,80000040 -80000020: 80000f17 auipc t5,0x80000 -80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> -80000028: 000f0463 beqz t5,80000030 -8000002c: 000f0067 jr t5 -80000030: 34202f73 csrr t5,mcause -80000034: 000f5463 bgez t5,8000003c -80000038: 0040006f j 8000003c - -8000003c : -8000003c: 5391e193 ori gp,gp,1337 - -80000040 : -80000040: 00001f17 auipc t5,0x1 -80000044: fc3f2023 sw gp,-64(t5) # 80001000 -80000048: ff9ff06f j 80000040 - -8000004c : -8000004c: f1402573 csrr a0,mhartid -80000050: 00051063 bnez a0,80000050 -80000054: 00000297 auipc t0,0x0 -80000058: 01028293 addi t0,t0,16 # 80000064 -8000005c: 30529073 csrw mtvec,t0 -80000060: 18005073 csrwi satp,0 -80000064: 00000297 auipc t0,0x0 -80000068: 02028293 addi t0,t0,32 # 80000084 -8000006c: 30529073 csrw mtvec,t0 -80000070: 800002b7 lui t0,0x80000 -80000074: fff28293 addi t0,t0,-1 # 7fffffff <_end+0xffffdfff> -80000078: 3b029073 csrw pmpaddr0,t0 -8000007c: 01f00293 li t0,31 -80000080: 3a029073 csrw pmpcfg0,t0 -80000084: 00000297 auipc t0,0x0 -80000088: 01828293 addi t0,t0,24 # 8000009c -8000008c: 30529073 csrw mtvec,t0 -80000090: 30205073 csrwi medeleg,0 -80000094: 30305073 csrwi mideleg,0 -80000098: 30405073 csrwi mie,0 -8000009c: 00000193 li gp,0 -800000a0: 00000297 auipc t0,0x0 -800000a4: f6428293 addi t0,t0,-156 # 80000004 -800000a8: 30529073 csrw mtvec,t0 -800000ac: 00100513 li a0,1 -800000b0: 01f51513 slli a0,a0,0x1f -800000b4: 00054c63 bltz a0,800000cc -800000b8: 0ff0000f fence -800000bc: 00100193 li gp,1 -800000c0: 05d00893 li a7,93 -800000c4: 00000513 li a0,0 -800000c8: 00000073 ecall -800000cc: 80000297 auipc t0,0x80000 -800000d0: f3428293 addi t0,t0,-204 # 0 <_start-0x80000000> -800000d4: 00028e63 beqz t0,800000f0 -800000d8: 10529073 csrw stvec,t0 -800000dc: 0000b2b7 lui t0,0xb -800000e0: 10928293 addi t0,t0,265 # b109 <_start-0x7fff4ef7> -800000e4: 30229073 csrw medeleg,t0 -800000e8: 30202373 csrr t1,medeleg -800000ec: f46298e3 bne t0,t1,8000003c -800000f0: 30005073 csrwi mstatus,0 -800000f4: 00000297 auipc t0,0x0 -800000f8: 01428293 addi t0,t0,20 # 80000108 -800000fc: 34129073 csrw mepc,t0 -80000100: f1402573 csrr a0,mhartid -80000104: 30200073 mret - -80000108 : -80000108: 00200193 li gp,2 -8000010c: 00000093 li ra,0 -80000110: 00100113 li sp,1 -80000114: 00209663 bne ra,sp,80000120 -80000118: 2a301a63 bne zero,gp,800003cc -8000011c: 00301663 bne zero,gp,80000128 -80000120: fe209ee3 bne ra,sp,8000011c -80000124: 2a301463 bne zero,gp,800003cc - -80000128 : -80000128: 00300193 li gp,3 -8000012c: 00100093 li ra,1 -80000130: 00000113 li sp,0 -80000134: 00209663 bne ra,sp,80000140 -80000138: 28301a63 bne zero,gp,800003cc -8000013c: 00301663 bne zero,gp,80000148 -80000140: fe209ee3 bne ra,sp,8000013c -80000144: 28301463 bne zero,gp,800003cc - -80000148 : -80000148: 00400193 li gp,4 -8000014c: fff00093 li ra,-1 -80000150: 00100113 li sp,1 -80000154: 00209663 bne ra,sp,80000160 -80000158: 26301a63 bne zero,gp,800003cc -8000015c: 00301663 bne zero,gp,80000168 -80000160: fe209ee3 bne ra,sp,8000015c -80000164: 26301463 bne zero,gp,800003cc - -80000168 : -80000168: 00500193 li gp,5 -8000016c: 00100093 li ra,1 -80000170: fff00113 li sp,-1 -80000174: 00209663 bne ra,sp,80000180 -80000178: 24301a63 bne zero,gp,800003cc -8000017c: 00301663 bne zero,gp,80000188 -80000180: fe209ee3 bne ra,sp,8000017c -80000184: 24301463 bne zero,gp,800003cc - -80000188 : -80000188: 00600193 li gp,6 -8000018c: 00000093 li ra,0 -80000190: 00000113 li sp,0 -80000194: 00209463 bne ra,sp,8000019c -80000198: 00301463 bne zero,gp,800001a0 -8000019c: 22301863 bne zero,gp,800003cc -800001a0: fe209ee3 bne ra,sp,8000019c - -800001a4 : -800001a4: 00700193 li gp,7 -800001a8: 00100093 li ra,1 -800001ac: 00100113 li sp,1 -800001b0: 00209463 bne ra,sp,800001b8 -800001b4: 00301463 bne zero,gp,800001bc -800001b8: 20301a63 bne zero,gp,800003cc -800001bc: fe209ee3 bne ra,sp,800001b8 - -800001c0 : -800001c0: 00800193 li gp,8 -800001c4: fff00093 li ra,-1 -800001c8: fff00113 li sp,-1 -800001cc: 00209463 bne ra,sp,800001d4 -800001d0: 00301463 bne zero,gp,800001d8 -800001d4: 1e301c63 bne zero,gp,800003cc -800001d8: fe209ee3 bne ra,sp,800001d4 - -800001dc : -800001dc: 00900193 li gp,9 -800001e0: 00000213 li tp,0 -800001e4: 00000093 li ra,0 -800001e8: 00000113 li sp,0 -800001ec: 1e209063 bne ra,sp,800003cc -800001f0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -800001f4: 00200293 li t0,2 -800001f8: fe5216e3 bne tp,t0,800001e4 - -800001fc : -800001fc: 00a00193 li gp,10 -80000200: 00000213 li tp,0 -80000204: 00000093 li ra,0 -80000208: 00000113 li sp,0 -8000020c: 00000013 nop -80000210: 1a209e63 bne ra,sp,800003cc -80000214: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000218: 00200293 li t0,2 -8000021c: fe5214e3 bne tp,t0,80000204 - -80000220 : -80000220: 00b00193 li gp,11 -80000224: 00000213 li tp,0 -80000228: 00000093 li ra,0 -8000022c: 00000113 li sp,0 -80000230: 00000013 nop -80000234: 00000013 nop -80000238: 18209a63 bne ra,sp,800003cc -8000023c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000240: 00200293 li t0,2 -80000244: fe5212e3 bne tp,t0,80000228 - -80000248 : -80000248: 00c00193 li gp,12 -8000024c: 00000213 li tp,0 -80000250: 00000093 li ra,0 -80000254: 00000013 nop -80000258: 00000113 li sp,0 -8000025c: 16209863 bne ra,sp,800003cc -80000260: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000264: 00200293 li t0,2 -80000268: fe5214e3 bne tp,t0,80000250 - -8000026c : -8000026c: 00d00193 li gp,13 -80000270: 00000213 li tp,0 -80000274: 00000093 li ra,0 -80000278: 00000013 nop -8000027c: 00000113 li sp,0 -80000280: 00000013 nop -80000284: 14209463 bne ra,sp,800003cc -80000288: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -8000028c: 00200293 li t0,2 -80000290: fe5212e3 bne tp,t0,80000274 - -80000294 : -80000294: 00e00193 li gp,14 -80000298: 00000213 li tp,0 -8000029c: 00000093 li ra,0 -800002a0: 00000013 nop -800002a4: 00000013 nop -800002a8: 00000113 li sp,0 -800002ac: 12209063 bne ra,sp,800003cc -800002b0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -800002b4: 00200293 li t0,2 -800002b8: fe5212e3 bne tp,t0,8000029c - -800002bc : -800002bc: 00f00193 li gp,15 -800002c0: 00000213 li tp,0 -800002c4: 00000093 li ra,0 -800002c8: 00000113 li sp,0 -800002cc: 10209063 bne ra,sp,800003cc -800002d0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -800002d4: 00200293 li t0,2 -800002d8: fe5216e3 bne tp,t0,800002c4 - -800002dc : -800002dc: 01000193 li gp,16 -800002e0: 00000213 li tp,0 -800002e4: 00000093 li ra,0 -800002e8: 00000113 li sp,0 -800002ec: 00000013 nop -800002f0: 0c209e63 bne ra,sp,800003cc -800002f4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -800002f8: 00200293 li t0,2 -800002fc: fe5214e3 bne tp,t0,800002e4 - -80000300 : -80000300: 01100193 li gp,17 -80000304: 00000213 li tp,0 -80000308: 00000093 li ra,0 -8000030c: 00000113 li sp,0 -80000310: 00000013 nop -80000314: 00000013 nop -80000318: 0a209a63 bne ra,sp,800003cc -8000031c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000320: 00200293 li t0,2 -80000324: fe5212e3 bne tp,t0,80000308 - -80000328 : -80000328: 01200193 li gp,18 -8000032c: 00000213 li tp,0 -80000330: 00000093 li ra,0 -80000334: 00000013 nop -80000338: 00000113 li sp,0 -8000033c: 08209863 bne ra,sp,800003cc -80000340: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000344: 00200293 li t0,2 -80000348: fe5214e3 bne tp,t0,80000330 - -8000034c : -8000034c: 01300193 li gp,19 -80000350: 00000213 li tp,0 -80000354: 00000093 li ra,0 -80000358: 00000013 nop -8000035c: 00000113 li sp,0 -80000360: 00000013 nop -80000364: 06209463 bne ra,sp,800003cc -80000368: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -8000036c: 00200293 li t0,2 -80000370: fe5212e3 bne tp,t0,80000354 - -80000374 : -80000374: 01400193 li gp,20 -80000378: 00000213 li tp,0 -8000037c: 00000093 li ra,0 -80000380: 00000013 nop -80000384: 00000013 nop -80000388: 00000113 li sp,0 -8000038c: 04209063 bne ra,sp,800003cc -80000390: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000394: 00200293 li t0,2 -80000398: fe5212e3 bne tp,t0,8000037c - -8000039c : -8000039c: 00100093 li ra,1 -800003a0: 00009a63 bnez ra,800003b4 -800003a4: 00108093 addi ra,ra,1 -800003a8: 00108093 addi ra,ra,1 -800003ac: 00108093 addi ra,ra,1 -800003b0: 00108093 addi ra,ra,1 -800003b4: 00108093 addi ra,ra,1 -800003b8: 00108093 addi ra,ra,1 -800003bc: 00300e93 li t4,3 -800003c0: 01500193 li gp,21 -800003c4: 01d09463 bne ra,t4,800003cc -800003c8: 02301063 bne zero,gp,800003e8 - -800003cc : -800003cc: 0ff0000f fence -800003d0: 00018063 beqz gp,800003d0 -800003d4: 00119193 slli gp,gp,0x1 -800003d8: 0011e193 ori gp,gp,1 -800003dc: 05d00893 li a7,93 -800003e0: 00018513 mv a0,gp -800003e4: 00000073 ecall - -800003e8 : -800003e8: 0ff0000f fence -800003ec: 00100193 li gp,1 -800003f0: 05d00893 li a7,93 -800003f4: 00000513 li a0,0 -800003f8: 00000073 ecall -800003fc: c0001073 unimp -80000400: 0000 unimp -80000402: 0000 unimp diff --git a/benchmarks/riscv_tests/rv32ui-p-bne.hex b/benchmarks/riscv_tests/rv32ui-p-bne.hex deleted file mode 100644 index 83bb9db9..00000000 --- a/benchmarks/riscv_tests/rv32ui-p-bne.hex +++ /dev/null @@ -1,69 +0,0 @@ -:0200000480007A -:100000006F00C004732F2034930F8000630AFF0336 -:10001000930F90006306FF03930FB0006302FF038A -:10002000170F0080130F0FFE63040F0067000F000F -:10003000732F203463540F006F004000136E9E53E3 -:10004000171F00002320CFFD6FF09FFF732540F1A5 -:100050006310050073251030635805000F00F00F82 -:10006000130E100073000000130E00009702000032 -:10007000938282F973905230735020307350303035 -:1000800073504030970200809382C2F7638C020065 -:10009000739052109302B01A739022307323203061 -:1000A000E39E62F873500030970200009382420191 -:1000B00073901234732540F173002030130E20002A -:1000C000930000001301100063962000631AC02BF8 -:1000D0006316C001E39E20FE6314C02B130E300094 -:1000E000930010001301000063962000631AC029DA -:1000F0006316C001E39E20FE6314C029130E400066 -:100100009300F0FF1301100063962000631AC027CC -:100110006316C001E39E20FE6314C027130E500037 -:10012000930010001301F0FF63962000631AC025AE -:100130006316C001E39E20FE6314C025130E600009 -:100140009300000013010000639420006314C001B9 -:100150006318C023E39E20FE130E7000930010006E -:1001600013011000639420006314C001631AC021BE -:10017000E39E20FE130E80009300F0FF1301F0FFBA -:10018000639420006314C001631CC01FE39E20FE23 -:10019000130E9000130200009300000013010000F2 -:1001A0006390201E1302120093022000E31652FEF9 -:1001B000130EA000130200009300000013010000C2 -:1001C00013000000639E201A130212009302200005 -:1001D000E31452FE130EB00013020000930000005F -:1001E000130100001300000013000000639A2018A0 -:1001F0001302120093022000E31252FE130EC000FD -:10020000130200009300000013000000130100001F -:10021000639820161302120093022000E31452FE8A -:10022000130ED00013020000930000001300000022 -:100230001301000013000000639420141302120045 -:1002400093022000E31252FE130EE000130200009E -:1002500093000000130000001300000013010000D1 -:10026000639020121302120093022000E31252FE48 -:10027000130EF000130200009300000013010000B1 -:10028000639020101302120093022000E31652FE26 -:10029000130E000113020000930000001301000080 -:1002A00013000000639E200C130212009302200032 -:1002B000E31452FE130E100113020000930000001D -:1002C000130100001300000013000000639A200ACD -:1002D0001302120093022000E31252FE130E2001BB -:1002E000130200009300000013000000130100003F -:1002F000639820081302120093022000E31452FEB8 -:10030000130E3001130200009300000013000000E0 -:100310001301000013000000639420061302120072 -:1003200093022000E31252FE130E4001130200005C -:1003300093000000130000001300000013010000F0 -:10034000639020041302120093022000E31252FE75 -:1003500093001000639A00009380100093801000B7 -:100360009380100093801000938010009380100001 -:10037000930E3000130E50016394D001631CC00132 -:100380000F00F00F63000E00131E1E00136E1E0000 -:10039000730000000F00F00F130E10007300000038 -:1003A000731000C00000000000000000000000000A -:1003B000000000000000000000000000000000003D -:0403C0000000000039 -:1010000000000000000000000000000000000000E0 -:1010100000000000000000000000000000000000D0 -:1010200000000000000000000000000000000000C0 -:1010300000000000000000000000000000000000B0 -:081040000000000000000000A8 -:040000058000200057 -:00000001FF diff --git a/benchmarks/riscv_tests/rv32ui-p-fence_i.dump b/benchmarks/riscv_tests/rv32ui-p-fence_i.dump deleted file mode 100644 index 492e0add..00000000 --- a/benchmarks/riscv_tests/rv32ui-p-fence_i.dump +++ /dev/null @@ -1,179 +0,0 @@ - -rv32ui-p-fence_i: file format elf32-littleriscv - - -Disassembly of section .text.init: - -80000000 <_start>: -80000000: 04c0006f j 8000004c - -80000004 : -80000004: 34202f73 csrr t5,mcause -80000008: 00800f93 li t6,8 -8000000c: 03ff0a63 beq t5,t6,80000040 -80000010: 00900f93 li t6,9 -80000014: 03ff0663 beq t5,t6,80000040 -80000018: 00b00f93 li t6,11 -8000001c: 03ff0263 beq t5,t6,80000040 -80000020: 80000f17 auipc t5,0x80000 -80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> -80000028: 000f0463 beqz t5,80000030 -8000002c: 000f0067 jr t5 -80000030: 34202f73 csrr t5,mcause -80000034: 000f5463 bgez t5,8000003c -80000038: 0040006f j 8000003c - -8000003c : -8000003c: 5391e193 ori gp,gp,1337 - -80000040 : -80000040: 00001f17 auipc t5,0x1 -80000044: fc3f2023 sw gp,-64(t5) # 80001000 -80000048: ff9ff06f j 80000040 - -8000004c : -8000004c: f1402573 csrr a0,mhartid -80000050: 00051063 bnez a0,80000050 -80000054: 00000297 auipc t0,0x0 -80000058: 01028293 addi t0,t0,16 # 80000064 -8000005c: 30529073 csrw mtvec,t0 -80000060: 18005073 csrwi satp,0 -80000064: 00000297 auipc t0,0x0 -80000068: 02028293 addi t0,t0,32 # 80000084 -8000006c: 30529073 csrw mtvec,t0 -80000070: 800002b7 lui t0,0x80000 -80000074: fff28293 addi t0,t0,-1 # 7fffffff <_end+0xffffdfef> -80000078: 3b029073 csrw pmpaddr0,t0 -8000007c: 01f00293 li t0,31 -80000080: 3a029073 csrw pmpcfg0,t0 -80000084: 00000297 auipc t0,0x0 -80000088: 01828293 addi t0,t0,24 # 8000009c -8000008c: 30529073 csrw mtvec,t0 -80000090: 30205073 csrwi medeleg,0 -80000094: 30305073 csrwi mideleg,0 -80000098: 30405073 csrwi mie,0 -8000009c: 00000193 li gp,0 -800000a0: 00000297 auipc t0,0x0 -800000a4: f6428293 addi t0,t0,-156 # 80000004 -800000a8: 30529073 csrw mtvec,t0 -800000ac: 00100513 li a0,1 -800000b0: 01f51513 slli a0,a0,0x1f -800000b4: 00054c63 bltz a0,800000cc -800000b8: 0ff0000f fence -800000bc: 00100193 li gp,1 -800000c0: 05d00893 li a7,93 -800000c4: 00000513 li a0,0 -800000c8: 00000073 ecall -800000cc: 80000297 auipc t0,0x80000 -800000d0: f3428293 addi t0,t0,-204 # 0 <_start-0x80000000> -800000d4: 00028e63 beqz t0,800000f0 -800000d8: 10529073 csrw stvec,t0 -800000dc: 0000b2b7 lui t0,0xb -800000e0: 10928293 addi t0,t0,265 # b109 <_start-0x7fff4ef7> -800000e4: 30229073 csrw medeleg,t0 -800000e8: 30202373 csrr t1,medeleg -800000ec: f46298e3 bne t0,t1,8000003c -800000f0: 30005073 csrwi mstatus,0 -800000f4: 00000297 auipc t0,0x0 -800000f8: 01428293 addi t0,t0,20 # 80000108 -800000fc: 34129073 csrw mepc,t0 -80000100: f1402573 csrr a0,mhartid -80000104: 30200073 mret -80000108: 06f00693 li a3,111 -8000010c: 00002517 auipc a0,0x2 -80000110: ef451503 lh a0,-268(a0) # 80002000 -80000114: 00002597 auipc a1,0x2 -80000118: eee59583 lh a1,-274(a1) # 80002002 -8000011c: 00000013 nop -80000120: 00000013 nop -80000124: 00000013 nop -80000128: 00000013 nop -8000012c: 00000013 nop -80000130: 00000013 nop -80000134: 00000013 nop -80000138: 00000013 nop -8000013c: 00000013 nop -80000140: 00000297 auipc t0,0x0 -80000144: 00a29a23 sh a0,20(t0) # 80000154 -80000148: 00000297 auipc t0,0x0 -8000014c: 00b29723 sh a1,14(t0) # 80000156 -80000150: 0000100f fence.i -80000154: 0de68693 addi a3,a3,222 - -80000158 : -80000158: 00000013 nop -8000015c: 1bc00e93 li t4,444 -80000160: 00200193 li gp,2 -80000164: 07d69a63 bne a3,t4,800001d8 -80000168: 06400713 li a4,100 -8000016c: fff70713 addi a4,a4,-1 -80000170: fe071ee3 bnez a4,8000016c -80000174: 00000297 auipc t0,0x0 -80000178: 04a29623 sh a0,76(t0) # 800001c0 -8000017c: 00000297 auipc t0,0x0 -80000180: 04b29323 sh a1,70(t0) # 800001c2 -80000184: 0000100f fence.i -80000188: 00000013 nop -8000018c: 00000013 nop -80000190: 00000013 nop -80000194: 00000013 nop -80000198: 00000013 nop -8000019c: 00000013 nop -800001a0: 00000013 nop -800001a4: 00000013 nop -800001a8: 00000013 nop -800001ac: 00000013 nop -800001b0: 00000013 nop -800001b4: 00000013 nop -800001b8: 00000013 nop -800001bc: 00000013 nop -800001c0: 22b68693 addi a3,a3,555 - -800001c4 : -800001c4: 00000013 nop -800001c8: 30900e93 li t4,777 -800001cc: 00300193 li gp,3 -800001d0: 01d69463 bne a3,t4,800001d8 -800001d4: 02301063 bne zero,gp,800001f4 - -800001d8 : -800001d8: 0ff0000f fence -800001dc: 00018063 beqz gp,800001dc -800001e0: 00119193 slli gp,gp,0x1 -800001e4: 0011e193 ori gp,gp,1 -800001e8: 05d00893 li a7,93 -800001ec: 00018513 mv a0,gp -800001f0: 00000073 ecall - -800001f4 : -800001f4: 0ff0000f fence -800001f8: 00100193 li gp,1 -800001fc: 05d00893 li a7,93 -80000200: 00000513 li a0,0 -80000204: 00000073 ecall -80000208: c0001073 unimp -8000020c: 0000 unimp -8000020e: 0000 unimp -80000210: 0000 unimp -80000212: 0000 unimp -80000214: 0000 unimp -80000216: 0000 unimp -80000218: 0000 unimp -8000021a: 0000 unimp -8000021c: 0000 unimp -8000021e: 0000 unimp -80000220: 0000 unimp -80000222: 0000 unimp -80000224: 0000 unimp -80000226: 0000 unimp - -Disassembly of section .data: - -80002000 : -80002000: 14d68693 addi a3,a3,333 -80002004: 0000 unimp -80002006: 0000 unimp -80002008: 0000 unimp -8000200a: 0000 unimp -8000200c: 0000 unimp -8000200e: 0000 unimp diff --git a/benchmarks/riscv_tests/rv32ui-p-fence_i.hex b/benchmarks/riscv_tests/rv32ui-p-fence_i.hex deleted file mode 100644 index 4823a04b..00000000 --- a/benchmarks/riscv_tests/rv32ui-p-fence_i.hex +++ /dev/null @@ -1,41 +0,0 @@ -:0200000480007A -:100000006F00C004732F2034930F8000630AFF0336 -:10001000930F90006306FF03930FB0006302FF038A -:10002000170F0080130F0FFE63040F0067000F000F -:10003000732F203463540F006F004000136E9E53E3 -:10004000171F00002320CFFD6FF09FFF732540F1A5 -:100050006310050073251030635805000F00F00F82 -:10006000130E100073000000130E00009702000032 -:10007000938282F973905230735020307350303035 -:1000800073504030970200809382C2F7638C020065 -:10009000739052109302B01A739022307323203061 -:1000A000E39E62F873500030970200009382420191 -:1000B00073901234732540F1730020309306F006DC -:1000C00017250000031505F4972500008395A5F377 -:1000D00013000000130000001300000013000000D4 -:1000E00013000000130000001300000013000000C4 -:1000F00013000000130000001300000013000000B4 -:1001000097020000239AA200970200002397B200F2 -:100110000F1000009386E60D13000000930EC01B25 -:10012000130E2000639AD607130740061307F7FF44 -:10013000E31E07FE970200002396A2049702000028 -:100140002393B2040F1000001300000013000000FE -:100150001300000013000000130000001300000053 -:100160001300000013000000130000001300000043 -:100170001300000013000000130000001300000033 -:100180009386B62213000000930E9030130E3000B9 -:100190006394D601631CC0010F00F00F63000E00D2 -:1001A000131E1E00136E1E00730000000F00F00FE0 -:1001B000130E100073000000731000C00000000058 -:1001C000000000000000000000000000000000002F -:1001D000000000000000000000000000000000001F -:1001E000000000000000000000000000000000000F -:0401F000000000000B -:1010000000000000000000000000000000000000E0 -:1010100000000000000000000000000000000000D0 -:1010200000000000000000000000000000000000C0 -:1010300000000000000000000000000000000000B0 -:081040000000000000000000A8 -:102000009386D614000000000000000000000000CD -:040000058000200057 -:00000001FF diff --git a/benchmarks/riscv_tests/rv32ui-p-jal.dump b/benchmarks/riscv_tests/rv32ui-p-jal.dump deleted file mode 100644 index 9d604b86..00000000 --- a/benchmarks/riscv_tests/rv32ui-p-jal.dump +++ /dev/null @@ -1,153 +0,0 @@ - -rv32ui-p-jal: file format elf32-littleriscv - - -Disassembly of section .text.init: - -80000000 <_start>: -80000000: 04c0006f j 8000004c - -80000004 : -80000004: 34202f73 csrr t5,mcause -80000008: 00800f93 li t6,8 -8000000c: 03ff0a63 beq t5,t6,80000040 -80000010: 00900f93 li t6,9 -80000014: 03ff0663 beq t5,t6,80000040 -80000018: 00b00f93 li t6,11 -8000001c: 03ff0263 beq t5,t6,80000040 -80000020: 80000f17 auipc t5,0x80000 -80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> -80000028: 000f0463 beqz t5,80000030 -8000002c: 000f0067 jr t5 -80000030: 34202f73 csrr t5,mcause -80000034: 000f5463 bgez t5,8000003c -80000038: 0040006f j 8000003c - -8000003c : -8000003c: 5391e193 ori gp,gp,1337 - -80000040 : -80000040: 00001f17 auipc t5,0x1 -80000044: fc3f2023 sw gp,-64(t5) # 80001000 -80000048: ff9ff06f j 80000040 - -8000004c : -8000004c: f1402573 csrr a0,mhartid -80000050: 00051063 bnez a0,80000050 -80000054: 00000297 auipc t0,0x0 -80000058: 01028293 addi t0,t0,16 # 80000064 -8000005c: 30529073 csrw mtvec,t0 -80000060: 18005073 csrwi satp,0 -80000064: 00000297 auipc t0,0x0 -80000068: 02028293 addi t0,t0,32 # 80000084 -8000006c: 30529073 csrw mtvec,t0 -80000070: 800002b7 lui t0,0x80000 -80000074: fff28293 addi t0,t0,-1 # 7fffffff <_end+0xffffdfff> -80000078: 3b029073 csrw pmpaddr0,t0 -8000007c: 01f00293 li t0,31 -80000080: 3a029073 csrw pmpcfg0,t0 -80000084: 00000297 auipc t0,0x0 -80000088: 01828293 addi t0,t0,24 # 8000009c -8000008c: 30529073 csrw mtvec,t0 -80000090: 30205073 csrwi medeleg,0 -80000094: 30305073 csrwi mideleg,0 -80000098: 30405073 csrwi mie,0 -8000009c: 00000193 li gp,0 -800000a0: 00000297 auipc t0,0x0 -800000a4: f6428293 addi t0,t0,-156 # 80000004 -800000a8: 30529073 csrw mtvec,t0 -800000ac: 00100513 li a0,1 -800000b0: 01f51513 slli a0,a0,0x1f -800000b4: 00054c63 bltz a0,800000cc -800000b8: 0ff0000f fence -800000bc: 00100193 li gp,1 -800000c0: 05d00893 li a7,93 -800000c4: 00000513 li a0,0 -800000c8: 00000073 ecall -800000cc: 80000297 auipc t0,0x80000 -800000d0: f3428293 addi t0,t0,-204 # 0 <_start-0x80000000> -800000d4: 00028e63 beqz t0,800000f0 -800000d8: 10529073 csrw stvec,t0 -800000dc: 0000b2b7 lui t0,0xb -800000e0: 10928293 addi t0,t0,265 # b109 <_start-0x7fff4ef7> -800000e4: 30229073 csrw medeleg,t0 -800000e8: 30202373 csrr t1,medeleg -800000ec: f46298e3 bne t0,t1,8000003c -800000f0: 30005073 csrwi mstatus,0 -800000f4: 00000297 auipc t0,0x0 -800000f8: 01428293 addi t0,t0,20 # 80000108 -800000fc: 34129073 csrw mepc,t0 -80000100: f1402573 csrr a0,mhartid -80000104: 30200073 mret - -80000108 : -80000108: 00200193 li gp,2 -8000010c: 00000093 li ra,0 -80000110: 0100026f jal tp,80000120 - -80000114 : -80000114: 00000013 nop -80000118: 00000013 nop -8000011c: 0400006f j 8000015c - -80000120 : -80000120: 00000117 auipc sp,0x0 -80000124: ff410113 addi sp,sp,-12 # 80000114 -80000128: 02411a63 bne sp,tp,8000015c - -8000012c : -8000012c: 00100093 li ra,1 -80000130: 0140006f j 80000144 -80000134: 00108093 addi ra,ra,1 -80000138: 00108093 addi ra,ra,1 -8000013c: 00108093 addi ra,ra,1 -80000140: 00108093 addi ra,ra,1 -80000144: 00108093 addi ra,ra,1 -80000148: 00108093 addi ra,ra,1 -8000014c: 00300e93 li t4,3 -80000150: 00300193 li gp,3 -80000154: 01d09463 bne ra,t4,8000015c -80000158: 02301063 bne zero,gp,80000178 - -8000015c : -8000015c: 0ff0000f fence -80000160: 00018063 beqz gp,80000160 -80000164: 00119193 slli gp,gp,0x1 -80000168: 0011e193 ori gp,gp,1 -8000016c: 05d00893 li a7,93 -80000170: 00018513 mv a0,gp -80000174: 00000073 ecall - -80000178 : -80000178: 0ff0000f fence -8000017c: 00100193 li gp,1 -80000180: 05d00893 li a7,93 -80000184: 00000513 li a0,0 -80000188: 00000073 ecall -8000018c: c0001073 unimp -80000190: 0000 unimp -80000192: 0000 unimp -80000194: 0000 unimp -80000196: 0000 unimp -80000198: 0000 unimp -8000019a: 0000 unimp -8000019c: 0000 unimp -8000019e: 0000 unimp -800001a0: 0000 unimp -800001a2: 0000 unimp -800001a4: 0000 unimp -800001a6: 0000 unimp -800001a8: 0000 unimp -800001aa: 0000 unimp -800001ac: 0000 unimp -800001ae: 0000 unimp -800001b0: 0000 unimp -800001b2: 0000 unimp -800001b4: 0000 unimp -800001b6: 0000 unimp -800001b8: 0000 unimp -800001ba: 0000 unimp -800001bc: 0000 unimp -800001be: 0000 unimp -800001c0: 0000 unimp -800001c2: 0000 unimp diff --git a/benchmarks/riscv_tests/rv32ui-p-jal.hex b/benchmarks/riscv_tests/rv32ui-p-jal.hex deleted file mode 100644 index f03aa976..00000000 --- a/benchmarks/riscv_tests/rv32ui-p-jal.hex +++ /dev/null @@ -1,29 +0,0 @@ -:0200000480007A -:100000006F00C004732F2034930F8000630AFF0336 -:10001000930F90006306FF03930FB0006302FF038A -:10002000170F0080130F0FFE63040F0067000F000F -:10003000732F203463540F006F004000136E9E53E3 -:10004000171F00002320CFFD6FF09FFF732540F1A5 -:100050006310050073251030635805000F00F00F82 -:10006000130E100073000000130E00009702000032 -:10007000938282F973905230735020307350303035 -:1000800073504030970200809382C2F7638C020065 -:10009000739052109302B01A739022307323203061 -:1000A000E39E62F873500030970200009382420191 -:1000B00073901234732540F173002030130E20002A -:1000C00093000000EF010001130000001300000086 -:1000D0006F00000417010000130141FF631A310291 -:1000E000930010006F004001938010009380100077 -:1000F0009380100093801000938010009380100074 -:10010000930E3000130E30006394D001631CC001C5 -:100110000F00F00F63000E00131E1E00136E1E0072 -:10012000730000000F00F00F130E100073000000AA -:10013000731000C00000000000000000000000007C -:0401400000000000BB -:1010000000000000000000000000000000000000E0 -:1010100000000000000000000000000000000000D0 -:1010200000000000000000000000000000000000C0 -:1010300000000000000000000000000000000000B0 -:081040000000000000000000A8 -:040000058000200057 -:00000001FF diff --git a/benchmarks/riscv_tests/rv32ui-p-jalr.dump b/benchmarks/riscv_tests/rv32ui-p-jalr.dump deleted file mode 100644 index 91db4db7..00000000 --- a/benchmarks/riscv_tests/rv32ui-p-jalr.dump +++ /dev/null @@ -1,191 +0,0 @@ - -rv32ui-p-jalr: file format elf32-littleriscv - - -Disassembly of section .text.init: - -80000000 <_start>: -80000000: 04c0006f j 8000004c - -80000004 : -80000004: 34202f73 csrr t5,mcause -80000008: 00800f93 li t6,8 -8000000c: 03ff0a63 beq t5,t6,80000040 -80000010: 00900f93 li t6,9 -80000014: 03ff0663 beq t5,t6,80000040 -80000018: 00b00f93 li t6,11 -8000001c: 03ff0263 beq t5,t6,80000040 -80000020: 80000f17 auipc t5,0x80000 -80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> -80000028: 000f0463 beqz t5,80000030 -8000002c: 000f0067 jr t5 -80000030: 34202f73 csrr t5,mcause -80000034: 000f5463 bgez t5,8000003c -80000038: 0040006f j 8000003c - -8000003c : -8000003c: 5391e193 ori gp,gp,1337 - -80000040 : -80000040: 00001f17 auipc t5,0x1 -80000044: fc3f2023 sw gp,-64(t5) # 80001000 -80000048: ff9ff06f j 80000040 - -8000004c : -8000004c: f1402573 csrr a0,mhartid -80000050: 00051063 bnez a0,80000050 -80000054: 00000297 auipc t0,0x0 -80000058: 01028293 addi t0,t0,16 # 80000064 -8000005c: 30529073 csrw mtvec,t0 -80000060: 18005073 csrwi satp,0 -80000064: 00000297 auipc t0,0x0 -80000068: 02028293 addi t0,t0,32 # 80000084 -8000006c: 30529073 csrw mtvec,t0 -80000070: 800002b7 lui t0,0x80000 -80000074: fff28293 addi t0,t0,-1 # 7fffffff <_end+0xffffdfff> -80000078: 3b029073 csrw pmpaddr0,t0 -8000007c: 01f00293 li t0,31 -80000080: 3a029073 csrw pmpcfg0,t0 -80000084: 00000297 auipc t0,0x0 -80000088: 01828293 addi t0,t0,24 # 8000009c -8000008c: 30529073 csrw mtvec,t0 -80000090: 30205073 csrwi medeleg,0 -80000094: 30305073 csrwi mideleg,0 -80000098: 30405073 csrwi mie,0 -8000009c: 00000193 li gp,0 -800000a0: 00000297 auipc t0,0x0 -800000a4: f6428293 addi t0,t0,-156 # 80000004 -800000a8: 30529073 csrw mtvec,t0 -800000ac: 00100513 li a0,1 -800000b0: 01f51513 slli a0,a0,0x1f -800000b4: 00054c63 bltz a0,800000cc -800000b8: 0ff0000f fence -800000bc: 00100193 li gp,1 -800000c0: 05d00893 li a7,93 -800000c4: 00000513 li a0,0 -800000c8: 00000073 ecall -800000cc: 80000297 auipc t0,0x80000 -800000d0: f3428293 addi t0,t0,-204 # 0 <_start-0x80000000> -800000d4: 00028e63 beqz t0,800000f0 -800000d8: 10529073 csrw stvec,t0 -800000dc: 0000b2b7 lui t0,0xb -800000e0: 10928293 addi t0,t0,265 # b109 <_start-0x7fff4ef7> -800000e4: 30229073 csrw medeleg,t0 -800000e8: 30202373 csrr t1,medeleg -800000ec: f46298e3 bne t0,t1,8000003c -800000f0: 30005073 csrwi mstatus,0 -800000f4: 00000297 auipc t0,0x0 -800000f8: 01428293 addi t0,t0,20 # 80000108 -800000fc: 34129073 csrw mepc,t0 -80000100: f1402573 csrr a0,mhartid -80000104: 30200073 mret - -80000108 : -80000108: 00200193 li gp,2 -8000010c: 00000293 li t0,0 -80000110: 00000317 auipc t1,0x0 -80000114: 01030313 addi t1,t1,16 # 80000120 -80000118: 000302e7 jalr t0,t1 - -8000011c : -8000011c: 0c00006f j 800001dc - -80000120 : -80000120: 00000317 auipc t1,0x0 -80000124: ffc30313 addi t1,t1,-4 # 8000011c -80000128: 0a629a63 bne t0,t1,800001dc - -8000012c : -8000012c: 00400193 li gp,4 -80000130: 00000213 li tp,0 -80000134: 00000317 auipc t1,0x0 -80000138: 01030313 addi t1,t1,16 # 80000144 -8000013c: 000306e7 jalr a3,t1 -80000140: 08301e63 bne zero,gp,800001dc -80000144: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000148: 00200293 li t0,2 -8000014c: fe5214e3 bne tp,t0,80000134 - -80000150 : -80000150: 00500193 li gp,5 -80000154: 00000213 li tp,0 -80000158: 00000317 auipc t1,0x0 -8000015c: 01430313 addi t1,t1,20 # 8000016c -80000160: 00000013 nop -80000164: 000306e7 jalr a3,t1 -80000168: 06301a63 bne zero,gp,800001dc -8000016c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000170: 00200293 li t0,2 -80000174: fe5212e3 bne tp,t0,80000158 - -80000178 : -80000178: 00600193 li gp,6 -8000017c: 00000213 li tp,0 -80000180: 00000317 auipc t1,0x0 -80000184: 01830313 addi t1,t1,24 # 80000198 -80000188: 00000013 nop -8000018c: 00000013 nop -80000190: 000306e7 jalr a3,t1 -80000194: 04301463 bne zero,gp,800001dc -80000198: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -8000019c: 00200293 li t0,2 -800001a0: fe5210e3 bne tp,t0,80000180 - -800001a4 : -800001a4: 00100293 li t0,1 -800001a8: 00000317 auipc t1,0x0 -800001ac: 01c30313 addi t1,t1,28 # 800001c4 -800001b0: ffc30067 jr -4(t1) -800001b4: 00128293 addi t0,t0,1 -800001b8: 00128293 addi t0,t0,1 -800001bc: 00128293 addi t0,t0,1 -800001c0: 00128293 addi t0,t0,1 -800001c4: 00128293 addi t0,t0,1 -800001c8: 00128293 addi t0,t0,1 -800001cc: 00400e93 li t4,4 -800001d0: 00700193 li gp,7 -800001d4: 01d29463 bne t0,t4,800001dc -800001d8: 02301063 bne zero,gp,800001f8 - -800001dc : -800001dc: 0ff0000f fence -800001e0: 00018063 beqz gp,800001e0 -800001e4: 00119193 slli gp,gp,0x1 -800001e8: 0011e193 ori gp,gp,1 -800001ec: 05d00893 li a7,93 -800001f0: 00018513 mv a0,gp -800001f4: 00000073 ecall - -800001f8 : -800001f8: 0ff0000f fence -800001fc: 00100193 li gp,1 -80000200: 05d00893 li a7,93 -80000204: 00000513 li a0,0 -80000208: 00000073 ecall -8000020c: c0001073 unimp -80000210: 0000 unimp -80000212: 0000 unimp -80000214: 0000 unimp -80000216: 0000 unimp -80000218: 0000 unimp -8000021a: 0000 unimp -8000021c: 0000 unimp -8000021e: 0000 unimp -80000220: 0000 unimp -80000222: 0000 unimp -80000224: 0000 unimp -80000226: 0000 unimp -80000228: 0000 unimp -8000022a: 0000 unimp -8000022c: 0000 unimp -8000022e: 0000 unimp -80000230: 0000 unimp -80000232: 0000 unimp -80000234: 0000 unimp -80000236: 0000 unimp -80000238: 0000 unimp -8000023a: 0000 unimp -8000023c: 0000 unimp -8000023e: 0000 unimp -80000240: 0000 unimp -80000242: 0000 unimp diff --git a/benchmarks/riscv_tests/rv32ui-p-jalr.hex b/benchmarks/riscv_tests/rv32ui-p-jalr.hex deleted file mode 100644 index 0381aae9..00000000 --- a/benchmarks/riscv_tests/rv32ui-p-jalr.hex +++ /dev/null @@ -1,37 +0,0 @@ -:0200000480007A -:100000006F00C004732F2034930F8000630AFF0336 -:10001000930F90006306FF03930FB0006302FF038A -:10002000170F0080130F0FFE63040F0067000F000F -:10003000732F203463540F006F004000136E9E53E3 -:10004000171F00002320CFFD6FF09FFF732540F1A5 -:100050006310050073251030635805000F00F00F82 -:10006000130E100073000000130E00009702000032 -:10007000938282F973905230735020307350303035 -:1000800073504030970200809382C2F7638C020065 -:10009000739052109302B01A739022307323203061 -:1000A000E39E62F873500030970200009382420191 -:1000B00073901234732540F173002030130E20002A -:1000C000930200001703000013030301E70203007B -:1000D0006F00000C170300001303C3FF639A620A4A -:1000E000130E400013020000170300001303030166 -:1000F000E7090300631EC0091302120093022000E7 -:10010000E31452FE130E5000130200001703000008 -:100110001303430113000000E7090300631AC0073B -:100120001302120093022000E31252FE130E60002D -:1001300013020000170300001303830113000000E3 -:1001400013000000E70903006314C0051302120046 -:1001500093022000E31052FE9302100017030000E8 -:100160001303C3016700C3FF93821200938212003E -:1001700093821200938212009382120093821200E3 -:10018000930E4000130E70006394D201631CC001F3 -:100190000F00F00F63000E00131E1E00136E1E00F2 -:1001A000730000000F00F00F130E1000730000002A -:1001B000731000C0000000000000000000000000FC -:0401C000000000003B -:1010000000000000000000000000000000000000E0 -:1010100000000000000000000000000000000000D0 -:1010200000000000000000000000000000000000C0 -:1010300000000000000000000000000000000000B0 -:081040000000000000000000A8 -:040000058000200057 -:00000001FF diff --git a/benchmarks/riscv_tests/rv32ui-p-lb.dump b/benchmarks/riscv_tests/rv32ui-p-lb.dump deleted file mode 100644 index 522d0b8b..00000000 --- a/benchmarks/riscv_tests/rv32ui-p-lb.dump +++ /dev/null @@ -1,331 +0,0 @@ - -rv32ui-p-lb: file format elf32-littleriscv - - -Disassembly of section .text.init: - -80000000 <_start>: -80000000: 04c0006f j 8000004c - -80000004 : -80000004: 34202f73 csrr t5,mcause -80000008: 00800f93 li t6,8 -8000000c: 03ff0a63 beq t5,t6,80000040 -80000010: 00900f93 li t6,9 -80000014: 03ff0663 beq t5,t6,80000040 -80000018: 00b00f93 li t6,11 -8000001c: 03ff0263 beq t5,t6,80000040 -80000020: 80000f17 auipc t5,0x80000 -80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> -80000028: 000f0463 beqz t5,80000030 -8000002c: 000f0067 jr t5 -80000030: 34202f73 csrr t5,mcause -80000034: 000f5463 bgez t5,8000003c -80000038: 0040006f j 8000003c - -8000003c : -8000003c: 5391e193 ori gp,gp,1337 - -80000040 : -80000040: 00001f17 auipc t5,0x1 -80000044: fc3f2023 sw gp,-64(t5) # 80001000 -80000048: ff9ff06f j 80000040 - -8000004c : -8000004c: f1402573 csrr a0,mhartid -80000050: 00051063 bnez a0,80000050 -80000054: 00000297 auipc t0,0x0 -80000058: 01028293 addi t0,t0,16 # 80000064 -8000005c: 30529073 csrw mtvec,t0 -80000060: 18005073 csrwi satp,0 -80000064: 00000297 auipc t0,0x0 -80000068: 02028293 addi t0,t0,32 # 80000084 -8000006c: 30529073 csrw mtvec,t0 -80000070: 800002b7 lui t0,0x80000 -80000074: fff28293 addi t0,t0,-1 # 7fffffff <_end+0xffffdfef> -80000078: 3b029073 csrw pmpaddr0,t0 -8000007c: 01f00293 li t0,31 -80000080: 3a029073 csrw pmpcfg0,t0 -80000084: 00000297 auipc t0,0x0 -80000088: 01828293 addi t0,t0,24 # 8000009c -8000008c: 30529073 csrw mtvec,t0 -80000090: 30205073 csrwi medeleg,0 -80000094: 30305073 csrwi mideleg,0 -80000098: 30405073 csrwi mie,0 -8000009c: 00000193 li gp,0 -800000a0: 00000297 auipc t0,0x0 -800000a4: f6428293 addi t0,t0,-156 # 80000004 -800000a8: 30529073 csrw mtvec,t0 -800000ac: 00100513 li a0,1 -800000b0: 01f51513 slli a0,a0,0x1f -800000b4: 00054c63 bltz a0,800000cc -800000b8: 0ff0000f fence -800000bc: 00100193 li gp,1 -800000c0: 05d00893 li a7,93 -800000c4: 00000513 li a0,0 -800000c8: 00000073 ecall -800000cc: 80000297 auipc t0,0x80000 -800000d0: f3428293 addi t0,t0,-204 # 0 <_start-0x80000000> -800000d4: 00028e63 beqz t0,800000f0 -800000d8: 10529073 csrw stvec,t0 -800000dc: 0000b2b7 lui t0,0xb -800000e0: 10928293 addi t0,t0,265 # b109 <_start-0x7fff4ef7> -800000e4: 30229073 csrw medeleg,t0 -800000e8: 30202373 csrr t1,medeleg -800000ec: f46298e3 bne t0,t1,8000003c -800000f0: 30005073 csrwi mstatus,0 -800000f4: 00000297 auipc t0,0x0 -800000f8: 01428293 addi t0,t0,20 # 80000108 -800000fc: 34129073 csrw mepc,t0 -80000100: f1402573 csrr a0,mhartid -80000104: 30200073 mret - -80000108 : -80000108: 00002097 auipc ra,0x2 -8000010c: ef808093 addi ra,ra,-264 # 80002000 -80000110: 00008703 lb a4,0(ra) -80000114: fff00e93 li t4,-1 -80000118: 00200193 li gp,2 -8000011c: 23d71c63 bne a4,t4,80000354 - -80000120 : -80000120: 00002097 auipc ra,0x2 -80000124: ee008093 addi ra,ra,-288 # 80002000 -80000128: 00108703 lb a4,1(ra) -8000012c: 00000e93 li t4,0 -80000130: 00300193 li gp,3 -80000134: 23d71063 bne a4,t4,80000354 - -80000138 : -80000138: 00002097 auipc ra,0x2 -8000013c: ec808093 addi ra,ra,-312 # 80002000 -80000140: 00208703 lb a4,2(ra) -80000144: ff000e93 li t4,-16 -80000148: 00400193 li gp,4 -8000014c: 21d71463 bne a4,t4,80000354 - -80000150 : -80000150: 00002097 auipc ra,0x2 -80000154: eb008093 addi ra,ra,-336 # 80002000 -80000158: 00308703 lb a4,3(ra) -8000015c: 00f00e93 li t4,15 -80000160: 00500193 li gp,5 -80000164: 1fd71863 bne a4,t4,80000354 - -80000168 : -80000168: 00002097 auipc ra,0x2 -8000016c: e9b08093 addi ra,ra,-357 # 80002003 -80000170: ffd08703 lb a4,-3(ra) -80000174: fff00e93 li t4,-1 -80000178: 00600193 li gp,6 -8000017c: 1dd71c63 bne a4,t4,80000354 - -80000180 : -80000180: 00002097 auipc ra,0x2 -80000184: e8308093 addi ra,ra,-381 # 80002003 -80000188: ffe08703 lb a4,-2(ra) -8000018c: 00000e93 li t4,0 -80000190: 00700193 li gp,7 -80000194: 1dd71063 bne a4,t4,80000354 - -80000198 : -80000198: 00002097 auipc ra,0x2 -8000019c: e6b08093 addi ra,ra,-405 # 80002003 -800001a0: fff08703 lb a4,-1(ra) -800001a4: ff000e93 li t4,-16 -800001a8: 00800193 li gp,8 -800001ac: 1bd71463 bne a4,t4,80000354 - -800001b0 : -800001b0: 00002097 auipc ra,0x2 -800001b4: e5308093 addi ra,ra,-429 # 80002003 -800001b8: 00008703 lb a4,0(ra) -800001bc: 00f00e93 li t4,15 -800001c0: 00900193 li gp,9 -800001c4: 19d71863 bne a4,t4,80000354 - -800001c8 : -800001c8: 00002097 auipc ra,0x2 -800001cc: e3808093 addi ra,ra,-456 # 80002000 -800001d0: fe008093 addi ra,ra,-32 -800001d4: 02008283 lb t0,32(ra) -800001d8: fff00e93 li t4,-1 -800001dc: 00a00193 li gp,10 -800001e0: 17d29a63 bne t0,t4,80000354 - -800001e4 : -800001e4: 00002097 auipc ra,0x2 -800001e8: e1c08093 addi ra,ra,-484 # 80002000 -800001ec: ffa08093 addi ra,ra,-6 -800001f0: 00708283 lb t0,7(ra) -800001f4: 00000e93 li t4,0 -800001f8: 00b00193 li gp,11 -800001fc: 15d29c63 bne t0,t4,80000354 - -80000200 : -80000200: 00c00193 li gp,12 -80000204: 00000213 li tp,0 -80000208: 00002097 auipc ra,0x2 -8000020c: df908093 addi ra,ra,-519 # 80002001 -80000210: 00108703 lb a4,1(ra) -80000214: 00070313 mv t1,a4 -80000218: ff000e93 li t4,-16 -8000021c: 13d31c63 bne t1,t4,80000354 -80000220: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000224: 00200293 li t0,2 -80000228: fe5210e3 bne tp,t0,80000208 - -8000022c : -8000022c: 00d00193 li gp,13 -80000230: 00000213 li tp,0 -80000234: 00002097 auipc ra,0x2 -80000238: dce08093 addi ra,ra,-562 # 80002002 -8000023c: 00108703 lb a4,1(ra) -80000240: 00000013 nop -80000244: 00070313 mv t1,a4 -80000248: 00f00e93 li t4,15 -8000024c: 11d31463 bne t1,t4,80000354 -80000250: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000254: 00200293 li t0,2 -80000258: fc521ee3 bne tp,t0,80000234 - -8000025c : -8000025c: 00e00193 li gp,14 -80000260: 00000213 li tp,0 -80000264: 00002097 auipc ra,0x2 -80000268: d9c08093 addi ra,ra,-612 # 80002000 -8000026c: 00108703 lb a4,1(ra) -80000270: 00000013 nop -80000274: 00000013 nop -80000278: 00070313 mv t1,a4 -8000027c: 00000e93 li t4,0 -80000280: 0dd31a63 bne t1,t4,80000354 -80000284: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000288: 00200293 li t0,2 -8000028c: fc521ce3 bne tp,t0,80000264 - -80000290 : -80000290: 00f00193 li gp,15 -80000294: 00000213 li tp,0 -80000298: 00002097 auipc ra,0x2 -8000029c: d6908093 addi ra,ra,-663 # 80002001 -800002a0: 00108703 lb a4,1(ra) -800002a4: ff000e93 li t4,-16 -800002a8: 0bd71663 bne a4,t4,80000354 -800002ac: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -800002b0: 00200293 li t0,2 -800002b4: fe5212e3 bne tp,t0,80000298 - -800002b8 : -800002b8: 01000193 li gp,16 -800002bc: 00000213 li tp,0 -800002c0: 00002097 auipc ra,0x2 -800002c4: d4208093 addi ra,ra,-702 # 80002002 -800002c8: 00000013 nop -800002cc: 00108703 lb a4,1(ra) -800002d0: 00f00e93 li t4,15 -800002d4: 09d71063 bne a4,t4,80000354 -800002d8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -800002dc: 00200293 li t0,2 -800002e0: fe5210e3 bne tp,t0,800002c0 - -800002e4 : -800002e4: 01100193 li gp,17 -800002e8: 00000213 li tp,0 -800002ec: 00002097 auipc ra,0x2 -800002f0: d1408093 addi ra,ra,-748 # 80002000 -800002f4: 00000013 nop -800002f8: 00000013 nop -800002fc: 00108703 lb a4,1(ra) -80000300: 00000e93 li t4,0 -80000304: 05d71863 bne a4,t4,80000354 -80000308: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -8000030c: 00200293 li t0,2 -80000310: fc521ee3 bne tp,t0,800002ec - -80000314 : -80000314: 00002297 auipc t0,0x2 -80000318: cec28293 addi t0,t0,-788 # 80002000 -8000031c: 00028103 lb sp,0(t0) -80000320: 00200113 li sp,2 -80000324: 00200e93 li t4,2 -80000328: 01200193 li gp,18 -8000032c: 03d11463 bne sp,t4,80000354 - -80000330 : -80000330: 00002297 auipc t0,0x2 -80000334: cd028293 addi t0,t0,-816 # 80002000 -80000338: 00028103 lb sp,0(t0) -8000033c: 00000013 nop -80000340: 00200113 li sp,2 -80000344: 00200e93 li t4,2 -80000348: 01300193 li gp,19 -8000034c: 01d11463 bne sp,t4,80000354 -80000350: 02301063 bne zero,gp,80000370 - -80000354 : -80000354: 0ff0000f fence -80000358: 00018063 beqz gp,80000358 -8000035c: 00119193 slli gp,gp,0x1 -80000360: 0011e193 ori gp,gp,1 -80000364: 05d00893 li a7,93 -80000368: 00018513 mv a0,gp -8000036c: 00000073 ecall - -80000370 : -80000370: 0ff0000f fence -80000374: 00100193 li gp,1 -80000378: 05d00893 li a7,93 -8000037c: 00000513 li a0,0 -80000380: 00000073 ecall -80000384: c0001073 unimp -80000388: 0000 unimp -8000038a: 0000 unimp -8000038c: 0000 unimp -8000038e: 0000 unimp -80000390: 0000 unimp -80000392: 0000 unimp -80000394: 0000 unimp -80000396: 0000 unimp -80000398: 0000 unimp -8000039a: 0000 unimp -8000039c: 0000 unimp -8000039e: 0000 unimp -800003a0: 0000 unimp -800003a2: 0000 unimp -800003a4: 0000 unimp -800003a6: 0000 unimp -800003a8: 0000 unimp -800003aa: 0000 unimp -800003ac: 0000 unimp -800003ae: 0000 unimp -800003b0: 0000 unimp -800003b2: 0000 unimp -800003b4: 0000 unimp -800003b6: 0000 unimp -800003b8: 0000 unimp -800003ba: 0000 unimp -800003bc: 0000 unimp -800003be: 0000 unimp -800003c0: 0000 unimp -800003c2: 0000 unimp - -Disassembly of section .data: - -80002000 : -80002000: 0xff - -80002001 : -80002001: fsw fs0,32(s0) - -80002002 : -80002002: addi a2,sp,988 - -80002003 : -80002003: 0000000f fence unknown,unknown -80002007: 0000 unimp -80002009: 0000 unimp -8000200b: 0000 unimp -8000200d: 0000 unimp -8000200f: 00 Address 0x000000008000200f is out of bounds. - diff --git a/benchmarks/riscv_tests/rv32ui-p-lb.hex b/benchmarks/riscv_tests/rv32ui-p-lb.hex deleted file mode 100644 index f91bb8b3..00000000 --- a/benchmarks/riscv_tests/rv32ui-p-lb.hex +++ /dev/null @@ -1,62 +0,0 @@ -:0200000480007A -:100000006F00C004732F2034930F8000630AFF0336 -:10001000930F90006306FF03930FB0006302FF038A -:10002000170F0080130F0FFE63040F0067000F000F -:10003000732F203463540F006F004000136E9E53E3 -:10004000171F00002320CFFD6FF09FFF732540F1A5 -:100050006310050073251030635805000F00F00F82 -:10006000130E100073000000130E00009702000032 -:10007000938282F973905230735020307350303035 -:1000800073504030970200809382C2F7638C020065 -:10009000739052109302B01A739022307323203061 -:1000A000E39E62F873500030970200009382420191 -:1000B00073901234732540F17300203097200000B4 -:1000C000938040F483810000930EF0FF130E200014 -:1000D000639CD123972000009380C0F2838110009D -:1000E000930E0000130E30006390D1239720000080 -:1000F000938040F183812000930E00FF130E400097 -:100100006394D121972000009380C0EF8381300059 -:10011000930EF000130E50006398D11F972000003B -:10012000938070EE8381D0FF930EF0FF130E60007A -:10013000639CD11D972000009380F0EC8381E0FF49 -:10014000930E0000130E70006390D11D97200000E5 -:10015000938070EB8381F0FF930E00FF130E8000FD -:100160006394D11B972000009380F0E98381000005 -:10017000930EF000130E90006398D11997200000A1 -:10018000938040E8938000FE83810002930EF0FF8D -:10019000130EA000639AD11797200000938080E689 -:1001A0009380A0FF83817000930E0000130EB000B7 -:1001B000639CD115130EC0001302000097200000AD -:1001C000938050E48381100013830100930E00FF9D -:1001D000631CD3131302120093022000E31052FE9B -:1001E000130ED00013020000972000009380A0E1BE -:1001F000838110001300000013830100930EF000B0 -:100200006314D3111302120093022000E31E52FC68 -:10021000130EE0001302000097200000938080DEA0 -:1002200083811000130000001300000013830100FD -:10023000930E0000631AD30D1302120093022000E4 -:10024000E31C52FC130EF000130200009720000084 -:10025000938050DB83811000930E00FF6396D10BD7 -:100260001302120093022000E31252FE130E00014B -:1002700013020000972000009380E0D813000000D4 -:1002800083811000930EF0006390D10913021200D5 -:1002900093022000E31052FE130E1001130200001F -:1002A00097200000938000D6130000001300000088 -:1002B00083811000930E00006398D1051302120091 -:1002C00093022000E31E52FC97210000938181D30A -:1002D0000381010013012000930E2000130E200162 -:1002E0006314D103972100009381C1D103810100E0 -:1002F0001300000013012000930E2000130E3001A4 -:100300006314D101631CC0010F00F00F63000E00E5 -:10031000131E1E00136E1E00730000000F00F00F6E -:10032000130E100073000000731000C000000000E6 -:1003300000000000000000000000000000000000BD -:0403400000000000B9 -:1010000000000000000000000000000000000000E0 -:1010100000000000000000000000000000000000D0 -:1010200000000000000000000000000000000000C0 -:1010300000000000000000000000000000000000B0 -:081040000000000000000000A8 -:10200000FF00F00F000000000000000000000000D2 -:040000058000200057 -:00000001FF diff --git a/benchmarks/riscv_tests/rv32ui-p-lbu.dump b/benchmarks/riscv_tests/rv32ui-p-lbu.dump deleted file mode 100644 index d30228b1..00000000 --- a/benchmarks/riscv_tests/rv32ui-p-lbu.dump +++ /dev/null @@ -1,331 +0,0 @@ - -rv32ui-p-lbu: file format elf32-littleriscv - - -Disassembly of section .text.init: - -80000000 <_start>: -80000000: 04c0006f j 8000004c - -80000004 : -80000004: 34202f73 csrr t5,mcause -80000008: 00800f93 li t6,8 -8000000c: 03ff0a63 beq t5,t6,80000040 -80000010: 00900f93 li t6,9 -80000014: 03ff0663 beq t5,t6,80000040 -80000018: 00b00f93 li t6,11 -8000001c: 03ff0263 beq t5,t6,80000040 -80000020: 80000f17 auipc t5,0x80000 -80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> -80000028: 000f0463 beqz t5,80000030 -8000002c: 000f0067 jr t5 -80000030: 34202f73 csrr t5,mcause -80000034: 000f5463 bgez t5,8000003c -80000038: 0040006f j 8000003c - -8000003c : -8000003c: 5391e193 ori gp,gp,1337 - -80000040 : -80000040: 00001f17 auipc t5,0x1 -80000044: fc3f2023 sw gp,-64(t5) # 80001000 -80000048: ff9ff06f j 80000040 - -8000004c : -8000004c: f1402573 csrr a0,mhartid -80000050: 00051063 bnez a0,80000050 -80000054: 00000297 auipc t0,0x0 -80000058: 01028293 addi t0,t0,16 # 80000064 -8000005c: 30529073 csrw mtvec,t0 -80000060: 18005073 csrwi satp,0 -80000064: 00000297 auipc t0,0x0 -80000068: 02028293 addi t0,t0,32 # 80000084 -8000006c: 30529073 csrw mtvec,t0 -80000070: 800002b7 lui t0,0x80000 -80000074: fff28293 addi t0,t0,-1 # 7fffffff <_end+0xffffdfef> -80000078: 3b029073 csrw pmpaddr0,t0 -8000007c: 01f00293 li t0,31 -80000080: 3a029073 csrw pmpcfg0,t0 -80000084: 00000297 auipc t0,0x0 -80000088: 01828293 addi t0,t0,24 # 8000009c -8000008c: 30529073 csrw mtvec,t0 -80000090: 30205073 csrwi medeleg,0 -80000094: 30305073 csrwi mideleg,0 -80000098: 30405073 csrwi mie,0 -8000009c: 00000193 li gp,0 -800000a0: 00000297 auipc t0,0x0 -800000a4: f6428293 addi t0,t0,-156 # 80000004 -800000a8: 30529073 csrw mtvec,t0 -800000ac: 00100513 li a0,1 -800000b0: 01f51513 slli a0,a0,0x1f -800000b4: 00054c63 bltz a0,800000cc -800000b8: 0ff0000f fence -800000bc: 00100193 li gp,1 -800000c0: 05d00893 li a7,93 -800000c4: 00000513 li a0,0 -800000c8: 00000073 ecall -800000cc: 80000297 auipc t0,0x80000 -800000d0: f3428293 addi t0,t0,-204 # 0 <_start-0x80000000> -800000d4: 00028e63 beqz t0,800000f0 -800000d8: 10529073 csrw stvec,t0 -800000dc: 0000b2b7 lui t0,0xb -800000e0: 10928293 addi t0,t0,265 # b109 <_start-0x7fff4ef7> -800000e4: 30229073 csrw medeleg,t0 -800000e8: 30202373 csrr t1,medeleg -800000ec: f46298e3 bne t0,t1,8000003c -800000f0: 30005073 csrwi mstatus,0 -800000f4: 00000297 auipc t0,0x0 -800000f8: 01428293 addi t0,t0,20 # 80000108 -800000fc: 34129073 csrw mepc,t0 -80000100: f1402573 csrr a0,mhartid -80000104: 30200073 mret - -80000108 : -80000108: 00002097 auipc ra,0x2 -8000010c: ef808093 addi ra,ra,-264 # 80002000 -80000110: 0000c703 lbu a4,0(ra) -80000114: 0ff00e93 li t4,255 -80000118: 00200193 li gp,2 -8000011c: 23d71c63 bne a4,t4,80000354 - -80000120 : -80000120: 00002097 auipc ra,0x2 -80000124: ee008093 addi ra,ra,-288 # 80002000 -80000128: 0010c703 lbu a4,1(ra) -8000012c: 00000e93 li t4,0 -80000130: 00300193 li gp,3 -80000134: 23d71063 bne a4,t4,80000354 - -80000138 : -80000138: 00002097 auipc ra,0x2 -8000013c: ec808093 addi ra,ra,-312 # 80002000 -80000140: 0020c703 lbu a4,2(ra) -80000144: 0f000e93 li t4,240 -80000148: 00400193 li gp,4 -8000014c: 21d71463 bne a4,t4,80000354 - -80000150 : -80000150: 00002097 auipc ra,0x2 -80000154: eb008093 addi ra,ra,-336 # 80002000 -80000158: 0030c703 lbu a4,3(ra) -8000015c: 00f00e93 li t4,15 -80000160: 00500193 li gp,5 -80000164: 1fd71863 bne a4,t4,80000354 - -80000168 : -80000168: 00002097 auipc ra,0x2 -8000016c: e9b08093 addi ra,ra,-357 # 80002003 -80000170: ffd0c703 lbu a4,-3(ra) -80000174: 0ff00e93 li t4,255 -80000178: 00600193 li gp,6 -8000017c: 1dd71c63 bne a4,t4,80000354 - -80000180 : -80000180: 00002097 auipc ra,0x2 -80000184: e8308093 addi ra,ra,-381 # 80002003 -80000188: ffe0c703 lbu a4,-2(ra) -8000018c: 00000e93 li t4,0 -80000190: 00700193 li gp,7 -80000194: 1dd71063 bne a4,t4,80000354 - -80000198 : -80000198: 00002097 auipc ra,0x2 -8000019c: e6b08093 addi ra,ra,-405 # 80002003 -800001a0: fff0c703 lbu a4,-1(ra) -800001a4: 0f000e93 li t4,240 -800001a8: 00800193 li gp,8 -800001ac: 1bd71463 bne a4,t4,80000354 - -800001b0 : -800001b0: 00002097 auipc ra,0x2 -800001b4: e5308093 addi ra,ra,-429 # 80002003 -800001b8: 0000c703 lbu a4,0(ra) -800001bc: 00f00e93 li t4,15 -800001c0: 00900193 li gp,9 -800001c4: 19d71863 bne a4,t4,80000354 - -800001c8 : -800001c8: 00002097 auipc ra,0x2 -800001cc: e3808093 addi ra,ra,-456 # 80002000 -800001d0: fe008093 addi ra,ra,-32 -800001d4: 0200c283 lbu t0,32(ra) -800001d8: 0ff00e93 li t4,255 -800001dc: 00a00193 li gp,10 -800001e0: 17d29a63 bne t0,t4,80000354 - -800001e4 : -800001e4: 00002097 auipc ra,0x2 -800001e8: e1c08093 addi ra,ra,-484 # 80002000 -800001ec: ffa08093 addi ra,ra,-6 -800001f0: 0070c283 lbu t0,7(ra) -800001f4: 00000e93 li t4,0 -800001f8: 00b00193 li gp,11 -800001fc: 15d29c63 bne t0,t4,80000354 - -80000200 : -80000200: 00c00193 li gp,12 -80000204: 00000213 li tp,0 -80000208: 00002097 auipc ra,0x2 -8000020c: df908093 addi ra,ra,-519 # 80002001 -80000210: 0010c703 lbu a4,1(ra) -80000214: 00070313 mv t1,a4 -80000218: 0f000e93 li t4,240 -8000021c: 13d31c63 bne t1,t4,80000354 -80000220: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000224: 00200293 li t0,2 -80000228: fe5210e3 bne tp,t0,80000208 - -8000022c : -8000022c: 00d00193 li gp,13 -80000230: 00000213 li tp,0 -80000234: 00002097 auipc ra,0x2 -80000238: dce08093 addi ra,ra,-562 # 80002002 -8000023c: 0010c703 lbu a4,1(ra) -80000240: 00000013 nop -80000244: 00070313 mv t1,a4 -80000248: 00f00e93 li t4,15 -8000024c: 11d31463 bne t1,t4,80000354 -80000250: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000254: 00200293 li t0,2 -80000258: fc521ee3 bne tp,t0,80000234 - -8000025c : -8000025c: 00e00193 li gp,14 -80000260: 00000213 li tp,0 -80000264: 00002097 auipc ra,0x2 -80000268: d9c08093 addi ra,ra,-612 # 80002000 -8000026c: 0010c703 lbu a4,1(ra) -80000270: 00000013 nop -80000274: 00000013 nop -80000278: 00070313 mv t1,a4 -8000027c: 00000e93 li t4,0 -80000280: 0dd31a63 bne t1,t4,80000354 -80000284: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000288: 00200293 li t0,2 -8000028c: fc521ce3 bne tp,t0,80000264 - -80000290 : -80000290: 00f00193 li gp,15 -80000294: 00000213 li tp,0 -80000298: 00002097 auipc ra,0x2 -8000029c: d6908093 addi ra,ra,-663 # 80002001 -800002a0: 0010c703 lbu a4,1(ra) -800002a4: 0f000e93 li t4,240 -800002a8: 0bd71663 bne a4,t4,80000354 -800002ac: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -800002b0: 00200293 li t0,2 -800002b4: fe5212e3 bne tp,t0,80000298 - -800002b8 : -800002b8: 01000193 li gp,16 -800002bc: 00000213 li tp,0 -800002c0: 00002097 auipc ra,0x2 -800002c4: d4208093 addi ra,ra,-702 # 80002002 -800002c8: 00000013 nop -800002cc: 0010c703 lbu a4,1(ra) -800002d0: 00f00e93 li t4,15 -800002d4: 09d71063 bne a4,t4,80000354 -800002d8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -800002dc: 00200293 li t0,2 -800002e0: fe5210e3 bne tp,t0,800002c0 - -800002e4 : -800002e4: 01100193 li gp,17 -800002e8: 00000213 li tp,0 -800002ec: 00002097 auipc ra,0x2 -800002f0: d1408093 addi ra,ra,-748 # 80002000 -800002f4: 00000013 nop -800002f8: 00000013 nop -800002fc: 0010c703 lbu a4,1(ra) -80000300: 00000e93 li t4,0 -80000304: 05d71863 bne a4,t4,80000354 -80000308: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -8000030c: 00200293 li t0,2 -80000310: fc521ee3 bne tp,t0,800002ec - -80000314 : -80000314: 00002297 auipc t0,0x2 -80000318: cec28293 addi t0,t0,-788 # 80002000 -8000031c: 0002c103 lbu sp,0(t0) -80000320: 00200113 li sp,2 -80000324: 00200e93 li t4,2 -80000328: 01200193 li gp,18 -8000032c: 03d11463 bne sp,t4,80000354 - -80000330 : -80000330: 00002297 auipc t0,0x2 -80000334: cd028293 addi t0,t0,-816 # 80002000 -80000338: 0002c103 lbu sp,0(t0) -8000033c: 00000013 nop -80000340: 00200113 li sp,2 -80000344: 00200e93 li t4,2 -80000348: 01300193 li gp,19 -8000034c: 01d11463 bne sp,t4,80000354 -80000350: 02301063 bne zero,gp,80000370 - -80000354 : -80000354: 0ff0000f fence -80000358: 00018063 beqz gp,80000358 -8000035c: 00119193 slli gp,gp,0x1 -80000360: 0011e193 ori gp,gp,1 -80000364: 05d00893 li a7,93 -80000368: 00018513 mv a0,gp -8000036c: 00000073 ecall - -80000370 : -80000370: 0ff0000f fence -80000374: 00100193 li gp,1 -80000378: 05d00893 li a7,93 -8000037c: 00000513 li a0,0 -80000380: 00000073 ecall -80000384: c0001073 unimp -80000388: 0000 unimp -8000038a: 0000 unimp -8000038c: 0000 unimp -8000038e: 0000 unimp -80000390: 0000 unimp -80000392: 0000 unimp -80000394: 0000 unimp -80000396: 0000 unimp -80000398: 0000 unimp -8000039a: 0000 unimp -8000039c: 0000 unimp -8000039e: 0000 unimp -800003a0: 0000 unimp -800003a2: 0000 unimp -800003a4: 0000 unimp -800003a6: 0000 unimp -800003a8: 0000 unimp -800003aa: 0000 unimp -800003ac: 0000 unimp -800003ae: 0000 unimp -800003b0: 0000 unimp -800003b2: 0000 unimp -800003b4: 0000 unimp -800003b6: 0000 unimp -800003b8: 0000 unimp -800003ba: 0000 unimp -800003bc: 0000 unimp -800003be: 0000 unimp -800003c0: 0000 unimp -800003c2: 0000 unimp - -Disassembly of section .data: - -80002000 : -80002000: 0xff - -80002001 : -80002001: fsw fs0,32(s0) - -80002002 : -80002002: addi a2,sp,988 - -80002003 : -80002003: 0000000f fence unknown,unknown -80002007: 0000 unimp -80002009: 0000 unimp -8000200b: 0000 unimp -8000200d: 0000 unimp -8000200f: 00 Address 0x000000008000200f is out of bounds. - diff --git a/benchmarks/riscv_tests/rv32ui-p-lbu.hex b/benchmarks/riscv_tests/rv32ui-p-lbu.hex deleted file mode 100644 index b7c6f987..00000000 --- a/benchmarks/riscv_tests/rv32ui-p-lbu.hex +++ /dev/null @@ -1,62 +0,0 @@ -:0200000480007A -:100000006F00C004732F2034930F8000630AFF0336 -:10001000930F90006306FF03930FB0006302FF038A -:10002000170F0080130F0FFE63040F0067000F000F -:10003000732F203463540F006F004000136E9E53E3 -:10004000171F00002320CFFD6FF09FFF732540F1A5 -:100050006310050073251030635805000F00F00F82 -:10006000130E100073000000130E00009702000032 -:10007000938282F973905230735020307350303035 -:1000800073504030970200809382C2F7638C020065 -:10009000739052109302B01A739022307323203061 -:1000A000E39E62F873500030970200009382420191 -:1000B00073901234732540F17300203097200000B4 -:1000C000938040F483C10000930EF00F130E2000C4 -:1000D000639CD123972000009380C0F283C110005D -:1000E000930E0000130E30006390D1239720000080 -:1000F000938040F183C12000930E000F130E400047 -:100100006394D121972000009380C0EF83C1300019 -:10011000930EF000130E50006398D11F972000003B -:10012000938070EE83C1D0FF930EF00F130E60002A -:10013000639CD11D972000009380F0EC83C1E0FF09 -:10014000930E0000130E70006390D11D97200000E5 -:10015000938070EB83C1F0FF930E000F130E8000AD -:100160006394D11B972000009380F0E983C10000C5 -:10017000930EF000130E90006398D11997200000A1 -:10018000938040E8938000FE83C10002930EF00F3D -:10019000130EA000639AD11797200000938080E689 -:1001A0009380A0FF83C17000930E0000130EB00077 -:1001B000639CD115130EC0001302000097200000AD -:1001C000938050E483C1100013830100930E000F4D -:1001D000631CD3131302120093022000E31052FE9B -:1001E000130ED00013020000972000009380A0E1BE -:1001F00083C110001300000013830100930EF00070 -:100200006314D3111302120093022000E31E52FC68 -:10021000130EE0001302000097200000938080DEA0 -:1002200083C11000130000001300000013830100BD -:10023000930E0000631AD30D1302120093022000E4 -:10024000E31C52FC130EF000130200009720000084 -:10025000938050DB83C11000930E000F6396D10B87 -:100260001302120093022000E31252FE130E00014B -:1002700013020000972000009380E0D813000000D4 -:1002800083C11000930EF0006390D1091302120095 -:1002900093022000E31052FE130E1001130200001F -:1002A00097200000938000D6130000001300000088 -:1002B00083C11000930E00006398D1051302120051 -:1002C00093022000E31E52FC97210000938181D30A -:1002D00003C1010013012000930E2000130E200122 -:1002E0006314D103972100009381C1D103C10100A0 -:1002F0001300000013012000930E2000130E3001A4 -:100300006314D101631CC0010F00F00F63000E00E5 -:10031000131E1E00136E1E00730000000F00F00F6E -:10032000130E100073000000731000C000000000E6 -:1003300000000000000000000000000000000000BD -:0403400000000000B9 -:1010000000000000000000000000000000000000E0 -:1010100000000000000000000000000000000000D0 -:1010200000000000000000000000000000000000C0 -:1010300000000000000000000000000000000000B0 -:081040000000000000000000A8 -:10200000FF00F00F000000000000000000000000D2 -:040000058000200057 -:00000001FF diff --git a/benchmarks/riscv_tests/rv32ui-p-lh.dump b/benchmarks/riscv_tests/rv32ui-p-lh.dump deleted file mode 100644 index 8386dbe9..00000000 --- a/benchmarks/riscv_tests/rv32ui-p-lh.dump +++ /dev/null @@ -1,320 +0,0 @@ - -rv32ui-p-lh: file format elf32-littleriscv - - -Disassembly of section .text.init: - -80000000 <_start>: -80000000: 04c0006f j 8000004c - -80000004 : -80000004: 34202f73 csrr t5,mcause -80000008: 00800f93 li t6,8 -8000000c: 03ff0a63 beq t5,t6,80000040 -80000010: 00900f93 li t6,9 -80000014: 03ff0663 beq t5,t6,80000040 -80000018: 00b00f93 li t6,11 -8000001c: 03ff0263 beq t5,t6,80000040 -80000020: 80000f17 auipc t5,0x80000 -80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> -80000028: 000f0463 beqz t5,80000030 -8000002c: 000f0067 jr t5 -80000030: 34202f73 csrr t5,mcause -80000034: 000f5463 bgez t5,8000003c -80000038: 0040006f j 8000003c - -8000003c : -8000003c: 5391e193 ori gp,gp,1337 - -80000040 : -80000040: 00001f17 auipc t5,0x1 -80000044: fc3f2023 sw gp,-64(t5) # 80001000 -80000048: ff9ff06f j 80000040 - -8000004c : -8000004c: f1402573 csrr a0,mhartid -80000050: 00051063 bnez a0,80000050 -80000054: 00000297 auipc t0,0x0 -80000058: 01028293 addi t0,t0,16 # 80000064 -8000005c: 30529073 csrw mtvec,t0 -80000060: 18005073 csrwi satp,0 -80000064: 00000297 auipc t0,0x0 -80000068: 02028293 addi t0,t0,32 # 80000084 -8000006c: 30529073 csrw mtvec,t0 -80000070: 800002b7 lui t0,0x80000 -80000074: fff28293 addi t0,t0,-1 # 7fffffff <_end+0xffffdfef> -80000078: 3b029073 csrw pmpaddr0,t0 -8000007c: 01f00293 li t0,31 -80000080: 3a029073 csrw pmpcfg0,t0 -80000084: 00000297 auipc t0,0x0 -80000088: 01828293 addi t0,t0,24 # 8000009c -8000008c: 30529073 csrw mtvec,t0 -80000090: 30205073 csrwi medeleg,0 -80000094: 30305073 csrwi mideleg,0 -80000098: 30405073 csrwi mie,0 -8000009c: 00000193 li gp,0 -800000a0: 00000297 auipc t0,0x0 -800000a4: f6428293 addi t0,t0,-156 # 80000004 -800000a8: 30529073 csrw mtvec,t0 -800000ac: 00100513 li a0,1 -800000b0: 01f51513 slli a0,a0,0x1f -800000b4: 00054c63 bltz a0,800000cc -800000b8: 0ff0000f fence -800000bc: 00100193 li gp,1 -800000c0: 05d00893 li a7,93 -800000c4: 00000513 li a0,0 -800000c8: 00000073 ecall -800000cc: 80000297 auipc t0,0x80000 -800000d0: f3428293 addi t0,t0,-204 # 0 <_start-0x80000000> -800000d4: 00028e63 beqz t0,800000f0 -800000d8: 10529073 csrw stvec,t0 -800000dc: 0000b2b7 lui t0,0xb -800000e0: 10928293 addi t0,t0,265 # b109 <_start-0x7fff4ef7> -800000e4: 30229073 csrw medeleg,t0 -800000e8: 30202373 csrr t1,medeleg -800000ec: f46298e3 bne t0,t1,8000003c -800000f0: 30005073 csrwi mstatus,0 -800000f4: 00000297 auipc t0,0x0 -800000f8: 01428293 addi t0,t0,20 # 80000108 -800000fc: 34129073 csrw mepc,t0 -80000100: f1402573 csrr a0,mhartid -80000104: 30200073 mret - -80000108 : -80000108: 00002097 auipc ra,0x2 -8000010c: ef808093 addi ra,ra,-264 # 80002000 -80000110: 00009703 lh a4,0(ra) -80000114: 0ff00e93 li t4,255 -80000118: 00200193 li gp,2 -8000011c: 25d71c63 bne a4,t4,80000374 - -80000120 : -80000120: 00002097 auipc ra,0x2 -80000124: ee008093 addi ra,ra,-288 # 80002000 -80000128: 00209703 lh a4,2(ra) -8000012c: f0000e93 li t4,-256 -80000130: 00300193 li gp,3 -80000134: 25d71063 bne a4,t4,80000374 - -80000138 : -80000138: 00002097 auipc ra,0x2 -8000013c: ec808093 addi ra,ra,-312 # 80002000 -80000140: 00409703 lh a4,4(ra) -80000144: 00001eb7 lui t4,0x1 -80000148: ff0e8e93 addi t4,t4,-16 # ff0 <_start-0x7ffff010> -8000014c: 00400193 li gp,4 -80000150: 23d71263 bne a4,t4,80000374 - -80000154 : -80000154: 00002097 auipc ra,0x2 -80000158: eac08093 addi ra,ra,-340 # 80002000 -8000015c: 00609703 lh a4,6(ra) -80000160: fffffeb7 lui t4,0xfffff -80000164: 00fe8e93 addi t4,t4,15 # fffff00f <_end+0x7fffcfff> -80000168: 00500193 li gp,5 -8000016c: 21d71463 bne a4,t4,80000374 - -80000170 : -80000170: 00002097 auipc ra,0x2 -80000174: e9608093 addi ra,ra,-362 # 80002006 -80000178: ffa09703 lh a4,-6(ra) -8000017c: 0ff00e93 li t4,255 -80000180: 00600193 li gp,6 -80000184: 1fd71863 bne a4,t4,80000374 - -80000188 : -80000188: 00002097 auipc ra,0x2 -8000018c: e7e08093 addi ra,ra,-386 # 80002006 -80000190: ffc09703 lh a4,-4(ra) -80000194: f0000e93 li t4,-256 -80000198: 00700193 li gp,7 -8000019c: 1dd71c63 bne a4,t4,80000374 - -800001a0 : -800001a0: 00002097 auipc ra,0x2 -800001a4: e6608093 addi ra,ra,-410 # 80002006 -800001a8: ffe09703 lh a4,-2(ra) -800001ac: 00001eb7 lui t4,0x1 -800001b0: ff0e8e93 addi t4,t4,-16 # ff0 <_start-0x7ffff010> -800001b4: 00800193 li gp,8 -800001b8: 1bd71e63 bne a4,t4,80000374 - -800001bc : -800001bc: 00002097 auipc ra,0x2 -800001c0: e4a08093 addi ra,ra,-438 # 80002006 -800001c4: 00009703 lh a4,0(ra) -800001c8: fffffeb7 lui t4,0xfffff -800001cc: 00fe8e93 addi t4,t4,15 # fffff00f <_end+0x7fffcfff> -800001d0: 00900193 li gp,9 -800001d4: 1bd71063 bne a4,t4,80000374 - -800001d8 : -800001d8: 00002097 auipc ra,0x2 -800001dc: e2808093 addi ra,ra,-472 # 80002000 -800001e0: fe008093 addi ra,ra,-32 -800001e4: 02009283 lh t0,32(ra) -800001e8: 0ff00e93 li t4,255 -800001ec: 00a00193 li gp,10 -800001f0: 19d29263 bne t0,t4,80000374 - -800001f4 : -800001f4: 00002097 auipc ra,0x2 -800001f8: e0c08093 addi ra,ra,-500 # 80002000 -800001fc: ffb08093 addi ra,ra,-5 -80000200: 00709283 lh t0,7(ra) -80000204: f0000e93 li t4,-256 -80000208: 00b00193 li gp,11 -8000020c: 17d29463 bne t0,t4,80000374 - -80000210 : -80000210: 00c00193 li gp,12 -80000214: 00000213 li tp,0 -80000218: 00002097 auipc ra,0x2 -8000021c: dea08093 addi ra,ra,-534 # 80002002 -80000220: 00209703 lh a4,2(ra) -80000224: 00070313 mv t1,a4 -80000228: 00001eb7 lui t4,0x1 -8000022c: ff0e8e93 addi t4,t4,-16 # ff0 <_start-0x7ffff010> -80000230: 15d31263 bne t1,t4,80000374 -80000234: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000238: 00200293 li t0,2 -8000023c: fc521ee3 bne tp,t0,80000218 - -80000240 : -80000240: 00d00193 li gp,13 -80000244: 00000213 li tp,0 -80000248: 00002097 auipc ra,0x2 -8000024c: dbc08093 addi ra,ra,-580 # 80002004 -80000250: 00209703 lh a4,2(ra) -80000254: 00000013 nop -80000258: 00070313 mv t1,a4 -8000025c: fffffeb7 lui t4,0xfffff -80000260: 00fe8e93 addi t4,t4,15 # fffff00f <_end+0x7fffcfff> -80000264: 11d31863 bne t1,t4,80000374 -80000268: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -8000026c: 00200293 li t0,2 -80000270: fc521ce3 bne tp,t0,80000248 - -80000274 : -80000274: 00e00193 li gp,14 -80000278: 00000213 li tp,0 -8000027c: 00002097 auipc ra,0x2 -80000280: d8408093 addi ra,ra,-636 # 80002000 -80000284: 00209703 lh a4,2(ra) -80000288: 00000013 nop -8000028c: 00000013 nop -80000290: 00070313 mv t1,a4 -80000294: f0000e93 li t4,-256 -80000298: 0dd31e63 bne t1,t4,80000374 -8000029c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -800002a0: 00200293 li t0,2 -800002a4: fc521ce3 bne tp,t0,8000027c - -800002a8 : -800002a8: 00f00193 li gp,15 -800002ac: 00000213 li tp,0 -800002b0: 00002097 auipc ra,0x2 -800002b4: d5208093 addi ra,ra,-686 # 80002002 -800002b8: 00209703 lh a4,2(ra) -800002bc: 00001eb7 lui t4,0x1 -800002c0: ff0e8e93 addi t4,t4,-16 # ff0 <_start-0x7ffff010> -800002c4: 0bd71863 bne a4,t4,80000374 -800002c8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -800002cc: 00200293 li t0,2 -800002d0: fe5210e3 bne tp,t0,800002b0 - -800002d4 : -800002d4: 01000193 li gp,16 -800002d8: 00000213 li tp,0 -800002dc: 00002097 auipc ra,0x2 -800002e0: d2808093 addi ra,ra,-728 # 80002004 -800002e4: 00000013 nop -800002e8: 00209703 lh a4,2(ra) -800002ec: fffffeb7 lui t4,0xfffff -800002f0: 00fe8e93 addi t4,t4,15 # fffff00f <_end+0x7fffcfff> -800002f4: 09d71063 bne a4,t4,80000374 -800002f8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -800002fc: 00200293 li t0,2 -80000300: fc521ee3 bne tp,t0,800002dc - -80000304 : -80000304: 01100193 li gp,17 -80000308: 00000213 li tp,0 -8000030c: 00002097 auipc ra,0x2 -80000310: cf408093 addi ra,ra,-780 # 80002000 -80000314: 00000013 nop -80000318: 00000013 nop -8000031c: 00209703 lh a4,2(ra) -80000320: f0000e93 li t4,-256 -80000324: 05d71863 bne a4,t4,80000374 -80000328: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -8000032c: 00200293 li t0,2 -80000330: fc521ee3 bne tp,t0,8000030c - -80000334 : -80000334: 00002297 auipc t0,0x2 -80000338: ccc28293 addi t0,t0,-820 # 80002000 -8000033c: 00029103 lh sp,0(t0) -80000340: 00200113 li sp,2 -80000344: 00200e93 li t4,2 -80000348: 01200193 li gp,18 -8000034c: 03d11463 bne sp,t4,80000374 - -80000350 : -80000350: 00002297 auipc t0,0x2 -80000354: cb028293 addi t0,t0,-848 # 80002000 -80000358: 00029103 lh sp,0(t0) -8000035c: 00000013 nop -80000360: 00200113 li sp,2 -80000364: 00200e93 li t4,2 -80000368: 01300193 li gp,19 -8000036c: 01d11463 bne sp,t4,80000374 -80000370: 02301063 bne zero,gp,80000390 - -80000374 : -80000374: 0ff0000f fence -80000378: 00018063 beqz gp,80000378 -8000037c: 00119193 slli gp,gp,0x1 -80000380: 0011e193 ori gp,gp,1 -80000384: 05d00893 li a7,93 -80000388: 00018513 mv a0,gp -8000038c: 00000073 ecall - -80000390 : -80000390: 0ff0000f fence -80000394: 00100193 li gp,1 -80000398: 05d00893 li a7,93 -8000039c: 00000513 li a0,0 -800003a0: 00000073 ecall -800003a4: c0001073 unimp -800003a8: 0000 unimp -800003aa: 0000 unimp -800003ac: 0000 unimp -800003ae: 0000 unimp -800003b0: 0000 unimp -800003b2: 0000 unimp -800003b4: 0000 unimp -800003b6: 0000 unimp -800003b8: 0000 unimp -800003ba: 0000 unimp -800003bc: 0000 unimp -800003be: 0000 unimp -800003c0: 0000 unimp -800003c2: 0000 unimp - -Disassembly of section .data: - -80002000 : -80002000: 00ff 0xff - -80002002 : -80002002: ff00 fsw fs0,56(a4) - -80002004 : -80002004: 0ff0 addi a2,sp,988 - -80002006 : -80002006: 0000f00f 0xf00f -8000200a: 0000 unimp -8000200c: 0000 unimp -8000200e: 0000 unimp diff --git a/benchmarks/riscv_tests/rv32ui-p-lh.hex b/benchmarks/riscv_tests/rv32ui-p-lh.hex deleted file mode 100644 index fe96f9c1..00000000 --- a/benchmarks/riscv_tests/rv32ui-p-lh.hex +++ /dev/null @@ -1,66 +0,0 @@ -:0200000480007A -:100000006F00C004732F2034930F8000630AFF0336 -:10001000930F90006306FF03930FB0006302FF038A -:10002000170F0080130F0FFE63040F0067000F000F -:10003000732F203463540F006F004000136E9E53E3 -:10004000171F00002320CFFD6FF09FFF732540F1A5 -:100050006310050073251030635805000F00F00F82 -:10006000130E100073000000130E00009702000032 -:10007000938282F973905230735020307350303035 -:1000800073504030970200809382C2F7638C020065 -:10009000739052109302B01A739022307323203061 -:1000A000E39E62F873500030970200009382420191 -:1000B00073901234732540F17300203097200000B4 -:1000C000938040F483910000930EF00F130E2000F4 -:1000D000639CD125972000009380C0F2839120007B -:1000E000930E00F0130E30006390D125972000008E -:1000F000938040F183914000B71E0000938E0EFF65 -:10010000130E40006392D12397200000938080EF6C -:1001100083916000B7FEFFFF938EFE00130E500028 -:100120006394D12197200000938020EE8391A0FF5B -:10013000930EF00F130E60006398D11F97200000FC -:100140009380A0EC8391C0FF930E00F0130E70001B -:10015000639CD11D97200000938020EB8391E0FFEA -:10016000B71E0000938E0EFF130E8000639ED11BFE -:1001700097200000938060E983910000B7FEFFFFA5 -:10018000938EFE00130E90006390D11B9720000009 -:10019000938040E7938000FE83910002930EF00F5E -:1001A000130EA0006392D11997200000938080E580 -:1001B0009380B0FF83917000930E00F0130EB00097 -:1001C0006394D117130EC0001302000097200000A3 -:1001D000938060E38391200013830100B71E000029 -:1001E000938E0EFF6312D3151302120093022000A8 -:1001F000E31E52FC130ED0001302000097200000F3 -:10020000938080E08391200013000000138301009D -:10021000B7FEFFFF938EFE006318D3111302120086 -:1002200093022000E31C52FC130EE00013020000B6 -:1002300097200000938000DD8391200013000000D0 -:100240001300000013830100930E00F0631ED30D12 -:100250001302120093022000E31C52FC130EF00064 -:1002600013020000972000009380E0D983912000C2 -:10027000B71E0000938E0EFF6398D10B130212007D -:1002800093022000E31052FE130E0001130200003F -:1002900097200000938040D7130000008391200036 -:1002A000B7FEFFFF938EFE006390D1091302120088 -:1002B00093022000E31E52FC130E100113020000F3 -:1002C00097200000938000D413000000130000006A -:1002D00083912000930E00F06398D1051302120061 -:1002E00093022000E31E52FC97210000938181D1EC -:1002F0000391010013012000930E2000130E200132 -:100300006314D103972100009381C1CF03910100B1 -:100310001300000013012000930E2000130E300183 -:100320006314D101631CC0010F00F00F63000E00C5 -:10033000131E1E00136E1E00730000000F00F00F4E -:10034000130E100073000000731000C000000000C6 -:10035000000000000000000000000000000000009D -:10036000000000000000000000000000000000008D -:10037000000000000000000000000000000000007D -:040380000000000079 -:1010000000000000000000000000000000000000E0 -:1010100000000000000000000000000000000000D0 -:1010200000000000000000000000000000000000C0 -:1010300000000000000000000000000000000000B0 -:081040000000000000000000A8 -:10200000FF0000FFF00F0FF00000000000000000D4 -:040000058000200057 -:00000001FF diff --git a/benchmarks/riscv_tests/rv32ui-p-lhu.dump b/benchmarks/riscv_tests/rv32ui-p-lhu.dump deleted file mode 100644 index 68b4f089..00000000 --- a/benchmarks/riscv_tests/rv32ui-p-lhu.dump +++ /dev/null @@ -1,315 +0,0 @@ - -rv32ui-p-lhu: file format elf32-littleriscv - - -Disassembly of section .text.init: - -80000000 <_start>: -80000000: 04c0006f j 8000004c - -80000004 : -80000004: 34202f73 csrr t5,mcause -80000008: 00800f93 li t6,8 -8000000c: 03ff0a63 beq t5,t6,80000040 -80000010: 00900f93 li t6,9 -80000014: 03ff0663 beq t5,t6,80000040 -80000018: 00b00f93 li t6,11 -8000001c: 03ff0263 beq t5,t6,80000040 -80000020: 80000f17 auipc t5,0x80000 -80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> -80000028: 000f0463 beqz t5,80000030 -8000002c: 000f0067 jr t5 -80000030: 34202f73 csrr t5,mcause -80000034: 000f5463 bgez t5,8000003c -80000038: 0040006f j 8000003c - -8000003c : -8000003c: 5391e193 ori gp,gp,1337 - -80000040 : -80000040: 00001f17 auipc t5,0x1 -80000044: fc3f2023 sw gp,-64(t5) # 80001000 -80000048: ff9ff06f j 80000040 - -8000004c : -8000004c: f1402573 csrr a0,mhartid -80000050: 00051063 bnez a0,80000050 -80000054: 00000297 auipc t0,0x0 -80000058: 01028293 addi t0,t0,16 # 80000064 -8000005c: 30529073 csrw mtvec,t0 -80000060: 18005073 csrwi satp,0 -80000064: 00000297 auipc t0,0x0 -80000068: 02028293 addi t0,t0,32 # 80000084 -8000006c: 30529073 csrw mtvec,t0 -80000070: 800002b7 lui t0,0x80000 -80000074: fff28293 addi t0,t0,-1 # 7fffffff <_end+0xffffdfef> -80000078: 3b029073 csrw pmpaddr0,t0 -8000007c: 01f00293 li t0,31 -80000080: 3a029073 csrw pmpcfg0,t0 -80000084: 00000297 auipc t0,0x0 -80000088: 01828293 addi t0,t0,24 # 8000009c -8000008c: 30529073 csrw mtvec,t0 -80000090: 30205073 csrwi medeleg,0 -80000094: 30305073 csrwi mideleg,0 -80000098: 30405073 csrwi mie,0 -8000009c: 00000193 li gp,0 -800000a0: 00000297 auipc t0,0x0 -800000a4: f6428293 addi t0,t0,-156 # 80000004 -800000a8: 30529073 csrw mtvec,t0 -800000ac: 00100513 li a0,1 -800000b0: 01f51513 slli a0,a0,0x1f -800000b4: 00054c63 bltz a0,800000cc -800000b8: 0ff0000f fence -800000bc: 00100193 li gp,1 -800000c0: 05d00893 li a7,93 -800000c4: 00000513 li a0,0 -800000c8: 00000073 ecall -800000cc: 80000297 auipc t0,0x80000 -800000d0: f3428293 addi t0,t0,-204 # 0 <_start-0x80000000> -800000d4: 00028e63 beqz t0,800000f0 -800000d8: 10529073 csrw stvec,t0 -800000dc: 0000b2b7 lui t0,0xb -800000e0: 10928293 addi t0,t0,265 # b109 <_start-0x7fff4ef7> -800000e4: 30229073 csrw medeleg,t0 -800000e8: 30202373 csrr t1,medeleg -800000ec: f46298e3 bne t0,t1,8000003c -800000f0: 30005073 csrwi mstatus,0 -800000f4: 00000297 auipc t0,0x0 -800000f8: 01428293 addi t0,t0,20 # 80000108 -800000fc: 34129073 csrw mepc,t0 -80000100: f1402573 csrr a0,mhartid -80000104: 30200073 mret - -80000108 : -80000108: 00002097 auipc ra,0x2 -8000010c: ef808093 addi ra,ra,-264 # 80002000 -80000110: 0000d703 lhu a4,0(ra) -80000114: 0ff00e93 li t4,255 -80000118: 00200193 li gp,2 -8000011c: 27d71663 bne a4,t4,80000388 - -80000120 : -80000120: 00002097 auipc ra,0x2 -80000124: ee008093 addi ra,ra,-288 # 80002000 -80000128: 0020d703 lhu a4,2(ra) -8000012c: 00010eb7 lui t4,0x10 -80000130: f00e8e93 addi t4,t4,-256 # ff00 <_start-0x7fff0100> -80000134: 00300193 li gp,3 -80000138: 25d71863 bne a4,t4,80000388 - -8000013c : -8000013c: 00002097 auipc ra,0x2 -80000140: ec408093 addi ra,ra,-316 # 80002000 -80000144: 0040d703 lhu a4,4(ra) -80000148: 00001eb7 lui t4,0x1 -8000014c: ff0e8e93 addi t4,t4,-16 # ff0 <_start-0x7ffff010> -80000150: 00400193 li gp,4 -80000154: 23d71a63 bne a4,t4,80000388 - -80000158 : -80000158: 00002097 auipc ra,0x2 -8000015c: ea808093 addi ra,ra,-344 # 80002000 -80000160: 0060d703 lhu a4,6(ra) -80000164: 0000feb7 lui t4,0xf -80000168: 00fe8e93 addi t4,t4,15 # f00f <_start-0x7fff0ff1> -8000016c: 00500193 li gp,5 -80000170: 21d71c63 bne a4,t4,80000388 - -80000174 : -80000174: 00002097 auipc ra,0x2 -80000178: e9208093 addi ra,ra,-366 # 80002006 -8000017c: ffa0d703 lhu a4,-6(ra) -80000180: 0ff00e93 li t4,255 -80000184: 00600193 li gp,6 -80000188: 21d71063 bne a4,t4,80000388 - -8000018c : -8000018c: 00002097 auipc ra,0x2 -80000190: e7a08093 addi ra,ra,-390 # 80002006 -80000194: ffc0d703 lhu a4,-4(ra) -80000198: 00010eb7 lui t4,0x10 -8000019c: f00e8e93 addi t4,t4,-256 # ff00 <_start-0x7fff0100> -800001a0: 00700193 li gp,7 -800001a4: 1fd71263 bne a4,t4,80000388 - -800001a8 : -800001a8: 00002097 auipc ra,0x2 -800001ac: e5e08093 addi ra,ra,-418 # 80002006 -800001b0: ffe0d703 lhu a4,-2(ra) -800001b4: 00001eb7 lui t4,0x1 -800001b8: ff0e8e93 addi t4,t4,-16 # ff0 <_start-0x7ffff010> -800001bc: 00800193 li gp,8 -800001c0: 1dd71463 bne a4,t4,80000388 - -800001c4 : -800001c4: 00002097 auipc ra,0x2 -800001c8: e4208093 addi ra,ra,-446 # 80002006 -800001cc: 0000d703 lhu a4,0(ra) -800001d0: 0000feb7 lui t4,0xf -800001d4: 00fe8e93 addi t4,t4,15 # f00f <_start-0x7fff0ff1> -800001d8: 00900193 li gp,9 -800001dc: 1bd71663 bne a4,t4,80000388 - -800001e0 : -800001e0: 00002097 auipc ra,0x2 -800001e4: e2008093 addi ra,ra,-480 # 80002000 -800001e8: fe008093 addi ra,ra,-32 -800001ec: 0200d283 lhu t0,32(ra) -800001f0: 0ff00e93 li t4,255 -800001f4: 00a00193 li gp,10 -800001f8: 19d29863 bne t0,t4,80000388 - -800001fc : -800001fc: 00002097 auipc ra,0x2 -80000200: e0408093 addi ra,ra,-508 # 80002000 -80000204: ffb08093 addi ra,ra,-5 -80000208: 0070d283 lhu t0,7(ra) -8000020c: 00010eb7 lui t4,0x10 -80000210: f00e8e93 addi t4,t4,-256 # ff00 <_start-0x7fff0100> -80000214: 00b00193 li gp,11 -80000218: 17d29863 bne t0,t4,80000388 - -8000021c : -8000021c: 00c00193 li gp,12 -80000220: 00000213 li tp,0 -80000224: 00002097 auipc ra,0x2 -80000228: dde08093 addi ra,ra,-546 # 80002002 -8000022c: 0020d703 lhu a4,2(ra) -80000230: 00070313 mv t1,a4 -80000234: 00001eb7 lui t4,0x1 -80000238: ff0e8e93 addi t4,t4,-16 # ff0 <_start-0x7ffff010> -8000023c: 15d31663 bne t1,t4,80000388 -80000240: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000244: 00200293 li t0,2 -80000248: fc521ee3 bne tp,t0,80000224 - -8000024c : -8000024c: 00d00193 li gp,13 -80000250: 00000213 li tp,0 -80000254: 00002097 auipc ra,0x2 -80000258: db008093 addi ra,ra,-592 # 80002004 -8000025c: 0020d703 lhu a4,2(ra) -80000260: 00000013 nop -80000264: 00070313 mv t1,a4 -80000268: 0000feb7 lui t4,0xf -8000026c: 00fe8e93 addi t4,t4,15 # f00f <_start-0x7fff0ff1> -80000270: 11d31c63 bne t1,t4,80000388 -80000274: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000278: 00200293 li t0,2 -8000027c: fc521ce3 bne tp,t0,80000254 - -80000280 : -80000280: 00e00193 li gp,14 -80000284: 00000213 li tp,0 -80000288: 00002097 auipc ra,0x2 -8000028c: d7808093 addi ra,ra,-648 # 80002000 -80000290: 0020d703 lhu a4,2(ra) -80000294: 00000013 nop -80000298: 00000013 nop -8000029c: 00070313 mv t1,a4 -800002a0: 00010eb7 lui t4,0x10 -800002a4: f00e8e93 addi t4,t4,-256 # ff00 <_start-0x7fff0100> -800002a8: 0fd31063 bne t1,t4,80000388 -800002ac: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -800002b0: 00200293 li t0,2 -800002b4: fc521ae3 bne tp,t0,80000288 - -800002b8 : -800002b8: 00f00193 li gp,15 -800002bc: 00000213 li tp,0 -800002c0: 00002097 auipc ra,0x2 -800002c4: d4208093 addi ra,ra,-702 # 80002002 -800002c8: 0020d703 lhu a4,2(ra) -800002cc: 00001eb7 lui t4,0x1 -800002d0: ff0e8e93 addi t4,t4,-16 # ff0 <_start-0x7ffff010> -800002d4: 0bd71a63 bne a4,t4,80000388 -800002d8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -800002dc: 00200293 li t0,2 -800002e0: fe5210e3 bne tp,t0,800002c0 - -800002e4 : -800002e4: 01000193 li gp,16 -800002e8: 00000213 li tp,0 -800002ec: 00002097 auipc ra,0x2 -800002f0: d1808093 addi ra,ra,-744 # 80002004 -800002f4: 00000013 nop -800002f8: 0020d703 lhu a4,2(ra) -800002fc: 0000feb7 lui t4,0xf -80000300: 00fe8e93 addi t4,t4,15 # f00f <_start-0x7fff0ff1> -80000304: 09d71263 bne a4,t4,80000388 -80000308: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -8000030c: 00200293 li t0,2 -80000310: fc521ee3 bne tp,t0,800002ec - -80000314 : -80000314: 01100193 li gp,17 -80000318: 00000213 li tp,0 -8000031c: 00002097 auipc ra,0x2 -80000320: ce408093 addi ra,ra,-796 # 80002000 -80000324: 00000013 nop -80000328: 00000013 nop -8000032c: 0020d703 lhu a4,2(ra) -80000330: 00010eb7 lui t4,0x10 -80000334: f00e8e93 addi t4,t4,-256 # ff00 <_start-0x7fff0100> -80000338: 05d71863 bne a4,t4,80000388 -8000033c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000340: 00200293 li t0,2 -80000344: fc521ce3 bne tp,t0,8000031c - -80000348 : -80000348: 00002297 auipc t0,0x2 -8000034c: cb828293 addi t0,t0,-840 # 80002000 -80000350: 0002d103 lhu sp,0(t0) -80000354: 00200113 li sp,2 -80000358: 00200e93 li t4,2 -8000035c: 01200193 li gp,18 -80000360: 03d11463 bne sp,t4,80000388 - -80000364 : -80000364: 00002297 auipc t0,0x2 -80000368: c9c28293 addi t0,t0,-868 # 80002000 -8000036c: 0002d103 lhu sp,0(t0) -80000370: 00000013 nop -80000374: 00200113 li sp,2 -80000378: 00200e93 li t4,2 -8000037c: 01300193 li gp,19 -80000380: 01d11463 bne sp,t4,80000388 -80000384: 02301063 bne zero,gp,800003a4 - -80000388 : -80000388: 0ff0000f fence -8000038c: 00018063 beqz gp,8000038c -80000390: 00119193 slli gp,gp,0x1 -80000394: 0011e193 ori gp,gp,1 -80000398: 05d00893 li a7,93 -8000039c: 00018513 mv a0,gp -800003a0: 00000073 ecall - -800003a4 : -800003a4: 0ff0000f fence -800003a8: 00100193 li gp,1 -800003ac: 05d00893 li a7,93 -800003b0: 00000513 li a0,0 -800003b4: 00000073 ecall -800003b8: c0001073 unimp -800003bc: 0000 unimp -800003be: 0000 unimp -800003c0: 0000 unimp -800003c2: 0000 unimp - -Disassembly of section .data: - -80002000 : -80002000: 00ff 0xff - -80002002 : -80002002: ff00 fsw fs0,56(a4) - -80002004 : -80002004: 0ff0 addi a2,sp,988 - -80002006 : -80002006: 0000f00f 0xf00f -8000200a: 0000 unimp -8000200c: 0000 unimp -8000200e: 0000 unimp diff --git a/benchmarks/riscv_tests/rv32ui-p-lhu.hex b/benchmarks/riscv_tests/rv32ui-p-lhu.hex deleted file mode 100644 index c191ecb9..00000000 --- a/benchmarks/riscv_tests/rv32ui-p-lhu.hex +++ /dev/null @@ -1,66 +0,0 @@ -:0200000480007A -:100000006F00C004732F2034930F8000630AFF0336 -:10001000930F90006306FF03930FB0006302FF038A -:10002000170F0080130F0FFE63040F0067000F000F -:10003000732F203463540F006F004000136E9E53E3 -:10004000171F00002320CFFD6FF09FFF732540F1A5 -:100050006310050073251030635805000F00F00F82 -:10006000130E100073000000130E00009702000032 -:10007000938282F973905230735020307350303035 -:1000800073504030970200809382C2F7638C020065 -:10009000739052109302B01A739022307323203061 -:1000A000E39E62F873500030970200009382420191 -:1000B00073901234732540F17300203097200000B4 -:1000C000938040F483D10000930EF00F130E2000B4 -:1000D0006396D127972000009380C0F283D120003F -:1000E000B70E0100938E0EF0130E30006398D125E9 -:1000F00097200000938000F183D14000B71E0000DC -:10010000938E0EFF130E4000639AD12397200000B8 -:10011000938040EF83D16000B7FE0000938EFE0015 -:10012000130E5000639CD121972000009380E0EDD6 -:1001300083D1A0FF930EF00F130E60006390D121C6 -:1001400097200000938060EC83D1C0FFB70E0100C0 -:10015000938E0EF0130E70006392D11F9720000053 -:100160009380A0EA83D1E0FFB71E0000938E0EFFBC -:10017000130E80006394D11D972000009380E0E867 -:1001800083D10000B7FE0000938EFE00130E900096 -:100190006396D11B972000009380C0E6938000FEF9 -:1001A00083D10002930EF00F130EA0006398D119B3 -:1001B00097200000938000E59380B0FF83D170000A -:1001C000B70E0100938E0EF0130EB0006398D11796 -:1001D000130EC00013020000972000009380A0E2DD -:1001E00083D1200013830100B71E0000938E0EFF01 -:1001F0006316D3151302120093022000E31E52FC73 -:10020000130ED00013020000972000009380C0DF7F -:1002100083D120001300000013830100B7FE00000B -:10022000938EFE00631CD311130212009302200070 -:10023000E31C52FC130EE0001302000097200000A4 -:10024000938040DC83D120001300000013000000E5 -:1002500013830100B70E0100938E0EF06310D30FCD -:100260001302120093022000E31A52FC130EF00056 -:1002700013020000972000009380E0D883D1200073 -:10028000B71E0000938E0EFF639AD10B130212006B -:1002900093022000E31052FE130E0001130200002F -:1002A00097200000938040D61300000083D12000E7 -:1002B000B7FE0000938EFE006392D1091302120074 -:1002C00093022000E31E52FC130E100113020000E3 -:1002D00097200000938000D313000000130000005B -:1002E00083D12000B70E0100938E0EF06398D105E4 -:1002F0001302120093022000E31C52FC972100001D -:10030000938141D003D1010013012000930E2000FE -:10031000130E20016314D10397210000938181CE35 -:1003200003D101001300000013012000930E2000F0 -:10033000130E30016314D101631CC0010F00F00FD4 -:1003400063000E00131E1E00136E1E0073000000DB -:100350000F00F00F130E100073000000731000C0A8 -:10036000000000000000000000000000000000008D -:10037000000000000000000000000000000000007D -:040380000000000079 -:1010000000000000000000000000000000000000E0 -:1010100000000000000000000000000000000000D0 -:1010200000000000000000000000000000000000C0 -:1010300000000000000000000000000000000000B0 -:081040000000000000000000A8 -:10200000FF0000FFF00F0FF00000000000000000D4 -:040000058000200057 -:00000001FF diff --git a/benchmarks/riscv_tests/rv32ui-p-lui.dump b/benchmarks/riscv_tests/rv32ui-p-lui.dump deleted file mode 100644 index 6768863a..00000000 --- a/benchmarks/riscv_tests/rv32ui-p-lui.dump +++ /dev/null @@ -1,152 +0,0 @@ - -rv32ui-p-lui: file format elf32-littleriscv - - -Disassembly of section .text.init: - -80000000 <_start>: -80000000: 04c0006f j 8000004c - -80000004 : -80000004: 34202f73 csrr t5,mcause -80000008: 00800f93 li t6,8 -8000000c: 03ff0a63 beq t5,t6,80000040 -80000010: 00900f93 li t6,9 -80000014: 03ff0663 beq t5,t6,80000040 -80000018: 00b00f93 li t6,11 -8000001c: 03ff0263 beq t5,t6,80000040 -80000020: 80000f17 auipc t5,0x80000 -80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> -80000028: 000f0463 beqz t5,80000030 -8000002c: 000f0067 jr t5 -80000030: 34202f73 csrr t5,mcause -80000034: 000f5463 bgez t5,8000003c -80000038: 0040006f j 8000003c - -8000003c : -8000003c: 5391e193 ori gp,gp,1337 - -80000040 : -80000040: 00001f17 auipc t5,0x1 -80000044: fc3f2023 sw gp,-64(t5) # 80001000 -80000048: ff9ff06f j 80000040 - -8000004c : -8000004c: f1402573 csrr a0,mhartid -80000050: 00051063 bnez a0,80000050 -80000054: 00000297 auipc t0,0x0 -80000058: 01028293 addi t0,t0,16 # 80000064 -8000005c: 30529073 csrw mtvec,t0 -80000060: 18005073 csrwi satp,0 -80000064: 00000297 auipc t0,0x0 -80000068: 02028293 addi t0,t0,32 # 80000084 -8000006c: 30529073 csrw mtvec,t0 -80000070: 800002b7 lui t0,0x80000 -80000074: fff28293 addi t0,t0,-1 # 7fffffff <_end+0xffffdfff> -80000078: 3b029073 csrw pmpaddr0,t0 -8000007c: 01f00293 li t0,31 -80000080: 3a029073 csrw pmpcfg0,t0 -80000084: 00000297 auipc t0,0x0 -80000088: 01828293 addi t0,t0,24 # 8000009c -8000008c: 30529073 csrw mtvec,t0 -80000090: 30205073 csrwi medeleg,0 -80000094: 30305073 csrwi mideleg,0 -80000098: 30405073 csrwi mie,0 -8000009c: 00000193 li gp,0 -800000a0: 00000297 auipc t0,0x0 -800000a4: f6428293 addi t0,t0,-156 # 80000004 -800000a8: 30529073 csrw mtvec,t0 -800000ac: 00100513 li a0,1 -800000b0: 01f51513 slli a0,a0,0x1f -800000b4: 00054c63 bltz a0,800000cc -800000b8: 0ff0000f fence -800000bc: 00100193 li gp,1 -800000c0: 05d00893 li a7,93 -800000c4: 00000513 li a0,0 -800000c8: 00000073 ecall -800000cc: 80000297 auipc t0,0x80000 -800000d0: f3428293 addi t0,t0,-204 # 0 <_start-0x80000000> -800000d4: 00028e63 beqz t0,800000f0 -800000d8: 10529073 csrw stvec,t0 -800000dc: 0000b2b7 lui t0,0xb -800000e0: 10928293 addi t0,t0,265 # b109 <_start-0x7fff4ef7> -800000e4: 30229073 csrw medeleg,t0 -800000e8: 30202373 csrr t1,medeleg -800000ec: f46298e3 bne t0,t1,8000003c -800000f0: 30005073 csrwi mstatus,0 -800000f4: 00000297 auipc t0,0x0 -800000f8: 01428293 addi t0,t0,20 # 80000108 -800000fc: 34129073 csrw mepc,t0 -80000100: f1402573 csrr a0,mhartid -80000104: 30200073 mret - -80000108 : -80000108: 000000b7 lui ra,0x0 -8000010c: 00000e93 li t4,0 -80000110: 00200193 li gp,2 -80000114: 05d09a63 bne ra,t4,80000168 - -80000118 : -80000118: fffff0b7 lui ra,0xfffff -8000011c: 4010d093 srai ra,ra,0x1 -80000120: 80000e93 li t4,-2048 -80000124: 00300193 li gp,3 -80000128: 05d09063 bne ra,t4,80000168 - -8000012c : -8000012c: 7ffff0b7 lui ra,0x7ffff -80000130: 4140d093 srai ra,ra,0x14 -80000134: 7ff00e93 li t4,2047 -80000138: 00400193 li gp,4 -8000013c: 03d09663 bne ra,t4,80000168 - -80000140 : -80000140: 800000b7 lui ra,0x80000 -80000144: 4140d093 srai ra,ra,0x14 -80000148: 80000e93 li t4,-2048 -8000014c: 00500193 li gp,5 -80000150: 01d09c63 bne ra,t4,80000168 - -80000154 : -80000154: 80000037 lui zero,0x80000 -80000158: 00000e93 li t4,0 -8000015c: 00600193 li gp,6 -80000160: 01d01463 bne zero,t4,80000168 -80000164: 02301063 bne zero,gp,80000184 - -80000168 : -80000168: 0ff0000f fence -8000016c: 00018063 beqz gp,8000016c -80000170: 00119193 slli gp,gp,0x1 -80000174: 0011e193 ori gp,gp,1 -80000178: 05d00893 li a7,93 -8000017c: 00018513 mv a0,gp -80000180: 00000073 ecall - -80000184 : -80000184: 0ff0000f fence -80000188: 00100193 li gp,1 -8000018c: 05d00893 li a7,93 -80000190: 00000513 li a0,0 -80000194: 00000073 ecall -80000198: c0001073 unimp -8000019c: 0000 unimp -8000019e: 0000 unimp -800001a0: 0000 unimp -800001a2: 0000 unimp -800001a4: 0000 unimp -800001a6: 0000 unimp -800001a8: 0000 unimp -800001aa: 0000 unimp -800001ac: 0000 unimp -800001ae: 0000 unimp -800001b0: 0000 unimp -800001b2: 0000 unimp -800001b4: 0000 unimp -800001b6: 0000 unimp -800001b8: 0000 unimp -800001ba: 0000 unimp -800001bc: 0000 unimp -800001be: 0000 unimp -800001c0: 0000 unimp -800001c2: 0000 unimp diff --git a/benchmarks/riscv_tests/rv32ui-p-lui.hex b/benchmarks/riscv_tests/rv32ui-p-lui.hex deleted file mode 100644 index f362421a..00000000 --- a/benchmarks/riscv_tests/rv32ui-p-lui.hex +++ /dev/null @@ -1,29 +0,0 @@ -:0200000480007A -:100000006F00C004732F2034930F8000630AFF0336 -:10001000930F90006306FF03930FB0006302FF038A -:10002000170F0080130F0FFE63040F0067000F000F -:10003000732F203463540F006F004000136E9E53E3 -:10004000171F00002320CFFD6FF09FFF732540F1A5 -:100050006310050073251030635805000F00F00F82 -:10006000130E100073000000130E00009702000032 -:10007000938282F973905230735020307350303035 -:1000800073504030970200809382C2F7638C020065 -:10009000739052109302B01A739022307323203061 -:1000A000E39E62F873500030970200009382420191 -:1000B00073901234732540F173002030B7000000B4 -:1000C000930E0000130E2000639AD005B7F0FFFFD7 -:1000D00093D01040930E0080130E30006390D00533 -:1000E000B7F0FF7F93D04041930EF07F130E400096 -:1000F0006396D003B700008093D04041930E0080F8 -:10010000130E5000639CD00137000080930E000056 -:10011000130E60006314D001631CC0010F00F00FC8 -:1001200063000E00131E1E00136E1E0073000000FD -:100130000F00F00F130E100073000000731000C0CA -:0401400000000000BB -:1010000000000000000000000000000000000000E0 -:1010100000000000000000000000000000000000D0 -:1010200000000000000000000000000000000000C0 -:1010300000000000000000000000000000000000B0 -:081040000000000000000000A8 -:040000058000200057 -:00000001FF diff --git a/benchmarks/riscv_tests/rv32ui-p-lui.hex.hex b/benchmarks/riscv_tests/rv32ui-p-lui.hex.hex deleted file mode 100644 index f362421a..00000000 --- a/benchmarks/riscv_tests/rv32ui-p-lui.hex.hex +++ /dev/null @@ -1,29 +0,0 @@ -:0200000480007A -:100000006F00C004732F2034930F8000630AFF0336 -:10001000930F90006306FF03930FB0006302FF038A -:10002000170F0080130F0FFE63040F0067000F000F -:10003000732F203463540F006F004000136E9E53E3 -:10004000171F00002320CFFD6FF09FFF732540F1A5 -:100050006310050073251030635805000F00F00F82 -:10006000130E100073000000130E00009702000032 -:10007000938282F973905230735020307350303035 -:1000800073504030970200809382C2F7638C020065 -:10009000739052109302B01A739022307323203061 -:1000A000E39E62F873500030970200009382420191 -:1000B00073901234732540F173002030B7000000B4 -:1000C000930E0000130E2000639AD005B7F0FFFFD7 -:1000D00093D01040930E0080130E30006390D00533 -:1000E000B7F0FF7F93D04041930EF07F130E400096 -:1000F0006396D003B700008093D04041930E0080F8 -:10010000130E5000639CD00137000080930E000056 -:10011000130E60006314D001631CC0010F00F00FC8 -:1001200063000E00131E1E00136E1E0073000000FD -:100130000F00F00F130E100073000000731000C0CA -:0401400000000000BB -:1010000000000000000000000000000000000000E0 -:1010100000000000000000000000000000000000D0 -:1010200000000000000000000000000000000000C0 -:1010300000000000000000000000000000000000B0 -:081040000000000000000000A8 -:040000058000200057 -:00000001FF diff --git a/benchmarks/riscv_tests/rv32ui-p-lw.dump b/benchmarks/riscv_tests/rv32ui-p-lw.dump deleted file mode 100644 index a33f55a2..00000000 --- a/benchmarks/riscv_tests/rv32ui-p-lw.dump +++ /dev/null @@ -1,344 +0,0 @@ - -rv32ui-p-lw: file format elf32-littleriscv - - -Disassembly of section .text.init: - -80000000 <_start>: -80000000: 04c0006f j 8000004c - -80000004 : -80000004: 34202f73 csrr t5,mcause -80000008: 00800f93 li t6,8 -8000000c: 03ff0a63 beq t5,t6,80000040 -80000010: 00900f93 li t6,9 -80000014: 03ff0663 beq t5,t6,80000040 -80000018: 00b00f93 li t6,11 -8000001c: 03ff0263 beq t5,t6,80000040 -80000020: 80000f17 auipc t5,0x80000 -80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> -80000028: 000f0463 beqz t5,80000030 -8000002c: 000f0067 jr t5 -80000030: 34202f73 csrr t5,mcause -80000034: 000f5463 bgez t5,8000003c -80000038: 0040006f j 8000003c - -8000003c : -8000003c: 5391e193 ori gp,gp,1337 - -80000040 : -80000040: 00001f17 auipc t5,0x1 -80000044: fc3f2023 sw gp,-64(t5) # 80001000 -80000048: ff9ff06f j 80000040 - -8000004c : -8000004c: f1402573 csrr a0,mhartid -80000050: 00051063 bnez a0,80000050 -80000054: 00000297 auipc t0,0x0 -80000058: 01028293 addi t0,t0,16 # 80000064 -8000005c: 30529073 csrw mtvec,t0 -80000060: 18005073 csrwi satp,0 -80000064: 00000297 auipc t0,0x0 -80000068: 02028293 addi t0,t0,32 # 80000084 -8000006c: 30529073 csrw mtvec,t0 -80000070: 800002b7 lui t0,0x80000 -80000074: fff28293 addi t0,t0,-1 # 7fffffff <_end+0xffffdfef> -80000078: 3b029073 csrw pmpaddr0,t0 -8000007c: 01f00293 li t0,31 -80000080: 3a029073 csrw pmpcfg0,t0 -80000084: 00000297 auipc t0,0x0 -80000088: 01828293 addi t0,t0,24 # 8000009c -8000008c: 30529073 csrw mtvec,t0 -80000090: 30205073 csrwi medeleg,0 -80000094: 30305073 csrwi mideleg,0 -80000098: 30405073 csrwi mie,0 -8000009c: 00000193 li gp,0 -800000a0: 00000297 auipc t0,0x0 -800000a4: f6428293 addi t0,t0,-156 # 80000004 -800000a8: 30529073 csrw mtvec,t0 -800000ac: 00100513 li a0,1 -800000b0: 01f51513 slli a0,a0,0x1f -800000b4: 00054c63 bltz a0,800000cc -800000b8: 0ff0000f fence -800000bc: 00100193 li gp,1 -800000c0: 05d00893 li a7,93 -800000c4: 00000513 li a0,0 -800000c8: 00000073 ecall -800000cc: 80000297 auipc t0,0x80000 -800000d0: f3428293 addi t0,t0,-204 # 0 <_start-0x80000000> -800000d4: 00028e63 beqz t0,800000f0 -800000d8: 10529073 csrw stvec,t0 -800000dc: 0000b2b7 lui t0,0xb -800000e0: 10928293 addi t0,t0,265 # b109 <_start-0x7fff4ef7> -800000e4: 30229073 csrw medeleg,t0 -800000e8: 30202373 csrr t1,medeleg -800000ec: f46298e3 bne t0,t1,8000003c -800000f0: 30005073 csrwi mstatus,0 -800000f4: 00000297 auipc t0,0x0 -800000f8: 01428293 addi t0,t0,20 # 80000108 -800000fc: 34129073 csrw mepc,t0 -80000100: f1402573 csrr a0,mhartid -80000104: 30200073 mret - -80000108 : -80000108: 00002097 auipc ra,0x2 -8000010c: ef808093 addi ra,ra,-264 # 80002000 -80000110: 0000a703 lw a4,0(ra) -80000114: 00ff0eb7 lui t4,0xff0 -80000118: 0ffe8e93 addi t4,t4,255 # ff00ff <_start-0x7f00ff01> -8000011c: 00200193 li gp,2 -80000120: 27d71a63 bne a4,t4,80000394 - -80000124 : -80000124: 00002097 auipc ra,0x2 -80000128: edc08093 addi ra,ra,-292 # 80002000 -8000012c: 0040a703 lw a4,4(ra) -80000130: ff010eb7 lui t4,0xff010 -80000134: f00e8e93 addi t4,t4,-256 # ff00ff00 <_end+0x7f00def0> -80000138: 00300193 li gp,3 -8000013c: 25d71c63 bne a4,t4,80000394 - -80000140 : -80000140: 00002097 auipc ra,0x2 -80000144: ec008093 addi ra,ra,-320 # 80002000 -80000148: 0080a703 lw a4,8(ra) -8000014c: 0ff01eb7 lui t4,0xff01 -80000150: ff0e8e93 addi t4,t4,-16 # ff00ff0 <_start-0x700ff010> -80000154: 00400193 li gp,4 -80000158: 23d71e63 bne a4,t4,80000394 - -8000015c : -8000015c: 00002097 auipc ra,0x2 -80000160: ea408093 addi ra,ra,-348 # 80002000 -80000164: 00c0a703 lw a4,12(ra) -80000168: f00ffeb7 lui t4,0xf00ff -8000016c: 00fe8e93 addi t4,t4,15 # f00ff00f <_end+0x700fcfff> -80000170: 00500193 li gp,5 -80000174: 23d71063 bne a4,t4,80000394 - -80000178 : -80000178: 00002097 auipc ra,0x2 -8000017c: e9408093 addi ra,ra,-364 # 8000200c -80000180: ff40a703 lw a4,-12(ra) -80000184: 00ff0eb7 lui t4,0xff0 -80000188: 0ffe8e93 addi t4,t4,255 # ff00ff <_start-0x7f00ff01> -8000018c: 00600193 li gp,6 -80000190: 21d71263 bne a4,t4,80000394 - -80000194 : -80000194: 00002097 auipc ra,0x2 -80000198: e7808093 addi ra,ra,-392 # 8000200c -8000019c: ff80a703 lw a4,-8(ra) -800001a0: ff010eb7 lui t4,0xff010 -800001a4: f00e8e93 addi t4,t4,-256 # ff00ff00 <_end+0x7f00def0> -800001a8: 00700193 li gp,7 -800001ac: 1fd71463 bne a4,t4,80000394 - -800001b0 : -800001b0: 00002097 auipc ra,0x2 -800001b4: e5c08093 addi ra,ra,-420 # 8000200c -800001b8: ffc0a703 lw a4,-4(ra) -800001bc: 0ff01eb7 lui t4,0xff01 -800001c0: ff0e8e93 addi t4,t4,-16 # ff00ff0 <_start-0x700ff010> -800001c4: 00800193 li gp,8 -800001c8: 1dd71663 bne a4,t4,80000394 - -800001cc : -800001cc: 00002097 auipc ra,0x2 -800001d0: e4008093 addi ra,ra,-448 # 8000200c -800001d4: 0000a703 lw a4,0(ra) -800001d8: f00ffeb7 lui t4,0xf00ff -800001dc: 00fe8e93 addi t4,t4,15 # f00ff00f <_end+0x700fcfff> -800001e0: 00900193 li gp,9 -800001e4: 1bd71863 bne a4,t4,80000394 - -800001e8 : -800001e8: 00002097 auipc ra,0x2 -800001ec: e1808093 addi ra,ra,-488 # 80002000 -800001f0: fe008093 addi ra,ra,-32 -800001f4: 0200a283 lw t0,32(ra) -800001f8: 00ff0eb7 lui t4,0xff0 -800001fc: 0ffe8e93 addi t4,t4,255 # ff00ff <_start-0x7f00ff01> -80000200: 00a00193 li gp,10 -80000204: 19d29863 bne t0,t4,80000394 - -80000208 : -80000208: 00002097 auipc ra,0x2 -8000020c: df808093 addi ra,ra,-520 # 80002000 -80000210: ffd08093 addi ra,ra,-3 -80000214: 0070a283 lw t0,7(ra) -80000218: ff010eb7 lui t4,0xff010 -8000021c: f00e8e93 addi t4,t4,-256 # ff00ff00 <_end+0x7f00def0> -80000220: 00b00193 li gp,11 -80000224: 17d29863 bne t0,t4,80000394 - -80000228 : -80000228: 00c00193 li gp,12 -8000022c: 00000213 li tp,0 -80000230: 00002097 auipc ra,0x2 -80000234: dd408093 addi ra,ra,-556 # 80002004 -80000238: 0040a703 lw a4,4(ra) -8000023c: 00070313 mv t1,a4 -80000240: 0ff01eb7 lui t4,0xff01 -80000244: ff0e8e93 addi t4,t4,-16 # ff00ff0 <_start-0x700ff010> -80000248: 15d31663 bne t1,t4,80000394 -8000024c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000250: 00200293 li t0,2 -80000254: fc521ee3 bne tp,t0,80000230 - -80000258 : -80000258: 00d00193 li gp,13 -8000025c: 00000213 li tp,0 -80000260: 00002097 auipc ra,0x2 -80000264: da808093 addi ra,ra,-600 # 80002008 -80000268: 0040a703 lw a4,4(ra) -8000026c: 00000013 nop -80000270: 00070313 mv t1,a4 -80000274: f00ffeb7 lui t4,0xf00ff -80000278: 00fe8e93 addi t4,t4,15 # f00ff00f <_end+0x700fcfff> -8000027c: 11d31c63 bne t1,t4,80000394 -80000280: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000284: 00200293 li t0,2 -80000288: fc521ce3 bne tp,t0,80000260 - -8000028c : -8000028c: 00e00193 li gp,14 -80000290: 00000213 li tp,0 -80000294: 00002097 auipc ra,0x2 -80000298: d6c08093 addi ra,ra,-660 # 80002000 -8000029c: 0040a703 lw a4,4(ra) -800002a0: 00000013 nop -800002a4: 00000013 nop -800002a8: 00070313 mv t1,a4 -800002ac: ff010eb7 lui t4,0xff010 -800002b0: f00e8e93 addi t4,t4,-256 # ff00ff00 <_end+0x7f00def0> -800002b4: 0fd31063 bne t1,t4,80000394 -800002b8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -800002bc: 00200293 li t0,2 -800002c0: fc521ae3 bne tp,t0,80000294 - -800002c4 : -800002c4: 00f00193 li gp,15 -800002c8: 00000213 li tp,0 -800002cc: 00002097 auipc ra,0x2 -800002d0: d3808093 addi ra,ra,-712 # 80002004 -800002d4: 0040a703 lw a4,4(ra) -800002d8: 0ff01eb7 lui t4,0xff01 -800002dc: ff0e8e93 addi t4,t4,-16 # ff00ff0 <_start-0x700ff010> -800002e0: 0bd71a63 bne a4,t4,80000394 -800002e4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -800002e8: 00200293 li t0,2 -800002ec: fe5210e3 bne tp,t0,800002cc - -800002f0 : -800002f0: 01000193 li gp,16 -800002f4: 00000213 li tp,0 -800002f8: 00002097 auipc ra,0x2 -800002fc: d1008093 addi ra,ra,-752 # 80002008 -80000300: 00000013 nop -80000304: 0040a703 lw a4,4(ra) -80000308: f00ffeb7 lui t4,0xf00ff -8000030c: 00fe8e93 addi t4,t4,15 # f00ff00f <_end+0x700fcfff> -80000310: 09d71263 bne a4,t4,80000394 -80000314: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000318: 00200293 li t0,2 -8000031c: fc521ee3 bne tp,t0,800002f8 - -80000320 : -80000320: 01100193 li gp,17 -80000324: 00000213 li tp,0 -80000328: 00002097 auipc ra,0x2 -8000032c: cd808093 addi ra,ra,-808 # 80002000 -80000330: 00000013 nop -80000334: 00000013 nop -80000338: 0040a703 lw a4,4(ra) -8000033c: ff010eb7 lui t4,0xff010 -80000340: f00e8e93 addi t4,t4,-256 # ff00ff00 <_end+0x7f00def0> -80000344: 05d71863 bne a4,t4,80000394 -80000348: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -8000034c: 00200293 li t0,2 -80000350: fc521ce3 bne tp,t0,80000328 - -80000354 : -80000354: 00002297 auipc t0,0x2 -80000358: cac28293 addi t0,t0,-852 # 80002000 -8000035c: 0002a103 lw sp,0(t0) -80000360: 00200113 li sp,2 -80000364: 00200e93 li t4,2 -80000368: 01200193 li gp,18 -8000036c: 03d11463 bne sp,t4,80000394 - -80000370 : -80000370: 00002297 auipc t0,0x2 -80000374: c9028293 addi t0,t0,-880 # 80002000 -80000378: 0002a103 lw sp,0(t0) -8000037c: 00000013 nop -80000380: 00200113 li sp,2 -80000384: 00200e93 li t4,2 -80000388: 01300193 li gp,19 -8000038c: 01d11463 bne sp,t4,80000394 -80000390: 02301063 bne zero,gp,800003b0 - -80000394 : -80000394: 0ff0000f fence -80000398: 00018063 beqz gp,80000398 -8000039c: 00119193 slli gp,gp,0x1 -800003a0: 0011e193 ori gp,gp,1 -800003a4: 05d00893 li a7,93 -800003a8: 00018513 mv a0,gp -800003ac: 00000073 ecall - -800003b0 : -800003b0: 0ff0000f fence -800003b4: 00100193 li gp,1 -800003b8: 05d00893 li a7,93 -800003bc: 00000513 li a0,0 -800003c0: 00000073 ecall -800003c4: c0001073 unimp -800003c8: 0000 unimp -800003ca: 0000 unimp -800003cc: 0000 unimp -800003ce: 0000 unimp -800003d0: 0000 unimp -800003d2: 0000 unimp -800003d4: 0000 unimp -800003d6: 0000 unimp -800003d8: 0000 unimp -800003da: 0000 unimp -800003dc: 0000 unimp -800003de: 0000 unimp -800003e0: 0000 unimp -800003e2: 0000 unimp -800003e4: 0000 unimp -800003e6: 0000 unimp -800003e8: 0000 unimp -800003ea: 0000 unimp -800003ec: 0000 unimp -800003ee: 0000 unimp -800003f0: 0000 unimp -800003f2: 0000 unimp -800003f4: 0000 unimp -800003f6: 0000 unimp -800003f8: 0000 unimp -800003fa: 0000 unimp -800003fc: 0000 unimp -800003fe: 0000 unimp -80000400: 0000 unimp -80000402: 0000 unimp - -Disassembly of section .data: - -80002000 : -80002000: 00ff 0xff -80002002: 00ff 0xff - -80002004 : -80002004: ff00 fsw fs0,56(a4) -80002006: ff00 fsw fs0,56(a4) - -80002008 : -80002008: 0ff0 addi a2,sp,988 -8000200a: 0ff0 addi a2,sp,988 - -8000200c : -8000200c: f00ff00f 0xf00ff00f diff --git a/benchmarks/riscv_tests/rv32ui-p-lw.hex b/benchmarks/riscv_tests/rv32ui-p-lw.hex deleted file mode 100644 index 6cf9e00a..00000000 --- a/benchmarks/riscv_tests/rv32ui-p-lw.hex +++ /dev/null @@ -1,66 +0,0 @@ -:0200000480007A -:100000006F00C004732F2034930F8000630AFF0336 -:10001000930F90006306FF03930FB0006302FF038A -:10002000170F0080130F0FFE63040F0067000F000F -:10003000732F203463540F006F004000136E9E53E3 -:10004000171F00002320CFFD6FF09FFF732540F1A5 -:100050006310050073251030635805000F00F00F82 -:10006000130E100073000000130E00009702000032 -:10007000938282F973905230735020307350303035 -:1000800073504030970200809382C2F7638C020065 -:10009000739052109302B01A739022307323203061 -:1000A000E39E62F873500030970200009382420191 -:1000B00073901234732540F17300203097200000B4 -:1000C000938040F483A10000B70EFF00938EFE0FD3 -:1000D000130E2000639AD12797200000938080F2AE -:1000E00083A14000B70E01FF938E0EF0130E300077 -:1000F000639CD125972000009380C0F083A18000ED -:10010000B71EF00F938E0EFF130E4000639ED12397 -:1001100097200000938000EF83A1C000B7FE0FF08E -:10012000938EFE00130E50006390D12397200000A1 -:10013000938000EE83A140FFB70EFF00938EFE0F69 -:10014000130E60006392D12197200000938040EC51 -:1001500083A180FFB70E01FF938E0EF0130E700087 -:100160006394D11F97200000938080EA83A1C0FF91 -:10017000B71EF00F938E0EFF130E80006396D11DF5 -:10018000972000009380C0E883A10000B7FE0FF025 -:10019000938EFE00130E90006398D11B97200000F1 -:1001A000938040E6938000FE83A10002B70EFF001B -:1001B000938EFE0F130EA0006398D11997200000B4 -:1001C000938040E49380D0FF83A17000B70E01FFBD -:1001D000938E0EF0130EB0006398D117130EC0006B -:1001E0001302000097200000938000E283A14000EA -:1001F00013830100B71EF00F938E0EFF6316D31505 -:100200001302120093022000E31E52FC130ED000D2 -:100210001302000097200000938040DF83A140007C -:100220001300000013830100B7FE0FF0938EFE0051 -:10023000631CD3111302120093022000E31C52FC32 -:10024000130EE0001302000097200000938080DB73 -:1002500083A140001300000013000000138301007D -:10026000B70E01FF938E0EF06310D30F130212002E -:1002700093022000E31A52FC130EF0001302000058 -:1002800097200000938040D883A14000B71EF00F54 -:10029000938E0EFF639AD10B13021200930220007B -:1002A000E31052FE130E000113020000972000001D -:1002B0009380C0D51300000083A14000B7FE0FF06B -:1002C000938EFE006392D109130212009302200064 -:1002D000E31E52FC130E10011302000097200000D1 -:1002E000938040D2130000001300000083A140005F -:1002F000B70E01FF938E0EF06398D1051302120022 -:1003000093022000E31C52FC97210000938181CFCF -:1003100003A1010013012000930E2000130E200101 -:100320006314D103972100009381C1CD03A1010083 -:100330001300000013012000930E2000130E300163 -:100340006314D101631CC0010F00F00F63000E00A5 -:10035000131E1E00136E1E00730000000F00F00F2E -:10036000130E100073000000731000C000000000A6 -:10037000000000000000000000000000000000007D -:040380000000000079 -:1010000000000000000000000000000000000000E0 -:1010100000000000000000000000000000000000D0 -:1010200000000000000000000000000000000000C0 -:1010300000000000000000000000000000000000B0 -:081040000000000000000000A8 -:10200000FF00FF0000FF00FFF00FF00F0FF00FF0D8 -:040000058000200057 -:00000001FF diff --git a/benchmarks/riscv_tests/rv32ui-p-or.dump b/benchmarks/riscv_tests/rv32ui-p-or.dump deleted file mode 100644 index 1e38373e..00000000 --- a/benchmarks/riscv_tests/rv32ui-p-or.dump +++ /dev/null @@ -1,457 +0,0 @@ - -rv32ui-p-or: file format elf32-littleriscv - - -Disassembly of section .text.init: - -80000000 <_start>: -80000000: 04c0006f j 8000004c - -80000004 : -80000004: 34202f73 csrr t5,mcause -80000008: 00800f93 li t6,8 -8000000c: 03ff0a63 beq t5,t6,80000040 -80000010: 00900f93 li t6,9 -80000014: 03ff0663 beq t5,t6,80000040 -80000018: 00b00f93 li t6,11 -8000001c: 03ff0263 beq t5,t6,80000040 -80000020: 80000f17 auipc t5,0x80000 -80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> -80000028: 000f0463 beqz t5,80000030 -8000002c: 000f0067 jr t5 -80000030: 34202f73 csrr t5,mcause -80000034: 000f5463 bgez t5,8000003c -80000038: 0040006f j 8000003c - -8000003c : -8000003c: 5391e193 ori gp,gp,1337 - -80000040 : -80000040: 00001f17 auipc t5,0x1 -80000044: fc3f2023 sw gp,-64(t5) # 80001000 -80000048: ff9ff06f j 80000040 - -8000004c : -8000004c: f1402573 csrr a0,mhartid -80000050: 00051063 bnez a0,80000050 -80000054: 00000297 auipc t0,0x0 -80000058: 01028293 addi t0,t0,16 # 80000064 -8000005c: 30529073 csrw mtvec,t0 -80000060: 18005073 csrwi satp,0 -80000064: 00000297 auipc t0,0x0 -80000068: 02028293 addi t0,t0,32 # 80000084 -8000006c: 30529073 csrw mtvec,t0 -80000070: 800002b7 lui t0,0x80000 -80000074: fff28293 addi t0,t0,-1 # 7fffffff <_end+0xffffdfff> -80000078: 3b029073 csrw pmpaddr0,t0 -8000007c: 01f00293 li t0,31 -80000080: 3a029073 csrw pmpcfg0,t0 -80000084: 00000297 auipc t0,0x0 -80000088: 01828293 addi t0,t0,24 # 8000009c -8000008c: 30529073 csrw mtvec,t0 -80000090: 30205073 csrwi medeleg,0 -80000094: 30305073 csrwi mideleg,0 -80000098: 30405073 csrwi mie,0 -8000009c: 00000193 li gp,0 -800000a0: 00000297 auipc t0,0x0 -800000a4: f6428293 addi t0,t0,-156 # 80000004 -800000a8: 30529073 csrw mtvec,t0 -800000ac: 00100513 li a0,1 -800000b0: 01f51513 slli a0,a0,0x1f -800000b4: 00054c63 bltz a0,800000cc -800000b8: 0ff0000f fence -800000bc: 00100193 li gp,1 -800000c0: 05d00893 li a7,93 -800000c4: 00000513 li a0,0 -800000c8: 00000073 ecall -800000cc: 80000297 auipc t0,0x80000 -800000d0: f3428293 addi t0,t0,-204 # 0 <_start-0x80000000> -800000d4: 00028e63 beqz t0,800000f0 -800000d8: 10529073 csrw stvec,t0 -800000dc: 0000b2b7 lui t0,0xb -800000e0: 10928293 addi t0,t0,265 # b109 <_start-0x7fff4ef7> -800000e4: 30229073 csrw medeleg,t0 -800000e8: 30202373 csrr t1,medeleg -800000ec: f46298e3 bne t0,t1,8000003c -800000f0: 30005073 csrwi mstatus,0 -800000f4: 00000297 auipc t0,0x0 -800000f8: 01428293 addi t0,t0,20 # 80000108 -800000fc: 34129073 csrw mepc,t0 -80000100: f1402573 csrr a0,mhartid -80000104: 30200073 mret - -80000108 : -80000108: ff0100b7 lui ra,0xff010 -8000010c: f0008093 addi ra,ra,-256 # ff00ff00 <_end+0x7f00df00> -80000110: 0f0f1137 lui sp,0xf0f1 -80000114: f0f10113 addi sp,sp,-241 # f0f0f0f <_start-0x70f0f0f1> -80000118: 0020e733 or a4,ra,sp -8000011c: ff100eb7 lui t4,0xff100 -80000120: f0fe8e93 addi t4,t4,-241 # ff0fff0f <_end+0x7f0fdf0f> -80000124: 00200193 li gp,2 -80000128: 4bd71263 bne a4,t4,800005cc - -8000012c : -8000012c: 0ff010b7 lui ra,0xff01 -80000130: ff008093 addi ra,ra,-16 # ff00ff0 <_start-0x700ff010> -80000134: f0f0f137 lui sp,0xf0f0f -80000138: 0f010113 addi sp,sp,240 # f0f0f0f0 <_end+0x70f0d0f0> -8000013c: 0020e733 or a4,ra,sp -80000140: fff10eb7 lui t4,0xfff10 -80000144: ff0e8e93 addi t4,t4,-16 # fff0fff0 <_end+0x7ff0dff0> -80000148: 00300193 li gp,3 -8000014c: 49d71063 bne a4,t4,800005cc - -80000150 : -80000150: 00ff00b7 lui ra,0xff0 -80000154: 0ff08093 addi ra,ra,255 # ff00ff <_start-0x7f00ff01> -80000158: 0f0f1137 lui sp,0xf0f1 -8000015c: f0f10113 addi sp,sp,-241 # f0f0f0f <_start-0x70f0f0f1> -80000160: 0020e733 or a4,ra,sp -80000164: 0fff1eb7 lui t4,0xfff1 -80000168: fffe8e93 addi t4,t4,-1 # fff0fff <_start-0x7000f001> -8000016c: 00400193 li gp,4 -80000170: 45d71e63 bne a4,t4,800005cc - -80000174 : -80000174: f00ff0b7 lui ra,0xf00ff -80000178: 00f08093 addi ra,ra,15 # f00ff00f <_end+0x700fd00f> -8000017c: f0f0f137 lui sp,0xf0f0f -80000180: 0f010113 addi sp,sp,240 # f0f0f0f0 <_end+0x70f0d0f0> -80000184: 0020e733 or a4,ra,sp -80000188: f0fffeb7 lui t4,0xf0fff -8000018c: 0ffe8e93 addi t4,t4,255 # f0fff0ff <_end+0x70ffd0ff> -80000190: 00500193 li gp,5 -80000194: 43d71c63 bne a4,t4,800005cc - -80000198 : -80000198: ff0100b7 lui ra,0xff010 -8000019c: f0008093 addi ra,ra,-256 # ff00ff00 <_end+0x7f00df00> -800001a0: 0f0f1137 lui sp,0xf0f1 -800001a4: f0f10113 addi sp,sp,-241 # f0f0f0f <_start-0x70f0f0f1> -800001a8: 0020e0b3 or ra,ra,sp -800001ac: ff100eb7 lui t4,0xff100 -800001b0: f0fe8e93 addi t4,t4,-241 # ff0fff0f <_end+0x7f0fdf0f> -800001b4: 00600193 li gp,6 -800001b8: 41d09a63 bne ra,t4,800005cc - -800001bc : -800001bc: ff0100b7 lui ra,0xff010 -800001c0: f0008093 addi ra,ra,-256 # ff00ff00 <_end+0x7f00df00> -800001c4: 0f0f1137 lui sp,0xf0f1 -800001c8: f0f10113 addi sp,sp,-241 # f0f0f0f <_start-0x70f0f0f1> -800001cc: 0020e133 or sp,ra,sp -800001d0: ff100eb7 lui t4,0xff100 -800001d4: f0fe8e93 addi t4,t4,-241 # ff0fff0f <_end+0x7f0fdf0f> -800001d8: 00700193 li gp,7 -800001dc: 3fd11863 bne sp,t4,800005cc - -800001e0 : -800001e0: ff0100b7 lui ra,0xff010 -800001e4: f0008093 addi ra,ra,-256 # ff00ff00 <_end+0x7f00df00> -800001e8: 0010e0b3 or ra,ra,ra -800001ec: ff010eb7 lui t4,0xff010 -800001f0: f00e8e93 addi t4,t4,-256 # ff00ff00 <_end+0x7f00df00> -800001f4: 00800193 li gp,8 -800001f8: 3dd09a63 bne ra,t4,800005cc - -800001fc : -800001fc: 00000213 li tp,0 -80000200: ff0100b7 lui ra,0xff010 -80000204: f0008093 addi ra,ra,-256 # ff00ff00 <_end+0x7f00df00> -80000208: 0f0f1137 lui sp,0xf0f1 -8000020c: f0f10113 addi sp,sp,-241 # f0f0f0f <_start-0x70f0f0f1> -80000210: 0020e733 or a4,ra,sp -80000214: 00070313 mv t1,a4 -80000218: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -8000021c: 00200293 li t0,2 -80000220: fe5210e3 bne tp,t0,80000200 -80000224: ff100eb7 lui t4,0xff100 -80000228: f0fe8e93 addi t4,t4,-241 # ff0fff0f <_end+0x7f0fdf0f> -8000022c: 00900193 li gp,9 -80000230: 39d31e63 bne t1,t4,800005cc - -80000234 : -80000234: 00000213 li tp,0 -80000238: 0ff010b7 lui ra,0xff01 -8000023c: ff008093 addi ra,ra,-16 # ff00ff0 <_start-0x700ff010> -80000240: f0f0f137 lui sp,0xf0f0f -80000244: 0f010113 addi sp,sp,240 # f0f0f0f0 <_end+0x70f0d0f0> -80000248: 0020e733 or a4,ra,sp -8000024c: 00000013 nop -80000250: 00070313 mv t1,a4 -80000254: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000258: 00200293 li t0,2 -8000025c: fc521ee3 bne tp,t0,80000238 -80000260: fff10eb7 lui t4,0xfff10 -80000264: ff0e8e93 addi t4,t4,-16 # fff0fff0 <_end+0x7ff0dff0> -80000268: 00a00193 li gp,10 -8000026c: 37d31063 bne t1,t4,800005cc - -80000270 : -80000270: 00000213 li tp,0 -80000274: 00ff00b7 lui ra,0xff0 -80000278: 0ff08093 addi ra,ra,255 # ff00ff <_start-0x7f00ff01> -8000027c: 0f0f1137 lui sp,0xf0f1 -80000280: f0f10113 addi sp,sp,-241 # f0f0f0f <_start-0x70f0f0f1> -80000284: 0020e733 or a4,ra,sp -80000288: 00000013 nop -8000028c: 00000013 nop -80000290: 00070313 mv t1,a4 -80000294: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000298: 00200293 li t0,2 -8000029c: fc521ce3 bne tp,t0,80000274 -800002a0: 0fff1eb7 lui t4,0xfff1 -800002a4: fffe8e93 addi t4,t4,-1 # fff0fff <_start-0x7000f001> -800002a8: 00b00193 li gp,11 -800002ac: 33d31063 bne t1,t4,800005cc - -800002b0 : -800002b0: 00000213 li tp,0 -800002b4: ff0100b7 lui ra,0xff010 -800002b8: f0008093 addi ra,ra,-256 # ff00ff00 <_end+0x7f00df00> -800002bc: 0f0f1137 lui sp,0xf0f1 -800002c0: f0f10113 addi sp,sp,-241 # f0f0f0f <_start-0x70f0f0f1> -800002c4: 0020e733 or a4,ra,sp -800002c8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -800002cc: 00200293 li t0,2 -800002d0: fe5212e3 bne tp,t0,800002b4 -800002d4: ff100eb7 lui t4,0xff100 -800002d8: f0fe8e93 addi t4,t4,-241 # ff0fff0f <_end+0x7f0fdf0f> -800002dc: 00c00193 li gp,12 -800002e0: 2fd71663 bne a4,t4,800005cc - -800002e4 : -800002e4: 00000213 li tp,0 -800002e8: 0ff010b7 lui ra,0xff01 -800002ec: ff008093 addi ra,ra,-16 # ff00ff0 <_start-0x700ff010> -800002f0: f0f0f137 lui sp,0xf0f0f -800002f4: 0f010113 addi sp,sp,240 # f0f0f0f0 <_end+0x70f0d0f0> -800002f8: 00000013 nop -800002fc: 0020e733 or a4,ra,sp -80000300: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000304: 00200293 li t0,2 -80000308: fe5210e3 bne tp,t0,800002e8 -8000030c: fff10eb7 lui t4,0xfff10 -80000310: ff0e8e93 addi t4,t4,-16 # fff0fff0 <_end+0x7ff0dff0> -80000314: 00d00193 li gp,13 -80000318: 2bd71a63 bne a4,t4,800005cc - -8000031c : -8000031c: 00000213 li tp,0 -80000320: 00ff00b7 lui ra,0xff0 -80000324: 0ff08093 addi ra,ra,255 # ff00ff <_start-0x7f00ff01> -80000328: 0f0f1137 lui sp,0xf0f1 -8000032c: f0f10113 addi sp,sp,-241 # f0f0f0f <_start-0x70f0f0f1> -80000330: 00000013 nop -80000334: 00000013 nop -80000338: 0020e733 or a4,ra,sp -8000033c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000340: 00200293 li t0,2 -80000344: fc521ee3 bne tp,t0,80000320 -80000348: 0fff1eb7 lui t4,0xfff1 -8000034c: fffe8e93 addi t4,t4,-1 # fff0fff <_start-0x7000f001> -80000350: 00e00193 li gp,14 -80000354: 27d71c63 bne a4,t4,800005cc - -80000358 : -80000358: 00000213 li tp,0 -8000035c: ff0100b7 lui ra,0xff010 -80000360: f0008093 addi ra,ra,-256 # ff00ff00 <_end+0x7f00df00> -80000364: 00000013 nop -80000368: 0f0f1137 lui sp,0xf0f1 -8000036c: f0f10113 addi sp,sp,-241 # f0f0f0f <_start-0x70f0f0f1> -80000370: 0020e733 or a4,ra,sp -80000374: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000378: 00200293 li t0,2 -8000037c: fe5210e3 bne tp,t0,8000035c -80000380: ff100eb7 lui t4,0xff100 -80000384: f0fe8e93 addi t4,t4,-241 # ff0fff0f <_end+0x7f0fdf0f> -80000388: 00f00193 li gp,15 -8000038c: 25d71063 bne a4,t4,800005cc - -80000390 : -80000390: 00000213 li tp,0 -80000394: 0ff010b7 lui ra,0xff01 -80000398: ff008093 addi ra,ra,-16 # ff00ff0 <_start-0x700ff010> -8000039c: 00000013 nop -800003a0: f0f0f137 lui sp,0xf0f0f -800003a4: 0f010113 addi sp,sp,240 # f0f0f0f0 <_end+0x70f0d0f0> -800003a8: 00000013 nop -800003ac: 0020e733 or a4,ra,sp -800003b0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -800003b4: 00200293 li t0,2 -800003b8: fc521ee3 bne tp,t0,80000394 -800003bc: fff10eb7 lui t4,0xfff10 -800003c0: ff0e8e93 addi t4,t4,-16 # fff0fff0 <_end+0x7ff0dff0> -800003c4: 01000193 li gp,16 -800003c8: 21d71263 bne a4,t4,800005cc - -800003cc : -800003cc: 00000213 li tp,0 -800003d0: 00ff00b7 lui ra,0xff0 -800003d4: 0ff08093 addi ra,ra,255 # ff00ff <_start-0x7f00ff01> -800003d8: 00000013 nop -800003dc: 00000013 nop -800003e0: 0f0f1137 lui sp,0xf0f1 -800003e4: f0f10113 addi sp,sp,-241 # f0f0f0f <_start-0x70f0f0f1> -800003e8: 0020e733 or a4,ra,sp -800003ec: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -800003f0: 00200293 li t0,2 -800003f4: fc521ee3 bne tp,t0,800003d0 -800003f8: 0fff1eb7 lui t4,0xfff1 -800003fc: fffe8e93 addi t4,t4,-1 # fff0fff <_start-0x7000f001> -80000400: 01100193 li gp,17 -80000404: 1dd71463 bne a4,t4,800005cc - -80000408 : -80000408: 00000213 li tp,0 -8000040c: 0f0f1137 lui sp,0xf0f1 -80000410: f0f10113 addi sp,sp,-241 # f0f0f0f <_start-0x70f0f0f1> -80000414: ff0100b7 lui ra,0xff010 -80000418: f0008093 addi ra,ra,-256 # ff00ff00 <_end+0x7f00df00> -8000041c: 0020e733 or a4,ra,sp -80000420: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000424: 00200293 li t0,2 -80000428: fe5212e3 bne tp,t0,8000040c -8000042c: ff100eb7 lui t4,0xff100 -80000430: f0fe8e93 addi t4,t4,-241 # ff0fff0f <_end+0x7f0fdf0f> -80000434: 01200193 li gp,18 -80000438: 19d71a63 bne a4,t4,800005cc - -8000043c : -8000043c: 00000213 li tp,0 -80000440: f0f0f137 lui sp,0xf0f0f -80000444: 0f010113 addi sp,sp,240 # f0f0f0f0 <_end+0x70f0d0f0> -80000448: 0ff010b7 lui ra,0xff01 -8000044c: ff008093 addi ra,ra,-16 # ff00ff0 <_start-0x700ff010> -80000450: 00000013 nop -80000454: 0020e733 or a4,ra,sp -80000458: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -8000045c: 00200293 li t0,2 -80000460: fe5210e3 bne tp,t0,80000440 -80000464: fff10eb7 lui t4,0xfff10 -80000468: ff0e8e93 addi t4,t4,-16 # fff0fff0 <_end+0x7ff0dff0> -8000046c: 01300193 li gp,19 -80000470: 15d71e63 bne a4,t4,800005cc - -80000474 : -80000474: 00000213 li tp,0 -80000478: 0f0f1137 lui sp,0xf0f1 -8000047c: f0f10113 addi sp,sp,-241 # f0f0f0f <_start-0x70f0f0f1> -80000480: 00ff00b7 lui ra,0xff0 -80000484: 0ff08093 addi ra,ra,255 # ff00ff <_start-0x7f00ff01> -80000488: 00000013 nop -8000048c: 00000013 nop -80000490: 0020e733 or a4,ra,sp -80000494: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000498: 00200293 li t0,2 -8000049c: fc521ee3 bne tp,t0,80000478 -800004a0: 0fff1eb7 lui t4,0xfff1 -800004a4: fffe8e93 addi t4,t4,-1 # fff0fff <_start-0x7000f001> -800004a8: 01400193 li gp,20 -800004ac: 13d71063 bne a4,t4,800005cc - -800004b0 : -800004b0: 00000213 li tp,0 -800004b4: 0f0f1137 lui sp,0xf0f1 -800004b8: f0f10113 addi sp,sp,-241 # f0f0f0f <_start-0x70f0f0f1> -800004bc: 00000013 nop -800004c0: ff0100b7 lui ra,0xff010 -800004c4: f0008093 addi ra,ra,-256 # ff00ff00 <_end+0x7f00df00> -800004c8: 0020e733 or a4,ra,sp -800004cc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -800004d0: 00200293 li t0,2 -800004d4: fe5210e3 bne tp,t0,800004b4 -800004d8: ff100eb7 lui t4,0xff100 -800004dc: f0fe8e93 addi t4,t4,-241 # ff0fff0f <_end+0x7f0fdf0f> -800004e0: 01500193 li gp,21 -800004e4: 0fd71463 bne a4,t4,800005cc - -800004e8 : -800004e8: 00000213 li tp,0 -800004ec: f0f0f137 lui sp,0xf0f0f -800004f0: 0f010113 addi sp,sp,240 # f0f0f0f0 <_end+0x70f0d0f0> -800004f4: 00000013 nop -800004f8: 0ff010b7 lui ra,0xff01 -800004fc: ff008093 addi ra,ra,-16 # ff00ff0 <_start-0x700ff010> -80000500: 00000013 nop -80000504: 0020e733 or a4,ra,sp -80000508: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -8000050c: 00200293 li t0,2 -80000510: fc521ee3 bne tp,t0,800004ec -80000514: fff10eb7 lui t4,0xfff10 -80000518: ff0e8e93 addi t4,t4,-16 # fff0fff0 <_end+0x7ff0dff0> -8000051c: 01600193 li gp,22 -80000520: 0bd71663 bne a4,t4,800005cc - -80000524 : -80000524: 00000213 li tp,0 -80000528: 0f0f1137 lui sp,0xf0f1 -8000052c: f0f10113 addi sp,sp,-241 # f0f0f0f <_start-0x70f0f0f1> -80000530: 00000013 nop -80000534: 00000013 nop -80000538: 00ff00b7 lui ra,0xff0 -8000053c: 0ff08093 addi ra,ra,255 # ff00ff <_start-0x7f00ff01> -80000540: 0020e733 or a4,ra,sp -80000544: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000548: 00200293 li t0,2 -8000054c: fc521ee3 bne tp,t0,80000528 -80000550: 0fff1eb7 lui t4,0xfff1 -80000554: fffe8e93 addi t4,t4,-1 # fff0fff <_start-0x7000f001> -80000558: 01700193 li gp,23 -8000055c: 07d71863 bne a4,t4,800005cc - -80000560 : -80000560: ff0100b7 lui ra,0xff010 -80000564: f0008093 addi ra,ra,-256 # ff00ff00 <_end+0x7f00df00> -80000568: 00106133 or sp,zero,ra -8000056c: ff010eb7 lui t4,0xff010 -80000570: f00e8e93 addi t4,t4,-256 # ff00ff00 <_end+0x7f00df00> -80000574: 01800193 li gp,24 -80000578: 05d11a63 bne sp,t4,800005cc - -8000057c : -8000057c: 00ff00b7 lui ra,0xff0 -80000580: 0ff08093 addi ra,ra,255 # ff00ff <_start-0x7f00ff01> -80000584: 0000e133 or sp,ra,zero -80000588: 00ff0eb7 lui t4,0xff0 -8000058c: 0ffe8e93 addi t4,t4,255 # ff00ff <_start-0x7f00ff01> -80000590: 01900193 li gp,25 -80000594: 03d11c63 bne sp,t4,800005cc - -80000598 : -80000598: 000060b3 or ra,zero,zero -8000059c: 00000e93 li t4,0 -800005a0: 01a00193 li gp,26 -800005a4: 03d09463 bne ra,t4,800005cc - -800005a8 : -800005a8: 111110b7 lui ra,0x11111 -800005ac: 11108093 addi ra,ra,273 # 11111111 <_start-0x6eeeeeef> -800005b0: 22222137 lui sp,0x22222 -800005b4: 22210113 addi sp,sp,546 # 22222222 <_start-0x5dddddde> -800005b8: 0020e033 or zero,ra,sp -800005bc: 00000e93 li t4,0 -800005c0: 01b00193 li gp,27 -800005c4: 01d01463 bne zero,t4,800005cc -800005c8: 02301063 bne zero,gp,800005e8 - -800005cc : -800005cc: 0ff0000f fence -800005d0: 00018063 beqz gp,800005d0 -800005d4: 00119193 slli gp,gp,0x1 -800005d8: 0011e193 ori gp,gp,1 -800005dc: 05d00893 li a7,93 -800005e0: 00018513 mv a0,gp -800005e4: 00000073 ecall - -800005e8 : -800005e8: 0ff0000f fence -800005ec: 00100193 li gp,1 -800005f0: 05d00893 li a7,93 -800005f4: 00000513 li a0,0 -800005f8: 00000073 ecall -800005fc: c0001073 unimp -80000600: 0000 unimp -80000602: 0000 unimp diff --git a/benchmarks/riscv_tests/rv32ui-p-or.hex b/benchmarks/riscv_tests/rv32ui-p-or.hex deleted file mode 100644 index e1140c85..00000000 --- a/benchmarks/riscv_tests/rv32ui-p-or.hex +++ /dev/null @@ -1,101 +0,0 @@ -:0200000480007A -:100000006F00C004732F2034930F8000630AFF0336 -:10001000930F90006306FF03930FB0006302FF038A -:10002000170F0080130F0FFE63040F0067000F000F -:10003000732F203463540F006F004000136E9E53E3 -:10004000171F00002320CFFD6FF09FFF732540F1A5 -:100050006310050073251030635805000F00F00F82 -:10006000130E100073000000130E00009702000032 -:10007000938282F973905230735020307350303035 -:1000800073504030970200809382C2F7638C020065 -:10009000739052109302B01A739022307323203061 -:1000A000E39E62F873500030970200009382420191 -:1000B00073901234732540F173002030B70001FFB4 -:1000C000938000F037110F0F1301F1F0B3E120001E -:1000D000B70E10FF938EFEF0130E20006392D14BEB -:1000E000B710F00F938000FF37F1F0F01301010F0C -:1000F000B3E12000B70EF1FF938E0EFF130E300018 -:100100006390D149B700FF009380F00F37110F0FB4 -:100110001301F1F0B3E12000B71EFF0F938EFEFF35 -:10012000130E4000639ED145B7F00FF09380F000AE -:1001300037F1F0F01301010FB3E12000B7FEFFF03B -:10014000938EFE0F130E5000639CD143B70001FF46 -:10015000938000F037110F0F1301F1F0B3E020008E -:10016000B70E10FF938EFEF0130E6000639AD0411D -:10017000B70001FF938000F037110F0F1301F1F06A -:1001800033E12000B70E10FF938EFEF0130E7000C7 -:100190006318D13FB70001FF938000F0B3E0100077 -:1001A000B70E01FF938E0EF0130E8000639AD03DC0 -:1001B00013020000B70001FF938000F037110F0F0A -:1001C0001301F1F0B3E120001383010013021200C8 -:1001D00093022000E31052FEB70E10FF938EFEF044 -:1001E000130E9000631ED33913020000B710F00FF6 -:1001F000938000FF37F1F0F01301010FB3E120000D -:100200001300000013830100130212009302200068 -:10021000E31E52FCB70EF1FF938E0EFF130EA000EB -:100220006310D33713020000B700FF009380F00F74 -:1002300037110F0F1301F1F0B3E12000130000009C -:100240001300000013830100130212009302200028 -:10025000E31C52FCB71EFF0F938EFEFF130EB0007F -:100260006310D33313020000B70001FF938000F046 -:1002700037110F0F1301F1F0B3E120001302120048 -:1002800093022000E31252FEB70E10FF938EFEF091 -:10029000130EC0006396D12F13020000B710F00FA9 -:1002A000938000FF37F1F0F01301010F13000000FD -:1002B000B3E120001302120093022000E31052FE6B -:1002C000B70EF1FF938E0EFF130ED000639AD12B61 -:1002D00013020000B700FF009380F00F37110F0FDB -:1002E0001301F1F01300000013000000B3E120003F -:1002F0001302120093022000E31E52FCB71EFF0FF0 -:10030000938EFEFF130EE000639CD12713020000C2 -:10031000B70001FF938000F01300000037110F0FAA -:100320001301F1F0B3E12000130212009302200048 -:10033000E31052FEB70E10FF938EFEF0130EF00086 -:100340006390D12513020000B710F00F938000FFD7 -:100350001300000037F1F0F01301010F130000004B -:10036000B3E120001302120093022000E31E52FCAE -:10037000B70EF1FF938E0EFF130E00016392D12191 -:1003800013020000B700FF009380F00F130000007D -:100390001300000037110F0F1301F1F0B3E120003B -:1003A0001302120093022000E31E52FCB71EFF0F3F -:1003B000938EFEFF130E10016394D11D13020000F3 -:1003C00037110F0F1301F1F0B70001FF938000F018 -:1003D000B3E120001302120093022000E31252FE48 -:1003E000B70E10FF938EFEF0130E2001639AD11901 -:1003F0001302000037F1F0F01301010FB710F00FF6 -:10040000938000FF13000000B3E1200013021200EC -:1004100093022000E31052FEB70EF1FF938E0EFF01 -:10042000130E3001639ED1151302000037110F0F18 -:100430001301F1F0B700FF009380F00F13000000EC -:1004400013000000B3E12000130212009302200009 -:10045000E31E52FCB71EFF0F938EFEFF130E4001EA -:100460006390D1131302000037110F0F1301F1F045 -:1004700013000000B70001FF938000F0B3E12000FB -:100480001302120093022000E31052FEB70E10FF79 -:10049000938EFEF0130E50016394D10F13020000EF -:1004A00037F1F0F01301010F13000000B710F00F47 -:1004B000938000FF13000000B3E12000130212003C -:1004C00093022000E31E52FCB70EF1FF938E0EFF45 -:1004D000130E60016396D10B1302000037110F0F4A -:1004E0001301F1F01300000013000000B700FF003B -:1004F0009380F00FB3E1200013021200930220005A -:10050000E31E52FCB71EFF0F938EFEFF130E700109 -:100510006398D107B70001FF938000F033611000AA -:10052000B70E01FF938E0EF0130E8001631AD105F2 -:10053000B700FF009380F00F33E10000B70EFF001B -:10054000938EFE0F130E9001631CD103B360000065 -:10055000930E0000130EA0016394D003B710111185 -:1005600093801011372122221301212233E0200031 -:10057000930E0000130EB0016314D001631CC00180 -:100580000F00F00F63000E00131E1E00136E1E00FE -:10059000730000000F00F00F130E10007300000036 -:1005A000731000C000000000000000000000000008 -:1005B000000000000000000000000000000000003B -:0405C0000000000037 -:1010000000000000000000000000000000000000E0 -:1010100000000000000000000000000000000000D0 -:1010200000000000000000000000000000000000C0 -:1010300000000000000000000000000000000000B0 -:081040000000000000000000A8 -:040000058000200057 -:00000001FF diff --git a/benchmarks/riscv_tests/rv32ui-p-ori.dump b/benchmarks/riscv_tests/rv32ui-p-ori.dump deleted file mode 100644 index 943be5ef..00000000 --- a/benchmarks/riscv_tests/rv32ui-p-ori.dump +++ /dev/null @@ -1,265 +0,0 @@ - -rv32ui-p-ori: file format elf32-littleriscv - - -Disassembly of section .text.init: - -80000000 <_start>: -80000000: 04c0006f j 8000004c - -80000004 : -80000004: 34202f73 csrr t5,mcause -80000008: 00800f93 li t6,8 -8000000c: 03ff0a63 beq t5,t6,80000040 -80000010: 00900f93 li t6,9 -80000014: 03ff0663 beq t5,t6,80000040 -80000018: 00b00f93 li t6,11 -8000001c: 03ff0263 beq t5,t6,80000040 -80000020: 80000f17 auipc t5,0x80000 -80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> -80000028: 000f0463 beqz t5,80000030 -8000002c: 000f0067 jr t5 -80000030: 34202f73 csrr t5,mcause -80000034: 000f5463 bgez t5,8000003c -80000038: 0040006f j 8000003c - -8000003c : -8000003c: 5391e193 ori gp,gp,1337 - -80000040 : -80000040: 00001f17 auipc t5,0x1 -80000044: fc3f2023 sw gp,-64(t5) # 80001000 -80000048: ff9ff06f j 80000040 - -8000004c : -8000004c: f1402573 csrr a0,mhartid -80000050: 00051063 bnez a0,80000050 -80000054: 00000297 auipc t0,0x0 -80000058: 01028293 addi t0,t0,16 # 80000064 -8000005c: 30529073 csrw mtvec,t0 -80000060: 18005073 csrwi satp,0 -80000064: 00000297 auipc t0,0x0 -80000068: 02028293 addi t0,t0,32 # 80000084 -8000006c: 30529073 csrw mtvec,t0 -80000070: 800002b7 lui t0,0x80000 -80000074: fff28293 addi t0,t0,-1 # 7fffffff <_end+0xffffdfff> -80000078: 3b029073 csrw pmpaddr0,t0 -8000007c: 01f00293 li t0,31 -80000080: 3a029073 csrw pmpcfg0,t0 -80000084: 00000297 auipc t0,0x0 -80000088: 01828293 addi t0,t0,24 # 8000009c -8000008c: 30529073 csrw mtvec,t0 -80000090: 30205073 csrwi medeleg,0 -80000094: 30305073 csrwi mideleg,0 -80000098: 30405073 csrwi mie,0 -8000009c: 00000193 li gp,0 -800000a0: 00000297 auipc t0,0x0 -800000a4: f6428293 addi t0,t0,-156 # 80000004 -800000a8: 30529073 csrw mtvec,t0 -800000ac: 00100513 li a0,1 -800000b0: 01f51513 slli a0,a0,0x1f -800000b4: 00054c63 bltz a0,800000cc -800000b8: 0ff0000f fence -800000bc: 00100193 li gp,1 -800000c0: 05d00893 li a7,93 -800000c4: 00000513 li a0,0 -800000c8: 00000073 ecall -800000cc: 80000297 auipc t0,0x80000 -800000d0: f3428293 addi t0,t0,-204 # 0 <_start-0x80000000> -800000d4: 00028e63 beqz t0,800000f0 -800000d8: 10529073 csrw stvec,t0 -800000dc: 0000b2b7 lui t0,0xb -800000e0: 10928293 addi t0,t0,265 # b109 <_start-0x7fff4ef7> -800000e4: 30229073 csrw medeleg,t0 -800000e8: 30202373 csrr t1,medeleg -800000ec: f46298e3 bne t0,t1,8000003c -800000f0: 30005073 csrwi mstatus,0 -800000f4: 00000297 auipc t0,0x0 -800000f8: 01428293 addi t0,t0,20 # 80000108 -800000fc: 34129073 csrw mepc,t0 -80000100: f1402573 csrr a0,mhartid -80000104: 30200073 mret - -80000108 : -80000108: ff0100b7 lui ra,0xff010 -8000010c: f0008093 addi ra,ra,-256 # ff00ff00 <_end+0x7f00df00> -80000110: f0f0e713 ori a4,ra,-241 -80000114: f0f00e93 li t4,-241 -80000118: 00200193 li gp,2 -8000011c: 1dd71463 bne a4,t4,800002e4 - -80000120 : -80000120: 0ff010b7 lui ra,0xff01 -80000124: ff008093 addi ra,ra,-16 # ff00ff0 <_start-0x700ff010> -80000128: 0f00e713 ori a4,ra,240 -8000012c: 0ff01eb7 lui t4,0xff01 -80000130: ff0e8e93 addi t4,t4,-16 # ff00ff0 <_start-0x700ff010> -80000134: 00300193 li gp,3 -80000138: 1bd71663 bne a4,t4,800002e4 - -8000013c : -8000013c: 00ff00b7 lui ra,0xff0 -80000140: 0ff08093 addi ra,ra,255 # ff00ff <_start-0x7f00ff01> -80000144: 70f0e713 ori a4,ra,1807 -80000148: 00ff0eb7 lui t4,0xff0 -8000014c: 7ffe8e93 addi t4,t4,2047 # ff07ff <_start-0x7f00f801> -80000150: 00400193 li gp,4 -80000154: 19d71863 bne a4,t4,800002e4 - -80000158 : -80000158: f00ff0b7 lui ra,0xf00ff -8000015c: 00f08093 addi ra,ra,15 # f00ff00f <_end+0x700fd00f> -80000160: 0f00e713 ori a4,ra,240 -80000164: f00ffeb7 lui t4,0xf00ff -80000168: 0ffe8e93 addi t4,t4,255 # f00ff0ff <_end+0x700fd0ff> -8000016c: 00500193 li gp,5 -80000170: 17d71a63 bne a4,t4,800002e4 - -80000174 : -80000174: ff0100b7 lui ra,0xff010 -80000178: f0008093 addi ra,ra,-256 # ff00ff00 <_end+0x7f00df00> -8000017c: 0f00e093 ori ra,ra,240 -80000180: ff010eb7 lui t4,0xff010 -80000184: ff0e8e93 addi t4,t4,-16 # ff00fff0 <_end+0x7f00dff0> -80000188: 00600193 li gp,6 -8000018c: 15d09c63 bne ra,t4,800002e4 - -80000190 : -80000190: 00000213 li tp,0 -80000194: 0ff010b7 lui ra,0xff01 -80000198: ff008093 addi ra,ra,-16 # ff00ff0 <_start-0x700ff010> -8000019c: 0f00e713 ori a4,ra,240 -800001a0: 00070313 mv t1,a4 -800001a4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -800001a8: 00200293 li t0,2 -800001ac: fe5214e3 bne tp,t0,80000194 -800001b0: 0ff01eb7 lui t4,0xff01 -800001b4: ff0e8e93 addi t4,t4,-16 # ff00ff0 <_start-0x700ff010> -800001b8: 00700193 li gp,7 -800001bc: 13d31463 bne t1,t4,800002e4 - -800001c0 : -800001c0: 00000213 li tp,0 -800001c4: 00ff00b7 lui ra,0xff0 -800001c8: 0ff08093 addi ra,ra,255 # ff00ff <_start-0x7f00ff01> -800001cc: 70f0e713 ori a4,ra,1807 -800001d0: 00000013 nop -800001d4: 00070313 mv t1,a4 -800001d8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -800001dc: 00200293 li t0,2 -800001e0: fe5212e3 bne tp,t0,800001c4 -800001e4: 00ff0eb7 lui t4,0xff0 -800001e8: 7ffe8e93 addi t4,t4,2047 # ff07ff <_start-0x7f00f801> -800001ec: 00800193 li gp,8 -800001f0: 0fd31a63 bne t1,t4,800002e4 - -800001f4 : -800001f4: 00000213 li tp,0 -800001f8: f00ff0b7 lui ra,0xf00ff -800001fc: 00f08093 addi ra,ra,15 # f00ff00f <_end+0x700fd00f> -80000200: 0f00e713 ori a4,ra,240 -80000204: 00000013 nop -80000208: 00000013 nop -8000020c: 00070313 mv t1,a4 -80000210: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000214: 00200293 li t0,2 -80000218: fe5210e3 bne tp,t0,800001f8 -8000021c: f00ffeb7 lui t4,0xf00ff -80000220: 0ffe8e93 addi t4,t4,255 # f00ff0ff <_end+0x700fd0ff> -80000224: 00900193 li gp,9 -80000228: 0bd31e63 bne t1,t4,800002e4 - -8000022c : -8000022c: 00000213 li tp,0 -80000230: 0ff010b7 lui ra,0xff01 -80000234: ff008093 addi ra,ra,-16 # ff00ff0 <_start-0x700ff010> -80000238: 0f00e713 ori a4,ra,240 -8000023c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000240: 00200293 li t0,2 -80000244: fe5216e3 bne tp,t0,80000230 -80000248: 0ff01eb7 lui t4,0xff01 -8000024c: ff0e8e93 addi t4,t4,-16 # ff00ff0 <_start-0x700ff010> -80000250: 00a00193 li gp,10 -80000254: 09d71863 bne a4,t4,800002e4 - -80000258 : -80000258: 00000213 li tp,0 -8000025c: 00ff00b7 lui ra,0xff0 -80000260: 0ff08093 addi ra,ra,255 # ff00ff <_start-0x7f00ff01> -80000264: 00000013 nop -80000268: f0f0e713 ori a4,ra,-241 -8000026c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000270: 00200293 li t0,2 -80000274: fe5214e3 bne tp,t0,8000025c -80000278: fff00e93 li t4,-1 -8000027c: 00b00193 li gp,11 -80000280: 07d71263 bne a4,t4,800002e4 - -80000284 : -80000284: 00000213 li tp,0 -80000288: f00ff0b7 lui ra,0xf00ff -8000028c: 00f08093 addi ra,ra,15 # f00ff00f <_end+0x700fd00f> -80000290: 00000013 nop -80000294: 00000013 nop -80000298: 0f00e713 ori a4,ra,240 -8000029c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -800002a0: 00200293 li t0,2 -800002a4: fe5212e3 bne tp,t0,80000288 -800002a8: f00ffeb7 lui t4,0xf00ff -800002ac: 0ffe8e93 addi t4,t4,255 # f00ff0ff <_end+0x700fd0ff> -800002b0: 00c00193 li gp,12 -800002b4: 03d71863 bne a4,t4,800002e4 - -800002b8 : -800002b8: 0f006093 ori ra,zero,240 -800002bc: 0f000e93 li t4,240 -800002c0: 00d00193 li gp,13 -800002c4: 03d09063 bne ra,t4,800002e4 - -800002c8 : -800002c8: 00ff00b7 lui ra,0xff0 -800002cc: 0ff08093 addi ra,ra,255 # ff00ff <_start-0x7f00ff01> -800002d0: 70f0e013 ori zero,ra,1807 -800002d4: 00000e93 li t4,0 -800002d8: 00e00193 li gp,14 -800002dc: 01d01463 bne zero,t4,800002e4 -800002e0: 02301063 bne zero,gp,80000300 - -800002e4 : -800002e4: 0ff0000f fence -800002e8: 00018063 beqz gp,800002e8 -800002ec: 00119193 slli gp,gp,0x1 -800002f0: 0011e193 ori gp,gp,1 -800002f4: 05d00893 li a7,93 -800002f8: 00018513 mv a0,gp -800002fc: 00000073 ecall - -80000300 : -80000300: 0ff0000f fence -80000304: 00100193 li gp,1 -80000308: 05d00893 li a7,93 -8000030c: 00000513 li a0,0 -80000310: 00000073 ecall -80000314: c0001073 unimp -80000318: 0000 unimp -8000031a: 0000 unimp -8000031c: 0000 unimp -8000031e: 0000 unimp -80000320: 0000 unimp -80000322: 0000 unimp -80000324: 0000 unimp -80000326: 0000 unimp -80000328: 0000 unimp -8000032a: 0000 unimp -8000032c: 0000 unimp -8000032e: 0000 unimp -80000330: 0000 unimp -80000332: 0000 unimp -80000334: 0000 unimp -80000336: 0000 unimp -80000338: 0000 unimp -8000033a: 0000 unimp -8000033c: 0000 unimp -8000033e: 0000 unimp -80000340: 0000 unimp -80000342: 0000 unimp diff --git a/benchmarks/riscv_tests/rv32ui-p-ori.hex b/benchmarks/riscv_tests/rv32ui-p-ori.hex deleted file mode 100644 index 17049a8d..00000000 --- a/benchmarks/riscv_tests/rv32ui-p-ori.hex +++ /dev/null @@ -1,53 +0,0 @@ -:0200000480007A -:100000006F00C004732F2034930F8000630AFF0336 -:10001000930F90006306FF03930FB0006302FF038A -:10002000170F0080130F0FFE63040F0067000F000F -:10003000732F203463540F006F004000136E9E53E3 -:10004000171F00002320CFFD6FF09FFF732540F1A5 -:100050006310050073251030635805000F00F00F82 -:10006000130E100073000000130E00009702000032 -:10007000938282F973905230735020307350303035 -:1000800073504030970200809382C2F7638C020065 -:10009000739052109302B01A739022307323203061 -:1000A000E39E62F873500030970200009382420191 -:1000B00073901234732540F173002030B70001FFB4 -:1000C000938000F093E1F0F0930EF0F0130E200017 -:1000D0006394D11DB710F00F938000FF93E1000FE0 -:1000E000B71EF00F938E0EFF130E30006396D11BD8 -:1000F000B700FF009380F00F93E1F070B70EFF00A0 -:10010000938EFE7F130E40006398D119B7F00FF065 -:100110009380F00093E1000FB7FE0FF0938EFE0F77 -:10012000130E5000639AD117B70001FF938000F0BF -:1001300093E0000FB70E01FF938E0EFF130E6000C9 -:10014000639CD01513020000B710F00F938000FFDE -:1001500093E1000F138301001302120093022000A9 -:10016000E31452FEB71EF00F938E0EFF130E7000B5 -:100170006314D31313020000B700FF009380F00F45 -:1001800093E1F070130000001383010013021200CA -:1001900093022000E31252FEB70EFF00938EFE7F03 -:1001A000130E8000631AD30F13020000B7F00FF094 -:1001B0009380F00093E1000F130000001300000093 -:1001C000138301001302120093022000E31052FE79 -:1001D000B7FE0FF0938EFE0F130E9000631ED30B2D -:1001E00013020000B710F00F938000FF93E1000F9F -:1001F0001302120093022000E31652FEB71EF00F06 -:10020000938E0EFF130EA0006398D1091302000015 -:10021000B700FF009380F00F1300000093E1F0F0AF -:100220001302120093022000E31452FE930EF0FF1B -:10023000130EB0006392D10713020000B7F00FF065 -:100240009380F000130000001300000093E1000F02 -:100250001302120093022000E31252FEB7FE0FF0C9 -:10026000938EFE0F130EC0006398D1039360000FAE -:10027000930E000F130ED0006390D003B700FF0061 -:100280009380F00F13E0F070930E0000130EE00067 -:100290006314D001631CC0010F00F00F63000E0057 -:1002A000131E1E00136E1E00730000000F00F00FDF -:1002B000130E100073000000731000C00000000057 -:0402C000000000003A -:1010000000000000000000000000000000000000E0 -:1010100000000000000000000000000000000000D0 -:1010200000000000000000000000000000000000C0 -:1010300000000000000000000000000000000000B0 -:081040000000000000000000A8 -:040000058000200057 -:00000001FF diff --git a/benchmarks/riscv_tests/rv32ui-p-sb.dump b/benchmarks/riscv_tests/rv32ui-p-sb.dump deleted file mode 100644 index c4ec3d70..00000000 --- a/benchmarks/riscv_tests/rv32ui-p-sb.dump +++ /dev/null @@ -1,440 +0,0 @@ - -rv32ui-p-sb: file format elf32-littleriscv - - -Disassembly of section .text.init: - -80000000 <_start>: -80000000: 04c0006f j 8000004c - -80000004 : -80000004: 34202f73 csrr t5,mcause -80000008: 00800f93 li t6,8 -8000000c: 03ff0a63 beq t5,t6,80000040 -80000010: 00900f93 li t6,9 -80000014: 03ff0663 beq t5,t6,80000040 -80000018: 00b00f93 li t6,11 -8000001c: 03ff0263 beq t5,t6,80000040 -80000020: 80000f17 auipc t5,0x80000 -80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> -80000028: 000f0463 beqz t5,80000030 -8000002c: 000f0067 jr t5 -80000030: 34202f73 csrr t5,mcause -80000034: 000f5463 bgez t5,8000003c -80000038: 0040006f j 8000003c - -8000003c : -8000003c: 5391e193 ori gp,gp,1337 - -80000040 : -80000040: 00001f17 auipc t5,0x1 -80000044: fc3f2023 sw gp,-64(t5) # 80001000 -80000048: ff9ff06f j 80000040 - -8000004c : -8000004c: f1402573 csrr a0,mhartid -80000050: 00051063 bnez a0,80000050 -80000054: 00000297 auipc t0,0x0 -80000058: 01028293 addi t0,t0,16 # 80000064 -8000005c: 30529073 csrw mtvec,t0 -80000060: 18005073 csrwi satp,0 -80000064: 00000297 auipc t0,0x0 -80000068: 02028293 addi t0,t0,32 # 80000084 -8000006c: 30529073 csrw mtvec,t0 -80000070: 800002b7 lui t0,0x80000 -80000074: fff28293 addi t0,t0,-1 # 7fffffff <_end+0xffffdfef> -80000078: 3b029073 csrw pmpaddr0,t0 -8000007c: 01f00293 li t0,31 -80000080: 3a029073 csrw pmpcfg0,t0 -80000084: 00000297 auipc t0,0x0 -80000088: 01828293 addi t0,t0,24 # 8000009c -8000008c: 30529073 csrw mtvec,t0 -80000090: 30205073 csrwi medeleg,0 -80000094: 30305073 csrwi mideleg,0 -80000098: 30405073 csrwi mie,0 -8000009c: 00000193 li gp,0 -800000a0: 00000297 auipc t0,0x0 -800000a4: f6428293 addi t0,t0,-156 # 80000004 -800000a8: 30529073 csrw mtvec,t0 -800000ac: 00100513 li a0,1 -800000b0: 01f51513 slli a0,a0,0x1f -800000b4: 00054c63 bltz a0,800000cc -800000b8: 0ff0000f fence -800000bc: 00100193 li gp,1 -800000c0: 05d00893 li a7,93 -800000c4: 00000513 li a0,0 -800000c8: 00000073 ecall -800000cc: 80000297 auipc t0,0x80000 -800000d0: f3428293 addi t0,t0,-204 # 0 <_start-0x80000000> -800000d4: 00028e63 beqz t0,800000f0 -800000d8: 10529073 csrw stvec,t0 -800000dc: 0000b2b7 lui t0,0xb -800000e0: 10928293 addi t0,t0,265 # b109 <_start-0x7fff4ef7> -800000e4: 30229073 csrw medeleg,t0 -800000e8: 30202373 csrr t1,medeleg -800000ec: f46298e3 bne t0,t1,8000003c -800000f0: 30005073 csrwi mstatus,0 -800000f4: 00000297 auipc t0,0x0 -800000f8: 01428293 addi t0,t0,20 # 80000108 -800000fc: 34129073 csrw mepc,t0 -80000100: f1402573 csrr a0,mhartid -80000104: 30200073 mret - -80000108 : -80000108: 00002097 auipc ra,0x2 -8000010c: ef808093 addi ra,ra,-264 # 80002000 -80000110: faa00113 li sp,-86 -80000114: 00208023 sb sp,0(ra) -80000118: 00008703 lb a4,0(ra) -8000011c: faa00e93 li t4,-86 -80000120: 00200193 li gp,2 -80000124: 3dd71c63 bne a4,t4,800004fc - -80000128 : -80000128: 00002097 auipc ra,0x2 -8000012c: ed808093 addi ra,ra,-296 # 80002000 -80000130: 00000113 li sp,0 -80000134: 002080a3 sb sp,1(ra) -80000138: 00108703 lb a4,1(ra) -8000013c: 00000e93 li t4,0 -80000140: 00300193 li gp,3 -80000144: 3bd71c63 bne a4,t4,800004fc - -80000148 : -80000148: 00002097 auipc ra,0x2 -8000014c: eb808093 addi ra,ra,-328 # 80002000 -80000150: fffff137 lui sp,0xfffff -80000154: fa010113 addi sp,sp,-96 # ffffefa0 <_end+0x7fffcf90> -80000158: 00208123 sb sp,2(ra) -8000015c: 00209703 lh a4,2(ra) -80000160: fffffeb7 lui t4,0xfffff -80000164: fa0e8e93 addi t4,t4,-96 # ffffefa0 <_end+0x7fffcf90> -80000168: 00400193 li gp,4 -8000016c: 39d71863 bne a4,t4,800004fc - -80000170 : -80000170: 00002097 auipc ra,0x2 -80000174: e9008093 addi ra,ra,-368 # 80002000 -80000178: 00a00113 li sp,10 -8000017c: 002081a3 sb sp,3(ra) -80000180: 00308703 lb a4,3(ra) -80000184: 00a00e93 li t4,10 -80000188: 00500193 li gp,5 -8000018c: 37d71863 bne a4,t4,800004fc - -80000190 : -80000190: 00002097 auipc ra,0x2 -80000194: e7708093 addi ra,ra,-393 # 80002007 -80000198: faa00113 li sp,-86 -8000019c: fe208ea3 sb sp,-3(ra) -800001a0: ffd08703 lb a4,-3(ra) -800001a4: faa00e93 li t4,-86 -800001a8: 00600193 li gp,6 -800001ac: 35d71863 bne a4,t4,800004fc - -800001b0 : -800001b0: 00002097 auipc ra,0x2 -800001b4: e5708093 addi ra,ra,-425 # 80002007 -800001b8: 00000113 li sp,0 -800001bc: fe208f23 sb sp,-2(ra) -800001c0: ffe08703 lb a4,-2(ra) -800001c4: 00000e93 li t4,0 -800001c8: 00700193 li gp,7 -800001cc: 33d71863 bne a4,t4,800004fc - -800001d0 : -800001d0: 00002097 auipc ra,0x2 -800001d4: e3708093 addi ra,ra,-457 # 80002007 -800001d8: fa000113 li sp,-96 -800001dc: fe208fa3 sb sp,-1(ra) -800001e0: fff08703 lb a4,-1(ra) -800001e4: fa000e93 li t4,-96 -800001e8: 00800193 li gp,8 -800001ec: 31d71863 bne a4,t4,800004fc - -800001f0 : -800001f0: 00002097 auipc ra,0x2 -800001f4: e1708093 addi ra,ra,-489 # 80002007 -800001f8: 00a00113 li sp,10 -800001fc: 00208023 sb sp,0(ra) -80000200: 00008703 lb a4,0(ra) -80000204: 00a00e93 li t4,10 -80000208: 00900193 li gp,9 -8000020c: 2fd71863 bne a4,t4,800004fc - -80000210 : -80000210: 00002097 auipc ra,0x2 -80000214: df808093 addi ra,ra,-520 # 80002008 -80000218: 12345137 lui sp,0x12345 -8000021c: 67810113 addi sp,sp,1656 # 12345678 <_start-0x6dcba988> -80000220: fe008213 addi tp,ra,-32 -80000224: 02220023 sb sp,32(tp) # 20 <_start-0x7fffffe0> -80000228: 00008283 lb t0,0(ra) -8000022c: 07800e93 li t4,120 -80000230: 00a00193 li gp,10 -80000234: 2dd29463 bne t0,t4,800004fc - -80000238 : -80000238: 00002097 auipc ra,0x2 -8000023c: dd008093 addi ra,ra,-560 # 80002008 -80000240: 00003137 lui sp,0x3 -80000244: 09810113 addi sp,sp,152 # 3098 <_start-0x7fffcf68> -80000248: ffa08093 addi ra,ra,-6 -8000024c: 002083a3 sb sp,7(ra) -80000250: 00002217 auipc tp,0x2 -80000254: db920213 addi tp,tp,-583 # 80002009 -80000258: 00020283 lb t0,0(tp) # 0 <_start-0x80000000> -8000025c: f9800e93 li t4,-104 -80000260: 00b00193 li gp,11 -80000264: 29d29c63 bne t0,t4,800004fc - -80000268 : -80000268: 00c00193 li gp,12 -8000026c: 00000213 li tp,0 -80000270: fdd00093 li ra,-35 -80000274: 00002117 auipc sp,0x2 -80000278: d8c10113 addi sp,sp,-628 # 80002000 -8000027c: 00110023 sb ra,0(sp) -80000280: 00010703 lb a4,0(sp) -80000284: fdd00e93 li t4,-35 -80000288: 27d71a63 bne a4,t4,800004fc -8000028c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000290: 00200293 li t0,2 -80000294: fc521ee3 bne tp,t0,80000270 - -80000298 : -80000298: 00d00193 li gp,13 -8000029c: 00000213 li tp,0 -800002a0: fcd00093 li ra,-51 -800002a4: 00002117 auipc sp,0x2 -800002a8: d5c10113 addi sp,sp,-676 # 80002000 -800002ac: 00000013 nop -800002b0: 001100a3 sb ra,1(sp) -800002b4: 00110703 lb a4,1(sp) -800002b8: fcd00e93 li t4,-51 -800002bc: 25d71063 bne a4,t4,800004fc -800002c0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -800002c4: 00200293 li t0,2 -800002c8: fc521ce3 bne tp,t0,800002a0 - -800002cc : -800002cc: 00e00193 li gp,14 -800002d0: 00000213 li tp,0 -800002d4: fcc00093 li ra,-52 -800002d8: 00002117 auipc sp,0x2 -800002dc: d2810113 addi sp,sp,-728 # 80002000 -800002e0: 00000013 nop -800002e4: 00000013 nop -800002e8: 00110123 sb ra,2(sp) -800002ec: 00210703 lb a4,2(sp) -800002f0: fcc00e93 li t4,-52 -800002f4: 21d71463 bne a4,t4,800004fc -800002f8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -800002fc: 00200293 li t0,2 -80000300: fc521ae3 bne tp,t0,800002d4 - -80000304 : -80000304: 00f00193 li gp,15 -80000308: 00000213 li tp,0 -8000030c: fbc00093 li ra,-68 -80000310: 00000013 nop -80000314: 00002117 auipc sp,0x2 -80000318: cec10113 addi sp,sp,-788 # 80002000 -8000031c: 001101a3 sb ra,3(sp) -80000320: 00310703 lb a4,3(sp) -80000324: fbc00e93 li t4,-68 -80000328: 1dd71a63 bne a4,t4,800004fc -8000032c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000330: 00200293 li t0,2 -80000334: fc521ce3 bne tp,t0,8000030c - -80000338 : -80000338: 01000193 li gp,16 -8000033c: 00000213 li tp,0 -80000340: fbb00093 li ra,-69 -80000344: 00000013 nop -80000348: 00002117 auipc sp,0x2 -8000034c: cb810113 addi sp,sp,-840 # 80002000 -80000350: 00000013 nop -80000354: 00110223 sb ra,4(sp) -80000358: 00410703 lb a4,4(sp) -8000035c: fbb00e93 li t4,-69 -80000360: 19d71e63 bne a4,t4,800004fc -80000364: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000368: 00200293 li t0,2 -8000036c: fc521ae3 bne tp,t0,80000340 - -80000370 : -80000370: 01100193 li gp,17 -80000374: 00000213 li tp,0 -80000378: fab00093 li ra,-85 -8000037c: 00000013 nop -80000380: 00000013 nop -80000384: 00002117 auipc sp,0x2 -80000388: c7c10113 addi sp,sp,-900 # 80002000 -8000038c: 001102a3 sb ra,5(sp) -80000390: 00510703 lb a4,5(sp) -80000394: fab00e93 li t4,-85 -80000398: 17d71263 bne a4,t4,800004fc -8000039c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -800003a0: 00200293 li t0,2 -800003a4: fc521ae3 bne tp,t0,80000378 - -800003a8 : -800003a8: 01200193 li gp,18 -800003ac: 00000213 li tp,0 -800003b0: 00002117 auipc sp,0x2 -800003b4: c5010113 addi sp,sp,-944 # 80002000 -800003b8: 03300093 li ra,51 -800003bc: 00110023 sb ra,0(sp) -800003c0: 00010703 lb a4,0(sp) -800003c4: 03300e93 li t4,51 -800003c8: 13d71a63 bne a4,t4,800004fc -800003cc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -800003d0: 00200293 li t0,2 -800003d4: fc521ee3 bne tp,t0,800003b0 - -800003d8 : -800003d8: 01300193 li gp,19 -800003dc: 00000213 li tp,0 -800003e0: 00002117 auipc sp,0x2 -800003e4: c2010113 addi sp,sp,-992 # 80002000 -800003e8: 02300093 li ra,35 -800003ec: 00000013 nop -800003f0: 001100a3 sb ra,1(sp) -800003f4: 00110703 lb a4,1(sp) -800003f8: 02300e93 li t4,35 -800003fc: 11d71063 bne a4,t4,800004fc -80000400: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000404: 00200293 li t0,2 -80000408: fc521ce3 bne tp,t0,800003e0 - -8000040c : -8000040c: 01400193 li gp,20 -80000410: 00000213 li tp,0 -80000414: 00002117 auipc sp,0x2 -80000418: bec10113 addi sp,sp,-1044 # 80002000 -8000041c: 02200093 li ra,34 -80000420: 00000013 nop -80000424: 00000013 nop -80000428: 00110123 sb ra,2(sp) -8000042c: 00210703 lb a4,2(sp) -80000430: 02200e93 li t4,34 -80000434: 0dd71463 bne a4,t4,800004fc -80000438: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -8000043c: 00200293 li t0,2 -80000440: fc521ae3 bne tp,t0,80000414 - -80000444 : -80000444: 01500193 li gp,21 -80000448: 00000213 li tp,0 -8000044c: 00002117 auipc sp,0x2 -80000450: bb410113 addi sp,sp,-1100 # 80002000 -80000454: 00000013 nop -80000458: 01200093 li ra,18 -8000045c: 001101a3 sb ra,3(sp) -80000460: 00310703 lb a4,3(sp) -80000464: 01200e93 li t4,18 -80000468: 09d71a63 bne a4,t4,800004fc -8000046c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000470: 00200293 li t0,2 -80000474: fc521ce3 bne tp,t0,8000044c - -80000478 : -80000478: 01600193 li gp,22 -8000047c: 00000213 li tp,0 -80000480: 00002117 auipc sp,0x2 -80000484: b8010113 addi sp,sp,-1152 # 80002000 -80000488: 00000013 nop -8000048c: 01100093 li ra,17 -80000490: 00000013 nop -80000494: 00110223 sb ra,4(sp) -80000498: 00410703 lb a4,4(sp) -8000049c: 01100e93 li t4,17 -800004a0: 05d71e63 bne a4,t4,800004fc -800004a4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -800004a8: 00200293 li t0,2 -800004ac: fc521ae3 bne tp,t0,80000480 - -800004b0 : -800004b0: 01700193 li gp,23 -800004b4: 00000213 li tp,0 -800004b8: 00002117 auipc sp,0x2 -800004bc: b4810113 addi sp,sp,-1208 # 80002000 -800004c0: 00000013 nop -800004c4: 00000013 nop -800004c8: 00100093 li ra,1 -800004cc: 001102a3 sb ra,5(sp) -800004d0: 00510703 lb a4,5(sp) -800004d4: 00100e93 li t4,1 -800004d8: 03d71263 bne a4,t4,800004fc -800004dc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -800004e0: 00200293 li t0,2 -800004e4: fc521ae3 bne tp,t0,800004b8 -800004e8: 0ef00513 li a0,239 -800004ec: 00002597 auipc a1,0x2 -800004f0: b1458593 addi a1,a1,-1260 # 80002000 -800004f4: 00a581a3 sb a0,3(a1) -800004f8: 02301063 bne zero,gp,80000518 - -800004fc : -800004fc: 0ff0000f fence -80000500: 00018063 beqz gp,80000500 -80000504: 00119193 slli gp,gp,0x1 -80000508: 0011e193 ori gp,gp,1 -8000050c: 05d00893 li a7,93 -80000510: 00018513 mv a0,gp -80000514: 00000073 ecall - -80000518 : -80000518: 0ff0000f fence -8000051c: 00100193 li gp,1 -80000520: 05d00893 li a7,93 -80000524: 00000513 li a0,0 -80000528: 00000073 ecall -8000052c: c0001073 unimp -80000530: 0000 unimp -80000532: 0000 unimp -80000534: 0000 unimp -80000536: 0000 unimp -80000538: 0000 unimp -8000053a: 0000 unimp -8000053c: 0000 unimp -8000053e: 0000 unimp -80000540: 0000 unimp -80000542: 0000 unimp - -Disassembly of section .data: - -80002000 : -80002000: jal t6,800006fe - -80002001 : -80002001: jal t6,800006ff - -80002002 : -80002002: jal t6,80000700 - -80002003 : -80002003: jal t6,80000701 - -80002004 : -80002004: jal t6,80000702 - -80002005 : -80002005: jal t6,80000703 - -80002006 : -80002006: jal t6,80000704 - -80002007 : -80002007: jal t6,80100015 <_end+0xfe005> - -80002008 : -80002008: jal t6,80010008 <_end+0xdff8> - -80002009 : -80002009: 000000ef jal ra,80002009 -8000200d: 0000 unimp -8000200f: 00 Address 0x000000008000200f is out of bounds. - diff --git a/benchmarks/riscv_tests/rv32ui-p-sb.hex b/benchmarks/riscv_tests/rv32ui-p-sb.hex deleted file mode 100644 index 5b83fec8..00000000 --- a/benchmarks/riscv_tests/rv32ui-p-sb.hex +++ /dev/null @@ -1,90 +0,0 @@ -:0200000480007A -:100000006F00C004732F2034930F8000630AFF0336 -:10001000930F90006306FF03930FB0006302FF038A -:10002000170F0080130F0FFE63040F0067000F000F -:10003000732F203463540F006F004000136E9E53E3 -:10004000171F00002320CFFD6FF09FFF732540F1A5 -:100050006310050073251030635805000F00F00F82 -:10006000130E100073000000130E00009702000032 -:10007000938282F973905230735020307350303035 -:1000800073504030970200809382C2F7638C020065 -:10009000739052109302B01A739022307323203061 -:1000A000E39E62F873500030970200009382420191 -:1000B00073901234732540F17300203097200000B4 -:1000C000938040F41301A0FA238020008381000074 -:1000D000930EA0FA130E2000639CD13D97200000E0 -:1000E000938040F213010000A38020008381100060 -:1000F000930E0000130E3000639CD13B972000004C -:10010000938040F037F1FFFF130101FA23812000B3 -:1001100083912000B7FEFFFF938E0EFA130E40006E -:100120006398D139972000009380C0ED1301A0009F -:10013000A381200083813000930EA000130E500095 -:100140006398D13797200000938030EC1301A0FA18 -:10015000A38E20FE8381D0FF930EA0FA130E6000C1 -:100160006398D13597200000938030EA1301000096 -:10017000238F20FE8381E0FF930E0000130E70009A -:100180006398D13397200000938030E8130100FA80 -:10019000A38F20FE8381F0FF930E00FA130E8000E0 -:1001A0006398D13197200000938030E61301A000BE -:1001B0002380200083810000930EA000130E900086 -:1001C0006398D12F97200000938040E43751341278 -:1001D00013018167138200FE230022028381000045 -:1001E000930E8007130EA0006394D12D972000007A -:1001F0009380C0E137310000130181099380A0FF93 -:10020000A383200017220000130252E083010200A2 -:10021000930E80F9130EB000639CD129130EC00019 -:10022000130200009300D0FD17210000130181DDAF -:100230002300110083010100930ED0FD639AD127A2 -:100240001302120093022000E31E52FC130ED00092 -:10025000130200009300D0FC17210000130181DA83 -:1002600013000000A300110083011100930ED0FCC5 -:100270006390D1251302120093022000E31C52FC6C -:10028000130EE000130200009300C0FC17210000D1 -:10029000130141D7130000001300000023011100D7 -:1002A00083012100930EC0FC6394D121130212003C -:1002B00093022000E31A52FC130EF0001302000018 -:1002C0009300C0FB1300000017210000130181D32D -:1002D000A301110083013100930EC0FB639AD11D6D -:1002E0001302120093022000E31C52FC130E0001C3 -:1002F000130200009300B0FB130000001721000060 -:10030000130141D0130000002302110083014100BA -:10031000930EB0FB639ED1191302120093022000CA -:10032000E31A52FC130E1001130200009300B0FAFE -:10033000130000001300000017210000130181CCFE -:10034000A302110083015100930EB0FA6392D117FA -:100350001302120093022000E31A52FC130E200134 -:1003600013020000172100001301C1C993003003DC -:100370002300110083010100930E3003639AD1130F -:100380001302120093022000E31E52FC130E3001F0 -:1003900013020000172100001301C1C693003002B0 -:1003A00013000000A300110083011100930E30021E -:1003B0006390D1111302120093022000E31C52FC3F -:1003C000130E40011302000017210000130181C326 -:1003D000930020021300000013000000230111000D -:1003E00083012100930E20026394D10D13021200A9 -:1003F00093022000E31A52FC130E50011302000076 -:1004000017210000130101C0130000009300200118 -:10041000A301110083013100930E2001639AD109D9 -:100420001302120093022000E31C52FC130E600121 -:1004300013020000172100001301C1BC13000000CB -:1004400093001001130000002302110083014100FA -:10045000930E1001639ED105130212009302200037 -:10046000E31A52FC130E7001130200001721000062 -:10047000130141B9130000001300000093001000A5 -:10048000A302110083015100930E10006392D10367 -:100490001302120093022000E31A52FC1305F00E1F -:1004A00097250000938505B6A381A500631CC001B4 -:1004B0000F00F00F63000E00131E1E00136E1E00CF -:1004C000730000000F00F00F130E10007300000007 -:1004D000731000C0000000000000000000000000D9 -:1004E000000000000000000000000000000000000C -:1004F00000000000000000000000000000000000FC -:0405000000000000F7 -:1010000000000000000000000000000000000000E0 -:1010100000000000000000000000000000000000D0 -:1010200000000000000000000000000000000000C0 -:1010300000000000000000000000000000000000B0 -:081040000000000000000000A8 -:10200000EFEFEFEFEFEFEFEFEFEF0000000000007A -:040000058000200057 -:00000001FF diff --git a/benchmarks/riscv_tests/rv32ui-p-sh.dump b/benchmarks/riscv_tests/rv32ui-p-sh.dump deleted file mode 100644 index 11bec70b..00000000 --- a/benchmarks/riscv_tests/rv32ui-p-sh.dump +++ /dev/null @@ -1,473 +0,0 @@ - -rv32ui-p-sh: file format elf32-littleriscv - - -Disassembly of section .text.init: - -80000000 <_start>: -80000000: 04c0006f j 8000004c - -80000004 : -80000004: 34202f73 csrr t5,mcause -80000008: 00800f93 li t6,8 -8000000c: 03ff0a63 beq t5,t6,80000040 -80000010: 00900f93 li t6,9 -80000014: 03ff0663 beq t5,t6,80000040 -80000018: 00b00f93 li t6,11 -8000001c: 03ff0263 beq t5,t6,80000040 -80000020: 80000f17 auipc t5,0x80000 -80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> -80000028: 000f0463 beqz t5,80000030 -8000002c: 000f0067 jr t5 -80000030: 34202f73 csrr t5,mcause -80000034: 000f5463 bgez t5,8000003c -80000038: 0040006f j 8000003c - -8000003c : -8000003c: 5391e193 ori gp,gp,1337 - -80000040 : -80000040: 00001f17 auipc t5,0x1 -80000044: fc3f2023 sw gp,-64(t5) # 80001000 -80000048: ff9ff06f j 80000040 - -8000004c : -8000004c: f1402573 csrr a0,mhartid -80000050: 00051063 bnez a0,80000050 -80000054: 00000297 auipc t0,0x0 -80000058: 01028293 addi t0,t0,16 # 80000064 -8000005c: 30529073 csrw mtvec,t0 -80000060: 18005073 csrwi satp,0 -80000064: 00000297 auipc t0,0x0 -80000068: 02028293 addi t0,t0,32 # 80000084 -8000006c: 30529073 csrw mtvec,t0 -80000070: 800002b7 lui t0,0x80000 -80000074: fff28293 addi t0,t0,-1 # 7fffffff <_end+0xffffdfdf> -80000078: 3b029073 csrw pmpaddr0,t0 -8000007c: 01f00293 li t0,31 -80000080: 3a029073 csrw pmpcfg0,t0 -80000084: 00000297 auipc t0,0x0 -80000088: 01828293 addi t0,t0,24 # 8000009c -8000008c: 30529073 csrw mtvec,t0 -80000090: 30205073 csrwi medeleg,0 -80000094: 30305073 csrwi mideleg,0 -80000098: 30405073 csrwi mie,0 -8000009c: 00000193 li gp,0 -800000a0: 00000297 auipc t0,0x0 -800000a4: f6428293 addi t0,t0,-156 # 80000004 -800000a8: 30529073 csrw mtvec,t0 -800000ac: 00100513 li a0,1 -800000b0: 01f51513 slli a0,a0,0x1f -800000b4: 00054c63 bltz a0,800000cc -800000b8: 0ff0000f fence -800000bc: 00100193 li gp,1 -800000c0: 05d00893 li a7,93 -800000c4: 00000513 li a0,0 -800000c8: 00000073 ecall -800000cc: 80000297 auipc t0,0x80000 -800000d0: f3428293 addi t0,t0,-204 # 0 <_start-0x80000000> -800000d4: 00028e63 beqz t0,800000f0 -800000d8: 10529073 csrw stvec,t0 -800000dc: 0000b2b7 lui t0,0xb -800000e0: 10928293 addi t0,t0,265 # b109 <_start-0x7fff4ef7> -800000e4: 30229073 csrw medeleg,t0 -800000e8: 30202373 csrr t1,medeleg -800000ec: f46298e3 bne t0,t1,8000003c -800000f0: 30005073 csrwi mstatus,0 -800000f4: 00000297 auipc t0,0x0 -800000f8: 01428293 addi t0,t0,20 # 80000108 -800000fc: 34129073 csrw mepc,t0 -80000100: f1402573 csrr a0,mhartid -80000104: 30200073 mret - -80000108 : -80000108: 00002097 auipc ra,0x2 -8000010c: ef808093 addi ra,ra,-264 # 80002000 -80000110: 0aa00113 li sp,170 -80000114: 00209023 sh sp,0(ra) -80000118: 00009703 lh a4,0(ra) -8000011c: 0aa00e93 li t4,170 -80000120: 00200193 li gp,2 -80000124: 45d71e63 bne a4,t4,80000580 - -80000128 : -80000128: 00002097 auipc ra,0x2 -8000012c: ed808093 addi ra,ra,-296 # 80002000 -80000130: ffffb137 lui sp,0xffffb -80000134: a0010113 addi sp,sp,-1536 # ffffaa00 <_end+0x7fff89e0> -80000138: 00209123 sh sp,2(ra) -8000013c: 00209703 lh a4,2(ra) -80000140: ffffbeb7 lui t4,0xffffb -80000144: a00e8e93 addi t4,t4,-1536 # ffffaa00 <_end+0x7fff89e0> -80000148: 00300193 li gp,3 -8000014c: 43d71a63 bne a4,t4,80000580 - -80000150 : -80000150: 00002097 auipc ra,0x2 -80000154: eb008093 addi ra,ra,-336 # 80002000 -80000158: beef1137 lui sp,0xbeef1 -8000015c: aa010113 addi sp,sp,-1376 # beef0aa0 <_end+0x3eeeea80> -80000160: 00209223 sh sp,4(ra) -80000164: 0040a703 lw a4,4(ra) -80000168: beef1eb7 lui t4,0xbeef1 -8000016c: aa0e8e93 addi t4,t4,-1376 # beef0aa0 <_end+0x3eeeea80> -80000170: 00400193 li gp,4 -80000174: 41d71663 bne a4,t4,80000580 - -80000178 : -80000178: 00002097 auipc ra,0x2 -8000017c: e8808093 addi ra,ra,-376 # 80002000 -80000180: ffffa137 lui sp,0xffffa -80000184: 00a10113 addi sp,sp,10 # ffffa00a <_end+0x7fff7fea> -80000188: 00209323 sh sp,6(ra) -8000018c: 00609703 lh a4,6(ra) -80000190: ffffaeb7 lui t4,0xffffa -80000194: 00ae8e93 addi t4,t4,10 # ffffa00a <_end+0x7fff7fea> -80000198: 00500193 li gp,5 -8000019c: 3fd71263 bne a4,t4,80000580 - -800001a0 : -800001a0: 00002097 auipc ra,0x2 -800001a4: e6e08093 addi ra,ra,-402 # 8000200e -800001a8: 0aa00113 li sp,170 -800001ac: fe209d23 sh sp,-6(ra) -800001b0: ffa09703 lh a4,-6(ra) -800001b4: 0aa00e93 li t4,170 -800001b8: 00600193 li gp,6 -800001bc: 3dd71263 bne a4,t4,80000580 - -800001c0 : -800001c0: 00002097 auipc ra,0x2 -800001c4: e4e08093 addi ra,ra,-434 # 8000200e -800001c8: ffffb137 lui sp,0xffffb -800001cc: a0010113 addi sp,sp,-1536 # ffffaa00 <_end+0x7fff89e0> -800001d0: fe209e23 sh sp,-4(ra) -800001d4: ffc09703 lh a4,-4(ra) -800001d8: ffffbeb7 lui t4,0xffffb -800001dc: a00e8e93 addi t4,t4,-1536 # ffffaa00 <_end+0x7fff89e0> -800001e0: 00700193 li gp,7 -800001e4: 39d71e63 bne a4,t4,80000580 - -800001e8 : -800001e8: 00002097 auipc ra,0x2 -800001ec: e2608093 addi ra,ra,-474 # 8000200e -800001f0: 00001137 lui sp,0x1 -800001f4: aa010113 addi sp,sp,-1376 # aa0 <_start-0x7ffff560> -800001f8: fe209f23 sh sp,-2(ra) -800001fc: ffe09703 lh a4,-2(ra) -80000200: 00001eb7 lui t4,0x1 -80000204: aa0e8e93 addi t4,t4,-1376 # aa0 <_start-0x7ffff560> -80000208: 00800193 li gp,8 -8000020c: 37d71a63 bne a4,t4,80000580 - -80000210 : -80000210: 00002097 auipc ra,0x2 -80000214: dfe08093 addi ra,ra,-514 # 8000200e -80000218: ffffa137 lui sp,0xffffa -8000021c: 00a10113 addi sp,sp,10 # ffffa00a <_end+0x7fff7fea> -80000220: 00209023 sh sp,0(ra) -80000224: 00009703 lh a4,0(ra) -80000228: ffffaeb7 lui t4,0xffffa -8000022c: 00ae8e93 addi t4,t4,10 # ffffa00a <_end+0x7fff7fea> -80000230: 00900193 li gp,9 -80000234: 35d71663 bne a4,t4,80000580 - -80000238 : -80000238: 00002097 auipc ra,0x2 -8000023c: dd808093 addi ra,ra,-552 # 80002010 -80000240: 12345137 lui sp,0x12345 -80000244: 67810113 addi sp,sp,1656 # 12345678 <_start-0x6dcba988> -80000248: fe008213 addi tp,ra,-32 -8000024c: 02221023 sh sp,32(tp) # 20 <_start-0x7fffffe0> -80000250: 00009283 lh t0,0(ra) -80000254: 00005eb7 lui t4,0x5 -80000258: 678e8e93 addi t4,t4,1656 # 5678 <_start-0x7fffa988> -8000025c: 00a00193 li gp,10 -80000260: 33d29063 bne t0,t4,80000580 - -80000264 : -80000264: 00002097 auipc ra,0x2 -80000268: dac08093 addi ra,ra,-596 # 80002010 -8000026c: 00003137 lui sp,0x3 -80000270: 09810113 addi sp,sp,152 # 3098 <_start-0x7fffcf68> -80000274: ffb08093 addi ra,ra,-5 -80000278: 002093a3 sh sp,7(ra) -8000027c: 00002217 auipc tp,0x2 -80000280: d9620213 addi tp,tp,-618 # 80002012 -80000284: 00021283 lh t0,0(tp) # 0 <_start-0x80000000> -80000288: 00003eb7 lui t4,0x3 -8000028c: 098e8e93 addi t4,t4,152 # 3098 <_start-0x7fffcf68> -80000290: 00b00193 li gp,11 -80000294: 2fd29663 bne t0,t4,80000580 - -80000298 : -80000298: 00c00193 li gp,12 -8000029c: 00000213 li tp,0 -800002a0: ffffd0b7 lui ra,0xffffd -800002a4: cdd08093 addi ra,ra,-803 # ffffccdd <_end+0x7fffacbd> -800002a8: 00002117 auipc sp,0x2 -800002ac: d5810113 addi sp,sp,-680 # 80002000 -800002b0: 00111023 sh ra,0(sp) -800002b4: 00011703 lh a4,0(sp) -800002b8: ffffdeb7 lui t4,0xffffd -800002bc: cdde8e93 addi t4,t4,-803 # ffffccdd <_end+0x7fffacbd> -800002c0: 2dd71063 bne a4,t4,80000580 -800002c4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -800002c8: 00200293 li t0,2 -800002cc: fc521ae3 bne tp,t0,800002a0 - -800002d0 : -800002d0: 00d00193 li gp,13 -800002d4: 00000213 li tp,0 -800002d8: ffffc0b7 lui ra,0xffffc -800002dc: ccd08093 addi ra,ra,-819 # ffffbccd <_end+0x7fff9cad> -800002e0: 00002117 auipc sp,0x2 -800002e4: d2010113 addi sp,sp,-736 # 80002000 -800002e8: 00000013 nop -800002ec: 00111123 sh ra,2(sp) -800002f0: 00211703 lh a4,2(sp) -800002f4: ffffceb7 lui t4,0xffffc -800002f8: ccde8e93 addi t4,t4,-819 # ffffbccd <_end+0x7fff9cad> -800002fc: 29d71263 bne a4,t4,80000580 -80000300: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000304: 00200293 li t0,2 -80000308: fc5218e3 bne tp,t0,800002d8 - -8000030c : -8000030c: 00e00193 li gp,14 -80000310: 00000213 li tp,0 -80000314: ffffc0b7 lui ra,0xffffc -80000318: bcc08093 addi ra,ra,-1076 # ffffbbcc <_end+0x7fff9bac> -8000031c: 00002117 auipc sp,0x2 -80000320: ce410113 addi sp,sp,-796 # 80002000 -80000324: 00000013 nop -80000328: 00000013 nop -8000032c: 00111223 sh ra,4(sp) -80000330: 00411703 lh a4,4(sp) -80000334: ffffceb7 lui t4,0xffffc -80000338: bcce8e93 addi t4,t4,-1076 # ffffbbcc <_end+0x7fff9bac> -8000033c: 25d71263 bne a4,t4,80000580 -80000340: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000344: 00200293 li t0,2 -80000348: fc5216e3 bne tp,t0,80000314 - -8000034c : -8000034c: 00f00193 li gp,15 -80000350: 00000213 li tp,0 -80000354: ffffb0b7 lui ra,0xffffb -80000358: bbc08093 addi ra,ra,-1092 # ffffabbc <_end+0x7fff8b9c> -8000035c: 00000013 nop -80000360: 00002117 auipc sp,0x2 -80000364: ca010113 addi sp,sp,-864 # 80002000 -80000368: 00111323 sh ra,6(sp) -8000036c: 00611703 lh a4,6(sp) -80000370: ffffbeb7 lui t4,0xffffb -80000374: bbce8e93 addi t4,t4,-1092 # ffffabbc <_end+0x7fff8b9c> -80000378: 21d71463 bne a4,t4,80000580 -8000037c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000380: 00200293 li t0,2 -80000384: fc5218e3 bne tp,t0,80000354 - -80000388 : -80000388: 01000193 li gp,16 -8000038c: 00000213 li tp,0 -80000390: ffffb0b7 lui ra,0xffffb -80000394: abb08093 addi ra,ra,-1349 # ffffaabb <_end+0x7fff8a9b> -80000398: 00000013 nop -8000039c: 00002117 auipc sp,0x2 -800003a0: c6410113 addi sp,sp,-924 # 80002000 -800003a4: 00000013 nop -800003a8: 00111423 sh ra,8(sp) -800003ac: 00811703 lh a4,8(sp) -800003b0: ffffbeb7 lui t4,0xffffb -800003b4: abbe8e93 addi t4,t4,-1349 # ffffaabb <_end+0x7fff8a9b> -800003b8: 1dd71463 bne a4,t4,80000580 -800003bc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -800003c0: 00200293 li t0,2 -800003c4: fc5216e3 bne tp,t0,80000390 - -800003c8 : -800003c8: 01100193 li gp,17 -800003cc: 00000213 li tp,0 -800003d0: ffffe0b7 lui ra,0xffffe -800003d4: aab08093 addi ra,ra,-1365 # ffffdaab <_end+0x7fffba8b> -800003d8: 00000013 nop -800003dc: 00000013 nop -800003e0: 00002117 auipc sp,0x2 -800003e4: c2010113 addi sp,sp,-992 # 80002000 -800003e8: 00111523 sh ra,10(sp) -800003ec: 00a11703 lh a4,10(sp) -800003f0: ffffeeb7 lui t4,0xffffe -800003f4: aabe8e93 addi t4,t4,-1365 # ffffdaab <_end+0x7fffba8b> -800003f8: 19d71463 bne a4,t4,80000580 -800003fc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000400: 00200293 li t0,2 -80000404: fc5216e3 bne tp,t0,800003d0 - -80000408 : -80000408: 01200193 li gp,18 -8000040c: 00000213 li tp,0 -80000410: 00002117 auipc sp,0x2 -80000414: bf010113 addi sp,sp,-1040 # 80002000 -80000418: 000020b7 lui ra,0x2 -8000041c: 23308093 addi ra,ra,563 # 2233 <_start-0x7fffddcd> -80000420: 00111023 sh ra,0(sp) -80000424: 00011703 lh a4,0(sp) -80000428: 00002eb7 lui t4,0x2 -8000042c: 233e8e93 addi t4,t4,563 # 2233 <_start-0x7fffddcd> -80000430: 15d71863 bne a4,t4,80000580 -80000434: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000438: 00200293 li t0,2 -8000043c: fc521ae3 bne tp,t0,80000410 - -80000440 : -80000440: 01300193 li gp,19 -80000444: 00000213 li tp,0 -80000448: 00002117 auipc sp,0x2 -8000044c: bb810113 addi sp,sp,-1096 # 80002000 -80000450: 000010b7 lui ra,0x1 -80000454: 22308093 addi ra,ra,547 # 1223 <_start-0x7fffeddd> -80000458: 00000013 nop -8000045c: 00111123 sh ra,2(sp) -80000460: 00211703 lh a4,2(sp) -80000464: 00001eb7 lui t4,0x1 -80000468: 223e8e93 addi t4,t4,547 # 1223 <_start-0x7fffeddd> -8000046c: 11d71a63 bne a4,t4,80000580 -80000470: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000474: 00200293 li t0,2 -80000478: fc5218e3 bne tp,t0,80000448 - -8000047c : -8000047c: 01400193 li gp,20 -80000480: 00000213 li tp,0 -80000484: 00002117 auipc sp,0x2 -80000488: b7c10113 addi sp,sp,-1156 # 80002000 -8000048c: 000010b7 lui ra,0x1 -80000490: 12208093 addi ra,ra,290 # 1122 <_start-0x7fffeede> -80000494: 00000013 nop -80000498: 00000013 nop -8000049c: 00111223 sh ra,4(sp) -800004a0: 00411703 lh a4,4(sp) -800004a4: 00001eb7 lui t4,0x1 -800004a8: 122e8e93 addi t4,t4,290 # 1122 <_start-0x7fffeede> -800004ac: 0dd71a63 bne a4,t4,80000580 -800004b0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -800004b4: 00200293 li t0,2 -800004b8: fc5216e3 bne tp,t0,80000484 - -800004bc : -800004bc: 01500193 li gp,21 -800004c0: 00000213 li tp,0 -800004c4: 00002117 auipc sp,0x2 -800004c8: b3c10113 addi sp,sp,-1220 # 80002000 -800004cc: 00000013 nop -800004d0: 11200093 li ra,274 -800004d4: 00111323 sh ra,6(sp) -800004d8: 00611703 lh a4,6(sp) -800004dc: 11200e93 li t4,274 -800004e0: 0bd71063 bne a4,t4,80000580 -800004e4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -800004e8: 00200293 li t0,2 -800004ec: fc521ce3 bne tp,t0,800004c4 - -800004f0 : -800004f0: 01600193 li gp,22 -800004f4: 00000213 li tp,0 -800004f8: 00002117 auipc sp,0x2 -800004fc: b0810113 addi sp,sp,-1272 # 80002000 -80000500: 00000013 nop -80000504: 01100093 li ra,17 -80000508: 00000013 nop -8000050c: 00111423 sh ra,8(sp) -80000510: 00811703 lh a4,8(sp) -80000514: 01100e93 li t4,17 -80000518: 07d71463 bne a4,t4,80000580 -8000051c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000520: 00200293 li t0,2 -80000524: fc521ae3 bne tp,t0,800004f8 - -80000528 : -80000528: 01700193 li gp,23 -8000052c: 00000213 li tp,0 -80000530: 00002117 auipc sp,0x2 -80000534: ad010113 addi sp,sp,-1328 # 80002000 -80000538: 00000013 nop -8000053c: 00000013 nop -80000540: 000030b7 lui ra,0x3 -80000544: 00108093 addi ra,ra,1 # 3001 <_start-0x7fffcfff> -80000548: 00111523 sh ra,10(sp) -8000054c: 00a11703 lh a4,10(sp) -80000550: 00003eb7 lui t4,0x3 -80000554: 001e8e93 addi t4,t4,1 # 3001 <_start-0x7fffcfff> -80000558: 03d71463 bne a4,t4,80000580 -8000055c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000560: 00200293 li t0,2 -80000564: fc5216e3 bne tp,t0,80000530 -80000568: 0000c537 lui a0,0xc -8000056c: eef50513 addi a0,a0,-273 # beef <_start-0x7fff4111> -80000570: 00002597 auipc a1,0x2 -80000574: a9058593 addi a1,a1,-1392 # 80002000 -80000578: 00a59323 sh a0,6(a1) -8000057c: 02301063 bne zero,gp,8000059c - -80000580 : -80000580: 0ff0000f fence -80000584: 00018063 beqz gp,80000584 -80000588: 00119193 slli gp,gp,0x1 -8000058c: 0011e193 ori gp,gp,1 -80000590: 05d00893 li a7,93 -80000594: 00018513 mv a0,gp -80000598: 00000073 ecall - -8000059c : -8000059c: 0ff0000f fence -800005a0: 00100193 li gp,1 -800005a4: 05d00893 li a7,93 -800005a8: 00000513 li a0,0 -800005ac: 00000073 ecall -800005b0: c0001073 unimp -800005b4: 0000 unimp -800005b6: 0000 unimp -800005b8: 0000 unimp -800005ba: 0000 unimp -800005bc: 0000 unimp -800005be: 0000 unimp -800005c0: 0000 unimp -800005c2: 0000 unimp - -Disassembly of section .data: - -80002000 : -80002000: jal t4,7fffd3ee <_start-0x2c12> - -80002002 : -80002002: jal t4,7fffd3f0 <_start-0x2c10> - -80002004 : -80002004: jal t4,7fffd3f2 <_start-0x2c0e> - -80002006 : -80002006: jal t4,7fffd3f4 <_start-0x2c0c> - -80002008 : -80002008: jal t4,7fffd3f6 <_start-0x2c0a> - -8000200a : -8000200a: jal t4,7fffd3f8 <_start-0x2c08> - -8000200c : -8000200c: jal t4,7fffd3fa <_start-0x2c06> - -8000200e : -8000200e: jal t4,7fffd3fc <_start-0x2c04> - -80002010 : -80002010: jal t4,7fffd3fe <_start-0x2c02> - -80002012 : -80002012: 0000beef jal t4,8000d012 <_end+0xaff2> -80002016: 0000 unimp -80002018: 0000 unimp -8000201a: 0000 unimp -8000201c: 0000 unimp -8000201e: 0000 unimp diff --git a/benchmarks/riscv_tests/rv32ui-p-sh.hex b/benchmarks/riscv_tests/rv32ui-p-sh.hex deleted file mode 100644 index b8ceb208..00000000 --- a/benchmarks/riscv_tests/rv32ui-p-sh.hex +++ /dev/null @@ -1,99 +0,0 @@ -:0200000480007A -:100000006F00C004732F2034930F8000630AFF0336 -:10001000930F90006306FF03930FB0006302FF038A -:10002000170F0080130F0FFE63040F0067000F000F -:10003000732F203463540F006F004000136E9E53E3 -:10004000171F00002320CFFD6FF09FFF732540F1A5 -:100050006310050073251030635805000F00F00F82 -:10006000130E100073000000130E00009702000032 -:10007000938282F973905230735020307350303035 -:1000800073504030970200809382C2F7638C020065 -:10009000739052109302B01A739022307323203061 -:1000A000E39E62F873500030970200009382420191 -:1000B00073901234732540F17300203097200000B4 -:1000C000938040F41301A00A239020008391000044 -:1000D000930EA00A130E2000639ED14597200000C6 -:1000E000938040F237B1FFFF130101A0239120005C -:1000F00083912000B7BEFFFF938E0EA0130E300039 -:10010000639AD143972000009380C0EF3711EFBE70 -:10011000130101AA2392200083A14000B71EEFBE65 -:10012000938E0EAA130E40006396D14197200000D3 -:10013000938040ED37A1FFFF1301A100239320001E -:1001400083916000B7AEFFFF938EAE00130E500098 -:100150006392D13F972000009380A0EB1301A00A87 -:10016000239D20FE8391A0FF930EA00A130E600032 -:100170006392D13D972000009380A0E937B1FFFF43 -:10018000130101A0239E20FE8391C0FFB7BEFFFF95 -:10019000938E0EA0130E7000639ED139972000003D -:1001A000938020E737110000130101AA239F20FE4E -:1001B0008391E0FFB71E0000938E0EAA130E8000FD -:1001C000639AD137972000009380A0E437A1FFFF06 -:1001D0001301A1002390200083910000B7AEFFFF20 -:1001E000938EAE00130E90006396D13597200000D9 -:1001F000938040E23751341213018167138200FE6D -:100200002310220283910000B75E0000938E8E6758 -:10021000130EA0006390D13397200000938080DFFD -:1002200037310000130181099380B0FFA3932000B0 -:1002300017220000130222DE83110200B73E0000E5 -:10024000938E8E09130EB0006396D12F130EC0004B -:1002500013020000B7D0FFFF9380D0CD172100001C -:10026000130141DA2310110083110100B7DEFFFFF3 -:10027000938EDECD6390D12D1302120093022000E5 -:10028000E31A52FC130ED00013020000B7C0FFFFA8 -:100290009380D0CC172100001301C1D613000000B9 -:1002A0002311110083112100B7CEFFFF938EDECC06 -:1002B0006392D1291302120093022000E31852FC2A -:1002C000130EE00013020000B7C0FFFF9380C0BC14 -:1002D00017210000130101D31300000013000000D8 -:1002E0002312110083114100B7CEFFFF938ECEBCC5 -:1002F0006392D1251302120093022000E31652FCF0 -:10030000130EF00013020000B7B0FFFF9380C0BBD4 -:1003100013000000172100001301C1CE23131100A8 -:1003200083116100B7BEFFFF938ECEBB6394D121D2 -:100330001302120093022000E31852FC130E000176 -:1003400013020000B7B0FFFF9380B0AB13000000B2 -:1003500017210000130101CB13000000231411002A -:1003600083118100B7BEFFFF938EBEAB6394D11D96 -:100370001302120093022000E31652FC130E100128 -:1003800013020000B7E0FFFF9380B0AA1300000043 -:1003900013000000172100001301C1C6231511002E -:1003A0008311A100B7EEFFFF938EBEAA6394D1190B -:1003B0001302120093022000E31652FC130E2001D8 -:1003C00013020000172100001301C1C3B720000071 -:1003D000938030232310110083110100B72E0000F9 -:1003E000938E3E236398D1151302120093022000CE -:1003F000E31A52FC130E3001130200001721000013 -:10040000130141C0B7100000938030221300000098 -:100410002311110083112100B71E0000938E3E228C -:10042000639AD1111302120093022000E31852FCC8 -:10043000130E40011302000017210000130181BCBC -:10044000B71000009380201213000000130000007A -:100450002312110083114100B71E0000938E2E124B -:10046000639AD10D1302120093022000E31652FC8E -:10047000130E50011302000017210000130181B870 -:100480001300000093002011231311008311610059 -:10049000930E20116390D10B1302120093022000DF -:1004A000E31C52FC130E6001130200001721000030 -:1004B000130141B513000000930010011300000068 -:1004C0002314110083118100930E10016394D1074E -:1004D0001302120093022000E31A52FC130E700163 -:1004E00013020000172100001301C1B11300000026 -:1004F00013000000B7300000938010002315110096 -:100500008311A100B73E0000938E1E006394D103B7 -:100510001302120093022000E31652FC37C50000BC -:100520001305F5EE972500009385C5AD2393A5002F -:10053000631CC0010F00F00F63000E00131E1E00AD -:10054000136E1E00730000000F00F00F130E10005A -:1005500073000000731000C00000000000000000E5 -:10056000000000000000000000000000000000008B -:10057000000000000000000000000000000000007B -:040580000000000077 -:1010000000000000000000000000000000000000E0 -:1010100000000000000000000000000000000000D0 -:1010200000000000000000000000000000000000C0 -:1010300000000000000000000000000000000000B0 -:081040000000000000000000A8 -:10200000EFBEEFBEEFBEEFBEEFBEEFBEEFBEEFBE68 -:10201000EFBEEFBE00000000000000000000000066 -:040000058000200057 -:00000001FF diff --git a/benchmarks/riscv_tests/rv32ui-p-simple.dump b/benchmarks/riscv_tests/rv32ui-p-simple.dump deleted file mode 100644 index 4ef40215..00000000 --- a/benchmarks/riscv_tests/rv32ui-p-simple.dump +++ /dev/null @@ -1,105 +0,0 @@ - -rv32ui-p-simple: file format elf32-littleriscv - - -Disassembly of section .text.init: - -80000000 <_start>: -80000000: 04c0006f j 8000004c - -80000004 : -80000004: 34202f73 csrr t5,mcause -80000008: 00800f93 li t6,8 -8000000c: 03ff0a63 beq t5,t6,80000040 -80000010: 00900f93 li t6,9 -80000014: 03ff0663 beq t5,t6,80000040 -80000018: 00b00f93 li t6,11 -8000001c: 03ff0263 beq t5,t6,80000040 -80000020: 80000f17 auipc t5,0x80000 -80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> -80000028: 000f0463 beqz t5,80000030 -8000002c: 000f0067 jr t5 -80000030: 34202f73 csrr t5,mcause -80000034: 000f5463 bgez t5,8000003c -80000038: 0040006f j 8000003c - -8000003c : -8000003c: 5391e193 ori gp,gp,1337 - -80000040 : -80000040: 00001f17 auipc t5,0x1 -80000044: fc3f2023 sw gp,-64(t5) # 80001000 -80000048: ff9ff06f j 80000040 - -8000004c : -8000004c: f1402573 csrr a0,mhartid -80000050: 00051063 bnez a0,80000050 -80000054: 00000297 auipc t0,0x0 -80000058: 01028293 addi t0,t0,16 # 80000064 -8000005c: 30529073 csrw mtvec,t0 -80000060: 18005073 csrwi satp,0 -80000064: 00000297 auipc t0,0x0 -80000068: 02028293 addi t0,t0,32 # 80000084 -8000006c: 30529073 csrw mtvec,t0 -80000070: 800002b7 lui t0,0x80000 -80000074: fff28293 addi t0,t0,-1 # 7fffffff <_end+0xffffdfff> -80000078: 3b029073 csrw pmpaddr0,t0 -8000007c: 01f00293 li t0,31 -80000080: 3a029073 csrw pmpcfg0,t0 -80000084: 00000297 auipc t0,0x0 -80000088: 01828293 addi t0,t0,24 # 8000009c -8000008c: 30529073 csrw mtvec,t0 -80000090: 30205073 csrwi medeleg,0 -80000094: 30305073 csrwi mideleg,0 -80000098: 30405073 csrwi mie,0 -8000009c: 00000193 li gp,0 -800000a0: 00000297 auipc t0,0x0 -800000a4: f6428293 addi t0,t0,-156 # 80000004 -800000a8: 30529073 csrw mtvec,t0 -800000ac: 00100513 li a0,1 -800000b0: 01f51513 slli a0,a0,0x1f -800000b4: 00054c63 bltz a0,800000cc -800000b8: 0ff0000f fence -800000bc: 00100193 li gp,1 -800000c0: 05d00893 li a7,93 -800000c4: 00000513 li a0,0 -800000c8: 00000073 ecall -800000cc: 80000297 auipc t0,0x80000 -800000d0: f3428293 addi t0,t0,-204 # 0 <_start-0x80000000> -800000d4: 00028e63 beqz t0,800000f0 -800000d8: 10529073 csrw stvec,t0 -800000dc: 0000b2b7 lui t0,0xb -800000e0: 10928293 addi t0,t0,265 # b109 <_start-0x7fff4ef7> -800000e4: 30229073 csrw medeleg,t0 -800000e8: 30202373 csrr t1,medeleg -800000ec: f46298e3 bne t0,t1,8000003c -800000f0: 30005073 csrwi mstatus,0 -800000f4: 00000297 auipc t0,0x0 -800000f8: 01428293 addi t0,t0,20 # 80000108 -800000fc: 34129073 csrw mepc,t0 -80000100: f1402573 csrr a0,mhartid -80000104: 30200073 mret -80000108: 0ff0000f fence -8000010c: 00100193 li gp,1 -80000110: 05d00893 li a7,93 -80000114: 00000513 li a0,0 -80000118: 00000073 ecall -8000011c: c0001073 unimp -80000120: 0000 unimp -80000122: 0000 unimp -80000124: 0000 unimp -80000126: 0000 unimp -80000128: 0000 unimp -8000012a: 0000 unimp -8000012c: 0000 unimp -8000012e: 0000 unimp -80000130: 0000 unimp -80000132: 0000 unimp -80000134: 0000 unimp -80000136: 0000 unimp -80000138: 0000 unimp -8000013a: 0000 unimp -8000013c: 0000 unimp -8000013e: 0000 unimp -80000140: 0000 unimp -80000142: 0000 unimp diff --git a/benchmarks/riscv_tests/rv32ui-p-simple.hex b/benchmarks/riscv_tests/rv32ui-p-simple.hex deleted file mode 100644 index 018e25ac..00000000 --- a/benchmarks/riscv_tests/rv32ui-p-simple.hex +++ /dev/null @@ -1,25 +0,0 @@ -:0200000480007A -:100000006F00C004732F2034930F8000630AFF0336 -:10001000930F90006306FF03930FB0006302FF038A -:10002000170F0080130F0FFE63040F0067000F000F -:10003000732F203463540F006F004000136E9E53E3 -:10004000171F00002320CFFD6FF09FFF732540F1A5 -:100050006310050073251030635805000F00F00F82 -:10006000130E100073000000130E00009702000032 -:10007000938282F973905230735020307350303035 -:1000800073504030970200809382C2F7638C020065 -:10009000739052109302B01A739022307323203061 -:1000A000E39E62F873500030970200009382420191 -:1000B00073901234732540F1730020300F00F00F5D -:1000C000130E100073000000731000C00000000049 -:1000D0000000000000000000000000000000000020 -:1000E0000000000000000000000000000000000010 -:1000F0000000000000000000000000000000000000 -:0401000000000000FB -:1010000000000000000000000000000000000000E0 -:1010100000000000000000000000000000000000D0 -:1010200000000000000000000000000000000000C0 -:1010300000000000000000000000000000000000B0 -:081040000000000000000000A8 -:040000058000200057 -:00000001FF diff --git a/benchmarks/riscv_tests/rv32ui-p-sll.dump b/benchmarks/riscv_tests/rv32ui-p-sll.dump deleted file mode 100644 index 8406695d..00000000 --- a/benchmarks/riscv_tests/rv32ui-p-sll.dump +++ /dev/null @@ -1,548 +0,0 @@ - -rv32ui-p-sll: file format elf32-littleriscv - - -Disassembly of section .text.init: - -80000000 <_start>: -80000000: 04c0006f j 8000004c - -80000004 : -80000004: 34202f73 csrr t5,mcause -80000008: 00800f93 li t6,8 -8000000c: 03ff0a63 beq t5,t6,80000040 -80000010: 00900f93 li t6,9 -80000014: 03ff0663 beq t5,t6,80000040 -80000018: 00b00f93 li t6,11 -8000001c: 03ff0263 beq t5,t6,80000040 -80000020: 80000f17 auipc t5,0x80000 -80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> -80000028: 000f0463 beqz t5,80000030 -8000002c: 000f0067 jr t5 -80000030: 34202f73 csrr t5,mcause -80000034: 000f5463 bgez t5,8000003c -80000038: 0040006f j 8000003c - -8000003c : -8000003c: 5391e193 ori gp,gp,1337 - -80000040 : -80000040: 00001f17 auipc t5,0x1 -80000044: fc3f2023 sw gp,-64(t5) # 80001000 -80000048: ff9ff06f j 80000040 - -8000004c : -8000004c: f1402573 csrr a0,mhartid -80000050: 00051063 bnez a0,80000050 -80000054: 00000297 auipc t0,0x0 -80000058: 01028293 addi t0,t0,16 # 80000064 -8000005c: 30529073 csrw mtvec,t0 -80000060: 18005073 csrwi satp,0 -80000064: 00000297 auipc t0,0x0 -80000068: 02028293 addi t0,t0,32 # 80000084 -8000006c: 30529073 csrw mtvec,t0 -80000070: 800002b7 lui t0,0x80000 -80000074: fff28293 addi t0,t0,-1 # 7fffffff <_end+0xffffdfff> -80000078: 3b029073 csrw pmpaddr0,t0 -8000007c: 01f00293 li t0,31 -80000080: 3a029073 csrw pmpcfg0,t0 -80000084: 00000297 auipc t0,0x0 -80000088: 01828293 addi t0,t0,24 # 8000009c -8000008c: 30529073 csrw mtvec,t0 -80000090: 30205073 csrwi medeleg,0 -80000094: 30305073 csrwi mideleg,0 -80000098: 30405073 csrwi mie,0 -8000009c: 00000193 li gp,0 -800000a0: 00000297 auipc t0,0x0 -800000a4: f6428293 addi t0,t0,-156 # 80000004 -800000a8: 30529073 csrw mtvec,t0 -800000ac: 00100513 li a0,1 -800000b0: 01f51513 slli a0,a0,0x1f -800000b4: 00054c63 bltz a0,800000cc -800000b8: 0ff0000f fence -800000bc: 00100193 li gp,1 -800000c0: 05d00893 li a7,93 -800000c4: 00000513 li a0,0 -800000c8: 00000073 ecall -800000cc: 80000297 auipc t0,0x80000 -800000d0: f3428293 addi t0,t0,-204 # 0 <_start-0x80000000> -800000d4: 00028e63 beqz t0,800000f0 -800000d8: 10529073 csrw stvec,t0 -800000dc: 0000b2b7 lui t0,0xb -800000e0: 10928293 addi t0,t0,265 # b109 <_start-0x7fff4ef7> -800000e4: 30229073 csrw medeleg,t0 -800000e8: 30202373 csrr t1,medeleg -800000ec: f46298e3 bne t0,t1,8000003c -800000f0: 30005073 csrwi mstatus,0 -800000f4: 00000297 auipc t0,0x0 -800000f8: 01428293 addi t0,t0,20 # 80000108 -800000fc: 34129073 csrw mepc,t0 -80000100: f1402573 csrr a0,mhartid -80000104: 30200073 mret - -80000108 : -80000108: 00100093 li ra,1 -8000010c: 00000113 li sp,0 -80000110: 00209733 sll a4,ra,sp -80000114: 00100e93 li t4,1 -80000118: 00200193 li gp,2 -8000011c: 53d71e63 bne a4,t4,80000658 - -80000120 : -80000120: 00100093 li ra,1 -80000124: 00100113 li sp,1 -80000128: 00209733 sll a4,ra,sp -8000012c: 00200e93 li t4,2 -80000130: 00300193 li gp,3 -80000134: 53d71263 bne a4,t4,80000658 - -80000138 : -80000138: 00100093 li ra,1 -8000013c: 00700113 li sp,7 -80000140: 00209733 sll a4,ra,sp -80000144: 08000e93 li t4,128 -80000148: 00400193 li gp,4 -8000014c: 51d71663 bne a4,t4,80000658 - -80000150 : -80000150: 00100093 li ra,1 -80000154: 00e00113 li sp,14 -80000158: 00209733 sll a4,ra,sp -8000015c: 00004eb7 lui t4,0x4 -80000160: 00500193 li gp,5 -80000164: 4fd71a63 bne a4,t4,80000658 - -80000168 : -80000168: 00100093 li ra,1 -8000016c: 01f00113 li sp,31 -80000170: 00209733 sll a4,ra,sp -80000174: 80000eb7 lui t4,0x80000 -80000178: 00600193 li gp,6 -8000017c: 4dd71e63 bne a4,t4,80000658 - -80000180 : -80000180: fff00093 li ra,-1 -80000184: 00000113 li sp,0 -80000188: 00209733 sll a4,ra,sp -8000018c: fff00e93 li t4,-1 -80000190: 00700193 li gp,7 -80000194: 4dd71263 bne a4,t4,80000658 - -80000198 : -80000198: fff00093 li ra,-1 -8000019c: 00100113 li sp,1 -800001a0: 00209733 sll a4,ra,sp -800001a4: ffe00e93 li t4,-2 -800001a8: 00800193 li gp,8 -800001ac: 4bd71663 bne a4,t4,80000658 - -800001b0 : -800001b0: fff00093 li ra,-1 -800001b4: 00700113 li sp,7 -800001b8: 00209733 sll a4,ra,sp -800001bc: f8000e93 li t4,-128 -800001c0: 00900193 li gp,9 -800001c4: 49d71a63 bne a4,t4,80000658 - -800001c8 : -800001c8: fff00093 li ra,-1 -800001cc: 00e00113 li sp,14 -800001d0: 00209733 sll a4,ra,sp -800001d4: ffffceb7 lui t4,0xffffc -800001d8: 00a00193 li gp,10 -800001dc: 47d71e63 bne a4,t4,80000658 - -800001e0 : -800001e0: fff00093 li ra,-1 -800001e4: 01f00113 li sp,31 -800001e8: 00209733 sll a4,ra,sp -800001ec: 80000eb7 lui t4,0x80000 -800001f0: 00b00193 li gp,11 -800001f4: 47d71263 bne a4,t4,80000658 - -800001f8 : -800001f8: 212120b7 lui ra,0x21212 -800001fc: 12108093 addi ra,ra,289 # 21212121 <_start-0x5edededf> -80000200: 00000113 li sp,0 -80000204: 00209733 sll a4,ra,sp -80000208: 21212eb7 lui t4,0x21212 -8000020c: 121e8e93 addi t4,t4,289 # 21212121 <_start-0x5edededf> -80000210: 00c00193 li gp,12 -80000214: 45d71263 bne a4,t4,80000658 - -80000218 : -80000218: 212120b7 lui ra,0x21212 -8000021c: 12108093 addi ra,ra,289 # 21212121 <_start-0x5edededf> -80000220: 00100113 li sp,1 -80000224: 00209733 sll a4,ra,sp -80000228: 42424eb7 lui t4,0x42424 -8000022c: 242e8e93 addi t4,t4,578 # 42424242 <_start-0x3dbdbdbe> -80000230: 00d00193 li gp,13 -80000234: 43d71263 bne a4,t4,80000658 - -80000238 : -80000238: 212120b7 lui ra,0x21212 -8000023c: 12108093 addi ra,ra,289 # 21212121 <_start-0x5edededf> -80000240: 00700113 li sp,7 -80000244: 00209733 sll a4,ra,sp -80000248: 90909eb7 lui t4,0x90909 -8000024c: 080e8e93 addi t4,t4,128 # 90909080 <_end+0x10907080> -80000250: 00e00193 li gp,14 -80000254: 41d71263 bne a4,t4,80000658 - -80000258 : -80000258: 212120b7 lui ra,0x21212 -8000025c: 12108093 addi ra,ra,289 # 21212121 <_start-0x5edededf> -80000260: 00e00113 li sp,14 -80000264: 00209733 sll a4,ra,sp -80000268: 48484eb7 lui t4,0x48484 -8000026c: 00f00193 li gp,15 -80000270: 3fd71463 bne a4,t4,80000658 - -80000274 : -80000274: 212120b7 lui ra,0x21212 -80000278: 12108093 addi ra,ra,289 # 21212121 <_start-0x5edededf> -8000027c: 01f00113 li sp,31 -80000280: 00209733 sll a4,ra,sp -80000284: 80000eb7 lui t4,0x80000 -80000288: 01000193 li gp,16 -8000028c: 3dd71663 bne a4,t4,80000658 - -80000290 : -80000290: 212120b7 lui ra,0x21212 -80000294: 12108093 addi ra,ra,289 # 21212121 <_start-0x5edededf> -80000298: fc000113 li sp,-64 -8000029c: 00209733 sll a4,ra,sp -800002a0: 21212eb7 lui t4,0x21212 -800002a4: 121e8e93 addi t4,t4,289 # 21212121 <_start-0x5edededf> -800002a8: 01100193 li gp,17 -800002ac: 3bd71663 bne a4,t4,80000658 - -800002b0 : -800002b0: 212120b7 lui ra,0x21212 -800002b4: 12108093 addi ra,ra,289 # 21212121 <_start-0x5edededf> -800002b8: fc100113 li sp,-63 -800002bc: 00209733 sll a4,ra,sp -800002c0: 42424eb7 lui t4,0x42424 -800002c4: 242e8e93 addi t4,t4,578 # 42424242 <_start-0x3dbdbdbe> -800002c8: 01200193 li gp,18 -800002cc: 39d71663 bne a4,t4,80000658 - -800002d0 : -800002d0: 212120b7 lui ra,0x21212 -800002d4: 12108093 addi ra,ra,289 # 21212121 <_start-0x5edededf> -800002d8: fc700113 li sp,-57 -800002dc: 00209733 sll a4,ra,sp -800002e0: 90909eb7 lui t4,0x90909 -800002e4: 080e8e93 addi t4,t4,128 # 90909080 <_end+0x10907080> -800002e8: 01300193 li gp,19 -800002ec: 37d71663 bne a4,t4,80000658 - -800002f0 : -800002f0: 212120b7 lui ra,0x21212 -800002f4: 12108093 addi ra,ra,289 # 21212121 <_start-0x5edededf> -800002f8: fce00113 li sp,-50 -800002fc: 00209733 sll a4,ra,sp -80000300: 48484eb7 lui t4,0x48484 -80000304: 01400193 li gp,20 -80000308: 35d71863 bne a4,t4,80000658 - -8000030c : -8000030c: 00100093 li ra,1 -80000310: 00700113 li sp,7 -80000314: 002090b3 sll ra,ra,sp -80000318: 08000e93 li t4,128 -8000031c: 01600193 li gp,22 -80000320: 33d09c63 bne ra,t4,80000658 - -80000324 : -80000324: 00100093 li ra,1 -80000328: 00e00113 li sp,14 -8000032c: 00209133 sll sp,ra,sp -80000330: 00004eb7 lui t4,0x4 -80000334: 01700193 li gp,23 -80000338: 33d11063 bne sp,t4,80000658 - -8000033c : -8000033c: 00300093 li ra,3 -80000340: 001090b3 sll ra,ra,ra -80000344: 01800e93 li t4,24 -80000348: 01800193 li gp,24 -8000034c: 31d09663 bne ra,t4,80000658 - -80000350 : -80000350: 00000213 li tp,0 -80000354: 00100093 li ra,1 -80000358: 00700113 li sp,7 -8000035c: 00209733 sll a4,ra,sp -80000360: 00070313 mv t1,a4 -80000364: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000368: 00200293 li t0,2 -8000036c: fe5214e3 bne tp,t0,80000354 -80000370: 08000e93 li t4,128 -80000374: 01900193 li gp,25 -80000378: 2fd31063 bne t1,t4,80000658 - -8000037c : -8000037c: 00000213 li tp,0 -80000380: 00100093 li ra,1 -80000384: 00e00113 li sp,14 -80000388: 00209733 sll a4,ra,sp -8000038c: 00000013 nop -80000390: 00070313 mv t1,a4 -80000394: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000398: 00200293 li t0,2 -8000039c: fe5212e3 bne tp,t0,80000380 -800003a0: 00004eb7 lui t4,0x4 -800003a4: 01a00193 li gp,26 -800003a8: 2bd31863 bne t1,t4,80000658 - -800003ac : -800003ac: 00000213 li tp,0 -800003b0: 00100093 li ra,1 -800003b4: 01f00113 li sp,31 -800003b8: 00209733 sll a4,ra,sp -800003bc: 00000013 nop -800003c0: 00000013 nop -800003c4: 00070313 mv t1,a4 -800003c8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -800003cc: 00200293 li t0,2 -800003d0: fe5210e3 bne tp,t0,800003b0 -800003d4: 80000eb7 lui t4,0x80000 -800003d8: 01b00193 li gp,27 -800003dc: 27d31e63 bne t1,t4,80000658 - -800003e0 : -800003e0: 00000213 li tp,0 -800003e4: 00100093 li ra,1 -800003e8: 00700113 li sp,7 -800003ec: 00209733 sll a4,ra,sp -800003f0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -800003f4: 00200293 li t0,2 -800003f8: fe5216e3 bne tp,t0,800003e4 -800003fc: 08000e93 li t4,128 -80000400: 01c00193 li gp,28 -80000404: 25d71a63 bne a4,t4,80000658 - -80000408 : -80000408: 00000213 li tp,0 -8000040c: 00100093 li ra,1 -80000410: 00e00113 li sp,14 -80000414: 00000013 nop -80000418: 00209733 sll a4,ra,sp -8000041c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000420: 00200293 li t0,2 -80000424: fe5214e3 bne tp,t0,8000040c -80000428: 00004eb7 lui t4,0x4 -8000042c: 01d00193 li gp,29 -80000430: 23d71463 bne a4,t4,80000658 - -80000434 : -80000434: 00000213 li tp,0 -80000438: 00100093 li ra,1 -8000043c: 01f00113 li sp,31 -80000440: 00000013 nop -80000444: 00000013 nop -80000448: 00209733 sll a4,ra,sp -8000044c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000450: 00200293 li t0,2 -80000454: fe5212e3 bne tp,t0,80000438 -80000458: 80000eb7 lui t4,0x80000 -8000045c: 01e00193 li gp,30 -80000460: 1fd71c63 bne a4,t4,80000658 - -80000464 : -80000464: 00000213 li tp,0 -80000468: 00100093 li ra,1 -8000046c: 00000013 nop -80000470: 00700113 li sp,7 -80000474: 00209733 sll a4,ra,sp -80000478: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -8000047c: 00200293 li t0,2 -80000480: fe5214e3 bne tp,t0,80000468 -80000484: 08000e93 li t4,128 -80000488: 01f00193 li gp,31 -8000048c: 1dd71663 bne a4,t4,80000658 - -80000490 : -80000490: 00000213 li tp,0 -80000494: 00100093 li ra,1 -80000498: 00000013 nop -8000049c: 00e00113 li sp,14 -800004a0: 00000013 nop -800004a4: 00209733 sll a4,ra,sp -800004a8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -800004ac: 00200293 li t0,2 -800004b0: fe5212e3 bne tp,t0,80000494 -800004b4: 00004eb7 lui t4,0x4 -800004b8: 02000193 li gp,32 -800004bc: 19d71e63 bne a4,t4,80000658 - -800004c0 : -800004c0: 00000213 li tp,0 -800004c4: 00100093 li ra,1 -800004c8: 00000013 nop -800004cc: 00000013 nop -800004d0: 01f00113 li sp,31 -800004d4: 00209733 sll a4,ra,sp -800004d8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -800004dc: 00200293 li t0,2 -800004e0: fe5212e3 bne tp,t0,800004c4 -800004e4: 80000eb7 lui t4,0x80000 -800004e8: 02100193 li gp,33 -800004ec: 17d71663 bne a4,t4,80000658 - -800004f0 : -800004f0: 00000213 li tp,0 -800004f4: 00700113 li sp,7 -800004f8: 00100093 li ra,1 -800004fc: 00209733 sll a4,ra,sp -80000500: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000504: 00200293 li t0,2 -80000508: fe5216e3 bne tp,t0,800004f4 -8000050c: 08000e93 li t4,128 -80000510: 02200193 li gp,34 -80000514: 15d71263 bne a4,t4,80000658 - -80000518 : -80000518: 00000213 li tp,0 -8000051c: 00e00113 li sp,14 -80000520: 00100093 li ra,1 -80000524: 00000013 nop -80000528: 00209733 sll a4,ra,sp -8000052c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000530: 00200293 li t0,2 -80000534: fe5214e3 bne tp,t0,8000051c -80000538: 00004eb7 lui t4,0x4 -8000053c: 02300193 li gp,35 -80000540: 11d71c63 bne a4,t4,80000658 - -80000544 : -80000544: 00000213 li tp,0 -80000548: 01f00113 li sp,31 -8000054c: 00100093 li ra,1 -80000550: 00000013 nop -80000554: 00000013 nop -80000558: 00209733 sll a4,ra,sp -8000055c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000560: 00200293 li t0,2 -80000564: fe5212e3 bne tp,t0,80000548 -80000568: 80000eb7 lui t4,0x80000 -8000056c: 02400193 li gp,36 -80000570: 0fd71463 bne a4,t4,80000658 - -80000574 : -80000574: 00000213 li tp,0 -80000578: 00700113 li sp,7 -8000057c: 00000013 nop -80000580: 00100093 li ra,1 -80000584: 00209733 sll a4,ra,sp -80000588: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -8000058c: 00200293 li t0,2 -80000590: fe5214e3 bne tp,t0,80000578 -80000594: 08000e93 li t4,128 -80000598: 02500193 li gp,37 -8000059c: 0bd71e63 bne a4,t4,80000658 - -800005a0 : -800005a0: 00000213 li tp,0 -800005a4: 00e00113 li sp,14 -800005a8: 00000013 nop -800005ac: 00100093 li ra,1 -800005b0: 00000013 nop -800005b4: 00209733 sll a4,ra,sp -800005b8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -800005bc: 00200293 li t0,2 -800005c0: fe5212e3 bne tp,t0,800005a4 -800005c4: 00004eb7 lui t4,0x4 -800005c8: 02600193 li gp,38 -800005cc: 09d71663 bne a4,t4,80000658 - -800005d0 : -800005d0: 00000213 li tp,0 -800005d4: 01f00113 li sp,31 -800005d8: 00000013 nop -800005dc: 00000013 nop -800005e0: 00100093 li ra,1 -800005e4: 00209733 sll a4,ra,sp -800005e8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -800005ec: 00200293 li t0,2 -800005f0: fe5212e3 bne tp,t0,800005d4 -800005f4: 80000eb7 lui t4,0x80000 -800005f8: 02700193 li gp,39 -800005fc: 05d71e63 bne a4,t4,80000658 - -80000600 : -80000600: 00f00093 li ra,15 -80000604: 00101133 sll sp,zero,ra -80000608: 00000e93 li t4,0 -8000060c: 02800193 li gp,40 -80000610: 05d11463 bne sp,t4,80000658 - -80000614 : -80000614: 02000093 li ra,32 -80000618: 00009133 sll sp,ra,zero -8000061c: 02000e93 li t4,32 -80000620: 02900193 li gp,41 -80000624: 03d11a63 bne sp,t4,80000658 - -80000628 : -80000628: 000010b3 sll ra,zero,zero -8000062c: 00000e93 li t4,0 -80000630: 02a00193 li gp,42 -80000634: 03d09263 bne ra,t4,80000658 - -80000638 : -80000638: 40000093 li ra,1024 -8000063c: 00001137 lui sp,0x1 -80000640: 80010113 addi sp,sp,-2048 # 800 <_start-0x7ffff800> -80000644: 00209033 sll zero,ra,sp -80000648: 00000e93 li t4,0 -8000064c: 02b00193 li gp,43 -80000650: 01d01463 bne zero,t4,80000658 -80000654: 02301063 bne zero,gp,80000674 - -80000658 : -80000658: 0ff0000f fence -8000065c: 00018063 beqz gp,8000065c -80000660: 00119193 slli gp,gp,0x1 -80000664: 0011e193 ori gp,gp,1 -80000668: 05d00893 li a7,93 -8000066c: 00018513 mv a0,gp -80000670: 00000073 ecall - -80000674 : -80000674: 0ff0000f fence -80000678: 00100193 li gp,1 -8000067c: 05d00893 li a7,93 -80000680: 00000513 li a0,0 -80000684: 00000073 ecall -80000688: c0001073 unimp -8000068c: 0000 unimp -8000068e: 0000 unimp -80000690: 0000 unimp -80000692: 0000 unimp -80000694: 0000 unimp -80000696: 0000 unimp -80000698: 0000 unimp -8000069a: 0000 unimp -8000069c: 0000 unimp -8000069e: 0000 unimp -800006a0: 0000 unimp -800006a2: 0000 unimp -800006a4: 0000 unimp -800006a6: 0000 unimp -800006a8: 0000 unimp -800006aa: 0000 unimp -800006ac: 0000 unimp -800006ae: 0000 unimp -800006b0: 0000 unimp -800006b2: 0000 unimp -800006b4: 0000 unimp -800006b6: 0000 unimp -800006b8: 0000 unimp -800006ba: 0000 unimp -800006bc: 0000 unimp -800006be: 0000 unimp -800006c0: 0000 unimp -800006c2: 0000 unimp diff --git a/benchmarks/riscv_tests/rv32ui-p-sll.hex b/benchmarks/riscv_tests/rv32ui-p-sll.hex deleted file mode 100644 index 9fdbf4a9..00000000 --- a/benchmarks/riscv_tests/rv32ui-p-sll.hex +++ /dev/null @@ -1,109 +0,0 @@ -:0200000480007A -:100000006F00C004732F2034930F8000630AFF0336 -:10001000930F90006306FF03930FB0006302FF038A -:10002000170F0080130F0FFE63040F0067000F000F -:10003000732F203463540F006F004000136E9E53E3 -:10004000171F00002320CFFD6FF09FFF732540F1A5 -:100050006310050073251030635805000F00F00F82 -:10006000130E100073000000130E00009702000032 -:10007000938282F973905230735020307350303035 -:1000800073504030970200809382C2F7638C020065 -:10009000739052109302B01A739022307323203061 -:1000A000E39E62F873500030970200009382420191 -:1000B00073901234732540F17300203093001000C8 -:1000C00013010000B3912000930E1000130E2000C6 -:1000D000639ED1539300100013011000B3912000D0 -:1000E000930E2000130E30006392D1539300100042 -:1000F00013017000B3912000930E0008130E40000E -:100100006396D151930010001301E000B3912000D9 -:10011000B74E0000130E5000639AD14F93001000A9 -:100120001301F001B3912000B70E0080130E6000A0 -:10013000639ED14D9300F0FF13010000B3912000A6 -:10014000930EF0FF130E70006392D14D9300F0FFF9 -:1001500013011000B3912000930EE0FF130E8000F6 -:100160006396D14B9300F0FF13017000B391200010 -:10017000930E00F8130E9000639AD1499300F0FF9C -:100180001301E000B3912000B7CEFFFF130EA000D3 -:10019000639ED1479300F0FF1301F001B39120005B -:1001A000B70E0080130EB0006392D147B720212113 -:1001B0009380101213010000B3912000B72E21216B -:1001C000938E1E12130EC0006392D145B7202121D9 -:1001D0009380101213011000B3912000B74E4242D9 -:1001E000938E2E24130ED0006392D143B720212189 -:1001F0009380101213017000B3912000B79E90906D -:10020000938E0E08130EE0006392D141B720212196 -:10021000938010121301E000B3912000B74E4848BC -:10022000130EF0006394D13FB72021219380101268 -:100230001301F001B3912000B70E0080130E0001EE -:100240006396D13DB720212193801012130100FC49 -:10025000B3912000B72E2121938E1E12130E100190 -:100260006396D13BB720212193801012130110FC1B -:10027000B3912000B74E4242938E2E24130E2001DC -:100280006396D139B720212193801012130170FC9D -:10029000B3912000B79E9090938E0E08130E3001FC -:1002A0006396D137B7202121938010121301E0FC0F -:1002B000B3912000B74E4848130E40016398D135E2 -:1002C0009300100013017000B3902000930E0008FB -:1002D000130E6001639CD033930010001301E00003 -:1002E00033912000B74E0000130E70016310D1331C -:1002F00093003000B3901000930E8001130E800124 -:100300006396D031130200009300100013017000B7 -:10031000B391200013830100130212009302200006 -:10032000E31452FE930E0008130E90016310D32FB6 -:1003300013020000930010001301E000B3912000AD -:100340001300000013830100130212009302200027 -:10035000E31252FEB74E0000130EA0016318D32B18 -:1003600013020000930010001301F001B39120006C -:100370001300000013000000138301001302120099 -:1003800093022000E31052FEB70E0080130EB0015E -:10039000631ED327130200009300100013017000A6 -:1003A000B39120001302120093022000E31652FEC4 -:1003B000930E0008130EC001639AD12513020000AA -:1003C000930010001301E00013000000B39120001F -:1003D0001302120093022000E31452FEB74E0000F5 -:1003E000130ED0016394D123130200009300100078 -:1003F0001301F0011300000013000000B39120006E -:100400001302120093022000E31252FEB70E008086 -:10041000130EE001639CD11F130200009300100033 -:100420001300000013017000B391200013021200AA -:1004300093022000E31452FE930E0008130EF00105 -:100440006396D11D130200009300100013000000FA -:100450001301E00013000000B3912000130212000A -:1004600093022000E31252FEB74E0000130E00026A -:10047000639ED119130200009300100013000000C6 -:10048000130000001301F001B391200013021200C9 -:1004900093022000E31252FEB70E0080130E1002EA -:1004A0006396D1171302000013017000930010002F -:1004B000B39120001302120093022000E31652FEB3 -:1004C000930E0008130E20026392D1151302000050 -:1004D0001301E0009300100013000000B39120000E -:1004E0001302120093022000E31452FEB74E0000E4 -:1004F000130E3002639CD111130200001301F001AE -:10050000930010001300000013000000B3912000BE -:100510001302120093022000E31252FEB70E008075 -:10052000130E40026394D10F1302000013017000F8 -:100530001300000093001000B3912000130212007A -:1005400093022000E31452FE930E0008130E500293 -:10055000639ED10B130200001301E00013000000A2 -:100560009300100013000000B3912000130212004A -:1005700093022000E31252FEB74E0000130E6002F9 -:100580006396D109130200001301F001130000006B -:100590001300000093001000B3912000130212001A -:1005A00093022000E31252FEB70E0080130E700279 -:1005B000639ED1059300F00033111000930E0000EC -:1005C000130E80026314D1059300000233910000E2 -:1005D000930E0002130E9002631AD103B3100000B1 -:1005E000930E0000130EA0026392D003930000400C -:1005F000371100001301018033902000930E00009A -:10060000130EB0026314D001631CC0010F00F00F81 -:1006100063000E00131E1E00136E1E007300000008 -:100620000F00F00F130E100073000000731000C0D5 -:1006300000000000000000000000000000000000BA -:0406400000000000B6 -:1010000000000000000000000000000000000000E0 -:1010100000000000000000000000000000000000D0 -:1010200000000000000000000000000000000000C0 -:1010300000000000000000000000000000000000B0 -:081040000000000000000000A8 -:040000058000200057 -:00000001FF diff --git a/benchmarks/riscv_tests/rv32ui-p-slli.dump b/benchmarks/riscv_tests/rv32ui-p-slli.dump deleted file mode 100644 index 9010d0ba..00000000 --- a/benchmarks/riscv_tests/rv32ui-p-slli.dump +++ /dev/null @@ -1,309 +0,0 @@ - -rv32ui-p-slli: file format elf32-littleriscv - - -Disassembly of section .text.init: - -80000000 <_start>: -80000000: 04c0006f j 8000004c - -80000004 : -80000004: 34202f73 csrr t5,mcause -80000008: 00800f93 li t6,8 -8000000c: 03ff0a63 beq t5,t6,80000040 -80000010: 00900f93 li t6,9 -80000014: 03ff0663 beq t5,t6,80000040 -80000018: 00b00f93 li t6,11 -8000001c: 03ff0263 beq t5,t6,80000040 -80000020: 80000f17 auipc t5,0x80000 -80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> -80000028: 000f0463 beqz t5,80000030 -8000002c: 000f0067 jr t5 -80000030: 34202f73 csrr t5,mcause -80000034: 000f5463 bgez t5,8000003c -80000038: 0040006f j 8000003c - -8000003c : -8000003c: 5391e193 ori gp,gp,1337 - -80000040 : -80000040: 00001f17 auipc t5,0x1 -80000044: fc3f2023 sw gp,-64(t5) # 80001000 -80000048: ff9ff06f j 80000040 - -8000004c : -8000004c: f1402573 csrr a0,mhartid -80000050: 00051063 bnez a0,80000050 -80000054: 00000297 auipc t0,0x0 -80000058: 01028293 addi t0,t0,16 # 80000064 -8000005c: 30529073 csrw mtvec,t0 -80000060: 18005073 csrwi satp,0 -80000064: 00000297 auipc t0,0x0 -80000068: 02028293 addi t0,t0,32 # 80000084 -8000006c: 30529073 csrw mtvec,t0 -80000070: 800002b7 lui t0,0x80000 -80000074: fff28293 addi t0,t0,-1 # 7fffffff <_end+0xffffdfff> -80000078: 3b029073 csrw pmpaddr0,t0 -8000007c: 01f00293 li t0,31 -80000080: 3a029073 csrw pmpcfg0,t0 -80000084: 00000297 auipc t0,0x0 -80000088: 01828293 addi t0,t0,24 # 8000009c -8000008c: 30529073 csrw mtvec,t0 -80000090: 30205073 csrwi medeleg,0 -80000094: 30305073 csrwi mideleg,0 -80000098: 30405073 csrwi mie,0 -8000009c: 00000193 li gp,0 -800000a0: 00000297 auipc t0,0x0 -800000a4: f6428293 addi t0,t0,-156 # 80000004 -800000a8: 30529073 csrw mtvec,t0 -800000ac: 00100513 li a0,1 -800000b0: 01f51513 slli a0,a0,0x1f -800000b4: 00054c63 bltz a0,800000cc -800000b8: 0ff0000f fence -800000bc: 00100193 li gp,1 -800000c0: 05d00893 li a7,93 -800000c4: 00000513 li a0,0 -800000c8: 00000073 ecall -800000cc: 80000297 auipc t0,0x80000 -800000d0: f3428293 addi t0,t0,-204 # 0 <_start-0x80000000> -800000d4: 00028e63 beqz t0,800000f0 -800000d8: 10529073 csrw stvec,t0 -800000dc: 0000b2b7 lui t0,0xb -800000e0: 10928293 addi t0,t0,265 # b109 <_start-0x7fff4ef7> -800000e4: 30229073 csrw medeleg,t0 -800000e8: 30202373 csrr t1,medeleg -800000ec: f46298e3 bne t0,t1,8000003c -800000f0: 30005073 csrwi mstatus,0 -800000f4: 00000297 auipc t0,0x0 -800000f8: 01428293 addi t0,t0,20 # 80000108 -800000fc: 34129073 csrw mepc,t0 -80000100: f1402573 csrr a0,mhartid -80000104: 30200073 mret - -80000108 : -80000108: 00100093 li ra,1 -8000010c: 00009713 slli a4,ra,0x0 -80000110: 00100e93 li t4,1 -80000114: 00200193 li gp,2 -80000118: 27d71a63 bne a4,t4,8000038c - -8000011c : -8000011c: 00100093 li ra,1 -80000120: 00109713 slli a4,ra,0x1 -80000124: 00200e93 li t4,2 -80000128: 00300193 li gp,3 -8000012c: 27d71063 bne a4,t4,8000038c - -80000130 : -80000130: 00100093 li ra,1 -80000134: 00709713 slli a4,ra,0x7 -80000138: 08000e93 li t4,128 -8000013c: 00400193 li gp,4 -80000140: 25d71663 bne a4,t4,8000038c - -80000144 : -80000144: 00100093 li ra,1 -80000148: 00e09713 slli a4,ra,0xe -8000014c: 00004eb7 lui t4,0x4 -80000150: 00500193 li gp,5 -80000154: 23d71c63 bne a4,t4,8000038c - -80000158 : -80000158: 00100093 li ra,1 -8000015c: 01f09713 slli a4,ra,0x1f -80000160: 80000eb7 lui t4,0x80000 -80000164: 00600193 li gp,6 -80000168: 23d71263 bne a4,t4,8000038c - -8000016c : -8000016c: fff00093 li ra,-1 -80000170: 00009713 slli a4,ra,0x0 -80000174: fff00e93 li t4,-1 -80000178: 00700193 li gp,7 -8000017c: 21d71863 bne a4,t4,8000038c - -80000180 : -80000180: fff00093 li ra,-1 -80000184: 00109713 slli a4,ra,0x1 -80000188: ffe00e93 li t4,-2 -8000018c: 00800193 li gp,8 -80000190: 1fd71e63 bne a4,t4,8000038c - -80000194 : -80000194: fff00093 li ra,-1 -80000198: 00709713 slli a4,ra,0x7 -8000019c: f8000e93 li t4,-128 -800001a0: 00900193 li gp,9 -800001a4: 1fd71463 bne a4,t4,8000038c - -800001a8 : -800001a8: fff00093 li ra,-1 -800001ac: 00e09713 slli a4,ra,0xe -800001b0: ffffceb7 lui t4,0xffffc -800001b4: 00a00193 li gp,10 -800001b8: 1dd71a63 bne a4,t4,8000038c - -800001bc : -800001bc: fff00093 li ra,-1 -800001c0: 01f09713 slli a4,ra,0x1f -800001c4: 80000eb7 lui t4,0x80000 -800001c8: 00b00193 li gp,11 -800001cc: 1dd71063 bne a4,t4,8000038c - -800001d0 : -800001d0: 212120b7 lui ra,0x21212 -800001d4: 12108093 addi ra,ra,289 # 21212121 <_start-0x5edededf> -800001d8: 00009713 slli a4,ra,0x0 -800001dc: 21212eb7 lui t4,0x21212 -800001e0: 121e8e93 addi t4,t4,289 # 21212121 <_start-0x5edededf> -800001e4: 00c00193 li gp,12 -800001e8: 1bd71263 bne a4,t4,8000038c - -800001ec : -800001ec: 212120b7 lui ra,0x21212 -800001f0: 12108093 addi ra,ra,289 # 21212121 <_start-0x5edededf> -800001f4: 00109713 slli a4,ra,0x1 -800001f8: 42424eb7 lui t4,0x42424 -800001fc: 242e8e93 addi t4,t4,578 # 42424242 <_start-0x3dbdbdbe> -80000200: 00d00193 li gp,13 -80000204: 19d71463 bne a4,t4,8000038c - -80000208 : -80000208: 212120b7 lui ra,0x21212 -8000020c: 12108093 addi ra,ra,289 # 21212121 <_start-0x5edededf> -80000210: 00709713 slli a4,ra,0x7 -80000214: 90909eb7 lui t4,0x90909 -80000218: 080e8e93 addi t4,t4,128 # 90909080 <_end+0x10907080> -8000021c: 00e00193 li gp,14 -80000220: 17d71663 bne a4,t4,8000038c - -80000224 : -80000224: 212120b7 lui ra,0x21212 -80000228: 12108093 addi ra,ra,289 # 21212121 <_start-0x5edededf> -8000022c: 00e09713 slli a4,ra,0xe -80000230: 48484eb7 lui t4,0x48484 -80000234: 00f00193 li gp,15 -80000238: 15d71a63 bne a4,t4,8000038c - -8000023c : -8000023c: 212120b7 lui ra,0x21212 -80000240: 12108093 addi ra,ra,289 # 21212121 <_start-0x5edededf> -80000244: 01f09713 slli a4,ra,0x1f -80000248: 80000eb7 lui t4,0x80000 -8000024c: 01000193 li gp,16 -80000250: 13d71e63 bne a4,t4,8000038c - -80000254 : -80000254: 00100093 li ra,1 -80000258: 00709093 slli ra,ra,0x7 -8000025c: 08000e93 li t4,128 -80000260: 01100193 li gp,17 -80000264: 13d09463 bne ra,t4,8000038c - -80000268 : -80000268: 00000213 li tp,0 -8000026c: 00100093 li ra,1 -80000270: 00709713 slli a4,ra,0x7 -80000274: 00070313 mv t1,a4 -80000278: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -8000027c: 00200293 li t0,2 -80000280: fe5216e3 bne tp,t0,8000026c -80000284: 08000e93 li t4,128 -80000288: 01200193 li gp,18 -8000028c: 11d31063 bne t1,t4,8000038c - -80000290 : -80000290: 00000213 li tp,0 -80000294: 00100093 li ra,1 -80000298: 00e09713 slli a4,ra,0xe -8000029c: 00000013 nop -800002a0: 00070313 mv t1,a4 -800002a4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -800002a8: 00200293 li t0,2 -800002ac: fe5214e3 bne tp,t0,80000294 -800002b0: 00004eb7 lui t4,0x4 -800002b4: 01300193 li gp,19 -800002b8: 0dd31a63 bne t1,t4,8000038c - -800002bc : -800002bc: 00000213 li tp,0 -800002c0: 00100093 li ra,1 -800002c4: 01f09713 slli a4,ra,0x1f -800002c8: 00000013 nop -800002cc: 00000013 nop -800002d0: 00070313 mv t1,a4 -800002d4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -800002d8: 00200293 li t0,2 -800002dc: fe5212e3 bne tp,t0,800002c0 -800002e0: 80000eb7 lui t4,0x80000 -800002e4: 01400193 li gp,20 -800002e8: 0bd31263 bne t1,t4,8000038c - -800002ec : -800002ec: 00000213 li tp,0 -800002f0: 00100093 li ra,1 -800002f4: 00709713 slli a4,ra,0x7 -800002f8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -800002fc: 00200293 li t0,2 -80000300: fe5218e3 bne tp,t0,800002f0 -80000304: 08000e93 li t4,128 -80000308: 01500193 li gp,21 -8000030c: 09d71063 bne a4,t4,8000038c - -80000310 : -80000310: 00000213 li tp,0 -80000314: 00100093 li ra,1 -80000318: 00000013 nop -8000031c: 00e09713 slli a4,ra,0xe -80000320: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000324: 00200293 li t0,2 -80000328: fe5216e3 bne tp,t0,80000314 -8000032c: 00004eb7 lui t4,0x4 -80000330: 01600193 li gp,22 -80000334: 05d71c63 bne a4,t4,8000038c - -80000338 : -80000338: 00000213 li tp,0 -8000033c: 00100093 li ra,1 -80000340: 00000013 nop -80000344: 00000013 nop -80000348: 01f09713 slli a4,ra,0x1f -8000034c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000350: 00200293 li t0,2 -80000354: fe5214e3 bne tp,t0,8000033c -80000358: 80000eb7 lui t4,0x80000 -8000035c: 01700193 li gp,23 -80000360: 03d71663 bne a4,t4,8000038c - -80000364 : -80000364: 01f01093 slli ra,zero,0x1f -80000368: 00000e93 li t4,0 -8000036c: 01800193 li gp,24 -80000370: 01d09e63 bne ra,t4,8000038c - -80000374 : -80000374: 02100093 li ra,33 -80000378: 01409013 slli zero,ra,0x14 -8000037c: 00000e93 li t4,0 -80000380: 01900193 li gp,25 -80000384: 01d01463 bne zero,t4,8000038c -80000388: 02301063 bne zero,gp,800003a8 - -8000038c : -8000038c: 0ff0000f fence -80000390: 00018063 beqz gp,80000390 -80000394: 00119193 slli gp,gp,0x1 -80000398: 0011e193 ori gp,gp,1 -8000039c: 05d00893 li a7,93 -800003a0: 00018513 mv a0,gp -800003a4: 00000073 ecall - -800003a8 : -800003a8: 0ff0000f fence -800003ac: 00100193 li gp,1 -800003b0: 05d00893 li a7,93 -800003b4: 00000513 li a0,0 -800003b8: 00000073 ecall -800003bc: c0001073 unimp -800003c0: 0000 unimp -800003c2: 0000 unimp diff --git a/benchmarks/riscv_tests/rv32ui-p-slli.hex b/benchmarks/riscv_tests/rv32ui-p-slli.hex deleted file mode 100644 index 6b602bd0..00000000 --- a/benchmarks/riscv_tests/rv32ui-p-slli.hex +++ /dev/null @@ -1,65 +0,0 @@ -:0200000480007A -:100000006F00C004732F2034930F8000630AFF0336 -:10001000930F90006306FF03930FB0006302FF038A -:10002000170F0080130F0FFE63040F0067000F000F -:10003000732F203463540F006F004000136E9E53E3 -:10004000171F00002320CFFD6FF09FFF732540F1A5 -:100050006310050073251030635805000F00F00F82 -:10006000130E100073000000130E00009702000032 -:10007000938282F973905230735020307350303035 -:1000800073504030970200809382C2F7638C020065 -:10009000739052109302B01A739022307323203061 -:1000A000E39E62F873500030970200009382420191 -:1000B00073901234732540F17300203093001000C8 -:1000C00093910000930E1000130E2000639AD12725 -:1000D0009300100093911000930E2000130E300037 -:1000E0006390D1279300100093917000930E000845 -:1000F000130E40006396D125930010009391E00009 -:10010000B74E0000130E5000639CD12393001000E3 -:100110009391F001B70E0080130E60006392D1231B -:100120009300F0FF93910000930EF0FF130E700008 -:100130006398D1219300F0FF93911000930EE0FF9C -:10014000130E8000639ED11F9300F0FF9391700007 -:10015000930E00F8130E90006394D11F9300F0FFEC -:100160009391E000B7CEFFFF130EA000639AD11D5C -:100170009300F0FF9391F001B70E0080130EB000D2 -:100180006390D11DB720212193801012939100001C -:10019000B72E2121938E1E12130EC0006392D11B25 -:1001A000B72021219380101293911000B74E424244 -:1001B000938E2E24130ED0006394D119B7202121E1 -:1001C0009380101293917000B79E9090938E0E08BA -:1001D000130EE0006396D117B720212193801012EF -:1001E0009391E000B74E4848130EF000639AD11582 -:1001F000B7202121938010129391F001B70E008057 -:10020000130E0001639ED1139300100093907000B1 -:10021000930E0008130E10016394D0131302000014 -:1002200093001000939170001383010013021200D9 -:1002300093022000E31652FE930E0008130E2001D5 -:100240006310D31113020000930010009391E0009B -:100250001300000013830100130212009302200018 -:10026000E31452FEB74E0000130E3001631AD30D93 -:1002700013020000930010009391F001130000009E -:1002800013000000138301001302120093022000E8 -:10029000E31252FEB70E0080130E40016312D30B1F -:1002A00013020000930010009391700013021200DB -:1002B00093022000E31852FE930E0008130E500123 -:1002C0006390D10913020000930010001300000096 -:1002D0009391E0001302120093022000E31652FEF5 -:1002E000B74E0000130E6001639CD105130200009D -:1002F0009300100013000000130000009391F00120 -:100300001302120093022000E31452FEB70E008085 -:10031000130E70016396D1039310F001930E000049 -:10032000130E8001639ED0019300100213904001D0 -:10033000930E0000130E90016314D001631CC001E2 -:100340000F00F00F63000E00131E1E00136E1E0040 -:10035000730000000F00F00F130E10007300000078 -:10036000731000C00000000000000000000000004A -:10037000000000000000000000000000000000007D -:040380000000000079 -:1010000000000000000000000000000000000000E0 -:1010100000000000000000000000000000000000D0 -:1010200000000000000000000000000000000000C0 -:1010300000000000000000000000000000000000B0 -:081040000000000000000000A8 -:040000058000200057 -:00000001FF diff --git a/benchmarks/riscv_tests/rv32ui-p-slt.dump b/benchmarks/riscv_tests/rv32ui-p-slt.dump deleted file mode 100644 index ec7b4174..00000000 --- a/benchmarks/riscv_tests/rv32ui-p-slt.dump +++ /dev/null @@ -1,478 +0,0 @@ - -rv32ui-p-slt: file format elf32-littleriscv - - -Disassembly of section .text.init: - -80000000 <_start>: -80000000: 04c0006f j 8000004c - -80000004 : -80000004: 34202f73 csrr t5,mcause -80000008: 00800f93 li t6,8 -8000000c: 03ff0a63 beq t5,t6,80000040 -80000010: 00900f93 li t6,9 -80000014: 03ff0663 beq t5,t6,80000040 -80000018: 00b00f93 li t6,11 -8000001c: 03ff0263 beq t5,t6,80000040 -80000020: 80000f17 auipc t5,0x80000 -80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> -80000028: 000f0463 beqz t5,80000030 -8000002c: 000f0067 jr t5 -80000030: 34202f73 csrr t5,mcause -80000034: 000f5463 bgez t5,8000003c -80000038: 0040006f j 8000003c - -8000003c : -8000003c: 5391e193 ori gp,gp,1337 - -80000040 : -80000040: 00001f17 auipc t5,0x1 -80000044: fc3f2023 sw gp,-64(t5) # 80001000 -80000048: ff9ff06f j 80000040 - -8000004c : -8000004c: f1402573 csrr a0,mhartid -80000050: 00051063 bnez a0,80000050 -80000054: 00000297 auipc t0,0x0 -80000058: 01028293 addi t0,t0,16 # 80000064 -8000005c: 30529073 csrw mtvec,t0 -80000060: 18005073 csrwi satp,0 -80000064: 00000297 auipc t0,0x0 -80000068: 02028293 addi t0,t0,32 # 80000084 -8000006c: 30529073 csrw mtvec,t0 -80000070: 800002b7 lui t0,0x80000 -80000074: fff28293 addi t0,t0,-1 # 7fffffff <_end+0xffffdfff> -80000078: 3b029073 csrw pmpaddr0,t0 -8000007c: 01f00293 li t0,31 -80000080: 3a029073 csrw pmpcfg0,t0 -80000084: 00000297 auipc t0,0x0 -80000088: 01828293 addi t0,t0,24 # 8000009c -8000008c: 30529073 csrw mtvec,t0 -80000090: 30205073 csrwi medeleg,0 -80000094: 30305073 csrwi mideleg,0 -80000098: 30405073 csrwi mie,0 -8000009c: 00000193 li gp,0 -800000a0: 00000297 auipc t0,0x0 -800000a4: f6428293 addi t0,t0,-156 # 80000004 -800000a8: 30529073 csrw mtvec,t0 -800000ac: 00100513 li a0,1 -800000b0: 01f51513 slli a0,a0,0x1f -800000b4: 00054c63 bltz a0,800000cc -800000b8: 0ff0000f fence -800000bc: 00100193 li gp,1 -800000c0: 05d00893 li a7,93 -800000c4: 00000513 li a0,0 -800000c8: 00000073 ecall -800000cc: 80000297 auipc t0,0x80000 -800000d0: f3428293 addi t0,t0,-204 # 0 <_start-0x80000000> -800000d4: 00028e63 beqz t0,800000f0 -800000d8: 10529073 csrw stvec,t0 -800000dc: 0000b2b7 lui t0,0xb -800000e0: 10928293 addi t0,t0,265 # b109 <_start-0x7fff4ef7> -800000e4: 30229073 csrw medeleg,t0 -800000e8: 30202373 csrr t1,medeleg -800000ec: f46298e3 bne t0,t1,8000003c -800000f0: 30005073 csrwi mstatus,0 -800000f4: 00000297 auipc t0,0x0 -800000f8: 01428293 addi t0,t0,20 # 80000108 -800000fc: 34129073 csrw mepc,t0 -80000100: f1402573 csrr a0,mhartid -80000104: 30200073 mret - -80000108 : -80000108: 00000093 li ra,0 -8000010c: 00000113 li sp,0 -80000110: 0020a733 slt a4,ra,sp -80000114: 00000e93 li t4,0 -80000118: 00200193 li gp,2 -8000011c: 4bd71a63 bne a4,t4,800005d0 - -80000120 : -80000120: 00100093 li ra,1 -80000124: 00100113 li sp,1 -80000128: 0020a733 slt a4,ra,sp -8000012c: 00000e93 li t4,0 -80000130: 00300193 li gp,3 -80000134: 49d71e63 bne a4,t4,800005d0 - -80000138 : -80000138: 00300093 li ra,3 -8000013c: 00700113 li sp,7 -80000140: 0020a733 slt a4,ra,sp -80000144: 00100e93 li t4,1 -80000148: 00400193 li gp,4 -8000014c: 49d71263 bne a4,t4,800005d0 - -80000150 : -80000150: 00700093 li ra,7 -80000154: 00300113 li sp,3 -80000158: 0020a733 slt a4,ra,sp -8000015c: 00000e93 li t4,0 -80000160: 00500193 li gp,5 -80000164: 47d71663 bne a4,t4,800005d0 - -80000168 : -80000168: 00000093 li ra,0 -8000016c: ffff8137 lui sp,0xffff8 -80000170: 0020a733 slt a4,ra,sp -80000174: 00000e93 li t4,0 -80000178: 00600193 li gp,6 -8000017c: 45d71a63 bne a4,t4,800005d0 - -80000180 : -80000180: 800000b7 lui ra,0x80000 -80000184: 00000113 li sp,0 -80000188: 0020a733 slt a4,ra,sp -8000018c: 00100e93 li t4,1 -80000190: 00700193 li gp,7 -80000194: 43d71e63 bne a4,t4,800005d0 - -80000198 : -80000198: 800000b7 lui ra,0x80000 -8000019c: ffff8137 lui sp,0xffff8 -800001a0: 0020a733 slt a4,ra,sp -800001a4: 00100e93 li t4,1 -800001a8: 00800193 li gp,8 -800001ac: 43d71263 bne a4,t4,800005d0 - -800001b0 : -800001b0: 00000093 li ra,0 -800001b4: 00008137 lui sp,0x8 -800001b8: fff10113 addi sp,sp,-1 # 7fff <_start-0x7fff8001> -800001bc: 0020a733 slt a4,ra,sp -800001c0: 00100e93 li t4,1 -800001c4: 00900193 li gp,9 -800001c8: 41d71463 bne a4,t4,800005d0 - -800001cc : -800001cc: 800000b7 lui ra,0x80000 -800001d0: fff08093 addi ra,ra,-1 # 7fffffff <_end+0xffffdfff> -800001d4: 00000113 li sp,0 -800001d8: 0020a733 slt a4,ra,sp -800001dc: 00000e93 li t4,0 -800001e0: 00a00193 li gp,10 -800001e4: 3fd71663 bne a4,t4,800005d0 - -800001e8 : -800001e8: 800000b7 lui ra,0x80000 -800001ec: fff08093 addi ra,ra,-1 # 7fffffff <_end+0xffffdfff> -800001f0: 00008137 lui sp,0x8 -800001f4: fff10113 addi sp,sp,-1 # 7fff <_start-0x7fff8001> -800001f8: 0020a733 slt a4,ra,sp -800001fc: 00000e93 li t4,0 -80000200: 00b00193 li gp,11 -80000204: 3dd71663 bne a4,t4,800005d0 - -80000208 : -80000208: 800000b7 lui ra,0x80000 -8000020c: 00008137 lui sp,0x8 -80000210: fff10113 addi sp,sp,-1 # 7fff <_start-0x7fff8001> -80000214: 0020a733 slt a4,ra,sp -80000218: 00100e93 li t4,1 -8000021c: 00c00193 li gp,12 -80000220: 3bd71863 bne a4,t4,800005d0 - -80000224 : -80000224: 800000b7 lui ra,0x80000 -80000228: fff08093 addi ra,ra,-1 # 7fffffff <_end+0xffffdfff> -8000022c: ffff8137 lui sp,0xffff8 -80000230: 0020a733 slt a4,ra,sp -80000234: 00000e93 li t4,0 -80000238: 00d00193 li gp,13 -8000023c: 39d71a63 bne a4,t4,800005d0 - -80000240 : -80000240: 00000093 li ra,0 -80000244: fff00113 li sp,-1 -80000248: 0020a733 slt a4,ra,sp -8000024c: 00000e93 li t4,0 -80000250: 00e00193 li gp,14 -80000254: 37d71e63 bne a4,t4,800005d0 - -80000258 : -80000258: fff00093 li ra,-1 -8000025c: 00100113 li sp,1 -80000260: 0020a733 slt a4,ra,sp -80000264: 00100e93 li t4,1 -80000268: 00f00193 li gp,15 -8000026c: 37d71263 bne a4,t4,800005d0 - -80000270 : -80000270: fff00093 li ra,-1 -80000274: fff00113 li sp,-1 -80000278: 0020a733 slt a4,ra,sp -8000027c: 00000e93 li t4,0 -80000280: 01000193 li gp,16 -80000284: 35d71663 bne a4,t4,800005d0 - -80000288 : -80000288: 00e00093 li ra,14 -8000028c: 00d00113 li sp,13 -80000290: 0020a0b3 slt ra,ra,sp -80000294: 00000e93 li t4,0 -80000298: 01100193 li gp,17 -8000029c: 33d09a63 bne ra,t4,800005d0 - -800002a0 : -800002a0: 00b00093 li ra,11 -800002a4: 00d00113 li sp,13 -800002a8: 0020a133 slt sp,ra,sp -800002ac: 00100e93 li t4,1 -800002b0: 01200193 li gp,18 -800002b4: 31d11e63 bne sp,t4,800005d0 - -800002b8 : -800002b8: 00d00093 li ra,13 -800002bc: 0010a0b3 slt ra,ra,ra -800002c0: 00000e93 li t4,0 -800002c4: 01300193 li gp,19 -800002c8: 31d09463 bne ra,t4,800005d0 - -800002cc : -800002cc: 00000213 li tp,0 -800002d0: 00b00093 li ra,11 -800002d4: 00d00113 li sp,13 -800002d8: 0020a733 slt a4,ra,sp -800002dc: 00070313 mv t1,a4 -800002e0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -800002e4: 00200293 li t0,2 -800002e8: fe5214e3 bne tp,t0,800002d0 -800002ec: 00100e93 li t4,1 -800002f0: 01400193 li gp,20 -800002f4: 2dd31e63 bne t1,t4,800005d0 - -800002f8 : -800002f8: 00000213 li tp,0 -800002fc: 00e00093 li ra,14 -80000300: 00d00113 li sp,13 -80000304: 0020a733 slt a4,ra,sp -80000308: 00000013 nop -8000030c: 00070313 mv t1,a4 -80000310: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000314: 00200293 li t0,2 -80000318: fe5212e3 bne tp,t0,800002fc -8000031c: 00000e93 li t4,0 -80000320: 01500193 li gp,21 -80000324: 2bd31663 bne t1,t4,800005d0 - -80000328 : -80000328: 00000213 li tp,0 -8000032c: 00c00093 li ra,12 -80000330: 00d00113 li sp,13 -80000334: 0020a733 slt a4,ra,sp -80000338: 00000013 nop -8000033c: 00000013 nop -80000340: 00070313 mv t1,a4 -80000344: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000348: 00200293 li t0,2 -8000034c: fe5210e3 bne tp,t0,8000032c -80000350: 00100e93 li t4,1 -80000354: 01600193 li gp,22 -80000358: 27d31c63 bne t1,t4,800005d0 - -8000035c : -8000035c: 00000213 li tp,0 -80000360: 00e00093 li ra,14 -80000364: 00d00113 li sp,13 -80000368: 0020a733 slt a4,ra,sp -8000036c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000370: 00200293 li t0,2 -80000374: fe5216e3 bne tp,t0,80000360 -80000378: 00000e93 li t4,0 -8000037c: 01700193 li gp,23 -80000380: 25d71863 bne a4,t4,800005d0 - -80000384 : -80000384: 00000213 li tp,0 -80000388: 00b00093 li ra,11 -8000038c: 00d00113 li sp,13 -80000390: 00000013 nop -80000394: 0020a733 slt a4,ra,sp -80000398: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -8000039c: 00200293 li t0,2 -800003a0: fe5214e3 bne tp,t0,80000388 -800003a4: 00100e93 li t4,1 -800003a8: 01800193 li gp,24 -800003ac: 23d71263 bne a4,t4,800005d0 - -800003b0 : -800003b0: 00000213 li tp,0 -800003b4: 00f00093 li ra,15 -800003b8: 00d00113 li sp,13 -800003bc: 00000013 nop -800003c0: 00000013 nop -800003c4: 0020a733 slt a4,ra,sp -800003c8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -800003cc: 00200293 li t0,2 -800003d0: fe5212e3 bne tp,t0,800003b4 -800003d4: 00000e93 li t4,0 -800003d8: 01900193 li gp,25 -800003dc: 1fd71a63 bne a4,t4,800005d0 - -800003e0 : -800003e0: 00000213 li tp,0 -800003e4: 00a00093 li ra,10 -800003e8: 00000013 nop -800003ec: 00d00113 li sp,13 -800003f0: 0020a733 slt a4,ra,sp -800003f4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -800003f8: 00200293 li t0,2 -800003fc: fe5214e3 bne tp,t0,800003e4 -80000400: 00100e93 li t4,1 -80000404: 01a00193 li gp,26 -80000408: 1dd71463 bne a4,t4,800005d0 - -8000040c : -8000040c: 00000213 li tp,0 -80000410: 01000093 li ra,16 -80000414: 00000013 nop -80000418: 00d00113 li sp,13 -8000041c: 00000013 nop -80000420: 0020a733 slt a4,ra,sp -80000424: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000428: 00200293 li t0,2 -8000042c: fe5212e3 bne tp,t0,80000410 -80000430: 00000e93 li t4,0 -80000434: 01b00193 li gp,27 -80000438: 19d71c63 bne a4,t4,800005d0 - -8000043c : -8000043c: 00000213 li tp,0 -80000440: 00900093 li ra,9 -80000444: 00000013 nop -80000448: 00000013 nop -8000044c: 00d00113 li sp,13 -80000450: 0020a733 slt a4,ra,sp -80000454: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000458: 00200293 li t0,2 -8000045c: fe5212e3 bne tp,t0,80000440 -80000460: 00100e93 li t4,1 -80000464: 01c00193 li gp,28 -80000468: 17d71463 bne a4,t4,800005d0 - -8000046c : -8000046c: 00000213 li tp,0 -80000470: 00d00113 li sp,13 -80000474: 01100093 li ra,17 -80000478: 0020a733 slt a4,ra,sp -8000047c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000480: 00200293 li t0,2 -80000484: fe5216e3 bne tp,t0,80000470 -80000488: 00000e93 li t4,0 -8000048c: 01d00193 li gp,29 -80000490: 15d71063 bne a4,t4,800005d0 - -80000494 : -80000494: 00000213 li tp,0 -80000498: 00d00113 li sp,13 -8000049c: 00800093 li ra,8 -800004a0: 00000013 nop -800004a4: 0020a733 slt a4,ra,sp -800004a8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -800004ac: 00200293 li t0,2 -800004b0: fe5214e3 bne tp,t0,80000498 -800004b4: 00100e93 li t4,1 -800004b8: 01e00193 li gp,30 -800004bc: 11d71a63 bne a4,t4,800005d0 - -800004c0 : -800004c0: 00000213 li tp,0 -800004c4: 00d00113 li sp,13 -800004c8: 01200093 li ra,18 -800004cc: 00000013 nop -800004d0: 00000013 nop -800004d4: 0020a733 slt a4,ra,sp -800004d8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -800004dc: 00200293 li t0,2 -800004e0: fe5212e3 bne tp,t0,800004c4 -800004e4: 00000e93 li t4,0 -800004e8: 01f00193 li gp,31 -800004ec: 0fd71263 bne a4,t4,800005d0 - -800004f0 : -800004f0: 00000213 li tp,0 -800004f4: 00d00113 li sp,13 -800004f8: 00000013 nop -800004fc: 00700093 li ra,7 -80000500: 0020a733 slt a4,ra,sp -80000504: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000508: 00200293 li t0,2 -8000050c: fe5214e3 bne tp,t0,800004f4 -80000510: 00100e93 li t4,1 -80000514: 02000193 li gp,32 -80000518: 0bd71c63 bne a4,t4,800005d0 - -8000051c : -8000051c: 00000213 li tp,0 -80000520: 00d00113 li sp,13 -80000524: 00000013 nop -80000528: 01300093 li ra,19 -8000052c: 00000013 nop -80000530: 0020a733 slt a4,ra,sp -80000534: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000538: 00200293 li t0,2 -8000053c: fe5212e3 bne tp,t0,80000520 -80000540: 00000e93 li t4,0 -80000544: 02100193 li gp,33 -80000548: 09d71463 bne a4,t4,800005d0 - -8000054c : -8000054c: 00000213 li tp,0 -80000550: 00d00113 li sp,13 -80000554: 00000013 nop -80000558: 00000013 nop -8000055c: 00600093 li ra,6 -80000560: 0020a733 slt a4,ra,sp -80000564: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000568: 00200293 li t0,2 -8000056c: fe5212e3 bne tp,t0,80000550 -80000570: 00100e93 li t4,1 -80000574: 02200193 li gp,34 -80000578: 05d71c63 bne a4,t4,800005d0 - -8000057c : -8000057c: fff00093 li ra,-1 -80000580: 00102133 sgtz sp,ra -80000584: 00000e93 li t4,0 -80000588: 02300193 li gp,35 -8000058c: 05d11263 bne sp,t4,800005d0 - -80000590 : -80000590: fff00093 li ra,-1 -80000594: 0000a133 sltz sp,ra -80000598: 00100e93 li t4,1 -8000059c: 02400193 li gp,36 -800005a0: 03d11863 bne sp,t4,800005d0 - -800005a4 : -800005a4: 000020b3 sltz ra,zero -800005a8: 00000e93 li t4,0 -800005ac: 02500193 li gp,37 -800005b0: 03d09063 bne ra,t4,800005d0 - -800005b4 : -800005b4: 01000093 li ra,16 -800005b8: 01e00113 li sp,30 -800005bc: 0020a033 slt zero,ra,sp -800005c0: 00000e93 li t4,0 -800005c4: 02600193 li gp,38 -800005c8: 01d01463 bne zero,t4,800005d0 -800005cc: 02301063 bne zero,gp,800005ec - -800005d0 : -800005d0: 0ff0000f fence -800005d4: 00018063 beqz gp,800005d4 -800005d8: 00119193 slli gp,gp,0x1 -800005dc: 0011e193 ori gp,gp,1 -800005e0: 05d00893 li a7,93 -800005e4: 00018513 mv a0,gp -800005e8: 00000073 ecall - -800005ec : -800005ec: 0ff0000f fence -800005f0: 00100193 li gp,1 -800005f4: 05d00893 li a7,93 -800005f8: 00000513 li a0,0 -800005fc: 00000073 ecall -80000600: c0001073 unimp diff --git a/benchmarks/riscv_tests/rv32ui-p-slt.hex b/benchmarks/riscv_tests/rv32ui-p-slt.hex deleted file mode 100644 index abca3020..00000000 --- a/benchmarks/riscv_tests/rv32ui-p-slt.hex +++ /dev/null @@ -1,101 +0,0 @@ -:0200000480007A -:100000006F00C004732F2034930F8000630AFF0336 -:10001000930F90006306FF03930FB0006302FF038A -:10002000170F0080130F0FFE63040F0067000F000F -:10003000732F203463540F006F004000136E9E53E3 -:10004000171F00002320CFFD6FF09FFF732540F1A5 -:100050006310050073251030635805000F00F00F82 -:10006000130E100073000000130E00009702000032 -:10007000938282F973905230735020307350303035 -:1000800073504030970200809382C2F7638C020065 -:10009000739052109302B01A739022307323203061 -:1000A000E39E62F873500030970200009382420191 -:1000B00073901234732540F17300203093000000D8 -:1000C00013010000B3A12000930E0000130E2000C6 -:1000D000639AD14B9300100013011000B3A12000CC -:1000E000930E0000130E3000639ED1499300300040 -:1000F00013017000B3A12000930E1000130E4000F6 -:100100006392D1499300700013013000B3A1200025 -:10011000930E0000130E50006396D1479300000029 -:100120003781FFFFB3A12000930E0000130E600083 -:10013000639AD145B700008013010000B3A12000ED -:10014000930E1000130E7000639ED143B700008021 -:100150003781FFFFB3A12000930E1000130E800023 -:100160006392D14393000000378100001301F1FF37 -:10017000B3A12000930E1000130E90006394D141A0 -:10018000B70000809380F0FF13010000B3A12000AE -:10019000930E0000130EA0006396D13FB7000080BD -:1001A0009380F0FF378100001301F1FFB3A120001D -:1001B000930E0000130EB0006396D13DB70000808F -:1001C000378100001301F1FFB3A12000930E10004E -:1001D000130EC0006398D13BB70000809380F0FFFE -:1001E0003781FFFFB3A12000930E0000130ED00053 -:1001F000639AD139930000001301F0FFB3A12000EE -:10020000930E0000130EE000639ED1379300F0FFC1 -:1002100013011000B3A12000930E1000130EF00084 -:100220006392D1379300F0FF1301F0FFB3A12000D8 -:10023000930E0000130E00016396D1359300E00089 -:100240001301D000B3A02000930E0000130E100184 -:10025000639AD0339300B0001301D00033A1200083 -:10026000930E1000130E2001631ED1319300D000B5 -:10027000B3A01000930E0000130E30016394D03130 -:10028000130200009300B0001301D000B3A12000BE -:10029000138301001302120093022000E31452FEA4 -:1002A000930E1000130E4001631ED32D13020000A5 -:1002B0009300E0001301D000B3A120001300000060 -:1002C000138301001302120093022000E31252FE76 -:1002D000930E0000130E50016316D32B130200007F -:1002E0009300C0001301D000B3A120001300000050 -:1002F0001300000013830100130212009302200078 -:10030000E31052FE930E1000130E6001631CD327FE -:10031000130200009300E0001301D000B3A12000FD -:100320001302120093022000E31652FE930E000007 -:10033000130E70016398D125130200009300B000E2 -:100340001301D00013000000B3A12000130212001B -:1003500093022000E31452FE930E1000130E80014E -:100360006392D123130200009300F0001301D00028 -:100370001300000013000000B3A1200013021200BC -:1003800093022000E31252FE930E0000130E900120 -:10039000639AD11F130200009300A0001300000015 -:1003A0001301D000B3A12000130212009302200019 -:1003B000E31452FE930E1000130EA0016394D11D9E -:1003C0001302000093000001130000001301D0008D -:1003D00013000000B3A120001302120093022000BA -:1003E000E31252FE930E0000130EB001639CD1196C -:1003F000130200009300900013000000130000009F -:100400001301D000B3A120001302120093022000B8 -:10041000E31252FE930E1000130EC0016394D11725 -:10042000130200001301D00093001001B3A12000BB -:100430001302120093022000E31652FE930E0000F6 -:10044000130ED0016390D115130200001301D000E8 -:100450009300800013000000B3A1200013021200DB -:1004600093022000E31452FE930E1000130EE001DD -:10047000639AD111130200001301D00093002001F0 -:100480001300000013000000B3A1200013021200AB -:1004900093022000E31252FE930E0000130EF001AF -:1004A0006392D10F130200001301D000130000006B -:1004B00093007000B3A120001302120093022000E9 -:1004C000E31452FE930E1000130E0002639CD10B36 -:1004D000130200001301D00013000000930030014C -:1004E00013000000B3A120001302120093022000A9 -:1004F000E31252FE930E0000130E10026394D10912 -:10050000130200001301D0001300000013000000CC -:1005100093006000B3A12000130212009302200098 -:10052000E31252FE930E1000130E2002639CD105BD -:100530009300F0FF33211000930E0000130E3002E1 -:100540006312D1059300F0FF33A10000930E100059 -:10055000130E40026318D103B3200000930E000075 -:10056000130E50026390D003930000011301E001C9 -:1005700033A02000930E0000130E60026314D0011C -:10058000631CC0010F00F00F63000E00131E1E005D -:10059000136E1E00730000000F00F00F130E10000A -:1005A00073000000731000C0000000000000000095 -:1005B000000000000000000000000000000000003B -:0405C0000000000037 -:1010000000000000000000000000000000000000E0 -:1010100000000000000000000000000000000000D0 -:1010200000000000000000000000000000000000C0 -:1010300000000000000000000000000000000000B0 -:081040000000000000000000A8 -:040000058000200057 -:00000001FF diff --git a/benchmarks/riscv_tests/rv32ui-p-slti.dump b/benchmarks/riscv_tests/rv32ui-p-slti.dump deleted file mode 100644 index 167a412d..00000000 --- a/benchmarks/riscv_tests/rv32ui-p-slti.dump +++ /dev/null @@ -1,313 +0,0 @@ - -rv32ui-p-slti: file format elf32-littleriscv - - -Disassembly of section .text.init: - -80000000 <_start>: -80000000: 04c0006f j 8000004c - -80000004 : -80000004: 34202f73 csrr t5,mcause -80000008: 00800f93 li t6,8 -8000000c: 03ff0a63 beq t5,t6,80000040 -80000010: 00900f93 li t6,9 -80000014: 03ff0663 beq t5,t6,80000040 -80000018: 00b00f93 li t6,11 -8000001c: 03ff0263 beq t5,t6,80000040 -80000020: 80000f17 auipc t5,0x80000 -80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> -80000028: 000f0463 beqz t5,80000030 -8000002c: 000f0067 jr t5 -80000030: 34202f73 csrr t5,mcause -80000034: 000f5463 bgez t5,8000003c -80000038: 0040006f j 8000003c - -8000003c : -8000003c: 5391e193 ori gp,gp,1337 - -80000040 : -80000040: 00001f17 auipc t5,0x1 -80000044: fc3f2023 sw gp,-64(t5) # 80001000 -80000048: ff9ff06f j 80000040 - -8000004c : -8000004c: f1402573 csrr a0,mhartid -80000050: 00051063 bnez a0,80000050 -80000054: 00000297 auipc t0,0x0 -80000058: 01028293 addi t0,t0,16 # 80000064 -8000005c: 30529073 csrw mtvec,t0 -80000060: 18005073 csrwi satp,0 -80000064: 00000297 auipc t0,0x0 -80000068: 02028293 addi t0,t0,32 # 80000084 -8000006c: 30529073 csrw mtvec,t0 -80000070: 800002b7 lui t0,0x80000 -80000074: fff28293 addi t0,t0,-1 # 7fffffff <_end+0xffffdfff> -80000078: 3b029073 csrw pmpaddr0,t0 -8000007c: 01f00293 li t0,31 -80000080: 3a029073 csrw pmpcfg0,t0 -80000084: 00000297 auipc t0,0x0 -80000088: 01828293 addi t0,t0,24 # 8000009c -8000008c: 30529073 csrw mtvec,t0 -80000090: 30205073 csrwi medeleg,0 -80000094: 30305073 csrwi mideleg,0 -80000098: 30405073 csrwi mie,0 -8000009c: 00000193 li gp,0 -800000a0: 00000297 auipc t0,0x0 -800000a4: f6428293 addi t0,t0,-156 # 80000004 -800000a8: 30529073 csrw mtvec,t0 -800000ac: 00100513 li a0,1 -800000b0: 01f51513 slli a0,a0,0x1f -800000b4: 00054c63 bltz a0,800000cc -800000b8: 0ff0000f fence -800000bc: 00100193 li gp,1 -800000c0: 05d00893 li a7,93 -800000c4: 00000513 li a0,0 -800000c8: 00000073 ecall -800000cc: 80000297 auipc t0,0x80000 -800000d0: f3428293 addi t0,t0,-204 # 0 <_start-0x80000000> -800000d4: 00028e63 beqz t0,800000f0 -800000d8: 10529073 csrw stvec,t0 -800000dc: 0000b2b7 lui t0,0xb -800000e0: 10928293 addi t0,t0,265 # b109 <_start-0x7fff4ef7> -800000e4: 30229073 csrw medeleg,t0 -800000e8: 30202373 csrr t1,medeleg -800000ec: f46298e3 bne t0,t1,8000003c -800000f0: 30005073 csrwi mstatus,0 -800000f4: 00000297 auipc t0,0x0 -800000f8: 01428293 addi t0,t0,20 # 80000108 -800000fc: 34129073 csrw mepc,t0 -80000100: f1402573 csrr a0,mhartid -80000104: 30200073 mret - -80000108 : -80000108: 00000093 li ra,0 -8000010c: 0000a713 slti a4,ra,0 -80000110: 00000e93 li t4,0 -80000114: 00200193 li gp,2 -80000118: 27d71263 bne a4,t4,8000037c - -8000011c : -8000011c: 00100093 li ra,1 -80000120: 0010a713 slti a4,ra,1 -80000124: 00000e93 li t4,0 -80000128: 00300193 li gp,3 -8000012c: 25d71863 bne a4,t4,8000037c - -80000130 : -80000130: 00300093 li ra,3 -80000134: 0070a713 slti a4,ra,7 -80000138: 00100e93 li t4,1 -8000013c: 00400193 li gp,4 -80000140: 23d71e63 bne a4,t4,8000037c - -80000144 : -80000144: 00700093 li ra,7 -80000148: 0030a713 slti a4,ra,3 -8000014c: 00000e93 li t4,0 -80000150: 00500193 li gp,5 -80000154: 23d71463 bne a4,t4,8000037c - -80000158 : -80000158: 00000093 li ra,0 -8000015c: 8000a713 slti a4,ra,-2048 -80000160: 00000e93 li t4,0 -80000164: 00600193 li gp,6 -80000168: 21d71a63 bne a4,t4,8000037c - -8000016c : -8000016c: 800000b7 lui ra,0x80000 -80000170: 0000a713 slti a4,ra,0 -80000174: 00100e93 li t4,1 -80000178: 00700193 li gp,7 -8000017c: 21d71063 bne a4,t4,8000037c - -80000180 : -80000180: 800000b7 lui ra,0x80000 -80000184: 8000a713 slti a4,ra,-2048 -80000188: 00100e93 li t4,1 -8000018c: 00800193 li gp,8 -80000190: 1fd71663 bne a4,t4,8000037c - -80000194 : -80000194: 00000093 li ra,0 -80000198: 7ff0a713 slti a4,ra,2047 -8000019c: 00100e93 li t4,1 -800001a0: 00900193 li gp,9 -800001a4: 1dd71c63 bne a4,t4,8000037c - -800001a8 : -800001a8: 800000b7 lui ra,0x80000 -800001ac: fff08093 addi ra,ra,-1 # 7fffffff <_end+0xffffdfff> -800001b0: 0000a713 slti a4,ra,0 -800001b4: 00000e93 li t4,0 -800001b8: 00a00193 li gp,10 -800001bc: 1dd71063 bne a4,t4,8000037c - -800001c0 : -800001c0: 800000b7 lui ra,0x80000 -800001c4: fff08093 addi ra,ra,-1 # 7fffffff <_end+0xffffdfff> -800001c8: 7ff0a713 slti a4,ra,2047 -800001cc: 00000e93 li t4,0 -800001d0: 00b00193 li gp,11 -800001d4: 1bd71463 bne a4,t4,8000037c - -800001d8 : -800001d8: 800000b7 lui ra,0x80000 -800001dc: 7ff0a713 slti a4,ra,2047 -800001e0: 00100e93 li t4,1 -800001e4: 00c00193 li gp,12 -800001e8: 19d71a63 bne a4,t4,8000037c - -800001ec : -800001ec: 800000b7 lui ra,0x80000 -800001f0: fff08093 addi ra,ra,-1 # 7fffffff <_end+0xffffdfff> -800001f4: 8000a713 slti a4,ra,-2048 -800001f8: 00000e93 li t4,0 -800001fc: 00d00193 li gp,13 -80000200: 17d71e63 bne a4,t4,8000037c - -80000204 : -80000204: 00000093 li ra,0 -80000208: fff0a713 slti a4,ra,-1 -8000020c: 00000e93 li t4,0 -80000210: 00e00193 li gp,14 -80000214: 17d71463 bne a4,t4,8000037c - -80000218 : -80000218: fff00093 li ra,-1 -8000021c: 0010a713 slti a4,ra,1 -80000220: 00100e93 li t4,1 -80000224: 00f00193 li gp,15 -80000228: 15d71a63 bne a4,t4,8000037c - -8000022c : -8000022c: fff00093 li ra,-1 -80000230: fff0a713 slti a4,ra,-1 -80000234: 00000e93 li t4,0 -80000238: 01000193 li gp,16 -8000023c: 15d71063 bne a4,t4,8000037c - -80000240 : -80000240: 00b00093 li ra,11 -80000244: 00d0a093 slti ra,ra,13 -80000248: 00100e93 li t4,1 -8000024c: 01100193 li gp,17 -80000250: 13d09663 bne ra,t4,8000037c - -80000254 : -80000254: 00000213 li tp,0 -80000258: 00f00093 li ra,15 -8000025c: 00a0a713 slti a4,ra,10 -80000260: 00070313 mv t1,a4 -80000264: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000268: 00200293 li t0,2 -8000026c: fe5216e3 bne tp,t0,80000258 -80000270: 00000e93 li t4,0 -80000274: 01200193 li gp,18 -80000278: 11d31263 bne t1,t4,8000037c - -8000027c : -8000027c: 00000213 li tp,0 -80000280: 00a00093 li ra,10 -80000284: 0100a713 slti a4,ra,16 -80000288: 00000013 nop -8000028c: 00070313 mv t1,a4 -80000290: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000294: 00200293 li t0,2 -80000298: fe5214e3 bne tp,t0,80000280 -8000029c: 00100e93 li t4,1 -800002a0: 01300193 li gp,19 -800002a4: 0dd31c63 bne t1,t4,8000037c - -800002a8 : -800002a8: 00000213 li tp,0 -800002ac: 01000093 li ra,16 -800002b0: 0090a713 slti a4,ra,9 -800002b4: 00000013 nop -800002b8: 00000013 nop -800002bc: 00070313 mv t1,a4 -800002c0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -800002c4: 00200293 li t0,2 -800002c8: fe5212e3 bne tp,t0,800002ac -800002cc: 00000e93 li t4,0 -800002d0: 01400193 li gp,20 -800002d4: 0bd31463 bne t1,t4,8000037c - -800002d8 : -800002d8: 00000213 li tp,0 -800002dc: 00b00093 li ra,11 -800002e0: 00f0a713 slti a4,ra,15 -800002e4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -800002e8: 00200293 li t0,2 -800002ec: fe5218e3 bne tp,t0,800002dc -800002f0: 00100e93 li t4,1 -800002f4: 01500193 li gp,21 -800002f8: 09d71263 bne a4,t4,8000037c - -800002fc : -800002fc: 00000213 li tp,0 -80000300: 01100093 li ra,17 -80000304: 00000013 nop -80000308: 0080a713 slti a4,ra,8 -8000030c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000310: 00200293 li t0,2 -80000314: fe5216e3 bne tp,t0,80000300 -80000318: 00000e93 li t4,0 -8000031c: 01600193 li gp,22 -80000320: 05d71e63 bne a4,t4,8000037c - -80000324 : -80000324: 00000213 li tp,0 -80000328: 00c00093 li ra,12 -8000032c: 00000013 nop -80000330: 00000013 nop -80000334: 00e0a713 slti a4,ra,14 -80000338: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -8000033c: 00200293 li t0,2 -80000340: fe5214e3 bne tp,t0,80000328 -80000344: 00100e93 li t4,1 -80000348: 01700193 li gp,23 -8000034c: 03d71863 bne a4,t4,8000037c - -80000350 : -80000350: fff02093 slti ra,zero,-1 -80000354: 00000e93 li t4,0 -80000358: 01800193 li gp,24 -8000035c: 03d09063 bne ra,t4,8000037c - -80000360 : -80000360: 00ff00b7 lui ra,0xff0 -80000364: 0ff08093 addi ra,ra,255 # ff00ff <_start-0x7f00ff01> -80000368: fff0a013 slti zero,ra,-1 -8000036c: 00000e93 li t4,0 -80000370: 01900193 li gp,25 -80000374: 01d01463 bne zero,t4,8000037c -80000378: 02301063 bne zero,gp,80000398 - -8000037c : -8000037c: 0ff0000f fence -80000380: 00018063 beqz gp,80000380 -80000384: 00119193 slli gp,gp,0x1 -80000388: 0011e193 ori gp,gp,1 -8000038c: 05d00893 li a7,93 -80000390: 00018513 mv a0,gp -80000394: 00000073 ecall - -80000398 : -80000398: 0ff0000f fence -8000039c: 00100193 li gp,1 -800003a0: 05d00893 li a7,93 -800003a4: 00000513 li a0,0 -800003a8: 00000073 ecall -800003ac: c0001073 unimp -800003b0: 0000 unimp -800003b2: 0000 unimp -800003b4: 0000 unimp -800003b6: 0000 unimp -800003b8: 0000 unimp -800003ba: 0000 unimp -800003bc: 0000 unimp -800003be: 0000 unimp -800003c0: 0000 unimp -800003c2: 0000 unimp diff --git a/benchmarks/riscv_tests/rv32ui-p-slti.hex b/benchmarks/riscv_tests/rv32ui-p-slti.hex deleted file mode 100644 index 8f6fdbbf..00000000 --- a/benchmarks/riscv_tests/rv32ui-p-slti.hex +++ /dev/null @@ -1,65 +0,0 @@ -:0200000480007A -:100000006F00C004732F2034930F8000630AFF0336 -:10001000930F90006306FF03930FB0006302FF038A -:10002000170F0080130F0FFE63040F0067000F000F -:10003000732F203463540F006F004000136E9E53E3 -:10004000171F00002320CFFD6FF09FFF732540F1A5 -:100050006310050073251030635805000F00F00F82 -:10006000130E100073000000130E00009702000032 -:10007000938282F973905230735020307350303035 -:1000800073504030970200809382C2F7638C020065 -:10009000739052109302B01A739022307323203061 -:1000A000E39E62F873500030970200009382420191 -:1000B00073901234732540F17300203093000000D8 -:1000C00093A10000930E0000130E20006392D1272D -:1000D0009300100093A11000930E0000130E300047 -:1000E0006398D1259300300093A17000930E100007 -:1000F000130E4000639ED1239300700093A1300043 -:10010000930E0000130E50006394D123930000005F -:1001100093A10080930E0000130E6000639AD1211A -:10012000B700008093A10000930E1000130E700022 -:100130006390D121B700008093A10080930E10003E -:10014000130E80006396D11F9300000093A1F07FEF -:10015000930E1000130E9000639CD11DB700008019 -:100160009380F0FF93A10000930E0000130EA000F7 -:100170006390D11DB70000809380F0FF93A1F07FC2 -:10018000930E0000130EB0006394D11BB7000080E3 -:1001900093A1F07F930E1000130EC000639AD11943 -:1001A000B70000809380F0FF93A10080930E0000C1 -:1001B000130ED000639ED1179300000093A1F0FFAF -:1001C000930E0000130EE0006394D1179300F0FF2C -:1001D00093A11000930E1000130EF000639AD11536 -:1001E0009300F0FF93A1F0FF930E0000130E0001A7 -:1001F0006390D1159300B00093A0D000930E10002F -:10020000130E10016396D013130200009300F00048 -:1002100093A1A00013830100130212009302200097 -:10022000E31652FE930E0000130E20016312D31149 -:10023000130200009300A00093A10001130000002E -:10024000138301001302120093022000E31452FEF4 -:10025000930E1000130E3001631CD30D1302000027 -:100260009300000193A19000130000001300000010 -:10027000138301001302120093022000E31252FEC6 -:10028000930E0000130E40016314D30B1302000001 -:100290009300B00093A1F00013021200930220001B -:1002A000E31852FE930E1000130E50016392D10911 -:1002B00013020000930010011300000093A18000BE -:1002C0001302120093022000E31652FE930E000068 -:1002D000130E6001639ED105130200009300C0005D -:1002E000130000001300000093A1E00013021200AD -:1002F00093022000E31452FE930E1000130E7001BF -:100300006398D1039320F0FF930E0000130E800139 -:100310006390D003B700FF009380F00F13A0F0FFAD -:10032000930E0000130E90016314D001631CC001F2 -:100330000F00F00F63000E00131E1E00136E1E0050 -:10034000730000000F00F00F130E10007300000088 -:10035000731000C00000000000000000000000005A -:10036000000000000000000000000000000000008D -:10037000000000000000000000000000000000007D -:040380000000000079 -:1010000000000000000000000000000000000000E0 -:1010100000000000000000000000000000000000D0 -:1010200000000000000000000000000000000000C0 -:1010300000000000000000000000000000000000B0 -:081040000000000000000000A8 -:040000058000200057 -:00000001FF diff --git a/benchmarks/riscv_tests/rv32ui-p-sltiu.dump b/benchmarks/riscv_tests/rv32ui-p-sltiu.dump deleted file mode 100644 index 06756139..00000000 --- a/benchmarks/riscv_tests/rv32ui-p-sltiu.dump +++ /dev/null @@ -1,320 +0,0 @@ - -rv32ui-p-sltiu: file format elf32-littleriscv - - -Disassembly of section .text.init: - -80000000 <_start>: -80000000: 04c0006f j 8000004c - -80000004 : -80000004: 34202f73 csrr t5,mcause -80000008: 00800f93 li t6,8 -8000000c: 03ff0a63 beq t5,t6,80000040 -80000010: 00900f93 li t6,9 -80000014: 03ff0663 beq t5,t6,80000040 -80000018: 00b00f93 li t6,11 -8000001c: 03ff0263 beq t5,t6,80000040 -80000020: 80000f17 auipc t5,0x80000 -80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> -80000028: 000f0463 beqz t5,80000030 -8000002c: 000f0067 jr t5 -80000030: 34202f73 csrr t5,mcause -80000034: 000f5463 bgez t5,8000003c -80000038: 0040006f j 8000003c - -8000003c : -8000003c: 5391e193 ori gp,gp,1337 - -80000040 : -80000040: 00001f17 auipc t5,0x1 -80000044: fc3f2023 sw gp,-64(t5) # 80001000 -80000048: ff9ff06f j 80000040 - -8000004c : -8000004c: f1402573 csrr a0,mhartid -80000050: 00051063 bnez a0,80000050 -80000054: 00000297 auipc t0,0x0 -80000058: 01028293 addi t0,t0,16 # 80000064 -8000005c: 30529073 csrw mtvec,t0 -80000060: 18005073 csrwi sptbr,0 -80000064: 00000297 auipc t0,0x0 -80000068: 01c28293 addi t0,t0,28 # 80000080 -8000006c: 30529073 csrw mtvec,t0 -80000070: fff00293 li t0,-1 -80000074: 3b029073 csrw pmpaddr0,t0 -80000078: 01f00293 li t0,31 -8000007c: 3a029073 csrw pmpcfg0,t0 -80000080: 00000297 auipc t0,0x0 -80000084: 01828293 addi t0,t0,24 # 80000098 -80000088: 30529073 csrw mtvec,t0 -8000008c: 30205073 csrwi medeleg,0 -80000090: 30305073 csrwi mideleg,0 -80000094: 30405073 csrwi mie,0 -80000098: 00000193 li gp,0 -8000009c: 00000297 auipc t0,0x0 -800000a0: f6828293 addi t0,t0,-152 # 80000004 -800000a4: 30529073 csrw mtvec,t0 -800000a8: 00100513 li a0,1 -800000ac: 01f51513 slli a0,a0,0x1f -800000b0: 00054863 bltz a0,800000c0 -800000b4: 0ff0000f fence -800000b8: 00100193 li gp,1 -800000bc: 00000073 ecall -800000c0: 80000297 auipc t0,0x80000 -800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> -800000c8: 00028e63 beqz t0,800000e4 -800000cc: 10529073 csrw stvec,t0 -800000d0: 0000b2b7 lui t0,0xb -800000d4: 10928293 addi t0,t0,265 # b109 <_start-0x7fff4ef7> -800000d8: 30229073 csrw medeleg,t0 -800000dc: 30202373 csrr t1,medeleg -800000e0: f4629ee3 bne t0,t1,8000003c -800000e4: 30005073 csrwi mstatus,0 -800000e8: 00000297 auipc t0,0x0 -800000ec: 01428293 addi t0,t0,20 # 800000fc -800000f0: 34129073 csrw mepc,t0 -800000f4: f1402573 csrr a0,mhartid -800000f8: 30200073 mret - -800000fc : -800000fc: 00000093 li ra,0 -80000100: 0000bf13 sltiu t5,ra,0 -80000104: 00000e93 li t4,0 -80000108: 00200193 li gp,2 -8000010c: 27df1263 bne t5,t4,80000370 - -80000110 : -80000110: 00100093 li ra,1 -80000114: 0010bf13 seqz t5,ra -80000118: 00000e93 li t4,0 -8000011c: 00300193 li gp,3 -80000120: 25df1863 bne t5,t4,80000370 - -80000124 : -80000124: 00300093 li ra,3 -80000128: 0070bf13 sltiu t5,ra,7 -8000012c: 00100e93 li t4,1 -80000130: 00400193 li gp,4 -80000134: 23df1e63 bne t5,t4,80000370 - -80000138 : -80000138: 00700093 li ra,7 -8000013c: 0030bf13 sltiu t5,ra,3 -80000140: 00000e93 li t4,0 -80000144: 00500193 li gp,5 -80000148: 23df1463 bne t5,t4,80000370 - -8000014c : -8000014c: 00000093 li ra,0 -80000150: 8000bf13 sltiu t5,ra,-2048 -80000154: 00100e93 li t4,1 -80000158: 00600193 li gp,6 -8000015c: 21df1a63 bne t5,t4,80000370 - -80000160 : -80000160: 800000b7 lui ra,0x80000 -80000164: 0000bf13 sltiu t5,ra,0 -80000168: 00000e93 li t4,0 -8000016c: 00700193 li gp,7 -80000170: 21df1063 bne t5,t4,80000370 - -80000174 : -80000174: 800000b7 lui ra,0x80000 -80000178: 8000bf13 sltiu t5,ra,-2048 -8000017c: 00100e93 li t4,1 -80000180: 00800193 li gp,8 -80000184: 1fdf1663 bne t5,t4,80000370 - -80000188 : -80000188: 00000093 li ra,0 -8000018c: 7ff0bf13 sltiu t5,ra,2047 -80000190: 00100e93 li t4,1 -80000194: 00900193 li gp,9 -80000198: 1ddf1c63 bne t5,t4,80000370 - -8000019c : -8000019c: 800000b7 lui ra,0x80000 -800001a0: fff08093 addi ra,ra,-1 # 7fffffff -800001a4: 0000bf13 sltiu t5,ra,0 -800001a8: 00000e93 li t4,0 -800001ac: 00a00193 li gp,10 -800001b0: 1ddf1063 bne t5,t4,80000370 - -800001b4 : -800001b4: 800000b7 lui ra,0x80000 -800001b8: fff08093 addi ra,ra,-1 # 7fffffff -800001bc: 7ff0bf13 sltiu t5,ra,2047 -800001c0: 00000e93 li t4,0 -800001c4: 00b00193 li gp,11 -800001c8: 1bdf1463 bne t5,t4,80000370 - -800001cc : -800001cc: 800000b7 lui ra,0x80000 -800001d0: 7ff0bf13 sltiu t5,ra,2047 -800001d4: 00000e93 li t4,0 -800001d8: 00c00193 li gp,12 -800001dc: 19df1a63 bne t5,t4,80000370 - -800001e0 : -800001e0: 800000b7 lui ra,0x80000 -800001e4: fff08093 addi ra,ra,-1 # 7fffffff -800001e8: 8000bf13 sltiu t5,ra,-2048 -800001ec: 00100e93 li t4,1 -800001f0: 00d00193 li gp,13 -800001f4: 17df1e63 bne t5,t4,80000370 - -800001f8 : -800001f8: 00000093 li ra,0 -800001fc: fff0bf13 sltiu t5,ra,-1 -80000200: 00100e93 li t4,1 -80000204: 00e00193 li gp,14 -80000208: 17df1463 bne t5,t4,80000370 - -8000020c : -8000020c: fff00093 li ra,-1 -80000210: 0010bf13 seqz t5,ra -80000214: 00000e93 li t4,0 -80000218: 00f00193 li gp,15 -8000021c: 15df1a63 bne t5,t4,80000370 - -80000220 : -80000220: fff00093 li ra,-1 -80000224: fff0bf13 sltiu t5,ra,-1 -80000228: 00000e93 li t4,0 -8000022c: 01000193 li gp,16 -80000230: 15df1063 bne t5,t4,80000370 - -80000234 : -80000234: 00b00093 li ra,11 -80000238: 00d0b093 sltiu ra,ra,13 -8000023c: 00100e93 li t4,1 -80000240: 01100193 li gp,17 -80000244: 13d09663 bne ra,t4,80000370 - -80000248 : -80000248: 00000213 li tp,0 -8000024c: 00f00093 li ra,15 -80000250: 00a0bf13 sltiu t5,ra,10 -80000254: 000f0313 mv t1,t5 -80000258: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -8000025c: 00200293 li t0,2 -80000260: fe5216e3 bne tp,t0,8000024c -80000264: 00000e93 li t4,0 -80000268: 01200193 li gp,18 -8000026c: 11d31263 bne t1,t4,80000370 - -80000270 : -80000270: 00000213 li tp,0 -80000274: 00a00093 li ra,10 -80000278: 0100bf13 sltiu t5,ra,16 -8000027c: 00000013 nop -80000280: 000f0313 mv t1,t5 -80000284: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000288: 00200293 li t0,2 -8000028c: fe5214e3 bne tp,t0,80000274 -80000290: 00100e93 li t4,1 -80000294: 01300193 li gp,19 -80000298: 0dd31c63 bne t1,t4,80000370 - -8000029c : -8000029c: 00000213 li tp,0 -800002a0: 01000093 li ra,16 -800002a4: 0090bf13 sltiu t5,ra,9 -800002a8: 00000013 nop -800002ac: 00000013 nop -800002b0: 000f0313 mv t1,t5 -800002b4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -800002b8: 00200293 li t0,2 -800002bc: fe5212e3 bne tp,t0,800002a0 -800002c0: 00000e93 li t4,0 -800002c4: 01400193 li gp,20 -800002c8: 0bd31463 bne t1,t4,80000370 - -800002cc : -800002cc: 00000213 li tp,0 -800002d0: 00b00093 li ra,11 -800002d4: 00f0bf13 sltiu t5,ra,15 -800002d8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -800002dc: 00200293 li t0,2 -800002e0: fe5218e3 bne tp,t0,800002d0 -800002e4: 00100e93 li t4,1 -800002e8: 01500193 li gp,21 -800002ec: 09df1263 bne t5,t4,80000370 - -800002f0 : -800002f0: 00000213 li tp,0 -800002f4: 01100093 li ra,17 -800002f8: 00000013 nop -800002fc: 0080bf13 sltiu t5,ra,8 -80000300: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000304: 00200293 li t0,2 -80000308: fe5216e3 bne tp,t0,800002f4 -8000030c: 00000e93 li t4,0 -80000310: 01600193 li gp,22 -80000314: 05df1e63 bne t5,t4,80000370 - -80000318 : -80000318: 00000213 li tp,0 -8000031c: 00c00093 li ra,12 -80000320: 00000013 nop -80000324: 00000013 nop -80000328: 00e0bf13 sltiu t5,ra,14 -8000032c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000330: 00200293 li t0,2 -80000334: fe5214e3 bne tp,t0,8000031c -80000338: 00100e93 li t4,1 -8000033c: 01700193 li gp,23 -80000340: 03df1863 bne t5,t4,80000370 - -80000344 : -80000344: fff03093 sltiu ra,zero,-1 -80000348: 00100e93 li t4,1 -8000034c: 01800193 li gp,24 -80000350: 03d09063 bne ra,t4,80000370 - -80000354 : -80000354: 00ff00b7 lui ra,0xff0 -80000358: 0ff08093 addi ra,ra,255 # ff00ff <_start-0x7f00ff01> -8000035c: fff0b013 sltiu zero,ra,-1 -80000360: 00000e93 li t4,0 -80000364: 01900193 li gp,25 -80000368: 01d01463 bne zero,t4,80000370 -8000036c: 00301c63 bne zero,gp,80000384 - -80000370 : -80000370: 0ff0000f fence -80000374: 00018063 beqz gp,80000374 -80000378: 00119193 slli gp,gp,0x1 -8000037c: 0011e193 ori gp,gp,1 -80000380: 00000073 ecall - -80000384 : -80000384: 0ff0000f fence -80000388: 00100193 li gp,1 -8000038c: 00000073 ecall -80000390: c0001073 unimp -80000394: 0000 unimp -80000396: 0000 unimp -80000398: 0000 unimp -8000039a: 0000 unimp -8000039c: 0000 unimp -8000039e: 0000 unimp -800003a0: 0000 unimp -800003a2: 0000 unimp -800003a4: 0000 unimp -800003a6: 0000 unimp -800003a8: 0000 unimp -800003aa: 0000 unimp -800003ac: 0000 unimp -800003ae: 0000 unimp -800003b0: 0000 unimp -800003b2: 0000 unimp -800003b4: 0000 unimp -800003b6: 0000 unimp -800003b8: 0000 unimp -800003ba: 0000 unimp -800003bc: 0000 unimp -800003be: 0000 unimp -800003c0: 0000 unimp -800003c2: 0000 unimp diff --git a/benchmarks/riscv_tests/rv32ui-p-sltiu.hex b/benchmarks/riscv_tests/rv32ui-p-sltiu.hex deleted file mode 100644 index 7d9a537d..00000000 --- a/benchmarks/riscv_tests/rv32ui-p-sltiu.hex +++ /dev/null @@ -1,65 +0,0 @@ -:0200000480007A -:100000006F00C004732F2034930F8000630AFF0336 -:10001000930F90006306FF03930FB0006302FF038A -:10002000170F0080130F0FFE63040F0067000F000F -:10003000732F203463540F006F004000136E9E53E3 -:10004000171F00002320CFFD6FF09FFF732540F1A5 -:100050006310050073251030635805000F00F00F82 -:10006000130E100073000000130E00009702000032 -:10007000938282F973905230735020307350303035 -:1000800073504030970200809382C2F7638C020065 -:10009000739052109302B01A739022307323203061 -:1000A000E39E62F873500030970200009382420191 -:1000B00073901234732540F17300203093000000D8 -:1000C00093B10000930E0000130E20006392D1271D -:1000D0009300100093B11000930E0000130E300037 -:1000E0006398D1259300300093B17000930E1000F7 -:1000F000130E4000639ED1239300700093B1300033 -:10010000930E0000130E50006394D123930000005F -:1001100093B10080930E1000130E6000639AD121FA -:10012000B700008093B10000930E0000130E700022 -:100130006390D121B700008093B10080930E10002E -:10014000130E80006396D11F9300000093B1F07FDF -:10015000930E1000130E9000639CD11DB700008019 -:100160009380F0FF93B10000930E0000130EA000E7 -:100170006390D11DB70000809380F0FF93B1F07FB2 -:10018000930E0000130EB0006394D11BB7000080E3 -:1001900093B1F07F930E0000130EC000639AD11943 -:1001A000B70000809380F0FF93B10080930E1000A1 -:1001B000130ED000639ED1179300000093B1F0FF9F -:1001C000930E1000130EE0006394D1179300F0FF1C -:1001D00093B11000930E0000130EF000639AD11536 -:1001E0009300F0FF93B1F0FF930E0000130E000197 -:1001F0006390D1159300B00093B0D000930E10001F -:10020000130E10016396D013130200009300F00048 -:1002100093B1A00013830100130212009302200087 -:10022000E31652FE930E0000130E20016312D31149 -:10023000130200009300A00093B10001130000001E -:10024000138301001302120093022000E31452FEF4 -:10025000930E1000130E3001631CD30D1302000027 -:100260009300000193B19000130000001300000000 -:10027000138301001302120093022000E31252FEC6 -:10028000930E0000130E40016314D30B1302000001 -:100290009300B00093B1F00013021200930220000B -:1002A000E31852FE930E1000130E50016392D10911 -:1002B00013020000930010011300000093B18000AE -:1002C0001302120093022000E31652FE930E000068 -:1002D000130E6001639ED105130200009300C0005D -:1002E000130000001300000093B1E000130212009D -:1002F00093022000E31452FE930E1000130E7001BF -:100300006398D1039330F0FF930E1000130E800119 -:100310006390D003B700FF009380F00F13B0F0FF9D -:10032000930E0000130E90016314D001631CC001F2 -:100330000F00F00F63000E00131E1E00136E1E0050 -:10034000730000000F00F00F130E10007300000088 -:10035000731000C00000000000000000000000005A -:10036000000000000000000000000000000000008D -:10037000000000000000000000000000000000007D -:040380000000000079 -:1010000000000000000000000000000000000000E0 -:1010100000000000000000000000000000000000D0 -:1010200000000000000000000000000000000000C0 -:1010300000000000000000000000000000000000B0 -:081040000000000000000000A8 -:040000058000200057 -:00000001FF diff --git a/benchmarks/riscv_tests/rv32ui-p-sltu.dump b/benchmarks/riscv_tests/rv32ui-p-sltu.dump deleted file mode 100644 index bd6d0fe6..00000000 --- a/benchmarks/riscv_tests/rv32ui-p-sltu.dump +++ /dev/null @@ -1,485 +0,0 @@ - -rv32ui-p-sltu: file format elf32-littleriscv - - -Disassembly of section .text.init: - -80000000 <_start>: -80000000: 04c0006f j 8000004c - -80000004 : -80000004: 34202f73 csrr t5,mcause -80000008: 00800f93 li t6,8 -8000000c: 03ff0a63 beq t5,t6,80000040 -80000010: 00900f93 li t6,9 -80000014: 03ff0663 beq t5,t6,80000040 -80000018: 00b00f93 li t6,11 -8000001c: 03ff0263 beq t5,t6,80000040 -80000020: 80000f17 auipc t5,0x80000 -80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> -80000028: 000f0463 beqz t5,80000030 -8000002c: 000f0067 jr t5 -80000030: 34202f73 csrr t5,mcause -80000034: 000f5463 bgez t5,8000003c -80000038: 0040006f j 8000003c - -8000003c : -8000003c: 5391e193 ori gp,gp,1337 - -80000040 : -80000040: 00001f17 auipc t5,0x1 -80000044: fc3f2023 sw gp,-64(t5) # 80001000 -80000048: ff9ff06f j 80000040 - -8000004c : -8000004c: f1402573 csrr a0,mhartid -80000050: 00051063 bnez a0,80000050 -80000054: 00000297 auipc t0,0x0 -80000058: 01028293 addi t0,t0,16 # 80000064 -8000005c: 30529073 csrw mtvec,t0 -80000060: 18005073 csrwi sptbr,0 -80000064: 00000297 auipc t0,0x0 -80000068: 01c28293 addi t0,t0,28 # 80000080 -8000006c: 30529073 csrw mtvec,t0 -80000070: fff00293 li t0,-1 -80000074: 3b029073 csrw pmpaddr0,t0 -80000078: 01f00293 li t0,31 -8000007c: 3a029073 csrw pmpcfg0,t0 -80000080: 00000297 auipc t0,0x0 -80000084: 01828293 addi t0,t0,24 # 80000098 -80000088: 30529073 csrw mtvec,t0 -8000008c: 30205073 csrwi medeleg,0 -80000090: 30305073 csrwi mideleg,0 -80000094: 30405073 csrwi mie,0 -80000098: 00000193 li gp,0 -8000009c: 00000297 auipc t0,0x0 -800000a0: f6828293 addi t0,t0,-152 # 80000004 -800000a4: 30529073 csrw mtvec,t0 -800000a8: 00100513 li a0,1 -800000ac: 01f51513 slli a0,a0,0x1f -800000b0: 00054863 bltz a0,800000c0 -800000b4: 0ff0000f fence -800000b8: 00100193 li gp,1 -800000bc: 00000073 ecall -800000c0: 80000297 auipc t0,0x80000 -800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> -800000c8: 00028e63 beqz t0,800000e4 -800000cc: 10529073 csrw stvec,t0 -800000d0: 0000b2b7 lui t0,0xb -800000d4: 10928293 addi t0,t0,265 # b109 <_start-0x7fff4ef7> -800000d8: 30229073 csrw medeleg,t0 -800000dc: 30202373 csrr t1,medeleg -800000e0: f4629ee3 bne t0,t1,8000003c -800000e4: 30005073 csrwi mstatus,0 -800000e8: 00000297 auipc t0,0x0 -800000ec: 01428293 addi t0,t0,20 # 800000fc -800000f0: 34129073 csrw mepc,t0 -800000f4: f1402573 csrr a0,mhartid -800000f8: 30200073 mret - -800000fc : -800000fc: 00000093 li ra,0 -80000100: 00000113 li sp,0 -80000104: 0020bf33 sltu t5,ra,sp -80000108: 00000e93 li t4,0 -8000010c: 00200193 li gp,2 -80000110: 4bdf1a63 bne t5,t4,800005c4 - -80000114 : -80000114: 00100093 li ra,1 -80000118: 00100113 li sp,1 -8000011c: 0020bf33 sltu t5,ra,sp -80000120: 00000e93 li t4,0 -80000124: 00300193 li gp,3 -80000128: 49df1e63 bne t5,t4,800005c4 - -8000012c : -8000012c: 00300093 li ra,3 -80000130: 00700113 li sp,7 -80000134: 0020bf33 sltu t5,ra,sp -80000138: 00100e93 li t4,1 -8000013c: 00400193 li gp,4 -80000140: 49df1263 bne t5,t4,800005c4 - -80000144 : -80000144: 00700093 li ra,7 -80000148: 00300113 li sp,3 -8000014c: 0020bf33 sltu t5,ra,sp -80000150: 00000e93 li t4,0 -80000154: 00500193 li gp,5 -80000158: 47df1663 bne t5,t4,800005c4 - -8000015c : -8000015c: 00000093 li ra,0 -80000160: ffff8137 lui sp,0xffff8 -80000164: 0020bf33 sltu t5,ra,sp -80000168: 00100e93 li t4,1 -8000016c: 00600193 li gp,6 -80000170: 45df1a63 bne t5,t4,800005c4 - -80000174 : -80000174: 800000b7 lui ra,0x80000 -80000178: 00000113 li sp,0 -8000017c: 0020bf33 sltu t5,ra,sp -80000180: 00000e93 li t4,0 -80000184: 00700193 li gp,7 -80000188: 43df1e63 bne t5,t4,800005c4 - -8000018c : -8000018c: 800000b7 lui ra,0x80000 -80000190: ffff8137 lui sp,0xffff8 -80000194: 0020bf33 sltu t5,ra,sp -80000198: 00100e93 li t4,1 -8000019c: 00800193 li gp,8 -800001a0: 43df1263 bne t5,t4,800005c4 - -800001a4 : -800001a4: 00000093 li ra,0 -800001a8: 00008137 lui sp,0x8 -800001ac: fff10113 addi sp,sp,-1 # 7fff <_start-0x7fff8001> -800001b0: 0020bf33 sltu t5,ra,sp -800001b4: 00100e93 li t4,1 -800001b8: 00900193 li gp,9 -800001bc: 41df1463 bne t5,t4,800005c4 - -800001c0 : -800001c0: 800000b7 lui ra,0x80000 -800001c4: fff08093 addi ra,ra,-1 # 7fffffff -800001c8: 00000113 li sp,0 -800001cc: 0020bf33 sltu t5,ra,sp -800001d0: 00000e93 li t4,0 -800001d4: 00a00193 li gp,10 -800001d8: 3fdf1663 bne t5,t4,800005c4 - -800001dc : -800001dc: 800000b7 lui ra,0x80000 -800001e0: fff08093 addi ra,ra,-1 # 7fffffff -800001e4: 00008137 lui sp,0x8 -800001e8: fff10113 addi sp,sp,-1 # 7fff <_start-0x7fff8001> -800001ec: 0020bf33 sltu t5,ra,sp -800001f0: 00000e93 li t4,0 -800001f4: 00b00193 li gp,11 -800001f8: 3ddf1663 bne t5,t4,800005c4 - -800001fc : -800001fc: 800000b7 lui ra,0x80000 -80000200: 00008137 lui sp,0x8 -80000204: fff10113 addi sp,sp,-1 # 7fff <_start-0x7fff8001> -80000208: 0020bf33 sltu t5,ra,sp -8000020c: 00000e93 li t4,0 -80000210: 00c00193 li gp,12 -80000214: 3bdf1863 bne t5,t4,800005c4 - -80000218 : -80000218: 800000b7 lui ra,0x80000 -8000021c: fff08093 addi ra,ra,-1 # 7fffffff -80000220: ffff8137 lui sp,0xffff8 -80000224: 0020bf33 sltu t5,ra,sp -80000228: 00100e93 li t4,1 -8000022c: 00d00193 li gp,13 -80000230: 39df1a63 bne t5,t4,800005c4 - -80000234 : -80000234: 00000093 li ra,0 -80000238: fff00113 li sp,-1 -8000023c: 0020bf33 sltu t5,ra,sp -80000240: 00100e93 li t4,1 -80000244: 00e00193 li gp,14 -80000248: 37df1e63 bne t5,t4,800005c4 - -8000024c : -8000024c: fff00093 li ra,-1 -80000250: 00100113 li sp,1 -80000254: 0020bf33 sltu t5,ra,sp -80000258: 00000e93 li t4,0 -8000025c: 00f00193 li gp,15 -80000260: 37df1263 bne t5,t4,800005c4 - -80000264 : -80000264: fff00093 li ra,-1 -80000268: fff00113 li sp,-1 -8000026c: 0020bf33 sltu t5,ra,sp -80000270: 00000e93 li t4,0 -80000274: 01000193 li gp,16 -80000278: 35df1663 bne t5,t4,800005c4 - -8000027c : -8000027c: 00e00093 li ra,14 -80000280: 00d00113 li sp,13 -80000284: 0020b0b3 sltu ra,ra,sp -80000288: 00000e93 li t4,0 -8000028c: 01100193 li gp,17 -80000290: 33d09a63 bne ra,t4,800005c4 - -80000294 : -80000294: 00b00093 li ra,11 -80000298: 00d00113 li sp,13 -8000029c: 0020b133 sltu sp,ra,sp -800002a0: 00100e93 li t4,1 -800002a4: 01200193 li gp,18 -800002a8: 31d11e63 bne sp,t4,800005c4 - -800002ac : -800002ac: 00d00093 li ra,13 -800002b0: 0010b0b3 sltu ra,ra,ra -800002b4: 00000e93 li t4,0 -800002b8: 01300193 li gp,19 -800002bc: 31d09463 bne ra,t4,800005c4 - -800002c0 : -800002c0: 00000213 li tp,0 -800002c4: 00b00093 li ra,11 -800002c8: 00d00113 li sp,13 -800002cc: 0020bf33 sltu t5,ra,sp -800002d0: 000f0313 mv t1,t5 -800002d4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -800002d8: 00200293 li t0,2 -800002dc: fe5214e3 bne tp,t0,800002c4 -800002e0: 00100e93 li t4,1 -800002e4: 01400193 li gp,20 -800002e8: 2dd31e63 bne t1,t4,800005c4 - -800002ec : -800002ec: 00000213 li tp,0 -800002f0: 00e00093 li ra,14 -800002f4: 00d00113 li sp,13 -800002f8: 0020bf33 sltu t5,ra,sp -800002fc: 00000013 nop -80000300: 000f0313 mv t1,t5 -80000304: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000308: 00200293 li t0,2 -8000030c: fe5212e3 bne tp,t0,800002f0 -80000310: 00000e93 li t4,0 -80000314: 01500193 li gp,21 -80000318: 2bd31663 bne t1,t4,800005c4 - -8000031c : -8000031c: 00000213 li tp,0 -80000320: 00c00093 li ra,12 -80000324: 00d00113 li sp,13 -80000328: 0020bf33 sltu t5,ra,sp -8000032c: 00000013 nop -80000330: 00000013 nop -80000334: 000f0313 mv t1,t5 -80000338: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -8000033c: 00200293 li t0,2 -80000340: fe5210e3 bne tp,t0,80000320 -80000344: 00100e93 li t4,1 -80000348: 01600193 li gp,22 -8000034c: 27d31c63 bne t1,t4,800005c4 - -80000350 : -80000350: 00000213 li tp,0 -80000354: 00e00093 li ra,14 -80000358: 00d00113 li sp,13 -8000035c: 0020bf33 sltu t5,ra,sp -80000360: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000364: 00200293 li t0,2 -80000368: fe5216e3 bne tp,t0,80000354 -8000036c: 00000e93 li t4,0 -80000370: 01700193 li gp,23 -80000374: 25df1863 bne t5,t4,800005c4 - -80000378 : -80000378: 00000213 li tp,0 -8000037c: 00b00093 li ra,11 -80000380: 00d00113 li sp,13 -80000384: 00000013 nop -80000388: 0020bf33 sltu t5,ra,sp -8000038c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000390: 00200293 li t0,2 -80000394: fe5214e3 bne tp,t0,8000037c -80000398: 00100e93 li t4,1 -8000039c: 01800193 li gp,24 -800003a0: 23df1263 bne t5,t4,800005c4 - -800003a4 : -800003a4: 00000213 li tp,0 -800003a8: 00f00093 li ra,15 -800003ac: 00d00113 li sp,13 -800003b0: 00000013 nop -800003b4: 00000013 nop -800003b8: 0020bf33 sltu t5,ra,sp -800003bc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -800003c0: 00200293 li t0,2 -800003c4: fe5212e3 bne tp,t0,800003a8 -800003c8: 00000e93 li t4,0 -800003cc: 01900193 li gp,25 -800003d0: 1fdf1a63 bne t5,t4,800005c4 - -800003d4 : -800003d4: 00000213 li tp,0 -800003d8: 00a00093 li ra,10 -800003dc: 00000013 nop -800003e0: 00d00113 li sp,13 -800003e4: 0020bf33 sltu t5,ra,sp -800003e8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -800003ec: 00200293 li t0,2 -800003f0: fe5214e3 bne tp,t0,800003d8 -800003f4: 00100e93 li t4,1 -800003f8: 01a00193 li gp,26 -800003fc: 1ddf1463 bne t5,t4,800005c4 - -80000400 : -80000400: 00000213 li tp,0 -80000404: 01000093 li ra,16 -80000408: 00000013 nop -8000040c: 00d00113 li sp,13 -80000410: 00000013 nop -80000414: 0020bf33 sltu t5,ra,sp -80000418: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -8000041c: 00200293 li t0,2 -80000420: fe5212e3 bne tp,t0,80000404 -80000424: 00000e93 li t4,0 -80000428: 01b00193 li gp,27 -8000042c: 19df1c63 bne t5,t4,800005c4 - -80000430 : -80000430: 00000213 li tp,0 -80000434: 00900093 li ra,9 -80000438: 00000013 nop -8000043c: 00000013 nop -80000440: 00d00113 li sp,13 -80000444: 0020bf33 sltu t5,ra,sp -80000448: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -8000044c: 00200293 li t0,2 -80000450: fe5212e3 bne tp,t0,80000434 -80000454: 00100e93 li t4,1 -80000458: 01c00193 li gp,28 -8000045c: 17df1463 bne t5,t4,800005c4 - -80000460 : -80000460: 00000213 li tp,0 -80000464: 00d00113 li sp,13 -80000468: 01100093 li ra,17 -8000046c: 0020bf33 sltu t5,ra,sp -80000470: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000474: 00200293 li t0,2 -80000478: fe5216e3 bne tp,t0,80000464 -8000047c: 00000e93 li t4,0 -80000480: 01d00193 li gp,29 -80000484: 15df1063 bne t5,t4,800005c4 - -80000488 : -80000488: 00000213 li tp,0 -8000048c: 00d00113 li sp,13 -80000490: 00800093 li ra,8 -80000494: 00000013 nop -80000498: 0020bf33 sltu t5,ra,sp -8000049c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -800004a0: 00200293 li t0,2 -800004a4: fe5214e3 bne tp,t0,8000048c -800004a8: 00100e93 li t4,1 -800004ac: 01e00193 li gp,30 -800004b0: 11df1a63 bne t5,t4,800005c4 - -800004b4 : -800004b4: 00000213 li tp,0 -800004b8: 00d00113 li sp,13 -800004bc: 01200093 li ra,18 -800004c0: 00000013 nop -800004c4: 00000013 nop -800004c8: 0020bf33 sltu t5,ra,sp -800004cc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -800004d0: 00200293 li t0,2 -800004d4: fe5212e3 bne tp,t0,800004b8 -800004d8: 00000e93 li t4,0 -800004dc: 01f00193 li gp,31 -800004e0: 0fdf1263 bne t5,t4,800005c4 - -800004e4 : -800004e4: 00000213 li tp,0 -800004e8: 00d00113 li sp,13 -800004ec: 00000013 nop -800004f0: 00700093 li ra,7 -800004f4: 0020bf33 sltu t5,ra,sp -800004f8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -800004fc: 00200293 li t0,2 -80000500: fe5214e3 bne tp,t0,800004e8 -80000504: 00100e93 li t4,1 -80000508: 02000193 li gp,32 -8000050c: 0bdf1c63 bne t5,t4,800005c4 - -80000510 : -80000510: 00000213 li tp,0 -80000514: 00d00113 li sp,13 -80000518: 00000013 nop -8000051c: 01300093 li ra,19 -80000520: 00000013 nop -80000524: 0020bf33 sltu t5,ra,sp -80000528: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -8000052c: 00200293 li t0,2 -80000530: fe5212e3 bne tp,t0,80000514 -80000534: 00000e93 li t4,0 -80000538: 02100193 li gp,33 -8000053c: 09df1463 bne t5,t4,800005c4 - -80000540 : -80000540: 00000213 li tp,0 -80000544: 00d00113 li sp,13 -80000548: 00000013 nop -8000054c: 00000013 nop -80000550: 00600093 li ra,6 -80000554: 0020bf33 sltu t5,ra,sp -80000558: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -8000055c: 00200293 li t0,2 -80000560: fe5212e3 bne tp,t0,80000544 -80000564: 00100e93 li t4,1 -80000568: 02200193 li gp,34 -8000056c: 05df1c63 bne t5,t4,800005c4 - -80000570 : -80000570: fff00093 li ra,-1 -80000574: 00103133 snez sp,ra -80000578: 00100e93 li t4,1 -8000057c: 02300193 li gp,35 -80000580: 05d11263 bne sp,t4,800005c4 - -80000584 : -80000584: fff00093 li ra,-1 -80000588: 0000b133 sltu sp,ra,zero -8000058c: 00000e93 li t4,0 -80000590: 02400193 li gp,36 -80000594: 03d11863 bne sp,t4,800005c4 - -80000598 : -80000598: 000030b3 snez ra,zero -8000059c: 00000e93 li t4,0 -800005a0: 02500193 li gp,37 -800005a4: 03d09063 bne ra,t4,800005c4 - -800005a8 : -800005a8: 01000093 li ra,16 -800005ac: 01e00113 li sp,30 -800005b0: 0020b033 sltu zero,ra,sp -800005b4: 00000e93 li t4,0 -800005b8: 02600193 li gp,38 -800005bc: 01d01463 bne zero,t4,800005c4 -800005c0: 00301c63 bne zero,gp,800005d8 - -800005c4 : -800005c4: 0ff0000f fence -800005c8: 00018063 beqz gp,800005c8 -800005cc: 00119193 slli gp,gp,0x1 -800005d0: 0011e193 ori gp,gp,1 -800005d4: 00000073 ecall - -800005d8 : -800005d8: 0ff0000f fence -800005dc: 00100193 li gp,1 -800005e0: 00000073 ecall -800005e4: c0001073 unimp -800005e8: 0000 unimp -800005ea: 0000 unimp -800005ec: 0000 unimp -800005ee: 0000 unimp -800005f0: 0000 unimp -800005f2: 0000 unimp -800005f4: 0000 unimp -800005f6: 0000 unimp -800005f8: 0000 unimp -800005fa: 0000 unimp -800005fc: 0000 unimp -800005fe: 0000 unimp -80000600: 0000 unimp -80000602: 0000 unimp diff --git a/benchmarks/riscv_tests/rv32ui-p-sltu.hex b/benchmarks/riscv_tests/rv32ui-p-sltu.hex deleted file mode 100644 index a94616d4..00000000 --- a/benchmarks/riscv_tests/rv32ui-p-sltu.hex +++ /dev/null @@ -1,101 +0,0 @@ -:0200000480007A -:100000006F00C004732F2034930F8000630AFF0336 -:10001000930F90006306FF03930FB0006302FF038A -:10002000170F0080130F0FFE63040F0067000F000F -:10003000732F203463540F006F004000136E9E53E3 -:10004000171F00002320CFFD6FF09FFF732540F1A5 -:100050006310050073251030635805000F00F00F82 -:10006000130E100073000000130E00009702000032 -:10007000938282F973905230735020307350303035 -:1000800073504030970200809382C2F7638C020065 -:10009000739052109302B01A739022307323203061 -:1000A000E39E62F873500030970200009382420191 -:1000B00073901234732540F17300203093000000D8 -:1000C00013010000B3B12000930E0000130E2000B6 -:1000D000639AD14B9300100013011000B3B12000BC -:1000E000930E0000130E3000639ED1499300300040 -:1000F00013017000B3B12000930E1000130E4000E6 -:100100006392D1499300700013013000B3B1200015 -:10011000930E0000130E50006396D1479300000029 -:100120003781FFFFB3B12000930E1000130E600063 -:10013000639AD145B700008013010000B3B12000DD -:10014000930E0000130E7000639ED143B700008031 -:100150003781FFFFB3B12000930E1000130E800013 -:100160006392D14393000000378100001301F1FF37 -:10017000B3B12000930E1000130E90006394D14190 -:10018000B70000809380F0FF13010000B3B120009E -:10019000930E0000130EA0006396D13FB7000080BD -:1001A0009380F0FF378100001301F1FFB3B120000D -:1001B000930E0000130EB0006396D13DB70000808F -:1001C000378100001301F1FFB3B12000930E00004E -:1001D000130EC0006398D13BB70000809380F0FFFE -:1001E0003781FFFFB3B12000930E1000130ED00033 -:1001F000639AD139930000001301F0FFB3B12000DE -:10020000930E1000130EE000639ED1379300F0FFB1 -:1002100013011000B3B12000930E0000130EF00084 -:100220006392D1379300F0FF1301F0FFB3B12000C8 -:10023000930E0000130E00016396D1359300E00089 -:100240001301D000B3B02000930E0000130E100174 -:10025000639AD0339300B0001301D00033B1200073 -:10026000930E1000130E2001631ED1319300D000B5 -:10027000B3B01000930E0000130E30016394D03120 -:10028000130200009300B0001301D000B3B12000AE -:10029000138301001302120093022000E31452FEA4 -:1002A000930E1000130E4001631ED32D13020000A5 -:1002B0009300E0001301D000B3B120001300000050 -:1002C000138301001302120093022000E31252FE76 -:1002D000930E0000130E50016316D32B130200007F -:1002E0009300C0001301D000B3B120001300000040 -:1002F0001300000013830100130212009302200078 -:10030000E31052FE930E1000130E6001631CD327FE -:10031000130200009300E0001301D000B3B12000ED -:100320001302120093022000E31652FE930E000007 -:10033000130E70016398D125130200009300B000E2 -:100340001301D00013000000B3B12000130212000B -:1003500093022000E31452FE930E1000130E80014E -:100360006392D123130200009300F0001301D00028 -:100370001300000013000000B3B1200013021200AC -:1003800093022000E31252FE930E0000130E900120 -:10039000639AD11F130200009300A0001300000015 -:1003A0001301D000B3B12000130212009302200009 -:1003B000E31452FE930E1000130EA0016394D11D9E -:1003C0001302000093000001130000001301D0008D -:1003D00013000000B3B120001302120093022000AA -:1003E000E31252FE930E0000130EB001639CD1196C -:1003F000130200009300900013000000130000009F -:100400001301D000B3B120001302120093022000A8 -:10041000E31252FE930E1000130EC0016394D11725 -:10042000130200001301D00093001001B3B12000AB -:100430001302120093022000E31652FE930E0000F6 -:10044000130ED0016390D115130200001301D000E8 -:100450009300800013000000B3B1200013021200CB -:1004600093022000E31452FE930E1000130EE001DD -:10047000639AD111130200001301D00093002001F0 -:100480001300000013000000B3B12000130212009B -:1004900093022000E31252FE930E0000130EF001AF -:1004A0006392D10F130200001301D000130000006B -:1004B00093007000B3B120001302120093022000D9 -:1004C000E31452FE930E1000130E0002639CD10B36 -:1004D000130200001301D00013000000930030014C -:1004E00013000000B3B12000130212009302200099 -:1004F000E31252FE930E0000130E10026394D10912 -:10050000130200001301D0001300000013000000CC -:1005100093006000B3B12000130212009302200088 -:10052000E31252FE930E1000130E2002639CD105BD -:100530009300F0FF33311000930E1000130E3002C1 -:100540006312D1059300F0FF33B10000930E000059 -:10055000130E40026318D103B3300000930E000065 -:10056000130E50026390D003930000011301E001C9 -:1005700033B02000930E0000130E60026314D0010C -:10058000631CC0010F00F00F63000E00131E1E005D -:10059000136E1E00730000000F00F00F130E10000A -:1005A00073000000731000C0000000000000000095 -:1005B000000000000000000000000000000000003B -:0405C0000000000037 -:1010000000000000000000000000000000000000E0 -:1010100000000000000000000000000000000000D0 -:1010200000000000000000000000000000000000C0 -:1010300000000000000000000000000000000000B0 -:081040000000000000000000A8 -:040000058000200057 -:00000001FF diff --git a/benchmarks/riscv_tests/rv32ui-p-sra.dump b/benchmarks/riscv_tests/rv32ui-p-sra.dump deleted file mode 100644 index 3654a09d..00000000 --- a/benchmarks/riscv_tests/rv32ui-p-sra.dump +++ /dev/null @@ -1,563 +0,0 @@ - -rv32ui-p-sra: file format elf32-littleriscv - - -Disassembly of section .text.init: - -80000000 <_start>: -80000000: 04c0006f j 8000004c - -80000004 : -80000004: 34202f73 csrr t5,mcause -80000008: 00800f93 li t6,8 -8000000c: 03ff0a63 beq t5,t6,80000040 -80000010: 00900f93 li t6,9 -80000014: 03ff0663 beq t5,t6,80000040 -80000018: 00b00f93 li t6,11 -8000001c: 03ff0263 beq t5,t6,80000040 -80000020: 80000f17 auipc t5,0x80000 -80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> -80000028: 000f0463 beqz t5,80000030 -8000002c: 000f0067 jr t5 -80000030: 34202f73 csrr t5,mcause -80000034: 000f5463 bgez t5,8000003c -80000038: 0040006f j 8000003c - -8000003c : -8000003c: 5391e193 ori gp,gp,1337 - -80000040 : -80000040: 00001f17 auipc t5,0x1 -80000044: fc3f2023 sw gp,-64(t5) # 80001000 -80000048: ff9ff06f j 80000040 - -8000004c : -8000004c: f1402573 csrr a0,mhartid -80000050: 00051063 bnez a0,80000050 -80000054: 00000297 auipc t0,0x0 -80000058: 01028293 addi t0,t0,16 # 80000064 -8000005c: 30529073 csrw mtvec,t0 -80000060: 18005073 csrwi satp,0 -80000064: 00000297 auipc t0,0x0 -80000068: 02028293 addi t0,t0,32 # 80000084 -8000006c: 30529073 csrw mtvec,t0 -80000070: 800002b7 lui t0,0x80000 -80000074: fff28293 addi t0,t0,-1 # 7fffffff <_end+0xffffdfff> -80000078: 3b029073 csrw pmpaddr0,t0 -8000007c: 01f00293 li t0,31 -80000080: 3a029073 csrw pmpcfg0,t0 -80000084: 00000297 auipc t0,0x0 -80000088: 01828293 addi t0,t0,24 # 8000009c -8000008c: 30529073 csrw mtvec,t0 -80000090: 30205073 csrwi medeleg,0 -80000094: 30305073 csrwi mideleg,0 -80000098: 30405073 csrwi mie,0 -8000009c: 00000193 li gp,0 -800000a0: 00000297 auipc t0,0x0 -800000a4: f6428293 addi t0,t0,-156 # 80000004 -800000a8: 30529073 csrw mtvec,t0 -800000ac: 00100513 li a0,1 -800000b0: 01f51513 slli a0,a0,0x1f -800000b4: 00054c63 bltz a0,800000cc -800000b8: 0ff0000f fence -800000bc: 00100193 li gp,1 -800000c0: 05d00893 li a7,93 -800000c4: 00000513 li a0,0 -800000c8: 00000073 ecall -800000cc: 80000297 auipc t0,0x80000 -800000d0: f3428293 addi t0,t0,-204 # 0 <_start-0x80000000> -800000d4: 00028e63 beqz t0,800000f0 -800000d8: 10529073 csrw stvec,t0 -800000dc: 0000b2b7 lui t0,0xb -800000e0: 10928293 addi t0,t0,265 # b109 <_start-0x7fff4ef7> -800000e4: 30229073 csrw medeleg,t0 -800000e8: 30202373 csrr t1,medeleg -800000ec: f46298e3 bne t0,t1,8000003c -800000f0: 30005073 csrwi mstatus,0 -800000f4: 00000297 auipc t0,0x0 -800000f8: 01428293 addi t0,t0,20 # 80000108 -800000fc: 34129073 csrw mepc,t0 -80000100: f1402573 csrr a0,mhartid -80000104: 30200073 mret - -80000108 : -80000108: 800000b7 lui ra,0x80000 -8000010c: 00000113 li sp,0 -80000110: 4020d733 sra a4,ra,sp -80000114: 80000eb7 lui t4,0x80000 -80000118: 00200193 li gp,2 -8000011c: 59d71463 bne a4,t4,800006a4 - -80000120 : -80000120: 800000b7 lui ra,0x80000 -80000124: 00100113 li sp,1 -80000128: 4020d733 sra a4,ra,sp -8000012c: c0000eb7 lui t4,0xc0000 -80000130: 00300193 li gp,3 -80000134: 57d71863 bne a4,t4,800006a4 - -80000138 : -80000138: 800000b7 lui ra,0x80000 -8000013c: 00700113 li sp,7 -80000140: 4020d733 sra a4,ra,sp -80000144: ff000eb7 lui t4,0xff000 -80000148: 00400193 li gp,4 -8000014c: 55d71c63 bne a4,t4,800006a4 - -80000150 : -80000150: 800000b7 lui ra,0x80000 -80000154: 00e00113 li sp,14 -80000158: 4020d733 sra a4,ra,sp -8000015c: fffe0eb7 lui t4,0xfffe0 -80000160: 00500193 li gp,5 -80000164: 55d71063 bne a4,t4,800006a4 - -80000168 : -80000168: 800000b7 lui ra,0x80000 -8000016c: 00108093 addi ra,ra,1 # 80000001 <_end+0xffffe001> -80000170: 01f00113 li sp,31 -80000174: 4020d733 sra a4,ra,sp -80000178: fff00e93 li t4,-1 -8000017c: 00600193 li gp,6 -80000180: 53d71263 bne a4,t4,800006a4 - -80000184 : -80000184: 800000b7 lui ra,0x80000 -80000188: fff08093 addi ra,ra,-1 # 7fffffff <_end+0xffffdfff> -8000018c: 00000113 li sp,0 -80000190: 4020d733 sra a4,ra,sp -80000194: 80000eb7 lui t4,0x80000 -80000198: fffe8e93 addi t4,t4,-1 # 7fffffff <_end+0xffffdfff> -8000019c: 00700193 li gp,7 -800001a0: 51d71263 bne a4,t4,800006a4 - -800001a4 : -800001a4: 800000b7 lui ra,0x80000 -800001a8: fff08093 addi ra,ra,-1 # 7fffffff <_end+0xffffdfff> -800001ac: 00100113 li sp,1 -800001b0: 4020d733 sra a4,ra,sp -800001b4: 40000eb7 lui t4,0x40000 -800001b8: fffe8e93 addi t4,t4,-1 # 3fffffff <_start-0x40000001> -800001bc: 00800193 li gp,8 -800001c0: 4fd71263 bne a4,t4,800006a4 - -800001c4 : -800001c4: 800000b7 lui ra,0x80000 -800001c8: fff08093 addi ra,ra,-1 # 7fffffff <_end+0xffffdfff> -800001cc: 00700113 li sp,7 -800001d0: 4020d733 sra a4,ra,sp -800001d4: 01000eb7 lui t4,0x1000 -800001d8: fffe8e93 addi t4,t4,-1 # ffffff <_start-0x7f000001> -800001dc: 00900193 li gp,9 -800001e0: 4dd71263 bne a4,t4,800006a4 - -800001e4 : -800001e4: 800000b7 lui ra,0x80000 -800001e8: fff08093 addi ra,ra,-1 # 7fffffff <_end+0xffffdfff> -800001ec: 00e00113 li sp,14 -800001f0: 4020d733 sra a4,ra,sp -800001f4: 00020eb7 lui t4,0x20 -800001f8: fffe8e93 addi t4,t4,-1 # 1ffff <_start-0x7ffe0001> -800001fc: 00a00193 li gp,10 -80000200: 4bd71263 bne a4,t4,800006a4 - -80000204 : -80000204: 800000b7 lui ra,0x80000 -80000208: fff08093 addi ra,ra,-1 # 7fffffff <_end+0xffffdfff> -8000020c: 01f00113 li sp,31 -80000210: 4020d733 sra a4,ra,sp -80000214: 00000e93 li t4,0 -80000218: 00b00193 li gp,11 -8000021c: 49d71463 bne a4,t4,800006a4 - -80000220 : -80000220: 818180b7 lui ra,0x81818 -80000224: 18108093 addi ra,ra,385 # 81818181 <_end+0x1816181> -80000228: 00000113 li sp,0 -8000022c: 4020d733 sra a4,ra,sp -80000230: 81818eb7 lui t4,0x81818 -80000234: 181e8e93 addi t4,t4,385 # 81818181 <_end+0x1816181> -80000238: 00c00193 li gp,12 -8000023c: 47d71463 bne a4,t4,800006a4 - -80000240 : -80000240: 818180b7 lui ra,0x81818 -80000244: 18108093 addi ra,ra,385 # 81818181 <_end+0x1816181> -80000248: 00100113 li sp,1 -8000024c: 4020d733 sra a4,ra,sp -80000250: c0c0ceb7 lui t4,0xc0c0c -80000254: 0c0e8e93 addi t4,t4,192 # c0c0c0c0 <_end+0x40c0a0c0> -80000258: 00d00193 li gp,13 -8000025c: 45d71463 bne a4,t4,800006a4 - -80000260 : -80000260: 818180b7 lui ra,0x81818 -80000264: 18108093 addi ra,ra,385 # 81818181 <_end+0x1816181> -80000268: 00700113 li sp,7 -8000026c: 4020d733 sra a4,ra,sp -80000270: ff030eb7 lui t4,0xff030 -80000274: 303e8e93 addi t4,t4,771 # ff030303 <_end+0x7f02e303> -80000278: 00e00193 li gp,14 -8000027c: 43d71463 bne a4,t4,800006a4 - -80000280 : -80000280: 818180b7 lui ra,0x81818 -80000284: 18108093 addi ra,ra,385 # 81818181 <_end+0x1816181> -80000288: 00e00113 li sp,14 -8000028c: 4020d733 sra a4,ra,sp -80000290: fffe0eb7 lui t4,0xfffe0 -80000294: 606e8e93 addi t4,t4,1542 # fffe0606 <_end+0x7ffde606> -80000298: 00f00193 li gp,15 -8000029c: 41d71463 bne a4,t4,800006a4 - -800002a0 : -800002a0: 818180b7 lui ra,0x81818 -800002a4: 18108093 addi ra,ra,385 # 81818181 <_end+0x1816181> -800002a8: 01f00113 li sp,31 -800002ac: 4020d733 sra a4,ra,sp -800002b0: fff00e93 li t4,-1 -800002b4: 01000193 li gp,16 -800002b8: 3fd71663 bne a4,t4,800006a4 - -800002bc : -800002bc: 818180b7 lui ra,0x81818 -800002c0: 18108093 addi ra,ra,385 # 81818181 <_end+0x1816181> -800002c4: fc000113 li sp,-64 -800002c8: 4020d733 sra a4,ra,sp -800002cc: 81818eb7 lui t4,0x81818 -800002d0: 181e8e93 addi t4,t4,385 # 81818181 <_end+0x1816181> -800002d4: 01100193 li gp,17 -800002d8: 3dd71663 bne a4,t4,800006a4 - -800002dc : -800002dc: 818180b7 lui ra,0x81818 -800002e0: 18108093 addi ra,ra,385 # 81818181 <_end+0x1816181> -800002e4: fc100113 li sp,-63 -800002e8: 4020d733 sra a4,ra,sp -800002ec: c0c0ceb7 lui t4,0xc0c0c -800002f0: 0c0e8e93 addi t4,t4,192 # c0c0c0c0 <_end+0x40c0a0c0> -800002f4: 01200193 li gp,18 -800002f8: 3bd71663 bne a4,t4,800006a4 - -800002fc : -800002fc: 818180b7 lui ra,0x81818 -80000300: 18108093 addi ra,ra,385 # 81818181 <_end+0x1816181> -80000304: fc700113 li sp,-57 -80000308: 4020d733 sra a4,ra,sp -8000030c: ff030eb7 lui t4,0xff030 -80000310: 303e8e93 addi t4,t4,771 # ff030303 <_end+0x7f02e303> -80000314: 01300193 li gp,19 -80000318: 39d71663 bne a4,t4,800006a4 - -8000031c : -8000031c: 818180b7 lui ra,0x81818 -80000320: 18108093 addi ra,ra,385 # 81818181 <_end+0x1816181> -80000324: fce00113 li sp,-50 -80000328: 4020d733 sra a4,ra,sp -8000032c: fffe0eb7 lui t4,0xfffe0 -80000330: 606e8e93 addi t4,t4,1542 # fffe0606 <_end+0x7ffde606> -80000334: 01400193 li gp,20 -80000338: 37d71663 bne a4,t4,800006a4 - -8000033c : -8000033c: 818180b7 lui ra,0x81818 -80000340: 18108093 addi ra,ra,385 # 81818181 <_end+0x1816181> -80000344: fff00113 li sp,-1 -80000348: 4020d733 sra a4,ra,sp -8000034c: fff00e93 li t4,-1 -80000350: 01500193 li gp,21 -80000354: 35d71863 bne a4,t4,800006a4 - -80000358 : -80000358: 800000b7 lui ra,0x80000 -8000035c: 00700113 li sp,7 -80000360: 4020d0b3 sra ra,ra,sp -80000364: ff000eb7 lui t4,0xff000 -80000368: 01600193 li gp,22 -8000036c: 33d09c63 bne ra,t4,800006a4 - -80000370 : -80000370: 800000b7 lui ra,0x80000 -80000374: 00e00113 li sp,14 -80000378: 4020d133 sra sp,ra,sp -8000037c: fffe0eb7 lui t4,0xfffe0 -80000380: 01700193 li gp,23 -80000384: 33d11063 bne sp,t4,800006a4 - -80000388 : -80000388: 00700093 li ra,7 -8000038c: 4010d0b3 sra ra,ra,ra -80000390: 00000e93 li t4,0 -80000394: 01800193 li gp,24 -80000398: 31d09663 bne ra,t4,800006a4 - -8000039c : -8000039c: 00000213 li tp,0 -800003a0: 800000b7 lui ra,0x80000 -800003a4: 00700113 li sp,7 -800003a8: 4020d733 sra a4,ra,sp -800003ac: 00070313 mv t1,a4 -800003b0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -800003b4: 00200293 li t0,2 -800003b8: fe5214e3 bne tp,t0,800003a0 -800003bc: ff000eb7 lui t4,0xff000 -800003c0: 01900193 li gp,25 -800003c4: 2fd31063 bne t1,t4,800006a4 - -800003c8 : -800003c8: 00000213 li tp,0 -800003cc: 800000b7 lui ra,0x80000 -800003d0: 00e00113 li sp,14 -800003d4: 4020d733 sra a4,ra,sp -800003d8: 00000013 nop -800003dc: 00070313 mv t1,a4 -800003e0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -800003e4: 00200293 li t0,2 -800003e8: fe5212e3 bne tp,t0,800003cc -800003ec: fffe0eb7 lui t4,0xfffe0 -800003f0: 01a00193 li gp,26 -800003f4: 2bd31863 bne t1,t4,800006a4 - -800003f8 : -800003f8: 00000213 li tp,0 -800003fc: 800000b7 lui ra,0x80000 -80000400: 01f00113 li sp,31 -80000404: 4020d733 sra a4,ra,sp -80000408: 00000013 nop -8000040c: 00000013 nop -80000410: 00070313 mv t1,a4 -80000414: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000418: 00200293 li t0,2 -8000041c: fe5210e3 bne tp,t0,800003fc -80000420: fff00e93 li t4,-1 -80000424: 01b00193 li gp,27 -80000428: 27d31e63 bne t1,t4,800006a4 - -8000042c : -8000042c: 00000213 li tp,0 -80000430: 800000b7 lui ra,0x80000 -80000434: 00700113 li sp,7 -80000438: 4020d733 sra a4,ra,sp -8000043c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000440: 00200293 li t0,2 -80000444: fe5216e3 bne tp,t0,80000430 -80000448: ff000eb7 lui t4,0xff000 -8000044c: 01c00193 li gp,28 -80000450: 25d71a63 bne a4,t4,800006a4 - -80000454 : -80000454: 00000213 li tp,0 -80000458: 800000b7 lui ra,0x80000 -8000045c: 00e00113 li sp,14 -80000460: 00000013 nop -80000464: 4020d733 sra a4,ra,sp -80000468: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -8000046c: 00200293 li t0,2 -80000470: fe5214e3 bne tp,t0,80000458 -80000474: fffe0eb7 lui t4,0xfffe0 -80000478: 01d00193 li gp,29 -8000047c: 23d71463 bne a4,t4,800006a4 - -80000480 : -80000480: 00000213 li tp,0 -80000484: 800000b7 lui ra,0x80000 -80000488: 01f00113 li sp,31 -8000048c: 00000013 nop -80000490: 00000013 nop -80000494: 4020d733 sra a4,ra,sp -80000498: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -8000049c: 00200293 li t0,2 -800004a0: fe5212e3 bne tp,t0,80000484 -800004a4: fff00e93 li t4,-1 -800004a8: 01e00193 li gp,30 -800004ac: 1fd71c63 bne a4,t4,800006a4 - -800004b0 : -800004b0: 00000213 li tp,0 -800004b4: 800000b7 lui ra,0x80000 -800004b8: 00000013 nop -800004bc: 00700113 li sp,7 -800004c0: 4020d733 sra a4,ra,sp -800004c4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -800004c8: 00200293 li t0,2 -800004cc: fe5214e3 bne tp,t0,800004b4 -800004d0: ff000eb7 lui t4,0xff000 -800004d4: 01f00193 li gp,31 -800004d8: 1dd71663 bne a4,t4,800006a4 - -800004dc : -800004dc: 00000213 li tp,0 -800004e0: 800000b7 lui ra,0x80000 -800004e4: 00000013 nop -800004e8: 00e00113 li sp,14 -800004ec: 00000013 nop -800004f0: 4020d733 sra a4,ra,sp -800004f4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -800004f8: 00200293 li t0,2 -800004fc: fe5212e3 bne tp,t0,800004e0 -80000500: fffe0eb7 lui t4,0xfffe0 -80000504: 02000193 li gp,32 -80000508: 19d71e63 bne a4,t4,800006a4 - -8000050c : -8000050c: 00000213 li tp,0 -80000510: 800000b7 lui ra,0x80000 -80000514: 00000013 nop -80000518: 00000013 nop -8000051c: 01f00113 li sp,31 -80000520: 4020d733 sra a4,ra,sp -80000524: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000528: 00200293 li t0,2 -8000052c: fe5212e3 bne tp,t0,80000510 -80000530: fff00e93 li t4,-1 -80000534: 02100193 li gp,33 -80000538: 17d71663 bne a4,t4,800006a4 - -8000053c : -8000053c: 00000213 li tp,0 -80000540: 00700113 li sp,7 -80000544: 800000b7 lui ra,0x80000 -80000548: 4020d733 sra a4,ra,sp -8000054c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000550: 00200293 li t0,2 -80000554: fe5216e3 bne tp,t0,80000540 -80000558: ff000eb7 lui t4,0xff000 -8000055c: 02200193 li gp,34 -80000560: 15d71263 bne a4,t4,800006a4 - -80000564 : -80000564: 00000213 li tp,0 -80000568: 00e00113 li sp,14 -8000056c: 800000b7 lui ra,0x80000 -80000570: 00000013 nop -80000574: 4020d733 sra a4,ra,sp -80000578: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -8000057c: 00200293 li t0,2 -80000580: fe5214e3 bne tp,t0,80000568 -80000584: fffe0eb7 lui t4,0xfffe0 -80000588: 02300193 li gp,35 -8000058c: 11d71c63 bne a4,t4,800006a4 - -80000590 : -80000590: 00000213 li tp,0 -80000594: 01f00113 li sp,31 -80000598: 800000b7 lui ra,0x80000 -8000059c: 00000013 nop -800005a0: 00000013 nop -800005a4: 4020d733 sra a4,ra,sp -800005a8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -800005ac: 00200293 li t0,2 -800005b0: fe5212e3 bne tp,t0,80000594 -800005b4: fff00e93 li t4,-1 -800005b8: 02400193 li gp,36 -800005bc: 0fd71463 bne a4,t4,800006a4 - -800005c0 : -800005c0: 00000213 li tp,0 -800005c4: 00700113 li sp,7 -800005c8: 00000013 nop -800005cc: 800000b7 lui ra,0x80000 -800005d0: 4020d733 sra a4,ra,sp -800005d4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -800005d8: 00200293 li t0,2 -800005dc: fe5214e3 bne tp,t0,800005c4 -800005e0: ff000eb7 lui t4,0xff000 -800005e4: 02500193 li gp,37 -800005e8: 0bd71e63 bne a4,t4,800006a4 - -800005ec : -800005ec: 00000213 li tp,0 -800005f0: 00e00113 li sp,14 -800005f4: 00000013 nop -800005f8: 800000b7 lui ra,0x80000 -800005fc: 00000013 nop -80000600: 4020d733 sra a4,ra,sp -80000604: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000608: 00200293 li t0,2 -8000060c: fe5212e3 bne tp,t0,800005f0 -80000610: fffe0eb7 lui t4,0xfffe0 -80000614: 02600193 li gp,38 -80000618: 09d71663 bne a4,t4,800006a4 - -8000061c : -8000061c: 00000213 li tp,0 -80000620: 01f00113 li sp,31 -80000624: 00000013 nop -80000628: 00000013 nop -8000062c: 800000b7 lui ra,0x80000 -80000630: 4020d733 sra a4,ra,sp -80000634: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000638: 00200293 li t0,2 -8000063c: fe5212e3 bne tp,t0,80000620 -80000640: fff00e93 li t4,-1 -80000644: 02700193 li gp,39 -80000648: 05d71e63 bne a4,t4,800006a4 - -8000064c : -8000064c: 00f00093 li ra,15 -80000650: 40105133 sra sp,zero,ra -80000654: 00000e93 li t4,0 -80000658: 02800193 li gp,40 -8000065c: 05d11463 bne sp,t4,800006a4 - -80000660 : -80000660: 02000093 li ra,32 -80000664: 4000d133 sra sp,ra,zero -80000668: 02000e93 li t4,32 -8000066c: 02900193 li gp,41 -80000670: 03d11a63 bne sp,t4,800006a4 - -80000674 : -80000674: 400050b3 sra ra,zero,zero -80000678: 00000e93 li t4,0 -8000067c: 02a00193 li gp,42 -80000680: 03d09263 bne ra,t4,800006a4 - -80000684 : -80000684: 40000093 li ra,1024 -80000688: 00001137 lui sp,0x1 -8000068c: 80010113 addi sp,sp,-2048 # 800 <_start-0x7ffff800> -80000690: 4020d033 sra zero,ra,sp -80000694: 00000e93 li t4,0 -80000698: 02b00193 li gp,43 -8000069c: 01d01463 bne zero,t4,800006a4 -800006a0: 02301063 bne zero,gp,800006c0 - -800006a4 : -800006a4: 0ff0000f fence -800006a8: 00018063 beqz gp,800006a8 -800006ac: 00119193 slli gp,gp,0x1 -800006b0: 0011e193 ori gp,gp,1 -800006b4: 05d00893 li a7,93 -800006b8: 00018513 mv a0,gp -800006bc: 00000073 ecall - -800006c0 : -800006c0: 0ff0000f fence -800006c4: 00100193 li gp,1 -800006c8: 05d00893 li a7,93 -800006cc: 00000513 li a0,0 -800006d0: 00000073 ecall -800006d4: c0001073 unimp -800006d8: 0000 unimp -800006da: 0000 unimp -800006dc: 0000 unimp -800006de: 0000 unimp -800006e0: 0000 unimp -800006e2: 0000 unimp -800006e4: 0000 unimp -800006e6: 0000 unimp -800006e8: 0000 unimp -800006ea: 0000 unimp -800006ec: 0000 unimp -800006ee: 0000 unimp -800006f0: 0000 unimp -800006f2: 0000 unimp -800006f4: 0000 unimp -800006f6: 0000 unimp -800006f8: 0000 unimp -800006fa: 0000 unimp -800006fc: 0000 unimp -800006fe: 0000 unimp -80000700: 0000 unimp -80000702: 0000 unimp diff --git a/benchmarks/riscv_tests/rv32ui-p-sra.hex b/benchmarks/riscv_tests/rv32ui-p-sra.hex deleted file mode 100644 index ac2ca2bb..00000000 --- a/benchmarks/riscv_tests/rv32ui-p-sra.hex +++ /dev/null @@ -1,113 +0,0 @@ -:0200000480007A -:100000006F00C004732F2034930F8000630AFF0336 -:10001000930F90006306FF03930FB0006302FF038A -:10002000170F0080130F0FFE63040F0067000F000F -:10003000732F203463540F006F004000136E9E53E3 -:10004000171F00002320CFFD6FF09FFF732540F1A5 -:100050006310050073251030635805000F00F00F82 -:10006000130E100073000000130E00009702000032 -:10007000938282F973905230735020307350303035 -:1000800073504030970200809382C2F7638C020065 -:10009000739052109302B01A739022307323203061 -:1000A000E39E62F873500030970200009382420191 -:1000B00073901234732540F173002030B700008034 -:1000C00013010000B3D12040B70E0080130E2000B2 -:1000D0006394D159B700008013011000B3D12040C0 -:1000E000B70E00C0130E30006398D157B7000080E0 -:1000F00013017000B3D12040B70E00FF130E400073 -:10010000639CD155B70000801301E000B3D12040BB -:10011000B70EFEFF130E50006390D155B70000805C -:10012000938010001301F001B3D12040930EF0FF33 -:10013000130E60006392D153B70000809380F0FFEC -:1001400013010000B3D12040B70E0080938EFEFF54 -:10015000130E70006392D151B70000809380F0FFBE -:1001600013011000B3D12040B70E0040938EFEFF64 -:10017000130E80006392D14FB70000809380F0FF90 -:1001800013017000B3D12040B70E0001938EFEFF23 -:10019000130E90006392D14DB70000809380F0FF62 -:1001A0001301E000B3D12040B70E0200938EFEFF92 -:1001B000130EA0006392D14BB70000809380F0FF34 -:1001C0001301F001B3D12040930E0000130EB000D4 -:1001D0006394D149B7808181938010181301000086 -:1001E000B3D12040B78E8181938E1E18130EC000AC -:1001F0006394D147B7808181938010181301100058 -:10020000B3D12040B7CEC0C0938E0E0C130ED000D9 -:100210006394D145B78081819380101813017000D9 -:10022000B3D12040B70E03FF938E3E30130EE00093 -:100230006394D143B7808181938010181301E0004B -:10024000B3D12040B70EFEFF938E6E60130EF00008 -:100250006394D141B7808181938010181301F0011C -:10026000B3D12040930EF0FF130E00016396D13FEF -:10027000B780818193801018130100FCB3D1204016 -:10028000B78E8181938E1E18130E10016396D13D97 -:10029000B780818193801018130110FCB3D12040E6 -:1002A000B7CEC0C0938E0E0C130E20016396D13BC7 -:1002B000B780818193801018130170FCB3D1204066 -:1002C000B70E03FF938E3E30130E30016396D13983 -:1002D000B7808181938010181301E0FCB3D12040D6 -:1002E000B70EFEFF938E6E60130E40016396D137FA -:1002F000B7808181938010181301F0FFB3D12040A3 -:10030000930EF0FF130E50016398D135B7000080B3 -:1003100013017000B3D02040B70E00FF130E600130 -:10032000639CD033B70000801301E00033D120403C -:10033000B70EFEFF130E70016310D13393007000EF -:10034000B3D01040930E0000130E80016396D0319D -:1003500013020000B700008013017000B3D12040E9 -:10036000138301001302120093022000E31452FED3 -:10037000B70E00FF130E90016310D32F130200007D -:10038000B70000801301E000B3D12040130000004B -:10039000138301001302120093022000E31252FEA5 -:1003A000B70EFEFF130EA0016318D32B130200003B -:1003B000B70000801301F001B3D12040130000000A -:1003C00013000000138301001302120093022000A7 -:1003D000E31052FE930EF0FF130EB001631ED327FD -:1003E00013020000B700008013017000B3D1204059 -:1003F0001302120093022000E31652FEB70E00FF14 -:10040000130EC001639AD12513020000B7000080CB -:100410001301E00013000000B3D1204013021200CA -:1004200093022000E31452FEB70EFEFF130ED0011C -:100430006394D12313020000B70000801301F00180 -:100440001300000013000000B3D12040130212007B -:1004500093022000E31252FE930EF0FF130EE00110 -:10046000639CD11F13020000B7000080130000003E -:1004700013017000B3D12040130212009302200038 -:10048000E31452FEB70E00FF130EF0016396D11D68 -:1004900013020000B7000080130000001301E00009 -:1004A00013000000B3D12040130212009302200079 -:1004B000E31252FEB70EFEFF130E0002639ED11927 -:1004C00013020000B70000801300000013000000BA -:1004D0001301F001B3D12040130212009302200057 -:1004E000E31252FE930EF0FF130E10026396D11723 -:1004F0001302000013017000B7000080B3D1204048 -:100500001302120093022000E31652FEB70E00FF02 -:10051000130E20026392D115130200001301E000B4 -:10052000B700008013000000B3D120401302120076 -:1005300093022000E31452FEB70EFEFF130E3002AA -:10054000639CD111130200001301F001B700008079 -:100550001300000013000000B3D12040130212006A -:1005600093022000E31252FE930EF0FF130E40029E -:100570006394D10F130200001301700013000000F8 -:10058000B7000080B3D12040130212009302200074 -:10059000E31452FEB70E00FF130E5002639ED10B00 -:1005A000130200001301E00013000000B7000080F8 -:1005B00013000000B3D12040130212009302200068 -:1005C000E31252FEB70EFEFF130E60026396D109CE -:1005D000130200001301F0011300000013000000DB -:1005E000B7000080B3D12040130212009302200014 -:1005F000E31252FE930EF0FF130E7002639ED105BC -:100600009300F00033511040930E0000130E80024F -:100610006314D1059300000233D10040930E000211 -:10062000130E9002631AD103B3500040930E0000E2 -:10063000130EA0026392D003930000403711000014 -:100640001301018033D02040930E0000130EB0023E -:100650006314D001631CC0010F00F00F63000E0093 -:10066000131E1E00136E1E00730000000F00F00F1B -:10067000130E100073000000731000C00000000093 -:040680000000000076 -:1010000000000000000000000000000000000000E0 -:1010100000000000000000000000000000000000D0 -:1010200000000000000000000000000000000000C0 -:1010300000000000000000000000000000000000B0 -:081040000000000000000000A8 -:040000058000200057 -:00000001FF diff --git a/benchmarks/riscv_tests/rv32ui-p-srai.dump b/benchmarks/riscv_tests/rv32ui-p-srai.dump deleted file mode 100644 index d13cc125..00000000 --- a/benchmarks/riscv_tests/rv32ui-p-srai.dump +++ /dev/null @@ -1,328 +0,0 @@ - -rv32ui-p-srai: file format elf32-littleriscv - - -Disassembly of section .text.init: - -80000000 <_start>: -80000000: 04c0006f j 8000004c - -80000004 : -80000004: 34202f73 csrr t5,mcause -80000008: 00800f93 li t6,8 -8000000c: 03ff0a63 beq t5,t6,80000040 -80000010: 00900f93 li t6,9 -80000014: 03ff0663 beq t5,t6,80000040 -80000018: 00b00f93 li t6,11 -8000001c: 03ff0263 beq t5,t6,80000040 -80000020: 80000f17 auipc t5,0x80000 -80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> -80000028: 000f0463 beqz t5,80000030 -8000002c: 000f0067 jr t5 -80000030: 34202f73 csrr t5,mcause -80000034: 000f5463 bgez t5,8000003c -80000038: 0040006f j 8000003c - -8000003c : -8000003c: 5391e193 ori gp,gp,1337 - -80000040 : -80000040: 00001f17 auipc t5,0x1 -80000044: fc3f2023 sw gp,-64(t5) # 80001000 -80000048: ff9ff06f j 80000040 - -8000004c : -8000004c: f1402573 csrr a0,mhartid -80000050: 00051063 bnez a0,80000050 -80000054: 00000297 auipc t0,0x0 -80000058: 01028293 addi t0,t0,16 # 80000064 -8000005c: 30529073 csrw mtvec,t0 -80000060: 18005073 csrwi satp,0 -80000064: 00000297 auipc t0,0x0 -80000068: 02028293 addi t0,t0,32 # 80000084 -8000006c: 30529073 csrw mtvec,t0 -80000070: 800002b7 lui t0,0x80000 -80000074: fff28293 addi t0,t0,-1 # 7fffffff <_end+0xffffdfff> -80000078: 3b029073 csrw pmpaddr0,t0 -8000007c: 01f00293 li t0,31 -80000080: 3a029073 csrw pmpcfg0,t0 -80000084: 00000297 auipc t0,0x0 -80000088: 01828293 addi t0,t0,24 # 8000009c -8000008c: 30529073 csrw mtvec,t0 -80000090: 30205073 csrwi medeleg,0 -80000094: 30305073 csrwi mideleg,0 -80000098: 30405073 csrwi mie,0 -8000009c: 00000193 li gp,0 -800000a0: 00000297 auipc t0,0x0 -800000a4: f6428293 addi t0,t0,-156 # 80000004 -800000a8: 30529073 csrw mtvec,t0 -800000ac: 00100513 li a0,1 -800000b0: 01f51513 slli a0,a0,0x1f -800000b4: 00054c63 bltz a0,800000cc -800000b8: 0ff0000f fence -800000bc: 00100193 li gp,1 -800000c0: 05d00893 li a7,93 -800000c4: 00000513 li a0,0 -800000c8: 00000073 ecall -800000cc: 80000297 auipc t0,0x80000 -800000d0: f3428293 addi t0,t0,-204 # 0 <_start-0x80000000> -800000d4: 00028e63 beqz t0,800000f0 -800000d8: 10529073 csrw stvec,t0 -800000dc: 0000b2b7 lui t0,0xb -800000e0: 10928293 addi t0,t0,265 # b109 <_start-0x7fff4ef7> -800000e4: 30229073 csrw medeleg,t0 -800000e8: 30202373 csrr t1,medeleg -800000ec: f46298e3 bne t0,t1,8000003c -800000f0: 30005073 csrwi mstatus,0 -800000f4: 00000297 auipc t0,0x0 -800000f8: 01428293 addi t0,t0,20 # 80000108 -800000fc: 34129073 csrw mepc,t0 -80000100: f1402573 csrr a0,mhartid -80000104: 30200073 mret - -80000108 : -80000108: 00000093 li ra,0 -8000010c: 4000d713 srai a4,ra,0x0 -80000110: 00000e93 li t4,0 -80000114: 00200193 li gp,2 -80000118: 2bd71463 bne a4,t4,800003c0 - -8000011c : -8000011c: 800000b7 lui ra,0x80000 -80000120: 4010d713 srai a4,ra,0x1 -80000124: c0000eb7 lui t4,0xc0000 -80000128: 00300193 li gp,3 -8000012c: 29d71a63 bne a4,t4,800003c0 - -80000130 : -80000130: 800000b7 lui ra,0x80000 -80000134: 4070d713 srai a4,ra,0x7 -80000138: ff000eb7 lui t4,0xff000 -8000013c: 00400193 li gp,4 -80000140: 29d71063 bne a4,t4,800003c0 - -80000144 : -80000144: 800000b7 lui ra,0x80000 -80000148: 40e0d713 srai a4,ra,0xe -8000014c: fffe0eb7 lui t4,0xfffe0 -80000150: 00500193 li gp,5 -80000154: 27d71663 bne a4,t4,800003c0 - -80000158 : -80000158: 800000b7 lui ra,0x80000 -8000015c: 00108093 addi ra,ra,1 # 80000001 <_end+0xffffe001> -80000160: 41f0d713 srai a4,ra,0x1f -80000164: fff00e93 li t4,-1 -80000168: 00600193 li gp,6 -8000016c: 25d71a63 bne a4,t4,800003c0 - -80000170 : -80000170: 800000b7 lui ra,0x80000 -80000174: fff08093 addi ra,ra,-1 # 7fffffff <_end+0xffffdfff> -80000178: 4000d713 srai a4,ra,0x0 -8000017c: 80000eb7 lui t4,0x80000 -80000180: fffe8e93 addi t4,t4,-1 # 7fffffff <_end+0xffffdfff> -80000184: 00700193 li gp,7 -80000188: 23d71c63 bne a4,t4,800003c0 - -8000018c : -8000018c: 800000b7 lui ra,0x80000 -80000190: fff08093 addi ra,ra,-1 # 7fffffff <_end+0xffffdfff> -80000194: 4010d713 srai a4,ra,0x1 -80000198: 40000eb7 lui t4,0x40000 -8000019c: fffe8e93 addi t4,t4,-1 # 3fffffff <_start-0x40000001> -800001a0: 00800193 li gp,8 -800001a4: 21d71e63 bne a4,t4,800003c0 - -800001a8 : -800001a8: 800000b7 lui ra,0x80000 -800001ac: fff08093 addi ra,ra,-1 # 7fffffff <_end+0xffffdfff> -800001b0: 4070d713 srai a4,ra,0x7 -800001b4: 01000eb7 lui t4,0x1000 -800001b8: fffe8e93 addi t4,t4,-1 # ffffff <_start-0x7f000001> -800001bc: 00900193 li gp,9 -800001c0: 21d71063 bne a4,t4,800003c0 - -800001c4 : -800001c4: 800000b7 lui ra,0x80000 -800001c8: fff08093 addi ra,ra,-1 # 7fffffff <_end+0xffffdfff> -800001cc: 40e0d713 srai a4,ra,0xe -800001d0: 00020eb7 lui t4,0x20 -800001d4: fffe8e93 addi t4,t4,-1 # 1ffff <_start-0x7ffe0001> -800001d8: 00a00193 li gp,10 -800001dc: 1fd71263 bne a4,t4,800003c0 - -800001e0 : -800001e0: 800000b7 lui ra,0x80000 -800001e4: fff08093 addi ra,ra,-1 # 7fffffff <_end+0xffffdfff> -800001e8: 41f0d713 srai a4,ra,0x1f -800001ec: 00000e93 li t4,0 -800001f0: 00b00193 li gp,11 -800001f4: 1dd71663 bne a4,t4,800003c0 - -800001f8 : -800001f8: 818180b7 lui ra,0x81818 -800001fc: 18108093 addi ra,ra,385 # 81818181 <_end+0x1816181> -80000200: 4000d713 srai a4,ra,0x0 -80000204: 81818eb7 lui t4,0x81818 -80000208: 181e8e93 addi t4,t4,385 # 81818181 <_end+0x1816181> -8000020c: 00c00193 li gp,12 -80000210: 1bd71863 bne a4,t4,800003c0 - -80000214 : -80000214: 818180b7 lui ra,0x81818 -80000218: 18108093 addi ra,ra,385 # 81818181 <_end+0x1816181> -8000021c: 4010d713 srai a4,ra,0x1 -80000220: c0c0ceb7 lui t4,0xc0c0c -80000224: 0c0e8e93 addi t4,t4,192 # c0c0c0c0 <_end+0x40c0a0c0> -80000228: 00d00193 li gp,13 -8000022c: 19d71a63 bne a4,t4,800003c0 - -80000230 : -80000230: 818180b7 lui ra,0x81818 -80000234: 18108093 addi ra,ra,385 # 81818181 <_end+0x1816181> -80000238: 4070d713 srai a4,ra,0x7 -8000023c: ff030eb7 lui t4,0xff030 -80000240: 303e8e93 addi t4,t4,771 # ff030303 <_end+0x7f02e303> -80000244: 00e00193 li gp,14 -80000248: 17d71c63 bne a4,t4,800003c0 - -8000024c : -8000024c: 818180b7 lui ra,0x81818 -80000250: 18108093 addi ra,ra,385 # 81818181 <_end+0x1816181> -80000254: 40e0d713 srai a4,ra,0xe -80000258: fffe0eb7 lui t4,0xfffe0 -8000025c: 606e8e93 addi t4,t4,1542 # fffe0606 <_end+0x7ffde606> -80000260: 00f00193 li gp,15 -80000264: 15d71e63 bne a4,t4,800003c0 - -80000268 : -80000268: 818180b7 lui ra,0x81818 -8000026c: 18108093 addi ra,ra,385 # 81818181 <_end+0x1816181> -80000270: 41f0d713 srai a4,ra,0x1f -80000274: fff00e93 li t4,-1 -80000278: 01000193 li gp,16 -8000027c: 15d71263 bne a4,t4,800003c0 - -80000280 : -80000280: 800000b7 lui ra,0x80000 -80000284: 4070d093 srai ra,ra,0x7 -80000288: ff000eb7 lui t4,0xff000 -8000028c: 01100193 li gp,17 -80000290: 13d09863 bne ra,t4,800003c0 - -80000294 : -80000294: 00000213 li tp,0 -80000298: 800000b7 lui ra,0x80000 -8000029c: 4070d713 srai a4,ra,0x7 -800002a0: 00070313 mv t1,a4 -800002a4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -800002a8: 00200293 li t0,2 -800002ac: fe5216e3 bne tp,t0,80000298 -800002b0: ff000eb7 lui t4,0xff000 -800002b4: 01200193 li gp,18 -800002b8: 11d31463 bne t1,t4,800003c0 - -800002bc : -800002bc: 00000213 li tp,0 -800002c0: 800000b7 lui ra,0x80000 -800002c4: 40e0d713 srai a4,ra,0xe -800002c8: 00000013 nop -800002cc: 00070313 mv t1,a4 -800002d0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -800002d4: 00200293 li t0,2 -800002d8: fe5214e3 bne tp,t0,800002c0 -800002dc: fffe0eb7 lui t4,0xfffe0 -800002e0: 01300193 li gp,19 -800002e4: 0dd31e63 bne t1,t4,800003c0 - -800002e8 : -800002e8: 00000213 li tp,0 -800002ec: 800000b7 lui ra,0x80000 -800002f0: 00108093 addi ra,ra,1 # 80000001 <_end+0xffffe001> -800002f4: 41f0d713 srai a4,ra,0x1f -800002f8: 00000013 nop -800002fc: 00000013 nop -80000300: 00070313 mv t1,a4 -80000304: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000308: 00200293 li t0,2 -8000030c: fe5210e3 bne tp,t0,800002ec -80000310: fff00e93 li t4,-1 -80000314: 01400193 li gp,20 -80000318: 0bd31463 bne t1,t4,800003c0 - -8000031c : -8000031c: 00000213 li tp,0 -80000320: 800000b7 lui ra,0x80000 -80000324: 4070d713 srai a4,ra,0x7 -80000328: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -8000032c: 00200293 li t0,2 -80000330: fe5218e3 bne tp,t0,80000320 -80000334: ff000eb7 lui t4,0xff000 -80000338: 01500193 li gp,21 -8000033c: 09d71263 bne a4,t4,800003c0 - -80000340 : -80000340: 00000213 li tp,0 -80000344: 800000b7 lui ra,0x80000 -80000348: 00000013 nop -8000034c: 40e0d713 srai a4,ra,0xe -80000350: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000354: 00200293 li t0,2 -80000358: fe5216e3 bne tp,t0,80000344 -8000035c: fffe0eb7 lui t4,0xfffe0 -80000360: 01600193 li gp,22 -80000364: 05d71e63 bne a4,t4,800003c0 - -80000368 : -80000368: 00000213 li tp,0 -8000036c: 800000b7 lui ra,0x80000 -80000370: 00108093 addi ra,ra,1 # 80000001 <_end+0xffffe001> -80000374: 00000013 nop -80000378: 00000013 nop -8000037c: 41f0d713 srai a4,ra,0x1f -80000380: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000384: 00200293 li t0,2 -80000388: fe5212e3 bne tp,t0,8000036c -8000038c: fff00e93 li t4,-1 -80000390: 01700193 li gp,23 -80000394: 03d71663 bne a4,t4,800003c0 - -80000398 : -80000398: 40405093 srai ra,zero,0x4 -8000039c: 00000e93 li t4,0 -800003a0: 01800193 li gp,24 -800003a4: 01d09e63 bne ra,t4,800003c0 - -800003a8 : -800003a8: 02100093 li ra,33 -800003ac: 40a0d013 srai zero,ra,0xa -800003b0: 00000e93 li t4,0 -800003b4: 01900193 li gp,25 -800003b8: 01d01463 bne zero,t4,800003c0 -800003bc: 02301063 bne zero,gp,800003dc - -800003c0 : -800003c0: 0ff0000f fence -800003c4: 00018063 beqz gp,800003c4 -800003c8: 00119193 slli gp,gp,0x1 -800003cc: 0011e193 ori gp,gp,1 -800003d0: 05d00893 li a7,93 -800003d4: 00018513 mv a0,gp -800003d8: 00000073 ecall - -800003dc : -800003dc: 0ff0000f fence -800003e0: 00100193 li gp,1 -800003e4: 05d00893 li a7,93 -800003e8: 00000513 li a0,0 -800003ec: 00000073 ecall -800003f0: c0001073 unimp -800003f4: 0000 unimp -800003f6: 0000 unimp -800003f8: 0000 unimp -800003fa: 0000 unimp -800003fc: 0000 unimp -800003fe: 0000 unimp -80000400: 0000 unimp -80000402: 0000 unimp diff --git a/benchmarks/riscv_tests/rv32ui-p-srai.hex b/benchmarks/riscv_tests/rv32ui-p-srai.hex deleted file mode 100644 index 6f388a08..00000000 --- a/benchmarks/riscv_tests/rv32ui-p-srai.hex +++ /dev/null @@ -1,69 +0,0 @@ -:0200000480007A -:100000006F00C004732F2034930F8000630AFF0336 -:10001000930F90006306FF03930FB0006302FF038A -:10002000170F0080130F0FFE63040F0067000F000F -:10003000732F203463540F006F004000136E9E53E3 -:10004000171F00002320CFFD6FF09FFF732540F1A5 -:100050006310050073251030635805000F00F00F82 -:10006000130E100073000000130E00009702000032 -:10007000938282F973905230735020307350303035 -:1000800073504030970200809382C2F7638C020065 -:10009000739052109302B01A739022307323203061 -:1000A000E39E62F873500030970200009382420191 -:1000B00073901234732540F17300203093000000D8 -:1000C00093D10040930E0000130E20006394D12BB7 -:1000D000B700008093D11040B70E00C0130E30005F -:1000E000639AD129B700008093D17040B70E00FF0A -:1000F000130E40006390D129B700008093D1E040F7 -:10010000B70EFEFF130E50006396D127B700008094 -:100110009380100093D1F041930EF0FF130E600016 -:10012000639AD125B70000809380F0FF93D10040FF -:10013000B70E0080938EFEFF130E7000639CD123D8 -:10014000B70000809380F0FF93D11040B70E0040BD -:10015000938EFEFF130E8000639ED121B7000080B6 -:100160009380F0FF93D17040B70E0001938EFEFF95 -:10017000130E90006390D121B70000809380F0FFB0 -:1001800093D1E040B70E0200938EFEFF130EA00045 -:100190006392D11FB70000809380F0FF93D1F041AC -:1001A000930E0000130EB0006396D11DB7808181BD -:1001B0009380101893D10040B78E8181938E1E18C2 -:1001C000130EC0006398D11BB780818193801018F3 -:1001D00093D11040B7CEC0C0938E0E0C130ED0003A -:1001E000639AD119B78081819380101893D17040A0 -:1001F000B70E03FF938E3E30130EE000639CD117C1 -:10020000B78081819380101893D1E040B70EFEFF34 -:10021000938E6E60130EF000639ED115B7808181BE -:100220009380101893D1F041930EF0FF130E00014C -:100230006392D115B700008093D07040B70E00FFD5 -:10024000130E10016398D01313020000B700008052 -:1002500093D1704013830100130212009302200017 -:10026000E31652FEB70E00FF130E20016314D311E4 -:1002700013020000B700008093D1E040130000009B -:10028000138301001302120093022000E31452FEB4 -:10029000B70EFEFF130E3001631ED30D13020000D4 -:1002A000B70000809380100093D1F041130000004C -:1002B00013000000138301001302120093022000B8 -:1002C000E31052FE930EF0FF130E40016314D30BA4 -:1002D00013020000B700008093D170401302120097 -:1002E00093022000E31852FEB70E00FF130E5001D8 -:1002F0006392D10913020000B700008013000000D0 -:1003000093D1E0401302120093022000E31652FE44 -:10031000B70EFEFF130E6001639ED10513020000AD -:10032000B70000809380100013000000130000004D -:1003300093D1F0411302120093022000E31252FE07 -:10034000930EF0FF130E70016396D103935040405B -:10035000930E0000130E8001639ED00193001002E3 -:1003600013D0A040930E0000130E90016314D0012F -:10037000631CC0010F00F00F63000E00131E1E006F -:10038000136E1E00730000000F00F00F130E10001C -:1003900073000000731000C00000000000000000A7 -:1003A000000000000000000000000000000000004D -:1003B000000000000000000000000000000000003D -:0403C0000000000039 -:1010000000000000000000000000000000000000E0 -:1010100000000000000000000000000000000000D0 -:1010200000000000000000000000000000000000C0 -:1010300000000000000000000000000000000000B0 -:081040000000000000000000A8 -:040000058000200057 -:00000001FF diff --git a/benchmarks/riscv_tests/rv32ui-p-srl.dump b/benchmarks/riscv_tests/rv32ui-p-srl.dump deleted file mode 100644 index fc0687dc..00000000 --- a/benchmarks/riscv_tests/rv32ui-p-srl.dump +++ /dev/null @@ -1,544 +0,0 @@ - -rv32ui-p-srl: file format elf32-littleriscv - - -Disassembly of section .text.init: - -80000000 <_start>: -80000000: 04c0006f j 8000004c - -80000004 : -80000004: 34202f73 csrr t5,mcause -80000008: 00800f93 li t6,8 -8000000c: 03ff0a63 beq t5,t6,80000040 -80000010: 00900f93 li t6,9 -80000014: 03ff0663 beq t5,t6,80000040 -80000018: 00b00f93 li t6,11 -8000001c: 03ff0263 beq t5,t6,80000040 -80000020: 80000f17 auipc t5,0x80000 -80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> -80000028: 000f0463 beqz t5,80000030 -8000002c: 000f0067 jr t5 -80000030: 34202f73 csrr t5,mcause -80000034: 000f5463 bgez t5,8000003c -80000038: 0040006f j 8000003c - -8000003c : -8000003c: 5391e193 ori gp,gp,1337 - -80000040 : -80000040: 00001f17 auipc t5,0x1 -80000044: fc3f2023 sw gp,-64(t5) # 80001000 -80000048: ff9ff06f j 80000040 - -8000004c : -8000004c: f1402573 csrr a0,mhartid -80000050: 00051063 bnez a0,80000050 -80000054: 00000297 auipc t0,0x0 -80000058: 01028293 addi t0,t0,16 # 80000064 -8000005c: 30529073 csrw mtvec,t0 -80000060: 18005073 csrwi sptbr,0 -80000064: 00000297 auipc t0,0x0 -80000068: 01c28293 addi t0,t0,28 # 80000080 -8000006c: 30529073 csrw mtvec,t0 -80000070: fff00293 li t0,-1 -80000074: 3b029073 csrw pmpaddr0,t0 -80000078: 01f00293 li t0,31 -8000007c: 3a029073 csrw pmpcfg0,t0 -80000080: 00000297 auipc t0,0x0 -80000084: 01828293 addi t0,t0,24 # 80000098 -80000088: 30529073 csrw mtvec,t0 -8000008c: 30205073 csrwi medeleg,0 -80000090: 30305073 csrwi mideleg,0 -80000094: 30405073 csrwi mie,0 -80000098: 00000193 li gp,0 -8000009c: 00000297 auipc t0,0x0 -800000a0: f6828293 addi t0,t0,-152 # 80000004 -800000a4: 30529073 csrw mtvec,t0 -800000a8: 00100513 li a0,1 -800000ac: 01f51513 slli a0,a0,0x1f -800000b0: 00054863 bltz a0,800000c0 -800000b4: 0ff0000f fence -800000b8: 00100193 li gp,1 -800000bc: 00000073 ecall -800000c0: 80000297 auipc t0,0x80000 -800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> -800000c8: 00028e63 beqz t0,800000e4 -800000cc: 10529073 csrw stvec,t0 -800000d0: 0000b2b7 lui t0,0xb -800000d4: 10928293 addi t0,t0,265 # b109 <_start-0x7fff4ef7> -800000d8: 30229073 csrw medeleg,t0 -800000dc: 30202373 csrr t1,medeleg -800000e0: f4629ee3 bne t0,t1,8000003c -800000e4: 30005073 csrwi mstatus,0 -800000e8: 00000297 auipc t0,0x0 -800000ec: 01428293 addi t0,t0,20 # 800000fc -800000f0: 34129073 csrw mepc,t0 -800000f4: f1402573 csrr a0,mhartid -800000f8: 30200073 mret - -800000fc : -800000fc: 800000b7 lui ra,0x80000 -80000100: 00000113 li sp,0 -80000104: 0020df33 srl t5,ra,sp -80000108: 80000eb7 lui t4,0x80000 -8000010c: 00200193 li gp,2 -80000110: 57df1863 bne t5,t4,80000680 - -80000114 : -80000114: 800000b7 lui ra,0x80000 -80000118: 00100113 li sp,1 -8000011c: 0020df33 srl t5,ra,sp -80000120: 40000eb7 lui t4,0x40000 -80000124: 00300193 li gp,3 -80000128: 55df1c63 bne t5,t4,80000680 - -8000012c : -8000012c: 800000b7 lui ra,0x80000 -80000130: 00700113 li sp,7 -80000134: 0020df33 srl t5,ra,sp -80000138: 01000eb7 lui t4,0x1000 -8000013c: 00400193 li gp,4 -80000140: 55df1063 bne t5,t4,80000680 - -80000144 : -80000144: 800000b7 lui ra,0x80000 -80000148: 00e00113 li sp,14 -8000014c: 0020df33 srl t5,ra,sp -80000150: 00020eb7 lui t4,0x20 -80000154: 00500193 li gp,5 -80000158: 53df1463 bne t5,t4,80000680 - -8000015c : -8000015c: 800000b7 lui ra,0x80000 -80000160: 00108093 addi ra,ra,1 # 80000001 -80000164: 01f00113 li sp,31 -80000168: 0020df33 srl t5,ra,sp -8000016c: 00100e93 li t4,1 -80000170: 00600193 li gp,6 -80000174: 51df1663 bne t5,t4,80000680 - -80000178 : -80000178: fff00093 li ra,-1 -8000017c: 00000113 li sp,0 -80000180: 0020df33 srl t5,ra,sp -80000184: fff00e93 li t4,-1 -80000188: 00700193 li gp,7 -8000018c: 4fdf1a63 bne t5,t4,80000680 - -80000190 : -80000190: fff00093 li ra,-1 -80000194: 00100113 li sp,1 -80000198: 0020df33 srl t5,ra,sp -8000019c: 80000eb7 lui t4,0x80000 -800001a0: fffe8e93 addi t4,t4,-1 # 7fffffff -800001a4: 00800193 li gp,8 -800001a8: 4ddf1c63 bne t5,t4,80000680 - -800001ac : -800001ac: fff00093 li ra,-1 -800001b0: 00700113 li sp,7 -800001b4: 0020df33 srl t5,ra,sp -800001b8: 02000eb7 lui t4,0x2000 -800001bc: fffe8e93 addi t4,t4,-1 # 1ffffff <_start-0x7e000001> -800001c0: 00900193 li gp,9 -800001c4: 4bdf1e63 bne t5,t4,80000680 - -800001c8 : -800001c8: fff00093 li ra,-1 -800001cc: 00e00113 li sp,14 -800001d0: 0020df33 srl t5,ra,sp -800001d4: 00040eb7 lui t4,0x40 -800001d8: fffe8e93 addi t4,t4,-1 # 3ffff <_start-0x7ffc0001> -800001dc: 00a00193 li gp,10 -800001e0: 4bdf1063 bne t5,t4,80000680 - -800001e4 : -800001e4: fff00093 li ra,-1 -800001e8: 01f00113 li sp,31 -800001ec: 0020df33 srl t5,ra,sp -800001f0: 00100e93 li t4,1 -800001f4: 00b00193 li gp,11 -800001f8: 49df1463 bne t5,t4,80000680 - -800001fc : -800001fc: 212120b7 lui ra,0x21212 -80000200: 12108093 addi ra,ra,289 # 21212121 <_start-0x5edededf> -80000204: 00000113 li sp,0 -80000208: 0020df33 srl t5,ra,sp -8000020c: 21212eb7 lui t4,0x21212 -80000210: 121e8e93 addi t4,t4,289 # 21212121 <_start-0x5edededf> -80000214: 00c00193 li gp,12 -80000218: 47df1463 bne t5,t4,80000680 - -8000021c : -8000021c: 212120b7 lui ra,0x21212 -80000220: 12108093 addi ra,ra,289 # 21212121 <_start-0x5edededf> -80000224: 00100113 li sp,1 -80000228: 0020df33 srl t5,ra,sp -8000022c: 10909eb7 lui t4,0x10909 -80000230: 090e8e93 addi t4,t4,144 # 10909090 <_start-0x6f6f6f70> -80000234: 00d00193 li gp,13 -80000238: 45df1463 bne t5,t4,80000680 - -8000023c : -8000023c: 212120b7 lui ra,0x21212 -80000240: 12108093 addi ra,ra,289 # 21212121 <_start-0x5edededf> -80000244: 00700113 li sp,7 -80000248: 0020df33 srl t5,ra,sp -8000024c: 00424eb7 lui t4,0x424 -80000250: 242e8e93 addi t4,t4,578 # 424242 <_start-0x7fbdbdbe> -80000254: 00e00193 li gp,14 -80000258: 43df1463 bne t5,t4,80000680 - -8000025c : -8000025c: 212120b7 lui ra,0x21212 -80000260: 12108093 addi ra,ra,289 # 21212121 <_start-0x5edededf> -80000264: 00e00113 li sp,14 -80000268: 0020df33 srl t5,ra,sp -8000026c: 00008eb7 lui t4,0x8 -80000270: 484e8e93 addi t4,t4,1156 # 8484 <_start-0x7fff7b7c> -80000274: 00f00193 li gp,15 -80000278: 41df1463 bne t5,t4,80000680 - -8000027c : -8000027c: 212120b7 lui ra,0x21212 -80000280: 12108093 addi ra,ra,289 # 21212121 <_start-0x5edededf> -80000284: 01f00113 li sp,31 -80000288: 0020df33 srl t5,ra,sp -8000028c: 00000e93 li t4,0 -80000290: 01000193 li gp,16 -80000294: 3fdf1663 bne t5,t4,80000680 - -80000298 : -80000298: 212120b7 lui ra,0x21212 -8000029c: 12108093 addi ra,ra,289 # 21212121 <_start-0x5edededf> -800002a0: fc000113 li sp,-64 -800002a4: 0020df33 srl t5,ra,sp -800002a8: 21212eb7 lui t4,0x21212 -800002ac: 121e8e93 addi t4,t4,289 # 21212121 <_start-0x5edededf> -800002b0: 01100193 li gp,17 -800002b4: 3ddf1663 bne t5,t4,80000680 - -800002b8 : -800002b8: 212120b7 lui ra,0x21212 -800002bc: 12108093 addi ra,ra,289 # 21212121 <_start-0x5edededf> -800002c0: fc100113 li sp,-63 -800002c4: 0020df33 srl t5,ra,sp -800002c8: 10909eb7 lui t4,0x10909 -800002cc: 090e8e93 addi t4,t4,144 # 10909090 <_start-0x6f6f6f70> -800002d0: 01200193 li gp,18 -800002d4: 3bdf1663 bne t5,t4,80000680 - -800002d8 : -800002d8: 212120b7 lui ra,0x21212 -800002dc: 12108093 addi ra,ra,289 # 21212121 <_start-0x5edededf> -800002e0: fc700113 li sp,-57 -800002e4: 0020df33 srl t5,ra,sp -800002e8: 00424eb7 lui t4,0x424 -800002ec: 242e8e93 addi t4,t4,578 # 424242 <_start-0x7fbdbdbe> -800002f0: 01300193 li gp,19 -800002f4: 39df1663 bne t5,t4,80000680 - -800002f8 : -800002f8: 212120b7 lui ra,0x21212 -800002fc: 12108093 addi ra,ra,289 # 21212121 <_start-0x5edededf> -80000300: fce00113 li sp,-50 -80000304: 0020df33 srl t5,ra,sp -80000308: 00008eb7 lui t4,0x8 -8000030c: 484e8e93 addi t4,t4,1156 # 8484 <_start-0x7fff7b7c> -80000310: 01400193 li gp,20 -80000314: 37df1663 bne t5,t4,80000680 - -80000318 : -80000318: 212120b7 lui ra,0x21212 -8000031c: 12108093 addi ra,ra,289 # 21212121 <_start-0x5edededf> -80000320: fff00113 li sp,-1 -80000324: 0020df33 srl t5,ra,sp -80000328: 00000e93 li t4,0 -8000032c: 01500193 li gp,21 -80000330: 35df1863 bne t5,t4,80000680 - -80000334 : -80000334: 800000b7 lui ra,0x80000 -80000338: 00700113 li sp,7 -8000033c: 0020d0b3 srl ra,ra,sp -80000340: 01000eb7 lui t4,0x1000 -80000344: 01600193 li gp,22 -80000348: 33d09c63 bne ra,t4,80000680 - -8000034c : -8000034c: 800000b7 lui ra,0x80000 -80000350: 00e00113 li sp,14 -80000354: 0020d133 srl sp,ra,sp -80000358: 00020eb7 lui t4,0x20 -8000035c: 01700193 li gp,23 -80000360: 33d11063 bne sp,t4,80000680 - -80000364 : -80000364: 00700093 li ra,7 -80000368: 0010d0b3 srl ra,ra,ra -8000036c: 00000e93 li t4,0 -80000370: 01800193 li gp,24 -80000374: 31d09663 bne ra,t4,80000680 - -80000378 : -80000378: 00000213 li tp,0 -8000037c: 800000b7 lui ra,0x80000 -80000380: 00700113 li sp,7 -80000384: 0020df33 srl t5,ra,sp -80000388: 000f0313 mv t1,t5 -8000038c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000390: 00200293 li t0,2 -80000394: fe5214e3 bne tp,t0,8000037c -80000398: 01000eb7 lui t4,0x1000 -8000039c: 01900193 li gp,25 -800003a0: 2fd31063 bne t1,t4,80000680 - -800003a4 : -800003a4: 00000213 li tp,0 -800003a8: 800000b7 lui ra,0x80000 -800003ac: 00e00113 li sp,14 -800003b0: 0020df33 srl t5,ra,sp -800003b4: 00000013 nop -800003b8: 000f0313 mv t1,t5 -800003bc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -800003c0: 00200293 li t0,2 -800003c4: fe5212e3 bne tp,t0,800003a8 -800003c8: 00020eb7 lui t4,0x20 -800003cc: 01a00193 li gp,26 -800003d0: 2bd31863 bne t1,t4,80000680 - -800003d4 : -800003d4: 00000213 li tp,0 -800003d8: 800000b7 lui ra,0x80000 -800003dc: 01f00113 li sp,31 -800003e0: 0020df33 srl t5,ra,sp -800003e4: 00000013 nop -800003e8: 00000013 nop -800003ec: 000f0313 mv t1,t5 -800003f0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -800003f4: 00200293 li t0,2 -800003f8: fe5210e3 bne tp,t0,800003d8 -800003fc: 00100e93 li t4,1 -80000400: 01b00193 li gp,27 -80000404: 27d31e63 bne t1,t4,80000680 - -80000408 : -80000408: 00000213 li tp,0 -8000040c: 800000b7 lui ra,0x80000 -80000410: 00700113 li sp,7 -80000414: 0020df33 srl t5,ra,sp -80000418: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -8000041c: 00200293 li t0,2 -80000420: fe5216e3 bne tp,t0,8000040c -80000424: 01000eb7 lui t4,0x1000 -80000428: 01c00193 li gp,28 -8000042c: 25df1a63 bne t5,t4,80000680 - -80000430 : -80000430: 00000213 li tp,0 -80000434: 800000b7 lui ra,0x80000 -80000438: 00e00113 li sp,14 -8000043c: 00000013 nop -80000440: 0020df33 srl t5,ra,sp -80000444: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000448: 00200293 li t0,2 -8000044c: fe5214e3 bne tp,t0,80000434 -80000450: 00020eb7 lui t4,0x20 -80000454: 01d00193 li gp,29 -80000458: 23df1463 bne t5,t4,80000680 - -8000045c : -8000045c: 00000213 li tp,0 -80000460: 800000b7 lui ra,0x80000 -80000464: 01f00113 li sp,31 -80000468: 00000013 nop -8000046c: 00000013 nop -80000470: 0020df33 srl t5,ra,sp -80000474: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000478: 00200293 li t0,2 -8000047c: fe5212e3 bne tp,t0,80000460 -80000480: 00100e93 li t4,1 -80000484: 01e00193 li gp,30 -80000488: 1fdf1c63 bne t5,t4,80000680 - -8000048c : -8000048c: 00000213 li tp,0 -80000490: 800000b7 lui ra,0x80000 -80000494: 00000013 nop -80000498: 00700113 li sp,7 -8000049c: 0020df33 srl t5,ra,sp -800004a0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -800004a4: 00200293 li t0,2 -800004a8: fe5214e3 bne tp,t0,80000490 -800004ac: 01000eb7 lui t4,0x1000 -800004b0: 01f00193 li gp,31 -800004b4: 1ddf1663 bne t5,t4,80000680 - -800004b8 : -800004b8: 00000213 li tp,0 -800004bc: 800000b7 lui ra,0x80000 -800004c0: 00000013 nop -800004c4: 00e00113 li sp,14 -800004c8: 00000013 nop -800004cc: 0020df33 srl t5,ra,sp -800004d0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -800004d4: 00200293 li t0,2 -800004d8: fe5212e3 bne tp,t0,800004bc -800004dc: 00020eb7 lui t4,0x20 -800004e0: 02000193 li gp,32 -800004e4: 19df1e63 bne t5,t4,80000680 - -800004e8 : -800004e8: 00000213 li tp,0 -800004ec: 800000b7 lui ra,0x80000 -800004f0: 00000013 nop -800004f4: 00000013 nop -800004f8: 01f00113 li sp,31 -800004fc: 0020df33 srl t5,ra,sp -80000500: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000504: 00200293 li t0,2 -80000508: fe5212e3 bne tp,t0,800004ec -8000050c: 00100e93 li t4,1 -80000510: 02100193 li gp,33 -80000514: 17df1663 bne t5,t4,80000680 - -80000518 : -80000518: 00000213 li tp,0 -8000051c: 00700113 li sp,7 -80000520: 800000b7 lui ra,0x80000 -80000524: 0020df33 srl t5,ra,sp -80000528: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -8000052c: 00200293 li t0,2 -80000530: fe5216e3 bne tp,t0,8000051c -80000534: 01000eb7 lui t4,0x1000 -80000538: 02200193 li gp,34 -8000053c: 15df1263 bne t5,t4,80000680 - -80000540 : -80000540: 00000213 li tp,0 -80000544: 00e00113 li sp,14 -80000548: 800000b7 lui ra,0x80000 -8000054c: 00000013 nop -80000550: 0020df33 srl t5,ra,sp -80000554: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000558: 00200293 li t0,2 -8000055c: fe5214e3 bne tp,t0,80000544 -80000560: 00020eb7 lui t4,0x20 -80000564: 02300193 li gp,35 -80000568: 11df1c63 bne t5,t4,80000680 - -8000056c : -8000056c: 00000213 li tp,0 -80000570: 01f00113 li sp,31 -80000574: 800000b7 lui ra,0x80000 -80000578: 00000013 nop -8000057c: 00000013 nop -80000580: 0020df33 srl t5,ra,sp -80000584: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000588: 00200293 li t0,2 -8000058c: fe5212e3 bne tp,t0,80000570 -80000590: 00100e93 li t4,1 -80000594: 02400193 li gp,36 -80000598: 0fdf1463 bne t5,t4,80000680 - -8000059c : -8000059c: 00000213 li tp,0 -800005a0: 00700113 li sp,7 -800005a4: 00000013 nop -800005a8: 800000b7 lui ra,0x80000 -800005ac: 0020df33 srl t5,ra,sp -800005b0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -800005b4: 00200293 li t0,2 -800005b8: fe5214e3 bne tp,t0,800005a0 -800005bc: 01000eb7 lui t4,0x1000 -800005c0: 02500193 li gp,37 -800005c4: 0bdf1e63 bne t5,t4,80000680 - -800005c8 : -800005c8: 00000213 li tp,0 -800005cc: 00e00113 li sp,14 -800005d0: 00000013 nop -800005d4: 800000b7 lui ra,0x80000 -800005d8: 00000013 nop -800005dc: 0020df33 srl t5,ra,sp -800005e0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -800005e4: 00200293 li t0,2 -800005e8: fe5212e3 bne tp,t0,800005cc -800005ec: 00020eb7 lui t4,0x20 -800005f0: 02600193 li gp,38 -800005f4: 09df1663 bne t5,t4,80000680 - -800005f8 : -800005f8: 00000213 li tp,0 -800005fc: 01f00113 li sp,31 -80000600: 00000013 nop -80000604: 00000013 nop -80000608: 800000b7 lui ra,0x80000 -8000060c: 0020df33 srl t5,ra,sp -80000610: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000614: 00200293 li t0,2 -80000618: fe5212e3 bne tp,t0,800005fc -8000061c: 00100e93 li t4,1 -80000620: 02700193 li gp,39 -80000624: 05df1e63 bne t5,t4,80000680 - -80000628 : -80000628: 00f00093 li ra,15 -8000062c: 00105133 srl sp,zero,ra -80000630: 00000e93 li t4,0 -80000634: 02800193 li gp,40 -80000638: 05d11463 bne sp,t4,80000680 - -8000063c : -8000063c: 02000093 li ra,32 -80000640: 0000d133 srl sp,ra,zero -80000644: 02000e93 li t4,32 -80000648: 02900193 li gp,41 -8000064c: 03d11a63 bne sp,t4,80000680 - -80000650 : -80000650: 000050b3 srl ra,zero,zero -80000654: 00000e93 li t4,0 -80000658: 02a00193 li gp,42 -8000065c: 03d09263 bne ra,t4,80000680 - -80000660 : -80000660: 40000093 li ra,1024 -80000664: 00001137 lui sp,0x1 -80000668: 80010113 addi sp,sp,-2048 # 800 <_start-0x7ffff800> -8000066c: 0020d033 srl zero,ra,sp -80000670: 00000e93 li t4,0 -80000674: 02b00193 li gp,43 -80000678: 01d01463 bne zero,t4,80000680 -8000067c: 00301c63 bne zero,gp,80000694 - -80000680 : -80000680: 0ff0000f fence -80000684: 00018063 beqz gp,80000684 -80000688: 00119193 slli gp,gp,0x1 -8000068c: 0011e193 ori gp,gp,1 -80000690: 00000073 ecall - -80000694 : -80000694: 0ff0000f fence -80000698: 00100193 li gp,1 -8000069c: 00000073 ecall -800006a0: c0001073 unimp -800006a4: 0000 unimp -800006a6: 0000 unimp -800006a8: 0000 unimp -800006aa: 0000 unimp -800006ac: 0000 unimp -800006ae: 0000 unimp -800006b0: 0000 unimp -800006b2: 0000 unimp -800006b4: 0000 unimp -800006b6: 0000 unimp -800006b8: 0000 unimp -800006ba: 0000 unimp -800006bc: 0000 unimp -800006be: 0000 unimp -800006c0: 0000 unimp -800006c2: 0000 unimp diff --git a/benchmarks/riscv_tests/rv32ui-p-srl.hex b/benchmarks/riscv_tests/rv32ui-p-srl.hex deleted file mode 100644 index 8f09b9ec..00000000 --- a/benchmarks/riscv_tests/rv32ui-p-srl.hex +++ /dev/null @@ -1,113 +0,0 @@ -:0200000480007A -:100000006F00C004732F2034930F8000630AFF0336 -:10001000930F90006306FF03930FB0006302FF038A -:10002000170F0080130F0FFE63040F0067000F000F -:10003000732F203463540F006F004000136E9E53E3 -:10004000171F00002320CFFD6FF09FFF732540F1A5 -:100050006310050073251030635805000F00F00F82 -:10006000130E100073000000130E00009702000032 -:10007000938282F973905230735020307350303035 -:1000800073504030970200809382C2F7638C020065 -:10009000739052109302B01A739022307323203061 -:1000A000E39E62F873500030970200009382420191 -:1000B00073901234732540F173002030B700008034 -:1000C00013010000B3D12000B70E0080130E2000F2 -:1000D0006398D157B700008013011000B3D12000FE -:1000E000B70E0040130E3000639CD155B70000805E -:1000F00013017000B3D12000B70E0001130E4000B1 -:100100006390D155B70000801301E000B3D1200007 -:10011000B70E0200130E50006394D153B700008055 -:10012000938010001301F001B3D12000930E100052 -:10013000130E60006396D1519300F0FF130100008D -:10014000B3D12000930EF0FF130E7000639AD14FCD -:100150009300F0FF13011000B3D12000B70E008010 -:10016000938EFEFF130E8000639CD14D9300F0FF31 -:1001700013017000B3D12000B70E0002938EFEFF72 -:10018000130E9000639ED14B9300F0FF1301E0002B -:10019000B3D12000B70E0400938EFEFF130EA00013 -:1001A0006390D14B9300F0FF1301F001B3D1200015 -:1001B000930E1000130EB0006394D149B720212193 -:1001C0009380101213010000B3D12000B72E21211B -:1001D000938E1E12130EC0006394D147B7202121C5 -:1001E0009380101213011000B3D12000B79E90101D -:1001F000938E0E09130ED0006394D145B7202121B0 -:100200009380101213017000B3D12000B74E42004A -:10021000938E2E24130EE0006394D143B720212146 -:10022000938010121301E000B3D12000B78E0000BC -:10023000938E4E48130EF0006394D141B7202121D4 -:10024000938010121301F001B3D12000930E00002F -:10025000130E00016396D13FB72021219380101225 -:10026000130100FCB3D12000B72E2121938E1E1262 -:10027000130E10016396D13DB720212193801012F7 -:10028000130110FCB3D12000B79E9010938E0E097D -:10029000130E20016396D13BB720212193801012C9 -:1002A000130170FCB3D12000B74E4200938E2E2470 -:1002B000130E30016396D139B7202121938010129B -:1002C0001301E0FCB3D12000B78E0000938E4E489E -:1002D000130E40016396D137B7202121938010126D -:1002E0001301F0FFB3D12000930E0000130E500154 -:1002F0006398D135B700008013017000B3D020009F -:10030000B70E0001130E6001639CD033B70000806C -:100310001301E00033D12000B70E0200130E70016C -:100320006310D13393007000B3D01000930E00001F -:10033000130E80016396D03113020000B7000080D5 -:1003400013017000B3D120001383010013021200C7 -:1003500093022000E31452FEB70E0001130E900129 -:100360006310D32F13020000B70000801301E000D8 -:10037000B3D1200013000000138301001302120008 -:1003800093022000E31252FEB70E0200130EA001EA -:100390006318D32B13020000B70000801301F00193 -:1003A000B3D12000130000001300000013830100EC -:1003B0001302120093022000E31052FE930E10006D -:1003C000130EB001631ED32713020000B700008094 -:1003D00013017000B3D12000130212009302200019 -:1003E000E31652FEB70E0001130EC001639AD12529 -:1003F00013020000B70000801301E00013000000AA -:10040000B3D120001302120093022000E31452FE25 -:10041000B70E0200130ED0016394D1231302000023 -:10042000B70000801301F00113000000130000006A -:10043000B3D120001302120093022000E31252FEF7 -:10044000930E1000130EE001639CD11F13020000F5 -:10045000B70000801300000013017000B3D120002A -:100460001302120093022000E31452FEB70E0001A3 -:10047000130EF0016396D11D13020000B700008037 -:10048000130000001301E00013000000B3D12000AE -:100490001302120093022000E31252FEB70E020074 -:1004A000130E0002639ED11913020000B7000080F2 -:1004B00013000000130000001301F001B3D120006D -:1004C0001302120093022000E31252FE930E10005A -:1004D000130E10026396D11713020000130170006F -:1004E000B7000080B3D12000130212009302200055 -:1004F000E31652FEB70E0001130E20026392D115CF -:10050000130200001301E000B70000801300000098 -:10051000B3D120001302120093022000E31452FE14 -:10052000B70E0200130E3002639CD11113020000BB -:100530001301F001B7000080130000001300000059 -:10054000B3D120001302120093022000E31252FEE6 -:10055000930E1000130E40026394D10F130200009B -:100560001301700013000000B7000080B3D1200019 -:100570001302120093022000E31452FEB70E000192 -:10058000130E5002639ED10B130200001301E00012 -:1005900013000000B700008013000000B3D120005A -:1005A0001302120093022000E31252FEB70E020063 -:1005B000130E60026396D109130200001301F001CB -:1005C0001300000013000000B7000080B3D120002A -:1005D0001302120093022000E31252FE930E100049 -:1005E000130E7002639ED1059300F000335110008A -:1005F000930E0000130E80026314D10593000002D5 -:1006000033D10000930E0002130E9002631AD1033F -:10061000B3500000930E0000130EA0026392D003AB -:1006200093000040371100001301018033D02000F7 -:10063000930E0000130EB0026314D001631CC001BE -:100640000F00F00F63000E00131E1E00136E1E003D -:10065000730000000F00F00F130E10007300000075 -:10066000731000C000000000000000000000000047 -:10067000000000000000000000000000000000007A -:040680000000000076 -:1010000000000000000000000000000000000000E0 -:1010100000000000000000000000000000000000D0 -:1010200000000000000000000000000000000000C0 -:1010300000000000000000000000000000000000B0 -:081040000000000000000000A8 -:040000058000200057 -:00000001FF diff --git a/benchmarks/riscv_tests/rv32ui-p-srli.dump b/benchmarks/riscv_tests/rv32ui-p-srli.dump deleted file mode 100644 index 4a09d141..00000000 --- a/benchmarks/riscv_tests/rv32ui-p-srli.dump +++ /dev/null @@ -1,309 +0,0 @@ - -rv32ui-p-srli: file format elf32-littleriscv - - -Disassembly of section .text.init: - -80000000 <_start>: -80000000: 04c0006f j 8000004c - -80000004 : -80000004: 34202f73 csrr t5,mcause -80000008: 00800f93 li t6,8 -8000000c: 03ff0a63 beq t5,t6,80000040 -80000010: 00900f93 li t6,9 -80000014: 03ff0663 beq t5,t6,80000040 -80000018: 00b00f93 li t6,11 -8000001c: 03ff0263 beq t5,t6,80000040 -80000020: 80000f17 auipc t5,0x80000 -80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> -80000028: 000f0463 beqz t5,80000030 -8000002c: 000f0067 jr t5 -80000030: 34202f73 csrr t5,mcause -80000034: 000f5463 bgez t5,8000003c -80000038: 0040006f j 8000003c - -8000003c : -8000003c: 5391e193 ori gp,gp,1337 - -80000040 : -80000040: 00001f17 auipc t5,0x1 -80000044: fc3f2023 sw gp,-64(t5) # 80001000 -80000048: ff9ff06f j 80000040 - -8000004c : -8000004c: f1402573 csrr a0,mhartid -80000050: 00051063 bnez a0,80000050 -80000054: 00000297 auipc t0,0x0 -80000058: 01028293 addi t0,t0,16 # 80000064 -8000005c: 30529073 csrw mtvec,t0 -80000060: 18005073 csrwi sptbr,0 -80000064: 00000297 auipc t0,0x0 -80000068: 01c28293 addi t0,t0,28 # 80000080 -8000006c: 30529073 csrw mtvec,t0 -80000070: fff00293 li t0,-1 -80000074: 3b029073 csrw pmpaddr0,t0 -80000078: 01f00293 li t0,31 -8000007c: 3a029073 csrw pmpcfg0,t0 -80000080: 00000297 auipc t0,0x0 -80000084: 01828293 addi t0,t0,24 # 80000098 -80000088: 30529073 csrw mtvec,t0 -8000008c: 30205073 csrwi medeleg,0 -80000090: 30305073 csrwi mideleg,0 -80000094: 30405073 csrwi mie,0 -80000098: 00000193 li gp,0 -8000009c: 00000297 auipc t0,0x0 -800000a0: f6828293 addi t0,t0,-152 # 80000004 -800000a4: 30529073 csrw mtvec,t0 -800000a8: 00100513 li a0,1 -800000ac: 01f51513 slli a0,a0,0x1f -800000b0: 00054863 bltz a0,800000c0 -800000b4: 0ff0000f fence -800000b8: 00100193 li gp,1 -800000bc: 00000073 ecall -800000c0: 80000297 auipc t0,0x80000 -800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> -800000c8: 00028e63 beqz t0,800000e4 -800000cc: 10529073 csrw stvec,t0 -800000d0: 0000b2b7 lui t0,0xb -800000d4: 10928293 addi t0,t0,265 # b109 <_start-0x7fff4ef7> -800000d8: 30229073 csrw medeleg,t0 -800000dc: 30202373 csrr t1,medeleg -800000e0: f4629ee3 bne t0,t1,8000003c -800000e4: 30005073 csrwi mstatus,0 -800000e8: 00000297 auipc t0,0x0 -800000ec: 01428293 addi t0,t0,20 # 800000fc -800000f0: 34129073 csrw mepc,t0 -800000f4: f1402573 csrr a0,mhartid -800000f8: 30200073 mret - -800000fc : -800000fc: 800000b7 lui ra,0x80000 -80000100: 0000df13 srli t5,ra,0x0 -80000104: 80000eb7 lui t4,0x80000 -80000108: 00200193 li gp,2 -8000010c: 29df1863 bne t5,t4,8000039c - -80000110 : -80000110: 800000b7 lui ra,0x80000 -80000114: 0010df13 srli t5,ra,0x1 -80000118: 40000eb7 lui t4,0x40000 -8000011c: 00300193 li gp,3 -80000120: 27df1e63 bne t5,t4,8000039c - -80000124 : -80000124: 800000b7 lui ra,0x80000 -80000128: 0070df13 srli t5,ra,0x7 -8000012c: 01000eb7 lui t4,0x1000 -80000130: 00400193 li gp,4 -80000134: 27df1463 bne t5,t4,8000039c - -80000138 : -80000138: 800000b7 lui ra,0x80000 -8000013c: 00e0df13 srli t5,ra,0xe -80000140: 00020eb7 lui t4,0x20 -80000144: 00500193 li gp,5 -80000148: 25df1a63 bne t5,t4,8000039c - -8000014c : -8000014c: 800000b7 lui ra,0x80000 -80000150: 00108093 addi ra,ra,1 # 80000001 -80000154: 01f0df13 srli t5,ra,0x1f -80000158: 00100e93 li t4,1 -8000015c: 00600193 li gp,6 -80000160: 23df1e63 bne t5,t4,8000039c - -80000164 : -80000164: fff00093 li ra,-1 -80000168: 0000df13 srli t5,ra,0x0 -8000016c: fff00e93 li t4,-1 -80000170: 00700193 li gp,7 -80000174: 23df1463 bne t5,t4,8000039c - -80000178 : -80000178: fff00093 li ra,-1 -8000017c: 0010df13 srli t5,ra,0x1 -80000180: 80000eb7 lui t4,0x80000 -80000184: fffe8e93 addi t4,t4,-1 # 7fffffff -80000188: 00800193 li gp,8 -8000018c: 21df1863 bne t5,t4,8000039c - -80000190 : -80000190: fff00093 li ra,-1 -80000194: 0070df13 srli t5,ra,0x7 -80000198: 02000eb7 lui t4,0x2000 -8000019c: fffe8e93 addi t4,t4,-1 # 1ffffff <_start-0x7e000001> -800001a0: 00900193 li gp,9 -800001a4: 1fdf1c63 bne t5,t4,8000039c - -800001a8 : -800001a8: fff00093 li ra,-1 -800001ac: 00e0df13 srli t5,ra,0xe -800001b0: 00040eb7 lui t4,0x40 -800001b4: fffe8e93 addi t4,t4,-1 # 3ffff <_start-0x7ffc0001> -800001b8: 00a00193 li gp,10 -800001bc: 1fdf1063 bne t5,t4,8000039c - -800001c0 : -800001c0: fff00093 li ra,-1 -800001c4: 01f0df13 srli t5,ra,0x1f -800001c8: 00100e93 li t4,1 -800001cc: 00b00193 li gp,11 -800001d0: 1ddf1663 bne t5,t4,8000039c - -800001d4 : -800001d4: 212120b7 lui ra,0x21212 -800001d8: 12108093 addi ra,ra,289 # 21212121 <_start-0x5edededf> -800001dc: 0000df13 srli t5,ra,0x0 -800001e0: 21212eb7 lui t4,0x21212 -800001e4: 121e8e93 addi t4,t4,289 # 21212121 <_start-0x5edededf> -800001e8: 00c00193 li gp,12 -800001ec: 1bdf1863 bne t5,t4,8000039c - -800001f0 : -800001f0: 212120b7 lui ra,0x21212 -800001f4: 12108093 addi ra,ra,289 # 21212121 <_start-0x5edededf> -800001f8: 0010df13 srli t5,ra,0x1 -800001fc: 10909eb7 lui t4,0x10909 -80000200: 090e8e93 addi t4,t4,144 # 10909090 <_start-0x6f6f6f70> -80000204: 00d00193 li gp,13 -80000208: 19df1a63 bne t5,t4,8000039c - -8000020c : -8000020c: 212120b7 lui ra,0x21212 -80000210: 12108093 addi ra,ra,289 # 21212121 <_start-0x5edededf> -80000214: 0070df13 srli t5,ra,0x7 -80000218: 00424eb7 lui t4,0x424 -8000021c: 242e8e93 addi t4,t4,578 # 424242 <_start-0x7fbdbdbe> -80000220: 00e00193 li gp,14 -80000224: 17df1c63 bne t5,t4,8000039c - -80000228 : -80000228: 212120b7 lui ra,0x21212 -8000022c: 12108093 addi ra,ra,289 # 21212121 <_start-0x5edededf> -80000230: 00e0df13 srli t5,ra,0xe -80000234: 00008eb7 lui t4,0x8 -80000238: 484e8e93 addi t4,t4,1156 # 8484 <_start-0x7fff7b7c> -8000023c: 00f00193 li gp,15 -80000240: 15df1e63 bne t5,t4,8000039c - -80000244 : -80000244: 212120b7 lui ra,0x21212 -80000248: 12108093 addi ra,ra,289 # 21212121 <_start-0x5edededf> -8000024c: 01f0df13 srli t5,ra,0x1f -80000250: 00000e93 li t4,0 -80000254: 01000193 li gp,16 -80000258: 15df1263 bne t5,t4,8000039c - -8000025c : -8000025c: 800000b7 lui ra,0x80000 -80000260: 0070d093 srli ra,ra,0x7 -80000264: 01000eb7 lui t4,0x1000 -80000268: 01100193 li gp,17 -8000026c: 13d09863 bne ra,t4,8000039c - -80000270 : -80000270: 00000213 li tp,0 -80000274: 800000b7 lui ra,0x80000 -80000278: 0070df13 srli t5,ra,0x7 -8000027c: 000f0313 mv t1,t5 -80000280: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000284: 00200293 li t0,2 -80000288: fe5216e3 bne tp,t0,80000274 -8000028c: 01000eb7 lui t4,0x1000 -80000290: 01200193 li gp,18 -80000294: 11d31463 bne t1,t4,8000039c - -80000298 : -80000298: 00000213 li tp,0 -8000029c: 800000b7 lui ra,0x80000 -800002a0: 00e0df13 srli t5,ra,0xe -800002a4: 00000013 nop -800002a8: 000f0313 mv t1,t5 -800002ac: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -800002b0: 00200293 li t0,2 -800002b4: fe5214e3 bne tp,t0,8000029c -800002b8: 00020eb7 lui t4,0x20 -800002bc: 01300193 li gp,19 -800002c0: 0dd31e63 bne t1,t4,8000039c - -800002c4 : -800002c4: 00000213 li tp,0 -800002c8: 800000b7 lui ra,0x80000 -800002cc: 00108093 addi ra,ra,1 # 80000001 -800002d0: 01f0df13 srli t5,ra,0x1f -800002d4: 00000013 nop -800002d8: 00000013 nop -800002dc: 000f0313 mv t1,t5 -800002e0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -800002e4: 00200293 li t0,2 -800002e8: fe5210e3 bne tp,t0,800002c8 -800002ec: 00100e93 li t4,1 -800002f0: 01400193 li gp,20 -800002f4: 0bd31463 bne t1,t4,8000039c - -800002f8 : -800002f8: 00000213 li tp,0 -800002fc: 800000b7 lui ra,0x80000 -80000300: 0070df13 srli t5,ra,0x7 -80000304: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000308: 00200293 li t0,2 -8000030c: fe5218e3 bne tp,t0,800002fc -80000310: 01000eb7 lui t4,0x1000 -80000314: 01500193 li gp,21 -80000318: 09df1263 bne t5,t4,8000039c - -8000031c : -8000031c: 00000213 li tp,0 -80000320: 800000b7 lui ra,0x80000 -80000324: 00000013 nop -80000328: 00e0df13 srli t5,ra,0xe -8000032c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000330: 00200293 li t0,2 -80000334: fe5216e3 bne tp,t0,80000320 -80000338: 00020eb7 lui t4,0x20 -8000033c: 01600193 li gp,22 -80000340: 05df1e63 bne t5,t4,8000039c - -80000344 : -80000344: 00000213 li tp,0 -80000348: 800000b7 lui ra,0x80000 -8000034c: 00108093 addi ra,ra,1 # 80000001 -80000350: 00000013 nop -80000354: 00000013 nop -80000358: 01f0df13 srli t5,ra,0x1f -8000035c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000360: 00200293 li t0,2 -80000364: fe5212e3 bne tp,t0,80000348 -80000368: 00100e93 li t4,1 -8000036c: 01700193 li gp,23 -80000370: 03df1663 bne t5,t4,8000039c - -80000374 : -80000374: 00405093 srli ra,zero,0x4 -80000378: 00000e93 li t4,0 -8000037c: 01800193 li gp,24 -80000380: 01d09e63 bne ra,t4,8000039c - -80000384 : -80000384: 02100093 li ra,33 -80000388: 00a0d013 srli zero,ra,0xa -8000038c: 00000e93 li t4,0 -80000390: 01900193 li gp,25 -80000394: 01d01463 bne zero,t4,8000039c -80000398: 00301c63 bne zero,gp,800003b0 - -8000039c : -8000039c: 0ff0000f fence -800003a0: 00018063 beqz gp,800003a0 -800003a4: 00119193 slli gp,gp,0x1 -800003a8: 0011e193 ori gp,gp,1 -800003ac: 00000073 ecall - -800003b0 : -800003b0: 0ff0000f fence -800003b4: 00100193 li gp,1 -800003b8: 00000073 ecall -800003bc: c0001073 unimp -800003c0: 0000 unimp -800003c2: 0000 unimp diff --git a/benchmarks/riscv_tests/rv32ui-p-srli.hex b/benchmarks/riscv_tests/rv32ui-p-srli.hex deleted file mode 100644 index b36084e3..00000000 --- a/benchmarks/riscv_tests/rv32ui-p-srli.hex +++ /dev/null @@ -1,65 +0,0 @@ -:0200000480007A -:100000006F00C004732F2034930F8000630AFF0336 -:10001000930F90006306FF03930FB0006302FF038A -:10002000170F0080130F0FFE63040F0067000F000F -:10003000732F203463540F006F004000136E9E53E3 -:10004000171F00002320CFFD6FF09FFF732540F1A5 -:100050006310050073251030635805000F00F00F82 -:10006000130E100073000000130E00009702000032 -:10007000938282F973905230735020307350303035 -:1000800073504030970200809382C2F7638C020065 -:10009000739052109302B01A739022307323203061 -:1000A000E39E62F873500030970200009382420191 -:1000B00073901234732540F173002030B700008034 -:1000C00093D10000B70E0080130E20006398D12951 -:1000D000B700008093D11000B70E0040130E30001F -:1000E000639ED127B700008093D17000B70E000146 -:1000F000130E40006394D127B700008093D1E00035 -:10010000B70E0200130E5000639AD125B70000808D -:100110009380100093D1F001930E1000130E600035 -:10012000639ED1239300F0FF93D10000930EF0FF64 -:10013000130E70006394D1239300F0FF93D110004D -:10014000B70E0080938EFEFF130E80006398D121BE -:100150009300F0FF93D17000B70E0002938EFEFF64 -:10016000130E9000639CD11F9300F0FF93D1E00029 -:10017000B70E0400938EFEFF130EA0006390D11FF4 -:100180009300F0FF93D1F001930E1000130EB00016 -:100190006396D11DB72021219380101293D10000C6 -:1001A000B72E2121938E1E12130EC0006398D11B0F -:1001B000B72021219380101293D11000B79E901088 -:1001C000938E0E09130ED000639AD119B720212106 -:1001D0009380101293D17000B74E4200938E2E245C -:1001E000130EE000639CD117B720212193801012D9 -:1001F00093D1E000B78E0000938E4E48130EF000AE -:10020000639ED115B72021219380101293D1F00164 -:10021000930E0000130E00016392D115B700008009 -:1002200093D07000B70E0001130E10016398D01325 -:1002300013020000B700008093D170001383010007 -:100240001302120093022000E31652FEB70E0001C3 -:10025000130E20016314D31113020000B7000080B5 -:1002600093D1E00013000000138301001302120079 -:1002700093022000E31452FEB70E0200130E300169 -:10028000631ED30D13020000B7000080938010009E -:1002900093D1F0011300000013000000138301004C -:1002A0001302120093022000E31052FE930E10007E -:1002B000130E40016314D30B13020000B70000803B -:1002C00093D170001302120093022000E31852FE33 -:1002D000B70E0001130E50016392D1091302000002 -:1002E000B70000801300000093D1E0001302120059 -:1002F00093022000E31652FEB70E0200130E6001B7 -:10030000639ED10513020000B700008093801000A7 -:10031000130000001300000093D1F001130212003B -:1003200093022000E31252FE930E1000130E700190 -:100330006396D10393504000930E0000130E80018A -:10034000639ED0019300100213D0A000930E000012 -:10035000130E90016314D001631CC0010F00F00F55 -:1003600063000E00131E1E00136E1E0073000000BB -:100370000F00F00F130E100073000000731000C088 -:040380000000000079 -:1010000000000000000000000000000000000000E0 -:1010100000000000000000000000000000000000D0 -:1010200000000000000000000000000000000000C0 -:1010300000000000000000000000000000000000B0 -:081040000000000000000000A8 -:040000058000200057 -:00000001FF diff --git a/benchmarks/riscv_tests/rv32ui-p-sub.dump b/benchmarks/riscv_tests/rv32ui-p-sub.dump deleted file mode 100644 index fd797213..00000000 --- a/benchmarks/riscv_tests/rv32ui-p-sub.dump +++ /dev/null @@ -1,478 +0,0 @@ - -rv32ui-p-sub: file format elf32-littleriscv - - -Disassembly of section .text.init: - -80000000 <_start>: -80000000: 04c0006f j 8000004c - -80000004 : -80000004: 34202f73 csrr t5,mcause -80000008: 00800f93 li t6,8 -8000000c: 03ff0a63 beq t5,t6,80000040 -80000010: 00900f93 li t6,9 -80000014: 03ff0663 beq t5,t6,80000040 -80000018: 00b00f93 li t6,11 -8000001c: 03ff0263 beq t5,t6,80000040 -80000020: 80000f17 auipc t5,0x80000 -80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> -80000028: 000f0463 beqz t5,80000030 -8000002c: 000f0067 jr t5 -80000030: 34202f73 csrr t5,mcause -80000034: 000f5463 bgez t5,8000003c -80000038: 0040006f j 8000003c - -8000003c : -8000003c: 5391e193 ori gp,gp,1337 - -80000040 : -80000040: 00001f17 auipc t5,0x1 -80000044: fc3f2023 sw gp,-64(t5) # 80001000 -80000048: ff9ff06f j 80000040 - -8000004c : -8000004c: f1402573 csrr a0,mhartid -80000050: 00051063 bnez a0,80000050 -80000054: 00000297 auipc t0,0x0 -80000058: 01028293 addi t0,t0,16 # 80000064 -8000005c: 30529073 csrw mtvec,t0 -80000060: 18005073 csrwi satp,0 -80000064: 00000297 auipc t0,0x0 -80000068: 02028293 addi t0,t0,32 # 80000084 -8000006c: 30529073 csrw mtvec,t0 -80000070: 800002b7 lui t0,0x80000 -80000074: fff28293 addi t0,t0,-1 # 7fffffff <_end+0xffffdfff> -80000078: 3b029073 csrw pmpaddr0,t0 -8000007c: 01f00293 li t0,31 -80000080: 3a029073 csrw pmpcfg0,t0 -80000084: 00000297 auipc t0,0x0 -80000088: 01828293 addi t0,t0,24 # 8000009c -8000008c: 30529073 csrw mtvec,t0 -80000090: 30205073 csrwi medeleg,0 -80000094: 30305073 csrwi mideleg,0 -80000098: 30405073 csrwi mie,0 -8000009c: 00000193 li gp,0 -800000a0: 00000297 auipc t0,0x0 -800000a4: f6428293 addi t0,t0,-156 # 80000004 -800000a8: 30529073 csrw mtvec,t0 -800000ac: 00100513 li a0,1 -800000b0: 01f51513 slli a0,a0,0x1f -800000b4: 00054c63 bltz a0,800000cc -800000b8: 0ff0000f fence -800000bc: 00100193 li gp,1 -800000c0: 05d00893 li a7,93 -800000c4: 00000513 li a0,0 -800000c8: 00000073 ecall -800000cc: 80000297 auipc t0,0x80000 -800000d0: f3428293 addi t0,t0,-204 # 0 <_start-0x80000000> -800000d4: 00028e63 beqz t0,800000f0 -800000d8: 10529073 csrw stvec,t0 -800000dc: 0000b2b7 lui t0,0xb -800000e0: 10928293 addi t0,t0,265 # b109 <_start-0x7fff4ef7> -800000e4: 30229073 csrw medeleg,t0 -800000e8: 30202373 csrr t1,medeleg -800000ec: f46298e3 bne t0,t1,8000003c -800000f0: 30005073 csrwi mstatus,0 -800000f4: 00000297 auipc t0,0x0 -800000f8: 01428293 addi t0,t0,20 # 80000108 -800000fc: 34129073 csrw mepc,t0 -80000100: f1402573 csrr a0,mhartid -80000104: 30200073 mret - -80000108 : -80000108: 00000093 li ra,0 -8000010c: 00000113 li sp,0 -80000110: 40208733 sub a4,ra,sp -80000114: 00000e93 li t4,0 -80000118: 00200193 li gp,2 -8000011c: 4bd71663 bne a4,t4,800005c8 - -80000120 : -80000120: 00100093 li ra,1 -80000124: 00100113 li sp,1 -80000128: 40208733 sub a4,ra,sp -8000012c: 00000e93 li t4,0 -80000130: 00300193 li gp,3 -80000134: 49d71a63 bne a4,t4,800005c8 - -80000138 : -80000138: 00300093 li ra,3 -8000013c: 00700113 li sp,7 -80000140: 40208733 sub a4,ra,sp -80000144: ffc00e93 li t4,-4 -80000148: 00400193 li gp,4 -8000014c: 47d71e63 bne a4,t4,800005c8 - -80000150 : -80000150: 00000093 li ra,0 -80000154: ffff8137 lui sp,0xffff8 -80000158: 40208733 sub a4,ra,sp -8000015c: 00008eb7 lui t4,0x8 -80000160: 00500193 li gp,5 -80000164: 47d71263 bne a4,t4,800005c8 - -80000168 : -80000168: 800000b7 lui ra,0x80000 -8000016c: 00000113 li sp,0 -80000170: 40208733 sub a4,ra,sp -80000174: 80000eb7 lui t4,0x80000 -80000178: 00600193 li gp,6 -8000017c: 45d71663 bne a4,t4,800005c8 - -80000180 : -80000180: 800000b7 lui ra,0x80000 -80000184: ffff8137 lui sp,0xffff8 -80000188: 40208733 sub a4,ra,sp -8000018c: 80008eb7 lui t4,0x80008 -80000190: 00700193 li gp,7 -80000194: 43d71a63 bne a4,t4,800005c8 - -80000198 : -80000198: 00000093 li ra,0 -8000019c: 00008137 lui sp,0x8 -800001a0: fff10113 addi sp,sp,-1 # 7fff <_start-0x7fff8001> -800001a4: 40208733 sub a4,ra,sp -800001a8: ffff8eb7 lui t4,0xffff8 -800001ac: 001e8e93 addi t4,t4,1 # ffff8001 <_end+0x7fff6001> -800001b0: 00800193 li gp,8 -800001b4: 41d71a63 bne a4,t4,800005c8 - -800001b8 : -800001b8: 800000b7 lui ra,0x80000 -800001bc: fff08093 addi ra,ra,-1 # 7fffffff <_end+0xffffdfff> -800001c0: 00000113 li sp,0 -800001c4: 40208733 sub a4,ra,sp -800001c8: 80000eb7 lui t4,0x80000 -800001cc: fffe8e93 addi t4,t4,-1 # 7fffffff <_end+0xffffdfff> -800001d0: 00900193 li gp,9 -800001d4: 3fd71a63 bne a4,t4,800005c8 - -800001d8 : -800001d8: 800000b7 lui ra,0x80000 -800001dc: fff08093 addi ra,ra,-1 # 7fffffff <_end+0xffffdfff> -800001e0: 00008137 lui sp,0x8 -800001e4: fff10113 addi sp,sp,-1 # 7fff <_start-0x7fff8001> -800001e8: 40208733 sub a4,ra,sp -800001ec: 7fff8eb7 lui t4,0x7fff8 -800001f0: 00a00193 li gp,10 -800001f4: 3dd71a63 bne a4,t4,800005c8 - -800001f8 : -800001f8: 800000b7 lui ra,0x80000 -800001fc: 00008137 lui sp,0x8 -80000200: fff10113 addi sp,sp,-1 # 7fff <_start-0x7fff8001> -80000204: 40208733 sub a4,ra,sp -80000208: 7fff8eb7 lui t4,0x7fff8 -8000020c: 001e8e93 addi t4,t4,1 # 7fff8001 <_start-0x7fff> -80000210: 00b00193 li gp,11 -80000214: 3bd71a63 bne a4,t4,800005c8 - -80000218 : -80000218: 800000b7 lui ra,0x80000 -8000021c: fff08093 addi ra,ra,-1 # 7fffffff <_end+0xffffdfff> -80000220: ffff8137 lui sp,0xffff8 -80000224: 40208733 sub a4,ra,sp -80000228: 80008eb7 lui t4,0x80008 -8000022c: fffe8e93 addi t4,t4,-1 # 80007fff <_end+0x5fff> -80000230: 00c00193 li gp,12 -80000234: 39d71a63 bne a4,t4,800005c8 - -80000238 : -80000238: 00000093 li ra,0 -8000023c: fff00113 li sp,-1 -80000240: 40208733 sub a4,ra,sp -80000244: 00100e93 li t4,1 -80000248: 00d00193 li gp,13 -8000024c: 37d71e63 bne a4,t4,800005c8 - -80000250 : -80000250: fff00093 li ra,-1 -80000254: 00100113 li sp,1 -80000258: 40208733 sub a4,ra,sp -8000025c: ffe00e93 li t4,-2 -80000260: 00e00193 li gp,14 -80000264: 37d71263 bne a4,t4,800005c8 - -80000268 : -80000268: fff00093 li ra,-1 -8000026c: fff00113 li sp,-1 -80000270: 40208733 sub a4,ra,sp -80000274: 00000e93 li t4,0 -80000278: 00f00193 li gp,15 -8000027c: 35d71663 bne a4,t4,800005c8 - -80000280 : -80000280: 00d00093 li ra,13 -80000284: 00b00113 li sp,11 -80000288: 402080b3 sub ra,ra,sp -8000028c: 00200e93 li t4,2 -80000290: 01000193 li gp,16 -80000294: 33d09a63 bne ra,t4,800005c8 - -80000298 : -80000298: 00e00093 li ra,14 -8000029c: 00b00113 li sp,11 -800002a0: 40208133 sub sp,ra,sp -800002a4: 00300e93 li t4,3 -800002a8: 01100193 li gp,17 -800002ac: 31d11e63 bne sp,t4,800005c8 - -800002b0 : -800002b0: 00d00093 li ra,13 -800002b4: 401080b3 sub ra,ra,ra -800002b8: 00000e93 li t4,0 -800002bc: 01200193 li gp,18 -800002c0: 31d09463 bne ra,t4,800005c8 - -800002c4 : -800002c4: 00000213 li tp,0 -800002c8: 00d00093 li ra,13 -800002cc: 00b00113 li sp,11 -800002d0: 40208733 sub a4,ra,sp -800002d4: 00070313 mv t1,a4 -800002d8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -800002dc: 00200293 li t0,2 -800002e0: fe5214e3 bne tp,t0,800002c8 -800002e4: 00200e93 li t4,2 -800002e8: 01300193 li gp,19 -800002ec: 2dd31e63 bne t1,t4,800005c8 - -800002f0 : -800002f0: 00000213 li tp,0 -800002f4: 00e00093 li ra,14 -800002f8: 00b00113 li sp,11 -800002fc: 40208733 sub a4,ra,sp -80000300: 00000013 nop -80000304: 00070313 mv t1,a4 -80000308: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -8000030c: 00200293 li t0,2 -80000310: fe5212e3 bne tp,t0,800002f4 -80000314: 00300e93 li t4,3 -80000318: 01400193 li gp,20 -8000031c: 2bd31663 bne t1,t4,800005c8 - -80000320 : -80000320: 00000213 li tp,0 -80000324: 00f00093 li ra,15 -80000328: 00b00113 li sp,11 -8000032c: 40208733 sub a4,ra,sp -80000330: 00000013 nop -80000334: 00000013 nop -80000338: 00070313 mv t1,a4 -8000033c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000340: 00200293 li t0,2 -80000344: fe5210e3 bne tp,t0,80000324 -80000348: 00400e93 li t4,4 -8000034c: 01500193 li gp,21 -80000350: 27d31c63 bne t1,t4,800005c8 - -80000354 : -80000354: 00000213 li tp,0 -80000358: 00d00093 li ra,13 -8000035c: 00b00113 li sp,11 -80000360: 40208733 sub a4,ra,sp -80000364: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000368: 00200293 li t0,2 -8000036c: fe5216e3 bne tp,t0,80000358 -80000370: 00200e93 li t4,2 -80000374: 01600193 li gp,22 -80000378: 25d71863 bne a4,t4,800005c8 - -8000037c : -8000037c: 00000213 li tp,0 -80000380: 00e00093 li ra,14 -80000384: 00b00113 li sp,11 -80000388: 00000013 nop -8000038c: 40208733 sub a4,ra,sp -80000390: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000394: 00200293 li t0,2 -80000398: fe5214e3 bne tp,t0,80000380 -8000039c: 00300e93 li t4,3 -800003a0: 01700193 li gp,23 -800003a4: 23d71263 bne a4,t4,800005c8 - -800003a8 : -800003a8: 00000213 li tp,0 -800003ac: 00f00093 li ra,15 -800003b0: 00b00113 li sp,11 -800003b4: 00000013 nop -800003b8: 00000013 nop -800003bc: 40208733 sub a4,ra,sp -800003c0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -800003c4: 00200293 li t0,2 -800003c8: fe5212e3 bne tp,t0,800003ac -800003cc: 00400e93 li t4,4 -800003d0: 01800193 li gp,24 -800003d4: 1fd71a63 bne a4,t4,800005c8 - -800003d8 : -800003d8: 00000213 li tp,0 -800003dc: 00d00093 li ra,13 -800003e0: 00000013 nop -800003e4: 00b00113 li sp,11 -800003e8: 40208733 sub a4,ra,sp -800003ec: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -800003f0: 00200293 li t0,2 -800003f4: fe5214e3 bne tp,t0,800003dc -800003f8: 00200e93 li t4,2 -800003fc: 01900193 li gp,25 -80000400: 1dd71463 bne a4,t4,800005c8 - -80000404 : -80000404: 00000213 li tp,0 -80000408: 00e00093 li ra,14 -8000040c: 00000013 nop -80000410: 00b00113 li sp,11 -80000414: 00000013 nop -80000418: 40208733 sub a4,ra,sp -8000041c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000420: 00200293 li t0,2 -80000424: fe5212e3 bne tp,t0,80000408 -80000428: 00300e93 li t4,3 -8000042c: 01a00193 li gp,26 -80000430: 19d71c63 bne a4,t4,800005c8 - -80000434 : -80000434: 00000213 li tp,0 -80000438: 00f00093 li ra,15 -8000043c: 00000013 nop -80000440: 00000013 nop -80000444: 00b00113 li sp,11 -80000448: 40208733 sub a4,ra,sp -8000044c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000450: 00200293 li t0,2 -80000454: fe5212e3 bne tp,t0,80000438 -80000458: 00400e93 li t4,4 -8000045c: 01b00193 li gp,27 -80000460: 17d71463 bne a4,t4,800005c8 - -80000464 : -80000464: 00000213 li tp,0 -80000468: 00b00113 li sp,11 -8000046c: 00d00093 li ra,13 -80000470: 40208733 sub a4,ra,sp -80000474: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000478: 00200293 li t0,2 -8000047c: fe5216e3 bne tp,t0,80000468 -80000480: 00200e93 li t4,2 -80000484: 01c00193 li gp,28 -80000488: 15d71063 bne a4,t4,800005c8 - -8000048c : -8000048c: 00000213 li tp,0 -80000490: 00b00113 li sp,11 -80000494: 00e00093 li ra,14 -80000498: 00000013 nop -8000049c: 40208733 sub a4,ra,sp -800004a0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -800004a4: 00200293 li t0,2 -800004a8: fe5214e3 bne tp,t0,80000490 -800004ac: 00300e93 li t4,3 -800004b0: 01d00193 li gp,29 -800004b4: 11d71a63 bne a4,t4,800005c8 - -800004b8 : -800004b8: 00000213 li tp,0 -800004bc: 00b00113 li sp,11 -800004c0: 00f00093 li ra,15 -800004c4: 00000013 nop -800004c8: 00000013 nop -800004cc: 40208733 sub a4,ra,sp -800004d0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -800004d4: 00200293 li t0,2 -800004d8: fe5212e3 bne tp,t0,800004bc -800004dc: 00400e93 li t4,4 -800004e0: 01e00193 li gp,30 -800004e4: 0fd71263 bne a4,t4,800005c8 - -800004e8 : -800004e8: 00000213 li tp,0 -800004ec: 00b00113 li sp,11 -800004f0: 00000013 nop -800004f4: 00d00093 li ra,13 -800004f8: 40208733 sub a4,ra,sp -800004fc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000500: 00200293 li t0,2 -80000504: fe5214e3 bne tp,t0,800004ec -80000508: 00200e93 li t4,2 -8000050c: 01f00193 li gp,31 -80000510: 0bd71c63 bne a4,t4,800005c8 - -80000514 : -80000514: 00000213 li tp,0 -80000518: 00b00113 li sp,11 -8000051c: 00000013 nop -80000520: 00e00093 li ra,14 -80000524: 00000013 nop -80000528: 40208733 sub a4,ra,sp -8000052c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000530: 00200293 li t0,2 -80000534: fe5212e3 bne tp,t0,80000518 -80000538: 00300e93 li t4,3 -8000053c: 02000193 li gp,32 -80000540: 09d71463 bne a4,t4,800005c8 - -80000544 : -80000544: 00000213 li tp,0 -80000548: 00b00113 li sp,11 -8000054c: 00000013 nop -80000550: 00000013 nop -80000554: 00f00093 li ra,15 -80000558: 40208733 sub a4,ra,sp -8000055c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000560: 00200293 li t0,2 -80000564: fe5212e3 bne tp,t0,80000548 -80000568: 00400e93 li t4,4 -8000056c: 02100193 li gp,33 -80000570: 05d71c63 bne a4,t4,800005c8 - -80000574 : -80000574: ff100093 li ra,-15 -80000578: 40100133 neg sp,ra -8000057c: 00f00e93 li t4,15 -80000580: 02200193 li gp,34 -80000584: 05d11263 bne sp,t4,800005c8 - -80000588 : -80000588: 02000093 li ra,32 -8000058c: 40008133 sub sp,ra,zero -80000590: 02000e93 li t4,32 -80000594: 02300193 li gp,35 -80000598: 03d11863 bne sp,t4,800005c8 - -8000059c : -8000059c: 400000b3 neg ra,zero -800005a0: 00000e93 li t4,0 -800005a4: 02400193 li gp,36 -800005a8: 03d09063 bne ra,t4,800005c8 - -800005ac : -800005ac: 01000093 li ra,16 -800005b0: 01e00113 li sp,30 -800005b4: 40208033 sub zero,ra,sp -800005b8: 00000e93 li t4,0 -800005bc: 02500193 li gp,37 -800005c0: 01d01463 bne zero,t4,800005c8 -800005c4: 02301063 bne zero,gp,800005e4 - -800005c8 : -800005c8: 0ff0000f fence -800005cc: 00018063 beqz gp,800005cc -800005d0: 00119193 slli gp,gp,0x1 -800005d4: 0011e193 ori gp,gp,1 -800005d8: 05d00893 li a7,93 -800005dc: 00018513 mv a0,gp -800005e0: 00000073 ecall - -800005e4 : -800005e4: 0ff0000f fence -800005e8: 00100193 li gp,1 -800005ec: 05d00893 li a7,93 -800005f0: 00000513 li a0,0 -800005f4: 00000073 ecall -800005f8: c0001073 unimp -800005fc: 0000 unimp -800005fe: 0000 unimp -80000600: 0000 unimp -80000602: 0000 unimp diff --git a/benchmarks/riscv_tests/rv32ui-p-sub.hex b/benchmarks/riscv_tests/rv32ui-p-sub.hex deleted file mode 100644 index aec1f5d4..00000000 --- a/benchmarks/riscv_tests/rv32ui-p-sub.hex +++ /dev/null @@ -1,101 +0,0 @@ -:0200000480007A -:100000006F00C004732F2034930F8000630AFF0336 -:10001000930F90006306FF03930FB0006302FF038A -:10002000170F0080130F0FFE63040F0067000F000F -:10003000732F203463540F006F004000136E9E53E3 -:10004000171F00002320CFFD6FF09FFF732540F1A5 -:100050006310050073251030635805000F00F00F82 -:10006000130E100073000000130E00009702000032 -:10007000938282F973905230735020307350303035 -:1000800073504030970200809382C2F7638C020065 -:10009000739052109302B01A739022307323203061 -:1000A000E39E62F873500030970200009382420191 -:1000B00073901234732540F17300203093000000D8 -:1000C00013010000B3812040930E0000130E2000A6 -:1000D0006396D14B9300100013011000B3812040B0 -:1000E000930E0000130E3000639AD1499300300044 -:1000F00013017000B3812040930EC0FF130E400027 -:10010000639ED147930000003781FFFFB3812040F9 -:10011000B78E0000130E50006392D147B7000080E5 -:1001200013010000B3812040B70E0080130E600061 -:100130006396D145B70000803781FFFFB38120402F -:10014000B78E0080130E7000639AD14393000000B5 -:10015000378100001301F1FFB3812040B78EFFFF0C -:10016000938E1E00130E8000639AD141B700008069 -:100170009380F0FF13010000B3812040B70E008090 -:10018000938EFEFF130E9000639AD13FB70000805C -:100190009380F0FF378100001301F1FFB38120400D -:1001A000B78EFF7F130EA000639AD13DB700008089 -:1001B000378100001301F1FFB3812040B78EFF7F2C -:1001C000938E1E00130EB000639AD13BB7000080DF -:1001D0009380F0FF3781FFFFB3812040B78E00800E -:1001E000938EFEFF130EC000639AD1399300000076 -:1001F0001301F0FFB3812040930E1000130ED000C6 -:10020000639ED1379300F0FF13011000B3812040AB -:10021000930EE0FF130EE0006392D1379300F0FFDE -:100220001301F0FFB3812040930E0000130EF00085 -:100230006396D1359300D0001301B000B380204005 -:10024000930E2000130E0001639AD0339300E00058 -:100250001301B00033812040930E3000130E1001C3 -:10026000631ED1319300D000B3801040930E000084 -:10027000130E20016394D031130200009300D000CC -:100280001301B000B3812040138301001302120058 -:1002900093022000E31452FE930E2000130E30014F -:1002A000631ED32D130200009300E0001301B00081 -:1002B000B3812040130000001383010013021200D9 -:1002C00093022000E31252FE930E3000130E400101 -:1002D0006316D32B130200009300F0001301B0004B -:1002E000B3812040130000001300000013830100BD -:1002F0001302120093022000E31052FE930E4000FE -:10030000130E5001631CD327130200009300D0008A -:100310001301B000B38120401302120093022000A9 -:10032000E31652FE930E2000130E60016398D12550 -:10033000130200009300E0001301B000130000005E -:10034000B38120401302120093022000E31452FEF6 -:10035000930E3000130E70016392D123130200003C -:100360009300F0001301B000130000001300000020 -:10037000B38120401302120093022000E31252FEC8 -:10038000930E4000130E8001639AD11F13020000E8 -:100390009300D000130000001301B000B38120408F -:1003A0001302120093022000E31452FE930E200069 -:1003B000130E90016394D11D130200009300E0001E -:1003C000130000001301B00013000000B3812040AF -:1003D0001302120093022000E31252FE930E30002B -:1003E000130EA001639CD119130200009300F000CA -:1003F00013000000130000001301B000B38120407F -:100400001302120093022000E31252FE930E4000EA -:10041000130EB0016394D117130200001301B00052 -:100420009300D000B38120401302120093022000F9 -:10043000E31652FE930E2000130EC0016390D115F7 -:10044000130200001301B0009300E000130000004D -:10045000B38120401302120093022000E31452FEE5 -:10046000930E3000130ED001639AD11113020000D5 -:100470001301B0009300F00013000000130000000F -:10048000B38120401302120093022000E31252FEB7 -:10049000930E4000130EE0016392D10F130200008F -:1004A0001301B000130000009300D000B38120407E -:1004B0001302120093022000E31452FE930E200058 -:1004C000130EF001639CD10B130200001301B00066 -:1004D000130000009300E00013000000B3812040EF -:1004E0001302120093022000E31252FE930E30001A -:1004F000130E00026394D109130200001301B0002F -:1005000013000000130000009300F000B3812040AE -:100510001302120093022000E31252FE930E4000D9 -:10052000130E1002639CD105930010FF330110409D -:10053000930EF000130E20026312D1059300000207 -:1005400033810040930E0002130E30026318D10372 -:10055000B3000040930E0000130E40026390D003DE -:10056000930000011301E00133802040930E00004E -:10057000130E50026314D001631CC0010F00F00F72 -:1005800063000E00131E1E00136E1E007300000099 -:100590000F00F00F130E100073000000731000C066 -:1005A000000000000000000000000000000000004B -:1005B000000000000000000000000000000000003B -:0405C0000000000037 -:1010000000000000000000000000000000000000E0 -:1010100000000000000000000000000000000000D0 -:1010200000000000000000000000000000000000C0 -:1010300000000000000000000000000000000000B0 -:081040000000000000000000A8 -:040000058000200057 -:00000001FF diff --git a/benchmarks/riscv_tests/rv32ui-p-sw.dump b/benchmarks/riscv_tests/rv32ui-p-sw.dump deleted file mode 100644 index 938362c9..00000000 --- a/benchmarks/riscv_tests/rv32ui-p-sw.dump +++ /dev/null @@ -1,469 +0,0 @@ - -rv32ui-p-sw: file format elf32-littleriscv - - -Disassembly of section .text.init: - -80000000 <_start>: -80000000: 04c0006f j 8000004c - -80000004 : -80000004: 34202f73 csrr t5,mcause -80000008: 00800f93 li t6,8 -8000000c: 03ff0a63 beq t5,t6,80000040 -80000010: 00900f93 li t6,9 -80000014: 03ff0663 beq t5,t6,80000040 -80000018: 00b00f93 li t6,11 -8000001c: 03ff0263 beq t5,t6,80000040 -80000020: 80000f17 auipc t5,0x80000 -80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> -80000028: 000f0463 beqz t5,80000030 -8000002c: 000f0067 jr t5 -80000030: 34202f73 csrr t5,mcause -80000034: 000f5463 bgez t5,8000003c -80000038: 0040006f j 8000003c - -8000003c : -8000003c: 5391e193 ori gp,gp,1337 - -80000040 : -80000040: 00001f17 auipc t5,0x1 -80000044: fc3f2023 sw gp,-64(t5) # 80001000 -80000048: ff9ff06f j 80000040 - -8000004c : -8000004c: f1402573 csrr a0,mhartid -80000050: 00051063 bnez a0,80000050 -80000054: 00000297 auipc t0,0x0 -80000058: 01028293 addi t0,t0,16 # 80000064 -8000005c: 30529073 csrw mtvec,t0 -80000060: 18005073 csrwi satp,0 -80000064: 00000297 auipc t0,0x0 -80000068: 02028293 addi t0,t0,32 # 80000084 -8000006c: 30529073 csrw mtvec,t0 -80000070: 800002b7 lui t0,0x80000 -80000074: fff28293 addi t0,t0,-1 # 7fffffff <_end+0xffffdfcf> -80000078: 3b029073 csrw pmpaddr0,t0 -8000007c: 01f00293 li t0,31 -80000080: 3a029073 csrw pmpcfg0,t0 -80000084: 00000297 auipc t0,0x0 -80000088: 01828293 addi t0,t0,24 # 8000009c -8000008c: 30529073 csrw mtvec,t0 -80000090: 30205073 csrwi medeleg,0 -80000094: 30305073 csrwi mideleg,0 -80000098: 30405073 csrwi mie,0 -8000009c: 00000193 li gp,0 -800000a0: 00000297 auipc t0,0x0 -800000a4: f6428293 addi t0,t0,-156 # 80000004 -800000a8: 30529073 csrw mtvec,t0 -800000ac: 00100513 li a0,1 -800000b0: 01f51513 slli a0,a0,0x1f -800000b4: 00054c63 bltz a0,800000cc -800000b8: 0ff0000f fence -800000bc: 00100193 li gp,1 -800000c0: 05d00893 li a7,93 -800000c4: 00000513 li a0,0 -800000c8: 00000073 ecall -800000cc: 80000297 auipc t0,0x80000 -800000d0: f3428293 addi t0,t0,-204 # 0 <_start-0x80000000> -800000d4: 00028e63 beqz t0,800000f0 -800000d8: 10529073 csrw stvec,t0 -800000dc: 0000b2b7 lui t0,0xb -800000e0: 10928293 addi t0,t0,265 # b109 <_start-0x7fff4ef7> -800000e4: 30229073 csrw medeleg,t0 -800000e8: 30202373 csrr t1,medeleg -800000ec: f46298e3 bne t0,t1,8000003c -800000f0: 30005073 csrwi mstatus,0 -800000f4: 00000297 auipc t0,0x0 -800000f8: 01428293 addi t0,t0,20 # 80000108 -800000fc: 34129073 csrw mepc,t0 -80000100: f1402573 csrr a0,mhartid -80000104: 30200073 mret - -80000108 : -80000108: 00002097 auipc ra,0x2 -8000010c: ef808093 addi ra,ra,-264 # 80002000 -80000110: 00aa0137 lui sp,0xaa0 -80000114: 0aa10113 addi sp,sp,170 # aa00aa <_start-0x7f55ff56> -80000118: 0020a023 sw sp,0(ra) -8000011c: 0000a703 lw a4,0(ra) -80000120: 00aa0eb7 lui t4,0xaa0 -80000124: 0aae8e93 addi t4,t4,170 # aa00aa <_start-0x7f55ff56> -80000128: 00200193 li gp,2 -8000012c: 47d71063 bne a4,t4,8000058c - -80000130 : -80000130: 00002097 auipc ra,0x2 -80000134: ed008093 addi ra,ra,-304 # 80002000 -80000138: aa00b137 lui sp,0xaa00b -8000013c: a0010113 addi sp,sp,-1536 # aa00aa00 <_end+0x2a0089d0> -80000140: 0020a223 sw sp,4(ra) -80000144: 0040a703 lw a4,4(ra) -80000148: aa00beb7 lui t4,0xaa00b -8000014c: a00e8e93 addi t4,t4,-1536 # aa00aa00 <_end+0x2a0089d0> -80000150: 00300193 li gp,3 -80000154: 43d71c63 bne a4,t4,8000058c - -80000158 : -80000158: 00002097 auipc ra,0x2 -8000015c: ea808093 addi ra,ra,-344 # 80002000 -80000160: 0aa01137 lui sp,0xaa01 -80000164: aa010113 addi sp,sp,-1376 # aa00aa0 <_start-0x755ff560> -80000168: 0020a423 sw sp,8(ra) -8000016c: 0080a703 lw a4,8(ra) -80000170: 0aa01eb7 lui t4,0xaa01 -80000174: aa0e8e93 addi t4,t4,-1376 # aa00aa0 <_start-0x755ff560> -80000178: 00400193 li gp,4 -8000017c: 41d71863 bne a4,t4,8000058c - -80000180 : -80000180: 00002097 auipc ra,0x2 -80000184: e8008093 addi ra,ra,-384 # 80002000 -80000188: a00aa137 lui sp,0xa00aa -8000018c: 00a10113 addi sp,sp,10 # a00aa00a <_end+0x200a7fda> -80000190: 0020a623 sw sp,12(ra) -80000194: 00c0a703 lw a4,12(ra) -80000198: a00aaeb7 lui t4,0xa00aa -8000019c: 00ae8e93 addi t4,t4,10 # a00aa00a <_end+0x200a7fda> -800001a0: 00500193 li gp,5 -800001a4: 3fd71463 bne a4,t4,8000058c - -800001a8 : -800001a8: 00002097 auipc ra,0x2 -800001ac: e7408093 addi ra,ra,-396 # 8000201c -800001b0: 00aa0137 lui sp,0xaa0 -800001b4: 0aa10113 addi sp,sp,170 # aa00aa <_start-0x7f55ff56> -800001b8: fe20aa23 sw sp,-12(ra) -800001bc: ff40a703 lw a4,-12(ra) -800001c0: 00aa0eb7 lui t4,0xaa0 -800001c4: 0aae8e93 addi t4,t4,170 # aa00aa <_start-0x7f55ff56> -800001c8: 00600193 li gp,6 -800001cc: 3dd71063 bne a4,t4,8000058c - -800001d0 : -800001d0: 00002097 auipc ra,0x2 -800001d4: e4c08093 addi ra,ra,-436 # 8000201c -800001d8: aa00b137 lui sp,0xaa00b -800001dc: a0010113 addi sp,sp,-1536 # aa00aa00 <_end+0x2a0089d0> -800001e0: fe20ac23 sw sp,-8(ra) -800001e4: ff80a703 lw a4,-8(ra) -800001e8: aa00beb7 lui t4,0xaa00b -800001ec: a00e8e93 addi t4,t4,-1536 # aa00aa00 <_end+0x2a0089d0> -800001f0: 00700193 li gp,7 -800001f4: 39d71c63 bne a4,t4,8000058c - -800001f8 : -800001f8: 00002097 auipc ra,0x2 -800001fc: e2408093 addi ra,ra,-476 # 8000201c -80000200: 0aa01137 lui sp,0xaa01 -80000204: aa010113 addi sp,sp,-1376 # aa00aa0 <_start-0x755ff560> -80000208: fe20ae23 sw sp,-4(ra) -8000020c: ffc0a703 lw a4,-4(ra) -80000210: 0aa01eb7 lui t4,0xaa01 -80000214: aa0e8e93 addi t4,t4,-1376 # aa00aa0 <_start-0x755ff560> -80000218: 00800193 li gp,8 -8000021c: 37d71863 bne a4,t4,8000058c - -80000220 : -80000220: 00002097 auipc ra,0x2 -80000224: dfc08093 addi ra,ra,-516 # 8000201c -80000228: a00aa137 lui sp,0xa00aa -8000022c: 00a10113 addi sp,sp,10 # a00aa00a <_end+0x200a7fda> -80000230: 0020a023 sw sp,0(ra) -80000234: 0000a703 lw a4,0(ra) -80000238: a00aaeb7 lui t4,0xa00aa -8000023c: 00ae8e93 addi t4,t4,10 # a00aa00a <_end+0x200a7fda> -80000240: 00900193 li gp,9 -80000244: 35d71463 bne a4,t4,8000058c - -80000248 : -80000248: 00002097 auipc ra,0x2 -8000024c: dd808093 addi ra,ra,-552 # 80002020 -80000250: 12345137 lui sp,0x12345 -80000254: 67810113 addi sp,sp,1656 # 12345678 <_start-0x6dcba988> -80000258: fe008213 addi tp,ra,-32 -8000025c: 02222023 sw sp,32(tp) # 20 <_start-0x7fffffe0> -80000260: 0000a283 lw t0,0(ra) -80000264: 12345eb7 lui t4,0x12345 -80000268: 678e8e93 addi t4,t4,1656 # 12345678 <_start-0x6dcba988> -8000026c: 00a00193 li gp,10 -80000270: 31d29e63 bne t0,t4,8000058c - -80000274 : -80000274: 00002097 auipc ra,0x2 -80000278: dac08093 addi ra,ra,-596 # 80002020 -8000027c: 58213137 lui sp,0x58213 -80000280: 09810113 addi sp,sp,152 # 58213098 <_start-0x27decf68> -80000284: ffd08093 addi ra,ra,-3 -80000288: 0020a3a3 sw sp,7(ra) -8000028c: 00002217 auipc tp,0x2 -80000290: d9820213 addi tp,tp,-616 # 80002024 -80000294: 00022283 lw t0,0(tp) # 0 <_start-0x80000000> -80000298: 58213eb7 lui t4,0x58213 -8000029c: 098e8e93 addi t4,t4,152 # 58213098 <_start-0x27decf68> -800002a0: 00b00193 li gp,11 -800002a4: 2fd29463 bne t0,t4,8000058c - -800002a8 : -800002a8: 00c00193 li gp,12 -800002ac: 00000213 li tp,0 -800002b0: aabbd0b7 lui ra,0xaabbd -800002b4: cdd08093 addi ra,ra,-803 # aabbccdd <_end+0x2abbacad> -800002b8: 00002117 auipc sp,0x2 -800002bc: d4810113 addi sp,sp,-696 # 80002000 -800002c0: 00112023 sw ra,0(sp) -800002c4: 00012703 lw a4,0(sp) -800002c8: aabbdeb7 lui t4,0xaabbd -800002cc: cdde8e93 addi t4,t4,-803 # aabbccdd <_end+0x2abbacad> -800002d0: 2bd71e63 bne a4,t4,8000058c -800002d4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -800002d8: 00200293 li t0,2 -800002dc: fc521ae3 bne tp,t0,800002b0 - -800002e0 : -800002e0: 00d00193 li gp,13 -800002e4: 00000213 li tp,0 -800002e8: daabc0b7 lui ra,0xdaabc -800002ec: ccd08093 addi ra,ra,-819 # daabbccd <_end+0x5aab9c9d> -800002f0: 00002117 auipc sp,0x2 -800002f4: d1010113 addi sp,sp,-752 # 80002000 -800002f8: 00000013 nop -800002fc: 00112223 sw ra,4(sp) -80000300: 00412703 lw a4,4(sp) -80000304: daabceb7 lui t4,0xdaabc -80000308: ccde8e93 addi t4,t4,-819 # daabbccd <_end+0x5aab9c9d> -8000030c: 29d71063 bne a4,t4,8000058c -80000310: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000314: 00200293 li t0,2 -80000318: fc5218e3 bne tp,t0,800002e8 - -8000031c : -8000031c: 00e00193 li gp,14 -80000320: 00000213 li tp,0 -80000324: ddaac0b7 lui ra,0xddaac -80000328: bcc08093 addi ra,ra,-1076 # ddaabbcc <_end+0x5daa9b9c> -8000032c: 00002117 auipc sp,0x2 -80000330: cd410113 addi sp,sp,-812 # 80002000 -80000334: 00000013 nop -80000338: 00000013 nop -8000033c: 00112423 sw ra,8(sp) -80000340: 00812703 lw a4,8(sp) -80000344: ddaaceb7 lui t4,0xddaac -80000348: bcce8e93 addi t4,t4,-1076 # ddaabbcc <_end+0x5daa9b9c> -8000034c: 25d71063 bne a4,t4,8000058c -80000350: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000354: 00200293 li t0,2 -80000358: fc5216e3 bne tp,t0,80000324 - -8000035c : -8000035c: 00f00193 li gp,15 -80000360: 00000213 li tp,0 -80000364: cddab0b7 lui ra,0xcddab -80000368: bbc08093 addi ra,ra,-1092 # cddaabbc <_end+0x4dda8b8c> -8000036c: 00000013 nop -80000370: 00002117 auipc sp,0x2 -80000374: c9010113 addi sp,sp,-880 # 80002000 -80000378: 00112623 sw ra,12(sp) -8000037c: 00c12703 lw a4,12(sp) -80000380: cddabeb7 lui t4,0xcddab -80000384: bbce8e93 addi t4,t4,-1092 # cddaabbc <_end+0x4dda8b8c> -80000388: 21d71263 bne a4,t4,8000058c -8000038c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000390: 00200293 li t0,2 -80000394: fc5218e3 bne tp,t0,80000364 - -80000398 : -80000398: 01000193 li gp,16 -8000039c: 00000213 li tp,0 -800003a0: ccddb0b7 lui ra,0xccddb -800003a4: abb08093 addi ra,ra,-1349 # ccddaabb <_end+0x4cdd8a8b> -800003a8: 00000013 nop -800003ac: 00002117 auipc sp,0x2 -800003b0: c5410113 addi sp,sp,-940 # 80002000 -800003b4: 00000013 nop -800003b8: 00112823 sw ra,16(sp) -800003bc: 01012703 lw a4,16(sp) -800003c0: ccddbeb7 lui t4,0xccddb -800003c4: abbe8e93 addi t4,t4,-1349 # ccddaabb <_end+0x4cdd8a8b> -800003c8: 1dd71263 bne a4,t4,8000058c -800003cc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -800003d0: 00200293 li t0,2 -800003d4: fc5216e3 bne tp,t0,800003a0 - -800003d8 : -800003d8: 01100193 li gp,17 -800003dc: 00000213 li tp,0 -800003e0: bccde0b7 lui ra,0xbccde -800003e4: aab08093 addi ra,ra,-1365 # bccddaab <_end+0x3ccdba7b> -800003e8: 00000013 nop -800003ec: 00000013 nop -800003f0: 00002117 auipc sp,0x2 -800003f4: c1010113 addi sp,sp,-1008 # 80002000 -800003f8: 00112a23 sw ra,20(sp) -800003fc: 01412703 lw a4,20(sp) -80000400: bccdeeb7 lui t4,0xbccde -80000404: aabe8e93 addi t4,t4,-1365 # bccddaab <_end+0x3ccdba7b> -80000408: 19d71263 bne a4,t4,8000058c -8000040c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000410: 00200293 li t0,2 -80000414: fc5216e3 bne tp,t0,800003e0 - -80000418 : -80000418: 01200193 li gp,18 -8000041c: 00000213 li tp,0 -80000420: 00002117 auipc sp,0x2 -80000424: be010113 addi sp,sp,-1056 # 80002000 -80000428: 001120b7 lui ra,0x112 -8000042c: 23308093 addi ra,ra,563 # 112233 <_start-0x7feeddcd> -80000430: 00112023 sw ra,0(sp) -80000434: 00012703 lw a4,0(sp) -80000438: 00112eb7 lui t4,0x112 -8000043c: 233e8e93 addi t4,t4,563 # 112233 <_start-0x7feeddcd> -80000440: 15d71663 bne a4,t4,8000058c -80000444: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000448: 00200293 li t0,2 -8000044c: fc521ae3 bne tp,t0,80000420 - -80000450 : -80000450: 01300193 li gp,19 -80000454: 00000213 li tp,0 -80000458: 00002117 auipc sp,0x2 -8000045c: ba810113 addi sp,sp,-1112 # 80002000 -80000460: 300110b7 lui ra,0x30011 -80000464: 22308093 addi ra,ra,547 # 30011223 <_start-0x4ffeeddd> -80000468: 00000013 nop -8000046c: 00112223 sw ra,4(sp) -80000470: 00412703 lw a4,4(sp) -80000474: 30011eb7 lui t4,0x30011 -80000478: 223e8e93 addi t4,t4,547 # 30011223 <_start-0x4ffeeddd> -8000047c: 11d71863 bne a4,t4,8000058c -80000480: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000484: 00200293 li t0,2 -80000488: fc5218e3 bne tp,t0,80000458 - -8000048c : -8000048c: 01400193 li gp,20 -80000490: 00000213 li tp,0 -80000494: 00002117 auipc sp,0x2 -80000498: b6c10113 addi sp,sp,-1172 # 80002000 -8000049c: 330010b7 lui ra,0x33001 -800004a0: 12208093 addi ra,ra,290 # 33001122 <_start-0x4cffeede> -800004a4: 00000013 nop -800004a8: 00000013 nop -800004ac: 00112423 sw ra,8(sp) -800004b0: 00812703 lw a4,8(sp) -800004b4: 33001eb7 lui t4,0x33001 -800004b8: 122e8e93 addi t4,t4,290 # 33001122 <_start-0x4cffeede> -800004bc: 0dd71863 bne a4,t4,8000058c -800004c0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -800004c4: 00200293 li t0,2 -800004c8: fc5216e3 bne tp,t0,80000494 - -800004cc : -800004cc: 01500193 li gp,21 -800004d0: 00000213 li tp,0 -800004d4: 00002117 auipc sp,0x2 -800004d8: b2c10113 addi sp,sp,-1236 # 80002000 -800004dc: 00000013 nop -800004e0: 233000b7 lui ra,0x23300 -800004e4: 11208093 addi ra,ra,274 # 23300112 <_start-0x5ccffeee> -800004e8: 00112623 sw ra,12(sp) -800004ec: 00c12703 lw a4,12(sp) -800004f0: 23300eb7 lui t4,0x23300 -800004f4: 112e8e93 addi t4,t4,274 # 23300112 <_start-0x5ccffeee> -800004f8: 09d71a63 bne a4,t4,8000058c -800004fc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000500: 00200293 li t0,2 -80000504: fc5218e3 bne tp,t0,800004d4 - -80000508 : -80000508: 01600193 li gp,22 -8000050c: 00000213 li tp,0 -80000510: 00002117 auipc sp,0x2 -80000514: af010113 addi sp,sp,-1296 # 80002000 -80000518: 00000013 nop -8000051c: 223300b7 lui ra,0x22330 -80000520: 01108093 addi ra,ra,17 # 22330011 <_start-0x5dccffef> -80000524: 00000013 nop -80000528: 00112823 sw ra,16(sp) -8000052c: 01012703 lw a4,16(sp) -80000530: 22330eb7 lui t4,0x22330 -80000534: 011e8e93 addi t4,t4,17 # 22330011 <_start-0x5dccffef> -80000538: 05d71a63 bne a4,t4,8000058c -8000053c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000540: 00200293 li t0,2 -80000544: fc5216e3 bne tp,t0,80000510 - -80000548 : -80000548: 01700193 li gp,23 -8000054c: 00000213 li tp,0 -80000550: 00002117 auipc sp,0x2 -80000554: ab010113 addi sp,sp,-1360 # 80002000 -80000558: 00000013 nop -8000055c: 00000013 nop -80000560: 122330b7 lui ra,0x12233 -80000564: 00108093 addi ra,ra,1 # 12233001 <_start-0x6ddccfff> -80000568: 00112a23 sw ra,20(sp) -8000056c: 01412703 lw a4,20(sp) -80000570: 12233eb7 lui t4,0x12233 -80000574: 001e8e93 addi t4,t4,1 # 12233001 <_start-0x6ddccfff> -80000578: 01d71a63 bne a4,t4,8000058c -8000057c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000580: 00200293 li t0,2 -80000584: fc5216e3 bne tp,t0,80000550 -80000588: 02301063 bne zero,gp,800005a8 - -8000058c : -8000058c: 0ff0000f fence -80000590: 00018063 beqz gp,80000590 -80000594: 00119193 slli gp,gp,0x1 -80000598: 0011e193 ori gp,gp,1 -8000059c: 05d00893 li a7,93 -800005a0: 00018513 mv a0,gp -800005a4: 00000073 ecall - -800005a8 : -800005a8: 0ff0000f fence -800005ac: 00100193 li gp,1 -800005b0: 05d00893 li a7,93 -800005b4: 00000513 li a0,0 -800005b8: 00000073 ecall -800005bc: c0001073 unimp -800005c0: 0000 unimp -800005c2: 0000 unimp - -Disassembly of section .data: - -80002000 : -80002000: deadbeef jal t4,7ffdd5ea <_start-0x22a16> - -80002004 : -80002004: deadbeef jal t4,7ffdd5ee <_start-0x22a12> - -80002008 : -80002008: deadbeef jal t4,7ffdd5f2 <_start-0x22a0e> - -8000200c : -8000200c: deadbeef jal t4,7ffdd5f6 <_start-0x22a0a> - -80002010 : -80002010: deadbeef jal t4,7ffdd5fa <_start-0x22a06> - -80002014 : -80002014: deadbeef jal t4,7ffdd5fe <_start-0x22a02> - -80002018 : -80002018: deadbeef jal t4,7ffdd602 <_start-0x229fe> - -8000201c : -8000201c: deadbeef jal t4,7ffdd606 <_start-0x229fa> - -80002020 : -80002020: deadbeef jal t4,7ffdd60a <_start-0x229f6> - -80002024 : -80002024: deadbeef jal t4,7ffdd60e <_start-0x229f2> -80002028: 0000 unimp -8000202a: 0000 unimp -8000202c: 0000 unimp -8000202e: 0000 unimp diff --git a/benchmarks/riscv_tests/rv32ui-p-sw.hex b/benchmarks/riscv_tests/rv32ui-p-sw.hex deleted file mode 100644 index 49c084f7..00000000 --- a/benchmarks/riscv_tests/rv32ui-p-sw.hex +++ /dev/null @@ -1,100 +0,0 @@ -:0200000480007A -:100000006F00C004732F2034930F8000630AFF0336 -:10001000930F90006306FF03930FB0006302FF038A -:10002000170F0080130F0FFE63040F0067000F000F -:10003000732F203463540F006F004000136E9E53E3 -:10004000171F00002320CFFD6FF09FFF732540F1A5 -:100050006310050073251030635805000F00F00F82 -:10006000130E100073000000130E00009702000032 -:10007000938282F973905230735020307350303035 -:1000800073504030970200809382C2F7638C020065 -:10009000739052109302B01A739022307323203061 -:1000A000E39E62F873500030970200009382420191 -:1000B00073901234732540F17300203097200000B4 -:1000C000938040F43701AA001301A10A23A0200065 -:1000D00083A10000B70EAA00938EAE0A130E200073 -:1000E0006390D147972000009380C0F137B100AAF8 -:1000F000130101A023A2200083A14000B7BE00AAE3 -:10010000938E0EA0130E3000639CD1439720000005 -:10011000938040EF3711A00A130101AA23A4200005 -:1001200083A18000B71EA00A938E0EAA130E400072 -:100130006398D141972000009380C0EC37A10AA0BA -:100140001301A10023A6200083A1C000B7AE0AA01E -:10015000938EAE00130E50006394D13F97200000A1 -:10016000938000EC3701AA001301A10A23AA20FE04 -:1001700083A140FFB70EAA00938EAE0A130E600053 -:100180006390D13D97200000938080E937B100AAA9 -:10019000130101A023AC20FE83A180FFB7BE00AAFB -:1001A000938E0EA0130E7000639CD139972000002F -:1001B000938000E73711A00A130101AA23AE20FEA5 -:1001C00083A1C0FFB71EA00A938E0EAA130E800053 -:1001D0006398D13797200000938080E437A10AA06C -:1001E0001301A10023A0200083A10000B7AE0AA044 -:1001F000938EAE00130E90006394D13597200000CB -:10020000938040E23751341213018167138200FE5C -:100210002320220283A10000B75E3412938E8E67E2 -:10022000130EA000639ED13197200000938080DFE1 -:1002300037312158130181099380D0FFA3A32000F7 -:1002400017220000130242DE83210200B73E21582C -:10025000938E8E09130EB0006394D12F130EC0003D -:1002600013020000B7D0BBAA9380D0CD17210000A5 -:10027000130141D92320110083210100B7DEBBAA5D -:10028000938EDECD639ED12B1302120093022000C9 -:10029000E31A52FC130ED00013020000B7C0ABDA11 -:1002A0009380D0CC172100001301C1D513000000AA -:1002B0002322110083214100B7CEABDA938EDECC2E -:1002C0006390D1291302120093022000E31852FC1C -:1002D000130EE00013020000B7C0AADD9380C0BC7B -:1002E00017210000130101D21300000013000000C9 -:1002F0002324110083218100B7CEAADD938ECEBCCA -:100300006390D1251302120093022000E31652FCE1 -:10031000130EF00013020000B7B0DACD9380C0BB1B -:1003200013000000172100001301C1CD2326110086 -:100330008321C100B7BEDACD938ECEBB6392D121AB -:100340001302120093022000E31852FC130E000166 -:1003500013020000B7B0DDCC9380B0AB13000000F7 -:1003600017210000130101CA130000002328110007 -:1003700083210101B7BEDDCC938EBEAB6392D11D4C -:100380001302120093022000E31652FC130E100118 -:1003900013020000B7E0CDBC9380B0AA13000000A8 -:1003A00013000000172100001301C1C5232A11000A -:1003B00083214101B7EECDBC938EBEAA6392D119C1 -:1003C0001302120093022000E31652FC130E2001C8 -:1003D00013020000172100001301C1C2B720110051 -:1003E000938030232320110083210100B72E1100B8 -:1003F000938E3E236396D1151302120093022000C0 -:10040000E31A52FC130E3001130200001721000002 -:10041000130141BFB7100130938030221300000058 -:100420002322110083214100B71E0130938E3E220A -:100430006398D1111302120093022000E31852FCBA -:10044000130E40011302000017210000130181BBAD -:10045000B710003393802012130000001300000037 -:100460002324110083218100B71E0033938E2E12A6 -:100470006398D10D1302120093022000E31652FC80 -:10048000130E50011302000017210000130181B761 -:1004900013000000B70030239380201123261100A1 -:1004A0008321C100B70E3023938E2E11639AD10998 -:1004B0001302120093022000E31852FC130E600195 -:1004C00013020000172100001301C1B31300000044 -:1004D000B70033229380100113000000232811007D -:1004E00083210101B70E3322938E1E01639AD10539 -:1004F0001302120093022000E31652FC130E700147 -:1005000013020000172100001301C1AF1300000007 -:1005100013000000B730231293801000232A11002B -:1005200083214101B73E2312938E1E00639AD101AD -:100530001302120093022000E31652FC631CC00158 -:100540000F00F00F63000E00131E1E00136E1E003E -:10055000730000000F00F00F130E10007300000076 -:10056000731000C000000000000000000000000048 -:10057000000000000000000000000000000000007B -:040580000000000077 -:1010000000000000000000000000000000000000E0 -:1010100000000000000000000000000000000000D0 -:1010200000000000000000000000000000000000C0 -:1010300000000000000000000000000000000000B0 -:081040000000000000000000A8 -:10200000EFBEADDEEFBEADDEEFBEADDEEFBEADDEF0 -:10201000EFBEADDEEFBEADDEEFBEADDEEFBEADDEE0 -:10202000EFBEADDEEFBEADDE000000000000000040 -:040000058000200057 -:00000001FF diff --git a/benchmarks/riscv_tests/rv32ui-p-xor.dump b/benchmarks/riscv_tests/rv32ui-p-xor.dump deleted file mode 100644 index 80e2c65c..00000000 --- a/benchmarks/riscv_tests/rv32ui-p-xor.dump +++ /dev/null @@ -1,458 +0,0 @@ - -rv32ui-p-xor: file format elf32-littleriscv - - -Disassembly of section .text.init: - -80000000 <_start>: -80000000: 04c0006f j 8000004c - -80000004 : -80000004: 34202f73 csrr t5,mcause -80000008: 00800f93 li t6,8 -8000000c: 03ff0a63 beq t5,t6,80000040 -80000010: 00900f93 li t6,9 -80000014: 03ff0663 beq t5,t6,80000040 -80000018: 00b00f93 li t6,11 -8000001c: 03ff0263 beq t5,t6,80000040 -80000020: 80000f17 auipc t5,0x80000 -80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> -80000028: 000f0463 beqz t5,80000030 -8000002c: 000f0067 jr t5 -80000030: 34202f73 csrr t5,mcause -80000034: 000f5463 bgez t5,8000003c -80000038: 0040006f j 8000003c - -8000003c : -8000003c: 5391e193 ori gp,gp,1337 - -80000040 : -80000040: 00001f17 auipc t5,0x1 -80000044: fc3f2023 sw gp,-64(t5) # 80001000 -80000048: ff9ff06f j 80000040 - -8000004c : -8000004c: f1402573 csrr a0,mhartid -80000050: 00051063 bnez a0,80000050 -80000054: 00000297 auipc t0,0x0 -80000058: 01028293 addi t0,t0,16 # 80000064 -8000005c: 30529073 csrw mtvec,t0 -80000060: 18005073 csrwi satp,0 -80000064: 00000297 auipc t0,0x0 -80000068: 02028293 addi t0,t0,32 # 80000084 -8000006c: 30529073 csrw mtvec,t0 -80000070: 800002b7 lui t0,0x80000 -80000074: fff28293 addi t0,t0,-1 # 7fffffff <_end+0xffffdfff> -80000078: 3b029073 csrw pmpaddr0,t0 -8000007c: 01f00293 li t0,31 -80000080: 3a029073 csrw pmpcfg0,t0 -80000084: 00000297 auipc t0,0x0 -80000088: 01828293 addi t0,t0,24 # 8000009c -8000008c: 30529073 csrw mtvec,t0 -80000090: 30205073 csrwi medeleg,0 -80000094: 30305073 csrwi mideleg,0 -80000098: 30405073 csrwi mie,0 -8000009c: 00000193 li gp,0 -800000a0: 00000297 auipc t0,0x0 -800000a4: f6428293 addi t0,t0,-156 # 80000004 -800000a8: 30529073 csrw mtvec,t0 -800000ac: 00100513 li a0,1 -800000b0: 01f51513 slli a0,a0,0x1f -800000b4: 00054c63 bltz a0,800000cc -800000b8: 0ff0000f fence -800000bc: 00100193 li gp,1 -800000c0: 05d00893 li a7,93 -800000c4: 00000513 li a0,0 -800000c8: 00000073 ecall -800000cc: 80000297 auipc t0,0x80000 -800000d0: f3428293 addi t0,t0,-204 # 0 <_start-0x80000000> -800000d4: 00028e63 beqz t0,800000f0 -800000d8: 10529073 csrw stvec,t0 -800000dc: 0000b2b7 lui t0,0xb -800000e0: 10928293 addi t0,t0,265 # b109 <_start-0x7fff4ef7> -800000e4: 30229073 csrw medeleg,t0 -800000e8: 30202373 csrr t1,medeleg -800000ec: f46298e3 bne t0,t1,8000003c -800000f0: 30005073 csrwi mstatus,0 -800000f4: 00000297 auipc t0,0x0 -800000f8: 01428293 addi t0,t0,20 # 80000108 -800000fc: 34129073 csrw mepc,t0 -80000100: f1402573 csrr a0,mhartid -80000104: 30200073 mret - -80000108 : -80000108: ff0100b7 lui ra,0xff010 -8000010c: f0008093 addi ra,ra,-256 # ff00ff00 <_end+0x7f00df00> -80000110: 0f0f1137 lui sp,0xf0f1 -80000114: f0f10113 addi sp,sp,-241 # f0f0f0f <_start-0x70f0f0f1> -80000118: 0020c733 xor a4,ra,sp -8000011c: f00ffeb7 lui t4,0xf00ff -80000120: 00fe8e93 addi t4,t4,15 # f00ff00f <_end+0x700fd00f> -80000124: 00200193 li gp,2 -80000128: 4bd71063 bne a4,t4,800005c8 - -8000012c : -8000012c: 0ff010b7 lui ra,0xff01 -80000130: ff008093 addi ra,ra,-16 # ff00ff0 <_start-0x700ff010> -80000134: f0f0f137 lui sp,0xf0f0f -80000138: 0f010113 addi sp,sp,240 # f0f0f0f0 <_end+0x70f0d0f0> -8000013c: 0020c733 xor a4,ra,sp -80000140: ff010eb7 lui t4,0xff010 -80000144: f00e8e93 addi t4,t4,-256 # ff00ff00 <_end+0x7f00df00> -80000148: 00300193 li gp,3 -8000014c: 47d71e63 bne a4,t4,800005c8 - -80000150 : -80000150: 00ff00b7 lui ra,0xff0 -80000154: 0ff08093 addi ra,ra,255 # ff00ff <_start-0x7f00ff01> -80000158: 0f0f1137 lui sp,0xf0f1 -8000015c: f0f10113 addi sp,sp,-241 # f0f0f0f <_start-0x70f0f0f1> -80000160: 0020c733 xor a4,ra,sp -80000164: 0ff01eb7 lui t4,0xff01 -80000168: ff0e8e93 addi t4,t4,-16 # ff00ff0 <_start-0x700ff010> -8000016c: 00400193 li gp,4 -80000170: 45d71c63 bne a4,t4,800005c8 - -80000174 : -80000174: f00ff0b7 lui ra,0xf00ff -80000178: 00f08093 addi ra,ra,15 # f00ff00f <_end+0x700fd00f> -8000017c: f0f0f137 lui sp,0xf0f0f -80000180: 0f010113 addi sp,sp,240 # f0f0f0f0 <_end+0x70f0d0f0> -80000184: 0020c733 xor a4,ra,sp -80000188: 00ff0eb7 lui t4,0xff0 -8000018c: 0ffe8e93 addi t4,t4,255 # ff00ff <_start-0x7f00ff01> -80000190: 00500193 li gp,5 -80000194: 43d71a63 bne a4,t4,800005c8 - -80000198 : -80000198: ff0100b7 lui ra,0xff010 -8000019c: f0008093 addi ra,ra,-256 # ff00ff00 <_end+0x7f00df00> -800001a0: 0f0f1137 lui sp,0xf0f1 -800001a4: f0f10113 addi sp,sp,-241 # f0f0f0f <_start-0x70f0f0f1> -800001a8: 0020c0b3 xor ra,ra,sp -800001ac: f00ffeb7 lui t4,0xf00ff -800001b0: 00fe8e93 addi t4,t4,15 # f00ff00f <_end+0x700fd00f> -800001b4: 00600193 li gp,6 -800001b8: 41d09863 bne ra,t4,800005c8 - -800001bc : -800001bc: ff0100b7 lui ra,0xff010 -800001c0: f0008093 addi ra,ra,-256 # ff00ff00 <_end+0x7f00df00> -800001c4: 0f0f1137 lui sp,0xf0f1 -800001c8: f0f10113 addi sp,sp,-241 # f0f0f0f <_start-0x70f0f0f1> -800001cc: 0020c133 xor sp,ra,sp -800001d0: f00ffeb7 lui t4,0xf00ff -800001d4: 00fe8e93 addi t4,t4,15 # f00ff00f <_end+0x700fd00f> -800001d8: 00700193 li gp,7 -800001dc: 3fd11663 bne sp,t4,800005c8 - -800001e0 : -800001e0: ff0100b7 lui ra,0xff010 -800001e4: f0008093 addi ra,ra,-256 # ff00ff00 <_end+0x7f00df00> -800001e8: 0010c0b3 xor ra,ra,ra -800001ec: 00000e93 li t4,0 -800001f0: 00800193 li gp,8 -800001f4: 3dd09a63 bne ra,t4,800005c8 - -800001f8 : -800001f8: 00000213 li tp,0 -800001fc: ff0100b7 lui ra,0xff010 -80000200: f0008093 addi ra,ra,-256 # ff00ff00 <_end+0x7f00df00> -80000204: 0f0f1137 lui sp,0xf0f1 -80000208: f0f10113 addi sp,sp,-241 # f0f0f0f <_start-0x70f0f0f1> -8000020c: 0020c733 xor a4,ra,sp -80000210: 00070313 mv t1,a4 -80000214: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000218: 00200293 li t0,2 -8000021c: fe5210e3 bne tp,t0,800001fc -80000220: f00ffeb7 lui t4,0xf00ff -80000224: 00fe8e93 addi t4,t4,15 # f00ff00f <_end+0x700fd00f> -80000228: 00900193 li gp,9 -8000022c: 39d31e63 bne t1,t4,800005c8 - -80000230 : -80000230: 00000213 li tp,0 -80000234: 0ff010b7 lui ra,0xff01 -80000238: ff008093 addi ra,ra,-16 # ff00ff0 <_start-0x700ff010> -8000023c: f0f0f137 lui sp,0xf0f0f -80000240: 0f010113 addi sp,sp,240 # f0f0f0f0 <_end+0x70f0d0f0> -80000244: 0020c733 xor a4,ra,sp -80000248: 00000013 nop -8000024c: 00070313 mv t1,a4 -80000250: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000254: 00200293 li t0,2 -80000258: fc521ee3 bne tp,t0,80000234 -8000025c: ff010eb7 lui t4,0xff010 -80000260: f00e8e93 addi t4,t4,-256 # ff00ff00 <_end+0x7f00df00> -80000264: 00a00193 li gp,10 -80000268: 37d31063 bne t1,t4,800005c8 - -8000026c : -8000026c: 00000213 li tp,0 -80000270: 00ff00b7 lui ra,0xff0 -80000274: 0ff08093 addi ra,ra,255 # ff00ff <_start-0x7f00ff01> -80000278: 0f0f1137 lui sp,0xf0f1 -8000027c: f0f10113 addi sp,sp,-241 # f0f0f0f <_start-0x70f0f0f1> -80000280: 0020c733 xor a4,ra,sp -80000284: 00000013 nop -80000288: 00000013 nop -8000028c: 00070313 mv t1,a4 -80000290: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000294: 00200293 li t0,2 -80000298: fc521ce3 bne tp,t0,80000270 -8000029c: 0ff01eb7 lui t4,0xff01 -800002a0: ff0e8e93 addi t4,t4,-16 # ff00ff0 <_start-0x700ff010> -800002a4: 00b00193 li gp,11 -800002a8: 33d31063 bne t1,t4,800005c8 - -800002ac : -800002ac: 00000213 li tp,0 -800002b0: ff0100b7 lui ra,0xff010 -800002b4: f0008093 addi ra,ra,-256 # ff00ff00 <_end+0x7f00df00> -800002b8: 0f0f1137 lui sp,0xf0f1 -800002bc: f0f10113 addi sp,sp,-241 # f0f0f0f <_start-0x70f0f0f1> -800002c0: 0020c733 xor a4,ra,sp -800002c4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -800002c8: 00200293 li t0,2 -800002cc: fe5212e3 bne tp,t0,800002b0 -800002d0: f00ffeb7 lui t4,0xf00ff -800002d4: 00fe8e93 addi t4,t4,15 # f00ff00f <_end+0x700fd00f> -800002d8: 00c00193 li gp,12 -800002dc: 2fd71663 bne a4,t4,800005c8 - -800002e0 : -800002e0: 00000213 li tp,0 -800002e4: 0ff010b7 lui ra,0xff01 -800002e8: ff008093 addi ra,ra,-16 # ff00ff0 <_start-0x700ff010> -800002ec: f0f0f137 lui sp,0xf0f0f -800002f0: 0f010113 addi sp,sp,240 # f0f0f0f0 <_end+0x70f0d0f0> -800002f4: 00000013 nop -800002f8: 0020c733 xor a4,ra,sp -800002fc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000300: 00200293 li t0,2 -80000304: fe5210e3 bne tp,t0,800002e4 -80000308: ff010eb7 lui t4,0xff010 -8000030c: f00e8e93 addi t4,t4,-256 # ff00ff00 <_end+0x7f00df00> -80000310: 00d00193 li gp,13 -80000314: 2bd71a63 bne a4,t4,800005c8 - -80000318 : -80000318: 00000213 li tp,0 -8000031c: 00ff00b7 lui ra,0xff0 -80000320: 0ff08093 addi ra,ra,255 # ff00ff <_start-0x7f00ff01> -80000324: 0f0f1137 lui sp,0xf0f1 -80000328: f0f10113 addi sp,sp,-241 # f0f0f0f <_start-0x70f0f0f1> -8000032c: 00000013 nop -80000330: 00000013 nop -80000334: 0020c733 xor a4,ra,sp -80000338: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -8000033c: 00200293 li t0,2 -80000340: fc521ee3 bne tp,t0,8000031c -80000344: 0ff01eb7 lui t4,0xff01 -80000348: ff0e8e93 addi t4,t4,-16 # ff00ff0 <_start-0x700ff010> -8000034c: 00e00193 li gp,14 -80000350: 27d71c63 bne a4,t4,800005c8 - -80000354 : -80000354: 00000213 li tp,0 -80000358: ff0100b7 lui ra,0xff010 -8000035c: f0008093 addi ra,ra,-256 # ff00ff00 <_end+0x7f00df00> -80000360: 00000013 nop -80000364: 0f0f1137 lui sp,0xf0f1 -80000368: f0f10113 addi sp,sp,-241 # f0f0f0f <_start-0x70f0f0f1> -8000036c: 0020c733 xor a4,ra,sp -80000370: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000374: 00200293 li t0,2 -80000378: fe5210e3 bne tp,t0,80000358 -8000037c: f00ffeb7 lui t4,0xf00ff -80000380: 00fe8e93 addi t4,t4,15 # f00ff00f <_end+0x700fd00f> -80000384: 00f00193 li gp,15 -80000388: 25d71063 bne a4,t4,800005c8 - -8000038c : -8000038c: 00000213 li tp,0 -80000390: 0ff010b7 lui ra,0xff01 -80000394: ff008093 addi ra,ra,-16 # ff00ff0 <_start-0x700ff010> -80000398: 00000013 nop -8000039c: f0f0f137 lui sp,0xf0f0f -800003a0: 0f010113 addi sp,sp,240 # f0f0f0f0 <_end+0x70f0d0f0> -800003a4: 00000013 nop -800003a8: 0020c733 xor a4,ra,sp -800003ac: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -800003b0: 00200293 li t0,2 -800003b4: fc521ee3 bne tp,t0,80000390 -800003b8: ff010eb7 lui t4,0xff010 -800003bc: f00e8e93 addi t4,t4,-256 # ff00ff00 <_end+0x7f00df00> -800003c0: 01000193 li gp,16 -800003c4: 21d71263 bne a4,t4,800005c8 - -800003c8 : -800003c8: 00000213 li tp,0 -800003cc: 00ff00b7 lui ra,0xff0 -800003d0: 0ff08093 addi ra,ra,255 # ff00ff <_start-0x7f00ff01> -800003d4: 00000013 nop -800003d8: 00000013 nop -800003dc: 0f0f1137 lui sp,0xf0f1 -800003e0: f0f10113 addi sp,sp,-241 # f0f0f0f <_start-0x70f0f0f1> -800003e4: 0020c733 xor a4,ra,sp -800003e8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -800003ec: 00200293 li t0,2 -800003f0: fc521ee3 bne tp,t0,800003cc -800003f4: 0ff01eb7 lui t4,0xff01 -800003f8: ff0e8e93 addi t4,t4,-16 # ff00ff0 <_start-0x700ff010> -800003fc: 01100193 li gp,17 -80000400: 1dd71463 bne a4,t4,800005c8 - -80000404 : -80000404: 00000213 li tp,0 -80000408: 0f0f1137 lui sp,0xf0f1 -8000040c: f0f10113 addi sp,sp,-241 # f0f0f0f <_start-0x70f0f0f1> -80000410: ff0100b7 lui ra,0xff010 -80000414: f0008093 addi ra,ra,-256 # ff00ff00 <_end+0x7f00df00> -80000418: 0020c733 xor a4,ra,sp -8000041c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000420: 00200293 li t0,2 -80000424: fe5212e3 bne tp,t0,80000408 -80000428: f00ffeb7 lui t4,0xf00ff -8000042c: 00fe8e93 addi t4,t4,15 # f00ff00f <_end+0x700fd00f> -80000430: 01200193 li gp,18 -80000434: 19d71a63 bne a4,t4,800005c8 - -80000438 : -80000438: 00000213 li tp,0 -8000043c: f0f0f137 lui sp,0xf0f0f -80000440: 0f010113 addi sp,sp,240 # f0f0f0f0 <_end+0x70f0d0f0> -80000444: 0ff010b7 lui ra,0xff01 -80000448: ff008093 addi ra,ra,-16 # ff00ff0 <_start-0x700ff010> -8000044c: 00000013 nop -80000450: 0020c733 xor a4,ra,sp -80000454: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000458: 00200293 li t0,2 -8000045c: fe5210e3 bne tp,t0,8000043c -80000460: ff010eb7 lui t4,0xff010 -80000464: f00e8e93 addi t4,t4,-256 # ff00ff00 <_end+0x7f00df00> -80000468: 01300193 li gp,19 -8000046c: 15d71e63 bne a4,t4,800005c8 - -80000470 : -80000470: 00000213 li tp,0 -80000474: 0f0f1137 lui sp,0xf0f1 -80000478: f0f10113 addi sp,sp,-241 # f0f0f0f <_start-0x70f0f0f1> -8000047c: 00ff00b7 lui ra,0xff0 -80000480: 0ff08093 addi ra,ra,255 # ff00ff <_start-0x7f00ff01> -80000484: 00000013 nop -80000488: 00000013 nop -8000048c: 0020c733 xor a4,ra,sp -80000490: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000494: 00200293 li t0,2 -80000498: fc521ee3 bne tp,t0,80000474 -8000049c: 0ff01eb7 lui t4,0xff01 -800004a0: ff0e8e93 addi t4,t4,-16 # ff00ff0 <_start-0x700ff010> -800004a4: 01400193 li gp,20 -800004a8: 13d71063 bne a4,t4,800005c8 - -800004ac : -800004ac: 00000213 li tp,0 -800004b0: 0f0f1137 lui sp,0xf0f1 -800004b4: f0f10113 addi sp,sp,-241 # f0f0f0f <_start-0x70f0f0f1> -800004b8: 00000013 nop -800004bc: ff0100b7 lui ra,0xff010 -800004c0: f0008093 addi ra,ra,-256 # ff00ff00 <_end+0x7f00df00> -800004c4: 0020c733 xor a4,ra,sp -800004c8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -800004cc: 00200293 li t0,2 -800004d0: fe5210e3 bne tp,t0,800004b0 -800004d4: f00ffeb7 lui t4,0xf00ff -800004d8: 00fe8e93 addi t4,t4,15 # f00ff00f <_end+0x700fd00f> -800004dc: 01500193 li gp,21 -800004e0: 0fd71463 bne a4,t4,800005c8 - -800004e4 : -800004e4: 00000213 li tp,0 -800004e8: f0f0f137 lui sp,0xf0f0f -800004ec: 0f010113 addi sp,sp,240 # f0f0f0f0 <_end+0x70f0d0f0> -800004f0: 00000013 nop -800004f4: 0ff010b7 lui ra,0xff01 -800004f8: ff008093 addi ra,ra,-16 # ff00ff0 <_start-0x700ff010> -800004fc: 00000013 nop -80000500: 0020c733 xor a4,ra,sp -80000504: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000508: 00200293 li t0,2 -8000050c: fc521ee3 bne tp,t0,800004e8 -80000510: ff010eb7 lui t4,0xff010 -80000514: f00e8e93 addi t4,t4,-256 # ff00ff00 <_end+0x7f00df00> -80000518: 01600193 li gp,22 -8000051c: 0bd71663 bne a4,t4,800005c8 - -80000520 : -80000520: 00000213 li tp,0 -80000524: 0f0f1137 lui sp,0xf0f1 -80000528: f0f10113 addi sp,sp,-241 # f0f0f0f <_start-0x70f0f0f1> -8000052c: 00000013 nop -80000530: 00000013 nop -80000534: 00ff00b7 lui ra,0xff0 -80000538: 0ff08093 addi ra,ra,255 # ff00ff <_start-0x7f00ff01> -8000053c: 0020c733 xor a4,ra,sp -80000540: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000544: 00200293 li t0,2 -80000548: fc521ee3 bne tp,t0,80000524 -8000054c: 0ff01eb7 lui t4,0xff01 -80000550: ff0e8e93 addi t4,t4,-16 # ff00ff0 <_start-0x700ff010> -80000554: 01700193 li gp,23 -80000558: 07d71863 bne a4,t4,800005c8 - -8000055c : -8000055c: ff0100b7 lui ra,0xff010 -80000560: f0008093 addi ra,ra,-256 # ff00ff00 <_end+0x7f00df00> -80000564: 00104133 xor sp,zero,ra -80000568: ff010eb7 lui t4,0xff010 -8000056c: f00e8e93 addi t4,t4,-256 # ff00ff00 <_end+0x7f00df00> -80000570: 01800193 li gp,24 -80000574: 05d11a63 bne sp,t4,800005c8 - -80000578 : -80000578: 00ff00b7 lui ra,0xff0 -8000057c: 0ff08093 addi ra,ra,255 # ff00ff <_start-0x7f00ff01> -80000580: 0000c133 xor sp,ra,zero -80000584: 00ff0eb7 lui t4,0xff0 -80000588: 0ffe8e93 addi t4,t4,255 # ff00ff <_start-0x7f00ff01> -8000058c: 01900193 li gp,25 -80000590: 03d11c63 bne sp,t4,800005c8 - -80000594 : -80000594: 000040b3 xor ra,zero,zero -80000598: 00000e93 li t4,0 -8000059c: 01a00193 li gp,26 -800005a0: 03d09463 bne ra,t4,800005c8 - -800005a4 : -800005a4: 111110b7 lui ra,0x11111 -800005a8: 11108093 addi ra,ra,273 # 11111111 <_start-0x6eeeeeef> -800005ac: 22222137 lui sp,0x22222 -800005b0: 22210113 addi sp,sp,546 # 22222222 <_start-0x5dddddde> -800005b4: 0020c033 xor zero,ra,sp -800005b8: 00000e93 li t4,0 -800005bc: 01b00193 li gp,27 -800005c0: 01d01463 bne zero,t4,800005c8 -800005c4: 02301063 bne zero,gp,800005e4 - -800005c8 : -800005c8: 0ff0000f fence -800005cc: 00018063 beqz gp,800005cc -800005d0: 00119193 slli gp,gp,0x1 -800005d4: 0011e193 ori gp,gp,1 -800005d8: 05d00893 li a7,93 -800005dc: 00018513 mv a0,gp -800005e0: 00000073 ecall - -800005e4 : -800005e4: 0ff0000f fence -800005e8: 00100193 li gp,1 -800005ec: 05d00893 li a7,93 -800005f0: 00000513 li a0,0 -800005f4: 00000073 ecall -800005f8: c0001073 unimp -800005fc: 0000 unimp -800005fe: 0000 unimp -80000600: 0000 unimp -80000602: 0000 unimp diff --git a/benchmarks/riscv_tests/rv32ui-p-xor.hex b/benchmarks/riscv_tests/rv32ui-p-xor.hex deleted file mode 100644 index 6e8cc1d8..00000000 --- a/benchmarks/riscv_tests/rv32ui-p-xor.hex +++ /dev/null @@ -1,101 +0,0 @@ -:0200000480007A -:100000006F00C004732F2034930F8000630AFF0336 -:10001000930F90006306FF03930FB0006302FF038A -:10002000170F0080130F0FFE63040F0067000F000F -:10003000732F203463540F006F004000136E9E53E3 -:10004000171F00002320CFFD6FF09FFF732540F1A5 -:100050006310050073251030635805000F00F00F82 -:10006000130E100073000000130E00009702000032 -:10007000938282F973905230735020307350303035 -:1000800073504030970200809382C2F7638C020065 -:10009000739052109302B01A739022307323203061 -:1000A000E39E62F873500030970200009382420191 -:1000B00073901234732540F173002030B70001FFB4 -:1000C000938000F037110F0F1301F1F0B3C120003E -:1000D000B7FE0FF0938EFE00130E20006390D14BFD -:1000E000B710F00F938000FF37F1F0F01301010F0C -:1000F000B3C12000B70E01FF938E0EF0130E300037 -:10010000639ED147B700FF009380F00F37110F0FA8 -:100110001301F1F0B3C12000B71EF00F938E0EFF54 -:10012000130E4000639CD145B7F00FF09380F000B0 -:1001300037F1F0F01301010FB3C12000B70EFF003B -:10014000938EFE0F130E5000639AD143B70001FF48 -:10015000938000F037110F0F1301F1F0B3C02000AE -:10016000B7FE0FF0938EFE00130E60006398D0412F -:10017000B70001FF938000F037110F0F1301F1F06A -:1001800033C12000B7FE0FF0938EFE00130E7000F7 -:100190006316D13FB70001FF938000F0B3C0100099 -:1001A000930E0000130E8000639AD03D13020000EE -:1001B000B70001FF938000F037110F0F1301F1F02A -:1001C000B3C1200013830100130212009302200028 -:1001D000E31052FEB7FE0FF0938EFE00130E900058 -:1001E000631ED33913020000B710F00F938000FF95 -:1001F00037F1F0F01301010FB3C12000130000002C -:10020000138301001302120093022000E31E52FC2C -:10021000B70E01FF938E0EF0130EA0006310D337BC -:1002200013020000B700FF009380F00F37110F0F8B -:100230001301F1F0B3C1200013000000130000000F -:10024000138301001302120093022000E31C52FCEE -:10025000B71EF00F938E0EFF130EB0006310D33352 -:1002600013020000B70001FF938000F037110F0F59 -:100270001301F1F0B3C12000130212009302200019 -:10028000E31252FEB7FE0FF0938EFE00130EC00075 -:100290006396D12F13020000B710F00F938000FF78 -:1002A00037F1F0F01301010F13000000B3C120007B -:1002B0001302120093022000E31052FEB70E01FF5A -:1002C000938E0EF0130ED000639AD12B1302000010 -:1002D000B700FF009380F00F37110F0F1301F1F0FB -:1002E0001300000013000000B3C12000130212002D -:1002F00093022000E31E52FCB71EF00F938E0EFFF8 -:10030000130EE000639CD12713020000B70001FF29 -:10031000938000F01300000037110F0F1301F1F06C -:10032000B3C120001302120093022000E31052FE1A -:10033000B7FE0FF0938EFE00130EF0006390D125F0 -:1003400013020000B710F00F938000FF13000000AD -:1003500037F1F0F01301010F13000000B3C12000CA -:100360001302120093022000E31E52FCB70E01FF9D -:10037000938E0EF0130E00016392D1211302000040 -:10038000B700FF009380F00F13000000130000007F -:1003900037110F0F1301F1F0B3C120001302120047 -:1003A00093022000E31E52FCB71EF00F938E0EFF47 -:1003B000130E10016394D11D1302000037110F0FAB -:1003C0001301F1F0B70001FF938000F0B3C12000EA -:1003D0001302120093022000E31252FEB7FE0FF048 -:1003E000938EFE00130E2001639AD11913020000B0 -:1003F00037F1F0F01301010FB710F00F938000FFF9 -:1004000013000000B3C12000130212009302200069 -:10041000E31052FEB70E01FF938E0EF0130E300163 -:10042000639ED1151302000037110F0F1301F1F075 -:10043000B700FF009380F00F1300000013000000CE -:10044000B3C120001302120093022000E31E52FCED -:10045000B71EF00F938E0EFF130E40016390D11361 -:100460001302000037110F0F1301F1F01300000009 -:10047000B70001FF938000F0B3C120001302120007 -:1004800093022000E31052FEB7FE0FF0938EFE00A1 -:10049000130E50016394D10F1302000037F1F0F0F6 -:1004A0001301010F13000000B710F00F938000FF3D -:1004B00013000000B3C120001302120093022000B9 -:1004C000E31E52FCB70E01FF938E0EF0130E600177 -:1004D0006396D10B1302000037110F0F1301F1F0D7 -:1004E0001300000013000000B700FF009380F00F1E -:1004F000B3C120001302120093022000E31E52FC3D -:10050000B71EF00F938E0EFF130E70016398D10784 -:10051000B70001FF938000F033411000B70E01FFD8 -:10052000938E0EF0130E8001631AD105B700FF0001 -:100530009380F00F33C10000B70EFF00938EFE0FC3 -:10054000130E9001631CD103B3400000930E000012 -:10055000130EA0016394D003B710111193801011F2 -:10056000372122221301212233C02000930E0000E4 -:10057000130EB0016314D001631CC0010F00F00F13 -:1005800063000E00131E1E00136E1E007300000099 -:100590000F00F00F130E100073000000731000C066 -:1005A000000000000000000000000000000000004B -:1005B000000000000000000000000000000000003B -:0405C0000000000037 -:1010000000000000000000000000000000000000E0 -:1010100000000000000000000000000000000000D0 -:1010200000000000000000000000000000000000C0 -:1010300000000000000000000000000000000000B0 -:081040000000000000000000A8 -:040000058000200057 -:00000001FF diff --git a/benchmarks/riscv_tests/rv32ui-p-xori.dump b/benchmarks/riscv_tests/rv32ui-p-xori.dump deleted file mode 100644 index 63433717..00000000 --- a/benchmarks/riscv_tests/rv32ui-p-xori.dump +++ /dev/null @@ -1,263 +0,0 @@ - -rv32ui-p-xori: file format elf32-littleriscv - - -Disassembly of section .text.init: - -80000000 <_start>: -80000000: 04c0006f j 8000004c - -80000004 : -80000004: 34202f73 csrr t5,mcause -80000008: 00800f93 li t6,8 -8000000c: 03ff0a63 beq t5,t6,80000040 -80000010: 00900f93 li t6,9 -80000014: 03ff0663 beq t5,t6,80000040 -80000018: 00b00f93 li t6,11 -8000001c: 03ff0263 beq t5,t6,80000040 -80000020: 80000f17 auipc t5,0x80000 -80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> -80000028: 000f0463 beqz t5,80000030 -8000002c: 000f0067 jr t5 -80000030: 34202f73 csrr t5,mcause -80000034: 000f5463 bgez t5,8000003c -80000038: 0040006f j 8000003c - -8000003c : -8000003c: 5391e193 ori gp,gp,1337 - -80000040 : -80000040: 00001f17 auipc t5,0x1 -80000044: fc3f2023 sw gp,-64(t5) # 80001000 -80000048: ff9ff06f j 80000040 - -8000004c : -8000004c: f1402573 csrr a0,mhartid -80000050: 00051063 bnez a0,80000050 -80000054: 00000297 auipc t0,0x0 -80000058: 01028293 addi t0,t0,16 # 80000064 -8000005c: 30529073 csrw mtvec,t0 -80000060: 18005073 csrwi satp,0 -80000064: 00000297 auipc t0,0x0 -80000068: 02028293 addi t0,t0,32 # 80000084 -8000006c: 30529073 csrw mtvec,t0 -80000070: 800002b7 lui t0,0x80000 -80000074: fff28293 addi t0,t0,-1 # 7fffffff <_end+0xffffdfff> -80000078: 3b029073 csrw pmpaddr0,t0 -8000007c: 01f00293 li t0,31 -80000080: 3a029073 csrw pmpcfg0,t0 -80000084: 00000297 auipc t0,0x0 -80000088: 01828293 addi t0,t0,24 # 8000009c -8000008c: 30529073 csrw mtvec,t0 -80000090: 30205073 csrwi medeleg,0 -80000094: 30305073 csrwi mideleg,0 -80000098: 30405073 csrwi mie,0 -8000009c: 00000193 li gp,0 -800000a0: 00000297 auipc t0,0x0 -800000a4: f6428293 addi t0,t0,-156 # 80000004 -800000a8: 30529073 csrw mtvec,t0 -800000ac: 00100513 li a0,1 -800000b0: 01f51513 slli a0,a0,0x1f -800000b4: 00054c63 bltz a0,800000cc -800000b8: 0ff0000f fence -800000bc: 00100193 li gp,1 -800000c0: 05d00893 li a7,93 -800000c4: 00000513 li a0,0 -800000c8: 00000073 ecall -800000cc: 80000297 auipc t0,0x80000 -800000d0: f3428293 addi t0,t0,-204 # 0 <_start-0x80000000> -800000d4: 00028e63 beqz t0,800000f0 -800000d8: 10529073 csrw stvec,t0 -800000dc: 0000b2b7 lui t0,0xb -800000e0: 10928293 addi t0,t0,265 # b109 <_start-0x7fff4ef7> -800000e4: 30229073 csrw medeleg,t0 -800000e8: 30202373 csrr t1,medeleg -800000ec: f46298e3 bne t0,t1,8000003c -800000f0: 30005073 csrwi mstatus,0 -800000f4: 00000297 auipc t0,0x0 -800000f8: 01428293 addi t0,t0,20 # 80000108 -800000fc: 34129073 csrw mepc,t0 -80000100: f1402573 csrr a0,mhartid -80000104: 30200073 mret - -80000108 : -80000108: 00ff10b7 lui ra,0xff1 -8000010c: f0008093 addi ra,ra,-256 # ff0f00 <_start-0x7f00f100> -80000110: f0f0c713 xori a4,ra,-241 -80000114: ff00feb7 lui t4,0xff00f -80000118: 00fe8e93 addi t4,t4,15 # ff00f00f <_end+0x7f00d00f> -8000011c: 00200193 li gp,2 -80000120: 1dd71663 bne a4,t4,800002ec - -80000124 : -80000124: 0ff010b7 lui ra,0xff01 -80000128: ff008093 addi ra,ra,-16 # ff00ff0 <_start-0x700ff010> -8000012c: 0f00c713 xori a4,ra,240 -80000130: 0ff01eb7 lui t4,0xff01 -80000134: f00e8e93 addi t4,t4,-256 # ff00f00 <_start-0x700ff100> -80000138: 00300193 li gp,3 -8000013c: 1bd71863 bne a4,t4,800002ec - -80000140 : -80000140: 00ff10b7 lui ra,0xff1 -80000144: 8ff08093 addi ra,ra,-1793 # ff08ff <_start-0x7f00f701> -80000148: 70f0c713 xori a4,ra,1807 -8000014c: 00ff1eb7 lui t4,0xff1 -80000150: ff0e8e93 addi t4,t4,-16 # ff0ff0 <_start-0x7f00f010> -80000154: 00400193 li gp,4 -80000158: 19d71a63 bne a4,t4,800002ec - -8000015c : -8000015c: f00ff0b7 lui ra,0xf00ff -80000160: 00f08093 addi ra,ra,15 # f00ff00f <_end+0x700fd00f> -80000164: 0f00c713 xori a4,ra,240 -80000168: f00ffeb7 lui t4,0xf00ff -8000016c: 0ffe8e93 addi t4,t4,255 # f00ff0ff <_end+0x700fd0ff> -80000170: 00500193 li gp,5 -80000174: 17d71c63 bne a4,t4,800002ec - -80000178 : -80000178: ff00f0b7 lui ra,0xff00f -8000017c: 70008093 addi ra,ra,1792 # ff00f700 <_end+0x7f00d700> -80000180: 70f0c093 xori ra,ra,1807 -80000184: ff00feb7 lui t4,0xff00f -80000188: 00fe8e93 addi t4,t4,15 # ff00f00f <_end+0x7f00d00f> -8000018c: 00600193 li gp,6 -80000190: 15d09e63 bne ra,t4,800002ec - -80000194 : -80000194: 00000213 li tp,0 -80000198: 0ff010b7 lui ra,0xff01 -8000019c: ff008093 addi ra,ra,-16 # ff00ff0 <_start-0x700ff010> -800001a0: 0f00c713 xori a4,ra,240 -800001a4: 00070313 mv t1,a4 -800001a8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -800001ac: 00200293 li t0,2 -800001b0: fe5214e3 bne tp,t0,80000198 -800001b4: 0ff01eb7 lui t4,0xff01 -800001b8: f00e8e93 addi t4,t4,-256 # ff00f00 <_start-0x700ff100> -800001bc: 00700193 li gp,7 -800001c0: 13d31663 bne t1,t4,800002ec - -800001c4 : -800001c4: 00000213 li tp,0 -800001c8: 00ff10b7 lui ra,0xff1 -800001cc: 8ff08093 addi ra,ra,-1793 # ff08ff <_start-0x7f00f701> -800001d0: 70f0c713 xori a4,ra,1807 -800001d4: 00000013 nop -800001d8: 00070313 mv t1,a4 -800001dc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -800001e0: 00200293 li t0,2 -800001e4: fe5212e3 bne tp,t0,800001c8 -800001e8: 00ff1eb7 lui t4,0xff1 -800001ec: ff0e8e93 addi t4,t4,-16 # ff0ff0 <_start-0x7f00f010> -800001f0: 00800193 li gp,8 -800001f4: 0fd31c63 bne t1,t4,800002ec - -800001f8 : -800001f8: 00000213 li tp,0 -800001fc: f00ff0b7 lui ra,0xf00ff -80000200: 00f08093 addi ra,ra,15 # f00ff00f <_end+0x700fd00f> -80000204: 0f00c713 xori a4,ra,240 -80000208: 00000013 nop -8000020c: 00000013 nop -80000210: 00070313 mv t1,a4 -80000214: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000218: 00200293 li t0,2 -8000021c: fe5210e3 bne tp,t0,800001fc -80000220: f00ffeb7 lui t4,0xf00ff -80000224: 0ffe8e93 addi t4,t4,255 # f00ff0ff <_end+0x700fd0ff> -80000228: 00900193 li gp,9 -8000022c: 0dd31063 bne t1,t4,800002ec - -80000230 : -80000230: 00000213 li tp,0 -80000234: 0ff010b7 lui ra,0xff01 -80000238: ff008093 addi ra,ra,-16 # ff00ff0 <_start-0x700ff010> -8000023c: 0f00c713 xori a4,ra,240 -80000240: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000244: 00200293 li t0,2 -80000248: fe5216e3 bne tp,t0,80000234 -8000024c: 0ff01eb7 lui t4,0xff01 -80000250: f00e8e93 addi t4,t4,-256 # ff00f00 <_start-0x700ff100> -80000254: 00a00193 li gp,10 -80000258: 09d71a63 bne a4,t4,800002ec - -8000025c : -8000025c: 00000213 li tp,0 -80000260: 00ff10b7 lui ra,0xff1 -80000264: fff08093 addi ra,ra,-1 # ff0fff <_start-0x7f00f001> -80000268: 00000013 nop -8000026c: 00f0c713 xori a4,ra,15 -80000270: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000274: 00200293 li t0,2 -80000278: fe5214e3 bne tp,t0,80000260 -8000027c: 00ff1eb7 lui t4,0xff1 -80000280: ff0e8e93 addi t4,t4,-16 # ff0ff0 <_start-0x7f00f010> -80000284: 00b00193 li gp,11 -80000288: 07d71263 bne a4,t4,800002ec - -8000028c : -8000028c: 00000213 li tp,0 -80000290: f00ff0b7 lui ra,0xf00ff -80000294: 00f08093 addi ra,ra,15 # f00ff00f <_end+0x700fd00f> -80000298: 00000013 nop -8000029c: 00000013 nop -800002a0: 0f00c713 xori a4,ra,240 -800002a4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -800002a8: 00200293 li t0,2 -800002ac: fe5212e3 bne tp,t0,80000290 -800002b0: f00ffeb7 lui t4,0xf00ff -800002b4: 0ffe8e93 addi t4,t4,255 # f00ff0ff <_end+0x700fd0ff> -800002b8: 00c00193 li gp,12 -800002bc: 03d71863 bne a4,t4,800002ec - -800002c0 : -800002c0: 0f004093 xori ra,zero,240 -800002c4: 0f000e93 li t4,240 -800002c8: 00d00193 li gp,13 -800002cc: 03d09063 bne ra,t4,800002ec - -800002d0 : -800002d0: 00ff00b7 lui ra,0xff0 -800002d4: 0ff08093 addi ra,ra,255 # ff00ff <_start-0x7f00ff01> -800002d8: 70f0c013 xori zero,ra,1807 -800002dc: 00000e93 li t4,0 -800002e0: 00e00193 li gp,14 -800002e4: 01d01463 bne zero,t4,800002ec -800002e8: 02301063 bne zero,gp,80000308 - -800002ec : -800002ec: 0ff0000f fence -800002f0: 00018063 beqz gp,800002f0 -800002f4: 00119193 slli gp,gp,0x1 -800002f8: 0011e193 ori gp,gp,1 -800002fc: 05d00893 li a7,93 -80000300: 00018513 mv a0,gp -80000304: 00000073 ecall - -80000308 : -80000308: 0ff0000f fence -8000030c: 00100193 li gp,1 -80000310: 05d00893 li a7,93 -80000314: 00000513 li a0,0 -80000318: 00000073 ecall -8000031c: c0001073 unimp -80000320: 0000 unimp -80000322: 0000 unimp -80000324: 0000 unimp -80000326: 0000 unimp -80000328: 0000 unimp -8000032a: 0000 unimp -8000032c: 0000 unimp -8000032e: 0000 unimp -80000330: 0000 unimp -80000332: 0000 unimp -80000334: 0000 unimp -80000336: 0000 unimp -80000338: 0000 unimp -8000033a: 0000 unimp -8000033c: 0000 unimp -8000033e: 0000 unimp -80000340: 0000 unimp -80000342: 0000 unimp diff --git a/benchmarks/riscv_tests/rv32ui-p-xori.hex b/benchmarks/riscv_tests/rv32ui-p-xori.hex deleted file mode 100644 index 98a84494..00000000 --- a/benchmarks/riscv_tests/rv32ui-p-xori.hex +++ /dev/null @@ -1,53 +0,0 @@ -:0200000480007A -:100000006F00C004732F2034930F8000630AFF0336 -:10001000930F90006306FF03930FB0006302FF038A -:10002000170F0080130F0FFE63040F0067000F000F -:10003000732F203463540F006F004000136E9E53E3 -:10004000171F00002320CFFD6FF09FFF732540F1A5 -:100050006310050073251030635805000F00F00F82 -:10006000130E100073000000130E00009702000032 -:10007000938282F973905230735020307350303035 -:1000800073504030970200809382C2F7638C020065 -:10009000739052109302B01A739022307323203061 -:1000A000E39E62F873500030970200009382420191 -:1000B00073901234732540F173002030B710FF00A5 -:1000C000938000F093C1F0F0B7FE00FF938EFE0026 -:1000D000130E20006396D11DB710F00F938000FF20 -:1000E00093C1000FB71EF00F938E0EF0130E300069 -:1000F0006398D11BB710FF009380F08F93C1F0700D -:10010000B71EFF00938E0EFF130E4000639AD119A5 -:10011000B7F00FF09380F00093C1000FB7FE0FF01F -:10012000938EFE0F130E5000639CD117B7F000FFA3 -:100130009380007093C0F070B7FE00FF938EFE00B6 -:10014000130E6000639ED01513020000B710F00F6D -:10015000938000FF93C1000F13830100130212006C -:1001600093022000E31452FEB71EF00F938E0EF0A0 -:10017000130E70006316D31313020000B710FF00B4 -:100180009380F08F93C1F07013000000138301007F -:100190001302120093022000E31252FEB71EFF006A -:1001A000938E0EFF130E8000631CD30F130200000A -:1001B000B7F00FF09380F00093C1000F1300000020 -:1001C00013000000138301001302120093022000A9 -:1001D000E31052FEB7FE0FF0938EFE0F130E900049 -:1001E0006310D30D13020000B710F00F938000FFCF -:1001F00093C1000F1302120093022000E31652FE77 -:10020000B71EF00F938E0EF0130EA000639AD10963 -:1002100013020000B710FF009380F0FF13000000EE -:1002200093C1F0001302120093022000E31452FE67 -:10023000B71EFF00938E0EFF130EB0006392D1071E -:1002400013020000B7F00FF09380F00013000000DD -:100250001300000093C1000F13021200930220004C -:10026000E31252FEB7FE0FF0938EFE0F130EC00086 -:100270006398D1039340000F930E000F130ED0002C -:100280006390D003B700FF009380F00F13C0F070AD -:10029000930E0000130EE0006314D001631CC00134 -:1002A0000F00F00F63000E00131E1E00136E1E00E1 -:1002B000730000000F00F00F130E10007300000019 -:0402C000731000C0F7 -:1010000000000000000000000000000000000000E0 -:1010100000000000000000000000000000000000D0 -:1010200000000000000000000000000000000000C0 -:1010300000000000000000000000000000000000B0 -:081040000000000000000000A8 -:040000058000200057 -:00000001FF diff --git a/benchmarks/riscv_tests/rv32um-p-div.dump b/benchmarks/riscv_tests/rv32um-p-div.dump deleted file mode 100644 index 665dc1ca..00000000 --- a/benchmarks/riscv_tests/rv32um-p-div.dump +++ /dev/null @@ -1,167 +0,0 @@ - -rv32um-p-div: file format elf32-littleriscv - - -Disassembly of section .text.init: - -80000000 <_start>: -80000000: 04c0006f j 8000004c - -80000004 : -80000004: 34202f73 csrr t5,mcause -80000008: 00800f93 li t6,8 -8000000c: 03ff0a63 beq t5,t6,80000040 -80000010: 00900f93 li t6,9 -80000014: 03ff0663 beq t5,t6,80000040 -80000018: 00b00f93 li t6,11 -8000001c: 03ff0263 beq t5,t6,80000040 -80000020: 80000f17 auipc t5,0x80000 -80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> -80000028: 000f0463 beqz t5,80000030 -8000002c: 000f0067 jr t5 -80000030: 34202f73 csrr t5,mcause -80000034: 000f5463 bgez t5,8000003c -80000038: 0040006f j 8000003c - -8000003c : -8000003c: 5391e193 ori gp,gp,1337 - -80000040 : -80000040: 00001f17 auipc t5,0x1 -80000044: fc3f2023 sw gp,-64(t5) # 80001000 -80000048: ff9ff06f j 80000040 - -8000004c : -8000004c: f1402573 csrr a0,mhartid -80000050: 00051063 bnez a0,80000050 -80000054: 00000297 auipc t0,0x0 -80000058: 01028293 addi t0,t0,16 # 80000064 -8000005c: 30529073 csrw mtvec,t0 -80000060: 18005073 csrwi satp,0 -80000064: 00000297 auipc t0,0x0 -80000068: 02028293 addi t0,t0,32 # 80000084 -8000006c: 30529073 csrw mtvec,t0 -80000070: 800002b7 lui t0,0x80000 -80000074: fff28293 addi t0,t0,-1 # 7fffffff <_end+0xffffdfff> -80000078: 3b029073 csrw pmpaddr0,t0 -8000007c: 01f00293 li t0,31 -80000080: 3a029073 csrw pmpcfg0,t0 -80000084: 00000297 auipc t0,0x0 -80000088: 01828293 addi t0,t0,24 # 8000009c -8000008c: 30529073 csrw mtvec,t0 -80000090: 30205073 csrwi medeleg,0 -80000094: 30305073 csrwi mideleg,0 -80000098: 30405073 csrwi mie,0 -8000009c: 00000193 li gp,0 -800000a0: 00000297 auipc t0,0x0 -800000a4: f6428293 addi t0,t0,-156 # 80000004 -800000a8: 30529073 csrw mtvec,t0 -800000ac: 00100513 li a0,1 -800000b0: 01f51513 slli a0,a0,0x1f -800000b4: 00054863 bltz a0,800000c4 -800000b8: 0ff0000f fence -800000bc: 00100193 li gp,1 -800000c0: 00000073 ecall -800000c4: 80000297 auipc t0,0x80000 -800000c8: f3c28293 addi t0,t0,-196 # 0 <_start-0x80000000> -800000cc: 00028e63 beqz t0,800000e8 -800000d0: 10529073 csrw stvec,t0 -800000d4: 0000b2b7 lui t0,0xb -800000d8: 10928293 addi t0,t0,265 # b109 <_start-0x7fff4ef7> -800000dc: 30229073 csrw medeleg,t0 -800000e0: 30202373 csrr t1,medeleg -800000e4: f4629ce3 bne t0,t1,8000003c -800000e8: 30005073 csrwi mstatus,0 -800000ec: 00000297 auipc t0,0x0 -800000f0: 01428293 addi t0,t0,20 # 80000100 -800000f4: 34129073 csrw mepc,t0 -800000f8: f1402573 csrr a0,mhartid -800000fc: 30200073 mret - -80000100 : -80000100: 01400093 li ra,20 -80000104: 00600113 li sp,6 -80000108: 0220cf33 div t5,ra,sp -8000010c: 00300e93 li t4,3 -80000110: 00200193 li gp,2 -80000114: 0ddf1463 bne t5,t4,800001dc - -80000118 : -80000118: fec00093 li ra,-20 -8000011c: 00600113 li sp,6 -80000120: 0220cf33 div t5,ra,sp -80000124: ffd00e93 li t4,-3 -80000128: 00300193 li gp,3 -8000012c: 0bdf1863 bne t5,t4,800001dc - -80000130 : -80000130: 01400093 li ra,20 -80000134: ffa00113 li sp,-6 -80000138: 0220cf33 div t5,ra,sp -8000013c: ffd00e93 li t4,-3 -80000140: 00400193 li gp,4 -80000144: 09df1c63 bne t5,t4,800001dc - -80000148 : -80000148: fec00093 li ra,-20 -8000014c: ffa00113 li sp,-6 -80000150: 0220cf33 div t5,ra,sp -80000154: 00300e93 li t4,3 -80000158: 00500193 li gp,5 -8000015c: 09df1063 bne t5,t4,800001dc - -80000160 : -80000160: 800000b7 lui ra,0x80000 -80000164: 00100113 li sp,1 -80000168: 0220cf33 div t5,ra,sp -8000016c: 80000eb7 lui t4,0x80000 -80000170: 00600193 li gp,6 -80000174: 07df1463 bne t5,t4,800001dc - -80000178 : -80000178: 800000b7 lui ra,0x80000 -8000017c: fff00113 li sp,-1 -80000180: 0220cf33 div t5,ra,sp -80000184: 80000eb7 lui t4,0x80000 -80000188: 00700193 li gp,7 -8000018c: 05df1863 bne t5,t4,800001dc - -80000190 : -80000190: 800000b7 lui ra,0x80000 -80000194: 00000113 li sp,0 -80000198: 0220cf33 div t5,ra,sp -8000019c: fff00e93 li t4,-1 -800001a0: 00800193 li gp,8 -800001a4: 03df1c63 bne t5,t4,800001dc - -800001a8 : -800001a8: 00100093 li ra,1 -800001ac: 00000113 li sp,0 -800001b0: 0220cf33 div t5,ra,sp -800001b4: fff00e93 li t4,-1 -800001b8: 00900193 li gp,9 -800001bc: 03df1063 bne t5,t4,800001dc - -800001c0 : -800001c0: 00000093 li ra,0 -800001c4: 00000113 li sp,0 -800001c8: 0220cf33 div t5,ra,sp -800001cc: fff00e93 li t4,-1 -800001d0: 00a00193 li gp,10 -800001d4: 01df1463 bne t5,t4,800001dc -800001d8: 00301c63 bne zero,gp,800001f0 - -800001dc : -800001dc: 0ff0000f fence -800001e0: 00018063 beqz gp,800001e0 -800001e4: 00119193 slli gp,gp,0x1 -800001e8: 0011e193 ori gp,gp,1 -800001ec: 00000073 ecall - -800001f0 : -800001f0: 0ff0000f fence -800001f4: 00100193 li gp,1 -800001f8: 00000073 ecall -800001fc: c0001073 unimp -80000200: 0000 unimp -80000202: 0000 unimp diff --git a/benchmarks/riscv_tests/rv32um-p-div.hex b/benchmarks/riscv_tests/rv32um-p-div.hex deleted file mode 100644 index c320a493..00000000 --- a/benchmarks/riscv_tests/rv32um-p-div.hex +++ /dev/null @@ -1,37 +0,0 @@ -:0200000480007A -:100000006F00C004732F2034930F8000630AFF0336 -:10001000930F90006306FF03930FB0006302FF038A -:10002000170F0080130F0FFE63040F0067000F000F -:10003000732F203463540F006F004000136E9E53E3 -:10004000171F00002320CFFD6FF09FFF732540F1A5 -:100050006310050073251030635805000F00F00F82 -:10006000130E100073000000130E00009702000032 -:10007000938282F973905230735020307350303035 -:1000800073504030970200809382C2F7638C020065 -:10009000739052109302B01A739022307323203061 -:1000A000E39E62F873500030970200009382420191 -:1000B00073901234732540F1730020309300400197 -:1000C00013016000B3C12002930E3000130E200014 -:1000D0006394D10D9300C0FE13016000B3C12002F0 -:1000E000930ED0FF130E30006398D10B93004001A4 -:1000F0001301A0FFB3C12002930ED0FF130E4000E6 -:10010000639CD1099300C0FE1301A0FFB3C120027C -:10011000930E3000130E50006390D109930000003D -:1001200013011000B3C12002930E0000130E6000F3 -:100130006394D107930000001301F0FFB3C12002C4 -:10014000930E0000130E70006398D1059300000019 -:1001500013010000B3C12002930EF0FF130E8000C4 -:10016000639CD1039300100013010000B3C120026F -:10017000930EF0FF130E90006390D10393000000E4 -:1001800013010000B3C12002930EF0FF130EA00074 -:100190006394D101631CC0010F00F00F63000E00D7 -:1001A000131E1E00136E1E00730000000F00F00FE0 -:1001B000130E100073000000731000C00000000058 -:0401C000000000003B -:1010000000000000000000000000000000000000E0 -:1010100000000000000000000000000000000000D0 -:1010200000000000000000000000000000000000C0 -:1010300000000000000000000000000000000000B0 -:081040000000000000000000A8 -:040000058000200057 -:00000001FF diff --git a/benchmarks/riscv_tests/rv32um-p-divu.dump b/benchmarks/riscv_tests/rv32um-p-divu.dump deleted file mode 100644 index ef4223ef..00000000 --- a/benchmarks/riscv_tests/rv32um-p-divu.dump +++ /dev/null @@ -1,166 +0,0 @@ - -rv32um-p-divu: file format elf32-littleriscv - - -Disassembly of section .text.init: - -80000000 <_start>: -80000000: 04c0006f j 8000004c - -80000004 : -80000004: 34202f73 csrr t5,mcause -80000008: 00800f93 li t6,8 -8000000c: 03ff0a63 beq t5,t6,80000040 -80000010: 00900f93 li t6,9 -80000014: 03ff0663 beq t5,t6,80000040 -80000018: 00b00f93 li t6,11 -8000001c: 03ff0263 beq t5,t6,80000040 -80000020: 80000f17 auipc t5,0x80000 -80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> -80000028: 000f0463 beqz t5,80000030 -8000002c: 000f0067 jr t5 -80000030: 34202f73 csrr t5,mcause -80000034: 000f5463 bgez t5,8000003c -80000038: 0040006f j 8000003c - -8000003c : -8000003c: 5391e193 ori gp,gp,1337 - -80000040 : -80000040: 00001f17 auipc t5,0x1 -80000044: fc3f2023 sw gp,-64(t5) # 80001000 -80000048: ff9ff06f j 80000040 - -8000004c : -8000004c: f1402573 csrr a0,mhartid -80000050: 00051063 bnez a0,80000050 -80000054: 00000297 auipc t0,0x0 -80000058: 01028293 addi t0,t0,16 # 80000064 -8000005c: 30529073 csrw mtvec,t0 -80000060: 18005073 csrwi satp,0 -80000064: 00000297 auipc t0,0x0 -80000068: 02028293 addi t0,t0,32 # 80000084 -8000006c: 30529073 csrw mtvec,t0 -80000070: 800002b7 lui t0,0x80000 -80000074: fff28293 addi t0,t0,-1 # 7fffffff <_end+0xffffdfff> -80000078: 3b029073 csrw pmpaddr0,t0 -8000007c: 01f00293 li t0,31 -80000080: 3a029073 csrw pmpcfg0,t0 -80000084: 00000297 auipc t0,0x0 -80000088: 01828293 addi t0,t0,24 # 8000009c -8000008c: 30529073 csrw mtvec,t0 -80000090: 30205073 csrwi medeleg,0 -80000094: 30305073 csrwi mideleg,0 -80000098: 30405073 csrwi mie,0 -8000009c: 00000193 li gp,0 -800000a0: 00000297 auipc t0,0x0 -800000a4: f6428293 addi t0,t0,-156 # 80000004 -800000a8: 30529073 csrw mtvec,t0 -800000ac: 00100513 li a0,1 -800000b0: 01f51513 slli a0,a0,0x1f -800000b4: 00054863 bltz a0,800000c4 -800000b8: 0ff0000f fence -800000bc: 00100193 li gp,1 -800000c0: 00000073 ecall -800000c4: 80000297 auipc t0,0x80000 -800000c8: f3c28293 addi t0,t0,-196 # 0 <_start-0x80000000> -800000cc: 00028e63 beqz t0,800000e8 -800000d0: 10529073 csrw stvec,t0 -800000d4: 0000b2b7 lui t0,0xb -800000d8: 10928293 addi t0,t0,265 # b109 <_start-0x7fff4ef7> -800000dc: 30229073 csrw medeleg,t0 -800000e0: 30202373 csrr t1,medeleg -800000e4: f4629ce3 bne t0,t1,8000003c -800000e8: 30005073 csrwi mstatus,0 -800000ec: 00000297 auipc t0,0x0 -800000f0: 01428293 addi t0,t0,20 # 80000100 -800000f4: 34129073 csrw mepc,t0 -800000f8: f1402573 csrr a0,mhartid -800000fc: 30200073 mret - -80000100 : -80000100: 01400093 li ra,20 -80000104: 00600113 li sp,6 -80000108: 0220df33 divu t5,ra,sp -8000010c: 00300e93 li t4,3 -80000110: 00200193 li gp,2 -80000114: 0ddf1663 bne t5,t4,800001e0 - -80000118 : -80000118: fec00093 li ra,-20 -8000011c: 00600113 li sp,6 -80000120: 0220df33 divu t5,ra,sp -80000124: 2aaabeb7 lui t4,0x2aaab -80000128: aa7e8e93 addi t4,t4,-1369 # 2aaaaaa7 <_start-0x55555559> -8000012c: 00300193 li gp,3 -80000130: 0bdf1863 bne t5,t4,800001e0 - -80000134 : -80000134: 01400093 li ra,20 -80000138: ffa00113 li sp,-6 -8000013c: 0220df33 divu t5,ra,sp -80000140: 00000e93 li t4,0 -80000144: 00400193 li gp,4 -80000148: 09df1c63 bne t5,t4,800001e0 - -8000014c : -8000014c: fec00093 li ra,-20 -80000150: ffa00113 li sp,-6 -80000154: 0220df33 divu t5,ra,sp -80000158: 00000e93 li t4,0 -8000015c: 00500193 li gp,5 -80000160: 09df1063 bne t5,t4,800001e0 - -80000164 : -80000164: 800000b7 lui ra,0x80000 -80000168: 00100113 li sp,1 -8000016c: 0220df33 divu t5,ra,sp -80000170: 80000eb7 lui t4,0x80000 -80000174: 00600193 li gp,6 -80000178: 07df1463 bne t5,t4,800001e0 - -8000017c : -8000017c: 800000b7 lui ra,0x80000 -80000180: fff00113 li sp,-1 -80000184: 0220df33 divu t5,ra,sp -80000188: 00000e93 li t4,0 -8000018c: 00700193 li gp,7 -80000190: 05df1863 bne t5,t4,800001e0 - -80000194 : -80000194: 800000b7 lui ra,0x80000 -80000198: 00000113 li sp,0 -8000019c: 0220df33 divu t5,ra,sp -800001a0: fff00e93 li t4,-1 -800001a4: 00800193 li gp,8 -800001a8: 03df1c63 bne t5,t4,800001e0 - -800001ac : -800001ac: 00100093 li ra,1 -800001b0: 00000113 li sp,0 -800001b4: 0220df33 divu t5,ra,sp -800001b8: fff00e93 li t4,-1 -800001bc: 00900193 li gp,9 -800001c0: 03df1063 bne t5,t4,800001e0 - -800001c4 : -800001c4: 00000093 li ra,0 -800001c8: 00000113 li sp,0 -800001cc: 0220df33 divu t5,ra,sp -800001d0: fff00e93 li t4,-1 -800001d4: 00a00193 li gp,10 -800001d8: 01df1463 bne t5,t4,800001e0 -800001dc: 00301c63 bne zero,gp,800001f4 - -800001e0 : -800001e0: 0ff0000f fence -800001e4: 00018063 beqz gp,800001e4 -800001e8: 00119193 slli gp,gp,0x1 -800001ec: 0011e193 ori gp,gp,1 -800001f0: 00000073 ecall - -800001f4 : -800001f4: 0ff0000f fence -800001f8: 00100193 li gp,1 -800001fc: 00000073 ecall -80000200: c0001073 unimp diff --git a/benchmarks/riscv_tests/rv32um-p-divu.hex b/benchmarks/riscv_tests/rv32um-p-divu.hex deleted file mode 100644 index ba68b46c..00000000 --- a/benchmarks/riscv_tests/rv32um-p-divu.hex +++ /dev/null @@ -1,37 +0,0 @@ -:0200000480007A -:100000006F00C004732F2034930F8000630AFF0336 -:10001000930F90006306FF03930FB0006302FF038A -:10002000170F0080130F0FFE63040F0067000F000F -:10003000732F203463540F006F004000136E9E53E3 -:10004000171F00002320CFFD6FF09FFF732540F1A5 -:100050006310050073251030635805000F00F00F82 -:10006000130E100073000000130E00009702000032 -:10007000938282F973905230735020307350303035 -:1000800073504030970200809382C2F7638C020065 -:10009000739052109302B01A739022307323203061 -:1000A000E39E62F873500030970200009382420191 -:1000B00073901234732540F1730020309300400197 -:1000C00013016000B3D12002930E3000130E200004 -:1000D0006396D10D9300C0FE13016000B3D12002DE -:1000E000B7BEAA2A938E7EAA130E30006398D10B56 -:1000F000930040011301A0FFB3D12002930E000032 -:10010000130E4000639CD1099300C0FE1301A0FFB1 -:10011000B3D12002930E0000130E50006390D1095A -:10012000B700008013011000B3D12002B70E008089 -:10013000130E60006394D107B70000801301F0FF35 -:10014000B3D12002930E0000130E70006398D10506 -:10015000B700008013010000B3D12002930EF0FF1E -:10016000130E8000639CD103930010001301000064 -:10017000B3D12002930EF0FF130E90006390D103D1 -:100180009300000013010000B3D12002930EF0FF92 -:10019000130EA0006394D101631CC0010F00F00F87 -:1001A00063000E00131E1E00136E1E00730000007D -:1001B0000F00F00F130E100073000000731000C04A -:0401C000000000003B -:1010000000000000000000000000000000000000E0 -:1010100000000000000000000000000000000000D0 -:1010200000000000000000000000000000000000C0 -:1010300000000000000000000000000000000000B0 -:081040000000000000000000A8 -:040000058000200057 -:00000001FF diff --git a/benchmarks/riscv_tests/rv32um-p-mul.dump b/benchmarks/riscv_tests/rv32um-p-mul.dump deleted file mode 100644 index 7f4f4151..00000000 --- a/benchmarks/riscv_tests/rv32um-p-mul.dump +++ /dev/null @@ -1,482 +0,0 @@ - -rv32um-p-mul: file format elf32-littleriscv - - -Disassembly of section .text.init: - -80000000 <_start>: -80000000: 04c0006f j 8000004c - -80000004 : -80000004: 34202f73 csrr t5,mcause -80000008: 00800f93 li t6,8 -8000000c: 03ff0a63 beq t5,t6,80000040 -80000010: 00900f93 li t6,9 -80000014: 03ff0663 beq t5,t6,80000040 -80000018: 00b00f93 li t6,11 -8000001c: 03ff0263 beq t5,t6,80000040 -80000020: 80000f17 auipc t5,0x80000 -80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> -80000028: 000f0463 beqz t5,80000030 -8000002c: 000f0067 jr t5 -80000030: 34202f73 csrr t5,mcause -80000034: 000f5463 bgez t5,8000003c -80000038: 0040006f j 8000003c - -8000003c : -8000003c: 5391e193 ori gp,gp,1337 - -80000040 : -80000040: 00001f17 auipc t5,0x1 -80000044: fc3f2023 sw gp,-64(t5) # 80001000 -80000048: ff9ff06f j 80000040 - -8000004c : -8000004c: f1402573 csrr a0,mhartid -80000050: 00051063 bnez a0,80000050 -80000054: 00000297 auipc t0,0x0 -80000058: 01028293 addi t0,t0,16 # 80000064 -8000005c: 30529073 csrw mtvec,t0 -80000060: 18005073 csrwi satp,0 -80000064: 00000297 auipc t0,0x0 -80000068: 02028293 addi t0,t0,32 # 80000084 -8000006c: 30529073 csrw mtvec,t0 -80000070: 800002b7 lui t0,0x80000 -80000074: fff28293 addi t0,t0,-1 # 7fffffff <_end+0xffffdfff> -80000078: 3b029073 csrw pmpaddr0,t0 -8000007c: 01f00293 li t0,31 -80000080: 3a029073 csrw pmpcfg0,t0 -80000084: 00000297 auipc t0,0x0 -80000088: 01828293 addi t0,t0,24 # 8000009c -8000008c: 30529073 csrw mtvec,t0 -80000090: 30205073 csrwi medeleg,0 -80000094: 30305073 csrwi mideleg,0 -80000098: 30405073 csrwi mie,0 -8000009c: 00000193 li gp,0 -800000a0: 00000297 auipc t0,0x0 -800000a4: f6428293 addi t0,t0,-156 # 80000004 -800000a8: 30529073 csrw mtvec,t0 -800000ac: 00100513 li a0,1 -800000b0: 01f51513 slli a0,a0,0x1f -800000b4: 00054863 bltz a0,800000c4 -800000b8: 0ff0000f fence -800000bc: 00100193 li gp,1 -800000c0: 00000073 ecall -800000c4: 80000297 auipc t0,0x80000 -800000c8: f3c28293 addi t0,t0,-196 # 0 <_start-0x80000000> -800000cc: 00028e63 beqz t0,800000e8 -800000d0: 10529073 csrw stvec,t0 -800000d4: 0000b2b7 lui t0,0xb -800000d8: 10928293 addi t0,t0,265 # b109 <_start-0x7fff4ef7> -800000dc: 30229073 csrw medeleg,t0 -800000e0: 30202373 csrr t1,medeleg -800000e4: f4629ce3 bne t0,t1,8000003c -800000e8: 30005073 csrwi mstatus,0 -800000ec: 00000297 auipc t0,0x0 -800000f0: 01428293 addi t0,t0,20 # 80000100 -800000f4: 34129073 csrw mepc,t0 -800000f8: f1402573 csrr a0,mhartid -800000fc: 30200073 mret - -80000100 : -80000100: 000080b7 lui ra,0x8 -80000104: e0008093 addi ra,ra,-512 # 7e00 <_start-0x7fff8200> -80000108: b6db7137 lui sp,0xb6db7 -8000010c: db710113 addi sp,sp,-585 # b6db6db7 <_end+0x36db4db7> -80000110: 02208f33 mul t5,ra,sp -80000114: 00001eb7 lui t4,0x1 -80000118: 200e8e93 addi t4,t4,512 # 1200 <_start-0x7fffee00> -8000011c: 02000193 li gp,32 -80000120: 4bdf1463 bne t5,t4,800005c8 - -80000124 : -80000124: 000080b7 lui ra,0x8 -80000128: fc008093 addi ra,ra,-64 # 7fc0 <_start-0x7fff8040> -8000012c: b6db7137 lui sp,0xb6db7 -80000130: db710113 addi sp,sp,-585 # b6db6db7 <_end+0x36db4db7> -80000134: 02208f33 mul t5,ra,sp -80000138: 00001eb7 lui t4,0x1 -8000013c: 240e8e93 addi t4,t4,576 # 1240 <_start-0x7fffedc0> -80000140: 02100193 li gp,33 -80000144: 49df1263 bne t5,t4,800005c8 - -80000148 : -80000148: 00000093 li ra,0 -8000014c: 00000113 li sp,0 -80000150: 02208f33 mul t5,ra,sp -80000154: 00000e93 li t4,0 -80000158: 00200193 li gp,2 -8000015c: 47df1663 bne t5,t4,800005c8 - -80000160 : -80000160: 00100093 li ra,1 -80000164: 00100113 li sp,1 -80000168: 02208f33 mul t5,ra,sp -8000016c: 00100e93 li t4,1 -80000170: 00300193 li gp,3 -80000174: 45df1a63 bne t5,t4,800005c8 - -80000178 : -80000178: 00300093 li ra,3 -8000017c: 00700113 li sp,7 -80000180: 02208f33 mul t5,ra,sp -80000184: 01500e93 li t4,21 -80000188: 00400193 li gp,4 -8000018c: 43df1e63 bne t5,t4,800005c8 - -80000190 : -80000190: 00000093 li ra,0 -80000194: ffff8137 lui sp,0xffff8 -80000198: 02208f33 mul t5,ra,sp -8000019c: 00000e93 li t4,0 -800001a0: 00500193 li gp,5 -800001a4: 43df1263 bne t5,t4,800005c8 - -800001a8 : -800001a8: 800000b7 lui ra,0x80000 -800001ac: 00000113 li sp,0 -800001b0: 02208f33 mul t5,ra,sp -800001b4: 00000e93 li t4,0 -800001b8: 00600193 li gp,6 -800001bc: 41df1663 bne t5,t4,800005c8 - -800001c0 : -800001c0: 800000b7 lui ra,0x80000 -800001c4: ffff8137 lui sp,0xffff8 -800001c8: 02208f33 mul t5,ra,sp -800001cc: 00000e93 li t4,0 -800001d0: 00700193 li gp,7 -800001d4: 3fdf1a63 bne t5,t4,800005c8 - -800001d8 : -800001d8: aaaab0b7 lui ra,0xaaaab -800001dc: aab08093 addi ra,ra,-1365 # aaaaaaab <_end+0x2aaa8aab> -800001e0: 00030137 lui sp,0x30 -800001e4: e7d10113 addi sp,sp,-387 # 2fe7d <_start-0x7ffd0183> -800001e8: 02208f33 mul t5,ra,sp -800001ec: 00010eb7 lui t4,0x10 -800001f0: f7fe8e93 addi t4,t4,-129 # ff7f <_start-0x7fff0081> -800001f4: 01e00193 li gp,30 -800001f8: 3ddf1863 bne t5,t4,800005c8 - -800001fc : -800001fc: 000300b7 lui ra,0x30 -80000200: e7d08093 addi ra,ra,-387 # 2fe7d <_start-0x7ffd0183> -80000204: aaaab137 lui sp,0xaaaab -80000208: aab10113 addi sp,sp,-1365 # aaaaaaab <_end+0x2aaa8aab> -8000020c: 02208f33 mul t5,ra,sp -80000210: 00010eb7 lui t4,0x10 -80000214: f7fe8e93 addi t4,t4,-129 # ff7f <_start-0x7fff0081> -80000218: 01f00193 li gp,31 -8000021c: 3bdf1663 bne t5,t4,800005c8 - -80000220 : -80000220: ff0000b7 lui ra,0xff000 -80000224: ff000137 lui sp,0xff000 -80000228: 02208f33 mul t5,ra,sp -8000022c: 00000e93 li t4,0 -80000230: 02200193 li gp,34 -80000234: 39df1a63 bne t5,t4,800005c8 - -80000238 : -80000238: fff00093 li ra,-1 -8000023c: fff00113 li sp,-1 -80000240: 02208f33 mul t5,ra,sp -80000244: 00100e93 li t4,1 -80000248: 02300193 li gp,35 -8000024c: 37df1e63 bne t5,t4,800005c8 - -80000250 : -80000250: fff00093 li ra,-1 -80000254: 00100113 li sp,1 -80000258: 02208f33 mul t5,ra,sp -8000025c: fff00e93 li t4,-1 -80000260: 02400193 li gp,36 -80000264: 37df1263 bne t5,t4,800005c8 - -80000268 : -80000268: 00100093 li ra,1 -8000026c: fff00113 li sp,-1 -80000270: 02208f33 mul t5,ra,sp -80000274: fff00e93 li t4,-1 -80000278: 02500193 li gp,37 -8000027c: 35df1663 bne t5,t4,800005c8 - -80000280 : -80000280: 00d00093 li ra,13 -80000284: 00b00113 li sp,11 -80000288: 022080b3 mul ra,ra,sp -8000028c: 08f00e93 li t4,143 -80000290: 00800193 li gp,8 -80000294: 33d09a63 bne ra,t4,800005c8 - -80000298 : -80000298: 00e00093 li ra,14 -8000029c: 00b00113 li sp,11 -800002a0: 02208133 mul sp,ra,sp -800002a4: 09a00e93 li t4,154 -800002a8: 00900193 li gp,9 -800002ac: 31d11e63 bne sp,t4,800005c8 - -800002b0 : -800002b0: 00d00093 li ra,13 -800002b4: 021080b3 mul ra,ra,ra -800002b8: 0a900e93 li t4,169 -800002bc: 00a00193 li gp,10 -800002c0: 31d09463 bne ra,t4,800005c8 - -800002c4 : -800002c4: 00000213 li tp,0 -800002c8: 00d00093 li ra,13 -800002cc: 00b00113 li sp,11 -800002d0: 02208f33 mul t5,ra,sp -800002d4: 000f0313 mv t1,t5 -800002d8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -800002dc: 00200293 li t0,2 -800002e0: fe5214e3 bne tp,t0,800002c8 -800002e4: 08f00e93 li t4,143 -800002e8: 00b00193 li gp,11 -800002ec: 2dd31e63 bne t1,t4,800005c8 - -800002f0 : -800002f0: 00000213 li tp,0 -800002f4: 00e00093 li ra,14 -800002f8: 00b00113 li sp,11 -800002fc: 02208f33 mul t5,ra,sp -80000300: 00000013 nop -80000304: 000f0313 mv t1,t5 -80000308: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -8000030c: 00200293 li t0,2 -80000310: fe5212e3 bne tp,t0,800002f4 -80000314: 09a00e93 li t4,154 -80000318: 00c00193 li gp,12 -8000031c: 2bd31663 bne t1,t4,800005c8 - -80000320 : -80000320: 00000213 li tp,0 -80000324: 00f00093 li ra,15 -80000328: 00b00113 li sp,11 -8000032c: 02208f33 mul t5,ra,sp -80000330: 00000013 nop -80000334: 00000013 nop -80000338: 000f0313 mv t1,t5 -8000033c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000340: 00200293 li t0,2 -80000344: fe5210e3 bne tp,t0,80000324 -80000348: 0a500e93 li t4,165 -8000034c: 00d00193 li gp,13 -80000350: 27d31c63 bne t1,t4,800005c8 - -80000354 : -80000354: 00000213 li tp,0 -80000358: 00d00093 li ra,13 -8000035c: 00b00113 li sp,11 -80000360: 02208f33 mul t5,ra,sp -80000364: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000368: 00200293 li t0,2 -8000036c: fe5216e3 bne tp,t0,80000358 -80000370: 08f00e93 li t4,143 -80000374: 00e00193 li gp,14 -80000378: 25df1863 bne t5,t4,800005c8 - -8000037c : -8000037c: 00000213 li tp,0 -80000380: 00e00093 li ra,14 -80000384: 00b00113 li sp,11 -80000388: 00000013 nop -8000038c: 02208f33 mul t5,ra,sp -80000390: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000394: 00200293 li t0,2 -80000398: fe5214e3 bne tp,t0,80000380 -8000039c: 09a00e93 li t4,154 -800003a0: 00f00193 li gp,15 -800003a4: 23df1263 bne t5,t4,800005c8 - -800003a8 : -800003a8: 00000213 li tp,0 -800003ac: 00f00093 li ra,15 -800003b0: 00b00113 li sp,11 -800003b4: 00000013 nop -800003b8: 00000013 nop -800003bc: 02208f33 mul t5,ra,sp -800003c0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -800003c4: 00200293 li t0,2 -800003c8: fe5212e3 bne tp,t0,800003ac -800003cc: 0a500e93 li t4,165 -800003d0: 01000193 li gp,16 -800003d4: 1fdf1a63 bne t5,t4,800005c8 - -800003d8 : -800003d8: 00000213 li tp,0 -800003dc: 00d00093 li ra,13 -800003e0: 00000013 nop -800003e4: 00b00113 li sp,11 -800003e8: 02208f33 mul t5,ra,sp -800003ec: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -800003f0: 00200293 li t0,2 -800003f4: fe5214e3 bne tp,t0,800003dc -800003f8: 08f00e93 li t4,143 -800003fc: 01100193 li gp,17 -80000400: 1ddf1463 bne t5,t4,800005c8 - -80000404 : -80000404: 00000213 li tp,0 -80000408: 00e00093 li ra,14 -8000040c: 00000013 nop -80000410: 00b00113 li sp,11 -80000414: 00000013 nop -80000418: 02208f33 mul t5,ra,sp -8000041c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000420: 00200293 li t0,2 -80000424: fe5212e3 bne tp,t0,80000408 -80000428: 09a00e93 li t4,154 -8000042c: 01200193 li gp,18 -80000430: 19df1c63 bne t5,t4,800005c8 - -80000434 : -80000434: 00000213 li tp,0 -80000438: 00f00093 li ra,15 -8000043c: 00000013 nop -80000440: 00000013 nop -80000444: 00b00113 li sp,11 -80000448: 02208f33 mul t5,ra,sp -8000044c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000450: 00200293 li t0,2 -80000454: fe5212e3 bne tp,t0,80000438 -80000458: 0a500e93 li t4,165 -8000045c: 01300193 li gp,19 -80000460: 17df1463 bne t5,t4,800005c8 - -80000464 : -80000464: 00000213 li tp,0 -80000468: 00b00113 li sp,11 -8000046c: 00d00093 li ra,13 -80000470: 02208f33 mul t5,ra,sp -80000474: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000478: 00200293 li t0,2 -8000047c: fe5216e3 bne tp,t0,80000468 -80000480: 08f00e93 li t4,143 -80000484: 01400193 li gp,20 -80000488: 15df1063 bne t5,t4,800005c8 - -8000048c : -8000048c: 00000213 li tp,0 -80000490: 00b00113 li sp,11 -80000494: 00e00093 li ra,14 -80000498: 00000013 nop -8000049c: 02208f33 mul t5,ra,sp -800004a0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -800004a4: 00200293 li t0,2 -800004a8: fe5214e3 bne tp,t0,80000490 -800004ac: 09a00e93 li t4,154 -800004b0: 01500193 li gp,21 -800004b4: 11df1a63 bne t5,t4,800005c8 - -800004b8 : -800004b8: 00000213 li tp,0 -800004bc: 00b00113 li sp,11 -800004c0: 00f00093 li ra,15 -800004c4: 00000013 nop -800004c8: 00000013 nop -800004cc: 02208f33 mul t5,ra,sp -800004d0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -800004d4: 00200293 li t0,2 -800004d8: fe5212e3 bne tp,t0,800004bc -800004dc: 0a500e93 li t4,165 -800004e0: 01600193 li gp,22 -800004e4: 0fdf1263 bne t5,t4,800005c8 - -800004e8 : -800004e8: 00000213 li tp,0 -800004ec: 00b00113 li sp,11 -800004f0: 00000013 nop -800004f4: 00d00093 li ra,13 -800004f8: 02208f33 mul t5,ra,sp -800004fc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000500: 00200293 li t0,2 -80000504: fe5214e3 bne tp,t0,800004ec -80000508: 08f00e93 li t4,143 -8000050c: 01700193 li gp,23 -80000510: 0bdf1c63 bne t5,t4,800005c8 - -80000514 : -80000514: 00000213 li tp,0 -80000518: 00b00113 li sp,11 -8000051c: 00000013 nop -80000520: 00e00093 li ra,14 -80000524: 00000013 nop -80000528: 02208f33 mul t5,ra,sp -8000052c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000530: 00200293 li t0,2 -80000534: fe5212e3 bne tp,t0,80000518 -80000538: 09a00e93 li t4,154 -8000053c: 01800193 li gp,24 -80000540: 09df1463 bne t5,t4,800005c8 - -80000544 : -80000544: 00000213 li tp,0 -80000548: 00b00113 li sp,11 -8000054c: 00000013 nop -80000550: 00000013 nop -80000554: 00f00093 li ra,15 -80000558: 02208f33 mul t5,ra,sp -8000055c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000560: 00200293 li t0,2 -80000564: fe5212e3 bne tp,t0,80000548 -80000568: 0a500e93 li t4,165 -8000056c: 01900193 li gp,25 -80000570: 05df1c63 bne t5,t4,800005c8 - -80000574 : -80000574: 01f00093 li ra,31 -80000578: 02100133 mul sp,zero,ra -8000057c: 00000e93 li t4,0 -80000580: 01a00193 li gp,26 -80000584: 05d11263 bne sp,t4,800005c8 - -80000588 : -80000588: 02000093 li ra,32 -8000058c: 02008133 mul sp,ra,zero -80000590: 00000e93 li t4,0 -80000594: 01b00193 li gp,27 -80000598: 03d11863 bne sp,t4,800005c8 - -8000059c : -8000059c: 020000b3 mul ra,zero,zero -800005a0: 00000e93 li t4,0 -800005a4: 01c00193 li gp,28 -800005a8: 03d09063 bne ra,t4,800005c8 - -800005ac : -800005ac: 02100093 li ra,33 -800005b0: 02200113 li sp,34 -800005b4: 02208033 mul zero,ra,sp -800005b8: 00000e93 li t4,0 -800005bc: 01d00193 li gp,29 -800005c0: 01d01463 bne zero,t4,800005c8 -800005c4: 00301c63 bne zero,gp,800005dc - -800005c8 : -800005c8: 0ff0000f fence -800005cc: 00018063 beqz gp,800005cc -800005d0: 00119193 slli gp,gp,0x1 -800005d4: 0011e193 ori gp,gp,1 -800005d8: 00000073 ecall - -800005dc : -800005dc: 0ff0000f fence -800005e0: 00100193 li gp,1 -800005e4: 00000073 ecall -800005e8: c0001073 unimp -800005ec: 0000 unimp -800005ee: 0000 unimp -800005f0: 0000 unimp -800005f2: 0000 unimp -800005f4: 0000 unimp -800005f6: 0000 unimp -800005f8: 0000 unimp -800005fa: 0000 unimp -800005fc: 0000 unimp -800005fe: 0000 unimp -80000600: 0000 unimp -80000602: 0000 unimp diff --git a/benchmarks/riscv_tests/rv32um-p-mul.hex b/benchmarks/riscv_tests/rv32um-p-mul.hex deleted file mode 100644 index c2e28a22..00000000 --- a/benchmarks/riscv_tests/rv32um-p-mul.hex +++ /dev/null @@ -1,101 +0,0 @@ -:0200000480007A -:100000006F00C004732F2034930F8000630AFF0336 -:10001000930F90006306FF03930FB0006302FF038A -:10002000170F0080130F0FFE63040F0067000F000F -:10003000732F203463540F006F004000136E9E53E3 -:10004000171F00002320CFFD6FF09FFF732540F1A5 -:100050006310050073251030635805000F00F00F82 -:10006000130E100073000000130E00009702000032 -:10007000938282F973905230735020307350303035 -:1000800073504030970200809382C2F7638C020065 -:10009000739052109302B01A739022307323203061 -:1000A000E39E62F873500030970200009382420191 -:1000B00073901234732540F173002030B780000034 -:1000C000938000E03771DBB6130171DBB38120024E -:1000D000B71E0000938E0E20130E00026394D14BC6 -:1000E000B7800000938000FC3771DBB6130171DB31 -:1000F000B3812002B71E0000938E0E24130E10024F -:100100006392D1499300000013010000B3812002E3 -:10011000930E0000130E20006396D1479300100049 -:1001200013011000B3812002930E1000130E300053 -:10013000639AD1459300300013017000B38120020F -:10014000930E5001130E4000639ED14393000000B4 -:100150003781FFFFB3812002930E0000130E500081 -:100160006392D143B700008013010000B3812002E5 -:10017000930E0000130E60006396D141B70000801B -:100180003781FFFFB3812002930E0000130E700031 -:10019000639AD13FB7B0AAAA9380B0AA37010300EF -:1001A0001301D1E7B3812002B70E0100938EFEF751 -:1001B000130EE0016398D13DB70003009380D0E7B0 -:1001C00037B1AAAA1301B1AAB3812002B70E010068 -:1001D000938EFEF7130EF0016396D13BB70000FF3C -:1001E000370100FFB3812002930E0000130E20029E -:1001F000639AD1399300F0FF1301F0FFB38120021D -:10020000930E1000130E3002639ED1379300F0FF5F -:1002100013011000B3812002930EF0FF130E400271 -:100220006392D137930010001301F0FFB3812002D5 -:10023000930EF0FF130E50026396D1359300D00059 -:100240001301B000B3802002930EF008130E80005B -:10025000639AD0339300E0001301B0003381200291 -:10026000930EA009130E9000631ED1319300D000AD -:10027000B3801002930E900A130EA0006394D03145 -:10028000130200009300D0001301B000B3812002DC -:10029000138301001302120093022000E31452FEA4 -:1002A000930EF008130EB000631ED32D130200004E -:1002B0009300E0001301B000B3812002130000009E -:1002C000138301001302120093022000E31252FE76 -:1002D000930EA009130EC0006316D32B1302000067 -:1002E0009300F0001301B000B3812002130000005E -:1002F0001300000013830100130212009302200078 -:10030000E31052FE930E500A130ED000631CD32745 -:10031000130200009300D0001301B000B38120024B -:100320001302120093022000E31652FE930EF0080F -:10033000130EE0006398D125130200009300E00043 -:100340001301B00013000000B38120021302120059 -:1003500093022000E31452FE930EA009130EF00046 -:100360006392D123130200009300F0001301B00048 -:100370001300000013000000B381200213021200DA -:1003800093022000E31252FE930E500A130E000156 -:10039000639AD11F130200009300D00013000000E5 -:1003A0001301B000B3812002130212009302200057 -:1003B000E31452FE930EF008130E10016394D11D46 -:1003C000130200009300E000130000001301B000CE -:1003D00013000000B38120021302120093022000D8 -:1003E000E31252FE930EA009130E2001639CD11953 -:1003F000130200009300F00013000000130000003F -:100400001301B000B38120021302120093022000F6 -:10041000E31252FE930E500A130E30016394D1176B -:10042000130200001301B0009300D000B38120023A -:100430001302120093022000E31652FE930EF008FE -:10044000130E40016390D115130200001301B00098 -:100450009300E00013000000B38120021302120099 -:1004600093022000E31452FE930EA009130E5001D4 -:10047000639AD111130200001301B0009300F00041 -:100480001300000013000000B381200213021200C9 -:1004900093022000E31252FE930E500A130E6001E5 -:1004A0006392D10F130200001301B000130000008B -:1004B0009300D000B38120021302120093022000A7 -:1004C000E31452FE930EF008130E7001639CD10BDF -:1004D000130200001301B000130000009300E000BD -:1004E00013000000B38120021302120093022000C7 -:1004F000E31252FE930EA009130E80016394D109FA -:10050000130200001301B0001300000013000000EC -:100510009300F000B3812002130212009302200026 -:10052000E31252FE930E500A130E9001639CD10504 -:100530009300F00133011002930E0000130EA0018E -:100540006312D1059300000233810002930E000074 -:10055000130EB0016318D103B3000002930E000024 -:10056000130EC0016390D003930010021301200208 -:1005700033802002930E0000130ED0016314D001CB -:10058000631CC0010F00F00F63000E00131E1E005D -:10059000136E1E00730000000F00F00F130E10000A -:1005A00073000000731000C0000000000000000095 -:1005B000000000000000000000000000000000003B -:0405C0000000000037 -:1010000000000000000000000000000000000000E0 -:1010100000000000000000000000000000000000D0 -:1010200000000000000000000000000000000000C0 -:1010300000000000000000000000000000000000B0 -:081040000000000000000000A8 -:040000058000200057 -:00000001FF diff --git a/benchmarks/riscv_tests/rv32um-p-mulh.dump b/benchmarks/riscv_tests/rv32um-p-mulh.dump deleted file mode 100644 index 2e5eed71..00000000 --- a/benchmarks/riscv_tests/rv32um-p-mulh.dump +++ /dev/null @@ -1,478 +0,0 @@ - -rv32um-p-mulh: file format elf32-littleriscv - - -Disassembly of section .text.init: - -80000000 <_start>: -80000000: 04c0006f j 8000004c - -80000004 : -80000004: 34202f73 csrr t5,mcause -80000008: 00800f93 li t6,8 -8000000c: 03ff0a63 beq t5,t6,80000040 -80000010: 00900f93 li t6,9 -80000014: 03ff0663 beq t5,t6,80000040 -80000018: 00b00f93 li t6,11 -8000001c: 03ff0263 beq t5,t6,80000040 -80000020: 80000f17 auipc t5,0x80000 -80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> -80000028: 000f0463 beqz t5,80000030 -8000002c: 000f0067 jr t5 -80000030: 34202f73 csrr t5,mcause -80000034: 000f5463 bgez t5,8000003c -80000038: 0040006f j 8000003c - -8000003c : -8000003c: 5391e193 ori gp,gp,1337 - -80000040 : -80000040: 00001f17 auipc t5,0x1 -80000044: fc3f2023 sw gp,-64(t5) # 80001000 -80000048: ff9ff06f j 80000040 - -8000004c : -8000004c: f1402573 csrr a0,mhartid -80000050: 00051063 bnez a0,80000050 -80000054: 00000297 auipc t0,0x0 -80000058: 01028293 addi t0,t0,16 # 80000064 -8000005c: 30529073 csrw mtvec,t0 -80000060: 18005073 csrwi satp,0 -80000064: 00000297 auipc t0,0x0 -80000068: 02028293 addi t0,t0,32 # 80000084 -8000006c: 30529073 csrw mtvec,t0 -80000070: 800002b7 lui t0,0x80000 -80000074: fff28293 addi t0,t0,-1 # 7fffffff <_end+0xffffdfff> -80000078: 3b029073 csrw pmpaddr0,t0 -8000007c: 01f00293 li t0,31 -80000080: 3a029073 csrw pmpcfg0,t0 -80000084: 00000297 auipc t0,0x0 -80000088: 01828293 addi t0,t0,24 # 8000009c -8000008c: 30529073 csrw mtvec,t0 -80000090: 30205073 csrwi medeleg,0 -80000094: 30305073 csrwi mideleg,0 -80000098: 30405073 csrwi mie,0 -8000009c: 00000193 li gp,0 -800000a0: 00000297 auipc t0,0x0 -800000a4: f6428293 addi t0,t0,-156 # 80000004 -800000a8: 30529073 csrw mtvec,t0 -800000ac: 00100513 li a0,1 -800000b0: 01f51513 slli a0,a0,0x1f -800000b4: 00054863 bltz a0,800000c4 -800000b8: 0ff0000f fence -800000bc: 00100193 li gp,1 -800000c0: 00000073 ecall -800000c4: 80000297 auipc t0,0x80000 -800000c8: f3c28293 addi t0,t0,-196 # 0 <_start-0x80000000> -800000cc: 00028e63 beqz t0,800000e8 -800000d0: 10529073 csrw stvec,t0 -800000d4: 0000b2b7 lui t0,0xb -800000d8: 10928293 addi t0,t0,265 # b109 <_start-0x7fff4ef7> -800000dc: 30229073 csrw medeleg,t0 -800000e0: 30202373 csrr t1,medeleg -800000e4: f4629ce3 bne t0,t1,8000003c -800000e8: 30005073 csrwi mstatus,0 -800000ec: 00000297 auipc t0,0x0 -800000f0: 01428293 addi t0,t0,20 # 80000100 -800000f4: 34129073 csrw mepc,t0 -800000f8: f1402573 csrr a0,mhartid -800000fc: 30200073 mret - -80000100 : -80000100: 00000093 li ra,0 -80000104: 00000113 li sp,0 -80000108: 02209f33 mulh t5,ra,sp -8000010c: 00000e93 li t4,0 -80000110: 00200193 li gp,2 -80000114: 4bdf1a63 bne t5,t4,800005c8 - -80000118 : -80000118: 00100093 li ra,1 -8000011c: 00100113 li sp,1 -80000120: 02209f33 mulh t5,ra,sp -80000124: 00000e93 li t4,0 -80000128: 00300193 li gp,3 -8000012c: 49df1e63 bne t5,t4,800005c8 - -80000130 : -80000130: 00300093 li ra,3 -80000134: 00700113 li sp,7 -80000138: 02209f33 mulh t5,ra,sp -8000013c: 00000e93 li t4,0 -80000140: 00400193 li gp,4 -80000144: 49df1263 bne t5,t4,800005c8 - -80000148 : -80000148: 00000093 li ra,0 -8000014c: ffff8137 lui sp,0xffff8 -80000150: 02209f33 mulh t5,ra,sp -80000154: 00000e93 li t4,0 -80000158: 00500193 li gp,5 -8000015c: 47df1663 bne t5,t4,800005c8 - -80000160 : -80000160: 800000b7 lui ra,0x80000 -80000164: 00000113 li sp,0 -80000168: 02209f33 mulh t5,ra,sp -8000016c: 00000e93 li t4,0 -80000170: 00600193 li gp,6 -80000174: 45df1a63 bne t5,t4,800005c8 - -80000178 : -80000178: 800000b7 lui ra,0x80000 -8000017c: 00000113 li sp,0 -80000180: 02209f33 mulh t5,ra,sp -80000184: 00000e93 li t4,0 -80000188: 00700193 li gp,7 -8000018c: 43df1e63 bne t5,t4,800005c8 - -80000190 : -80000190: aaaab0b7 lui ra,0xaaaab -80000194: aab08093 addi ra,ra,-1365 # aaaaaaab <_end+0x2aaa8aab> -80000198: 00030137 lui sp,0x30 -8000019c: e7d10113 addi sp,sp,-387 # 2fe7d <_start-0x7ffd0183> -800001a0: 02209f33 mulh t5,ra,sp -800001a4: ffff0eb7 lui t4,0xffff0 -800001a8: 081e8e93 addi t4,t4,129 # ffff0081 <_end+0x7ffee081> -800001ac: 01e00193 li gp,30 -800001b0: 41df1c63 bne t5,t4,800005c8 - -800001b4 : -800001b4: 000300b7 lui ra,0x30 -800001b8: e7d08093 addi ra,ra,-387 # 2fe7d <_start-0x7ffd0183> -800001bc: aaaab137 lui sp,0xaaaab -800001c0: aab10113 addi sp,sp,-1365 # aaaaaaab <_end+0x2aaa8aab> -800001c4: 02209f33 mulh t5,ra,sp -800001c8: ffff0eb7 lui t4,0xffff0 -800001cc: 081e8e93 addi t4,t4,129 # ffff0081 <_end+0x7ffee081> -800001d0: 01f00193 li gp,31 -800001d4: 3fdf1a63 bne t5,t4,800005c8 - -800001d8 : -800001d8: ff0000b7 lui ra,0xff000 -800001dc: ff000137 lui sp,0xff000 -800001e0: 02209f33 mulh t5,ra,sp -800001e4: 00010eb7 lui t4,0x10 -800001e8: 02000193 li gp,32 -800001ec: 3ddf1e63 bne t5,t4,800005c8 - -800001f0 : -800001f0: fff00093 li ra,-1 -800001f4: fff00113 li sp,-1 -800001f8: 02209f33 mulh t5,ra,sp -800001fc: 00000e93 li t4,0 -80000200: 02100193 li gp,33 -80000204: 3ddf1263 bne t5,t4,800005c8 - -80000208 : -80000208: fff00093 li ra,-1 -8000020c: 00100113 li sp,1 -80000210: 02209f33 mulh t5,ra,sp -80000214: fff00e93 li t4,-1 -80000218: 02200193 li gp,34 -8000021c: 3bdf1663 bne t5,t4,800005c8 - -80000220 : -80000220: 00100093 li ra,1 -80000224: fff00113 li sp,-1 -80000228: 02209f33 mulh t5,ra,sp -8000022c: fff00e93 li t4,-1 -80000230: 02300193 li gp,35 -80000234: 39df1a63 bne t5,t4,800005c8 - -80000238 : -80000238: 00d000b7 lui ra,0xd00 -8000023c: 00b00137 lui sp,0xb00 -80000240: 022090b3 mulh ra,ra,sp -80000244: 00009eb7 lui t4,0x9 -80000248: f00e8e93 addi t4,t4,-256 # 8f00 <_start-0x7fff7100> -8000024c: 00800193 li gp,8 -80000250: 37d09c63 bne ra,t4,800005c8 - -80000254 : -80000254: 00e000b7 lui ra,0xe00 -80000258: 00b00137 lui sp,0xb00 -8000025c: 02209133 mulh sp,ra,sp -80000260: 0000aeb7 lui t4,0xa -80000264: a00e8e93 addi t4,t4,-1536 # 9a00 <_start-0x7fff6600> -80000268: 00900193 li gp,9 -8000026c: 35d11e63 bne sp,t4,800005c8 - -80000270 : -80000270: 00d000b7 lui ra,0xd00 -80000274: 021090b3 mulh ra,ra,ra -80000278: 0000beb7 lui t4,0xb -8000027c: 900e8e93 addi t4,t4,-1792 # a900 <_start-0x7fff5700> -80000280: 00a00193 li gp,10 -80000284: 35d09263 bne ra,t4,800005c8 - -80000288 : -80000288: 00000213 li tp,0 -8000028c: 00d000b7 lui ra,0xd00 -80000290: 00b00137 lui sp,0xb00 -80000294: 02209f33 mulh t5,ra,sp -80000298: 000f0313 mv t1,t5 -8000029c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -800002a0: 00200293 li t0,2 -800002a4: fe5214e3 bne tp,t0,8000028c -800002a8: 00009eb7 lui t4,0x9 -800002ac: f00e8e93 addi t4,t4,-256 # 8f00 <_start-0x7fff7100> -800002b0: 00b00193 li gp,11 -800002b4: 31d31a63 bne t1,t4,800005c8 - -800002b8 : -800002b8: 00000213 li tp,0 -800002bc: 00e000b7 lui ra,0xe00 -800002c0: 00b00137 lui sp,0xb00 -800002c4: 02209f33 mulh t5,ra,sp -800002c8: 00000013 nop -800002cc: 000f0313 mv t1,t5 -800002d0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -800002d4: 00200293 li t0,2 -800002d8: fe5212e3 bne tp,t0,800002bc -800002dc: 0000aeb7 lui t4,0xa -800002e0: a00e8e93 addi t4,t4,-1536 # 9a00 <_start-0x7fff6600> -800002e4: 00c00193 li gp,12 -800002e8: 2fd31063 bne t1,t4,800005c8 - -800002ec : -800002ec: 00000213 li tp,0 -800002f0: 00f000b7 lui ra,0xf00 -800002f4: 00b00137 lui sp,0xb00 -800002f8: 02209f33 mulh t5,ra,sp -800002fc: 00000013 nop -80000300: 00000013 nop -80000304: 000f0313 mv t1,t5 -80000308: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -8000030c: 00200293 li t0,2 -80000310: fe5210e3 bne tp,t0,800002f0 -80000314: 0000aeb7 lui t4,0xa -80000318: 500e8e93 addi t4,t4,1280 # a500 <_start-0x7fff5b00> -8000031c: 00d00193 li gp,13 -80000320: 2bd31463 bne t1,t4,800005c8 - -80000324 : -80000324: 00000213 li tp,0 -80000328: 00d000b7 lui ra,0xd00 -8000032c: 00b00137 lui sp,0xb00 -80000330: 02209f33 mulh t5,ra,sp -80000334: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000338: 00200293 li t0,2 -8000033c: fe5216e3 bne tp,t0,80000328 -80000340: 00009eb7 lui t4,0x9 -80000344: f00e8e93 addi t4,t4,-256 # 8f00 <_start-0x7fff7100> -80000348: 00e00193 li gp,14 -8000034c: 27df1e63 bne t5,t4,800005c8 - -80000350 : -80000350: 00000213 li tp,0 -80000354: 00e000b7 lui ra,0xe00 -80000358: 00b00137 lui sp,0xb00 -8000035c: 00000013 nop -80000360: 02209f33 mulh t5,ra,sp -80000364: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000368: 00200293 li t0,2 -8000036c: fe5214e3 bne tp,t0,80000354 -80000370: 0000aeb7 lui t4,0xa -80000374: a00e8e93 addi t4,t4,-1536 # 9a00 <_start-0x7fff6600> -80000378: 00f00193 li gp,15 -8000037c: 25df1663 bne t5,t4,800005c8 - -80000380 : -80000380: 00000213 li tp,0 -80000384: 00f000b7 lui ra,0xf00 -80000388: 00b00137 lui sp,0xb00 -8000038c: 00000013 nop -80000390: 00000013 nop -80000394: 02209f33 mulh t5,ra,sp -80000398: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -8000039c: 00200293 li t0,2 -800003a0: fe5212e3 bne tp,t0,80000384 -800003a4: 0000aeb7 lui t4,0xa -800003a8: 500e8e93 addi t4,t4,1280 # a500 <_start-0x7fff5b00> -800003ac: 01000193 li gp,16 -800003b0: 21df1c63 bne t5,t4,800005c8 - -800003b4 : -800003b4: 00000213 li tp,0 -800003b8: 00d000b7 lui ra,0xd00 -800003bc: 00000013 nop -800003c0: 00b00137 lui sp,0xb00 -800003c4: 02209f33 mulh t5,ra,sp -800003c8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -800003cc: 00200293 li t0,2 -800003d0: fe5214e3 bne tp,t0,800003b8 -800003d4: 00009eb7 lui t4,0x9 -800003d8: f00e8e93 addi t4,t4,-256 # 8f00 <_start-0x7fff7100> -800003dc: 01100193 li gp,17 -800003e0: 1fdf1463 bne t5,t4,800005c8 - -800003e4 : -800003e4: 00000213 li tp,0 -800003e8: 00e000b7 lui ra,0xe00 -800003ec: 00000013 nop -800003f0: 00b00137 lui sp,0xb00 -800003f4: 00000013 nop -800003f8: 02209f33 mulh t5,ra,sp -800003fc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000400: 00200293 li t0,2 -80000404: fe5212e3 bne tp,t0,800003e8 -80000408: 0000aeb7 lui t4,0xa -8000040c: a00e8e93 addi t4,t4,-1536 # 9a00 <_start-0x7fff6600> -80000410: 01200193 li gp,18 -80000414: 1bdf1a63 bne t5,t4,800005c8 - -80000418 : -80000418: 00000213 li tp,0 -8000041c: 00f000b7 lui ra,0xf00 -80000420: 00000013 nop -80000424: 00000013 nop -80000428: 00b00137 lui sp,0xb00 -8000042c: 02209f33 mulh t5,ra,sp -80000430: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000434: 00200293 li t0,2 -80000438: fe5212e3 bne tp,t0,8000041c -8000043c: 0000aeb7 lui t4,0xa -80000440: 500e8e93 addi t4,t4,1280 # a500 <_start-0x7fff5b00> -80000444: 01300193 li gp,19 -80000448: 19df1063 bne t5,t4,800005c8 - -8000044c : -8000044c: 00000213 li tp,0 -80000450: 00b00137 lui sp,0xb00 -80000454: 00d000b7 lui ra,0xd00 -80000458: 02209f33 mulh t5,ra,sp -8000045c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000460: 00200293 li t0,2 -80000464: fe5216e3 bne tp,t0,80000450 -80000468: 00009eb7 lui t4,0x9 -8000046c: f00e8e93 addi t4,t4,-256 # 8f00 <_start-0x7fff7100> -80000470: 01400193 li gp,20 -80000474: 15df1a63 bne t5,t4,800005c8 - -80000478 : -80000478: 00000213 li tp,0 -8000047c: 00b00137 lui sp,0xb00 -80000480: 00e000b7 lui ra,0xe00 -80000484: 00000013 nop -80000488: 02209f33 mulh t5,ra,sp -8000048c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000490: 00200293 li t0,2 -80000494: fe5214e3 bne tp,t0,8000047c -80000498: 0000aeb7 lui t4,0xa -8000049c: a00e8e93 addi t4,t4,-1536 # 9a00 <_start-0x7fff6600> -800004a0: 01500193 li gp,21 -800004a4: 13df1263 bne t5,t4,800005c8 - -800004a8 : -800004a8: 00000213 li tp,0 -800004ac: 00b00137 lui sp,0xb00 -800004b0: 00f000b7 lui ra,0xf00 -800004b4: 00000013 nop -800004b8: 00000013 nop -800004bc: 02209f33 mulh t5,ra,sp -800004c0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -800004c4: 00200293 li t0,2 -800004c8: fe5212e3 bne tp,t0,800004ac -800004cc: 0000aeb7 lui t4,0xa -800004d0: 500e8e93 addi t4,t4,1280 # a500 <_start-0x7fff5b00> -800004d4: 01600193 li gp,22 -800004d8: 0fdf1863 bne t5,t4,800005c8 - -800004dc : -800004dc: 00000213 li tp,0 -800004e0: 00b00137 lui sp,0xb00 -800004e4: 00000013 nop -800004e8: 00d000b7 lui ra,0xd00 -800004ec: 02209f33 mulh t5,ra,sp -800004f0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -800004f4: 00200293 li t0,2 -800004f8: fe5214e3 bne tp,t0,800004e0 -800004fc: 00009eb7 lui t4,0x9 -80000500: f00e8e93 addi t4,t4,-256 # 8f00 <_start-0x7fff7100> -80000504: 01700193 li gp,23 -80000508: 0ddf1063 bne t5,t4,800005c8 - -8000050c : -8000050c: 00000213 li tp,0 -80000510: 00b00137 lui sp,0xb00 -80000514: 00000013 nop -80000518: 00e000b7 lui ra,0xe00 -8000051c: 00000013 nop -80000520: 02209f33 mulh t5,ra,sp -80000524: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000528: 00200293 li t0,2 -8000052c: fe5212e3 bne tp,t0,80000510 -80000530: 0000aeb7 lui t4,0xa -80000534: a00e8e93 addi t4,t4,-1536 # 9a00 <_start-0x7fff6600> -80000538: 01800193 li gp,24 -8000053c: 09df1663 bne t5,t4,800005c8 - -80000540 : -80000540: 00000213 li tp,0 -80000544: 00b00137 lui sp,0xb00 -80000548: 00000013 nop -8000054c: 00000013 nop -80000550: 00f000b7 lui ra,0xf00 -80000554: 02209f33 mulh t5,ra,sp -80000558: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -8000055c: 00200293 li t0,2 -80000560: fe5212e3 bne tp,t0,80000544 -80000564: 0000aeb7 lui t4,0xa -80000568: 500e8e93 addi t4,t4,1280 # a500 <_start-0x7fff5b00> -8000056c: 01900193 li gp,25 -80000570: 05df1c63 bne t5,t4,800005c8 - -80000574 : -80000574: 7c0000b7 lui ra,0x7c000 -80000578: 02101133 mulh sp,zero,ra -8000057c: 00000e93 li t4,0 -80000580: 01a00193 li gp,26 -80000584: 05d11263 bne sp,t4,800005c8 - -80000588 : -80000588: 800000b7 lui ra,0x80000 -8000058c: 02009133 mulh sp,ra,zero -80000590: 00000e93 li t4,0 -80000594: 01b00193 li gp,27 -80000598: 03d11863 bne sp,t4,800005c8 - -8000059c : -8000059c: 020010b3 mulh ra,zero,zero -800005a0: 00000e93 li t4,0 -800005a4: 01c00193 li gp,28 -800005a8: 03d09063 bne ra,t4,800005c8 - -800005ac : -800005ac: 021000b7 lui ra,0x2100 -800005b0: 02200137 lui sp,0x2200 -800005b4: 02209033 mulh zero,ra,sp -800005b8: 00000e93 li t4,0 -800005bc: 01d00193 li gp,29 -800005c0: 01d01463 bne zero,t4,800005c8 -800005c4: 00301c63 bne zero,gp,800005dc - -800005c8 : -800005c8: 0ff0000f fence -800005cc: 00018063 beqz gp,800005cc -800005d0: 00119193 slli gp,gp,0x1 -800005d4: 0011e193 ori gp,gp,1 -800005d8: 00000073 ecall - -800005dc : -800005dc: 0ff0000f fence -800005e0: 00100193 li gp,1 -800005e4: 00000073 ecall -800005e8: c0001073 unimp -800005ec: 0000 unimp -800005ee: 0000 unimp -800005f0: 0000 unimp -800005f2: 0000 unimp -800005f4: 0000 unimp -800005f6: 0000 unimp -800005f8: 0000 unimp -800005fa: 0000 unimp -800005fc: 0000 unimp -800005fe: 0000 unimp -80000600: 0000 unimp -80000602: 0000 unimp diff --git a/benchmarks/riscv_tests/rv32um-p-mulh.hex b/benchmarks/riscv_tests/rv32um-p-mulh.hex deleted file mode 100644 index d4117c00..00000000 --- a/benchmarks/riscv_tests/rv32um-p-mulh.hex +++ /dev/null @@ -1,101 +0,0 @@ -:0200000480007A -:100000006F00C004732F2034930F8000630AFF0336 -:10001000930F90006306FF03930FB0006302FF038A -:10002000170F0080130F0FFE63040F0067000F000F -:10003000732F203463540F006F004000136E9E53E3 -:10004000171F00002320CFFD6FF09FFF732540F1A5 -:100050006310050073251030635805000F00F00F82 -:10006000130E100073000000130E00009702000032 -:10007000938282F973905230735020307350303035 -:1000800073504030970200809382C2F7638C020065 -:10009000739052109302B01A739022307323203061 -:1000A000E39E62F873500030970200009382420191 -:1000B00073901234732540F17300203093000000D8 -:1000C00013010000B3912002930E0000130E2000D4 -:1000D000639AD14B9300100013011000B3912002DA -:1000E000930E0000130E3000639ED1499300300040 -:1000F00013017000B3912002930E0000130E400014 -:100100006392D149930000003781FFFFB391200231 -:10011000930E0000130E50006396D147B700008085 -:1001200013010000B3912002930E0000130E600033 -:10013000639AD145B700008013010000B3912002FB -:10014000930E0000130E7000639ED143B7B0AAAAAD -:100150009380B0AA370103001301D1E7B3912002C5 -:10016000B70EFFFF938E1E08130EE001639CD14172 -:10017000B70003009380D0E737B1AAAA1301B1AA50 -:10018000B3912002B70EFFFF938E1E08130EF001ED -:10019000639AD13FB70000FF370100FFB3912002FF -:1001A000B70E0100130E0002639ED13D9300F0FFD5 -:1001B0001301F0FFB3912002930E0000130E100202 -:1001C0006392D13D9300F0FF13011000B391200220 -:1001D000930EF0FF130E20026396D13B93001000A4 -:1001E0001301F0FFB3912002930EF0FF130E3002C3 -:1001F000639AD139B700D0003701B000B390200224 -:10020000B79E0000938E0EF0130E8000639CD037D3 -:10021000B700E0003701B00033912002B7AE000014 -:10022000938E0EA0130E9000631ED135B700D00040 -:10023000B3901002B7BE0000938E0E90130EA00074 -:100240006392D03513020000B700D0003701B00030 -:10025000B3912002138301001302120093022000C5 -:10026000E31452FEB79E0000938E0EF0130EB00002 -:10027000631AD33113020000B700E0003701B00069 -:10028000B391200213000000138301001302120037 -:1002900093022000E31252FEB7AE0000938E0EA030 -:1002A000130EC0006310D32F13020000B700F0003C -:1002B0003701B000B39120021300000013000000CA -:1002C000138301001302120093022000E31052FE78 -:1002D000B7AE0000938E0E50130ED0006314D32BD4 -:1002E00013020000B700D0003701B000B391200224 -:1002F0001302120093022000E31652FEB79E000084 -:10030000938E0EF0130EE000639ED12713020000BF -:10031000B700E0003701B00013000000B3912002E5 -:100320001302120093022000E31452FEB7AE000045 -:10033000938E0EA0130EF0006396D12513020000D9 -:10034000B700F0003701B0001300000013000000F8 -:10035000B39120021302120093022000E31252FE16 -:10036000B7AE0000938E0E50130E0001639CD12196 -:1003700013020000B700D000130000003701B000E6 -:10038000B39120021302120093022000E31452FEE4 -:10039000B79E0000938E0EF0130E10016394D11FD0 -:1003A00013020000B700E000130000003701B000A6 -:1003B00013000000B39120021302120093022000E8 -:1003C000E31252FEB7AE0000938E0EA0130E200172 -:1003D000639AD11B13020000B700F0001300000065 -:1003E000130000003701B000B39120021302120085 -:1003F00093022000E31252FEB7AE0000938E0E501F -:10040000130E30016390D119130200003701B000C0 -:10041000B700D000B3912002130212009302200013 -:10042000E31652FEB79E0000938E0EF0130E4001AD -:10043000639AD115130200003701B000B700E00045 -:1004400013000000B3912002130212009302200057 -:10045000E31452FEB7AE0000938E0EA0130E5001AF -:100460006392D113130200003701B000B700F0000F -:100470001300000013000000B391200213021200C9 -:1004800093022000E31252FEB7AE0000938E0E508E -:10049000130E60016398D10F130200003701B00002 -:1004A00013000000B700D000B39120021302120025 -:1004B00093022000E31452FEB79E0000938E0EF0CC -:1004C000130E70016390D10D130200003701B000CC -:1004D00013000000B700E00013000000B3912002F9 -:1004E0001302120093022000E31252FEB7AE000086 -:1004F000938E0EA0130E80016396D10913020000A3 -:100500003701B0001300000013000000B700F00036 -:10051000B39120021302120093022000E31252FE54 -:10052000B7AE0000938E0E50130E9001639CD10560 -:10053000B700007C33111002930E0000130EA001CF -:100540006312D105B700008033910002930E0000C2 -:10055000130EB0016318D103B3100002930E000014 -:10056000130EC0016390D003B700100237012002C0 -:1005700033902002930E0000130ED0016314D001BB -:10058000631CC0010F00F00F63000E00131E1E005D -:10059000136E1E00730000000F00F00F130E10000A -:1005A00073000000731000C0000000000000000095 -:1005B000000000000000000000000000000000003B -:0405C0000000000037 -:1010000000000000000000000000000000000000E0 -:1010100000000000000000000000000000000000D0 -:1010200000000000000000000000000000000000C0 -:1010300000000000000000000000000000000000B0 -:081040000000000000000000A8 -:040000058000200057 -:00000001FF diff --git a/benchmarks/riscv_tests/rv32um-p-mulhsu.dump b/benchmarks/riscv_tests/rv32um-p-mulhsu.dump deleted file mode 100644 index 7ce86c65..00000000 --- a/benchmarks/riscv_tests/rv32um-p-mulhsu.dump +++ /dev/null @@ -1,478 +0,0 @@ - -rv32um-p-mulhsu: file format elf32-littleriscv - - -Disassembly of section .text.init: - -80000000 <_start>: -80000000: 04c0006f j 8000004c - -80000004 : -80000004: 34202f73 csrr t5,mcause -80000008: 00800f93 li t6,8 -8000000c: 03ff0a63 beq t5,t6,80000040 -80000010: 00900f93 li t6,9 -80000014: 03ff0663 beq t5,t6,80000040 -80000018: 00b00f93 li t6,11 -8000001c: 03ff0263 beq t5,t6,80000040 -80000020: 80000f17 auipc t5,0x80000 -80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> -80000028: 000f0463 beqz t5,80000030 -8000002c: 000f0067 jr t5 -80000030: 34202f73 csrr t5,mcause -80000034: 000f5463 bgez t5,8000003c -80000038: 0040006f j 8000003c - -8000003c : -8000003c: 5391e193 ori gp,gp,1337 - -80000040 : -80000040: 00001f17 auipc t5,0x1 -80000044: fc3f2023 sw gp,-64(t5) # 80001000 -80000048: ff9ff06f j 80000040 - -8000004c : -8000004c: f1402573 csrr a0,mhartid -80000050: 00051063 bnez a0,80000050 -80000054: 00000297 auipc t0,0x0 -80000058: 01028293 addi t0,t0,16 # 80000064 -8000005c: 30529073 csrw mtvec,t0 -80000060: 18005073 csrwi satp,0 -80000064: 00000297 auipc t0,0x0 -80000068: 02028293 addi t0,t0,32 # 80000084 -8000006c: 30529073 csrw mtvec,t0 -80000070: 800002b7 lui t0,0x80000 -80000074: fff28293 addi t0,t0,-1 # 7fffffff <_end+0xffffdfff> -80000078: 3b029073 csrw pmpaddr0,t0 -8000007c: 01f00293 li t0,31 -80000080: 3a029073 csrw pmpcfg0,t0 -80000084: 00000297 auipc t0,0x0 -80000088: 01828293 addi t0,t0,24 # 8000009c -8000008c: 30529073 csrw mtvec,t0 -80000090: 30205073 csrwi medeleg,0 -80000094: 30305073 csrwi mideleg,0 -80000098: 30405073 csrwi mie,0 -8000009c: 00000193 li gp,0 -800000a0: 00000297 auipc t0,0x0 -800000a4: f6428293 addi t0,t0,-156 # 80000004 -800000a8: 30529073 csrw mtvec,t0 -800000ac: 00100513 li a0,1 -800000b0: 01f51513 slli a0,a0,0x1f -800000b4: 00054863 bltz a0,800000c4 -800000b8: 0ff0000f fence -800000bc: 00100193 li gp,1 -800000c0: 00000073 ecall -800000c4: 80000297 auipc t0,0x80000 -800000c8: f3c28293 addi t0,t0,-196 # 0 <_start-0x80000000> -800000cc: 00028e63 beqz t0,800000e8 -800000d0: 10529073 csrw stvec,t0 -800000d4: 0000b2b7 lui t0,0xb -800000d8: 10928293 addi t0,t0,265 # b109 <_start-0x7fff4ef7> -800000dc: 30229073 csrw medeleg,t0 -800000e0: 30202373 csrr t1,medeleg -800000e4: f4629ce3 bne t0,t1,8000003c -800000e8: 30005073 csrwi mstatus,0 -800000ec: 00000297 auipc t0,0x0 -800000f0: 01428293 addi t0,t0,20 # 80000100 -800000f4: 34129073 csrw mepc,t0 -800000f8: f1402573 csrr a0,mhartid -800000fc: 30200073 mret - -80000100 : -80000100: 00000093 li ra,0 -80000104: 00000113 li sp,0 -80000108: 0220af33 mulhsu t5,ra,sp -8000010c: 00000e93 li t4,0 -80000110: 00200193 li gp,2 -80000114: 4bdf1a63 bne t5,t4,800005c8 - -80000118 : -80000118: 00100093 li ra,1 -8000011c: 00100113 li sp,1 -80000120: 0220af33 mulhsu t5,ra,sp -80000124: 00000e93 li t4,0 -80000128: 00300193 li gp,3 -8000012c: 49df1e63 bne t5,t4,800005c8 - -80000130 : -80000130: 00300093 li ra,3 -80000134: 00700113 li sp,7 -80000138: 0220af33 mulhsu t5,ra,sp -8000013c: 00000e93 li t4,0 -80000140: 00400193 li gp,4 -80000144: 49df1263 bne t5,t4,800005c8 - -80000148 : -80000148: 00000093 li ra,0 -8000014c: ffff8137 lui sp,0xffff8 -80000150: 0220af33 mulhsu t5,ra,sp -80000154: 00000e93 li t4,0 -80000158: 00500193 li gp,5 -8000015c: 47df1663 bne t5,t4,800005c8 - -80000160 : -80000160: 800000b7 lui ra,0x80000 -80000164: 00000113 li sp,0 -80000168: 0220af33 mulhsu t5,ra,sp -8000016c: 00000e93 li t4,0 -80000170: 00600193 li gp,6 -80000174: 45df1a63 bne t5,t4,800005c8 - -80000178 : -80000178: 800000b7 lui ra,0x80000 -8000017c: ffff8137 lui sp,0xffff8 -80000180: 0220af33 mulhsu t5,ra,sp -80000184: 80004eb7 lui t4,0x80004 -80000188: 00700193 li gp,7 -8000018c: 43df1e63 bne t5,t4,800005c8 - -80000190 : -80000190: aaaab0b7 lui ra,0xaaaab -80000194: aab08093 addi ra,ra,-1365 # aaaaaaab <_end+0x2aaa8aab> -80000198: 00030137 lui sp,0x30 -8000019c: e7d10113 addi sp,sp,-387 # 2fe7d <_start-0x7ffd0183> -800001a0: 0220af33 mulhsu t5,ra,sp -800001a4: ffff0eb7 lui t4,0xffff0 -800001a8: 081e8e93 addi t4,t4,129 # ffff0081 <_end+0x7ffee081> -800001ac: 01e00193 li gp,30 -800001b0: 41df1c63 bne t5,t4,800005c8 - -800001b4 : -800001b4: 000300b7 lui ra,0x30 -800001b8: e7d08093 addi ra,ra,-387 # 2fe7d <_start-0x7ffd0183> -800001bc: aaaab137 lui sp,0xaaaab -800001c0: aab10113 addi sp,sp,-1365 # aaaaaaab <_end+0x2aaa8aab> -800001c4: 0220af33 mulhsu t5,ra,sp -800001c8: 00020eb7 lui t4,0x20 -800001cc: efee8e93 addi t4,t4,-258 # 1fefe <_start-0x7ffe0102> -800001d0: 01f00193 li gp,31 -800001d4: 3fdf1a63 bne t5,t4,800005c8 - -800001d8 : -800001d8: ff0000b7 lui ra,0xff000 -800001dc: ff000137 lui sp,0xff000 -800001e0: 0220af33 mulhsu t5,ra,sp -800001e4: ff010eb7 lui t4,0xff010 -800001e8: 02000193 li gp,32 -800001ec: 3ddf1e63 bne t5,t4,800005c8 - -800001f0 : -800001f0: fff00093 li ra,-1 -800001f4: fff00113 li sp,-1 -800001f8: 0220af33 mulhsu t5,ra,sp -800001fc: fff00e93 li t4,-1 -80000200: 02100193 li gp,33 -80000204: 3ddf1263 bne t5,t4,800005c8 - -80000208 : -80000208: fff00093 li ra,-1 -8000020c: 00100113 li sp,1 -80000210: 0220af33 mulhsu t5,ra,sp -80000214: fff00e93 li t4,-1 -80000218: 02200193 li gp,34 -8000021c: 3bdf1663 bne t5,t4,800005c8 - -80000220 : -80000220: 00100093 li ra,1 -80000224: fff00113 li sp,-1 -80000228: 0220af33 mulhsu t5,ra,sp -8000022c: 00000e93 li t4,0 -80000230: 02300193 li gp,35 -80000234: 39df1a63 bne t5,t4,800005c8 - -80000238 : -80000238: 00d000b7 lui ra,0xd00 -8000023c: 00b00137 lui sp,0xb00 -80000240: 0220a0b3 mulhsu ra,ra,sp -80000244: 00009eb7 lui t4,0x9 -80000248: f00e8e93 addi t4,t4,-256 # 8f00 <_start-0x7fff7100> -8000024c: 00800193 li gp,8 -80000250: 37d09c63 bne ra,t4,800005c8 - -80000254 : -80000254: 00e000b7 lui ra,0xe00 -80000258: 00b00137 lui sp,0xb00 -8000025c: 0220a133 mulhsu sp,ra,sp -80000260: 0000aeb7 lui t4,0xa -80000264: a00e8e93 addi t4,t4,-1536 # 9a00 <_start-0x7fff6600> -80000268: 00900193 li gp,9 -8000026c: 35d11e63 bne sp,t4,800005c8 - -80000270 : -80000270: 00d000b7 lui ra,0xd00 -80000274: 0210a0b3 mulhsu ra,ra,ra -80000278: 0000beb7 lui t4,0xb -8000027c: 900e8e93 addi t4,t4,-1792 # a900 <_start-0x7fff5700> -80000280: 00a00193 li gp,10 -80000284: 35d09263 bne ra,t4,800005c8 - -80000288 : -80000288: 00000213 li tp,0 -8000028c: 00d000b7 lui ra,0xd00 -80000290: 00b00137 lui sp,0xb00 -80000294: 0220af33 mulhsu t5,ra,sp -80000298: 000f0313 mv t1,t5 -8000029c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -800002a0: 00200293 li t0,2 -800002a4: fe5214e3 bne tp,t0,8000028c -800002a8: 00009eb7 lui t4,0x9 -800002ac: f00e8e93 addi t4,t4,-256 # 8f00 <_start-0x7fff7100> -800002b0: 00b00193 li gp,11 -800002b4: 31d31a63 bne t1,t4,800005c8 - -800002b8 : -800002b8: 00000213 li tp,0 -800002bc: 00e000b7 lui ra,0xe00 -800002c0: 00b00137 lui sp,0xb00 -800002c4: 0220af33 mulhsu t5,ra,sp -800002c8: 00000013 nop -800002cc: 000f0313 mv t1,t5 -800002d0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -800002d4: 00200293 li t0,2 -800002d8: fe5212e3 bne tp,t0,800002bc -800002dc: 0000aeb7 lui t4,0xa -800002e0: a00e8e93 addi t4,t4,-1536 # 9a00 <_start-0x7fff6600> -800002e4: 00c00193 li gp,12 -800002e8: 2fd31063 bne t1,t4,800005c8 - -800002ec : -800002ec: 00000213 li tp,0 -800002f0: 00f000b7 lui ra,0xf00 -800002f4: 00b00137 lui sp,0xb00 -800002f8: 0220af33 mulhsu t5,ra,sp -800002fc: 00000013 nop -80000300: 00000013 nop -80000304: 000f0313 mv t1,t5 -80000308: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -8000030c: 00200293 li t0,2 -80000310: fe5210e3 bne tp,t0,800002f0 -80000314: 0000aeb7 lui t4,0xa -80000318: 500e8e93 addi t4,t4,1280 # a500 <_start-0x7fff5b00> -8000031c: 00d00193 li gp,13 -80000320: 2bd31463 bne t1,t4,800005c8 - -80000324 : -80000324: 00000213 li tp,0 -80000328: 00d000b7 lui ra,0xd00 -8000032c: 00b00137 lui sp,0xb00 -80000330: 0220af33 mulhsu t5,ra,sp -80000334: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000338: 00200293 li t0,2 -8000033c: fe5216e3 bne tp,t0,80000328 -80000340: 00009eb7 lui t4,0x9 -80000344: f00e8e93 addi t4,t4,-256 # 8f00 <_start-0x7fff7100> -80000348: 00e00193 li gp,14 -8000034c: 27df1e63 bne t5,t4,800005c8 - -80000350 : -80000350: 00000213 li tp,0 -80000354: 00e000b7 lui ra,0xe00 -80000358: 00b00137 lui sp,0xb00 -8000035c: 00000013 nop -80000360: 0220af33 mulhsu t5,ra,sp -80000364: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000368: 00200293 li t0,2 -8000036c: fe5214e3 bne tp,t0,80000354 -80000370: 0000aeb7 lui t4,0xa -80000374: a00e8e93 addi t4,t4,-1536 # 9a00 <_start-0x7fff6600> -80000378: 00f00193 li gp,15 -8000037c: 25df1663 bne t5,t4,800005c8 - -80000380 : -80000380: 00000213 li tp,0 -80000384: 00f000b7 lui ra,0xf00 -80000388: 00b00137 lui sp,0xb00 -8000038c: 00000013 nop -80000390: 00000013 nop -80000394: 0220af33 mulhsu t5,ra,sp -80000398: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -8000039c: 00200293 li t0,2 -800003a0: fe5212e3 bne tp,t0,80000384 -800003a4: 0000aeb7 lui t4,0xa -800003a8: 500e8e93 addi t4,t4,1280 # a500 <_start-0x7fff5b00> -800003ac: 01000193 li gp,16 -800003b0: 21df1c63 bne t5,t4,800005c8 - -800003b4 : -800003b4: 00000213 li tp,0 -800003b8: 00d000b7 lui ra,0xd00 -800003bc: 00000013 nop -800003c0: 00b00137 lui sp,0xb00 -800003c4: 0220af33 mulhsu t5,ra,sp -800003c8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -800003cc: 00200293 li t0,2 -800003d0: fe5214e3 bne tp,t0,800003b8 -800003d4: 00009eb7 lui t4,0x9 -800003d8: f00e8e93 addi t4,t4,-256 # 8f00 <_start-0x7fff7100> -800003dc: 01100193 li gp,17 -800003e0: 1fdf1463 bne t5,t4,800005c8 - -800003e4 : -800003e4: 00000213 li tp,0 -800003e8: 00e000b7 lui ra,0xe00 -800003ec: 00000013 nop -800003f0: 00b00137 lui sp,0xb00 -800003f4: 00000013 nop -800003f8: 0220af33 mulhsu t5,ra,sp -800003fc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000400: 00200293 li t0,2 -80000404: fe5212e3 bne tp,t0,800003e8 -80000408: 0000aeb7 lui t4,0xa -8000040c: a00e8e93 addi t4,t4,-1536 # 9a00 <_start-0x7fff6600> -80000410: 01200193 li gp,18 -80000414: 1bdf1a63 bne t5,t4,800005c8 - -80000418 : -80000418: 00000213 li tp,0 -8000041c: 00f000b7 lui ra,0xf00 -80000420: 00000013 nop -80000424: 00000013 nop -80000428: 00b00137 lui sp,0xb00 -8000042c: 0220af33 mulhsu t5,ra,sp -80000430: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000434: 00200293 li t0,2 -80000438: fe5212e3 bne tp,t0,8000041c -8000043c: 0000aeb7 lui t4,0xa -80000440: 500e8e93 addi t4,t4,1280 # a500 <_start-0x7fff5b00> -80000444: 01300193 li gp,19 -80000448: 19df1063 bne t5,t4,800005c8 - -8000044c : -8000044c: 00000213 li tp,0 -80000450: 00b00137 lui sp,0xb00 -80000454: 00d000b7 lui ra,0xd00 -80000458: 0220af33 mulhsu t5,ra,sp -8000045c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000460: 00200293 li t0,2 -80000464: fe5216e3 bne tp,t0,80000450 -80000468: 00009eb7 lui t4,0x9 -8000046c: f00e8e93 addi t4,t4,-256 # 8f00 <_start-0x7fff7100> -80000470: 01400193 li gp,20 -80000474: 15df1a63 bne t5,t4,800005c8 - -80000478 : -80000478: 00000213 li tp,0 -8000047c: 00b00137 lui sp,0xb00 -80000480: 00e000b7 lui ra,0xe00 -80000484: 00000013 nop -80000488: 0220af33 mulhsu t5,ra,sp -8000048c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000490: 00200293 li t0,2 -80000494: fe5214e3 bne tp,t0,8000047c -80000498: 0000aeb7 lui t4,0xa -8000049c: a00e8e93 addi t4,t4,-1536 # 9a00 <_start-0x7fff6600> -800004a0: 01500193 li gp,21 -800004a4: 13df1263 bne t5,t4,800005c8 - -800004a8 : -800004a8: 00000213 li tp,0 -800004ac: 00b00137 lui sp,0xb00 -800004b0: 00f000b7 lui ra,0xf00 -800004b4: 00000013 nop -800004b8: 00000013 nop -800004bc: 0220af33 mulhsu t5,ra,sp -800004c0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -800004c4: 00200293 li t0,2 -800004c8: fe5212e3 bne tp,t0,800004ac -800004cc: 0000aeb7 lui t4,0xa -800004d0: 500e8e93 addi t4,t4,1280 # a500 <_start-0x7fff5b00> -800004d4: 01600193 li gp,22 -800004d8: 0fdf1863 bne t5,t4,800005c8 - -800004dc : -800004dc: 00000213 li tp,0 -800004e0: 00b00137 lui sp,0xb00 -800004e4: 00000013 nop -800004e8: 00d000b7 lui ra,0xd00 -800004ec: 0220af33 mulhsu t5,ra,sp -800004f0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -800004f4: 00200293 li t0,2 -800004f8: fe5214e3 bne tp,t0,800004e0 -800004fc: 00009eb7 lui t4,0x9 -80000500: f00e8e93 addi t4,t4,-256 # 8f00 <_start-0x7fff7100> -80000504: 01700193 li gp,23 -80000508: 0ddf1063 bne t5,t4,800005c8 - -8000050c : -8000050c: 00000213 li tp,0 -80000510: 00b00137 lui sp,0xb00 -80000514: 00000013 nop -80000518: 00e000b7 lui ra,0xe00 -8000051c: 00000013 nop -80000520: 0220af33 mulhsu t5,ra,sp -80000524: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000528: 00200293 li t0,2 -8000052c: fe5212e3 bne tp,t0,80000510 -80000530: 0000aeb7 lui t4,0xa -80000534: a00e8e93 addi t4,t4,-1536 # 9a00 <_start-0x7fff6600> -80000538: 01800193 li gp,24 -8000053c: 09df1663 bne t5,t4,800005c8 - -80000540 : -80000540: 00000213 li tp,0 -80000544: 00b00137 lui sp,0xb00 -80000548: 00000013 nop -8000054c: 00000013 nop -80000550: 00f000b7 lui ra,0xf00 -80000554: 0220af33 mulhsu t5,ra,sp -80000558: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -8000055c: 00200293 li t0,2 -80000560: fe5212e3 bne tp,t0,80000544 -80000564: 0000aeb7 lui t4,0xa -80000568: 500e8e93 addi t4,t4,1280 # a500 <_start-0x7fff5b00> -8000056c: 01900193 li gp,25 -80000570: 05df1c63 bne t5,t4,800005c8 - -80000574 : -80000574: 7c0000b7 lui ra,0x7c000 -80000578: 02102133 mulhsu sp,zero,ra -8000057c: 00000e93 li t4,0 -80000580: 01a00193 li gp,26 -80000584: 05d11263 bne sp,t4,800005c8 - -80000588 : -80000588: 800000b7 lui ra,0x80000 -8000058c: 0200a133 mulhsu sp,ra,zero -80000590: 00000e93 li t4,0 -80000594: 01b00193 li gp,27 -80000598: 03d11863 bne sp,t4,800005c8 - -8000059c : -8000059c: 020020b3 mulhsu ra,zero,zero -800005a0: 00000e93 li t4,0 -800005a4: 01c00193 li gp,28 -800005a8: 03d09063 bne ra,t4,800005c8 - -800005ac : -800005ac: 021000b7 lui ra,0x2100 -800005b0: 02200137 lui sp,0x2200 -800005b4: 0220a033 mulhsu zero,ra,sp -800005b8: 00000e93 li t4,0 -800005bc: 01d00193 li gp,29 -800005c0: 01d01463 bne zero,t4,800005c8 -800005c4: 00301c63 bne zero,gp,800005dc - -800005c8 : -800005c8: 0ff0000f fence -800005cc: 00018063 beqz gp,800005cc -800005d0: 00119193 slli gp,gp,0x1 -800005d4: 0011e193 ori gp,gp,1 -800005d8: 00000073 ecall - -800005dc : -800005dc: 0ff0000f fence -800005e0: 00100193 li gp,1 -800005e4: 00000073 ecall -800005e8: c0001073 unimp -800005ec: 0000 unimp -800005ee: 0000 unimp -800005f0: 0000 unimp -800005f2: 0000 unimp -800005f4: 0000 unimp -800005f6: 0000 unimp -800005f8: 0000 unimp -800005fa: 0000 unimp -800005fc: 0000 unimp -800005fe: 0000 unimp -80000600: 0000 unimp -80000602: 0000 unimp diff --git a/benchmarks/riscv_tests/rv32um-p-mulhsu.hex b/benchmarks/riscv_tests/rv32um-p-mulhsu.hex deleted file mode 100644 index 131a31a2..00000000 --- a/benchmarks/riscv_tests/rv32um-p-mulhsu.hex +++ /dev/null @@ -1,101 +0,0 @@ -:0200000480007A -:100000006F00C004732F2034930F8000630AFF0336 -:10001000930F90006306FF03930FB0006302FF038A -:10002000170F0080130F0FFE63040F0067000F000F -:10003000732F203463540F006F004000136E9E53E3 -:10004000171F00002320CFFD6FF09FFF732540F1A5 -:100050006310050073251030635805000F00F00F82 -:10006000130E100073000000130E00009702000032 -:10007000938282F973905230735020307350303035 -:1000800073504030970200809382C2F7638C020065 -:10009000739052109302B01A739022307323203061 -:1000A000E39E62F873500030970200009382420191 -:1000B00073901234732540F17300203093000000D8 -:1000C00013010000B3A12002930E0000130E2000C4 -:1000D000639AD14B9300100013011000B3A12002CA -:1000E000930E0000130E3000639ED1499300300040 -:1000F00013017000B3A12002930E0000130E400004 -:100100006392D149930000003781FFFFB3A1200221 -:10011000930E0000130E50006396D147B700008085 -:1001200013010000B3A12002930E0000130E600023 -:10013000639AD145B70000803781FFFFB3A1200249 -:10014000B74E0080130E7000639ED143B7B0AAAAC9 -:100150009380B0AA370103001301D1E7B3A12002B5 -:10016000B70EFFFF938E1E08130EE001639CD14172 -:10017000B70003009380D0E737B1AAAA1301B1AA50 -:10018000B3A12002B70E0200938EEEEF130EF00122 -:10019000639AD13FB70000FF370100FFB3A12002EF -:1001A000B70E01FF130E0002639ED13D9300F0FFD6 -:1001B0001301F0FFB3A12002930EF0FF130E100203 -:1001C0006392D13D9300F0FF13011000B3A1200210 -:1001D000930EF0FF130E20026396D13B93001000A4 -:1001E0001301F0FFB3A12002930E0000130E3002A2 -:1001F000639AD139B700D0003701B000B3A0200214 -:10020000B79E0000938E0EF0130E8000639CD037D3 -:10021000B700E0003701B00033A12002B7AE000004 -:10022000938E0EA0130E9000631ED135B700D00040 -:10023000B3A01002B7BE0000938E0E90130EA00064 -:100240006392D03513020000B700D0003701B00030 -:10025000B3A12002138301001302120093022000B5 -:10026000E31452FEB79E0000938E0EF0130EB00002 -:10027000631AD33113020000B700E0003701B00069 -:10028000B3A1200213000000138301001302120027 -:1002900093022000E31252FEB7AE0000938E0EA030 -:1002A000130EC0006310D32F13020000B700F0003C -:1002B0003701B000B3A120021300000013000000BA -:1002C000138301001302120093022000E31052FE78 -:1002D000B7AE0000938E0E50130ED0006314D32BD4 -:1002E00013020000B700D0003701B000B3A1200214 -:1002F0001302120093022000E31652FEB79E000084 -:10030000938E0EF0130EE000639ED12713020000BF -:10031000B700E0003701B00013000000B3A12002D5 -:100320001302120093022000E31452FEB7AE000045 -:10033000938E0EA0130EF0006396D12513020000D9 -:10034000B700F0003701B0001300000013000000F8 -:10035000B3A120021302120093022000E31252FE06 -:10036000B7AE0000938E0E50130E0001639CD12196 -:1003700013020000B700D000130000003701B000E6 -:10038000B3A120021302120093022000E31452FED4 -:10039000B79E0000938E0EF0130E10016394D11FD0 -:1003A00013020000B700E000130000003701B000A6 -:1003B00013000000B3A120021302120093022000D8 -:1003C000E31252FEB7AE0000938E0EA0130E200172 -:1003D000639AD11B13020000B700F0001300000065 -:1003E000130000003701B000B3A120021302120075 -:1003F00093022000E31252FEB7AE0000938E0E501F -:10040000130E30016390D119130200003701B000C0 -:10041000B700D000B3A12002130212009302200003 -:10042000E31652FEB79E0000938E0EF0130E4001AD -:10043000639AD115130200003701B000B700E00045 -:1004400013000000B3A12002130212009302200047 -:10045000E31452FEB7AE0000938E0EA0130E5001AF -:100460006392D113130200003701B000B700F0000F -:100470001300000013000000B3A1200213021200B9 -:1004800093022000E31252FEB7AE0000938E0E508E -:10049000130E60016398D10F130200003701B00002 -:1004A00013000000B700D000B3A120021302120015 -:1004B00093022000E31452FEB79E0000938E0EF0CC -:1004C000130E70016390D10D130200003701B000CC -:1004D00013000000B700E00013000000B3A12002E9 -:1004E0001302120093022000E31252FEB7AE000086 -:1004F000938E0EA0130E80016396D10913020000A3 -:100500003701B0001300000013000000B700F00036 -:10051000B3A120021302120093022000E31252FE44 -:10052000B7AE0000938E0E50130E9001639CD10560 -:10053000B700007C33211002930E0000130EA001BF -:100540006312D105B700008033A10002930E0000B2 -:10055000130EB0016318D103B3200002930E000004 -:10056000130EC0016390D003B700100237012002C0 -:1005700033A02002930E0000130ED0016314D001AB -:10058000631CC0010F00F00F63000E00131E1E005D -:10059000136E1E00730000000F00F00F130E10000A -:1005A00073000000731000C0000000000000000095 -:1005B000000000000000000000000000000000003B -:0405C0000000000037 -:1010000000000000000000000000000000000000E0 -:1010100000000000000000000000000000000000D0 -:1010200000000000000000000000000000000000C0 -:1010300000000000000000000000000000000000B0 -:081040000000000000000000A8 -:040000058000200057 -:00000001FF diff --git a/benchmarks/riscv_tests/rv32um-p-mulhu.dump b/benchmarks/riscv_tests/rv32um-p-mulhu.dump deleted file mode 100644 index d2e65008..00000000 --- a/benchmarks/riscv_tests/rv32um-p-mulhu.dump +++ /dev/null @@ -1,478 +0,0 @@ - -rv32um-p-mulhu: file format elf32-littleriscv - - -Disassembly of section .text.init: - -80000000 <_start>: -80000000: 04c0006f j 8000004c - -80000004 : -80000004: 34202f73 csrr t5,mcause -80000008: 00800f93 li t6,8 -8000000c: 03ff0a63 beq t5,t6,80000040 -80000010: 00900f93 li t6,9 -80000014: 03ff0663 beq t5,t6,80000040 -80000018: 00b00f93 li t6,11 -8000001c: 03ff0263 beq t5,t6,80000040 -80000020: 80000f17 auipc t5,0x80000 -80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> -80000028: 000f0463 beqz t5,80000030 -8000002c: 000f0067 jr t5 -80000030: 34202f73 csrr t5,mcause -80000034: 000f5463 bgez t5,8000003c -80000038: 0040006f j 8000003c - -8000003c : -8000003c: 5391e193 ori gp,gp,1337 - -80000040 : -80000040: 00001f17 auipc t5,0x1 -80000044: fc3f2023 sw gp,-64(t5) # 80001000 -80000048: ff9ff06f j 80000040 - -8000004c : -8000004c: f1402573 csrr a0,mhartid -80000050: 00051063 bnez a0,80000050 -80000054: 00000297 auipc t0,0x0 -80000058: 01028293 addi t0,t0,16 # 80000064 -8000005c: 30529073 csrw mtvec,t0 -80000060: 18005073 csrwi satp,0 -80000064: 00000297 auipc t0,0x0 -80000068: 02028293 addi t0,t0,32 # 80000084 -8000006c: 30529073 csrw mtvec,t0 -80000070: 800002b7 lui t0,0x80000 -80000074: fff28293 addi t0,t0,-1 # 7fffffff <_end+0xffffdfff> -80000078: 3b029073 csrw pmpaddr0,t0 -8000007c: 01f00293 li t0,31 -80000080: 3a029073 csrw pmpcfg0,t0 -80000084: 00000297 auipc t0,0x0 -80000088: 01828293 addi t0,t0,24 # 8000009c -8000008c: 30529073 csrw mtvec,t0 -80000090: 30205073 csrwi medeleg,0 -80000094: 30305073 csrwi mideleg,0 -80000098: 30405073 csrwi mie,0 -8000009c: 00000193 li gp,0 -800000a0: 00000297 auipc t0,0x0 -800000a4: f6428293 addi t0,t0,-156 # 80000004 -800000a8: 30529073 csrw mtvec,t0 -800000ac: 00100513 li a0,1 -800000b0: 01f51513 slli a0,a0,0x1f -800000b4: 00054863 bltz a0,800000c4 -800000b8: 0ff0000f fence -800000bc: 00100193 li gp,1 -800000c0: 00000073 ecall -800000c4: 80000297 auipc t0,0x80000 -800000c8: f3c28293 addi t0,t0,-196 # 0 <_start-0x80000000> -800000cc: 00028e63 beqz t0,800000e8 -800000d0: 10529073 csrw stvec,t0 -800000d4: 0000b2b7 lui t0,0xb -800000d8: 10928293 addi t0,t0,265 # b109 <_start-0x7fff4ef7> -800000dc: 30229073 csrw medeleg,t0 -800000e0: 30202373 csrr t1,medeleg -800000e4: f4629ce3 bne t0,t1,8000003c -800000e8: 30005073 csrwi mstatus,0 -800000ec: 00000297 auipc t0,0x0 -800000f0: 01428293 addi t0,t0,20 # 80000100 -800000f4: 34129073 csrw mepc,t0 -800000f8: f1402573 csrr a0,mhartid -800000fc: 30200073 mret - -80000100 : -80000100: 00000093 li ra,0 -80000104: 00000113 li sp,0 -80000108: 0220bf33 mulhu t5,ra,sp -8000010c: 00000e93 li t4,0 -80000110: 00200193 li gp,2 -80000114: 4bdf1a63 bne t5,t4,800005c8 - -80000118 : -80000118: 00100093 li ra,1 -8000011c: 00100113 li sp,1 -80000120: 0220bf33 mulhu t5,ra,sp -80000124: 00000e93 li t4,0 -80000128: 00300193 li gp,3 -8000012c: 49df1e63 bne t5,t4,800005c8 - -80000130 : -80000130: 00300093 li ra,3 -80000134: 00700113 li sp,7 -80000138: 0220bf33 mulhu t5,ra,sp -8000013c: 00000e93 li t4,0 -80000140: 00400193 li gp,4 -80000144: 49df1263 bne t5,t4,800005c8 - -80000148 : -80000148: 00000093 li ra,0 -8000014c: ffff8137 lui sp,0xffff8 -80000150: 0220bf33 mulhu t5,ra,sp -80000154: 00000e93 li t4,0 -80000158: 00500193 li gp,5 -8000015c: 47df1663 bne t5,t4,800005c8 - -80000160 : -80000160: 800000b7 lui ra,0x80000 -80000164: 00000113 li sp,0 -80000168: 0220bf33 mulhu t5,ra,sp -8000016c: 00000e93 li t4,0 -80000170: 00600193 li gp,6 -80000174: 45df1a63 bne t5,t4,800005c8 - -80000178 : -80000178: 800000b7 lui ra,0x80000 -8000017c: ffff8137 lui sp,0xffff8 -80000180: 0220bf33 mulhu t5,ra,sp -80000184: 7fffceb7 lui t4,0x7fffc -80000188: 00700193 li gp,7 -8000018c: 43df1e63 bne t5,t4,800005c8 - -80000190 : -80000190: aaaab0b7 lui ra,0xaaaab -80000194: aab08093 addi ra,ra,-1365 # aaaaaaab <_end+0x2aaa8aab> -80000198: 00030137 lui sp,0x30 -8000019c: e7d10113 addi sp,sp,-387 # 2fe7d <_start-0x7ffd0183> -800001a0: 0220bf33 mulhu t5,ra,sp -800001a4: 00020eb7 lui t4,0x20 -800001a8: efee8e93 addi t4,t4,-258 # 1fefe <_start-0x7ffe0102> -800001ac: 01e00193 li gp,30 -800001b0: 41df1c63 bne t5,t4,800005c8 - -800001b4 : -800001b4: 000300b7 lui ra,0x30 -800001b8: e7d08093 addi ra,ra,-387 # 2fe7d <_start-0x7ffd0183> -800001bc: aaaab137 lui sp,0xaaaab -800001c0: aab10113 addi sp,sp,-1365 # aaaaaaab <_end+0x2aaa8aab> -800001c4: 0220bf33 mulhu t5,ra,sp -800001c8: 00020eb7 lui t4,0x20 -800001cc: efee8e93 addi t4,t4,-258 # 1fefe <_start-0x7ffe0102> -800001d0: 01f00193 li gp,31 -800001d4: 3fdf1a63 bne t5,t4,800005c8 - -800001d8 : -800001d8: ff0000b7 lui ra,0xff000 -800001dc: ff000137 lui sp,0xff000 -800001e0: 0220bf33 mulhu t5,ra,sp -800001e4: fe010eb7 lui t4,0xfe010 -800001e8: 02000193 li gp,32 -800001ec: 3ddf1e63 bne t5,t4,800005c8 - -800001f0 : -800001f0: fff00093 li ra,-1 -800001f4: fff00113 li sp,-1 -800001f8: 0220bf33 mulhu t5,ra,sp -800001fc: ffe00e93 li t4,-2 -80000200: 02100193 li gp,33 -80000204: 3ddf1263 bne t5,t4,800005c8 - -80000208 : -80000208: fff00093 li ra,-1 -8000020c: 00100113 li sp,1 -80000210: 0220bf33 mulhu t5,ra,sp -80000214: 00000e93 li t4,0 -80000218: 02200193 li gp,34 -8000021c: 3bdf1663 bne t5,t4,800005c8 - -80000220 : -80000220: 00100093 li ra,1 -80000224: fff00113 li sp,-1 -80000228: 0220bf33 mulhu t5,ra,sp -8000022c: 00000e93 li t4,0 -80000230: 02300193 li gp,35 -80000234: 39df1a63 bne t5,t4,800005c8 - -80000238 : -80000238: 00d000b7 lui ra,0xd00 -8000023c: 00b00137 lui sp,0xb00 -80000240: 0220b0b3 mulhu ra,ra,sp -80000244: 00009eb7 lui t4,0x9 -80000248: f00e8e93 addi t4,t4,-256 # 8f00 <_start-0x7fff7100> -8000024c: 00800193 li gp,8 -80000250: 37d09c63 bne ra,t4,800005c8 - -80000254 : -80000254: 00e000b7 lui ra,0xe00 -80000258: 00b00137 lui sp,0xb00 -8000025c: 0220b133 mulhu sp,ra,sp -80000260: 0000aeb7 lui t4,0xa -80000264: a00e8e93 addi t4,t4,-1536 # 9a00 <_start-0x7fff6600> -80000268: 00900193 li gp,9 -8000026c: 35d11e63 bne sp,t4,800005c8 - -80000270 : -80000270: 00d000b7 lui ra,0xd00 -80000274: 0210b0b3 mulhu ra,ra,ra -80000278: 0000beb7 lui t4,0xb -8000027c: 900e8e93 addi t4,t4,-1792 # a900 <_start-0x7fff5700> -80000280: 00a00193 li gp,10 -80000284: 35d09263 bne ra,t4,800005c8 - -80000288 : -80000288: 00000213 li tp,0 -8000028c: 00d000b7 lui ra,0xd00 -80000290: 00b00137 lui sp,0xb00 -80000294: 0220bf33 mulhu t5,ra,sp -80000298: 000f0313 mv t1,t5 -8000029c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -800002a0: 00200293 li t0,2 -800002a4: fe5214e3 bne tp,t0,8000028c -800002a8: 00009eb7 lui t4,0x9 -800002ac: f00e8e93 addi t4,t4,-256 # 8f00 <_start-0x7fff7100> -800002b0: 00b00193 li gp,11 -800002b4: 31d31a63 bne t1,t4,800005c8 - -800002b8 : -800002b8: 00000213 li tp,0 -800002bc: 00e000b7 lui ra,0xe00 -800002c0: 00b00137 lui sp,0xb00 -800002c4: 0220bf33 mulhu t5,ra,sp -800002c8: 00000013 nop -800002cc: 000f0313 mv t1,t5 -800002d0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -800002d4: 00200293 li t0,2 -800002d8: fe5212e3 bne tp,t0,800002bc -800002dc: 0000aeb7 lui t4,0xa -800002e0: a00e8e93 addi t4,t4,-1536 # 9a00 <_start-0x7fff6600> -800002e4: 00c00193 li gp,12 -800002e8: 2fd31063 bne t1,t4,800005c8 - -800002ec : -800002ec: 00000213 li tp,0 -800002f0: 00f000b7 lui ra,0xf00 -800002f4: 00b00137 lui sp,0xb00 -800002f8: 0220bf33 mulhu t5,ra,sp -800002fc: 00000013 nop -80000300: 00000013 nop -80000304: 000f0313 mv t1,t5 -80000308: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -8000030c: 00200293 li t0,2 -80000310: fe5210e3 bne tp,t0,800002f0 -80000314: 0000aeb7 lui t4,0xa -80000318: 500e8e93 addi t4,t4,1280 # a500 <_start-0x7fff5b00> -8000031c: 00d00193 li gp,13 -80000320: 2bd31463 bne t1,t4,800005c8 - -80000324 : -80000324: 00000213 li tp,0 -80000328: 00d000b7 lui ra,0xd00 -8000032c: 00b00137 lui sp,0xb00 -80000330: 0220bf33 mulhu t5,ra,sp -80000334: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000338: 00200293 li t0,2 -8000033c: fe5216e3 bne tp,t0,80000328 -80000340: 00009eb7 lui t4,0x9 -80000344: f00e8e93 addi t4,t4,-256 # 8f00 <_start-0x7fff7100> -80000348: 00e00193 li gp,14 -8000034c: 27df1e63 bne t5,t4,800005c8 - -80000350 : -80000350: 00000213 li tp,0 -80000354: 00e000b7 lui ra,0xe00 -80000358: 00b00137 lui sp,0xb00 -8000035c: 00000013 nop -80000360: 0220bf33 mulhu t5,ra,sp -80000364: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000368: 00200293 li t0,2 -8000036c: fe5214e3 bne tp,t0,80000354 -80000370: 0000aeb7 lui t4,0xa -80000374: a00e8e93 addi t4,t4,-1536 # 9a00 <_start-0x7fff6600> -80000378: 00f00193 li gp,15 -8000037c: 25df1663 bne t5,t4,800005c8 - -80000380 : -80000380: 00000213 li tp,0 -80000384: 00f000b7 lui ra,0xf00 -80000388: 00b00137 lui sp,0xb00 -8000038c: 00000013 nop -80000390: 00000013 nop -80000394: 0220bf33 mulhu t5,ra,sp -80000398: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -8000039c: 00200293 li t0,2 -800003a0: fe5212e3 bne tp,t0,80000384 -800003a4: 0000aeb7 lui t4,0xa -800003a8: 500e8e93 addi t4,t4,1280 # a500 <_start-0x7fff5b00> -800003ac: 01000193 li gp,16 -800003b0: 21df1c63 bne t5,t4,800005c8 - -800003b4 : -800003b4: 00000213 li tp,0 -800003b8: 00d000b7 lui ra,0xd00 -800003bc: 00000013 nop -800003c0: 00b00137 lui sp,0xb00 -800003c4: 0220bf33 mulhu t5,ra,sp -800003c8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -800003cc: 00200293 li t0,2 -800003d0: fe5214e3 bne tp,t0,800003b8 -800003d4: 00009eb7 lui t4,0x9 -800003d8: f00e8e93 addi t4,t4,-256 # 8f00 <_start-0x7fff7100> -800003dc: 01100193 li gp,17 -800003e0: 1fdf1463 bne t5,t4,800005c8 - -800003e4 : -800003e4: 00000213 li tp,0 -800003e8: 00e000b7 lui ra,0xe00 -800003ec: 00000013 nop -800003f0: 00b00137 lui sp,0xb00 -800003f4: 00000013 nop -800003f8: 0220bf33 mulhu t5,ra,sp -800003fc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000400: 00200293 li t0,2 -80000404: fe5212e3 bne tp,t0,800003e8 -80000408: 0000aeb7 lui t4,0xa -8000040c: a00e8e93 addi t4,t4,-1536 # 9a00 <_start-0x7fff6600> -80000410: 01200193 li gp,18 -80000414: 1bdf1a63 bne t5,t4,800005c8 - -80000418 : -80000418: 00000213 li tp,0 -8000041c: 00f000b7 lui ra,0xf00 -80000420: 00000013 nop -80000424: 00000013 nop -80000428: 00b00137 lui sp,0xb00 -8000042c: 0220bf33 mulhu t5,ra,sp -80000430: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000434: 00200293 li t0,2 -80000438: fe5212e3 bne tp,t0,8000041c -8000043c: 0000aeb7 lui t4,0xa -80000440: 500e8e93 addi t4,t4,1280 # a500 <_start-0x7fff5b00> -80000444: 01300193 li gp,19 -80000448: 19df1063 bne t5,t4,800005c8 - -8000044c : -8000044c: 00000213 li tp,0 -80000450: 00b00137 lui sp,0xb00 -80000454: 00d000b7 lui ra,0xd00 -80000458: 0220bf33 mulhu t5,ra,sp -8000045c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000460: 00200293 li t0,2 -80000464: fe5216e3 bne tp,t0,80000450 -80000468: 00009eb7 lui t4,0x9 -8000046c: f00e8e93 addi t4,t4,-256 # 8f00 <_start-0x7fff7100> -80000470: 01400193 li gp,20 -80000474: 15df1a63 bne t5,t4,800005c8 - -80000478 : -80000478: 00000213 li tp,0 -8000047c: 00b00137 lui sp,0xb00 -80000480: 00e000b7 lui ra,0xe00 -80000484: 00000013 nop -80000488: 0220bf33 mulhu t5,ra,sp -8000048c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000490: 00200293 li t0,2 -80000494: fe5214e3 bne tp,t0,8000047c -80000498: 0000aeb7 lui t4,0xa -8000049c: a00e8e93 addi t4,t4,-1536 # 9a00 <_start-0x7fff6600> -800004a0: 01500193 li gp,21 -800004a4: 13df1263 bne t5,t4,800005c8 - -800004a8 : -800004a8: 00000213 li tp,0 -800004ac: 00b00137 lui sp,0xb00 -800004b0: 00f000b7 lui ra,0xf00 -800004b4: 00000013 nop -800004b8: 00000013 nop -800004bc: 0220bf33 mulhu t5,ra,sp -800004c0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -800004c4: 00200293 li t0,2 -800004c8: fe5212e3 bne tp,t0,800004ac -800004cc: 0000aeb7 lui t4,0xa -800004d0: 500e8e93 addi t4,t4,1280 # a500 <_start-0x7fff5b00> -800004d4: 01600193 li gp,22 -800004d8: 0fdf1863 bne t5,t4,800005c8 - -800004dc : -800004dc: 00000213 li tp,0 -800004e0: 00b00137 lui sp,0xb00 -800004e4: 00000013 nop -800004e8: 00d000b7 lui ra,0xd00 -800004ec: 0220bf33 mulhu t5,ra,sp -800004f0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -800004f4: 00200293 li t0,2 -800004f8: fe5214e3 bne tp,t0,800004e0 -800004fc: 00009eb7 lui t4,0x9 -80000500: f00e8e93 addi t4,t4,-256 # 8f00 <_start-0x7fff7100> -80000504: 01700193 li gp,23 -80000508: 0ddf1063 bne t5,t4,800005c8 - -8000050c : -8000050c: 00000213 li tp,0 -80000510: 00b00137 lui sp,0xb00 -80000514: 00000013 nop -80000518: 00e000b7 lui ra,0xe00 -8000051c: 00000013 nop -80000520: 0220bf33 mulhu t5,ra,sp -80000524: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -80000528: 00200293 li t0,2 -8000052c: fe5212e3 bne tp,t0,80000510 -80000530: 0000aeb7 lui t4,0xa -80000534: a00e8e93 addi t4,t4,-1536 # 9a00 <_start-0x7fff6600> -80000538: 01800193 li gp,24 -8000053c: 09df1663 bne t5,t4,800005c8 - -80000540 : -80000540: 00000213 li tp,0 -80000544: 00b00137 lui sp,0xb00 -80000548: 00000013 nop -8000054c: 00000013 nop -80000550: 00f000b7 lui ra,0xf00 -80000554: 0220bf33 mulhu t5,ra,sp -80000558: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> -8000055c: 00200293 li t0,2 -80000560: fe5212e3 bne tp,t0,80000544 -80000564: 0000aeb7 lui t4,0xa -80000568: 500e8e93 addi t4,t4,1280 # a500 <_start-0x7fff5b00> -8000056c: 01900193 li gp,25 -80000570: 05df1c63 bne t5,t4,800005c8 - -80000574 : -80000574: 7c0000b7 lui ra,0x7c000 -80000578: 02103133 mulhu sp,zero,ra -8000057c: 00000e93 li t4,0 -80000580: 01a00193 li gp,26 -80000584: 05d11263 bne sp,t4,800005c8 - -80000588 : -80000588: 800000b7 lui ra,0x80000 -8000058c: 0200b133 mulhu sp,ra,zero -80000590: 00000e93 li t4,0 -80000594: 01b00193 li gp,27 -80000598: 03d11863 bne sp,t4,800005c8 - -8000059c : -8000059c: 020030b3 mulhu ra,zero,zero -800005a0: 00000e93 li t4,0 -800005a4: 01c00193 li gp,28 -800005a8: 03d09063 bne ra,t4,800005c8 - -800005ac : -800005ac: 021000b7 lui ra,0x2100 -800005b0: 02200137 lui sp,0x2200 -800005b4: 0220b033 mulhu zero,ra,sp -800005b8: 00000e93 li t4,0 -800005bc: 01d00193 li gp,29 -800005c0: 01d01463 bne zero,t4,800005c8 -800005c4: 00301c63 bne zero,gp,800005dc - -800005c8 : -800005c8: 0ff0000f fence -800005cc: 00018063 beqz gp,800005cc -800005d0: 00119193 slli gp,gp,0x1 -800005d4: 0011e193 ori gp,gp,1 -800005d8: 00000073 ecall - -800005dc : -800005dc: 0ff0000f fence -800005e0: 00100193 li gp,1 -800005e4: 00000073 ecall -800005e8: c0001073 unimp -800005ec: 0000 unimp -800005ee: 0000 unimp -800005f0: 0000 unimp -800005f2: 0000 unimp -800005f4: 0000 unimp -800005f6: 0000 unimp -800005f8: 0000 unimp -800005fa: 0000 unimp -800005fc: 0000 unimp -800005fe: 0000 unimp -80000600: 0000 unimp -80000602: 0000 unimp diff --git a/benchmarks/riscv_tests/rv32um-p-mulhu.hex b/benchmarks/riscv_tests/rv32um-p-mulhu.hex deleted file mode 100644 index 55359540..00000000 --- a/benchmarks/riscv_tests/rv32um-p-mulhu.hex +++ /dev/null @@ -1,101 +0,0 @@ -:0200000480007A -:100000006F00C004732F2034930F8000630AFF0336 -:10001000930F90006306FF03930FB0006302FF038A -:10002000170F0080130F0FFE63040F0067000F000F -:10003000732F203463540F006F004000136E9E53E3 -:10004000171F00002320CFFD6FF09FFF732540F1A5 -:100050006310050073251030635805000F00F00F82 -:10006000130E100073000000130E00009702000032 -:10007000938282F973905230735020307350303035 -:1000800073504030970200809382C2F7638C020065 -:10009000739052109302B01A739022307323203061 -:1000A000E39E62F873500030970200009382420191 -:1000B00073901234732540F17300203093000000D8 -:1000C00013010000B3B12002930E0000130E2000B4 -:1000D000639AD14B9300100013011000B3B12002BA -:1000E000930E0000130E3000639ED1499300300040 -:1000F00013017000B3B12002930E0000130E4000F4 -:100100006392D149930000003781FFFFB3B1200211 -:10011000930E0000130E50006396D147B700008085 -:1001200013010000B3B12002930E0000130E600013 -:10013000639AD145B70000803781FFFFB3B1200239 -:10014000B7CEFF7F130E7000639ED143B7B0AAAA4B -:100150009380B0AA370103001301D1E7B3B12002A5 -:10016000B70E0200938EEEEF130EE001639CD141B7 -:10017000B70003009380D0E737B1AAAA1301B1AA50 -:10018000B3B12002B70E0200938EEEEF130EF00112 -:10019000639AD13FB70000FF370100FFB3B12002DF -:1001A000B70E01FE130E0002639ED13D9300F0FFD7 -:1001B0001301F0FFB3B12002930EE0FF130E100203 -:1001C0006392D13D9300F0FF13011000B3B1200200 -:1001D000930E0000130E20026396D13B9300100093 -:1001E0001301F0FFB3B12002930E0000130E300292 -:1001F000639AD139B700D0003701B000B3B0200204 -:10020000B79E0000938E0EF0130E8000639CD037D3 -:10021000B700E0003701B00033B12002B7AE0000F4 -:10022000938E0EA0130E9000631ED135B700D00040 -:10023000B3B01002B7BE0000938E0E90130EA00054 -:100240006392D03513020000B700D0003701B00030 -:10025000B3B12002138301001302120093022000A5 -:10026000E31452FEB79E0000938E0EF0130EB00002 -:10027000631AD33113020000B700E0003701B00069 -:10028000B3B1200213000000138301001302120017 -:1002900093022000E31252FEB7AE0000938E0EA030 -:1002A000130EC0006310D32F13020000B700F0003C -:1002B0003701B000B3B120021300000013000000AA -:1002C000138301001302120093022000E31052FE78 -:1002D000B7AE0000938E0E50130ED0006314D32BD4 -:1002E00013020000B700D0003701B000B3B1200204 -:1002F0001302120093022000E31652FEB79E000084 -:10030000938E0EF0130EE000639ED12713020000BF -:10031000B700E0003701B00013000000B3B12002C5 -:100320001302120093022000E31452FEB7AE000045 -:10033000938E0EA0130EF0006396D12513020000D9 -:10034000B700F0003701B0001300000013000000F8 -:10035000B3B120021302120093022000E31252FEF6 -:10036000B7AE0000938E0E50130E0001639CD12196 -:1003700013020000B700D000130000003701B000E6 -:10038000B3B120021302120093022000E31452FEC4 -:10039000B79E0000938E0EF0130E10016394D11FD0 -:1003A00013020000B700E000130000003701B000A6 -:1003B00013000000B3B120021302120093022000C8 -:1003C000E31252FEB7AE0000938E0EA0130E200172 -:1003D000639AD11B13020000B700F0001300000065 -:1003E000130000003701B000B3B120021302120065 -:1003F00093022000E31252FEB7AE0000938E0E501F -:10040000130E30016390D119130200003701B000C0 -:10041000B700D000B3B120021302120093022000F3 -:10042000E31652FEB79E0000938E0EF0130E4001AD -:10043000639AD115130200003701B000B700E00045 -:1004400013000000B3B12002130212009302200037 -:10045000E31452FEB7AE0000938E0EA0130E5001AF -:100460006392D113130200003701B000B700F0000F -:100470001300000013000000B3B1200213021200A9 -:1004800093022000E31252FEB7AE0000938E0E508E -:10049000130E60016398D10F130200003701B00002 -:1004A00013000000B700D000B3B120021302120005 -:1004B00093022000E31452FEB79E0000938E0EF0CC -:1004C000130E70016390D10D130200003701B000CC -:1004D00013000000B700E00013000000B3B12002D9 -:1004E0001302120093022000E31252FEB7AE000086 -:1004F000938E0EA0130E80016396D10913020000A3 -:100500003701B0001300000013000000B700F00036 -:10051000B3B120021302120093022000E31252FE34 -:10052000B7AE0000938E0E50130E9001639CD10560 -:10053000B700007C33311002930E0000130EA001AF -:100540006312D105B700008033B10002930E0000A2 -:10055000130EB0016318D103B3300002930E0000F4 -:10056000130EC0016390D003B700100237012002C0 -:1005700033B02002930E0000130ED0016314D0019B -:10058000631CC0010F00F00F63000E00131E1E005D -:10059000136E1E00730000000F00F00F130E10000A -:1005A00073000000731000C0000000000000000095 -:1005B000000000000000000000000000000000003B -:0405C0000000000037 -:1010000000000000000000000000000000000000E0 -:1010100000000000000000000000000000000000D0 -:1010200000000000000000000000000000000000C0 -:1010300000000000000000000000000000000000B0 -:081040000000000000000000A8 -:040000058000200057 -:00000001FF diff --git a/benchmarks/riscv_tests/rv32um-p-rem.dump b/benchmarks/riscv_tests/rv32um-p-rem.dump deleted file mode 100644 index 67bbe86f..00000000 --- a/benchmarks/riscv_tests/rv32um-p-rem.dump +++ /dev/null @@ -1,167 +0,0 @@ - -rv32um-p-rem: file format elf32-littleriscv - - -Disassembly of section .text.init: - -80000000 <_start>: -80000000: 04c0006f j 8000004c - -80000004 : -80000004: 34202f73 csrr t5,mcause -80000008: 00800f93 li t6,8 -8000000c: 03ff0a63 beq t5,t6,80000040 -80000010: 00900f93 li t6,9 -80000014: 03ff0663 beq t5,t6,80000040 -80000018: 00b00f93 li t6,11 -8000001c: 03ff0263 beq t5,t6,80000040 -80000020: 80000f17 auipc t5,0x80000 -80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> -80000028: 000f0463 beqz t5,80000030 -8000002c: 000f0067 jr t5 -80000030: 34202f73 csrr t5,mcause -80000034: 000f5463 bgez t5,8000003c -80000038: 0040006f j 8000003c - -8000003c : -8000003c: 5391e193 ori gp,gp,1337 - -80000040 : -80000040: 00001f17 auipc t5,0x1 -80000044: fc3f2023 sw gp,-64(t5) # 80001000 -80000048: ff9ff06f j 80000040 - -8000004c : -8000004c: f1402573 csrr a0,mhartid -80000050: 00051063 bnez a0,80000050 -80000054: 00000297 auipc t0,0x0 -80000058: 01028293 addi t0,t0,16 # 80000064 -8000005c: 30529073 csrw mtvec,t0 -80000060: 18005073 csrwi satp,0 -80000064: 00000297 auipc t0,0x0 -80000068: 02028293 addi t0,t0,32 # 80000084 -8000006c: 30529073 csrw mtvec,t0 -80000070: 800002b7 lui t0,0x80000 -80000074: fff28293 addi t0,t0,-1 # 7fffffff <_end+0xffffdfff> -80000078: 3b029073 csrw pmpaddr0,t0 -8000007c: 01f00293 li t0,31 -80000080: 3a029073 csrw pmpcfg0,t0 -80000084: 00000297 auipc t0,0x0 -80000088: 01828293 addi t0,t0,24 # 8000009c -8000008c: 30529073 csrw mtvec,t0 -80000090: 30205073 csrwi medeleg,0 -80000094: 30305073 csrwi mideleg,0 -80000098: 30405073 csrwi mie,0 -8000009c: 00000193 li gp,0 -800000a0: 00000297 auipc t0,0x0 -800000a4: f6428293 addi t0,t0,-156 # 80000004 -800000a8: 30529073 csrw mtvec,t0 -800000ac: 00100513 li a0,1 -800000b0: 01f51513 slli a0,a0,0x1f -800000b4: 00054863 bltz a0,800000c4 -800000b8: 0ff0000f fence -800000bc: 00100193 li gp,1 -800000c0: 00000073 ecall -800000c4: 80000297 auipc t0,0x80000 -800000c8: f3c28293 addi t0,t0,-196 # 0 <_start-0x80000000> -800000cc: 00028e63 beqz t0,800000e8 -800000d0: 10529073 csrw stvec,t0 -800000d4: 0000b2b7 lui t0,0xb -800000d8: 10928293 addi t0,t0,265 # b109 <_start-0x7fff4ef7> -800000dc: 30229073 csrw medeleg,t0 -800000e0: 30202373 csrr t1,medeleg -800000e4: f4629ce3 bne t0,t1,8000003c -800000e8: 30005073 csrwi mstatus,0 -800000ec: 00000297 auipc t0,0x0 -800000f0: 01428293 addi t0,t0,20 # 80000100 -800000f4: 34129073 csrw mepc,t0 -800000f8: f1402573 csrr a0,mhartid -800000fc: 30200073 mret - -80000100 : -80000100: 01400093 li ra,20 -80000104: 00600113 li sp,6 -80000108: 0220ef33 rem t5,ra,sp -8000010c: 00200e93 li t4,2 -80000110: 00200193 li gp,2 -80000114: 0ddf1463 bne t5,t4,800001dc - -80000118 : -80000118: fec00093 li ra,-20 -8000011c: 00600113 li sp,6 -80000120: 0220ef33 rem t5,ra,sp -80000124: ffe00e93 li t4,-2 -80000128: 00300193 li gp,3 -8000012c: 0bdf1863 bne t5,t4,800001dc - -80000130 : -80000130: 01400093 li ra,20 -80000134: ffa00113 li sp,-6 -80000138: 0220ef33 rem t5,ra,sp -8000013c: 00200e93 li t4,2 -80000140: 00400193 li gp,4 -80000144: 09df1c63 bne t5,t4,800001dc - -80000148 : -80000148: fec00093 li ra,-20 -8000014c: ffa00113 li sp,-6 -80000150: 0220ef33 rem t5,ra,sp -80000154: ffe00e93 li t4,-2 -80000158: 00500193 li gp,5 -8000015c: 09df1063 bne t5,t4,800001dc - -80000160 : -80000160: 800000b7 lui ra,0x80000 -80000164: 00100113 li sp,1 -80000168: 0220ef33 rem t5,ra,sp -8000016c: 00000e93 li t4,0 -80000170: 00600193 li gp,6 -80000174: 07df1463 bne t5,t4,800001dc - -80000178 : -80000178: 800000b7 lui ra,0x80000 -8000017c: fff00113 li sp,-1 -80000180: 0220ef33 rem t5,ra,sp -80000184: 00000e93 li t4,0 -80000188: 00700193 li gp,7 -8000018c: 05df1863 bne t5,t4,800001dc - -80000190 : -80000190: 800000b7 lui ra,0x80000 -80000194: 00000113 li sp,0 -80000198: 0220ef33 rem t5,ra,sp -8000019c: 80000eb7 lui t4,0x80000 -800001a0: 00800193 li gp,8 -800001a4: 03df1c63 bne t5,t4,800001dc - -800001a8 : -800001a8: 00100093 li ra,1 -800001ac: 00000113 li sp,0 -800001b0: 0220ef33 rem t5,ra,sp -800001b4: 00100e93 li t4,1 -800001b8: 00900193 li gp,9 -800001bc: 03df1063 bne t5,t4,800001dc - -800001c0 : -800001c0: 00000093 li ra,0 -800001c4: 00000113 li sp,0 -800001c8: 0220ef33 rem t5,ra,sp -800001cc: 00000e93 li t4,0 -800001d0: 00a00193 li gp,10 -800001d4: 01df1463 bne t5,t4,800001dc -800001d8: 00301c63 bne zero,gp,800001f0 - -800001dc : -800001dc: 0ff0000f fence -800001e0: 00018063 beqz gp,800001e0 -800001e4: 00119193 slli gp,gp,0x1 -800001e8: 0011e193 ori gp,gp,1 -800001ec: 00000073 ecall - -800001f0 : -800001f0: 0ff0000f fence -800001f4: 00100193 li gp,1 -800001f8: 00000073 ecall -800001fc: c0001073 unimp -80000200: 0000 unimp -80000202: 0000 unimp diff --git a/benchmarks/riscv_tests/rv32um-p-rem.hex b/benchmarks/riscv_tests/rv32um-p-rem.hex deleted file mode 100644 index f65f890b..00000000 --- a/benchmarks/riscv_tests/rv32um-p-rem.hex +++ /dev/null @@ -1,37 +0,0 @@ -:0200000480007A -:100000006F00C004732F2034930F8000630AFF0336 -:10001000930F90006306FF03930FB0006302FF038A -:10002000170F0080130F0FFE63040F0067000F000F -:10003000732F203463540F006F004000136E9E53E3 -:10004000171F00002320CFFD6FF09FFF732540F1A5 -:100050006310050073251030635805000F00F00F82 -:10006000130E100073000000130E00009702000032 -:10007000938282F973905230735020307350303035 -:1000800073504030970200809382C2F7638C020065 -:10009000739052109302B01A739022307323203061 -:1000A000E39E62F873500030970200009382420191 -:1000B00073901234732540F1730020309300400197 -:1000C00013016000B3E12002930E2000130E200004 -:1000D0006394D10D9300C0FE13016000B3E12002D0 -:1000E000930EE0FF130E30006398D10B9300400194 -:1000F0001301A0FFB3E12002930E2000130E400075 -:10010000639CD1099300C0FE1301A0FFB3E120025C -:10011000930EE0FF130E50006390D109930000008E -:1001200013011000B3E12002930E0000130E6000D3 -:100130006394D107930000001301F0FFB3E12002A4 -:10014000930E0000130E70006398D1059300000019 -:1001500013010000B3E12002930E0000130E800093 -:10016000639CD1039300100013010000B3E120024F -:10017000930E1000130E90006390D10393000000C3 -:1001800013010000B3E12002930E0000130EA00043 -:100190006394D101631CC0010F00F00F63000E00D7 -:1001A000131E1E00136E1E00730000000F00F00FE0 -:1001B000130E100073000000731000C00000000058 -:0401C000000000003B -:1010000000000000000000000000000000000000E0 -:1010100000000000000000000000000000000000D0 -:1010200000000000000000000000000000000000C0 -:1010300000000000000000000000000000000000B0 -:081040000000000000000000A8 -:040000058000200057 -:00000001FF diff --git a/benchmarks/riscv_tests/rv32um-p-remu.dump b/benchmarks/riscv_tests/rv32um-p-remu.dump deleted file mode 100644 index c6cecce4..00000000 --- a/benchmarks/riscv_tests/rv32um-p-remu.dump +++ /dev/null @@ -1,167 +0,0 @@ - -rv32um-p-remu: file format elf32-littleriscv - - -Disassembly of section .text.init: - -80000000 <_start>: -80000000: 04c0006f j 8000004c - -80000004 : -80000004: 34202f73 csrr t5,mcause -80000008: 00800f93 li t6,8 -8000000c: 03ff0a63 beq t5,t6,80000040 -80000010: 00900f93 li t6,9 -80000014: 03ff0663 beq t5,t6,80000040 -80000018: 00b00f93 li t6,11 -8000001c: 03ff0263 beq t5,t6,80000040 -80000020: 80000f17 auipc t5,0x80000 -80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> -80000028: 000f0463 beqz t5,80000030 -8000002c: 000f0067 jr t5 -80000030: 34202f73 csrr t5,mcause -80000034: 000f5463 bgez t5,8000003c -80000038: 0040006f j 8000003c - -8000003c : -8000003c: 5391e193 ori gp,gp,1337 - -80000040 : -80000040: 00001f17 auipc t5,0x1 -80000044: fc3f2023 sw gp,-64(t5) # 80001000 -80000048: ff9ff06f j 80000040 - -8000004c : -8000004c: f1402573 csrr a0,mhartid -80000050: 00051063 bnez a0,80000050 -80000054: 00000297 auipc t0,0x0 -80000058: 01028293 addi t0,t0,16 # 80000064 -8000005c: 30529073 csrw mtvec,t0 -80000060: 18005073 csrwi satp,0 -80000064: 00000297 auipc t0,0x0 -80000068: 02028293 addi t0,t0,32 # 80000084 -8000006c: 30529073 csrw mtvec,t0 -80000070: 800002b7 lui t0,0x80000 -80000074: fff28293 addi t0,t0,-1 # 7fffffff <_end+0xffffdfff> -80000078: 3b029073 csrw pmpaddr0,t0 -8000007c: 01f00293 li t0,31 -80000080: 3a029073 csrw pmpcfg0,t0 -80000084: 00000297 auipc t0,0x0 -80000088: 01828293 addi t0,t0,24 # 8000009c -8000008c: 30529073 csrw mtvec,t0 -80000090: 30205073 csrwi medeleg,0 -80000094: 30305073 csrwi mideleg,0 -80000098: 30405073 csrwi mie,0 -8000009c: 00000193 li gp,0 -800000a0: 00000297 auipc t0,0x0 -800000a4: f6428293 addi t0,t0,-156 # 80000004 -800000a8: 30529073 csrw mtvec,t0 -800000ac: 00100513 li a0,1 -800000b0: 01f51513 slli a0,a0,0x1f -800000b4: 00054863 bltz a0,800000c4 -800000b8: 0ff0000f fence -800000bc: 00100193 li gp,1 -800000c0: 00000073 ecall -800000c4: 80000297 auipc t0,0x80000 -800000c8: f3c28293 addi t0,t0,-196 # 0 <_start-0x80000000> -800000cc: 00028e63 beqz t0,800000e8 -800000d0: 10529073 csrw stvec,t0 -800000d4: 0000b2b7 lui t0,0xb -800000d8: 10928293 addi t0,t0,265 # b109 <_start-0x7fff4ef7> -800000dc: 30229073 csrw medeleg,t0 -800000e0: 30202373 csrr t1,medeleg -800000e4: f4629ce3 bne t0,t1,8000003c -800000e8: 30005073 csrwi mstatus,0 -800000ec: 00000297 auipc t0,0x0 -800000f0: 01428293 addi t0,t0,20 # 80000100 -800000f4: 34129073 csrw mepc,t0 -800000f8: f1402573 csrr a0,mhartid -800000fc: 30200073 mret - -80000100 : -80000100: 01400093 li ra,20 -80000104: 00600113 li sp,6 -80000108: 0220ff33 remu t5,ra,sp -8000010c: 00200e93 li t4,2 -80000110: 00200193 li gp,2 -80000114: 0ddf1463 bne t5,t4,800001dc - -80000118 : -80000118: fec00093 li ra,-20 -8000011c: 00600113 li sp,6 -80000120: 0220ff33 remu t5,ra,sp -80000124: 00200e93 li t4,2 -80000128: 00300193 li gp,3 -8000012c: 0bdf1863 bne t5,t4,800001dc - -80000130 : -80000130: 01400093 li ra,20 -80000134: ffa00113 li sp,-6 -80000138: 0220ff33 remu t5,ra,sp -8000013c: 01400e93 li t4,20 -80000140: 00400193 li gp,4 -80000144: 09df1c63 bne t5,t4,800001dc - -80000148 : -80000148: fec00093 li ra,-20 -8000014c: ffa00113 li sp,-6 -80000150: 0220ff33 remu t5,ra,sp -80000154: fec00e93 li t4,-20 -80000158: 00500193 li gp,5 -8000015c: 09df1063 bne t5,t4,800001dc - -80000160 : -80000160: 800000b7 lui ra,0x80000 -80000164: 00100113 li sp,1 -80000168: 0220ff33 remu t5,ra,sp -8000016c: 00000e93 li t4,0 -80000170: 00600193 li gp,6 -80000174: 07df1463 bne t5,t4,800001dc - -80000178 : -80000178: 800000b7 lui ra,0x80000 -8000017c: fff00113 li sp,-1 -80000180: 0220ff33 remu t5,ra,sp -80000184: 80000eb7 lui t4,0x80000 -80000188: 00700193 li gp,7 -8000018c: 05df1863 bne t5,t4,800001dc - -80000190 : -80000190: 800000b7 lui ra,0x80000 -80000194: 00000113 li sp,0 -80000198: 0220ff33 remu t5,ra,sp -8000019c: 80000eb7 lui t4,0x80000 -800001a0: 00800193 li gp,8 -800001a4: 03df1c63 bne t5,t4,800001dc - -800001a8 : -800001a8: 00100093 li ra,1 -800001ac: 00000113 li sp,0 -800001b0: 0220ff33 remu t5,ra,sp -800001b4: 00100e93 li t4,1 -800001b8: 00900193 li gp,9 -800001bc: 03df1063 bne t5,t4,800001dc - -800001c0 : -800001c0: 00000093 li ra,0 -800001c4: 00000113 li sp,0 -800001c8: 0220ff33 remu t5,ra,sp -800001cc: 00000e93 li t4,0 -800001d0: 00a00193 li gp,10 -800001d4: 01df1463 bne t5,t4,800001dc -800001d8: 00301c63 bne zero,gp,800001f0 - -800001dc : -800001dc: 0ff0000f fence -800001e0: 00018063 beqz gp,800001e0 -800001e4: 00119193 slli gp,gp,0x1 -800001e8: 0011e193 ori gp,gp,1 -800001ec: 00000073 ecall - -800001f0 : -800001f0: 0ff0000f fence -800001f4: 00100193 li gp,1 -800001f8: 00000073 ecall -800001fc: c0001073 unimp -80000200: 0000 unimp -80000202: 0000 unimp diff --git a/benchmarks/riscv_tests/rv32um-p-remu.hex b/benchmarks/riscv_tests/rv32um-p-remu.hex deleted file mode 100644 index 1be01270..00000000 --- a/benchmarks/riscv_tests/rv32um-p-remu.hex +++ /dev/null @@ -1,37 +0,0 @@ -:0200000480007A -:100000006F00C004732F2034930F8000630AFF0336 -:10001000930F90006306FF03930FB0006302FF038A -:10002000170F0080130F0FFE63040F0067000F000F -:10003000732F203463540F006F004000136E9E53E3 -:10004000171F00002320CFFD6FF09FFF732540F1A5 -:100050006310050073251030635805000F00F00F82 -:10006000130E100073000000130E00009702000032 -:10007000938282F973905230735020307350303035 -:1000800073504030970200809382C2F7638C020065 -:10009000739052109302B01A739022307323203061 -:1000A000E39E62F873500030970200009382420191 -:1000B00073901234732540F1730020309300400197 -:1000C00013016000B3F12002930E2000130E2000F4 -:1000D0006394D10D9300C0FE13016000B3F12002C0 -:1000E000930E2000130E30006398D10B9300400153 -:1000F0001301A0FFB3F12002930E4001130E400044 -:10010000639CD1099300C0FE1301A0FFB3F120024C -:10011000930EC0FE130E50006390D10993000000AF -:1001200013011000B3F12002930E0000130E6000C3 -:100130006394D107930000001301F0FFB3F1200294 -:10014000930E0000130E70006398D1059300000019 -:1001500013010000B3F12002930E0000130E800083 -:10016000639CD1039300100013010000B3F120023F -:10017000930E1000130E90006390D10393000000C3 -:1001800013010000B3F12002930E0000130EA00033 -:100190006394D101631CC0010F00F00F63000E00D7 -:1001A000131E1E00136E1E00730000000F00F00FE0 -:1001B000130E100073000000731000C00000000058 -:0401C000000000003B -:1010000000000000000000000000000000000000E0 -:1010100000000000000000000000000000000000D0 -:1010200000000000000000000000000000000000C0 -:1010300000000000000000000000000000000000B0 -:081040000000000000000000A8 -:040000058000200057 -:00000001FF diff --git a/benchmarks/riscv_tests/testA.hex b/benchmarks/riscv_tests/testA.hex deleted file mode 100644 index 8bb3b24a..00000000 --- a/benchmarks/riscv_tests/testA.hex +++ /dev/null @@ -1,29 +0,0 @@ -:1000000013000000130000001300000013000000A4 -:100010001300000013000000130000009300A00074 -:100020001300000013000000130000001300000084 -:100030001300000013000000130000001301400132 -:100040001300000013000000130000001300000064 -:100050001300000013000000130000009381E00172 -:100060001300000013000000130000001300000044 -:100070001300000013000000130000003382210071 -:100080001300000013000000130000001300000024 -:100090001300000013000000130000009300A000F4 -:1000A000130140019381E00133822100130000001D -:1000B00013000000130000001300000013000000F4 -:1000C00013000000130000001300000013000000E4 -:1000D00013000000130000001300000013000000D4 -:1000E00013000000130000001300000013000000C4 -:1000F00013000000130000001300000013000000B4 -:1001000013000000130000001300000013000000A3 -:100110001300000013000000130000009302100001 -:100120001300000013000000130000001300000083 -:100130001300000013000000130000006F00000413 -:100140001300000013000000130000001300000063 -:100150001300000013000000130000001303200030 -:100160001300000013000000130000001300000043 -:100170001300000013000000130000009303300080 -:100180001300000013000000130000001300000023 -:100190001300000013000000130000009302100081 -:0C01A0006F008000130320009303300068 -:0400000540000000B7 -:00000001FF diff --git a/ci/test_driver.sh b/ci/test_driver.sh new file mode 100755 index 00000000..73e0ae78 --- /dev/null +++ b/ci/test_driver.sh @@ -0,0 +1,3 @@ +#!/bin/bash + +make -C driver/tests run \ No newline at end of file diff --git a/ci/test_opencl.sh b/ci/test_opencl.sh new file mode 100755 index 00000000..9cb23e8f --- /dev/null +++ b/ci/test_opencl.sh @@ -0,0 +1,3 @@ +#!/bin/sh + +make -C benchmarks/opencl run diff --git a/ci/test_riscv_isa.sh b/ci/test_riscv_isa.sh new file mode 100755 index 00000000..f0bc11c9 --- /dev/null +++ b/ci/test_riscv_isa.sh @@ -0,0 +1,3 @@ +#!/bin/bash + +make -C benchmarks/riscv_tests/isa run diff --git a/ci/test_runtime.sh b/ci/test_runtime.sh new file mode 100755 index 00000000..5886e1c2 --- /dev/null +++ b/ci/test_runtime.sh @@ -0,0 +1,3 @@ +#!/bin/bash + +make -C runtime/tests run diff --git a/ci/toolchain_install.sh b/ci/toolchain_install.sh new file mode 100755 index 00000000..5097444f --- /dev/null +++ b/ci/toolchain_install.sh @@ -0,0 +1,20 @@ +#!/bin/bash + +REPOSITORY=https://github.com/vortexgpgpu/vortex-toolchain-prebuilt/raw/master + +# RISCV-GNU_TOOLCHAIN + +for x in {a..o} +do + wget $REPOSITORY/riscv-gnu-toolchain/ubuntu/bionic/riscv-gnu-toolchain.tar.bz2.parta$x +done + +cat riscv-gnu-toolchain.tar.bz2.parta* > riscv-gnu-toolchain.tar.bz2 +tar -xvf riscv-gnu-toolchain.tar.bz2 +rm -f riscv-gnu-toolchain.tar.bz2* + +# VERILATOR + +wget $REPOSITORY/verilator/ubuntu/bionic/verilator.tar.bz2 +tar -xvf verilator.tar.bz2 +rm -f verilator.tar.bz2 \ No newline at end of file diff --git a/docs/Vortex.pptx b/docs/Vortex.pptx deleted file mode 100755 index 89e1128e..00000000 Binary files a/docs/Vortex.pptx and /dev/null differ diff --git a/docs/Vortex_CARRV2019.pdf b/docs/Vortex_CARRV2019.pdf deleted file mode 100755 index 59ce9fd8..00000000 Binary files a/docs/Vortex_CARRV2019.pdf and /dev/null differ diff --git a/docs/Vortex_OpenCL.pptx b/docs/Vortex_OpenCL.pptx deleted file mode 100755 index fb5e8cef..00000000 Binary files a/docs/Vortex_OpenCL.pptx and /dev/null differ diff --git a/docs/Vortex_RISCV_GPGPU.pdf b/docs/Vortex_RISCV_GPGPU.pdf deleted file mode 100755 index 84daa8c7..00000000 Binary files a/docs/Vortex_RISCV_GPGPU.pdf and /dev/null differ diff --git a/docs/Vortex_cache_diagram.pdf b/docs/Vortex_cache_diagram.pdf deleted file mode 100644 index f84d6643..00000000 --- a/docs/Vortex_cache_diagram.pdf +++ /dev/null @@ -1,63630 +0,0 @@ -%PDF-1.4 -1 0 obj -<< - /Title (_1) - /Author (tinebp) - /Producer (Concept Engineering GmbH) - /Creator (Nlview 6.6.0 2016-02-25 bk=1.3518 VDI=39 GEI=35) - /CreationDate (D:20200421013517) ->> -endobj -2 0 obj -<< - /Type /Catalog - /Pages 3 0 R - /Outlines 7 0 R - /PageMode /UseThumbs - /ViewerPreferences << /DisplayDocTitle true >> ->> -endobj -4 0 obj -<< - /Type /Font - /Subtype /Type1 - /Name /F1 - /BaseFont /Helvetica - /Encoding /MacRomanEncoding ->> -endobj -5 0 obj -<< - /ExtGState << /GS 6 0 R >> - /Font << /F1 4 0 R >> - /ColorSpace << /PCS [/Pattern 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-(snp_fwd_pop) Tj -ET -Q -3 w -1170 840 m -1180 840 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1178 839 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --92.82 2.07 Td -(core_req_valids[1..0]) Tj -ET -Q -1170 780 m -1180 780 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1178 779 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --98.39 2.07 Td -(core_req_read[0][2..0]) Tj -ET -Q -1170 800 m -1180 800 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1178 799 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --98.39 2.07 Td -(core_req_read[1][2..0]) Tj -ET -Q -1170 920 m -1180 920 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1178 919 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --99.49 2.07 Td -(core_req_write[0][2..0]) Tj -ET -Q -1170 940 m -1180 940 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1178 939 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --99.49 2.07 Td -(core_req_write[1][2..0]) Tj -ET -Q -1170 660 m -1180 660 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1178 659 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --103.95 2.07 Td -(core_req_addr[0][31..0]) Tj -ET -Q -1170 680 m -1180 680 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1178 679 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --103.95 2.07 Td -(core_req_addr[1][31..0]) Tj -ET -Q -1170 700 m -1180 700 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1178 699 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --108.96 2.07 Td -(core_req_data[0][127..0]) Tj -ET -Q -1170 720 m -1180 720 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1178 719 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --108.96 2.07 Td -(core_req_data[1][127..0]) Tj -ET -Q -1170 760 m -1180 760 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1178 759 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --76.15 2.07 Td -(core_req_rd[4..0]) Tj -ET -Q -1170 880 m -1180 880 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1178 879 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --91.16 2.07 Td -(core_req_wb[0][1..0]) Tj -ET -Q -1170 900 m -1180 900 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1178 899 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --91.16 2.07 Td -(core_req_wb[1][1..0]) Tj -ET -Q -1170 740 m -1180 740 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1178 739 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --83.38 2.07 Td -(core_req_pc[31..0]) Tj -ET -Q -1170 860 m -1180 860 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1178 859 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --113.94 2.07 Td -(core_req_warp_num[2..0]) Tj -ET -Q -1170 1000 m -1180 1000 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1178 999 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --110.6 2.07 Td -(dram_fill_rsp_addr[31..0]) Tj -ET -Q -1170 1020 m -1180 1020 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1178 1019 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --126.73 2.07 Td -(dram_fill_rsp_data[0][127..0]) Tj -ET -Q -1170 1120 m -1180 1120 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1178 1119 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --89.5 2.07 Td -(snp_req_addr[31..0]) Tj -ET -Q -1 w -1250 720 m -1240 720 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1246 719 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(core_req_full) Tj -ET -Q -1250 840 m -1240 840 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1246 839 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(core_rsp_valid) Tj -ET -Q -1250 920 m -1240 920 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1246 919 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(dram_fill_req_valid) Tj -ET -Q -1250 940 m -1240 940 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1246 939 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(dram_fill_rsp_ready) Tj -ET -Q -1250 1000 m -1240 1000 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1246 999 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(dram_wb_req_valid) Tj -ET -Q -1250 1060 m -1240 1060 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1246 1059 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(snp_req_full) Tj -ET -Q -1250 1040 m -1240 1040 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1246 1039 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(snp_fwd_valid) Tj -ET -Q -3 w -1250 820 m -1240 820 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1246 819 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(core_rsp_tid[0..0]) Tj -ET -Q -1250 800 m -1240 800 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1246 799 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(core_rsp_rd[4..0]) Tj -ET -Q -1250 880 m -1240 880 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1246 879 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(core_rsp_wb[1..0]) Tj -ET -Q -1250 860 m -1240 860 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1246 859 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(core_rsp_warp_num[2..0]) Tj -ET -Q -1250 760 m -1240 760 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1246 759 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(core_rsp_data[127..0]) Tj -ET -Q -1250 780 m -1240 780 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1246 779 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(core_rsp_pc[31..0]) Tj -ET -Q -1250 740 m -1240 740 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1246 739 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(core_rsp_addr[31..0]) Tj -ET -Q -1250 900 m -1240 900 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1246 899 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(dram_fill_req_addr[31..0]) Tj -ET -Q -1250 960 m -1240 960 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1246 959 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(dram_wb_req_addr[31..0]) Tj -ET -Q -1250 980 m -1240 980 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1246 979 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(dram_wb_req_data[0][127..0]) Tj -ET -Q -1250 1020 m -1240 1020 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1246 1019 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(snp_fwd_addr[31..0]) Tj -ET -Q -1 w -1190 640 m -1180 640 l -S -1190 1080 m -1180 1080 l -S -1190 820 m -1180 820 l -S -1190 960 m -1180 960 l -S -1190 980 m -1180 980 l -S -1190 1040 m -1180 1040 l -S -1190 1060 m -1180 1060 l -S -1190 1140 m -1180 1140 l -S -1190 1100 m -1180 1100 l -S -3 w -1190 840 m -1180 840 l -S -1190 780 m -1180 780 l -S -1190 800 m -1180 800 l -S -1190 920 m -1180 920 l -S -1190 940 m -1180 940 l -S -1190 660 m -1180 660 l -S -1190 680 m -1180 680 l -S -1190 700 m -1180 700 l -S -1190 720 m -1180 720 l -S -1190 760 m -1180 760 l -S -1190 880 m -1180 880 l -S -1190 900 m -1180 900 l -S -1190 740 m -1180 740 l -S -1190 860 m -1180 860 l -S -1190 1000 m -1180 1000 l -S -1190 1020 m -1180 1020 l -S -1190 1120 m -1180 1120 l -S -1 w -1230 720 m -1240 720 l -S -1230 840 m -1240 840 l -S -1230 920 m -1240 920 l -S -1230 940 m -1240 940 l -S -1230 1000 m -1240 1000 l -S -1230 1060 m -1240 1060 l -S -1230 1040 m -1240 1040 l -S -3 w -1230 820 m -1240 820 l -S -1230 800 m -1240 800 l -S -1230 880 m -1240 880 l -S -1230 860 m -1240 860 l -S -1230 760 m -1240 760 l -S -1230 780 m -1240 780 l -S -1230 740 m -1240 740 l -S -1230 900 m -1240 900 l -S -1230 960 m -1240 960 l -S -1230 980 m -1240 980 l -S -1230 1020 m -1240 1020 l -S -1 w -0.000 0.000 1.000 RG -0 1040 m --14 1040 l --21 1047 l -S --14 1040 m --21 1033 l -S -q -0.000 0.000 1.000 rg -1 0 0 1 -25 1056 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm --23.352 -4.308 Td -([1,3]) Tj -ET -Q -q -0.176 0.176 0.176 rg -1 0 0 1 -25 1040 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm --212.064 -4.308 Td -([2].curr_bank_dram_fill_rsp_valid:OUT0) Tj -ET -Q -3 w -4784 947 m -4791 940 l -4784 933 l -S -4770 940 m -4791 940 l -S -q -0.000 0.000 1.000 rg -1 0 0 1 4795 956 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm -0 -4.308 Td -([1-2]) Tj -ET -Q -q -0.176 0.176 0.176 rg -1 0 0 1 4795 940 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm -0 -4.308 Td -(dram_wb_req_addr[31..0]) Tj -ET -Q -1 w -0 1140 m --14 1140 l --21 1147 l -S --14 1140 m --21 1133 l -S -q -0.000 0.000 1.000 rg -1 0 0 1 -25 1156 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm --23.352 -4.308 Td -([1,3]) Tj -ET -Q -q -0.176 0.176 0.176 rg -1 0 0 1 -25 1140 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm --155.4 -4.308 Td -([2].curr_bank_snp_req:OUT0) Tj -ET -Q -3 w -4784 987 m -4791 980 l -4784 973 l -S -4770 980 m -4791 980 l -S -q -0.000 0.000 1.000 rg -1 0 0 1 4795 996 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm -0 -4.308 Td -([1-2]) Tj -ET -Q -q -0.176 0.176 0.176 rg -1 0 0 1 4795 980 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm -0 -4.308 Td -(dram_wb_req_data[0][127..0]) Tj -ET -Q -4784 1407 m -4791 1400 l -4784 1393 l -S -4770 1400 m -4791 1400 l -S -q -0.000 0.000 1.000 rg -1 0 0 1 4795 1416 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm -0 -4.308 Td -([1-2]) Tj -ET -Q -q -0.176 0.176 0.176 rg -1 0 0 1 4795 1400 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm -0 -4.308 Td -(dram_fill_req_addr[31..0]) Tj -ET -Q -q -0.000 0.000 0.000 rg -1185 1193 60 542 re -f -Q -q -0.506 0.749 0.373 rg -1180 1188 60 542 re -f -Q -1 w -0.176 0.176 0.176 RG -1180 1188 60 542 re -S -3 w -1191 1193 m -1191 1205 l -S -1185 1199 m -1197 1199 l -S -1 w -1183 1191 16 16 re -S -q -0.000 0.000 0.000 rg -1 0 0 1 1210 1186 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm --21.348 2.484 Td -([3].bank) Tj -ET -Q -q -0.176 0.176 0.176 rg -1 0 0 1 1210 1736 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm --28.344 -8.616 Td -(\(VX_bank\)) Tj -ET -Q -0.024 0.278 0.435 RG -1170 1220 m -1180 1220 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1178 1219 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --12.22 2.07 Td -(clk) Tj -ET -Q -1170 1660 m -1180 1660 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1178 1659 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --22.23 2.07 Td -(reset) Tj -ET -Q -1180 1400 m -1180 1398.34 1178.66 1397 1177 1397 c -1175.34 1397 1174 1398.34 1174 1400 c -1174 1401.66 1175.34 1403 1177 1403 c -1178.66 1403 1180 1401.66 1180 1400 c -S -1170 1400 m -1174 1400 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1174 1399 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --70.03 2.07 Td -(core_req_ready) Tj -ET -Q -1170 1540 m -1180 1540 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1178 1539 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --61.14 2.07 Td -(core_rsp_pop) Tj -ET -Q -1170 1560 m -1180 1560 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1178 1559 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --76.13 2.07 Td -(dram_fill_req_full) Tj -ET -Q -1170 1620 m -1180 1620 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1178 1619 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --83.35 2.07 Td -(dram_fill_rsp_valid) Tj -ET -Q -1170 1640 m -1180 1640 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1178 1639 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --83.37 2.07 Td -(dram_wb_req_pop) Tj -ET -Q -1170 1720 m -1180 1720 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1178 1719 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --62.25 2.07 Td -(snp_req_valid) Tj -ET -Q -1170 1680 m -1180 1680 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1178 1679 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --59.48 2.07 Td -(snp_fwd_pop) Tj -ET -Q -3 w -1170 1420 m -1180 1420 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1178 1419 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --92.82 2.07 Td -(core_req_valids[1..0]) Tj -ET -Q -1170 1360 m -1180 1360 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1178 1359 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --98.39 2.07 Td -(core_req_read[0][2..0]) Tj -ET -Q -1170 1380 m -1180 1380 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1178 1379 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --98.39 2.07 Td -(core_req_read[1][2..0]) Tj -ET -Q -1170 1500 m -1180 1500 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1178 1499 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --99.49 2.07 Td -(core_req_write[0][2..0]) Tj -ET -Q -1170 1520 m -1180 1520 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1178 1519 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --99.49 2.07 Td -(core_req_write[1][2..0]) Tj -ET -Q -1170 1240 m -1180 1240 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1178 1239 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --103.95 2.07 Td -(core_req_addr[0][31..0]) Tj -ET -Q -1170 1260 m -1180 1260 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1178 1259 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --103.95 2.07 Td -(core_req_addr[1][31..0]) Tj -ET -Q -1170 1280 m -1180 1280 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1178 1279 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --108.96 2.07 Td -(core_req_data[0][127..0]) Tj -ET -Q -1170 1300 m -1180 1300 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1178 1299 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --108.96 2.07 Td -(core_req_data[1][127..0]) Tj -ET -Q -1170 1340 m -1180 1340 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1178 1339 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --76.15 2.07 Td -(core_req_rd[4..0]) Tj -ET -Q -1170 1460 m -1180 1460 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1178 1459 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --91.16 2.07 Td -(core_req_wb[0][1..0]) Tj -ET -Q -1170 1480 m -1180 1480 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1178 1479 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --91.16 2.07 Td -(core_req_wb[1][1..0]) Tj -ET -Q -1170 1320 m -1180 1320 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1178 1319 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --83.38 2.07 Td -(core_req_pc[31..0]) Tj -ET -Q -1170 1440 m -1180 1440 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1178 1439 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --113.94 2.07 Td -(core_req_warp_num[2..0]) Tj -ET -Q -1170 1580 m -1180 1580 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1178 1579 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --110.6 2.07 Td -(dram_fill_rsp_addr[31..0]) Tj -ET -Q -1170 1600 m -1180 1600 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1178 1599 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --126.73 2.07 Td -(dram_fill_rsp_data[0][127..0]) Tj -ET -Q -1170 1700 m -1180 1700 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1178 1699 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --89.5 2.07 Td -(snp_req_addr[31..0]) Tj -ET -Q -1 w -1250 1300 m -1240 1300 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1246 1299 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(core_req_full) Tj -ET -Q -1250 1420 m -1240 1420 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1246 1419 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(core_rsp_valid) Tj -ET -Q -1250 1500 m -1240 1500 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1246 1499 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(dram_fill_req_valid) Tj -ET -Q -1250 1520 m -1240 1520 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1246 1519 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(dram_fill_rsp_ready) Tj -ET -Q -1250 1580 m -1240 1580 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1246 1579 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(dram_wb_req_valid) Tj -ET -Q -1250 1640 m -1240 1640 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1246 1639 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(snp_req_full) Tj -ET -Q -1250 1620 m -1240 1620 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1246 1619 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(snp_fwd_valid) Tj -ET -Q -3 w -1250 1400 m -1240 1400 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1246 1399 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(core_rsp_tid[0..0]) Tj -ET -Q -1250 1380 m -1240 1380 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1246 1379 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(core_rsp_rd[4..0]) Tj -ET -Q -1250 1460 m -1240 1460 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1246 1459 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(core_rsp_wb[1..0]) Tj -ET -Q -1250 1440 m -1240 1440 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1246 1439 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(core_rsp_warp_num[2..0]) Tj -ET -Q -1250 1340 m -1240 1340 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1246 1339 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(core_rsp_data[127..0]) Tj -ET -Q -1250 1360 m -1240 1360 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1246 1359 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(core_rsp_pc[31..0]) Tj -ET -Q -1250 1320 m -1240 1320 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1246 1319 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(core_rsp_addr[31..0]) Tj -ET -Q -1250 1480 m -1240 1480 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1246 1479 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(dram_fill_req_addr[31..0]) Tj -ET -Q -1250 1540 m -1240 1540 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1246 1539 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(dram_wb_req_addr[31..0]) Tj -ET -Q -1250 1560 m -1240 1560 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1246 1559 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(dram_wb_req_data[0][127..0]) Tj -ET -Q -1250 1600 m -1240 1600 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1246 1599 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(snp_fwd_addr[31..0]) Tj -ET -Q -1 w -1190 1220 m -1180 1220 l -S -1190 1660 m -1180 1660 l -S -1190 1400 m -1180 1400 l -S -1190 1540 m -1180 1540 l -S -1190 1560 m -1180 1560 l -S -1190 1620 m -1180 1620 l -S -1190 1640 m -1180 1640 l -S -1190 1720 m -1180 1720 l -S -1190 1680 m -1180 1680 l -S -3 w -1190 1420 m -1180 1420 l -S -1190 1360 m -1180 1360 l -S -1190 1380 m -1180 1380 l -S -1190 1500 m -1180 1500 l -S -1190 1520 m -1180 1520 l -S -1190 1240 m -1180 1240 l -S -1190 1260 m -1180 1260 l -S -1190 1280 m -1180 1280 l -S -1190 1300 m -1180 1300 l -S -1190 1340 m -1180 1340 l -S -1190 1460 m -1180 1460 l -S -1190 1480 m -1180 1480 l -S -1190 1320 m -1180 1320 l -S -1190 1440 m -1180 1440 l -S -1190 1580 m -1180 1580 l -S -1190 1600 m -1180 1600 l -S -1190 1700 m -1180 1700 l -S -1 w -1230 1300 m -1240 1300 l -S -1230 1420 m -1240 1420 l -S -1230 1500 m -1240 1500 l -S -1230 1520 m -1240 1520 l -S -1230 1580 m -1240 1580 l -S -1230 1640 m -1240 1640 l -S -1230 1620 m -1240 1620 l -S -3 w -1230 1400 m -1240 1400 l -S -1230 1380 m -1240 1380 l -S -1230 1460 m -1240 1460 l -S -1230 1440 m -1240 1440 l -S -1230 1340 m -1240 1340 l -S -1230 1360 m -1240 1360 l -S -1230 1320 m -1240 1320 l -S -1230 1480 m -1240 1480 l -S -1230 1540 m -1240 1540 l -S -1230 1560 m -1240 1560 l -S -1230 1600 m -1240 1600 l -S -1 w -0.000 0.000 1.000 RG -0 1620 m --14 1620 l --21 1627 l -S --14 1620 m --21 1613 l -S -q -0.000 0.000 1.000 rg -1 0 0 1 -25 1636 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm --23.352 -4.308 Td -([1,3]) Tj -ET -Q -q -0.176 0.176 0.176 rg -1 0 0 1 -25 1620 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm --212.064 -4.308 Td -([3].curr_bank_dram_fill_rsp_valid:OUT0) Tj -ET -Q -3 w -4784 1447 m -4791 1440 l -4784 1433 l -S -4770 1440 m -4791 1440 l -S -q -0.000 0.000 1.000 rg -1 0 0 1 4795 1456 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm -0 -4.308 Td -([1-2]) Tj -ET -Q -q -0.176 0.176 0.176 rg -1 0 0 1 4795 1440 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm -0 -4.308 Td -(dram_wb_req_addr[31..0]) Tj -ET -Q -1 w -0 1720 m --14 1720 l --21 1727 l -S --14 1720 m --21 1713 l -S -q -0.000 0.000 1.000 rg -1 0 0 1 -25 1736 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm --23.352 -4.308 Td -([1,3]) Tj -ET -Q -q -0.176 0.176 0.176 rg -1 0 0 1 -25 1720 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm --155.4 -4.308 Td -([3].curr_bank_snp_req:OUT0) Tj -ET -Q -3 w -4784 1487 m -4791 1480 l -4784 1473 l -S -4770 1480 m -4791 1480 l -S -q -0.000 0.000 1.000 rg -1 0 0 1 4795 1496 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm -0 -4.308 Td -([1-2]) Tj -ET -Q -q -0.176 0.176 0.176 rg -1 0 0 1 4795 1480 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm -0 -4.308 Td -(dram_wb_req_data[0][127..0]) Tj -ET -Q -1 w -0 1760 m --7 1767 l --21 1767 l --21 1753 l --7 1753 l -h S -q -0.000 0.000 0.000 rg -1 0 0 1 -25 1760 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm --83.364 -4.308 Td -(core_rsp_ready) Tj -ET -Q -q -0.000 0.000 0.000 rg -1185 1793 60 542 re -f -Q -q -0.506 0.749 0.373 rg -1180 1788 60 542 re -f -Q -0.176 0.176 0.176 RG -1180 1788 60 542 re -S -3 w -1191 1793 m -1191 1805 l -S -1185 1799 m -1197 1799 l -S -1 w -1183 1791 16 16 re -S -q -0.000 0.000 0.000 rg -1 0 0 1 1210 1786 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm --21.348 2.484 Td -([5].bank) Tj -ET -Q -q -0.176 0.176 0.176 rg -1 0 0 1 1210 2336 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm --28.344 -8.616 Td -(\(VX_bank\)) Tj -ET -Q -0.024 0.278 0.435 RG -1170 1820 m -1180 1820 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1178 1819 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --12.22 2.07 Td -(clk) Tj -ET -Q -1170 2260 m -1180 2260 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1178 2259 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --22.23 2.07 Td -(reset) Tj -ET -Q -1180 2000 m -1180 1998.34 1178.66 1997 1177 1997 c -1175.34 1997 1174 1998.34 1174 2000 c -1174 2001.66 1175.34 2003 1177 2003 c -1178.66 2003 1180 2001.66 1180 2000 c -S -1170 2000 m -1174 2000 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1174 1999 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --70.03 2.07 Td -(core_req_ready) Tj -ET -Q -1170 2140 m -1180 2140 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1178 2139 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --61.14 2.07 Td -(core_rsp_pop) Tj -ET -Q -1170 2160 m -1180 2160 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1178 2159 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --76.13 2.07 Td -(dram_fill_req_full) Tj -ET -Q -1170 2220 m -1180 2220 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1178 2219 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --83.35 2.07 Td -(dram_fill_rsp_valid) Tj -ET -Q -1170 2240 m -1180 2240 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1178 2239 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --83.37 2.07 Td -(dram_wb_req_pop) Tj -ET -Q -1170 2320 m -1180 2320 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1178 2319 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --62.25 2.07 Td -(snp_req_valid) Tj -ET -Q -1170 2280 m -1180 2280 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1178 2279 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --59.48 2.07 Td -(snp_fwd_pop) Tj -ET -Q -3 w -1170 2020 m -1180 2020 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1178 2019 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --92.82 2.07 Td -(core_req_valids[1..0]) Tj -ET -Q -1170 1960 m -1180 1960 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1178 1959 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --98.39 2.07 Td -(core_req_read[0][2..0]) Tj -ET -Q -1170 1980 m -1180 1980 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1178 1979 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --98.39 2.07 Td -(core_req_read[1][2..0]) Tj -ET -Q -1170 2100 m -1180 2100 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1178 2099 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --99.49 2.07 Td -(core_req_write[0][2..0]) Tj -ET -Q -1170 2120 m -1180 2120 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1178 2119 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --99.49 2.07 Td -(core_req_write[1][2..0]) Tj -ET -Q -1170 1840 m -1180 1840 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1178 1839 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --103.95 2.07 Td -(core_req_addr[0][31..0]) Tj -ET -Q -1170 1860 m -1180 1860 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1178 1859 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --103.95 2.07 Td -(core_req_addr[1][31..0]) Tj -ET -Q -1170 1880 m -1180 1880 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1178 1879 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --108.96 2.07 Td -(core_req_data[0][127..0]) Tj -ET -Q -1170 1900 m -1180 1900 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1178 1899 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --108.96 2.07 Td -(core_req_data[1][127..0]) Tj -ET -Q -1170 1940 m -1180 1940 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1178 1939 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --76.15 2.07 Td -(core_req_rd[4..0]) Tj -ET -Q -1170 2060 m -1180 2060 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1178 2059 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --91.16 2.07 Td -(core_req_wb[0][1..0]) Tj -ET -Q -1170 2080 m -1180 2080 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1178 2079 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --91.16 2.07 Td -(core_req_wb[1][1..0]) Tj -ET -Q -1170 1920 m -1180 1920 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1178 1919 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --83.38 2.07 Td -(core_req_pc[31..0]) Tj -ET -Q -1170 2040 m -1180 2040 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1178 2039 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --113.94 2.07 Td -(core_req_warp_num[2..0]) Tj -ET -Q -1170 2180 m -1180 2180 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1178 2179 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --110.6 2.07 Td -(dram_fill_rsp_addr[31..0]) Tj -ET -Q -1170 2200 m -1180 2200 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1178 2199 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --126.73 2.07 Td -(dram_fill_rsp_data[0][127..0]) Tj -ET -Q -1170 2300 m -1180 2300 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1178 2299 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --89.5 2.07 Td -(snp_req_addr[31..0]) Tj -ET -Q -1 w -1250 1900 m -1240 1900 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1246 1899 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(core_req_full) Tj -ET -Q -1250 2020 m -1240 2020 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1246 2019 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(core_rsp_valid) Tj -ET -Q -1250 2100 m -1240 2100 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1246 2099 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(dram_fill_req_valid) Tj -ET -Q -1250 2120 m -1240 2120 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1246 2119 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(dram_fill_rsp_ready) Tj -ET -Q -1250 2180 m -1240 2180 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1246 2179 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(dram_wb_req_valid) Tj -ET -Q -1250 2240 m -1240 2240 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1246 2239 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(snp_req_full) Tj -ET -Q -1250 2220 m -1240 2220 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1246 2219 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(snp_fwd_valid) Tj -ET -Q -3 w -1250 2000 m -1240 2000 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1246 1999 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(core_rsp_tid[0..0]) Tj -ET -Q -1250 1980 m -1240 1980 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1246 1979 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(core_rsp_rd[4..0]) Tj -ET -Q -1250 2060 m -1240 2060 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1246 2059 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(core_rsp_wb[1..0]) Tj -ET -Q -1250 2040 m -1240 2040 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1246 2039 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(core_rsp_warp_num[2..0]) Tj -ET -Q -1250 1940 m -1240 1940 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1246 1939 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(core_rsp_data[127..0]) Tj -ET -Q -1250 1960 m -1240 1960 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1246 1959 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(core_rsp_pc[31..0]) Tj -ET -Q -1250 1920 m -1240 1920 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1246 1919 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(core_rsp_addr[31..0]) Tj -ET -Q -1250 2080 m -1240 2080 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1246 2079 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(dram_fill_req_addr[31..0]) Tj -ET -Q -1250 2140 m -1240 2140 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1246 2139 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(dram_wb_req_addr[31..0]) Tj -ET -Q -1250 2160 m -1240 2160 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1246 2159 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(dram_wb_req_data[0][127..0]) Tj -ET -Q -1250 2200 m -1240 2200 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1246 2199 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(snp_fwd_addr[31..0]) Tj -ET -Q -1 w -1190 1820 m -1180 1820 l -S -1190 2260 m -1180 2260 l -S -1190 2000 m -1180 2000 l -S -1190 2140 m -1180 2140 l -S -1190 2160 m -1180 2160 l -S -1190 2220 m -1180 2220 l -S -1190 2240 m -1180 2240 l -S -1190 2320 m -1180 2320 l -S -1190 2280 m -1180 2280 l -S -3 w -1190 2020 m -1180 2020 l -S -1190 1960 m -1180 1960 l -S -1190 1980 m -1180 1980 l -S -1190 2100 m -1180 2100 l -S -1190 2120 m -1180 2120 l -S -1190 1840 m -1180 1840 l -S -1190 1860 m -1180 1860 l -S -1190 1880 m -1180 1880 l -S -1190 1900 m -1180 1900 l -S -1190 1940 m -1180 1940 l -S -1190 2060 m -1180 2060 l -S -1190 2080 m -1180 2080 l -S -1190 1920 m -1180 1920 l -S -1190 2040 m -1180 2040 l -S -1190 2180 m -1180 2180 l -S -1190 2200 m -1180 2200 l -S -1190 2300 m -1180 2300 l -S -1 w -1230 1900 m -1240 1900 l -S -1230 2020 m -1240 2020 l -S -1230 2100 m -1240 2100 l -S -1230 2120 m -1240 2120 l -S -1230 2180 m -1240 2180 l -S -1230 2240 m -1240 2240 l -S -1230 2220 m -1240 2220 l -S -3 w -1230 2000 m -1240 2000 l -S -1230 1980 m -1240 1980 l -S -1230 2060 m -1240 2060 l -S -1230 2040 m -1240 2040 l -S -1230 1940 m -1240 1940 l -S -1230 1960 m -1240 1960 l -S -1230 1920 m -1240 1920 l -S -1230 2080 m -1240 2080 l -S -1230 2140 m -1240 2140 l -S -1230 2160 m -1240 2160 l -S -1230 2200 m -1240 2200 l -S -0.000 0.000 1.000 RG -4784 1527 m -4791 1520 l -4784 1513 l -S -4770 1520 m -4791 1520 l -S -q -0.000 0.000 1.000 rg -1 0 0 1 4795 1536 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm -0 -4.308 Td -([1-2]) Tj -ET -Q -q -0.176 0.176 0.176 rg -1 0 0 1 4795 1520 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm -0 -4.308 Td -(dram_fill_req_addr[31..0]) Tj -ET -Q -1 w -0 2220 m --14 2220 l --21 2227 l -S --14 2220 m --21 2213 l -S -q -0.000 0.000 1.000 rg -1 0 0 1 -25 2236 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm --23.352 -4.308 Td -([1,3]) Tj -ET -Q -q -0.176 0.176 0.176 rg -1 0 0 1 -25 2220 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm --212.064 -4.308 Td -([5].curr_bank_dram_fill_rsp_valid:OUT0) Tj -ET -Q -0 2320 m --14 2320 l --21 2327 l -S --14 2320 m --21 2313 l -S -q -0.000 0.000 1.000 rg -1 0 0 1 -25 2336 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm --23.352 -4.308 Td -([1,3]) Tj -ET -Q -q -0.176 0.176 0.176 rg -1 0 0 1 -25 2320 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm --155.4 -4.308 Td -([5].curr_bank_snp_req:OUT0) Tj -ET -Q -q -0.000 0.000 0.000 rg -4485 1533 60 1182 re -f -Q -q -0.506 0.749 0.373 rg -4480 1528 60 1182 re -f -Q -0.176 0.176 0.176 RG -4480 1528 60 1182 re -S -3 w -4491 1533 m -4491 1545 l -S -4485 1539 m -4497 1539 l -S -1 w -4483 1531 16 16 re -S -q -0.000 0.000 0.000 rg -1 0 0 1 4510 1526 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm --74.028 2.484 Td -(cache_core_rsp_sel_merge) Tj -ET -Q -q -0.176 0.176 0.176 rg -1 0 0 1 4510 2716 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm --73.692 -8.616 Td -(\(VX_cache_wb_sel_merge\)) Tj -ET -Q -0.024 0.278 0.435 RG -4470 1560 m -4480 1560 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 4478 1559 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --69.47 2.07 Td -(core_rsp_ready) Tj -ET -Q -3 w -4470 2380 m -4480 2380 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 4478 2379 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --108.39 2.07 Td -(per_bank_wb_valid[7..0]) Tj -ET -Q -4470 2220 m -4480 2220 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 4478 2219 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --109.51 2.07 Td -(per_bank_wb_tid[0][0..0]) Tj -ET -Q -4470 2240 m -4480 2240 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 4478 2239 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --109.51 2.07 Td -(per_bank_wb_tid[1][0..0]) Tj -ET -Q -4470 2260 m -4480 2260 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 4478 2259 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --109.51 2.07 Td -(per_bank_wb_tid[2][0..0]) Tj -ET -Q -4470 2280 m -4480 2280 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 4478 2279 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --109.51 2.07 Td -(per_bank_wb_tid[3][0..0]) Tj -ET -Q -4470 2300 m -4480 2300 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 4478 2299 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --109.51 2.07 Td -(per_bank_wb_tid[4][0..0]) Tj -ET -Q -4470 2320 m -4480 2320 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 4478 2319 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --109.51 2.07 Td -(per_bank_wb_tid[5][0..0]) Tj -ET -Q -4470 2340 m -4480 2340 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 4478 2339 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --109.51 2.07 Td -(per_bank_wb_tid[6][0..0]) Tj -ET -Q -4470 2360 m -4480 2360 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 4478 2359 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --109.51 2.07 Td -(per_bank_wb_tid[7][0..0]) Tj -ET -Q -4470 2060 m -4480 2060 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 4478 2059 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --107.84 2.07 Td -(per_bank_wb_rd[0][4..0]) Tj -ET -Q -4470 2080 m -4480 2080 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 4478 2079 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --107.84 2.07 Td -(per_bank_wb_rd[1][4..0]) Tj -ET -Q -4470 2100 m -4480 2100 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 4478 2099 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --107.84 2.07 Td -(per_bank_wb_rd[2][4..0]) Tj -ET -Q -4470 2120 m -4480 2120 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 4478 2119 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --107.84 2.07 Td -(per_bank_wb_rd[3][4..0]) Tj -ET -Q -4470 2140 m -4480 2140 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 4478 2139 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --107.84 2.07 Td -(per_bank_wb_rd[4][4..0]) Tj -ET -Q -4470 2160 m -4480 2160 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 4478 2159 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --107.84 2.07 Td -(per_bank_wb_rd[5][4..0]) Tj -ET -Q -4470 2180 m -4480 2180 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 4478 2179 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --107.84 2.07 Td -(per_bank_wb_rd[6][4..0]) Tj -ET -Q -4470 2200 m -4480 2200 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 4478 2199 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --107.84 2.07 Td -(per_bank_wb_rd[7][4..0]) Tj -ET -Q -4470 2560 m -4480 2560 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 4478 2559 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --111.73 2.07 Td -(per_bank_wb_wb[0][1..0]) Tj -ET -Q -4470 2580 m -4480 2580 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 4478 2579 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --111.73 2.07 Td -(per_bank_wb_wb[1][1..0]) Tj -ET -Q -4470 2600 m -4480 2600 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 4478 2599 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --111.73 2.07 Td -(per_bank_wb_wb[2][1..0]) Tj -ET -Q -4470 2620 m -4480 2620 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 4478 2619 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --111.73 2.07 Td -(per_bank_wb_wb[3][1..0]) Tj -ET -Q -4470 2640 m -4480 2640 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 4478 2639 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --111.73 2.07 Td -(per_bank_wb_wb[4][1..0]) Tj -ET -Q -4470 2660 m -4480 2660 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 4478 2659 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --111.73 2.07 Td -(per_bank_wb_wb[5][1..0]) Tj -ET -Q -4470 2680 m -4480 2680 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 4478 2679 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --111.73 2.07 Td -(per_bank_wb_wb[6][1..0]) Tj -ET -Q -4470 2700 m -4480 2700 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 4478 2699 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --111.73 2.07 Td -(per_bank_wb_wb[7][1..0]) Tj -ET -Q -4470 2400 m -4480 2400 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 4478 2399 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --145.63 2.07 Td -(per_bank_wb_warp_num[0][2..0]) Tj -ET -Q -4470 2420 m -4480 2420 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 4478 2419 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --145.63 2.07 Td -(per_bank_wb_warp_num[1][2..0]) Tj -ET -Q -4470 2440 m -4480 2440 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 4478 2439 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --145.63 2.07 Td -(per_bank_wb_warp_num[2][2..0]) Tj -ET -Q -4470 2460 m -4480 2460 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 4478 2459 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --145.63 2.07 Td -(per_bank_wb_warp_num[3][2..0]) Tj -ET -Q -4470 2480 m -4480 2480 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 4478 2479 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --145.63 2.07 Td -(per_bank_wb_warp_num[4][2..0]) Tj -ET -Q -4470 2500 m -4480 2500 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 4478 2499 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --145.63 2.07 Td -(per_bank_wb_warp_num[5][2..0]) Tj -ET -Q -4470 2520 m -4480 2520 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 4478 2519 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --145.63 2.07 Td -(per_bank_wb_warp_num[6][2..0]) Tj -ET -Q -4470 2540 m -4480 2540 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 4478 2539 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --145.63 2.07 Td -(per_bank_wb_warp_num[7][2..0]) Tj -ET -Q -4470 1740 m -4480 1740 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 4478 1739 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --129.53 2.07 Td -(per_bank_wb_data[0][127..0]) Tj -ET -Q -4470 1760 m -4480 1760 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 4478 1759 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --129.53 2.07 Td -(per_bank_wb_data[1][127..0]) Tj -ET -Q -4470 1780 m -4480 1780 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 4478 1779 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --129.53 2.07 Td -(per_bank_wb_data[2][127..0]) Tj -ET -Q -4470 1800 m -4480 1800 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 4478 1799 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --129.53 2.07 Td -(per_bank_wb_data[3][127..0]) Tj -ET -Q -4470 1820 m -4480 1820 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 4478 1819 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --129.53 2.07 Td -(per_bank_wb_data[4][127..0]) Tj -ET -Q -4470 1840 m -4480 1840 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 4478 1839 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --129.53 2.07 Td -(per_bank_wb_data[5][127..0]) Tj -ET -Q -4470 1860 m -4480 1860 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 4478 1859 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --129.53 2.07 Td -(per_bank_wb_data[6][127..0]) Tj -ET -Q -4470 1880 m -4480 1880 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 4478 1879 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --129.53 2.07 Td -(per_bank_wb_data[7][127..0]) Tj -ET -Q -4470 1900 m -4480 1900 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 4478 1899 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --115.07 2.07 Td -(per_bank_wb_pc[0][31..0]) Tj -ET -Q -4470 1920 m -4480 1920 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 4478 1919 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --115.07 2.07 Td -(per_bank_wb_pc[1][31..0]) Tj -ET -Q -4470 1940 m -4480 1940 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 4478 1939 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --115.07 2.07 Td -(per_bank_wb_pc[2][31..0]) Tj -ET -Q -4470 1960 m -4480 1960 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 4478 1959 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --115.07 2.07 Td -(per_bank_wb_pc[3][31..0]) Tj -ET -Q -4470 1980 m -4480 1980 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 4478 1979 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --115.07 2.07 Td -(per_bank_wb_pc[4][31..0]) Tj -ET -Q -4470 2000 m -4480 2000 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 4478 1999 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --115.07 2.07 Td -(per_bank_wb_pc[5][31..0]) Tj -ET -Q -4470 2020 m -4480 2020 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 4478 2019 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --115.07 2.07 Td -(per_bank_wb_pc[6][31..0]) Tj -ET -Q -4470 2040 m -4480 2040 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 4478 2039 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --115.07 2.07 Td -(per_bank_wb_pc[7][31..0]) Tj -ET -Q -4470 1580 m -4480 1580 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 4478 1579 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --124.52 2.07 Td -(per_bank_wb_addr[0][31..0]) Tj -ET -Q -4470 1600 m -4480 1600 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 4478 1599 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --124.52 2.07 Td -(per_bank_wb_addr[1][31..0]) Tj -ET -Q -4470 1620 m -4480 1620 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 4478 1619 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --124.52 2.07 Td -(per_bank_wb_addr[2][31..0]) Tj -ET -Q -4470 1640 m -4480 1640 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 4478 1639 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --124.52 2.07 Td -(per_bank_wb_addr[3][31..0]) Tj -ET -Q -4470 1660 m -4480 1660 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 4478 1659 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --124.52 2.07 Td -(per_bank_wb_addr[4][31..0]) Tj -ET -Q -4470 1680 m -4480 1680 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 4478 1679 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --124.52 2.07 Td -(per_bank_wb_addr[5][31..0]) Tj -ET -Q -4470 1700 m -4480 1700 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 4478 1699 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --124.52 2.07 Td -(per_bank_wb_addr[6][31..0]) Tj -ET -Q -4470 1720 m -4480 1720 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 4478 1719 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --124.52 2.07 Td -(per_bank_wb_addr[7][31..0]) Tj -ET -Q -4550 2220 m -4540 2220 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 4546 2219 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(per_bank_wb_pop[7..0]) Tj -ET -Q -4550 2160 m -4540 2160 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 4546 2159 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(core_rsp_valid[1..0]) Tj -ET -Q -4550 2060 m -4540 2060 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 4546 2059 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(core_rsp_data[0][127..0]) Tj -ET -Q -4550 2080 m -4540 2080 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 4546 2079 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(core_rsp_data[1][127..0]) Tj -ET -Q -4550 2100 m -4540 2100 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 4546 2099 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(core_rsp_pc[0][31..0]) Tj -ET -Q -4550 2120 m -4540 2120 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 4546 2119 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(core_rsp_pc[1][31..0]) Tj -ET -Q -4550 2140 m -4540 2140 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 4546 2139 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(core_rsp_read[4..0]) Tj -ET -Q -4550 2200 m -4540 2200 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 4546 2199 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(core_rsp_write[1..0]) Tj -ET -Q -4550 2180 m -4540 2180 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 4546 2179 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(core_rsp_warp_num[2..0]) Tj -ET -Q -4550 2020 m -4540 2020 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 4546 2019 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(core_rsp_addr[0][31..0]) Tj -ET -Q -4550 2040 m -4540 2040 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 4546 2039 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(core_rsp_addr[1][31..0]) Tj -ET -Q -1 w -4490 1560 m -4480 1560 l -S -3 w -4490 2380 m -4480 2380 l -S -4490 2220 m -4480 2220 l -S -4490 2240 m -4480 2240 l -S -4490 2260 m -4480 2260 l -S -4490 2280 m -4480 2280 l -S -4490 2300 m -4480 2300 l -S -4490 2320 m -4480 2320 l -S -4490 2340 m -4480 2340 l -S -4490 2360 m -4480 2360 l -S -4490 2060 m -4480 2060 l -S -4490 2080 m -4480 2080 l -S -4490 2100 m -4480 2100 l -S -4490 2120 m -4480 2120 l -S -4490 2140 m -4480 2140 l -S -4490 2160 m -4480 2160 l -S -4490 2180 m -4480 2180 l -S -4490 2200 m -4480 2200 l -S -4490 2560 m -4480 2560 l -S -4490 2580 m -4480 2580 l -S -4490 2600 m -4480 2600 l -S -4490 2620 m -4480 2620 l -S -4490 2640 m -4480 2640 l -S -4490 2660 m -4480 2660 l -S -4490 2680 m -4480 2680 l -S -4490 2700 m -4480 2700 l -S -4490 2400 m -4480 2400 l -S -4490 2420 m -4480 2420 l -S -4490 2440 m -4480 2440 l -S -4490 2460 m -4480 2460 l -S -4490 2480 m -4480 2480 l -S -4490 2500 m -4480 2500 l -S -4490 2520 m -4480 2520 l -S -4490 2540 m -4480 2540 l -S -4490 1740 m -4480 1740 l -S -4490 1760 m -4480 1760 l -S -4490 1780 m -4480 1780 l -S -4490 1800 m -4480 1800 l -S -4490 1820 m -4480 1820 l -S -4490 1840 m -4480 1840 l -S -4490 1860 m -4480 1860 l -S -4490 1880 m -4480 1880 l -S -4490 1900 m -4480 1900 l -S -4490 1920 m -4480 1920 l -S -4490 1940 m -4480 1940 l -S -4490 1960 m -4480 1960 l -S -4490 1980 m -4480 1980 l -S -4490 2000 m -4480 2000 l -S -4490 2020 m -4480 2020 l -S -4490 2040 m -4480 2040 l -S -4490 1580 m -4480 1580 l -S -4490 1600 m -4480 1600 l -S -4490 1620 m -4480 1620 l -S -4490 1640 m -4480 1640 l -S -4490 1660 m -4480 1660 l -S -4490 1680 m -4480 1680 l -S -4490 1700 m -4480 1700 l -S -4490 1720 m -4480 1720 l -S -4530 2220 m -4540 2220 l -S -4530 2160 m -4540 2160 l -S -4530 2060 m -4540 2060 l -S -4530 2080 m -4540 2080 l -S -4530 2100 m -4540 2100 l -S -4530 2120 m -4540 2120 l -S -4530 2140 m -4540 2140 l -S -4530 2200 m -4540 2200 l -S -4530 2180 m -4540 2180 l -S -4530 2020 m -4540 2020 l -S -4530 2040 m -4540 2040 l -S -q -0.000 0.000 0.000 rg -1185 2373 60 542 re -f -Q -q -0.506 0.749 0.373 rg -1180 2368 60 542 re -f -Q -1 w -0.176 0.176 0.176 RG -1180 2368 60 542 re -S -3 w -1191 2373 m -1191 2385 l -S -1185 2379 m -1197 2379 l -S -1 w -1183 2371 16 16 re -S -q -0.000 0.000 0.000 rg -1 0 0 1 1210 2366 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm --21.348 2.484 Td -([4].bank) Tj -ET -Q -q -0.176 0.176 0.176 rg -1 0 0 1 1210 2916 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm --28.344 -8.616 Td -(\(VX_bank\)) Tj -ET -Q -0.024 0.278 0.435 RG -1170 2400 m -1180 2400 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1178 2399 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --12.22 2.07 Td -(clk) Tj -ET -Q -1170 2840 m -1180 2840 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1178 2839 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --22.23 2.07 Td -(reset) Tj -ET -Q -1180 2580 m -1180 2578.34 1178.66 2577 1177 2577 c -1175.34 2577 1174 2578.34 1174 2580 c -1174 2581.66 1175.34 2583 1177 2583 c -1178.66 2583 1180 2581.66 1180 2580 c -S -1170 2580 m -1174 2580 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1174 2579 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --70.03 2.07 Td -(core_req_ready) Tj -ET -Q -1170 2720 m -1180 2720 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1178 2719 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --61.14 2.07 Td -(core_rsp_pop) Tj -ET -Q -1170 2740 m -1180 2740 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1178 2739 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --76.13 2.07 Td -(dram_fill_req_full) Tj -ET -Q -1170 2800 m -1180 2800 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1178 2799 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --83.35 2.07 Td -(dram_fill_rsp_valid) Tj -ET -Q -1170 2820 m -1180 2820 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1178 2819 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --83.37 2.07 Td -(dram_wb_req_pop) Tj -ET -Q -1170 2900 m -1180 2900 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1178 2899 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --62.25 2.07 Td -(snp_req_valid) Tj -ET -Q -1170 2860 m -1180 2860 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1178 2859 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --59.48 2.07 Td -(snp_fwd_pop) Tj -ET -Q -3 w -1170 2600 m -1180 2600 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1178 2599 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --92.82 2.07 Td -(core_req_valids[1..0]) Tj -ET -Q -1170 2540 m -1180 2540 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1178 2539 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --98.39 2.07 Td -(core_req_read[0][2..0]) Tj -ET -Q -1170 2560 m -1180 2560 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1178 2559 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --98.39 2.07 Td -(core_req_read[1][2..0]) Tj -ET -Q -1170 2680 m -1180 2680 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1178 2679 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --99.49 2.07 Td -(core_req_write[0][2..0]) Tj -ET -Q -1170 2700 m -1180 2700 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1178 2699 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --99.49 2.07 Td -(core_req_write[1][2..0]) Tj -ET -Q -1170 2420 m -1180 2420 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1178 2419 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --103.95 2.07 Td -(core_req_addr[0][31..0]) Tj -ET -Q -1170 2440 m -1180 2440 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1178 2439 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --103.95 2.07 Td -(core_req_addr[1][31..0]) Tj -ET -Q -1170 2460 m -1180 2460 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1178 2459 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --108.96 2.07 Td -(core_req_data[0][127..0]) Tj -ET -Q -1170 2480 m -1180 2480 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1178 2479 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --108.96 2.07 Td -(core_req_data[1][127..0]) Tj -ET -Q -1170 2520 m -1180 2520 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1178 2519 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --76.15 2.07 Td -(core_req_rd[4..0]) Tj -ET -Q -1170 2640 m -1180 2640 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1178 2639 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --91.16 2.07 Td -(core_req_wb[0][1..0]) Tj -ET -Q -1170 2660 m -1180 2660 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1178 2659 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --91.16 2.07 Td -(core_req_wb[1][1..0]) Tj -ET -Q -1170 2500 m -1180 2500 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1178 2499 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --83.38 2.07 Td -(core_req_pc[31..0]) Tj -ET -Q -1170 2620 m -1180 2620 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1178 2619 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --113.94 2.07 Td -(core_req_warp_num[2..0]) Tj -ET -Q -1170 2760 m -1180 2760 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1178 2759 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --110.6 2.07 Td -(dram_fill_rsp_addr[31..0]) Tj -ET -Q -1170 2780 m -1180 2780 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1178 2779 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --126.73 2.07 Td -(dram_fill_rsp_data[0][127..0]) Tj -ET -Q -1170 2880 m -1180 2880 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1178 2879 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --89.5 2.07 Td -(snp_req_addr[31..0]) Tj -ET -Q -1 w -1250 2480 m -1240 2480 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1246 2479 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(core_req_full) Tj -ET -Q -1250 2600 m -1240 2600 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1246 2599 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(core_rsp_valid) Tj -ET -Q -1250 2680 m -1240 2680 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1246 2679 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(dram_fill_req_valid) Tj -ET -Q -1250 2700 m -1240 2700 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1246 2699 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(dram_fill_rsp_ready) Tj -ET -Q -1250 2760 m -1240 2760 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1246 2759 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(dram_wb_req_valid) Tj -ET -Q -1250 2820 m -1240 2820 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1246 2819 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(snp_req_full) Tj -ET -Q -1250 2800 m -1240 2800 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1246 2799 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(snp_fwd_valid) Tj -ET -Q -3 w -1250 2580 m -1240 2580 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1246 2579 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(core_rsp_tid[0..0]) Tj -ET -Q -1250 2560 m -1240 2560 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1246 2559 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(core_rsp_rd[4..0]) Tj -ET -Q -1250 2640 m -1240 2640 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1246 2639 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(core_rsp_wb[1..0]) Tj -ET -Q -1250 2620 m -1240 2620 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1246 2619 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(core_rsp_warp_num[2..0]) Tj -ET -Q -1250 2520 m -1240 2520 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1246 2519 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(core_rsp_data[127..0]) Tj -ET -Q -1250 2540 m -1240 2540 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1246 2539 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(core_rsp_pc[31..0]) Tj -ET -Q -1250 2500 m -1240 2500 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1246 2499 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(core_rsp_addr[31..0]) Tj -ET -Q -1250 2660 m -1240 2660 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1246 2659 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(dram_fill_req_addr[31..0]) Tj -ET -Q -1250 2720 m -1240 2720 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1246 2719 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(dram_wb_req_addr[31..0]) Tj -ET -Q -1250 2740 m -1240 2740 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1246 2739 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(dram_wb_req_data[0][127..0]) Tj -ET -Q -1250 2780 m -1240 2780 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1246 2779 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(snp_fwd_addr[31..0]) Tj -ET -Q -1 w -1190 2400 m -1180 2400 l -S -1190 2840 m -1180 2840 l -S -1190 2580 m -1180 2580 l -S -1190 2720 m -1180 2720 l -S -1190 2740 m -1180 2740 l -S -1190 2800 m -1180 2800 l -S -1190 2820 m -1180 2820 l -S -1190 2900 m -1180 2900 l -S -1190 2860 m -1180 2860 l -S -3 w -1190 2600 m -1180 2600 l -S -1190 2540 m -1180 2540 l -S -1190 2560 m -1180 2560 l -S -1190 2680 m -1180 2680 l -S -1190 2700 m -1180 2700 l -S -1190 2420 m -1180 2420 l -S -1190 2440 m -1180 2440 l -S -1190 2460 m -1180 2460 l -S -1190 2480 m -1180 2480 l -S -1190 2520 m -1180 2520 l -S -1190 2640 m -1180 2640 l -S -1190 2660 m -1180 2660 l -S -1190 2500 m -1180 2500 l -S -1190 2620 m -1180 2620 l -S -1190 2760 m -1180 2760 l -S -1190 2780 m -1180 2780 l -S -1190 2880 m -1180 2880 l -S -1 w -1230 2480 m -1240 2480 l -S -1230 2600 m -1240 2600 l -S -1230 2680 m -1240 2680 l -S -1230 2700 m -1240 2700 l -S -1230 2760 m -1240 2760 l -S -1230 2820 m -1240 2820 l -S -1230 2800 m -1240 2800 l -S -3 w -1230 2580 m -1240 2580 l -S -1230 2560 m -1240 2560 l -S -1230 2640 m -1240 2640 l -S -1230 2620 m -1240 2620 l -S -1230 2520 m -1240 2520 l -S -1230 2540 m -1240 2540 l -S -1230 2500 m -1240 2500 l -S -1230 2660 m -1240 2660 l -S -1230 2720 m -1240 2720 l -S -1230 2740 m -1240 2740 l -S -1230 2780 m -1240 2780 l -S -q -0.000 0.000 0.000 rg -2815 2480 m -2817 2482 l -2819 2485 l -2820 2487 l -2821 2490 l -2822 2493 l -2822 2497 l -2821 2500 l -2820 2503 l -2819 2505 l -2817 2508 l -2815 2510 l -2815 2510 l -2830 2510 l -2830 2510 l -2833 2510 l -2836 2509 l -2839 2508 l -2841 2507 l -2844 2506 l -2847 2504 l -2849 2502 l -2851 2500 l -2853 2498 l -2855 2495 l -2855 2495 l -2853 2492 l -2851 2490 l -2849 2488 l -2847 2486 l -2844 2484 l -2841 2483 l -2839 2482 l -2836 2481 l -2833 2480 l -2830 2480 l -2830 2480 l -h f -Q -q -0.451 0.675 0.675 rg -2810 2475 m -2812 2477 l -2814 2480 l -2815 2482 l -2816 2485 l -2817 2488 l -2817 2492 l -2816 2495 l -2815 2498 l -2814 2500 l -2812 2503 l -2810 2505 l -2810 2505 l -2825 2505 l -2825 2505 l -2828 2505 l -2831 2504 l -2834 2503 l -2836 2502 l -2839 2501 l -2842 2499 l -2844 2497 l -2846 2495 l -2848 2493 l -2850 2490 l -2850 2490 l -2848 2487 l -2846 2485 l -2844 2483 l -2842 2481 l -2839 2479 l -2836 2478 l -2834 2477 l -2831 2476 l -2828 2475 l -2825 2475 l -2825 2475 l -h f -Q -1 w -0.176 0.176 0.176 RG -2810 2505 m -2810.88 2504.26 2811.69 2503.45 2812.43 2502.57 c -2819.37 2494.29 2818.28 2481.94 2810 2475 c -S -2810 2505 m -2825 2505 l -S -2850 2490 m -2844.49 2498.66 2835.23 2504.21 2825 2505 c -S -2825 2475 m -2835.23 2475.79 2844.49 2481.34 2850 2490 c -S -2825 2475 m -2810 2475 l -S -2810 2475 m -2810 2446 l -S -2810 2505 m -2810 2524 l -S -q -0.000 0.000 0.000 rg -1 0 0 1 2812 2474 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm -0 2.484 Td -(reduce_or_0) Tj -ET -Q -0.024 0.278 0.435 RG -2800 2520 m -2810 2520 l -S -2800 2450 m -2810 2450 l -S -2800 2460 m -2810 2460 l -S -2800 2470 m -2810 2470 l -S -2800 2490 m -2817 2490 l -S -2800 2480 m -2814 2480 l -S -2800 2500 m -2814 2500 l -S -2800 2510 m -2810 2510 l -S -2860 2490 m -2850 2490 l -S -3 w -0.000 0.000 1.000 RG -4770 2020 m -4770 2013 l -4784 2013 l -4791 2020 l -4784 2027 l -4770 2027 l -h S -q -0.000 0.000 0.000 rg -1 0 0 1 4799 2020 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm -0 -4.308 Td -(core_rsp_addr[0][31..0]) Tj -ET -Q -4770 2040 m -4770 2033 l -4784 2033 l -4791 2040 l -4784 2047 l -4770 2047 l -h S -q -0.000 0.000 0.000 rg -1 0 0 1 4799 2040 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm -0 -4.308 Td -(core_rsp_addr[1][31..0]) Tj -ET -Q -4784 2727 m -4791 2720 l -4784 2713 l -S -4770 2720 m -4791 2720 l -S -q -0.000 0.000 1.000 rg -1 0 0 1 4795 2736 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm -0 -4.308 Td -([1-2]) Tj -ET -Q -q -0.176 0.176 0.176 rg -1 0 0 1 4795 2720 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm -0 -4.308 Td -(dram_fill_req_addr[31..0]) Tj -ET -Q -4770 2060 m -4770 2053 l -4784 2053 l -4791 2060 l -4784 2067 l -4770 2067 l -h S -q -0.000 0.000 0.000 rg -1 0 0 1 4799 2060 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm -0 -4.308 Td -(core_rsp_data[0][127..0]) Tj -ET -Q -4770 2080 m -4770 2073 l -4784 2073 l -4791 2080 l -4784 2087 l -4770 2087 l -h S -q -0.000 0.000 0.000 rg -1 0 0 1 4799 2080 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm -0 -4.308 Td -(core_rsp_data[1][127..0]) Tj -ET -Q -4770 2100 m -4770 2093 l -4784 2093 l -4791 2100 l -4784 2107 l -4770 2107 l -h S -q -0.000 0.000 0.000 rg -1 0 0 1 4799 2100 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm -0 -4.308 Td -(core_rsp_pc[0][31..0]) Tj -ET -Q -1 w -0 2800 m --14 2800 l --21 2807 l -S --14 2800 m --21 2793 l -S -q -0.000 0.000 1.000 rg -1 0 0 1 -25 2816 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm --23.352 -4.308 Td -([1,3]) Tj -ET -Q -q -0.176 0.176 0.176 rg -1 0 0 1 -25 2800 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm --212.064 -4.308 Td -([4].curr_bank_dram_fill_rsp_valid:OUT0) Tj -ET -Q -3 w -4770 2120 m -4770 2113 l -4784 2113 l -4791 2120 l -4784 2127 l -4770 2127 l -h S -q -0.000 0.000 0.000 rg -1 0 0 1 4799 2120 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm -0 -4.308 Td -(core_rsp_pc[1][31..0]) Tj -ET -Q -4770 2140 m -4770 2133 l -4784 2133 l -4791 2140 l -4784 2147 l -4770 2147 l -h S -q -0.000 0.000 0.000 rg -1 0 0 1 4799 2140 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm -0 -4.308 Td -(core_rsp_read[4..0]) Tj -ET -Q -4770 2160 m -4770 2153 l -4784 2153 l -4791 2160 l -4784 2167 l -4770 2167 l -h S -q -0.000 0.000 0.000 rg -1 0 0 1 4799 2160 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm -0 -4.308 Td -(core_rsp_valid[1..0]) Tj -ET -Q -1 w -0 2900 m --14 2900 l --21 2907 l -S --14 2900 m --21 2893 l -S -q -0.000 0.000 1.000 rg -1 0 0 1 -25 2916 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm --23.352 -4.308 Td -([1,3]) Tj -ET -Q -q -0.176 0.176 0.176 rg -1 0 0 1 -25 2900 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm --155.4 -4.308 Td -([4].curr_bank_snp_req:OUT0) Tj -ET -Q -3 w -4770 2180 m -4770 2173 l -4784 2173 l -4791 2180 l -4784 2187 l -4770 2187 l -h S -q -0.000 0.000 0.000 rg -1 0 0 1 4799 2180 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm -0 -4.308 Td -(core_rsp_warp_num[2..0]) Tj -ET -Q -4770 2200 m -4770 2193 l -4784 2193 l -4791 2200 l -4784 2207 l -4770 2207 l -h S -q -0.000 0.000 0.000 rg -1 0 0 1 4799 2200 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm -0 -4.308 Td -(core_rsp_write[1..0]) Tj -ET -Q -4784 2767 m -4791 2760 l -4784 2753 l -S -4770 2760 m -4791 2760 l -S -q -0.000 0.000 1.000 rg -1 0 0 1 4795 2776 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm -0 -4.308 Td -([1-2]) Tj -ET -Q -q -0.176 0.176 0.176 rg -1 0 0 1 4795 2760 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm -0 -4.308 Td -(dram_wb_req_addr[31..0]) Tj -ET -Q -4784 2807 m -4791 2800 l -4784 2793 l -S -4770 2800 m -4791 2800 l -S -q -0.000 0.000 1.000 rg -1 0 0 1 4795 2816 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm -0 -4.308 Td -([1-2]) Tj -ET -Q -q -0.176 0.176 0.176 rg -1 0 0 1 4795 2800 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm -0 -4.308 Td -(dram_wb_req_addr[31..0]) Tj -ET -Q -q -0.000 0.000 0.000 rg -4485 2830 m -4487 2832 l -4489 2835 l -4490 2837 l -4491 2840 l -4492 2843 l -4492 2847 l -4491 2850 l -4490 2853 l -4489 2855 l -4487 2858 l -4485 2860 l -4485 2860 l -4500 2860 l -4500 2860 l -4503 2860 l -4506 2859 l -4509 2858 l -4511 2857 l -4514 2856 l -4517 2854 l -4519 2852 l -4521 2850 l -4523 2848 l -4525 2845 l -4525 2845 l -4523 2842 l -4521 2840 l -4519 2838 l -4517 2836 l -4514 2834 l -4511 2833 l -4509 2832 l -4506 2831 l -4503 2830 l -4500 2830 l -4500 2830 l -h f -Q -q -0.451 0.675 0.675 rg -4480 2825 m -4482 2827 l -4484 2830 l -4485 2832 l -4486 2835 l -4487 2838 l -4487 2842 l -4486 2845 l -4485 2848 l -4484 2850 l -4482 2853 l -4480 2855 l -4480 2855 l -4495 2855 l -4495 2855 l -4498 2855 l -4501 2854 l -4504 2853 l -4506 2852 l -4509 2851 l -4512 2849 l -4514 2847 l -4516 2845 l -4518 2843 l -4520 2840 l -4520 2840 l -4518 2837 l -4516 2835 l -4514 2833 l -4512 2831 l -4509 2829 l -4506 2828 l -4504 2827 l -4501 2826 l -4498 2825 l -4495 2825 l -4495 2825 l -h f -Q -1 w -0.176 0.176 0.176 RG -4480 2855 m -4480.88 2854.26 4481.69 2853.45 4482.43 2852.57 c -4489.37 2844.29 4488.28 2831.94 4480 2825 c -S -4480 2855 m -4495 2855 l -S -4520 2840 m -4514.49 2848.66 4505.23 2854.21 4495 2855 c -S -4495 2825 m -4505.23 2825.79 4514.49 2831.34 4520 2840 c -S -4495 2825 m -4480 2825 l -S -4480 2825 m -4480 2796 l -S -4480 2855 m -4480 2874 l -S -q -0.000 0.000 0.000 rg -1 0 0 1 4482 2824 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm -0 2.484 Td -(reduce_or_1) Tj -ET -Q -0.024 0.278 0.435 RG -4470 2870 m -4480 2870 l -S -4470 2800 m -4480 2800 l -S -4470 2810 m -4480 2810 l -S -4470 2820 m -4480 2820 l -S -4470 2830 m -4484 2830 l -S -4470 2840 m -4487 2840 l -S -4470 2850 m -4484 2850 l -S -4470 2860 m -4480 2860 l -S -4530 2840 m -4520 2840 l -S -3 w -0.000 0.000 1.000 RG -0 2940 m --7 2947 l --21 2947 l --21 2933 l --7 2933 l -h S -q -0.000 0.000 0.000 rg -1 0 0 1 -25 2940 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm --124.74 -4.308 Td -(core_req_addr[0][31..0]) Tj -ET -Q -1 w -4784 2847 m -4791 2840 l -4784 2833 l -S -4770 2840 m -4791 2840 l -S -q -0.000 0.000 1.000 rg -1 0 0 1 4795 2856 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm -0 -4.308 Td -([1,3]) Tj -ET -Q -q -0.176 0.176 0.176 rg -1 0 0 1 4795 2840 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm -0 -4.308 Td -(reduce_or_1:OUT0) Tj -ET -Q -3 w -0 2960 m --7 2967 l --21 2967 l --21 2953 l --7 2953 l -h S -q -0.000 0.000 0.000 rg -1 0 0 1 -25 2960 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm --124.74 -4.308 Td -(core_req_addr[1][31..0]) Tj -ET -Q -q -0.000 0.000 0.000 rg -185 2973 60 182 re -f -Q -q -0.506 0.749 0.373 rg -180 2968 60 182 re -f -Q -1 w -0.176 0.176 0.176 RG -180 2968 60 182 re -S -3 w -191 2973 m -191 2985 l -S -185 2979 m -197 2979 l -S -1 w -183 2971 16 16 re -S -q -0.000 0.000 0.000 rg -1 0 0 1 210 2966 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm --71.7 2.484 Td -(cache_core_req_bank_sell) Tj -ET -Q -q -0.176 0.176 0.176 rg -1 0 0 1 210 3156 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm --85.704 -8.616 Td -(\(VX_cache_core_req_bank_sel\)) Tj -ET -Q -3 w -0.024 0.278 0.435 RG -170 3080 m -180 3080 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 178 3079 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --87.82 2.07 Td -(core_req_valid[1..0]) Tj -ET -Q -170 3040 m -180 3040 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 178 3039 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --103.95 2.07 Td -(core_req_addr[0][31..0]) Tj -ET -Q -170 3060 m -180 3060 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 178 3059 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --103.95 2.07 Td -(core_req_addr[1][31..0]) Tj -ET -Q -250 3000 m -240 3000 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 246 2999 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(per_bank_valids[0][1..0]) Tj -ET -Q -250 3020 m -240 3020 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 246 3019 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(per_bank_valids[1][1..0]) Tj -ET -Q -250 3040 m -240 3040 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 246 3039 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(per_bank_valids[2][1..0]) Tj -ET -Q -250 3060 m -240 3060 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 246 3059 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(per_bank_valids[3][1..0]) Tj -ET -Q -250 3080 m -240 3080 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 246 3079 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(per_bank_valids[4][1..0]) Tj -ET -Q -250 3100 m -240 3100 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 246 3099 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(per_bank_valids[5][1..0]) Tj -ET -Q -250 3120 m -240 3120 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 246 3119 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(per_bank_valids[6][1..0]) Tj -ET -Q -250 3140 m -240 3140 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 246 3139 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(per_bank_valids[7][1..0]) Tj -ET -Q -190 3080 m -180 3080 l -S -190 3040 m -180 3040 l -S -190 3060 m -180 3060 l -S -230 3000 m -240 3000 l -S -230 3020 m -240 3020 l -S -230 3040 m -240 3040 l -S -230 3060 m -240 3060 l -S -230 3080 m -240 3080 l -S -230 3100 m -240 3100 l -S -230 3120 m -240 3120 l -S -230 3140 m -240 3140 l -S -0.000 0.000 1.000 RG -4784 2897 m -4791 2890 l -4784 2883 l -S -4770 2890 m -4791 2890 l -S -q -0.000 0.000 1.000 rg -1 0 0 1 4795 2906 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm -0 -4.308 Td -([1-2]) Tj -ET -Q -q -0.176 0.176 0.176 rg -1 0 0 1 4795 2890 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm -0 -4.308 Td -(dram_wb_req_data[0][127..0]) Tj -ET -Q -q -0.000 0.000 0.000 rg -4485 2960 m -4487 2962 l -4489 2965 l -4490 2967 l -4491 2970 l -4492 2973 l -4492 2977 l -4491 2980 l -4490 2983 l -4489 2985 l -4487 2988 l -4485 2990 l -4485 2990 l -4500 2990 l -4500 2990 l -4503 2990 l -4506 2989 l -4509 2988 l -4511 2987 l -4514 2986 l -4517 2984 l -4519 2982 l -4521 2980 l -4523 2978 l -4525 2975 l -4525 2975 l -4523 2972 l -4521 2970 l -4519 2968 l -4517 2966 l -4514 2964 l -4511 2963 l -4509 2962 l -4506 2961 l -4503 2960 l -4500 2960 l -4500 2960 l -h f -Q -q -0.451 0.675 0.675 rg -4480 2955 m -4482 2957 l -4484 2960 l -4485 2962 l -4486 2965 l -4487 2968 l -4487 2972 l -4486 2975 l -4485 2978 l -4484 2980 l -4482 2983 l -4480 2985 l -4480 2985 l -4495 2985 l -4495 2985 l -4498 2985 l -4501 2984 l -4504 2983 l -4506 2982 l -4509 2981 l -4512 2979 l -4514 2977 l -4516 2975 l -4518 2973 l -4520 2970 l -4520 2970 l -4518 2967 l -4516 2965 l -4514 2963 l -4512 2961 l -4509 2959 l -4506 2958 l -4504 2957 l -4501 2956 l -4498 2955 l -4495 2955 l -4495 2955 l -h f -Q -1 w -0.176 0.176 0.176 RG -4480 2985 m -4480.88 2984.26 4481.69 2983.45 4482.43 2982.57 c -4489.37 2974.29 4488.28 2961.94 4480 2955 c -S -4480 2985 m -4495 2985 l -S -4520 2970 m -4514.49 2978.66 4505.23 2984.21 4495 2985 c -S -4495 2955 m -4505.23 2955.79 4514.49 2961.34 4520 2970 c -S -4495 2955 m -4480 2955 l -S -4480 2955 m -4480 2926 l -S -4480 2985 m -4480 3004 l -S -q -0.000 0.000 0.000 rg -1 0 0 1 4482 2954 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm -0 2.484 Td -(reduce_or_2) Tj -ET -Q -0.024 0.278 0.435 RG -4470 3000 m -4480 3000 l -S -4470 2940 m -4480 2940 l -S -4470 2950 m -4480 2950 l -S -4470 2930 m -4480 2930 l -S -4470 2960 m -4484 2960 l -S -4470 2970 m -4487 2970 l -S -4470 2980 m -4484 2980 l -S -4470 2990 m -4480 2990 l -S -4530 2970 m -4520 2970 l -S -3 w -0.000 0.000 1.000 RG -0 3080 m --7 3087 l --21 3087 l --21 3073 l --7 3073 l -h S -q -0.000 0.000 0.000 rg -1 0 0 1 -25 3080 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm --105.384 -4.308 Td -(core_req_valid[1..0]) Tj -ET -Q -4784 2937 m -4791 2930 l -4784 2923 l -S -4770 2930 m -4791 2930 l -S -q -0.000 0.000 1.000 rg -1 0 0 1 4795 2946 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm -0 -4.308 Td -([1-2]) Tj -ET -Q -q -0.176 0.176 0.176 rg -1 0 0 1 4795 2930 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm -0 -4.308 Td -(dram_wb_req_data[0][127..0]) Tj -ET -Q -1 w -4770 2970 m -4770 2963 l -4784 2963 l -4791 2970 l -4784 2977 l -4770 2977 l -h S -q -0.000 0.000 0.000 rg -1 0 0 1 4799 2970 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm -0 -4.308 Td -(dram_rsp_ready) Tj -ET -Q -q -0.000 0.000 0.000 rg -1185 2953 60 542 re -f -Q -q -0.506 0.749 0.373 rg -1180 2948 60 542 re -f -Q -0.176 0.176 0.176 RG -1180 2948 60 542 re -S -3 w -1191 2953 m -1191 2965 l -S -1185 2959 m -1197 2959 l -S -1 w -1183 2951 16 16 re -S -q -0.000 0.000 0.000 rg -1 0 0 1 1210 2946 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm --21.348 2.484 Td -([6].bank) Tj -ET -Q -q -0.176 0.176 0.176 rg -1 0 0 1 1210 3496 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm --28.344 -8.616 Td -(\(VX_bank\)) Tj -ET -Q -0.024 0.278 0.435 RG -1170 2980 m -1180 2980 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1178 2979 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --12.22 2.07 Td -(clk) Tj -ET -Q -1170 3420 m -1180 3420 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1178 3419 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --22.23 2.07 Td -(reset) Tj -ET -Q -1180 3160 m -1180 3158.34 1178.66 3157 1177 3157 c -1175.34 3157 1174 3158.34 1174 3160 c -1174 3161.66 1175.34 3163 1177 3163 c -1178.66 3163 1180 3161.66 1180 3160 c -S -1170 3160 m -1174 3160 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1174 3159 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --70.03 2.07 Td -(core_req_ready) Tj -ET -Q -1170 3300 m -1180 3300 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1178 3299 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --61.14 2.07 Td -(core_rsp_pop) Tj -ET -Q -1170 3320 m -1180 3320 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1178 3319 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --76.13 2.07 Td -(dram_fill_req_full) Tj -ET -Q -1170 3380 m -1180 3380 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1178 3379 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --83.35 2.07 Td -(dram_fill_rsp_valid) Tj -ET -Q -1170 3400 m -1180 3400 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1178 3399 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --83.37 2.07 Td -(dram_wb_req_pop) Tj -ET -Q -1170 3480 m -1180 3480 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1178 3479 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --62.25 2.07 Td -(snp_req_valid) Tj -ET -Q -1170 3440 m -1180 3440 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1178 3439 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --59.48 2.07 Td -(snp_fwd_pop) Tj -ET -Q -3 w -1170 3180 m -1180 3180 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1178 3179 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --92.82 2.07 Td -(core_req_valids[1..0]) Tj -ET -Q -1170 3120 m -1180 3120 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1178 3119 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --98.39 2.07 Td -(core_req_read[0][2..0]) Tj -ET -Q -1170 3140 m -1180 3140 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1178 3139 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --98.39 2.07 Td -(core_req_read[1][2..0]) Tj -ET -Q -1170 3260 m -1180 3260 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1178 3259 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --99.49 2.07 Td -(core_req_write[0][2..0]) Tj -ET -Q -1170 3280 m -1180 3280 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1178 3279 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --99.49 2.07 Td -(core_req_write[1][2..0]) Tj -ET -Q -1170 3000 m -1180 3000 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1178 2999 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --103.95 2.07 Td -(core_req_addr[0][31..0]) Tj -ET -Q -1170 3020 m -1180 3020 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1178 3019 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --103.95 2.07 Td -(core_req_addr[1][31..0]) Tj -ET -Q -1170 3040 m -1180 3040 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1178 3039 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --108.96 2.07 Td -(core_req_data[0][127..0]) Tj -ET -Q -1170 3060 m -1180 3060 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1178 3059 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --108.96 2.07 Td -(core_req_data[1][127..0]) Tj -ET -Q -1170 3100 m -1180 3100 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1178 3099 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --76.15 2.07 Td -(core_req_rd[4..0]) Tj -ET -Q -1170 3220 m -1180 3220 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1178 3219 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --91.16 2.07 Td -(core_req_wb[0][1..0]) Tj -ET -Q -1170 3240 m -1180 3240 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1178 3239 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --91.16 2.07 Td -(core_req_wb[1][1..0]) Tj -ET -Q -1170 3080 m -1180 3080 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1178 3079 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --83.38 2.07 Td -(core_req_pc[31..0]) Tj -ET -Q -1170 3200 m -1180 3200 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1178 3199 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --113.94 2.07 Td -(core_req_warp_num[2..0]) Tj -ET -Q -1170 3340 m -1180 3340 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1178 3339 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --110.6 2.07 Td -(dram_fill_rsp_addr[31..0]) Tj -ET -Q -1170 3360 m -1180 3360 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1178 3359 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --126.73 2.07 Td -(dram_fill_rsp_data[0][127..0]) Tj -ET -Q -1170 3460 m -1180 3460 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1178 3459 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --89.5 2.07 Td -(snp_req_addr[31..0]) Tj -ET -Q -1 w -1250 3060 m -1240 3060 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1246 3059 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(core_req_full) Tj -ET -Q -1250 3180 m -1240 3180 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1246 3179 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(core_rsp_valid) Tj -ET -Q -1250 3260 m -1240 3260 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1246 3259 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(dram_fill_req_valid) Tj -ET -Q -1250 3280 m -1240 3280 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1246 3279 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(dram_fill_rsp_ready) Tj -ET -Q -1250 3340 m -1240 3340 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1246 3339 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(dram_wb_req_valid) Tj -ET -Q -1250 3400 m -1240 3400 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1246 3399 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(snp_req_full) Tj -ET -Q -1250 3380 m -1240 3380 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1246 3379 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(snp_fwd_valid) Tj -ET -Q -3 w -1250 3160 m -1240 3160 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1246 3159 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(core_rsp_tid[0..0]) Tj -ET -Q -1250 3140 m -1240 3140 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1246 3139 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(core_rsp_rd[4..0]) Tj -ET -Q -1250 3220 m -1240 3220 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1246 3219 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(core_rsp_wb[1..0]) Tj -ET -Q -1250 3200 m -1240 3200 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1246 3199 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(core_rsp_warp_num[2..0]) Tj -ET -Q -1250 3100 m -1240 3100 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1246 3099 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(core_rsp_data[127..0]) Tj -ET -Q -1250 3120 m -1240 3120 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1246 3119 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(core_rsp_pc[31..0]) Tj -ET -Q -1250 3080 m -1240 3080 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1246 3079 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(core_rsp_addr[31..0]) Tj -ET -Q -1250 3240 m -1240 3240 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1246 3239 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(dram_fill_req_addr[31..0]) Tj -ET -Q -1250 3300 m -1240 3300 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1246 3299 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(dram_wb_req_addr[31..0]) Tj -ET -Q -1250 3320 m -1240 3320 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1246 3319 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(dram_wb_req_data[0][127..0]) Tj -ET -Q -1250 3360 m -1240 3360 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1246 3359 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(snp_fwd_addr[31..0]) Tj -ET -Q -1 w -1190 2980 m -1180 2980 l -S -1190 3420 m -1180 3420 l -S -1190 3160 m -1180 3160 l -S -1190 3300 m -1180 3300 l -S -1190 3320 m -1180 3320 l -S -1190 3380 m -1180 3380 l -S -1190 3400 m -1180 3400 l -S -1190 3480 m -1180 3480 l -S -1190 3440 m -1180 3440 l -S -3 w -1190 3180 m -1180 3180 l -S -1190 3120 m -1180 3120 l -S -1190 3140 m -1180 3140 l -S -1190 3260 m -1180 3260 l -S -1190 3280 m -1180 3280 l -S -1190 3000 m -1180 3000 l -S -1190 3020 m -1180 3020 l -S -1190 3040 m -1180 3040 l -S -1190 3060 m -1180 3060 l -S -1190 3100 m -1180 3100 l -S -1190 3220 m -1180 3220 l -S -1190 3240 m -1180 3240 l -S -1190 3080 m -1180 3080 l -S -1190 3200 m -1180 3200 l -S -1190 3340 m -1180 3340 l -S -1190 3360 m -1180 3360 l -S -1190 3460 m -1180 3460 l -S -1 w -1230 3060 m -1240 3060 l -S -1230 3180 m -1240 3180 l -S -1230 3260 m -1240 3260 l -S -1230 3280 m -1240 3280 l -S -1230 3340 m -1240 3340 l -S -1230 3400 m -1240 3400 l -S -1230 3380 m -1240 3380 l -S -3 w -1230 3160 m -1240 3160 l -S -1230 3140 m -1240 3140 l -S -1230 3220 m -1240 3220 l -S -1230 3200 m -1240 3200 l -S -1230 3100 m -1240 3100 l -S -1230 3120 m -1240 3120 l -S -1230 3080 m -1240 3080 l -S -1230 3240 m -1240 3240 l -S -1230 3300 m -1240 3300 l -S -1230 3320 m -1240 3320 l -S -1230 3360 m -1240 3360 l -S -0.000 0.000 1.000 RG -4784 3247 m -4791 3240 l -4784 3233 l -S -4770 3240 m -4791 3240 l -S -q -0.000 0.000 1.000 rg -1 0 0 1 4795 3256 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm -0 -4.308 Td -([1-2]) Tj -ET -Q -q -0.176 0.176 0.176 rg -1 0 0 1 4795 3240 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm -0 -4.308 Td -(dram_fill_req_addr[31..0]) Tj -ET -Q -4784 3287 m -4791 3280 l -4784 3273 l -S -4770 3280 m -4791 3280 l -S -q -0.000 0.000 1.000 rg -1 0 0 1 4795 3296 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm -0 -4.308 Td -([1-2]) Tj -ET -Q -q -0.176 0.176 0.176 rg -1 0 0 1 4795 3280 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm -0 -4.308 Td -(dram_wb_req_addr[31..0]) Tj -ET -Q -1 w -0 3380 m --14 3380 l --21 3387 l -S --14 3380 m --21 3373 l -S -q -0.000 0.000 1.000 rg -1 0 0 1 -25 3396 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm --23.352 -4.308 Td -([1,3]) Tj -ET -Q -q -0.176 0.176 0.176 rg -1 0 0 1 -25 3380 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm --212.064 -4.308 Td -([6].curr_bank_dram_fill_rsp_valid:OUT0) Tj -ET -Q -3 w -4784 3327 m -4791 3320 l -4784 3313 l -S -4770 3320 m -4791 3320 l -S -q -0.000 0.000 1.000 rg -1 0 0 1 4795 3336 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm -0 -4.308 Td -([1-2]) Tj -ET -Q -q -0.176 0.176 0.176 rg -1 0 0 1 4795 3320 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm -0 -4.308 Td -(dram_wb_req_data[0][127..0]) Tj -ET -Q -4770 3440 m -4770 3433 l -4784 3433 l -4791 3440 l -4784 3447 l -4770 3447 l -h S -q -0.000 0.000 0.000 rg -1 0 0 1 4799 3440 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm -0 -4.308 Td -(snp_fwd_addr[31..0]) Tj -ET -Q -q -0.000 0.000 0.000 rg -4485 3333 60 222 re -f -Q -q -0.506 0.749 0.373 rg -4480 3328 60 222 re -f -Q -1 w -0.176 0.176 0.176 RG -4480 3328 60 222 re -S -3 w -4491 3333 m -4491 3345 l -S -4485 3339 m -4497 3339 l -S -1 w -4483 3331 16 16 re -S -q -0.000 0.000 0.000 rg -1 0 0 1 4510 3326 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm --34.35 2.484 Td -(snp_fwd_arb) Tj -ET -Q -q -0.176 0.176 0.176 rg -1 0 0 1 4510 3556 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm --49.686 -8.616 Td -(\(VX_snp_fwd_arb\)) Tj -ET -Q -0.024 0.278 0.435 RG -4470 3540 m -4480 3540 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 4478 3539 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --67.81 2.07 Td -(snp_fwd_ready) Tj -ET -Q -3 w -4470 3520 m -4480 3520 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 4478 3519 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --132.85 2.07 Td -(per_bank_snp_fwd_valid[7..0]) Tj -ET -Q -4470 3360 m -4480 3360 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 4478 3359 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --148.98 2.07 Td -(per_bank_snp_fwd_addr[0][31..0]) Tj -ET -Q -4470 3380 m -4480 3380 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 4478 3379 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --148.98 2.07 Td -(per_bank_snp_fwd_addr[1][31..0]) Tj -ET -Q -4470 3400 m -4480 3400 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 4478 3399 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --148.98 2.07 Td -(per_bank_snp_fwd_addr[2][31..0]) Tj -ET -Q -4470 3420 m -4480 3420 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 4478 3419 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --148.98 2.07 Td -(per_bank_snp_fwd_addr[3][31..0]) Tj -ET -Q -4470 3440 m -4480 3440 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 4478 3439 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --148.98 2.07 Td -(per_bank_snp_fwd_addr[4][31..0]) Tj -ET -Q -4470 3460 m -4480 3460 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 4478 3459 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --148.98 2.07 Td -(per_bank_snp_fwd_addr[5][31..0]) Tj -ET -Q -4470 3480 m -4480 3480 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 4478 3479 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --148.98 2.07 Td -(per_bank_snp_fwd_addr[6][31..0]) Tj -ET -Q -4470 3500 m -4480 3500 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 4478 3499 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --148.98 2.07 Td -(per_bank_snp_fwd_addr[7][31..0]) Tj -ET -Q -1 w -4550 3460 m -4540 3460 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 4546 3459 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(snp_fwd_valid) Tj -ET -Q -3 w -4550 3420 m -4540 3420 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 4546 3419 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(per_bank_snp_fwd_pop[7..0]) Tj -ET -Q -4550 3440 m -4540 3440 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 4546 3439 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(snp_fwd_addr[31..0]) Tj -ET -Q -1 w -4490 3540 m -4480 3540 l -S -3 w -4490 3520 m -4480 3520 l -S -4490 3360 m -4480 3360 l -S -4490 3380 m -4480 3380 l -S -4490 3400 m -4480 3400 l -S -4490 3420 m -4480 3420 l -S -4490 3440 m -4480 3440 l -S -4490 3460 m -4480 3460 l -S -4490 3480 m -4480 3480 l -S -4490 3500 m -4480 3500 l -S -1 w -4530 3460 m -4540 3460 l -S -3 w -4530 3420 m -4540 3420 l -S -4530 3440 m -4540 3440 l -S -1 w -0.000 0.000 1.000 RG -0 3480 m --14 3480 l --21 3487 l -S --14 3480 m --21 3473 l -S -q -0.000 0.000 1.000 rg -1 0 0 1 -25 3496 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm --23.352 -4.308 Td -([1,3]) Tj -ET -Q -q -0.176 0.176 0.176 rg -1 0 0 1 -25 3480 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm --155.4 -4.308 Td -([6].curr_bank_snp_req:OUT0) Tj -ET -Q -4770 3460 m -4770 3453 l -4784 3453 l -4791 3460 l -4784 3467 l -4770 3467 l -h S -q -0.000 0.000 0.000 rg -1 0 0 1 4799 3460 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm -0 -4.308 Td -(snp_fwd_valid) Tj -ET -Q -0 3540 m --7 3547 l --21 3547 l --21 3533 l --7 3533 l -h S -q -0.000 0.000 0.000 rg -1 0 0 1 -25 3540 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm --81.372 -4.308 Td -(snp_fwd_ready) Tj -ET -Q -3 w -0 3600 m --7 3607 l --21 3607 l --21 3593 l --7 3593 l -h S -q -0.000 0.000 0.000 rg -1 0 0 1 -25 3600 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm --130.752 -4.308 Td -(core_req_data[0][127..0]) Tj -ET -Q -0 3680 m --7 3687 l --21 3687 l --21 3673 l --7 3673 l -h S -q -0.000 0.000 0.000 rg -1 0 0 1 -25 3680 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm --118.068 -4.308 Td -(core_req_read[0][2..0]) Tj -ET -Q -0 3700 m --7 3707 l --21 3707 l --21 3693 l --7 3693 l -h S -q -0.000 0.000 0.000 rg -1 0 0 1 -25 3700 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm --118.068 -4.308 Td -(core_req_read[1][2..0]) Tj -ET -Q -1 w -4784 3607 m -4791 3600 l -4784 3593 l -S -4770 3600 m -4791 3600 l -S -q -0.000 0.000 1.000 rg -1 0 0 1 4795 3616 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm -0 -4.308 Td -([1,3]) Tj -ET -Q -q -0.176 0.176 0.176 rg -1 0 0 1 4795 3600 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm -0 -4.308 Td -(reduce_or_0:OUT0) Tj -ET -Q -3 w -0 3780 m --7 3787 l --21 3787 l --21 3773 l --7 3773 l -h S -q -0.000 0.000 0.000 rg -1 0 0 1 -25 3780 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm --119.388 -4.308 Td -(core_req_write[0][2..0]) Tj -ET -Q -0 3800 m --7 3807 l --21 3807 l --21 3793 l --7 3793 l -h S -q -0.000 0.000 0.000 rg -1 0 0 1 -25 3800 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm --119.388 -4.308 Td -(core_req_write[1][2..0]) Tj -ET -Q -q -0.000 0.000 0.000 rg -1185 3633 60 542 re -f -Q -q -0.506 0.749 0.373 rg -1180 3628 60 542 re -f -Q -1 w -0.176 0.176 0.176 RG -1180 3628 60 542 re -S -3 w -1191 3633 m -1191 3645 l -S -1185 3639 m -1197 3639 l -S -1 w -1183 3631 16 16 re -S -q -0.000 0.000 0.000 rg -1 0 0 1 1210 3626 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm --21.348 2.484 Td -([7].bank) Tj -ET -Q -q -0.176 0.176 0.176 rg -1 0 0 1 1210 4176 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm --28.344 -8.616 Td -(\(VX_bank\)) Tj -ET -Q -0.024 0.278 0.435 RG -1170 3660 m -1180 3660 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1178 3659 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --12.22 2.07 Td -(clk) Tj -ET -Q -1170 4100 m -1180 4100 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1178 4099 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --22.23 2.07 Td -(reset) Tj -ET -Q -1180 3840 m -1180 3838.34 1178.66 3837 1177 3837 c -1175.34 3837 1174 3838.34 1174 3840 c -1174 3841.66 1175.34 3843 1177 3843 c -1178.66 3843 1180 3841.66 1180 3840 c -S -1170 3840 m -1174 3840 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1174 3839 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --70.03 2.07 Td -(core_req_ready) Tj -ET -Q -1170 3980 m -1180 3980 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1178 3979 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --61.14 2.07 Td -(core_rsp_pop) Tj -ET -Q -1170 4000 m -1180 4000 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1178 3999 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --76.13 2.07 Td -(dram_fill_req_full) Tj -ET -Q -1170 4060 m -1180 4060 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1178 4059 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --83.35 2.07 Td -(dram_fill_rsp_valid) Tj -ET -Q -1170 4080 m -1180 4080 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1178 4079 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --83.37 2.07 Td -(dram_wb_req_pop) Tj -ET -Q -1170 4160 m -1180 4160 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1178 4159 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --62.25 2.07 Td -(snp_req_valid) Tj -ET -Q -1170 4120 m -1180 4120 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1178 4119 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --59.48 2.07 Td -(snp_fwd_pop) Tj -ET -Q -3 w -1170 3860 m -1180 3860 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1178 3859 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --92.82 2.07 Td -(core_req_valids[1..0]) Tj -ET -Q -1170 3800 m -1180 3800 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1178 3799 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --98.39 2.07 Td -(core_req_read[0][2..0]) Tj -ET -Q -1170 3820 m -1180 3820 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1178 3819 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --98.39 2.07 Td -(core_req_read[1][2..0]) Tj -ET -Q -1170 3940 m -1180 3940 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1178 3939 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --99.49 2.07 Td -(core_req_write[0][2..0]) Tj -ET -Q -1170 3960 m -1180 3960 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1178 3959 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --99.49 2.07 Td -(core_req_write[1][2..0]) Tj -ET -Q -1170 3680 m -1180 3680 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1178 3679 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --103.95 2.07 Td -(core_req_addr[0][31..0]) Tj -ET -Q -1170 3700 m -1180 3700 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1178 3699 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --103.95 2.07 Td -(core_req_addr[1][31..0]) Tj -ET -Q -1170 3720 m -1180 3720 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1178 3719 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --108.96 2.07 Td -(core_req_data[0][127..0]) Tj -ET -Q -1170 3740 m -1180 3740 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1178 3739 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --108.96 2.07 Td -(core_req_data[1][127..0]) Tj -ET -Q -1170 3780 m -1180 3780 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1178 3779 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --76.15 2.07 Td -(core_req_rd[4..0]) Tj -ET -Q -1170 3900 m -1180 3900 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1178 3899 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --91.16 2.07 Td -(core_req_wb[0][1..0]) Tj -ET -Q -1170 3920 m -1180 3920 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1178 3919 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --91.16 2.07 Td -(core_req_wb[1][1..0]) Tj -ET -Q -1170 3760 m -1180 3760 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1178 3759 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --83.38 2.07 Td -(core_req_pc[31..0]) Tj -ET -Q -1170 3880 m -1180 3880 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1178 3879 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --113.94 2.07 Td -(core_req_warp_num[2..0]) Tj -ET -Q -1170 4020 m -1180 4020 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1178 4019 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --110.6 2.07 Td -(dram_fill_rsp_addr[31..0]) Tj -ET -Q -1170 4040 m -1180 4040 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1178 4039 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --126.73 2.07 Td -(dram_fill_rsp_data[0][127..0]) Tj -ET -Q -1170 4140 m -1180 4140 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1178 4139 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --89.5 2.07 Td -(snp_req_addr[31..0]) Tj -ET -Q -1 w -1250 3740 m -1240 3740 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1246 3739 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(core_req_full) Tj -ET -Q -1250 3860 m -1240 3860 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1246 3859 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(core_rsp_valid) Tj -ET -Q -1250 3940 m -1240 3940 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1246 3939 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(dram_fill_req_valid) Tj -ET -Q -1250 3960 m -1240 3960 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1246 3959 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(dram_fill_rsp_ready) Tj -ET -Q -1250 4020 m -1240 4020 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1246 4019 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(dram_wb_req_valid) Tj -ET -Q -1250 4080 m -1240 4080 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1246 4079 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(snp_req_full) Tj -ET -Q -1250 4060 m -1240 4060 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1246 4059 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(snp_fwd_valid) Tj -ET -Q -3 w -1250 3840 m -1240 3840 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1246 3839 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(core_rsp_tid[0..0]) Tj -ET -Q -1250 3820 m -1240 3820 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1246 3819 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(core_rsp_rd[4..0]) Tj -ET -Q -1250 3900 m -1240 3900 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1246 3899 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(core_rsp_wb[1..0]) Tj -ET -Q -1250 3880 m -1240 3880 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1246 3879 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(core_rsp_warp_num[2..0]) Tj -ET -Q -1250 3780 m -1240 3780 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1246 3779 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(core_rsp_data[127..0]) Tj -ET -Q -1250 3800 m -1240 3800 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1246 3799 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(core_rsp_pc[31..0]) Tj -ET -Q -1250 3760 m -1240 3760 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1246 3759 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(core_rsp_addr[31..0]) Tj -ET -Q -1250 3920 m -1240 3920 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1246 3919 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(dram_fill_req_addr[31..0]) Tj -ET -Q -1250 3980 m -1240 3980 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1246 3979 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(dram_wb_req_addr[31..0]) Tj -ET -Q -1250 4000 m -1240 4000 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1246 3999 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(dram_wb_req_data[0][127..0]) Tj -ET -Q -1250 4040 m -1240 4040 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 1246 4039 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(snp_fwd_addr[31..0]) Tj -ET -Q -1 w -1190 3660 m -1180 3660 l -S -1190 4100 m -1180 4100 l -S -1190 3840 m -1180 3840 l -S -1190 3980 m -1180 3980 l -S -1190 4000 m -1180 4000 l -S -1190 4060 m -1180 4060 l -S -1190 4080 m -1180 4080 l -S -1190 4160 m -1180 4160 l -S -1190 4120 m -1180 4120 l -S -3 w -1190 3860 m -1180 3860 l -S -1190 3800 m -1180 3800 l -S -1190 3820 m -1180 3820 l -S -1190 3940 m -1180 3940 l -S -1190 3960 m -1180 3960 l -S -1190 3680 m -1180 3680 l -S -1190 3700 m -1180 3700 l -S -1190 3720 m -1180 3720 l -S -1190 3740 m -1180 3740 l -S -1190 3780 m -1180 3780 l -S -1190 3900 m -1180 3900 l -S -1190 3920 m -1180 3920 l -S -1190 3760 m -1180 3760 l -S -1190 3880 m -1180 3880 l -S -1190 4020 m -1180 4020 l -S -1190 4040 m -1180 4040 l -S -1190 4140 m -1180 4140 l -S -1 w -1230 3740 m -1240 3740 l -S -1230 3860 m -1240 3860 l -S -1230 3940 m -1240 3940 l -S -1230 3960 m -1240 3960 l -S -1230 4020 m -1240 4020 l -S -1230 4080 m -1240 4080 l -S -1230 4060 m -1240 4060 l -S -3 w -1230 3840 m -1240 3840 l -S -1230 3820 m -1240 3820 l -S -1230 3900 m -1240 3900 l -S -1230 3880 m -1240 3880 l -S -1230 3780 m -1240 3780 l -S -1230 3800 m -1240 3800 l -S -1230 3760 m -1240 3760 l -S -1230 3920 m -1240 3920 l -S -1230 3980 m -1240 3980 l -S -1230 4000 m -1240 4000 l -S -1230 4040 m -1240 4040 l -S -0.000 0.000 1.000 RG -4784 3927 m -4791 3920 l -4784 3913 l -S -4770 3920 m -4791 3920 l -S -q -0.000 0.000 1.000 rg -1 0 0 1 4795 3936 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm -0 -4.308 Td -([1-2]) Tj -ET -Q -q -0.176 0.176 0.176 rg -1 0 0 1 4795 3920 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm -0 -4.308 Td -(dram_fill_req_addr[31..0]) Tj -ET -Q -1 w -0 4060 m --14 4060 l --21 4067 l -S --14 4060 m --21 4053 l -S -q -0.000 0.000 1.000 rg -1 0 0 1 -25 4076 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm --23.352 -4.308 Td -([1,3]) Tj -ET -Q -q -0.176 0.176 0.176 rg -1 0 0 1 -25 4060 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm --212.064 -4.308 Td -([7].curr_bank_dram_fill_rsp_valid:OUT0) Tj -ET -Q -3 w -4784 3987 m -4791 3980 l -4784 3973 l -S -4770 3980 m -4791 3980 l -S -q -0.000 0.000 1.000 rg -1 0 0 1 4795 3996 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm -0 -4.308 Td -([1-2]) Tj -ET -Q -q -0.176 0.176 0.176 rg -1 0 0 1 4795 3980 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm -0 -4.308 Td -(dram_wb_req_addr[31..0]) Tj -ET -Q -1 w -0 4220 m --14 4220 l --21 4227 l -S --14 4220 m --21 4213 l -S -q -0.000 0.000 1.000 rg -1 0 0 1 -25 4236 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm --23.352 -4.308 Td -([1,3]) Tj -ET -Q -q -0.176 0.176 0.176 rg -1 0 0 1 -25 4220 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm --155.4 -4.308 Td -([7].curr_bank_snp_req:OUT0) Tj -ET -Q -3 w -4784 4027 m -4791 4020 l -4784 4013 l -S -4770 4020 m -4791 4020 l -S -q -0.000 0.000 1.000 rg -1 0 0 1 4795 4036 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm -0 -4.308 Td -([1-2]) Tj -ET -Q -q -0.176 0.176 0.176 rg -1 0 0 1 4795 4020 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm -0 -4.308 Td -(dram_wb_req_data[0][127..0]) Tj -ET -Q -0 4180 m --14 4180 l --21 4187 l -S --14 4180 m --21 4173 l -S -q -0.000 0.000 1.000 rg -1 0 0 1 -25 4196 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm --23.352 -4.308 Td -([1,3]) Tj -ET -Q -q -0.176 0.176 0.176 rg -1 0 0 1 -25 4180 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm --107.4 -4.308 Td -(snp_req_addr[31..0]) Tj -ET -Q -0 3760 m --7 3767 l --21 3767 l --21 3753 l --7 3753 l -h S -q -0.000 0.000 0.000 rg -1 0 0 1 -25 3760 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm --109.392 -4.308 Td -(core_req_wb[1][1..0]) Tj -ET -Q -1 w -0 3560 m --14 3560 l --21 3567 l -S --14 3560 m --21 3553 l -S -q -0.000 0.000 1.000 rg -1 0 0 1 -25 3576 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm --24.012 -4.308 Td -([1-2]) Tj -ET -Q -q -0.176 0.176 0.176 rg -1 0 0 1 -25 3560 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm --14.664 -4.308 Td -(clk) Tj -ET -Q -q -0.000 0.000 0.000 rg -2815 4153 60 542 re -f -Q -q -0.506 0.749 0.373 rg -2810 4148 60 542 re -f -Q -0.176 0.176 0.176 RG -2810 4148 60 542 re -S -3 w -2821 4153 m -2821 4165 l -S -2815 4159 m -2827 4159 l -S -1 w -2813 4151 16 16 re -S -q -0.000 0.000 0.000 rg -1 0 0 1 2840 4146 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm --21.348 2.484 Td -([0].bank) Tj -ET -Q -q -0.176 0.176 0.176 rg -1 0 0 1 2840 4696 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm --28.344 -8.616 Td -(\(VX_bank\)) Tj -ET -Q -0.024 0.278 0.435 RG -2800 4180 m -2810 4180 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 2808 4179 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --12.22 2.07 Td -(clk) Tj -ET -Q -2800 4620 m -2810 4620 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 2808 4619 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --22.23 2.07 Td -(reset) Tj -ET -Q -2810 4360 m -2810 4358.34 2808.66 4357 2807 4357 c -2805.34 4357 2804 4358.34 2804 4360 c -2804 4361.66 2805.34 4363 2807 4363 c -2808.66 4363 2810 4361.66 2810 4360 c -S -2800 4360 m -2804 4360 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 2804 4359 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --70.03 2.07 Td -(core_req_ready) Tj -ET -Q -2800 4500 m -2810 4500 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 2808 4499 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --61.14 2.07 Td -(core_rsp_pop) Tj -ET -Q -2800 4520 m -2810 4520 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 2808 4519 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --76.13 2.07 Td -(dram_fill_req_full) Tj -ET -Q -2800 4580 m -2810 4580 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 2808 4579 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --83.35 2.07 Td -(dram_fill_rsp_valid) Tj -ET -Q -2800 4600 m -2810 4600 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 2808 4599 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --83.37 2.07 Td -(dram_wb_req_pop) Tj -ET -Q -2800 4680 m -2810 4680 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 2808 4679 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --62.25 2.07 Td -(snp_req_valid) Tj -ET -Q -2800 4640 m -2810 4640 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 2808 4639 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --59.48 2.07 Td -(snp_fwd_pop) Tj -ET -Q -3 w -2800 4380 m -2810 4380 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 2808 4379 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --92.82 2.07 Td -(core_req_valids[1..0]) Tj -ET -Q -2800 4320 m -2810 4320 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 2808 4319 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --98.39 2.07 Td -(core_req_read[0][2..0]) Tj -ET -Q -2800 4340 m -2810 4340 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 2808 4339 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --98.39 2.07 Td -(core_req_read[1][2..0]) Tj -ET -Q -2800 4460 m -2810 4460 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 2808 4459 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --99.49 2.07 Td -(core_req_write[0][2..0]) Tj -ET -Q -2800 4480 m -2810 4480 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 2808 4479 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --99.49 2.07 Td -(core_req_write[1][2..0]) Tj -ET -Q -2800 4200 m -2810 4200 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 2808 4199 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --103.95 2.07 Td -(core_req_addr[0][31..0]) Tj -ET -Q -2800 4220 m -2810 4220 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 2808 4219 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --103.95 2.07 Td -(core_req_addr[1][31..0]) Tj -ET -Q -2800 4240 m -2810 4240 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 2808 4239 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --108.96 2.07 Td -(core_req_data[0][127..0]) Tj -ET -Q -2800 4260 m -2810 4260 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 2808 4259 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --108.96 2.07 Td -(core_req_data[1][127..0]) Tj -ET -Q -2800 4300 m -2810 4300 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 2808 4299 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --76.15 2.07 Td -(core_req_rd[4..0]) Tj -ET -Q -2800 4420 m -2810 4420 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 2808 4419 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --91.16 2.07 Td -(core_req_wb[0][1..0]) Tj -ET -Q -2800 4440 m -2810 4440 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 2808 4439 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --91.16 2.07 Td -(core_req_wb[1][1..0]) Tj -ET -Q -2800 4280 m -2810 4280 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 2808 4279 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --83.38 2.07 Td -(core_req_pc[31..0]) Tj -ET -Q -2800 4400 m -2810 4400 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 2808 4399 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --113.94 2.07 Td -(core_req_warp_num[2..0]) Tj -ET -Q -2800 4540 m -2810 4540 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 2808 4539 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --110.6 2.07 Td -(dram_fill_rsp_addr[31..0]) Tj -ET -Q -2800 4560 m -2810 4560 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 2808 4559 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --126.73 2.07 Td -(dram_fill_rsp_data[0][127..0]) Tj -ET -Q -2800 4660 m -2810 4660 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 2808 4659 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --89.5 2.07 Td -(snp_req_addr[31..0]) Tj -ET -Q -1 w -2880 4260 m -2870 4260 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 2876 4259 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(core_req_full) Tj -ET -Q -2880 4380 m -2870 4380 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 2876 4379 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(core_rsp_valid) Tj -ET -Q -2880 4460 m -2870 4460 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 2876 4459 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(dram_fill_req_valid) Tj -ET -Q -2880 4480 m -2870 4480 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 2876 4479 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(dram_fill_rsp_ready) Tj -ET -Q -2880 4540 m -2870 4540 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 2876 4539 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(dram_wb_req_valid) Tj -ET -Q -2880 4600 m -2870 4600 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 2876 4599 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(snp_req_full) Tj -ET -Q -2880 4580 m -2870 4580 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 2876 4579 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(snp_fwd_valid) Tj -ET -Q -3 w -2880 4360 m -2870 4360 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 2876 4359 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(core_rsp_tid[0..0]) Tj -ET -Q -2880 4340 m -2870 4340 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 2876 4339 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(core_rsp_rd[4..0]) Tj -ET -Q -2880 4420 m -2870 4420 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 2876 4419 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(core_rsp_wb[1..0]) Tj -ET -Q -2880 4400 m -2870 4400 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 2876 4399 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(core_rsp_warp_num[2..0]) Tj -ET -Q -2880 4300 m -2870 4300 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 2876 4299 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(core_rsp_data[127..0]) Tj -ET -Q -2880 4320 m -2870 4320 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 2876 4319 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(core_rsp_pc[31..0]) Tj -ET -Q -2880 4280 m -2870 4280 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 2876 4279 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(core_rsp_addr[31..0]) Tj -ET -Q -2880 4440 m -2870 4440 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 2876 4439 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(dram_fill_req_addr[31..0]) Tj -ET -Q -2880 4500 m -2870 4500 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 2876 4499 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(dram_wb_req_addr[31..0]) Tj -ET -Q -2880 4520 m -2870 4520 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 2876 4519 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(dram_wb_req_data[0][127..0]) Tj -ET -Q -2880 4560 m -2870 4560 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 2876 4559 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(snp_fwd_addr[31..0]) Tj -ET -Q -1 w -2820 4180 m -2810 4180 l -S -2820 4620 m -2810 4620 l -S -2820 4360 m -2810 4360 l -S -2820 4500 m -2810 4500 l -S -2820 4520 m -2810 4520 l -S -2820 4580 m -2810 4580 l -S -2820 4600 m -2810 4600 l -S -2820 4680 m -2810 4680 l -S -2820 4640 m -2810 4640 l -S -3 w -2820 4380 m -2810 4380 l -S -2820 4320 m -2810 4320 l -S -2820 4340 m -2810 4340 l -S -2820 4460 m -2810 4460 l -S -2820 4480 m -2810 4480 l -S -2820 4200 m -2810 4200 l -S -2820 4220 m -2810 4220 l -S -2820 4240 m -2810 4240 l -S -2820 4260 m -2810 4260 l -S -2820 4300 m -2810 4300 l -S -2820 4420 m -2810 4420 l -S -2820 4440 m -2810 4440 l -S -2820 4280 m -2810 4280 l -S -2820 4400 m -2810 4400 l -S -2820 4540 m -2810 4540 l -S -2820 4560 m -2810 4560 l -S -2820 4660 m -2810 4660 l -S -1 w -2860 4260 m -2870 4260 l -S -2860 4380 m -2870 4380 l -S -2860 4460 m -2870 4460 l -S -2860 4480 m -2870 4480 l -S -2860 4540 m -2870 4540 l -S -2860 4600 m -2870 4600 l -S -2860 4580 m -2870 4580 l -S -3 w -2860 4360 m -2870 4360 l -S -2860 4340 m -2870 4340 l -S -2860 4420 m -2870 4420 l -S -2860 4400 m -2870 4400 l -S -2860 4300 m -2870 4300 l -S -2860 4320 m -2870 4320 l -S -2860 4280 m -2870 4280 l -S -2860 4440 m -2870 4440 l -S -2860 4500 m -2870 4500 l -S -2860 4520 m -2870 4520 l -S -2860 4560 m -2870 4560 l -S -1 w -0.000 0.000 1.000 RG -0 3820 m --14 3820 l --21 3827 l -S --14 3820 m --21 3813 l -S -q -0.000 0.000 1.000 rg -1 0 0 1 -25 3836 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm --24.012 -4.308 Td -([1-2]) Tj -ET -Q -q -0.176 0.176 0.176 rg -1 0 0 1 -25 3820 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm --45.36 -4.308 Td -(dfqq_full) Tj -ET -Q -3 w -0 3900 m --7 3907 l --21 3907 l --21 3893 l --7 3893 l -h S -q -0.000 0.000 0.000 rg -1 0 0 1 -25 3900 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm --127.404 -4.308 Td -(dram_rsp_data[0][31..0]) Tj -ET -Q -4784 4467 m -4791 4460 l -4784 4453 l -S -4770 4460 m -4791 4460 l -S -q -0.000 0.000 1.000 rg -1 0 0 1 4795 4476 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm -0 -4.308 Td -([1-2]) Tj -ET -Q -q -0.176 0.176 0.176 rg -1 0 0 1 4795 4460 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm -0 -4.308 Td -(@dram_fill_req_valid_13632) Tj -ET -Q -0 3920 m --7 3927 l --21 3927 l --21 3913 l --7 3913 l -h S -q -0.000 0.000 0.000 rg -1 0 0 1 -25 3920 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm --127.404 -4.308 Td -(dram_rsp_data[1][31..0]) Tj -ET -Q -0 3620 m --7 3627 l --21 3627 l --21 3613 l --7 3613 l -h S -q -0.000 0.000 0.000 rg -1 0 0 1 -25 3620 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm --130.752 -4.308 Td -(core_req_data[1][127..0]) Tj -ET -Q -0 3940 m --7 3947 l --21 3947 l --21 3933 l --7 3933 l -h S -q -0.000 0.000 0.000 rg -1 0 0 1 -25 3940 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm --127.404 -4.308 Td -(dram_rsp_data[2][31..0]) Tj -ET -Q -0 3640 m --7 3647 l --21 3647 l --21 3633 l --7 3633 l -h S -q -0.000 0.000 0.000 rg -1 0 0 1 -25 3640 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm --100.056 -4.308 Td -(core_req_pc[31..0]) Tj -ET -Q -0 3660 m --7 3667 l --21 3667 l --21 3653 l --7 3653 l -h S -q -0.000 0.000 0.000 rg -1 0 0 1 -25 3660 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm --91.38 -4.308 Td -(core_req_rd[4..0]) Tj -ET -Q -0 3960 m --7 3967 l --21 3967 l --21 3953 l --7 3953 l -h S -q -0.000 0.000 0.000 rg -1 0 0 1 -25 3960 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm --127.404 -4.308 Td -(dram_rsp_data[3][31..0]) Tj -ET -Q -0 3720 m --7 3727 l --21 3727 l --21 3713 l --7 3713 l -h S -q -0.000 0.000 0.000 rg -1 0 0 1 -25 3720 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm --136.728 -4.308 Td -(core_req_warp_num[2..0]) Tj -ET -Q -4784 4587 m -4791 4580 l -4784 4573 l -S -4770 4580 m -4791 4580 l -S -q -0.000 0.000 1.000 rg -1 0 0 1 4795 4596 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm -0 -4.308 Td -([1-2]) Tj -ET -Q -q -0.176 0.176 0.176 rg -1 0 0 1 4795 4580 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm -0 -4.308 Td -(@dram_wb_req_valid_13896) Tj -ET -Q -0 3740 m --7 3747 l --21 3747 l --21 3733 l --7 3733 l -h S -q -0.000 0.000 0.000 rg -1 0 0 1 -25 3740 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm --109.392 -4.308 Td -(core_req_wb[0][1..0]) Tj -ET -Q -1 w -0 4140 m --14 4140 l --21 4147 l -S --14 4140 m --21 4133 l -S -q -0.000 0.000 1.000 rg -1 0 0 1 -25 4156 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm --24.012 -4.308 Td -([1-2]) Tj -ET -Q -q -0.176 0.176 0.176 rg -1 0 0 1 -25 4140 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm --26.676 -4.308 Td -(reset) Tj -ET -Q -3 w -4784 4427 m -4791 4420 l -4784 4413 l -S -4770 4420 m -4791 4420 l -S -q -0.000 0.000 1.000 rg -1 0 0 1 4795 4436 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm -0 -4.308 Td -([1-2]) Tj -ET -Q -q -0.176 0.176 0.176 rg -1 0 0 1 4795 4420 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm -0 -4.308 Td -(dram_fill_req_addr[31..0]) Tj -ET -Q -0 3860 m --14 3860 l --21 3867 l -S --14 3860 m --21 3853 l -S -q -0.000 0.000 1.000 rg -1 0 0 1 -25 3876 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm --23.352 -4.308 Td -([1,3]) Tj -ET -Q -q -0.176 0.176 0.176 rg -1 0 0 1 -25 3860 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm --114.72 -4.308 Td -(dram_rsp_addr[31..0]) Tj -ET -Q -4784 4507 m -4791 4500 l -4784 4493 l -S -4770 4500 m -4791 4500 l -S -q -0.000 0.000 1.000 rg -1 0 0 1 4795 4516 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm -0 -4.308 Td -([1-2]) Tj -ET -Q -q -0.176 0.176 0.176 rg -1 0 0 1 4795 4500 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm -0 -4.308 Td -(dram_wb_req_addr[31..0]) Tj -ET -Q -0 4100 m --14 4100 l --21 4107 l -S --14 4100 m --21 4093 l -S -q -0.000 0.000 1.000 rg -1 0 0 1 -25 4116 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm --24.012 -4.308 Td -([1-2]) Tj -ET -Q -q -0.176 0.176 0.176 rg -1 0 0 1 -25 4100 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm --199.452 -4.308 Td -(per_bank_dram_wb_queue_pop[7..0]) Tj -ET -Q -4784 4547 m -4791 4540 l -4784 4533 l -S -4770 4540 m -4791 4540 l -S -q -0.000 0.000 1.000 rg -1 0 0 1 4795 4556 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm -0 -4.308 Td -([1-2]) Tj -ET -Q -q -0.176 0.176 0.176 rg -1 0 0 1 4795 4540 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm -0 -4.308 Td -(dram_wb_req_data[0][127..0]) Tj -ET -Q -1 w -0 4600 m --14 4600 l --21 4607 l -S --14 4600 m --21 4593 l -S -q -0.000 0.000 1.000 rg -1 0 0 1 -25 4616 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm --23.352 -4.308 Td -([1,3]) Tj -ET -Q -q -0.176 0.176 0.176 rg -1 0 0 1 -25 4600 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm --212.064 -4.308 Td -([0].curr_bank_dram_fill_rsp_valid:OUT0) Tj -ET -Q -0 4680 m --14 4680 l --21 4687 l -S --14 4680 m --21 4673 l -S -q -0.000 0.000 1.000 rg -1 0 0 1 -25 4696 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm --23.352 -4.308 Td -([1,3]) Tj -ET -Q -q -0.176 0.176 0.176 rg -1 0 0 1 -25 4680 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm --155.4 -4.308 Td -([0].curr_bank_snp_req:OUT0) Tj -ET -Q -3 w -0.176 0.176 0.176 RG -1800 257 m -1800 3863 l -S -1800 3180 m -4090 3180 l -S -q -0.176 0.176 0.176 rg -4087 3177 7 7 re -f -Q -4090 4383 m -4090 2380 l -4470 2380 l -S -1 w -1250 260 m -1800 260 l -S -1250 840 m -1800 840 l -S -1250 1420 m -1800 1420 l -S -1250 2020 m -1800 2020 l -S -1250 2600 m -1800 2600 l -S -1250 3180 m -1800 3180 l -S -1250 3860 m -1800 3860 l -S -2880 4380 m -4090 4380 l -S -3 w -0.000 0.000 0.000 RG -q -0.000 0.000 0.000 rg -4091 4375 m -4091 4385 l -4080 4380 l -f -Q -q -0.000 0.000 0.000 rg -1801 255 m -1801 265 l -1790 260 l -f -Q -q -0.000 0.000 0.000 rg -1801 835 m -1801 845 l -1790 840 l -f -Q -q -0.000 0.000 0.000 rg -1801 1415 m -1801 1425 l -1790 1420 l -f -Q -q -0.000 0.000 0.000 rg -1801 2015 m -1801 2025 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-4.308 Td -([1-2]) Tj -ET -Q -q -0.176 0.176 0.176 rg -1 0 0 1 -25 500 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm --137.4 -4.308 Td -(dram_wb_req_addr[31..0]) Tj -ET -Q -0 460 m --14 460 l --21 467 l -S --14 460 m --21 453 l -S -q -0.000 0.000 1.000 rg -1 0 0 1 -25 476 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm --24.012 -4.308 Td -([1-2]) Tj -ET -Q -q -0.176 0.176 0.176 rg -1 0 0 1 -25 460 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm --137.4 -4.308 Td -(dram_wb_req_addr[31..0]) Tj -ET -Q -0 420 m --14 420 l --21 427 l -S --14 420 m --21 413 l -S -q -0.000 0.000 1.000 rg -1 0 0 1 -25 436 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm --24.012 -4.308 Td -([1-2]) Tj -ET -Q -q -0.176 0.176 0.176 rg -1 0 0 1 -25 420 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm --137.4 -4.308 Td -(dram_wb_req_addr[31..0]) Tj -ET -Q -1 w -744 27 m -751 20 l -744 13 l -S -730 20 m -751 20 l -S -q -0.000 0.000 1.000 rg -1 0 0 1 755 36 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm -0 -4.308 Td -([1-2]) Tj -ET -Q -q -0.176 0.176 0.176 rg -1 0 0 1 755 20 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm -0 -4.308 Td -(clk) Tj -ET -Q -3 w -0 3100 m --14 3100 l --21 3107 l -S --14 3100 m --21 3093 l -S -q -0.000 0.000 1.000 rg -1 0 0 1 -25 3116 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm --24.012 -4.308 Td -([1-2]) Tj -ET -Q -q -0.176 0.176 0.176 rg -1 0 0 1 -25 3100 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm --156.756 -4.308 Td -(dram_wb_req_data[0][127..0]) Tj -ET -Q -0 5660 m --14 5660 l --21 5667 l -S --14 5660 m --21 5653 l -S -q -0.000 0.000 1.000 rg -1 0 0 1 -25 5676 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm --24.012 -4.308 Td -([1-2]) Tj -ET -Q -q -0.176 0.176 0.176 rg -1 0 0 1 -25 5660 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm --156.756 -4.308 Td -(dram_wb_req_data[0][127..0]) Tj -ET -Q -1 w -744 10507 m -751 10500 l -744 10493 l -S -730 10500 m -751 10500 l -S -q -0.000 0.000 1.000 rg -1 0 0 1 755 10516 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm -0 -4.308 Td -([1-2]) Tj -ET -Q -q -0.176 0.176 0.176 rg -1 0 0 1 755 10500 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm -0 -4.308 Td -(dfqq_full) Tj -ET -Q -3 w -0 740 m --14 740 l --21 747 l -S --14 740 m --21 733 l -S -q -0.000 0.000 1.000 rg -1 0 0 1 -25 756 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm --24.012 -4.308 Td -([1-2]) Tj -ET -Q -q -0.176 0.176 0.176 rg -1 0 0 1 -25 740 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm --156.756 -4.308 Td -(dram_wb_req_data[0][127..0]) Tj -ET -Q -730 10540 m -730 10533 l -744 10533 l -751 10540 l -744 10547 l -730 10547 l -h S -q -0.000 0.000 0.000 rg -1 0 0 1 759 10540 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm -0 -4.308 Td -(dram_req_addr[31..0]) Tj -ET -Q -730 10560 m -730 10553 l -744 10553 l -751 10560 l -744 10567 l -730 10567 l -h S -q -0.000 0.000 0.000 rg -1 0 0 1 759 10560 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm -0 -4.308 Td -(dram_req_data[0][31..0]) Tj -ET -Q -0 8220 m --14 8220 l --21 8227 l -S --14 8220 m --21 8213 l -S -q -0.000 0.000 1.000 rg -1 0 0 1 -25 8236 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm --24.012 -4.308 Td -([1-2]) Tj -ET -Q -q -0.176 0.176 0.176 rg -1 0 0 1 -25 8220 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm --156.756 -4.308 Td -(dram_wb_req_data[0][127..0]) Tj -ET -Q -730 10580 m -730 10573 l -744 10573 l -751 10580 l -744 10587 l -730 10587 l -h S -q -0.000 0.000 0.000 rg -1 0 0 1 759 10580 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm -0 -4.308 Td -(dram_req_data[1][31..0]) Tj -ET -Q -q -0.000 0.000 0.000 rg -435 133 60 20922 re -f -Q -q -0.506 0.749 0.373 rg -430 128 60 20922 re -f -Q -1 w -0.176 0.176 0.176 RG -430 128 60 20922 re -S -3 w -441 133 m -441 145 l -S -435 139 m -447 139 l -S -1 w -433 131 16 16 re -S -q -0.000 0.000 0.000 rg -1 0 0 1 460 126 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm --57.024 2.484 Td -(cache_dram_req_arb) Tj -ET -Q -q -0.176 0.176 0.176 rg -1 0 0 1 460 21056 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm --72.36 -8.616 Td -(\(VX_cache_dram_req_arb\)) Tj -ET -Q -0.024 0.278 0.435 RG -420 160 m -430 160 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 159 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --12.22 2.07 Td -(clk) Tj -ET -Q -420 21040 m -430 21040 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 21039 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --22.23 2.07 Td -(reset) Tj -ET -Q -420 540 m -430 540 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 539 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --166.76 2.07 Td -(per_bank_dram_wb_req_data[0][0][0]) Tj -ET -Q -420 560 m -430 560 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 559 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --166.76 2.07 Td -(per_bank_dram_wb_req_data[0][0][1]) Tj -ET -Q -420 580 m -430 580 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 579 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --166.76 2.07 Td -(per_bank_dram_wb_req_data[0][0][2]) Tj -ET -Q -420 600 m -430 600 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 599 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --166.76 2.07 Td -(per_bank_dram_wb_req_data[0][0][3]) Tj -ET -Q -420 620 m -430 620 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 619 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --166.76 2.07 Td -(per_bank_dram_wb_req_data[0][0][4]) Tj -ET -Q -420 640 m -430 640 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 639 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --166.76 2.07 Td -(per_bank_dram_wb_req_data[0][0][5]) Tj -ET -Q -420 660 m -430 660 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 659 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --166.76 2.07 Td -(per_bank_dram_wb_req_data[0][0][6]) Tj -ET -Q -420 680 m -430 680 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 679 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --166.76 2.07 Td -(per_bank_dram_wb_req_data[0][0][7]) Tj -ET -Q -420 700 m -430 700 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 699 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --166.76 2.07 Td -(per_bank_dram_wb_req_data[0][0][8]) Tj -ET -Q -420 720 m -430 720 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 719 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --166.76 2.07 Td -(per_bank_dram_wb_req_data[0][0][9]) Tj -ET -Q -420 740 m -430 740 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 739 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[0][0][10]) Tj -ET -Q -420 760 m -430 760 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 759 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[0][0][11]) Tj -ET -Q -420 780 m -430 780 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 779 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[0][0][12]) Tj -ET -Q -420 800 m -430 800 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 799 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[0][0][13]) Tj -ET -Q -420 820 m -430 820 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 819 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[0][0][14]) Tj -ET -Q -420 840 m -430 840 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 839 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[0][0][15]) Tj -ET -Q -420 860 m -430 860 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 859 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[0][0][16]) Tj -ET -Q -420 880 m -430 880 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 879 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[0][0][17]) Tj -ET -Q -420 900 m -430 900 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 899 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[0][0][18]) Tj -ET -Q -420 920 m -430 920 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 919 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[0][0][19]) Tj -ET -Q -420 940 m -430 940 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 939 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[0][0][20]) Tj -ET -Q -420 960 m -430 960 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 959 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[0][0][21]) Tj -ET -Q -420 980 m -430 980 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 979 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[0][0][22]) Tj -ET -Q -420 1000 m -430 1000 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 999 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[0][0][23]) Tj -ET -Q -420 1020 m -430 1020 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 1019 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[0][0][24]) Tj -ET -Q -420 1040 m -430 1040 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 1039 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[0][0][25]) Tj -ET -Q -420 1060 m -430 1060 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 1059 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[0][0][26]) Tj -ET -Q -420 1080 m -430 1080 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 1079 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[0][0][27]) Tj -ET -Q -420 1100 m -430 1100 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 1099 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[0][0][28]) Tj -ET -Q -420 1120 m -430 1120 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 1119 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[0][0][29]) Tj -ET -Q -420 1140 m -430 1140 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 1139 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[0][0][30]) Tj -ET -Q -420 1160 m -430 1160 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 1159 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[0][0][31]) Tj -ET -Q -420 1180 m -430 1180 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 1179 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[0][0][32]) Tj -ET -Q -420 1200 m -430 1200 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 1199 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[0][0][33]) Tj -ET -Q -420 1220 m -430 1220 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 1219 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[0][0][34]) Tj -ET -Q -420 1240 m -430 1240 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 1239 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[0][0][35]) Tj -ET -Q -420 1260 m -430 1260 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 1259 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[0][0][36]) Tj -ET -Q -420 1280 m -430 1280 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 1279 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[0][0][37]) Tj -ET -Q -420 1300 m -430 1300 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 1299 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[0][0][38]) Tj -ET -Q -420 1320 m -430 1320 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 1319 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[0][0][39]) Tj -ET -Q -420 1340 m -430 1340 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 1339 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[0][0][40]) Tj -ET -Q -420 1360 m -430 1360 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 1359 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[0][0][41]) Tj -ET -Q -420 1380 m -430 1380 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 1379 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[0][0][42]) Tj -ET -Q -420 1400 m -430 1400 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 1399 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[0][0][43]) Tj -ET -Q -420 1420 m -430 1420 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 1419 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[0][0][44]) Tj -ET -Q -420 1440 m -430 1440 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 1439 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[0][0][45]) Tj -ET -Q -420 1460 m -430 1460 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 1459 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[0][0][46]) Tj -ET -Q -420 1480 m -430 1480 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 1479 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[0][0][47]) Tj -ET -Q -420 1500 m -430 1500 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 1499 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[0][0][48]) Tj -ET -Q -420 1520 m -430 1520 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 1519 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[0][0][49]) Tj -ET -Q -420 1540 m -430 1540 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 1539 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[0][0][50]) Tj -ET -Q -420 1560 m -430 1560 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 1559 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[0][0][51]) Tj -ET -Q -420 1580 m -430 1580 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 1579 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[0][0][52]) Tj -ET -Q -420 1600 m -430 1600 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 1599 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[0][0][53]) Tj -ET -Q -420 1620 m -430 1620 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 1619 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[0][0][54]) Tj -ET -Q -420 1640 m -430 1640 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 1639 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[0][0][55]) Tj -ET -Q -420 1660 m -430 1660 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 1659 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[0][0][56]) Tj -ET -Q -420 1680 m -430 1680 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 1679 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[0][0][57]) Tj -ET -Q -420 1700 m -430 1700 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 1699 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[0][0][58]) Tj -ET -Q -420 1720 m -430 1720 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 1719 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[0][0][59]) Tj -ET -Q -420 1740 m -430 1740 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 1739 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[0][0][60]) Tj -ET -Q -420 1760 m -430 1760 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 1759 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[0][0][61]) Tj -ET -Q -420 1780 m -430 1780 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 1779 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[0][0][62]) Tj -ET -Q -420 1800 m -430 1800 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 1799 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[0][0][63]) Tj -ET -Q -420 1820 m -430 1820 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 1819 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[0][0][64]) Tj -ET -Q -420 1840 m -430 1840 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 1839 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[0][0][65]) Tj -ET -Q -420 1860 m -430 1860 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 1859 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[0][0][66]) Tj -ET -Q -420 1880 m -430 1880 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 1879 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[0][0][67]) Tj -ET -Q -420 1900 m -430 1900 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 1899 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[0][0][68]) Tj -ET -Q -420 1920 m -430 1920 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 1919 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[0][0][69]) Tj -ET -Q -420 1940 m -430 1940 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 1939 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[0][0][70]) Tj -ET -Q -420 1960 m -430 1960 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 1959 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[0][0][71]) Tj -ET -Q -420 1980 m -430 1980 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 1979 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[0][0][72]) Tj -ET -Q -420 2000 m -430 2000 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 1999 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[0][0][73]) Tj -ET -Q -420 2020 m -430 2020 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 2019 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[0][0][74]) Tj -ET -Q -420 2040 m -430 2040 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 2039 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[0][0][75]) Tj -ET -Q -420 2060 m -430 2060 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 2059 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[0][0][76]) Tj -ET -Q -420 2080 m -430 2080 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 2079 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[0][0][77]) Tj -ET -Q -420 2100 m -430 2100 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 2099 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[0][0][78]) Tj -ET -Q -420 2120 m -430 2120 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 2119 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[0][0][79]) Tj -ET -Q -420 2140 m -430 2140 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 2139 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[0][0][80]) Tj -ET -Q -420 2160 m -430 2160 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 2159 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[0][0][81]) Tj -ET -Q -420 2180 m -430 2180 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 2179 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[0][0][82]) Tj -ET -Q -420 2200 m -430 2200 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 2199 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[0][0][83]) Tj -ET -Q -420 2220 m -430 2220 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 2219 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[0][0][84]) Tj -ET -Q -420 2240 m -430 2240 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 2239 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[0][0][85]) Tj -ET -Q -420 2260 m -430 2260 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 2259 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[0][0][86]) Tj -ET -Q -420 2280 m -430 2280 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 2279 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[0][0][87]) Tj -ET -Q -420 2300 m -430 2300 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 2299 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[0][0][88]) Tj -ET -Q -420 2320 m -430 2320 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 2319 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[0][0][89]) Tj -ET -Q -420 2340 m -430 2340 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 2339 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[0][0][90]) Tj -ET -Q -420 2360 m -430 2360 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 2359 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[0][0][91]) Tj -ET -Q -420 2380 m -430 2380 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 2379 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[0][0][92]) Tj -ET -Q -420 2400 m -430 2400 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 2399 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[0][0][93]) Tj -ET -Q -420 2420 m -430 2420 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 2419 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[0][0][94]) Tj -ET -Q -420 2440 m -430 2440 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 2439 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[0][0][95]) Tj -ET -Q -420 2460 m -430 2460 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 2459 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[0][0][96]) Tj -ET -Q -420 2480 m -430 2480 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 2479 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[0][0][97]) Tj -ET -Q -420 2500 m -430 2500 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 2499 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[0][0][98]) Tj -ET -Q -420 2520 m -430 2520 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 2519 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[0][0][99]) Tj -ET -Q -420 2540 m -430 2540 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 2539 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[0][0][100]) Tj -ET -Q -420 2560 m -430 2560 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 2559 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[0][0][101]) Tj -ET -Q -420 2580 m -430 2580 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 2579 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[0][0][102]) Tj -ET -Q -420 2600 m -430 2600 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 2599 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[0][0][103]) Tj -ET -Q -420 2620 m -430 2620 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 2619 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[0][0][104]) Tj -ET -Q -420 2640 m -430 2640 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 2639 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[0][0][105]) Tj -ET -Q -420 2660 m -430 2660 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 2659 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[0][0][106]) Tj -ET -Q -420 2680 m -430 2680 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 2679 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[0][0][107]) Tj -ET -Q -420 2700 m -430 2700 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 2699 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[0][0][108]) Tj -ET -Q -420 2720 m -430 2720 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 2719 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[0][0][109]) Tj -ET -Q -420 2740 m -430 2740 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 2739 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[0][0][110]) Tj -ET -Q -420 2760 m -430 2760 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 2759 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[0][0][111]) Tj -ET -Q -420 2780 m -430 2780 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 2779 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[0][0][112]) Tj -ET -Q -420 2800 m -430 2800 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 2799 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[0][0][113]) Tj -ET -Q -420 2820 m -430 2820 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 2819 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[0][0][114]) Tj -ET -Q -420 2840 m -430 2840 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 2839 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[0][0][115]) Tj -ET -Q -420 2860 m -430 2860 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 2859 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[0][0][116]) Tj -ET -Q -420 2880 m -430 2880 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 2879 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[0][0][117]) Tj -ET -Q -420 2900 m -430 2900 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 2899 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[0][0][118]) Tj -ET -Q -420 2920 m -430 2920 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 2919 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[0][0][119]) Tj -ET -Q -420 2940 m -430 2940 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 2939 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[0][0][120]) Tj -ET -Q -420 2960 m -430 2960 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 2959 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[0][0][121]) Tj -ET -Q -420 2980 m -430 2980 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 2979 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[0][0][122]) Tj -ET -Q -420 3000 m -430 3000 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 2999 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[0][0][123]) Tj -ET -Q -420 3020 m -430 3020 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 3019 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[0][0][124]) Tj -ET -Q -420 3040 m -430 3040 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 3039 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[0][0][125]) Tj -ET -Q -420 3060 m -430 3060 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 3059 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[0][0][126]) Tj -ET -Q -420 3080 m -430 3080 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 3079 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[0][0][127]) Tj -ET -Q -420 3100 m -430 3100 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 3099 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --166.76 2.07 Td -(per_bank_dram_wb_req_data[1][0][0]) Tj -ET -Q -420 3120 m -430 3120 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 3119 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --166.76 2.07 Td -(per_bank_dram_wb_req_data[1][0][1]) Tj -ET -Q -420 3140 m -430 3140 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 3139 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --166.76 2.07 Td -(per_bank_dram_wb_req_data[1][0][2]) Tj -ET -Q -420 3160 m -430 3160 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 3159 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --166.76 2.07 Td -(per_bank_dram_wb_req_data[1][0][3]) Tj -ET -Q -420 3180 m -430 3180 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 3179 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --166.76 2.07 Td -(per_bank_dram_wb_req_data[1][0][4]) Tj -ET -Q -420 3200 m -430 3200 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 3199 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --166.76 2.07 Td -(per_bank_dram_wb_req_data[1][0][5]) Tj -ET -Q -420 3220 m -430 3220 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 3219 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --166.76 2.07 Td -(per_bank_dram_wb_req_data[1][0][6]) Tj -ET -Q -420 3240 m -430 3240 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 3239 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --166.76 2.07 Td -(per_bank_dram_wb_req_data[1][0][7]) Tj -ET -Q -420 3260 m -430 3260 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 3259 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --166.76 2.07 Td -(per_bank_dram_wb_req_data[1][0][8]) Tj -ET -Q -420 3280 m -430 3280 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 3279 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --166.76 2.07 Td -(per_bank_dram_wb_req_data[1][0][9]) Tj -ET -Q -420 3300 m -430 3300 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 3299 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[1][0][10]) Tj -ET -Q -420 3320 m -430 3320 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 3319 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[1][0][11]) Tj -ET -Q -420 3340 m -430 3340 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 3339 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[1][0][12]) Tj -ET -Q -420 3360 m -430 3360 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 3359 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[1][0][13]) Tj -ET -Q -420 3380 m -430 3380 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 3379 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[1][0][14]) Tj -ET -Q -420 3400 m -430 3400 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 3399 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[1][0][15]) Tj -ET -Q -420 3420 m -430 3420 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 3419 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[1][0][16]) Tj -ET -Q -420 3440 m -430 3440 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 3439 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[1][0][17]) Tj -ET -Q -420 3460 m -430 3460 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 3459 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[1][0][18]) Tj -ET -Q -420 3480 m -430 3480 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 3479 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[1][0][19]) Tj -ET -Q -420 3500 m -430 3500 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 3499 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[1][0][20]) Tj -ET -Q -420 3520 m -430 3520 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 3519 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[1][0][21]) Tj -ET -Q -420 3540 m -430 3540 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 3539 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[1][0][22]) Tj -ET -Q -420 3560 m -430 3560 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 3559 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[1][0][23]) Tj -ET -Q -420 3580 m -430 3580 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 3579 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[1][0][24]) Tj -ET -Q -420 3600 m -430 3600 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 3599 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[1][0][25]) Tj -ET -Q -420 3620 m -430 3620 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 3619 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[1][0][26]) Tj -ET -Q -420 3640 m -430 3640 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 3639 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[1][0][27]) Tj -ET -Q -420 3660 m -430 3660 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 3659 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[1][0][28]) Tj -ET -Q -420 3680 m -430 3680 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 3679 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[1][0][29]) Tj -ET -Q -420 3700 m -430 3700 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 3699 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[1][0][30]) Tj -ET -Q -420 3720 m -430 3720 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 3719 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[1][0][31]) Tj -ET -Q -420 3740 m -430 3740 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 3739 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[1][0][32]) Tj -ET -Q -420 3760 m -430 3760 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 3759 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[1][0][33]) Tj -ET -Q -420 3780 m -430 3780 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 3779 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[1][0][34]) Tj -ET -Q -420 3800 m -430 3800 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 3799 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[1][0][35]) Tj -ET -Q -420 3820 m -430 3820 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 3819 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[1][0][36]) Tj -ET -Q -420 3840 m -430 3840 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 3839 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[1][0][37]) Tj -ET -Q -420 3860 m -430 3860 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 3859 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[1][0][38]) Tj -ET -Q -420 3880 m -430 3880 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 3879 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[1][0][39]) Tj -ET -Q -420 3900 m -430 3900 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 3899 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[1][0][40]) Tj -ET -Q -420 3920 m -430 3920 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 3919 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[1][0][41]) Tj -ET -Q -420 3940 m -430 3940 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 3939 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[1][0][42]) Tj -ET -Q -420 3960 m -430 3960 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 3959 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[1][0][43]) Tj -ET -Q -420 3980 m -430 3980 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 3979 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[1][0][44]) Tj -ET -Q -420 4000 m -430 4000 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 3999 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[1][0][45]) Tj -ET -Q -420 4020 m -430 4020 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 4019 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[1][0][46]) Tj -ET -Q -420 4040 m -430 4040 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 4039 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[1][0][47]) Tj -ET -Q -420 4060 m -430 4060 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 4059 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[1][0][48]) Tj -ET -Q -420 4080 m -430 4080 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 4079 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[1][0][49]) Tj -ET -Q -420 4100 m -430 4100 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 4099 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[1][0][50]) Tj -ET -Q -420 4120 m -430 4120 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 4119 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[1][0][51]) Tj -ET -Q -420 4140 m -430 4140 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 4139 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[1][0][52]) Tj -ET -Q -420 4160 m -430 4160 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 4159 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[1][0][53]) Tj -ET -Q -420 4180 m -430 4180 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 4179 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[1][0][54]) Tj -ET -Q -420 4200 m -430 4200 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 4199 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[1][0][55]) Tj -ET -Q -420 4220 m -430 4220 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 4219 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[1][0][56]) Tj -ET -Q -420 4240 m -430 4240 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 4239 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[1][0][57]) Tj -ET -Q -420 4260 m -430 4260 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 4259 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[1][0][58]) Tj -ET -Q -420 4280 m -430 4280 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 4279 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[1][0][59]) Tj -ET -Q -420 4300 m -430 4300 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 4299 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[1][0][60]) Tj -ET -Q -420 4320 m -430 4320 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 4319 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[1][0][61]) Tj -ET -Q -420 4340 m -430 4340 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 4339 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[1][0][62]) Tj -ET -Q -420 4360 m -430 4360 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 4359 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[1][0][63]) Tj -ET -Q -420 4380 m -430 4380 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 4379 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[1][0][64]) Tj -ET -Q -420 4400 m -430 4400 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 4399 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[1][0][65]) Tj -ET -Q -420 4420 m -430 4420 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 4419 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[1][0][66]) Tj -ET -Q -420 4440 m -430 4440 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 4439 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[1][0][67]) Tj -ET -Q -420 4460 m -430 4460 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 4459 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[1][0][68]) Tj -ET -Q -420 4480 m -430 4480 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 4479 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[1][0][69]) Tj -ET -Q -420 4500 m -430 4500 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 4499 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[1][0][70]) Tj -ET -Q -420 4520 m -430 4520 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 4519 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[1][0][71]) Tj -ET -Q -420 4540 m -430 4540 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 4539 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[1][0][72]) Tj -ET -Q -420 4560 m -430 4560 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 4559 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[1][0][73]) Tj -ET -Q -420 4580 m -430 4580 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 4579 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[1][0][74]) Tj -ET -Q -420 4600 m -430 4600 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 4599 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[1][0][75]) Tj -ET -Q -420 4620 m -430 4620 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 4619 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[1][0][76]) Tj -ET -Q -420 4640 m -430 4640 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 4639 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[1][0][77]) Tj -ET -Q -420 4660 m -430 4660 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 4659 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[1][0][78]) Tj -ET -Q -420 4680 m -430 4680 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 4679 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[1][0][79]) Tj -ET -Q -420 4700 m -430 4700 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 4699 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[1][0][80]) Tj -ET -Q -420 4720 m -430 4720 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 4719 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[1][0][81]) Tj -ET -Q -420 4740 m -430 4740 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 4739 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[1][0][82]) Tj -ET -Q -420 4760 m -430 4760 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 4759 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[1][0][83]) Tj -ET -Q -420 4780 m -430 4780 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 4779 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[1][0][84]) Tj -ET -Q -420 4800 m -430 4800 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 4799 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[1][0][85]) Tj -ET -Q -420 4820 m -430 4820 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 4819 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[1][0][86]) Tj -ET -Q -420 4840 m -430 4840 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 4839 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[1][0][87]) Tj -ET -Q -420 4860 m -430 4860 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 4859 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[1][0][88]) Tj -ET -Q -420 4880 m -430 4880 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 4879 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[1][0][89]) Tj -ET -Q -420 4900 m -430 4900 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 4899 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[1][0][90]) Tj -ET -Q -420 4920 m -430 4920 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 4919 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[1][0][91]) Tj -ET -Q -420 4940 m -430 4940 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 4939 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[1][0][92]) Tj -ET -Q -420 4960 m -430 4960 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 4959 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[1][0][93]) Tj -ET -Q -420 4980 m -430 4980 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 4979 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[1][0][94]) Tj -ET -Q -420 5000 m -430 5000 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 4999 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[1][0][95]) Tj -ET -Q -420 5020 m -430 5020 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 5019 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[1][0][96]) Tj -ET -Q -420 5040 m -430 5040 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 5039 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[1][0][97]) Tj -ET -Q -420 5060 m -430 5060 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 5059 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[1][0][98]) Tj -ET -Q -420 5080 m -430 5080 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 5079 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[1][0][99]) Tj -ET -Q -420 5100 m -430 5100 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 5099 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[1][0][100]) Tj -ET -Q -420 5120 m -430 5120 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 5119 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[1][0][101]) Tj -ET -Q -420 5140 m -430 5140 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 5139 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[1][0][102]) Tj -ET -Q -420 5160 m -430 5160 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 5159 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[1][0][103]) Tj -ET -Q -420 5180 m -430 5180 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 5179 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[1][0][104]) Tj -ET -Q -420 5200 m -430 5200 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 5199 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[1][0][105]) Tj -ET -Q -420 5220 m -430 5220 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 5219 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[1][0][106]) Tj -ET -Q -420 5240 m -430 5240 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 5239 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[1][0][107]) Tj -ET -Q -420 5260 m -430 5260 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 5259 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[1][0][108]) Tj -ET -Q -420 5280 m -430 5280 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 5279 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[1][0][109]) Tj -ET -Q -420 5300 m -430 5300 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 5299 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[1][0][110]) Tj -ET -Q -420 5320 m -430 5320 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 5319 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[1][0][111]) Tj -ET -Q -420 5340 m -430 5340 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 5339 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[1][0][112]) Tj -ET -Q -420 5360 m -430 5360 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 5359 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[1][0][113]) Tj -ET -Q -420 5380 m -430 5380 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 5379 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[1][0][114]) Tj -ET -Q -420 5400 m -430 5400 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 5399 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[1][0][115]) Tj -ET -Q -420 5420 m -430 5420 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 5419 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[1][0][116]) Tj -ET -Q -420 5440 m -430 5440 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 5439 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[1][0][117]) Tj -ET -Q -420 5460 m -430 5460 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 5459 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[1][0][118]) Tj -ET -Q -420 5480 m -430 5480 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 5479 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[1][0][119]) Tj -ET -Q -420 5500 m -430 5500 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 5499 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[1][0][120]) Tj -ET -Q -420 5520 m -430 5520 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 5519 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[1][0][121]) Tj -ET -Q -420 5540 m -430 5540 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 5539 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[1][0][122]) Tj -ET -Q -420 5560 m -430 5560 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 5559 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[1][0][123]) Tj -ET -Q -420 5580 m -430 5580 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 5579 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[1][0][124]) Tj -ET -Q -420 5600 m -430 5600 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 5599 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[1][0][125]) Tj -ET -Q -420 5620 m -430 5620 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 5619 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[1][0][126]) Tj -ET -Q -420 5640 m -430 5640 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 5639 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[1][0][127]) Tj -ET -Q -420 5660 m -430 5660 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 5659 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --166.76 2.07 Td -(per_bank_dram_wb_req_data[2][0][0]) Tj -ET -Q -420 5680 m -430 5680 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 5679 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --166.76 2.07 Td -(per_bank_dram_wb_req_data[2][0][1]) Tj -ET -Q -420 5700 m -430 5700 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 5699 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --166.76 2.07 Td -(per_bank_dram_wb_req_data[2][0][2]) Tj -ET -Q -420 5720 m -430 5720 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 5719 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --166.76 2.07 Td -(per_bank_dram_wb_req_data[2][0][3]) Tj -ET -Q -420 5740 m -430 5740 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 5739 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --166.76 2.07 Td -(per_bank_dram_wb_req_data[2][0][4]) Tj -ET -Q -420 5760 m -430 5760 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 5759 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --166.76 2.07 Td -(per_bank_dram_wb_req_data[2][0][5]) Tj -ET -Q -420 5780 m -430 5780 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 5779 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --166.76 2.07 Td -(per_bank_dram_wb_req_data[2][0][6]) Tj -ET -Q -420 5800 m -430 5800 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 5799 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --166.76 2.07 Td -(per_bank_dram_wb_req_data[2][0][7]) Tj -ET -Q -420 5820 m -430 5820 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 5819 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --166.76 2.07 Td -(per_bank_dram_wb_req_data[2][0][8]) Tj -ET -Q -420 5840 m -430 5840 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 5839 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --166.76 2.07 Td -(per_bank_dram_wb_req_data[2][0][9]) Tj -ET -Q -420 5860 m -430 5860 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 5859 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[2][0][10]) Tj -ET -Q -420 5880 m -430 5880 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 5879 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[2][0][11]) Tj -ET -Q -420 5900 m -430 5900 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 5899 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[2][0][12]) Tj -ET -Q -420 5920 m -430 5920 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 5919 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[2][0][13]) Tj -ET -Q -420 5940 m -430 5940 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 5939 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[2][0][14]) Tj -ET -Q -420 5960 m -430 5960 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 5959 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[2][0][15]) Tj -ET -Q -420 5980 m -430 5980 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 5979 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[2][0][16]) Tj -ET -Q -420 6000 m -430 6000 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 5999 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[2][0][17]) Tj -ET -Q -420 6020 m -430 6020 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 6019 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[2][0][18]) Tj -ET -Q -420 6040 m -430 6040 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 6039 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[2][0][19]) Tj -ET -Q -420 6060 m -430 6060 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 6059 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[2][0][20]) Tj -ET -Q -420 6080 m -430 6080 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 6079 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[2][0][21]) Tj -ET -Q -420 6100 m -430 6100 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 6099 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[2][0][22]) Tj -ET -Q -420 6120 m -430 6120 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 6119 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[2][0][23]) Tj -ET -Q -420 6140 m -430 6140 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 6139 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[2][0][24]) Tj -ET -Q -420 6160 m -430 6160 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 6159 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[2][0][25]) Tj -ET -Q -420 6180 m -430 6180 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 6179 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[2][0][26]) Tj -ET -Q -420 6200 m -430 6200 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 6199 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[2][0][27]) Tj -ET -Q -420 6220 m -430 6220 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 6219 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[2][0][28]) Tj -ET -Q -420 6240 m -430 6240 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 6239 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[2][0][29]) Tj -ET -Q -420 6260 m -430 6260 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 6259 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[2][0][30]) Tj -ET -Q -420 6280 m -430 6280 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 6279 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[2][0][31]) Tj -ET -Q -420 6300 m -430 6300 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 6299 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[2][0][32]) Tj -ET -Q -420 6320 m -430 6320 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 6319 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[2][0][33]) Tj -ET -Q -420 6340 m -430 6340 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 6339 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[2][0][34]) Tj -ET -Q -420 6360 m -430 6360 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 6359 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[2][0][35]) Tj -ET -Q -420 6380 m -430 6380 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 6379 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[2][0][36]) Tj -ET -Q -420 6400 m -430 6400 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 6399 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[2][0][37]) Tj -ET -Q -420 6420 m -430 6420 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 6419 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[2][0][38]) Tj -ET -Q -420 6440 m -430 6440 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 6439 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[2][0][39]) Tj -ET -Q -420 6460 m -430 6460 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 6459 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[2][0][40]) Tj -ET -Q -420 6480 m -430 6480 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 6479 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[2][0][41]) Tj -ET -Q -420 6500 m -430 6500 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 6499 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[2][0][42]) Tj -ET -Q -420 6520 m -430 6520 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 6519 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[2][0][43]) Tj -ET -Q -420 6540 m -430 6540 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 6539 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[2][0][44]) Tj -ET -Q -420 6560 m -430 6560 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 6559 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[2][0][45]) Tj -ET -Q -420 6580 m -430 6580 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 6579 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[2][0][46]) Tj -ET -Q -420 6600 m -430 6600 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 6599 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[2][0][47]) Tj -ET -Q -420 6620 m -430 6620 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 6619 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[2][0][48]) Tj -ET -Q -420 6640 m -430 6640 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 6639 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[2][0][49]) Tj -ET -Q -420 6660 m -430 6660 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 6659 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[2][0][50]) Tj -ET -Q -420 6680 m -430 6680 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 6679 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[2][0][51]) Tj -ET -Q -420 6700 m -430 6700 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 6699 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[2][0][52]) Tj -ET -Q -420 6720 m -430 6720 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 6719 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[2][0][53]) Tj -ET -Q -420 6740 m -430 6740 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 6739 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[2][0][54]) Tj -ET -Q -420 6760 m -430 6760 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 6759 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[2][0][55]) Tj -ET -Q -420 6780 m -430 6780 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 6779 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[2][0][56]) Tj -ET -Q -420 6800 m -430 6800 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 6799 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[2][0][57]) Tj -ET -Q -420 6820 m -430 6820 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 6819 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[2][0][58]) Tj -ET -Q -420 6840 m -430 6840 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 6839 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[2][0][59]) Tj -ET -Q -420 6860 m -430 6860 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 6859 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[2][0][60]) Tj -ET -Q -420 6880 m -430 6880 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 6879 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[2][0][61]) Tj -ET -Q -420 6900 m -430 6900 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 6899 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[2][0][62]) Tj -ET -Q -420 6920 m -430 6920 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 6919 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[2][0][63]) Tj -ET -Q -420 6940 m -430 6940 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 6939 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[2][0][64]) Tj -ET -Q -420 6960 m -430 6960 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 6959 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[2][0][65]) Tj -ET -Q -420 6980 m -430 6980 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 6979 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[2][0][66]) Tj -ET -Q -420 7000 m -430 7000 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 6999 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[2][0][67]) Tj -ET -Q -420 7020 m -430 7020 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 7019 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[2][0][68]) Tj -ET -Q -420 7040 m -430 7040 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 7039 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[2][0][69]) Tj -ET -Q -420 7060 m -430 7060 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 7059 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[2][0][70]) Tj -ET -Q -420 7080 m -430 7080 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 7079 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[2][0][71]) Tj -ET -Q -420 7100 m -430 7100 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 7099 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[2][0][72]) Tj -ET -Q -420 7120 m -430 7120 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 7119 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[2][0][73]) Tj -ET -Q -420 7140 m -430 7140 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 7139 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[2][0][74]) Tj -ET -Q -420 7160 m -430 7160 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 7159 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[2][0][75]) Tj -ET -Q -420 7180 m -430 7180 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 7179 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[2][0][76]) Tj -ET -Q -420 7200 m -430 7200 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 7199 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[2][0][77]) Tj -ET -Q -420 7220 m -430 7220 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 7219 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[2][0][78]) Tj -ET -Q -420 7240 m -430 7240 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 7239 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[2][0][79]) Tj -ET -Q -420 7260 m -430 7260 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 7259 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[2][0][80]) Tj -ET -Q -420 7280 m -430 7280 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 7279 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[2][0][81]) Tj -ET -Q -420 7300 m -430 7300 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 7299 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[2][0][82]) Tj -ET -Q -420 7320 m -430 7320 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 7319 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[2][0][83]) Tj -ET -Q -420 7340 m -430 7340 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 7339 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[2][0][84]) Tj -ET -Q -420 7360 m -430 7360 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 7359 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[2][0][85]) Tj -ET -Q -420 7380 m -430 7380 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 7379 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[2][0][86]) Tj -ET -Q -420 7400 m -430 7400 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 7399 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[2][0][87]) Tj -ET -Q -420 7420 m -430 7420 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 7419 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[2][0][88]) Tj -ET -Q -420 7440 m -430 7440 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 7439 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[2][0][89]) Tj -ET -Q -420 7460 m -430 7460 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 7459 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[2][0][90]) Tj -ET -Q -420 7480 m -430 7480 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 7479 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[2][0][91]) Tj -ET -Q -420 7500 m -430 7500 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 7499 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[2][0][92]) Tj -ET -Q -420 7520 m -430 7520 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 7519 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[2][0][93]) Tj -ET -Q -420 7540 m -430 7540 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 7539 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[2][0][94]) Tj -ET -Q -420 7560 m -430 7560 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 7559 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[2][0][95]) Tj -ET -Q -420 7580 m -430 7580 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 7579 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[2][0][96]) Tj -ET -Q -420 7600 m -430 7600 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 7599 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[2][0][97]) Tj -ET -Q -420 7620 m -430 7620 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 7619 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[2][0][98]) Tj -ET -Q -420 7640 m -430 7640 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 7639 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[2][0][99]) Tj -ET -Q -420 7660 m -430 7660 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 7659 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[2][0][100]) Tj -ET -Q -420 7680 m -430 7680 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 7679 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[2][0][101]) Tj -ET -Q -420 7700 m -430 7700 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 7699 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[2][0][102]) Tj -ET -Q -420 7720 m -430 7720 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 7719 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[2][0][103]) Tj -ET -Q -420 7740 m -430 7740 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 7739 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[2][0][104]) Tj -ET -Q -420 7760 m -430 7760 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 7759 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[2][0][105]) Tj -ET -Q -420 7780 m -430 7780 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 7779 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[2][0][106]) Tj -ET -Q -420 7800 m -430 7800 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 7799 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[2][0][107]) Tj -ET -Q -420 7820 m -430 7820 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 7819 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[2][0][108]) Tj -ET -Q -420 7840 m -430 7840 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 7839 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[2][0][109]) Tj -ET -Q -420 7860 m -430 7860 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 7859 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[2][0][110]) Tj -ET -Q -420 7880 m -430 7880 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 7879 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[2][0][111]) Tj -ET -Q -420 7900 m -430 7900 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 7899 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[2][0][112]) Tj -ET -Q -420 7920 m -430 7920 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 7919 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[2][0][113]) Tj -ET -Q -420 7940 m -430 7940 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 7939 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[2][0][114]) Tj -ET -Q -420 7960 m -430 7960 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 7959 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[2][0][115]) Tj -ET -Q -420 7980 m -430 7980 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 7979 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[2][0][116]) Tj -ET -Q -420 8000 m -430 8000 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 7999 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[2][0][117]) Tj -ET -Q -420 8020 m -430 8020 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 8019 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[2][0][118]) Tj -ET -Q -420 8040 m -430 8040 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 8039 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[2][0][119]) Tj -ET -Q -420 8060 m -430 8060 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 8059 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[2][0][120]) Tj -ET -Q -420 8080 m -430 8080 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 8079 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[2][0][121]) Tj -ET -Q -420 8100 m -430 8100 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 8099 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[2][0][122]) Tj -ET -Q -420 8120 m -430 8120 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 8119 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[2][0][123]) Tj -ET -Q -420 8140 m -430 8140 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 8139 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[2][0][124]) Tj -ET -Q -420 8160 m -430 8160 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 8159 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[2][0][125]) Tj -ET -Q -420 8180 m -430 8180 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 8179 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[2][0][126]) Tj -ET -Q -420 8200 m -430 8200 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 8199 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[2][0][127]) Tj -ET -Q -420 8220 m -430 8220 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 8219 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --166.76 2.07 Td -(per_bank_dram_wb_req_data[3][0][0]) Tj -ET -Q -420 8240 m -430 8240 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 8239 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --166.76 2.07 Td -(per_bank_dram_wb_req_data[3][0][1]) Tj -ET -Q -420 8260 m -430 8260 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 8259 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --166.76 2.07 Td -(per_bank_dram_wb_req_data[3][0][2]) Tj -ET -Q -420 8280 m -430 8280 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 8279 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --166.76 2.07 Td -(per_bank_dram_wb_req_data[3][0][3]) Tj -ET -Q -420 8300 m -430 8300 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 8299 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --166.76 2.07 Td -(per_bank_dram_wb_req_data[3][0][4]) Tj -ET -Q -420 8320 m -430 8320 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 8319 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --166.76 2.07 Td -(per_bank_dram_wb_req_data[3][0][5]) Tj -ET -Q -420 8340 m -430 8340 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 8339 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --166.76 2.07 Td -(per_bank_dram_wb_req_data[3][0][6]) Tj -ET -Q -420 8360 m -430 8360 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 8359 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --166.76 2.07 Td -(per_bank_dram_wb_req_data[3][0][7]) Tj -ET -Q -420 8380 m -430 8380 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 8379 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --166.76 2.07 Td -(per_bank_dram_wb_req_data[3][0][8]) Tj -ET -Q -420 8400 m -430 8400 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 8399 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --166.76 2.07 Td -(per_bank_dram_wb_req_data[3][0][9]) Tj -ET -Q -420 8420 m -430 8420 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 8419 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[3][0][10]) Tj -ET -Q -420 8440 m -430 8440 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 8439 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[3][0][11]) Tj -ET -Q -420 8460 m -430 8460 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 8459 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[3][0][12]) Tj -ET -Q -420 8480 m -430 8480 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 8479 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[3][0][13]) Tj -ET -Q -420 8500 m -430 8500 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 8499 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[3][0][14]) Tj -ET -Q -420 8520 m -430 8520 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 8519 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[3][0][15]) Tj -ET -Q -420 8540 m -430 8540 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 8539 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[3][0][16]) Tj -ET -Q -420 8560 m -430 8560 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 8559 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[3][0][17]) Tj -ET -Q -420 8580 m -430 8580 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 8579 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[3][0][18]) Tj -ET -Q -420 8600 m -430 8600 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 8599 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[3][0][19]) Tj -ET -Q -420 8620 m -430 8620 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 8619 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[3][0][20]) Tj -ET -Q -420 8640 m -430 8640 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 8639 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[3][0][21]) Tj -ET -Q -420 8660 m -430 8660 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 8659 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[3][0][22]) Tj -ET -Q -420 8680 m -430 8680 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 8679 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[3][0][23]) Tj -ET -Q -420 8700 m -430 8700 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 8699 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[3][0][24]) Tj -ET -Q -420 8720 m -430 8720 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 8719 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[3][0][25]) Tj -ET -Q -420 8740 m -430 8740 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 8739 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[3][0][26]) Tj -ET -Q -420 8760 m -430 8760 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 8759 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[3][0][27]) Tj -ET -Q -420 8780 m -430 8780 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 8779 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[3][0][28]) Tj -ET -Q -420 8800 m -430 8800 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 8799 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[3][0][29]) Tj -ET -Q -420 8820 m -430 8820 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 8819 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[3][0][30]) Tj -ET -Q -420 8840 m -430 8840 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 8839 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[3][0][31]) Tj -ET -Q -420 8860 m -430 8860 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 8859 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[3][0][32]) Tj -ET -Q -420 8880 m -430 8880 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 8879 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[3][0][33]) Tj -ET -Q -420 8900 m -430 8900 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 8899 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[3][0][34]) Tj -ET -Q -420 8920 m -430 8920 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 8919 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[3][0][35]) Tj -ET -Q -420 8940 m -430 8940 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 8939 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[3][0][36]) Tj -ET -Q -420 8960 m -430 8960 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 8959 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[3][0][37]) Tj -ET -Q -420 8980 m -430 8980 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 8979 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[3][0][38]) Tj -ET -Q -420 9000 m -430 9000 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 8999 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[3][0][39]) Tj -ET -Q -420 9020 m -430 9020 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 9019 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[3][0][40]) Tj -ET -Q -420 9040 m -430 9040 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 9039 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[3][0][41]) Tj -ET -Q -420 9060 m -430 9060 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 9059 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[3][0][42]) Tj -ET -Q -420 9080 m -430 9080 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 9079 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[3][0][43]) Tj -ET -Q -420 9100 m -430 9100 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 9099 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[3][0][44]) Tj -ET -Q -420 9120 m -430 9120 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 9119 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[3][0][45]) Tj -ET -Q -420 9140 m -430 9140 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 9139 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[3][0][46]) Tj -ET -Q -420 9160 m -430 9160 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 9159 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[3][0][47]) Tj -ET -Q -420 9180 m -430 9180 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 9179 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[3][0][48]) Tj -ET -Q -420 9200 m -430 9200 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 9199 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[3][0][49]) Tj -ET -Q -420 9220 m -430 9220 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 9219 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[3][0][50]) Tj -ET -Q -420 9240 m -430 9240 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 9239 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[3][0][51]) Tj -ET -Q -420 9260 m -430 9260 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 9259 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[3][0][52]) Tj -ET -Q -420 9280 m -430 9280 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 9279 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[3][0][53]) Tj -ET -Q -420 9300 m -430 9300 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 9299 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[3][0][54]) Tj -ET -Q -420 9320 m -430 9320 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 9319 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[3][0][55]) Tj -ET -Q -420 9340 m -430 9340 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 9339 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[3][0][56]) Tj -ET -Q -420 9360 m -430 9360 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 9359 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[3][0][57]) Tj -ET -Q -420 9380 m -430 9380 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 9379 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[3][0][58]) Tj -ET -Q -420 9400 m -430 9400 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 9399 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[3][0][59]) Tj -ET -Q -420 9420 m -430 9420 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 9419 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[3][0][60]) Tj -ET -Q -420 9440 m -430 9440 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 9439 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[3][0][61]) Tj -ET -Q -420 9460 m -430 9460 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 9459 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[3][0][62]) Tj -ET -Q -420 9480 m -430 9480 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 9479 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[3][0][63]) Tj -ET -Q -420 9500 m -430 9500 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 9499 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[3][0][64]) Tj -ET -Q -420 9520 m -430 9520 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 9519 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[3][0][65]) Tj -ET -Q -420 9540 m -430 9540 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 9539 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[3][0][66]) Tj -ET -Q -420 9560 m -430 9560 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 9559 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[3][0][67]) Tj -ET -Q -420 9580 m -430 9580 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 9579 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[3][0][68]) Tj -ET -Q -420 9600 m -430 9600 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 9599 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[3][0][69]) Tj -ET -Q -420 9620 m -430 9620 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 9619 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[3][0][70]) Tj -ET -Q -420 9640 m -430 9640 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 9639 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[3][0][71]) Tj -ET -Q -420 9660 m -430 9660 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 9659 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[3][0][72]) Tj -ET -Q -420 9680 m -430 9680 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 9679 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[3][0][73]) Tj -ET -Q -420 9700 m -430 9700 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 9699 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[3][0][74]) Tj -ET -Q -420 9720 m -430 9720 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 9719 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[3][0][75]) Tj -ET -Q -420 9740 m -430 9740 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 9739 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[3][0][76]) Tj -ET -Q -420 9760 m -430 9760 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 9759 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[3][0][77]) Tj -ET -Q -420 9780 m -430 9780 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 9779 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[3][0][78]) Tj -ET -Q -420 9800 m -430 9800 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 9799 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[3][0][79]) Tj -ET -Q -420 9820 m -430 9820 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 9819 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[3][0][80]) Tj -ET -Q -420 9840 m -430 9840 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 9839 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[3][0][81]) Tj -ET -Q -420 9860 m -430 9860 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 9859 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[3][0][82]) Tj -ET -Q -420 9880 m -430 9880 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 9879 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[3][0][83]) Tj -ET -Q -420 9900 m -430 9900 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 9899 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[3][0][84]) Tj -ET -Q -420 9920 m -430 9920 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 9919 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[3][0][85]) Tj -ET -Q -420 9940 m -430 9940 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 9939 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[3][0][86]) Tj -ET -Q -420 9960 m -430 9960 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 9959 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[3][0][87]) Tj -ET -Q -420 9980 m -430 9980 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 9979 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[3][0][88]) Tj -ET -Q -420 10000 m -430 10000 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 9999 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[3][0][89]) Tj -ET -Q -420 10020 m -430 10020 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 10019 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[3][0][90]) Tj -ET -Q -420 10040 m -430 10040 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 10039 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[3][0][91]) Tj -ET -Q -420 10060 m -430 10060 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 10059 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[3][0][92]) Tj -ET -Q -420 10080 m -430 10080 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 10079 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[3][0][93]) Tj -ET -Q -420 10100 m -430 10100 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 10099 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[3][0][94]) Tj -ET -Q -420 10120 m -430 10120 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 10119 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[3][0][95]) Tj -ET -Q -420 10140 m -430 10140 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 10139 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[3][0][96]) Tj -ET -Q -420 10160 m -430 10160 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 10159 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[3][0][97]) Tj -ET -Q -420 10180 m -430 10180 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 10179 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[3][0][98]) Tj -ET -Q -420 10200 m -430 10200 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 10199 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[3][0][99]) Tj -ET -Q -420 10220 m -430 10220 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 10219 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[3][0][100]) Tj -ET -Q -420 10240 m -430 10240 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 10239 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[3][0][101]) Tj -ET -Q -420 10260 m -430 10260 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 10259 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[3][0][102]) Tj -ET -Q -420 10280 m -430 10280 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 10279 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[3][0][103]) Tj -ET -Q -420 10300 m -430 10300 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 10299 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[3][0][104]) Tj -ET -Q -420 10320 m -430 10320 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 10319 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[3][0][105]) Tj -ET -Q -420 10340 m -430 10340 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 10339 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[3][0][106]) Tj -ET -Q -420 10360 m -430 10360 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 10359 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[3][0][107]) Tj -ET -Q -420 10380 m -430 10380 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 10379 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[3][0][108]) Tj -ET -Q -420 10400 m -430 10400 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 10399 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[3][0][109]) Tj -ET -Q -420 10420 m -430 10420 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 10419 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[3][0][110]) Tj -ET -Q -420 10440 m -430 10440 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 10439 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[3][0][111]) Tj -ET -Q -420 10460 m -430 10460 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 10459 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[3][0][112]) Tj -ET -Q -420 10480 m -430 10480 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 10479 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[3][0][113]) Tj -ET -Q -420 10500 m -430 10500 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 10499 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[3][0][114]) Tj -ET -Q -420 10520 m -430 10520 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 10519 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[3][0][115]) Tj -ET -Q -420 10540 m -430 10540 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 10539 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[3][0][116]) Tj -ET -Q -420 10560 m -430 10560 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 10559 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[3][0][117]) Tj -ET -Q -420 10580 m -430 10580 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 10579 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[3][0][118]) Tj -ET -Q -420 10600 m -430 10600 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 10599 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[3][0][119]) Tj -ET -Q -420 10620 m -430 10620 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 10619 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[3][0][120]) Tj -ET -Q -420 10640 m -430 10640 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 10639 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[3][0][121]) Tj -ET -Q -420 10660 m -430 10660 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 10659 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[3][0][122]) Tj -ET -Q -420 10680 m -430 10680 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 10679 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[3][0][123]) Tj -ET -Q -420 10700 m -430 10700 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 10699 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[3][0][124]) Tj -ET -Q -420 10720 m -430 10720 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 10719 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[3][0][125]) Tj -ET -Q -420 10740 m -430 10740 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 10739 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[3][0][126]) Tj -ET -Q -420 10760 m -430 10760 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 10759 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[3][0][127]) Tj -ET -Q -420 10780 m -430 10780 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 10779 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --166.76 2.07 Td -(per_bank_dram_wb_req_data[4][0][0]) Tj -ET -Q -420 10800 m -430 10800 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 10799 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --166.76 2.07 Td -(per_bank_dram_wb_req_data[4][0][1]) Tj -ET -Q -420 10820 m -430 10820 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 10819 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --166.76 2.07 Td -(per_bank_dram_wb_req_data[4][0][2]) Tj -ET -Q -420 10840 m -430 10840 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 10839 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --166.76 2.07 Td -(per_bank_dram_wb_req_data[4][0][3]) Tj -ET -Q -420 10860 m -430 10860 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 10859 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --166.76 2.07 Td -(per_bank_dram_wb_req_data[4][0][4]) Tj -ET -Q -420 10880 m -430 10880 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 10879 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --166.76 2.07 Td -(per_bank_dram_wb_req_data[4][0][5]) Tj -ET -Q -420 10900 m -430 10900 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 10899 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --166.76 2.07 Td -(per_bank_dram_wb_req_data[4][0][6]) Tj -ET -Q -420 10920 m -430 10920 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 10919 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --166.76 2.07 Td -(per_bank_dram_wb_req_data[4][0][7]) Tj -ET -Q -420 10940 m -430 10940 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 10939 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --166.76 2.07 Td -(per_bank_dram_wb_req_data[4][0][8]) Tj -ET -Q -420 10960 m -430 10960 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 10959 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --166.76 2.07 Td -(per_bank_dram_wb_req_data[4][0][9]) Tj -ET -Q -420 10980 m -430 10980 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 10979 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[4][0][10]) Tj -ET -Q -420 11000 m -430 11000 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 10999 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[4][0][11]) Tj -ET -Q -420 11020 m -430 11020 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 11019 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[4][0][12]) Tj -ET -Q -420 11040 m -430 11040 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 11039 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[4][0][13]) Tj -ET -Q -420 11060 m -430 11060 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 11059 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[4][0][14]) Tj -ET -Q -420 11080 m -430 11080 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 11079 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[4][0][15]) Tj -ET -Q -420 11100 m -430 11100 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 11099 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[4][0][16]) Tj -ET -Q -420 11120 m -430 11120 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 11119 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[4][0][17]) Tj -ET -Q -420 11140 m -430 11140 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 11139 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[4][0][18]) Tj -ET -Q -420 11160 m -430 11160 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 11159 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[4][0][19]) Tj -ET -Q -420 11180 m -430 11180 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 11179 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[4][0][20]) Tj -ET -Q -420 11200 m -430 11200 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 11199 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[4][0][21]) Tj -ET -Q -420 11220 m -430 11220 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 11219 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[4][0][22]) Tj -ET -Q -420 11240 m -430 11240 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 11239 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[4][0][23]) Tj -ET -Q -420 11260 m -430 11260 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 11259 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[4][0][24]) Tj -ET -Q -420 11280 m -430 11280 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 11279 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[4][0][25]) Tj -ET -Q -420 11300 m -430 11300 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 11299 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[4][0][26]) Tj -ET -Q -420 11320 m -430 11320 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 11319 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[4][0][27]) Tj -ET -Q -420 11340 m -430 11340 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 11339 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[4][0][28]) Tj -ET -Q -420 11360 m -430 11360 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 11359 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[4][0][29]) Tj -ET -Q -420 11380 m -430 11380 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 11379 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[4][0][30]) Tj -ET -Q -420 11400 m -430 11400 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 11399 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[4][0][31]) Tj -ET -Q -420 11420 m -430 11420 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 11419 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[4][0][32]) Tj -ET -Q -420 11440 m -430 11440 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 11439 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[4][0][33]) Tj -ET -Q -420 11460 m -430 11460 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 11459 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[4][0][34]) Tj -ET -Q -420 11480 m -430 11480 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 11479 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[4][0][35]) Tj -ET -Q -420 11500 m -430 11500 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 11499 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[4][0][36]) Tj -ET -Q -420 11520 m -430 11520 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 11519 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[4][0][37]) Tj -ET -Q -420 11540 m -430 11540 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 11539 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[4][0][38]) Tj -ET -Q -420 11560 m -430 11560 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 11559 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[4][0][39]) Tj -ET -Q -420 11580 m -430 11580 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 11579 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[4][0][40]) Tj -ET -Q -420 11600 m -430 11600 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 11599 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[4][0][41]) Tj -ET -Q -420 11620 m -430 11620 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 11619 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[4][0][42]) Tj -ET -Q -420 11640 m -430 11640 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 11639 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[4][0][43]) Tj -ET -Q -420 11660 m -430 11660 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 11659 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[4][0][44]) Tj -ET -Q -420 11680 m -430 11680 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 11679 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[4][0][45]) Tj -ET -Q -420 11700 m -430 11700 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 11699 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[4][0][46]) Tj -ET -Q -420 11720 m -430 11720 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 11719 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[4][0][47]) Tj -ET -Q -420 11740 m -430 11740 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 11739 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[4][0][48]) Tj -ET -Q -420 11760 m -430 11760 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 11759 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[4][0][49]) Tj -ET -Q -420 11780 m -430 11780 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 11779 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[4][0][50]) Tj -ET -Q -420 11800 m -430 11800 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 11799 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[4][0][51]) Tj -ET -Q -420 11820 m -430 11820 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 11819 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[4][0][52]) Tj -ET -Q -420 11840 m -430 11840 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 11839 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[4][0][53]) Tj -ET -Q -420 11860 m -430 11860 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 11859 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[4][0][54]) Tj -ET -Q -420 11880 m -430 11880 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 11879 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[4][0][55]) Tj -ET -Q -420 11900 m -430 11900 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 11899 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[4][0][56]) Tj -ET -Q -420 11920 m -430 11920 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 11919 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[4][0][57]) Tj -ET -Q -420 11940 m -430 11940 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 11939 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[4][0][58]) Tj -ET -Q -420 11960 m -430 11960 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 11959 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[4][0][59]) Tj -ET -Q -420 11980 m -430 11980 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 11979 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[4][0][60]) Tj -ET -Q -420 12000 m -430 12000 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 11999 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[4][0][61]) Tj -ET -Q -420 12020 m -430 12020 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 12019 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[4][0][62]) Tj -ET -Q -420 12040 m -430 12040 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 12039 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[4][0][63]) Tj -ET -Q -420 12060 m -430 12060 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 12059 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[4][0][64]) Tj -ET -Q -420 12080 m -430 12080 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 12079 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[4][0][65]) Tj -ET -Q -420 12100 m -430 12100 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 12099 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[4][0][66]) Tj -ET -Q -420 12120 m -430 12120 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 12119 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[4][0][67]) Tj -ET -Q -420 12140 m -430 12140 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 12139 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[4][0][68]) Tj -ET -Q -420 12160 m -430 12160 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 12159 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[4][0][69]) Tj -ET -Q -420 12180 m -430 12180 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 12179 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[4][0][70]) Tj -ET -Q -420 12200 m -430 12200 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 12199 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[4][0][71]) Tj -ET -Q -420 12220 m -430 12220 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 12219 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[4][0][72]) Tj -ET -Q -420 12240 m -430 12240 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 12239 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[4][0][73]) Tj -ET -Q -420 12260 m -430 12260 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 12259 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[4][0][74]) Tj -ET -Q -420 12280 m -430 12280 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 12279 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[4][0][75]) Tj -ET -Q -420 12300 m -430 12300 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 12299 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[4][0][76]) Tj -ET -Q -420 12320 m -430 12320 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 12319 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[4][0][77]) Tj -ET -Q -420 12340 m -430 12340 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 12339 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[4][0][78]) Tj -ET -Q -420 12360 m -430 12360 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 12359 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[4][0][79]) Tj -ET -Q -420 12380 m -430 12380 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 12379 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[4][0][80]) Tj -ET -Q -420 12400 m -430 12400 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 12399 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[4][0][81]) Tj -ET -Q -420 12420 m -430 12420 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 12419 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[4][0][82]) Tj -ET -Q -420 12440 m -430 12440 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 12439 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[4][0][83]) Tj -ET -Q -420 12460 m -430 12460 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 12459 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[4][0][84]) Tj -ET -Q -420 12480 m -430 12480 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 12479 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[4][0][85]) Tj -ET -Q -420 12500 m -430 12500 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 12499 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[4][0][86]) Tj -ET -Q -420 12520 m -430 12520 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 12519 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[4][0][87]) Tj -ET -Q -420 12540 m -430 12540 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 12539 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[4][0][88]) Tj -ET -Q -420 12560 m -430 12560 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 12559 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[4][0][89]) Tj -ET -Q -420 12580 m -430 12580 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 12579 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[4][0][90]) Tj -ET -Q -420 12600 m -430 12600 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 12599 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[4][0][91]) Tj -ET -Q -420 12620 m -430 12620 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 12619 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[4][0][92]) Tj -ET -Q -420 12640 m -430 12640 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 12639 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[4][0][93]) Tj -ET -Q -420 12660 m -430 12660 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 12659 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[4][0][94]) Tj -ET -Q -420 12680 m -430 12680 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 12679 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[4][0][95]) Tj -ET -Q -420 12700 m -430 12700 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 12699 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[4][0][96]) Tj -ET -Q -420 12720 m -430 12720 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 12719 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[4][0][97]) Tj -ET -Q -420 12740 m -430 12740 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 12739 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[4][0][98]) Tj -ET -Q -420 12760 m -430 12760 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 12759 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[4][0][99]) Tj -ET -Q -420 12780 m -430 12780 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 12779 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[4][0][100]) Tj -ET -Q -420 12800 m -430 12800 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 12799 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[4][0][101]) Tj -ET -Q -420 12820 m -430 12820 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 12819 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[4][0][102]) Tj -ET -Q -420 12840 m -430 12840 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 12839 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[4][0][103]) Tj -ET -Q -420 12860 m -430 12860 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 12859 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[4][0][104]) Tj -ET -Q -420 12880 m -430 12880 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 12879 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[4][0][105]) Tj -ET -Q -420 12900 m -430 12900 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 12899 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[4][0][106]) Tj -ET -Q -420 12920 m -430 12920 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 12919 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[4][0][107]) Tj -ET -Q -420 12940 m -430 12940 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 12939 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[4][0][108]) Tj -ET -Q -420 12960 m -430 12960 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 12959 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[4][0][109]) Tj -ET -Q -420 12980 m -430 12980 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 12979 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[4][0][110]) Tj -ET -Q -420 13000 m -430 13000 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 12999 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[4][0][111]) Tj -ET -Q -420 13020 m -430 13020 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 13019 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[4][0][112]) Tj -ET -Q -420 13040 m -430 13040 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 13039 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[4][0][113]) Tj -ET -Q -420 13060 m -430 13060 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 13059 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[4][0][114]) Tj -ET -Q -420 13080 m -430 13080 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 13079 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[4][0][115]) Tj -ET -Q -420 13100 m -430 13100 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 13099 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[4][0][116]) Tj -ET -Q -420 13120 m -430 13120 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 13119 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[4][0][117]) Tj -ET -Q -420 13140 m -430 13140 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 13139 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[4][0][118]) Tj -ET -Q -420 13160 m -430 13160 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 13159 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[4][0][119]) Tj -ET -Q -420 13180 m -430 13180 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 13179 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[4][0][120]) Tj -ET -Q -420 13200 m -430 13200 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 13199 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[4][0][121]) Tj -ET -Q -420 13220 m -430 13220 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 13219 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[4][0][122]) Tj -ET -Q -420 13240 m -430 13240 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 13239 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[4][0][123]) Tj -ET -Q -420 13260 m -430 13260 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 13259 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[4][0][124]) Tj -ET -Q -420 13280 m -430 13280 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 13279 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[4][0][125]) Tj -ET -Q -420 13300 m -430 13300 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 13299 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[4][0][126]) Tj -ET -Q -420 13320 m -430 13320 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 13319 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[4][0][127]) Tj -ET -Q -420 13340 m -430 13340 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 13339 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --166.76 2.07 Td -(per_bank_dram_wb_req_data[5][0][0]) Tj -ET -Q -420 13360 m -430 13360 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 13359 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --166.76 2.07 Td -(per_bank_dram_wb_req_data[5][0][1]) Tj -ET -Q -420 13380 m -430 13380 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 13379 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --166.76 2.07 Td -(per_bank_dram_wb_req_data[5][0][2]) Tj -ET -Q -420 13400 m -430 13400 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 13399 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --166.76 2.07 Td -(per_bank_dram_wb_req_data[5][0][3]) Tj -ET -Q -420 13420 m -430 13420 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 13419 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --166.76 2.07 Td -(per_bank_dram_wb_req_data[5][0][4]) Tj -ET -Q -420 13440 m -430 13440 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 13439 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --166.76 2.07 Td -(per_bank_dram_wb_req_data[5][0][5]) Tj -ET -Q -420 13460 m -430 13460 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 13459 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --166.76 2.07 Td -(per_bank_dram_wb_req_data[5][0][6]) Tj -ET -Q -420 13480 m -430 13480 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 13479 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --166.76 2.07 Td -(per_bank_dram_wb_req_data[5][0][7]) Tj -ET -Q -420 13500 m -430 13500 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 13499 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --166.76 2.07 Td -(per_bank_dram_wb_req_data[5][0][8]) Tj -ET -Q -420 13520 m -430 13520 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 13519 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --166.76 2.07 Td -(per_bank_dram_wb_req_data[5][0][9]) Tj -ET -Q -420 13540 m -430 13540 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 13539 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[5][0][10]) Tj -ET -Q -420 13560 m -430 13560 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 13559 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[5][0][11]) Tj -ET -Q -420 13580 m -430 13580 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 13579 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[5][0][12]) Tj -ET -Q -420 13600 m -430 13600 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 13599 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[5][0][13]) Tj -ET -Q -420 13620 m -430 13620 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 13619 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[5][0][14]) Tj -ET -Q -420 13640 m -430 13640 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 13639 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[5][0][15]) Tj -ET -Q -420 13660 m -430 13660 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 13659 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[5][0][16]) Tj -ET -Q -420 13680 m -430 13680 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 13679 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[5][0][17]) Tj -ET -Q -420 13700 m -430 13700 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 13699 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[5][0][18]) Tj -ET -Q -420 13720 m -430 13720 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 13719 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[5][0][19]) Tj -ET -Q -420 13740 m -430 13740 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 13739 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[5][0][20]) Tj -ET -Q -420 13760 m -430 13760 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 13759 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[5][0][21]) Tj -ET -Q -420 13780 m -430 13780 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 13779 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[5][0][22]) Tj -ET -Q -420 13800 m -430 13800 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 13799 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[5][0][23]) Tj -ET -Q -420 13820 m -430 13820 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 13819 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[5][0][24]) Tj -ET -Q -420 13840 m -430 13840 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 13839 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[5][0][25]) Tj -ET -Q -420 13860 m -430 13860 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 13859 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[5][0][26]) Tj -ET -Q -420 13880 m -430 13880 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 13879 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[5][0][27]) Tj -ET -Q -420 13900 m -430 13900 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 13899 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[5][0][28]) Tj -ET -Q -420 13920 m -430 13920 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 13919 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[5][0][29]) Tj -ET -Q -420 13940 m -430 13940 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 13939 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[5][0][30]) Tj -ET -Q -420 13960 m -430 13960 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 13959 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[5][0][31]) Tj -ET -Q -420 13980 m -430 13980 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 13979 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[5][0][32]) Tj -ET -Q -420 14000 m -430 14000 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 13999 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[5][0][33]) Tj -ET -Q -420 14020 m -430 14020 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 14019 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[5][0][34]) Tj -ET -Q -420 14040 m -430 14040 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 14039 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[5][0][35]) Tj -ET -Q -420 14060 m -430 14060 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 14059 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[5][0][36]) Tj -ET -Q -420 14080 m -430 14080 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 14079 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[5][0][37]) Tj -ET -Q -420 14100 m -430 14100 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 14099 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[5][0][38]) Tj -ET -Q -420 14120 m -430 14120 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 14119 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[5][0][39]) Tj -ET -Q -420 14140 m -430 14140 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 14139 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[5][0][40]) Tj -ET -Q -420 14160 m -430 14160 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 14159 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[5][0][41]) Tj -ET -Q -420 14180 m -430 14180 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 14179 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[5][0][42]) Tj -ET -Q -420 14200 m -430 14200 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 14199 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[5][0][43]) Tj -ET -Q -420 14220 m -430 14220 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 14219 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[5][0][44]) Tj -ET -Q -420 14240 m -430 14240 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 14239 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[5][0][45]) Tj -ET -Q -420 14260 m -430 14260 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 14259 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[5][0][46]) Tj -ET -Q -420 14280 m -430 14280 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 14279 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[5][0][47]) Tj -ET -Q -420 14300 m -430 14300 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 14299 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[5][0][48]) Tj -ET -Q -420 14320 m -430 14320 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 14319 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[5][0][49]) Tj -ET -Q -420 14340 m -430 14340 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 14339 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[5][0][50]) Tj -ET -Q -420 14360 m -430 14360 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 14359 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[5][0][51]) Tj -ET -Q -420 14380 m -430 14380 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 14379 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[5][0][52]) Tj -ET -Q -420 14400 m -430 14400 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 14399 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[5][0][53]) Tj -ET -Q -420 14420 m -430 14420 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 14419 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[5][0][54]) Tj -ET -Q -420 14440 m -430 14440 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 14439 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[5][0][55]) Tj -ET -Q -420 14460 m -430 14460 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 14459 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[5][0][56]) Tj -ET -Q -420 14480 m -430 14480 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 14479 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[5][0][57]) Tj -ET -Q -420 14500 m -430 14500 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 14499 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[5][0][58]) Tj -ET -Q -420 14520 m -430 14520 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 14519 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[5][0][59]) Tj -ET -Q -420 14540 m -430 14540 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 14539 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[5][0][60]) Tj -ET -Q -420 14560 m -430 14560 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 14559 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[5][0][61]) Tj -ET -Q -420 14580 m -430 14580 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 14579 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[5][0][62]) Tj -ET -Q -420 14600 m -430 14600 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 14599 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[5][0][63]) Tj -ET -Q -420 14620 m -430 14620 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 14619 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[5][0][64]) Tj -ET -Q -420 14640 m -430 14640 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 14639 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[5][0][65]) Tj -ET -Q -420 14660 m -430 14660 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 14659 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[5][0][66]) Tj -ET -Q -420 14680 m -430 14680 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 14679 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[5][0][67]) Tj -ET -Q -420 14700 m -430 14700 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 14699 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[5][0][68]) Tj -ET -Q -420 14720 m -430 14720 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 14719 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[5][0][69]) Tj -ET -Q -420 14740 m -430 14740 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 14739 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[5][0][70]) Tj -ET -Q -420 14760 m -430 14760 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 14759 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[5][0][71]) Tj -ET -Q -420 14780 m -430 14780 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 14779 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[5][0][72]) Tj -ET -Q -420 14800 m -430 14800 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 14799 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[5][0][73]) Tj -ET -Q -420 14820 m -430 14820 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 14819 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[5][0][74]) Tj -ET -Q -420 14840 m -430 14840 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 14839 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[5][0][75]) Tj -ET -Q -420 14860 m -430 14860 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 14859 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[5][0][76]) Tj -ET -Q -420 14880 m -430 14880 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 14879 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[5][0][77]) Tj -ET -Q -420 14900 m -430 14900 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 14899 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[5][0][78]) Tj -ET -Q -420 14920 m -430 14920 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 14919 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[5][0][79]) Tj -ET -Q -420 14940 m -430 14940 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 14939 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[5][0][80]) Tj -ET -Q -420 14960 m -430 14960 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 14959 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[5][0][81]) Tj -ET -Q -420 14980 m -430 14980 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 14979 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[5][0][82]) Tj -ET -Q -420 15000 m -430 15000 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 14999 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[5][0][83]) Tj -ET -Q -420 15020 m -430 15020 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 15019 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[5][0][84]) Tj -ET -Q -420 15040 m -430 15040 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 15039 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[5][0][85]) Tj -ET -Q -420 15060 m -430 15060 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 15059 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[5][0][86]) Tj -ET -Q -420 15080 m -430 15080 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 15079 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[5][0][87]) Tj -ET -Q -420 15100 m -430 15100 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 15099 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[5][0][88]) Tj -ET -Q -420 15120 m -430 15120 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 15119 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[5][0][89]) Tj -ET -Q -420 15140 m -430 15140 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 15139 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[5][0][90]) Tj -ET -Q -420 15160 m -430 15160 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 15159 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[5][0][91]) Tj -ET -Q -420 15180 m -430 15180 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 15179 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[5][0][92]) Tj -ET -Q -420 15200 m -430 15200 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 15199 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[5][0][93]) Tj -ET -Q -420 15220 m -430 15220 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 15219 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[5][0][94]) Tj -ET -Q -420 15240 m -430 15240 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 15239 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[5][0][95]) Tj -ET -Q -420 15260 m -430 15260 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 15259 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[5][0][96]) Tj -ET -Q -420 15280 m -430 15280 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 15279 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[5][0][97]) Tj -ET -Q -420 15300 m -430 15300 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 15299 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[5][0][98]) Tj -ET -Q -420 15320 m -430 15320 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 15319 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[5][0][99]) Tj -ET -Q -420 15340 m -430 15340 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 15339 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[5][0][100]) Tj -ET -Q -420 15360 m -430 15360 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 15359 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[5][0][101]) Tj -ET -Q -420 15380 m -430 15380 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 15379 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[5][0][102]) Tj -ET -Q -420 15400 m -430 15400 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 15399 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[5][0][103]) Tj -ET -Q -420 15420 m -430 15420 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 15419 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[5][0][104]) Tj -ET -Q -420 15440 m -430 15440 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 15439 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[5][0][105]) Tj -ET -Q -420 15460 m -430 15460 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 15459 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[5][0][106]) Tj -ET -Q -420 15480 m -430 15480 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 15479 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[5][0][107]) Tj -ET -Q -420 15500 m -430 15500 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 15499 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[5][0][108]) Tj -ET -Q -420 15520 m -430 15520 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 15519 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[5][0][109]) Tj -ET -Q -420 15540 m -430 15540 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 15539 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[5][0][110]) Tj -ET -Q -420 15560 m -430 15560 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 15559 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[5][0][111]) Tj -ET -Q -420 15580 m -430 15580 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 15579 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[5][0][112]) Tj -ET -Q -420 15600 m -430 15600 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 15599 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[5][0][113]) Tj -ET -Q -420 15620 m -430 15620 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 15619 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[5][0][114]) Tj -ET -Q -420 15640 m -430 15640 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 15639 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[5][0][115]) Tj -ET -Q -420 15660 m -430 15660 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 15659 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[5][0][116]) Tj -ET -Q -420 15680 m -430 15680 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 15679 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[5][0][117]) Tj -ET -Q -420 15700 m -430 15700 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 15699 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[5][0][118]) Tj -ET -Q -420 15720 m -430 15720 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 15719 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[5][0][119]) Tj -ET -Q -420 15740 m -430 15740 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 15739 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[5][0][120]) Tj -ET -Q -420 15760 m -430 15760 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 15759 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[5][0][121]) Tj -ET -Q -420 15780 m -430 15780 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 15779 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[5][0][122]) Tj -ET -Q -420 15800 m -430 15800 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 15799 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[5][0][123]) Tj -ET -Q -420 15820 m -430 15820 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 15819 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[5][0][124]) Tj -ET -Q -420 15840 m -430 15840 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 15839 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[5][0][125]) Tj -ET -Q -420 15860 m -430 15860 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 15859 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[5][0][126]) Tj -ET -Q -420 15880 m -430 15880 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 15879 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[5][0][127]) Tj -ET -Q -420 15900 m -430 15900 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 15899 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --166.76 2.07 Td -(per_bank_dram_wb_req_data[6][0][0]) Tj -ET -Q -420 15920 m -430 15920 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 15919 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --166.76 2.07 Td -(per_bank_dram_wb_req_data[6][0][1]) Tj -ET -Q -420 15940 m -430 15940 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 15939 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --166.76 2.07 Td -(per_bank_dram_wb_req_data[6][0][2]) Tj -ET -Q -420 15960 m -430 15960 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 15959 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --166.76 2.07 Td -(per_bank_dram_wb_req_data[6][0][3]) Tj -ET -Q -420 15980 m -430 15980 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 15979 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --166.76 2.07 Td -(per_bank_dram_wb_req_data[6][0][4]) Tj -ET -Q -420 16000 m -430 16000 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 15999 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --166.76 2.07 Td -(per_bank_dram_wb_req_data[6][0][5]) Tj -ET -Q -420 16020 m -430 16020 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 16019 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --166.76 2.07 Td -(per_bank_dram_wb_req_data[6][0][6]) Tj -ET -Q -420 16040 m -430 16040 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 16039 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --166.76 2.07 Td -(per_bank_dram_wb_req_data[6][0][7]) Tj -ET -Q -420 16060 m -430 16060 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 16059 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --166.76 2.07 Td -(per_bank_dram_wb_req_data[6][0][8]) Tj -ET -Q -420 16080 m -430 16080 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 16079 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --166.76 2.07 Td -(per_bank_dram_wb_req_data[6][0][9]) Tj -ET -Q -420 16100 m -430 16100 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 16099 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[6][0][10]) Tj -ET -Q -420 16120 m -430 16120 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 16119 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[6][0][11]) Tj -ET -Q -420 16140 m -430 16140 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 16139 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[6][0][12]) Tj -ET -Q -420 16160 m -430 16160 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 16159 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[6][0][13]) Tj -ET -Q -420 16180 m -430 16180 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 16179 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[6][0][14]) Tj -ET -Q -420 16200 m -430 16200 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 16199 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[6][0][15]) Tj -ET -Q -420 16220 m -430 16220 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 16219 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[6][0][16]) Tj -ET -Q -420 16240 m -430 16240 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 16239 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[6][0][17]) Tj -ET -Q -420 16260 m -430 16260 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 16259 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[6][0][18]) Tj -ET -Q -420 16280 m -430 16280 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 16279 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[6][0][19]) Tj -ET -Q -420 16300 m -430 16300 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 16299 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[6][0][20]) Tj -ET -Q -420 16320 m -430 16320 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 16319 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[6][0][21]) Tj -ET -Q -420 16340 m -430 16340 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 16339 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[6][0][22]) Tj -ET -Q -420 16360 m -430 16360 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 16359 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[6][0][23]) Tj -ET -Q -420 16380 m -430 16380 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 16379 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[6][0][24]) Tj -ET -Q -420 16400 m -430 16400 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 16399 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[6][0][25]) Tj -ET -Q -420 16420 m -430 16420 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 16419 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[6][0][26]) Tj -ET -Q -420 16440 m -430 16440 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 16439 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[6][0][27]) Tj -ET -Q -420 16460 m -430 16460 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 16459 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[6][0][28]) Tj -ET -Q -420 16480 m -430 16480 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 16479 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[6][0][29]) Tj -ET -Q -420 16500 m -430 16500 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 16499 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[6][0][30]) Tj -ET -Q -420 16520 m -430 16520 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 16519 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[6][0][31]) Tj -ET -Q -420 16540 m -430 16540 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 16539 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[6][0][32]) Tj -ET -Q -420 16560 m -430 16560 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 16559 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[6][0][33]) Tj -ET -Q -420 16580 m -430 16580 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 16579 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[6][0][34]) Tj -ET -Q -420 16600 m -430 16600 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 16599 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[6][0][35]) Tj -ET -Q -420 16620 m -430 16620 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 16619 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[6][0][36]) Tj -ET -Q -420 16640 m -430 16640 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 16639 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[6][0][37]) Tj -ET -Q -420 16660 m -430 16660 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 16659 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[6][0][38]) Tj -ET -Q -420 16680 m -430 16680 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 16679 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[6][0][39]) Tj -ET -Q -420 16700 m -430 16700 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 16699 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[6][0][40]) Tj -ET -Q -420 16720 m -430 16720 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 16719 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[6][0][41]) Tj -ET -Q -420 16740 m -430 16740 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 16739 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[6][0][42]) Tj -ET -Q -420 16760 m -430 16760 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 16759 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[6][0][43]) Tj -ET -Q -420 16780 m -430 16780 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 16779 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[6][0][44]) Tj -ET -Q -420 16800 m -430 16800 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 16799 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[6][0][45]) Tj -ET -Q -420 16820 m -430 16820 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 16819 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[6][0][46]) Tj -ET -Q -420 16840 m -430 16840 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 16839 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[6][0][47]) Tj -ET -Q -420 16860 m -430 16860 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 16859 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[6][0][48]) Tj -ET -Q -420 16880 m -430 16880 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 16879 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[6][0][49]) Tj -ET -Q -420 16900 m -430 16900 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 16899 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[6][0][50]) Tj -ET -Q -420 16920 m -430 16920 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 16919 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[6][0][51]) Tj -ET -Q -420 16940 m -430 16940 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 16939 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[6][0][52]) Tj -ET -Q -420 16960 m -430 16960 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 16959 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[6][0][53]) Tj -ET -Q -420 16980 m -430 16980 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 16979 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[6][0][54]) Tj -ET -Q -420 17000 m -430 17000 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 16999 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[6][0][55]) Tj -ET -Q -420 17020 m -430 17020 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 17019 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[6][0][56]) Tj -ET -Q -420 17040 m -430 17040 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 17039 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[6][0][57]) Tj -ET -Q -420 17060 m -430 17060 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 17059 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[6][0][58]) Tj -ET -Q -420 17080 m -430 17080 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 17079 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[6][0][59]) Tj -ET -Q -420 17100 m -430 17100 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 17099 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[6][0][60]) Tj -ET -Q -420 17120 m -430 17120 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 17119 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[6][0][61]) Tj -ET -Q -420 17140 m -430 17140 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 17139 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[6][0][62]) Tj -ET -Q -420 17160 m -430 17160 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 17159 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[6][0][63]) Tj -ET -Q -420 17180 m -430 17180 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 17179 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[6][0][64]) Tj -ET -Q -420 17200 m -430 17200 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 17199 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[6][0][65]) Tj -ET -Q -420 17220 m -430 17220 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 17219 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[6][0][66]) Tj -ET -Q -420 17240 m -430 17240 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 17239 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[6][0][67]) Tj -ET -Q -420 17260 m -430 17260 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 17259 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[6][0][68]) Tj -ET -Q -420 17280 m -430 17280 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 17279 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[6][0][69]) Tj -ET -Q -420 17300 m -430 17300 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 17299 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[6][0][70]) Tj -ET -Q -420 17320 m -430 17320 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 17319 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[6][0][71]) Tj -ET -Q -420 17340 m -430 17340 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 17339 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[6][0][72]) Tj -ET -Q -420 17360 m -430 17360 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 17359 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[6][0][73]) Tj -ET -Q -420 17380 m -430 17380 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 17379 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[6][0][74]) Tj -ET -Q -420 17400 m -430 17400 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 17399 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[6][0][75]) Tj -ET -Q -420 17420 m -430 17420 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 17419 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[6][0][76]) Tj -ET -Q -420 17440 m -430 17440 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 17439 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[6][0][77]) Tj -ET -Q -420 17460 m -430 17460 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 17459 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[6][0][78]) Tj -ET -Q -420 17480 m -430 17480 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 17479 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[6][0][79]) Tj -ET -Q -420 17500 m -430 17500 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 17499 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[6][0][80]) Tj -ET -Q -420 17520 m -430 17520 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 17519 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[6][0][81]) Tj -ET -Q -420 17540 m -430 17540 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 17539 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[6][0][82]) Tj -ET -Q -420 17560 m -430 17560 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 17559 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[6][0][83]) Tj -ET -Q -420 17580 m -430 17580 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 17579 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[6][0][84]) Tj -ET -Q -420 17600 m -430 17600 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 17599 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[6][0][85]) Tj -ET -Q -420 17620 m -430 17620 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 17619 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[6][0][86]) Tj -ET -Q -420 17640 m -430 17640 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 17639 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[6][0][87]) Tj -ET -Q -420 17660 m -430 17660 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 17659 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[6][0][88]) Tj -ET -Q -420 17680 m -430 17680 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 17679 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[6][0][89]) Tj -ET -Q -420 17700 m -430 17700 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 17699 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[6][0][90]) Tj -ET -Q -420 17720 m -430 17720 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 17719 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[6][0][91]) Tj -ET -Q -420 17740 m -430 17740 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 17739 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[6][0][92]) Tj -ET -Q -420 17760 m -430 17760 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 17759 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[6][0][93]) Tj -ET -Q -420 17780 m -430 17780 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 17779 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[6][0][94]) Tj -ET -Q -420 17800 m -430 17800 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 17799 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[6][0][95]) Tj -ET -Q -420 17820 m -430 17820 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 17819 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[6][0][96]) Tj -ET -Q -420 17840 m -430 17840 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 17839 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[6][0][97]) Tj -ET -Q -420 17860 m -430 17860 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 17859 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[6][0][98]) Tj -ET -Q -420 17880 m -430 17880 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 17879 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[6][0][99]) Tj -ET -Q -420 17900 m -430 17900 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 17899 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[6][0][100]) Tj -ET -Q -420 17920 m -430 17920 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 17919 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[6][0][101]) Tj -ET -Q -420 17940 m -430 17940 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 17939 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[6][0][102]) Tj -ET -Q -420 17960 m -430 17960 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 17959 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[6][0][103]) Tj -ET -Q -420 17980 m -430 17980 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 17979 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[6][0][104]) Tj -ET -Q -420 18000 m -430 18000 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 17999 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[6][0][105]) Tj -ET -Q -420 18020 m -430 18020 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 18019 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[6][0][106]) Tj -ET -Q -420 18040 m -430 18040 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 18039 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[6][0][107]) Tj -ET -Q -420 18060 m -430 18060 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 18059 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[6][0][108]) Tj -ET -Q -420 18080 m -430 18080 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 18079 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[6][0][109]) Tj -ET -Q -420 18100 m -430 18100 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 18099 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[6][0][110]) Tj -ET -Q -420 18120 m -430 18120 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 18119 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[6][0][111]) Tj -ET -Q -420 18140 m -430 18140 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 18139 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[6][0][112]) Tj -ET -Q -420 18160 m -430 18160 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 18159 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[6][0][113]) Tj -ET -Q -420 18180 m -430 18180 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 18179 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[6][0][114]) Tj -ET -Q -420 18200 m -430 18200 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 18199 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[6][0][115]) Tj -ET -Q -420 18220 m -430 18220 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 18219 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[6][0][116]) Tj -ET -Q -420 18240 m -430 18240 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 18239 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[6][0][117]) Tj -ET -Q -420 18260 m -430 18260 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 18259 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[6][0][118]) Tj -ET -Q -420 18280 m -430 18280 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 18279 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[6][0][119]) Tj -ET -Q -420 18300 m -430 18300 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 18299 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[6][0][120]) Tj -ET -Q -420 18320 m -430 18320 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 18319 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[6][0][121]) Tj -ET -Q -420 18340 m -430 18340 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 18339 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[6][0][122]) Tj -ET -Q -420 18360 m -430 18360 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 18359 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[6][0][123]) Tj -ET -Q -420 18380 m -430 18380 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 18379 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[6][0][124]) Tj -ET -Q -420 18400 m -430 18400 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 18399 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[6][0][125]) Tj -ET -Q -420 18420 m -430 18420 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 18419 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[6][0][126]) Tj -ET -Q -420 18440 m -430 18440 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 18439 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[6][0][127]) Tj -ET -Q -420 18460 m -430 18460 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 18459 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --166.76 2.07 Td -(per_bank_dram_wb_req_data[7][0][0]) Tj -ET -Q -420 18480 m -430 18480 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 18479 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --166.76 2.07 Td -(per_bank_dram_wb_req_data[7][0][1]) Tj -ET -Q -420 18500 m -430 18500 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 18499 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --166.76 2.07 Td -(per_bank_dram_wb_req_data[7][0][2]) Tj -ET -Q -420 18520 m -430 18520 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 18519 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --166.76 2.07 Td -(per_bank_dram_wb_req_data[7][0][3]) Tj -ET -Q -420 18540 m -430 18540 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 18539 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --166.76 2.07 Td -(per_bank_dram_wb_req_data[7][0][4]) Tj -ET -Q -420 18560 m -430 18560 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 18559 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --166.76 2.07 Td -(per_bank_dram_wb_req_data[7][0][5]) Tj -ET -Q -420 18580 m -430 18580 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 18579 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --166.76 2.07 Td -(per_bank_dram_wb_req_data[7][0][6]) Tj -ET -Q -420 18600 m -430 18600 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 18599 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --166.76 2.07 Td -(per_bank_dram_wb_req_data[7][0][7]) Tj -ET -Q -420 18620 m -430 18620 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 18619 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --166.76 2.07 Td -(per_bank_dram_wb_req_data[7][0][8]) Tj -ET -Q -420 18640 m -430 18640 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 18639 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --166.76 2.07 Td -(per_bank_dram_wb_req_data[7][0][9]) Tj -ET -Q -420 18660 m -430 18660 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 18659 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[7][0][10]) Tj -ET -Q -420 18680 m -430 18680 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 18679 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[7][0][11]) Tj -ET -Q -420 18700 m -430 18700 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 18699 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[7][0][12]) Tj -ET -Q -420 18720 m -430 18720 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 18719 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[7][0][13]) Tj -ET -Q -420 18740 m -430 18740 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 18739 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[7][0][14]) Tj -ET -Q -420 18760 m -430 18760 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 18759 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[7][0][15]) Tj -ET -Q -420 18780 m -430 18780 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 18779 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[7][0][16]) Tj -ET -Q -420 18800 m -430 18800 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 18799 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[7][0][17]) Tj -ET -Q -420 18820 m -430 18820 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 18819 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[7][0][18]) Tj -ET -Q -420 18840 m -430 18840 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 18839 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[7][0][19]) Tj -ET -Q -420 18860 m -430 18860 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 18859 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[7][0][20]) Tj -ET -Q -420 18880 m -430 18880 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 18879 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[7][0][21]) Tj -ET -Q -420 18900 m -430 18900 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 18899 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[7][0][22]) Tj -ET -Q -420 18920 m -430 18920 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 18919 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[7][0][23]) Tj -ET -Q -420 18940 m -430 18940 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 18939 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[7][0][24]) Tj -ET -Q -420 18960 m -430 18960 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 18959 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[7][0][25]) Tj -ET -Q -420 18980 m -430 18980 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 18979 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[7][0][26]) Tj -ET -Q -420 19000 m -430 19000 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 18999 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[7][0][27]) Tj -ET -Q -420 19020 m -430 19020 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 19019 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[7][0][28]) Tj -ET -Q -420 19040 m -430 19040 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 19039 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[7][0][29]) Tj -ET -Q -420 19060 m -430 19060 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 19059 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[7][0][30]) Tj -ET -Q -420 19080 m -430 19080 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 19079 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[7][0][31]) Tj -ET -Q -420 19100 m -430 19100 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 19099 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[7][0][32]) Tj -ET -Q -420 19120 m -430 19120 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 19119 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[7][0][33]) Tj -ET -Q -420 19140 m -430 19140 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 19139 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[7][0][34]) Tj -ET -Q -420 19160 m -430 19160 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 19159 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[7][0][35]) Tj -ET -Q -420 19180 m -430 19180 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 19179 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[7][0][36]) Tj -ET -Q -420 19200 m -430 19200 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 19199 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[7][0][37]) Tj -ET -Q -420 19220 m -430 19220 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 19219 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[7][0][38]) Tj -ET -Q -420 19240 m -430 19240 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 19239 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[7][0][39]) Tj -ET -Q -420 19260 m -430 19260 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 19259 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[7][0][40]) Tj -ET -Q -420 19280 m -430 19280 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 19279 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[7][0][41]) Tj -ET -Q -420 19300 m -430 19300 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 19299 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[7][0][42]) Tj -ET -Q -420 19320 m -430 19320 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 19319 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[7][0][43]) Tj -ET -Q -420 19340 m -430 19340 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 19339 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[7][0][44]) Tj -ET -Q -420 19360 m -430 19360 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 19359 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[7][0][45]) Tj -ET -Q -420 19380 m -430 19380 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 19379 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[7][0][46]) Tj -ET -Q -420 19400 m -430 19400 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 19399 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[7][0][47]) Tj -ET -Q -420 19420 m -430 19420 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 19419 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[7][0][48]) Tj -ET -Q -420 19440 m -430 19440 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 19439 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[7][0][49]) Tj -ET -Q -420 19460 m -430 19460 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 19459 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[7][0][50]) Tj -ET -Q -420 19480 m -430 19480 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 19479 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[7][0][51]) Tj -ET -Q -420 19500 m -430 19500 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 19499 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[7][0][52]) Tj -ET -Q -420 19520 m -430 19520 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 19519 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[7][0][53]) Tj -ET -Q -420 19540 m -430 19540 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 19539 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[7][0][54]) Tj -ET -Q -420 19560 m -430 19560 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 19559 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[7][0][55]) Tj -ET -Q -420 19580 m -430 19580 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 19579 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[7][0][56]) Tj -ET -Q -420 19600 m -430 19600 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 19599 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[7][0][57]) Tj -ET -Q -420 19620 m -430 19620 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 19619 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[7][0][58]) Tj -ET -Q -420 19640 m -430 19640 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 19639 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[7][0][59]) Tj -ET -Q -420 19660 m -430 19660 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 19659 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[7][0][60]) Tj -ET -Q -420 19680 m -430 19680 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 19679 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[7][0][61]) Tj -ET -Q -420 19700 m -430 19700 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 19699 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[7][0][62]) Tj -ET -Q -420 19720 m -430 19720 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 19719 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[7][0][63]) Tj -ET -Q -420 19740 m -430 19740 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 19739 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[7][0][64]) Tj -ET -Q -420 19760 m -430 19760 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 19759 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[7][0][65]) Tj -ET -Q -420 19780 m -430 19780 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 19779 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[7][0][66]) Tj -ET -Q -420 19800 m -430 19800 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 19799 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[7][0][67]) Tj -ET -Q -420 19820 m -430 19820 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 19819 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[7][0][68]) Tj -ET -Q -420 19840 m -430 19840 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 19839 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[7][0][69]) Tj -ET -Q -420 19860 m -430 19860 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 19859 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[7][0][70]) Tj -ET -Q -420 19880 m -430 19880 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 19879 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[7][0][71]) Tj -ET -Q -420 19900 m -430 19900 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 19899 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[7][0][72]) Tj -ET -Q -420 19920 m -430 19920 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 19919 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[7][0][73]) Tj -ET -Q -420 19940 m -430 19940 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 19939 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[7][0][74]) Tj -ET -Q -420 19960 m -430 19960 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 19959 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[7][0][75]) Tj -ET -Q -420 19980 m -430 19980 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 19979 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[7][0][76]) Tj -ET -Q -420 20000 m -430 20000 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 19999 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[7][0][77]) Tj -ET -Q -420 20020 m -430 20020 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 20019 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[7][0][78]) Tj -ET -Q -420 20040 m -430 20040 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 20039 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[7][0][79]) Tj -ET -Q -420 20060 m -430 20060 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 20059 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[7][0][80]) Tj -ET -Q -420 20080 m -430 20080 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 20079 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[7][0][81]) Tj -ET -Q -420 20100 m -430 20100 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 20099 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[7][0][82]) Tj -ET -Q -420 20120 m -430 20120 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 20119 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[7][0][83]) Tj -ET -Q -420 20140 m -430 20140 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 20139 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[7][0][84]) Tj -ET -Q -420 20160 m -430 20160 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 20159 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[7][0][85]) Tj -ET -Q -420 20180 m -430 20180 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 20179 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[7][0][86]) Tj -ET -Q -420 20200 m -430 20200 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 20199 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[7][0][87]) Tj -ET -Q -420 20220 m -430 20220 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 20219 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[7][0][88]) Tj -ET -Q -420 20240 m -430 20240 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 20239 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[7][0][89]) Tj -ET -Q -420 20260 m -430 20260 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 20259 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[7][0][90]) Tj -ET -Q -420 20280 m -430 20280 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 20279 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[7][0][91]) Tj -ET -Q -420 20300 m -430 20300 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 20299 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[7][0][92]) Tj -ET -Q -420 20320 m -430 20320 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 20319 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[7][0][93]) Tj -ET -Q -420 20340 m -430 20340 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 20339 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[7][0][94]) Tj -ET -Q -420 20360 m -430 20360 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 20359 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[7][0][95]) Tj -ET -Q -420 20380 m -430 20380 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 20379 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[7][0][96]) Tj -ET -Q -420 20400 m -430 20400 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 20399 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[7][0][97]) Tj -ET -Q -420 20420 m -430 20420 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 20419 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[7][0][98]) Tj -ET -Q -420 20440 m -430 20440 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 20439 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.32 2.07 Td -(per_bank_dram_wb_req_data[7][0][99]) Tj -ET -Q -420 20460 m -430 20460 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 20459 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[7][0][100]) Tj -ET -Q -420 20480 m -430 20480 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 20479 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[7][0][101]) Tj -ET -Q -420 20500 m -430 20500 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 20499 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[7][0][102]) Tj -ET -Q -420 20520 m -430 20520 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 20519 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[7][0][103]) Tj -ET -Q -420 20540 m -430 20540 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 20539 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[7][0][104]) Tj -ET -Q -420 20560 m -430 20560 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 20559 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[7][0][105]) Tj -ET -Q -420 20580 m -430 20580 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 20579 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[7][0][106]) Tj -ET -Q -420 20600 m -430 20600 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 20599 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[7][0][107]) Tj -ET -Q -420 20620 m -430 20620 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 20619 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[7][0][108]) Tj -ET -Q -420 20640 m -430 20640 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 20639 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[7][0][109]) Tj -ET -Q -420 20660 m -430 20660 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 20659 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[7][0][110]) Tj -ET -Q -420 20680 m -430 20680 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 20679 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[7][0][111]) Tj -ET -Q -420 20700 m -430 20700 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 20699 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[7][0][112]) Tj -ET -Q -420 20720 m -430 20720 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 20719 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[7][0][113]) Tj -ET -Q -420 20740 m -430 20740 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 20739 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[7][0][114]) Tj -ET -Q -420 20760 m -430 20760 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 20759 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[7][0][115]) Tj -ET -Q -420 20780 m -430 20780 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 20779 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[7][0][116]) Tj -ET -Q -420 20800 m -430 20800 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 20799 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[7][0][117]) Tj -ET -Q -420 20820 m -430 20820 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 20819 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[7][0][118]) Tj -ET -Q -420 20840 m -430 20840 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 20839 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[7][0][119]) Tj -ET -Q -420 20860 m -430 20860 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 20859 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[7][0][120]) Tj -ET -Q -420 20880 m -430 20880 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 20879 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[7][0][121]) Tj -ET -Q -420 20900 m -430 20900 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 20899 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[7][0][122]) Tj -ET -Q -420 20920 m -430 20920 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 20919 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[7][0][123]) Tj -ET -Q -420 20940 m -430 20940 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 20939 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[7][0][124]) Tj -ET -Q -420 20960 m -430 20960 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 20959 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[7][0][125]) Tj -ET -Q -420 20980 m -430 20980 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 20979 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[7][0][126]) Tj -ET -Q -420 21000 m -430 21000 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 20999 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --177.88 2.07 Td -(per_bank_dram_wb_req_data[7][0][127]) Tj -ET -Q -420 180 m -430 180 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 179 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --73.36 2.07 Td -(dram_req_ready) Tj -ET -Q -3 w -420 360 m -430 360 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 359 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --153.4 2.07 Td -(per_bank_dram_fill_req_valid[7..0]) Tj -ET -Q -420 200 m -430 200 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 199 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --169.53 2.07 Td -(per_bank_dram_fill_req_addr[0][31..0]) Tj -ET -Q -420 220 m -430 220 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 219 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --169.53 2.07 Td -(per_bank_dram_fill_req_addr[1][31..0]) Tj -ET -Q -420 240 m -430 240 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 239 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --169.53 2.07 Td -(per_bank_dram_fill_req_addr[2][31..0]) Tj -ET -Q -420 260 m -430 260 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 259 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --169.53 2.07 Td -(per_bank_dram_fill_req_addr[3][31..0]) Tj -ET -Q -420 280 m -430 280 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 279 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --169.53 2.07 Td -(per_bank_dram_fill_req_addr[4][31..0]) Tj -ET -Q -420 300 m -430 300 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 299 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --169.53 2.07 Td -(per_bank_dram_fill_req_addr[5][31..0]) Tj -ET -Q -420 320 m -430 320 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 319 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --169.53 2.07 Td -(per_bank_dram_fill_req_addr[6][31..0]) Tj -ET -Q -420 340 m -430 340 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 339 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --169.53 2.07 Td -(per_bank_dram_fill_req_addr[7][31..0]) Tj -ET -Q -420 21020 m -430 21020 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 21019 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --156.74 2.07 Td -(per_bank_dram_wb_req_valid[7..0]) Tj -ET -Q -420 380 m -430 380 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 379 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.87 2.07 Td -(per_bank_dram_wb_req_addr[0][31..0]) Tj -ET -Q -420 400 m -430 400 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 399 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.87 2.07 Td -(per_bank_dram_wb_req_addr[1][31..0]) Tj -ET -Q -420 420 m -430 420 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 419 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.87 2.07 Td -(per_bank_dram_wb_req_addr[2][31..0]) Tj -ET -Q -420 440 m -430 440 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 439 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.87 2.07 Td -(per_bank_dram_wb_req_addr[3][31..0]) Tj -ET -Q -420 460 m -430 460 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 459 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.87 2.07 Td -(per_bank_dram_wb_req_addr[4][31..0]) Tj -ET -Q -420 480 m -430 480 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 479 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.87 2.07 Td -(per_bank_dram_wb_req_addr[5][31..0]) Tj -ET -Q -420 500 m -430 500 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 499 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.87 2.07 Td -(per_bank_dram_wb_req_addr[6][31..0]) Tj -ET -Q -420 520 m -430 520 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 428 519 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --172.87 2.07 Td -(per_bank_dram_wb_req_addr[7][31..0]) Tj -ET -Q -1 w -500 10520 m -490 10520 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 496 10519 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(dfqq_full) Tj -ET -Q -500 10640 m -490 10640 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 496 10639 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(dram_req_read) Tj -ET -Q -500 10660 m -490 10660 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 496 10659 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(dram_req_write) Tj -ET -Q -3 w -500 10680 m -490 10680 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 496 10679 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(per_bank_dram_wb_queue_pop[7..0]) Tj -ET -Q -500 10540 m -490 10540 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 496 10539 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(dram_req_addr[31..0]) Tj -ET -Q -500 10560 m -490 10560 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 496 10559 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(dram_req_data[0][31..0]) Tj -ET -Q -500 10580 m -490 10580 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 496 10579 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(dram_req_data[1][31..0]) Tj -ET -Q -500 10600 m -490 10600 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 496 10599 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(dram_req_data[2][31..0]) Tj -ET -Q -500 10620 m -490 10620 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 496 10619 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(dram_req_data[3][31..0]) Tj -ET -Q -1 w -440 160 m -430 160 l -S -440 21040 m -430 21040 l -S -440 540 m -430 540 l -S -440 560 m -430 560 l -S -440 580 m -430 580 l -S -440 600 m -430 600 l -S -440 620 m -430 620 l -S -440 640 m -430 640 l -S -440 660 m -430 660 l -S -440 680 m -430 680 l -S -440 700 m -430 700 l -S -440 720 m -430 720 l -S -440 740 m -430 740 l -S -440 760 m -430 760 l -S -440 780 m -430 780 l -S -440 800 m -430 800 l -S -440 820 m -430 820 l -S -440 840 m -430 840 l -S -440 860 m -430 860 l -S -440 880 m -430 880 l -S -440 900 m -430 900 l -S -440 920 m -430 920 l -S -440 940 m -430 940 l -S -440 960 m -430 960 l -S -440 980 m -430 980 l -S -440 1000 m -430 1000 l -S -440 1020 m -430 1020 l -S -440 1040 m -430 1040 l -S -440 1060 m -430 1060 l -S -440 1080 m -430 1080 l -S -440 1100 m -430 1100 l -S -440 1120 m -430 1120 l -S -440 1140 m -430 1140 l -S -440 1160 m -430 1160 l -S -440 1180 m -430 1180 l -S -440 1200 m -430 1200 l -S -440 1220 m -430 1220 l -S -440 1240 m -430 1240 l -S -440 1260 m -430 1260 l -S -440 1280 m -430 1280 l -S -440 1300 m -430 1300 l -S -440 1320 m -430 1320 l -S -440 1340 m -430 1340 l -S -440 1360 m -430 1360 l -S -440 1380 m -430 1380 l -S -440 1400 m -430 1400 l -S -440 1420 m -430 1420 l -S -440 1440 m -430 1440 l -S -440 1460 m -430 1460 l -S -440 1480 m -430 1480 l -S -440 1500 m -430 1500 l -S -440 1520 m -430 1520 l -S -440 1540 m -430 1540 l -S -440 1560 m -430 1560 l -S -440 1580 m -430 1580 l -S -440 1600 m -430 1600 l -S -440 1620 m -430 1620 l -S -440 1640 m -430 1640 l -S -440 1660 m -430 1660 l -S -440 1680 m -430 1680 l -S -440 1700 m -430 1700 l -S -440 1720 m -430 1720 l -S -440 1740 m -430 1740 l -S -440 1760 m -430 1760 l -S -440 1780 m -430 1780 l -S -440 1800 m -430 1800 l -S -440 1820 m -430 1820 l -S -440 1840 m -430 1840 l -S -440 1860 m -430 1860 l -S -440 1880 m -430 1880 l -S -440 1900 m -430 1900 l -S -440 1920 m -430 1920 l -S -440 1940 m -430 1940 l -S -440 1960 m -430 1960 l -S -440 1980 m -430 1980 l -S -440 2000 m -430 2000 l -S -440 2020 m -430 2020 l -S -440 2040 m -430 2040 l -S -440 2060 m -430 2060 l -S -440 2080 m -430 2080 l -S -440 2100 m -430 2100 l -S -440 2120 m -430 2120 l -S -440 2140 m -430 2140 l -S -440 2160 m -430 2160 l -S -440 2180 m -430 2180 l -S -440 2200 m -430 2200 l -S -440 2220 m -430 2220 l -S -440 2240 m -430 2240 l -S -440 2260 m -430 2260 l -S -440 2280 m -430 2280 l -S -440 2300 m -430 2300 l -S -440 2320 m -430 2320 l -S -440 2340 m -430 2340 l -S -440 2360 m -430 2360 l -S -440 2380 m -430 2380 l -S -440 2400 m -430 2400 l -S -440 2420 m -430 2420 l -S -440 2440 m -430 2440 l -S -440 2460 m -430 2460 l -S -440 2480 m -430 2480 l -S -440 2500 m -430 2500 l -S -440 2520 m -430 2520 l -S -440 2540 m -430 2540 l -S -440 2560 m -430 2560 l -S -440 2580 m -430 2580 l -S -440 2600 m -430 2600 l -S -440 2620 m -430 2620 l -S -440 2640 m -430 2640 l -S -440 2660 m -430 2660 l -S -440 2680 m -430 2680 l -S -440 2700 m -430 2700 l -S -440 2720 m -430 2720 l -S -440 2740 m -430 2740 l -S -440 2760 m -430 2760 l -S -440 2780 m -430 2780 l -S -440 2800 m -430 2800 l -S -440 2820 m -430 2820 l -S -440 2840 m -430 2840 l -S -440 2860 m -430 2860 l -S -440 2880 m -430 2880 l -S -440 2900 m -430 2900 l -S -440 2920 m -430 2920 l -S -440 2940 m -430 2940 l -S -440 2960 m -430 2960 l -S -440 2980 m -430 2980 l -S -440 3000 m -430 3000 l -S -440 3020 m -430 3020 l -S -440 3040 m -430 3040 l -S -440 3060 m -430 3060 l -S -440 3080 m -430 3080 l -S -440 3100 m -430 3100 l -S -440 3120 m -430 3120 l -S -440 3140 m -430 3140 l -S -440 3160 m -430 3160 l -S -440 3180 m -430 3180 l -S -440 3200 m -430 3200 l -S -440 3220 m -430 3220 l -S -440 3240 m -430 3240 l -S -440 3260 m -430 3260 l -S -440 3280 m -430 3280 l -S -440 3300 m -430 3300 l -S -440 3320 m -430 3320 l -S -440 3340 m -430 3340 l -S -440 3360 m -430 3360 l -S -440 3380 m -430 3380 l -S -440 3400 m -430 3400 l -S -440 3420 m -430 3420 l -S -440 3440 m -430 3440 l -S -440 3460 m -430 3460 l -S -440 3480 m -430 3480 l -S -440 3500 m -430 3500 l -S -440 3520 m -430 3520 l -S -440 3540 m -430 3540 l -S -440 3560 m -430 3560 l -S -440 3580 m -430 3580 l -S -440 3600 m -430 3600 l -S -440 3620 m -430 3620 l -S -440 3640 m -430 3640 l -S -440 3660 m -430 3660 l -S -440 3680 m -430 3680 l -S -440 3700 m -430 3700 l -S -440 3720 m -430 3720 l -S -440 3740 m -430 3740 l -S -440 3760 m -430 3760 l -S -440 3780 m -430 3780 l -S -440 3800 m -430 3800 l -S -440 3820 m -430 3820 l -S -440 3840 m -430 3840 l -S -440 3860 m -430 3860 l -S -440 3880 m -430 3880 l -S -440 3900 m -430 3900 l -S -440 3920 m -430 3920 l -S -440 3940 m -430 3940 l -S -440 3960 m -430 3960 l -S -440 3980 m -430 3980 l -S -440 4000 m -430 4000 l -S -440 4020 m -430 4020 l -S -440 4040 m -430 4040 l -S -440 4060 m -430 4060 l -S -440 4080 m -430 4080 l -S -440 4100 m -430 4100 l -S -440 4120 m -430 4120 l -S -440 4140 m -430 4140 l -S -440 4160 m -430 4160 l -S -440 4180 m -430 4180 l -S -440 4200 m -430 4200 l -S -440 4220 m -430 4220 l -S -440 4240 m -430 4240 l -S -440 4260 m -430 4260 l -S -440 4280 m -430 4280 l -S -440 4300 m -430 4300 l -S -440 4320 m -430 4320 l -S -440 4340 m -430 4340 l -S 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-45.3431 177 44 178.343 44 180 c -44 181.657 45.3431 183 47 183 c -48.6569 183 50 181.657 50 180 c -S -40 180 m -44 180 l -S -100 160 m -90 160 l -S -q -0.000 0.000 0.000 rg -195 175 m -195 190 l -220 190 l -220 190 l -223 190 l -226 189 l -228 188 l -230 186 l -233 183 l -234 181 l -235 178 l -235 175 l -235 172 l -234 169 l -233 167 l -231 165 l -228 162 l -226 161 l -223 160 l -220 160 l -220 160 l -195 160 l -h f -Q -q -0.451 0.675 0.675 rg -190 170 m -190 185 l -215 185 l -215 185 l -218 185 l -221 184 l -223 183 l -225 181 l -228 178 l -229 176 l -230 173 l -230 170 l -230 167 l -229 164 l -228 162 l -226 160 l -223 157 l -221 156 l -218 155 l -215 155 l -215 155 l -190 155 l -h f -Q -0.176 0.176 0.176 RG -190 170 m -190 185 l -215 185 l -S -215 155 m -215 155 215 155 215 155 c -223.284 155 230 161.716 230 170 c -230 178.284 223.284 185 215 185 c -S -215 155 m -190 155 l -190 170 l -S -q -0.000 0.000 0.000 rg -1 0 0 1 192 154 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm -0 2.484 Td -([6].curr_bank_dram_fill_rsp_valid) Tj -ET -Q -0.024 0.278 0.435 RG -190 160 m -190 158.343 188.657 157 187 157 c -185.343 157 184 158.343 184 160 c -184 161.657 185.343 163 187 163 c -188.657 163 190 161.657 190 160 c -S -180 160 m -184 160 l -S -180 180 m -190 180 l -S -240 170 m -230 170 l -S -0.000 0.000 1.000 RG -424 177 m -431 170 l -424 163 l -S -410 170 m -431 170 l -S -q -0.000 0.000 1.000 rg -1 0 0 1 435 186 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm -0 -4.308 Td -([1,3]) Tj -ET -Q -q -0.176 0.176 0.176 rg -1 0 0 1 435 170 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm -0 -4.308 Td -([6].curr_bank_dram_fill_rsp_valid:OUT0) Tj -ET -Q -q -0.000 0.000 0.000 rg -233 225 m -233 222.791 231.209 221 229 221 c -226.791 221 225 222.791 225 225 c -225 227.209 226.791 229 229 229 c -231.209 229 233 227.209 233 225 c -f -Q -q -0.000 0.000 0.000 rg -195 225 m -195 213 l -225 225 l -195 237 l -h f -Q -q -0.451 0.675 0.675 rg -228 220 m -228 217.791 226.209 216 224 216 c -221.791 216 220 217.791 220 220 c -220 222.209 221.791 224 224 224 c -226.209 224 228 222.209 228 220 c -f -Q -q -0.451 0.675 0.675 rg -190 220 m -190 208 l -220 220 l -190 232 l -h f -Q -0.176 0.176 0.176 RG -228 220 m -228 217.791 226.209 216 224 216 c -221.791 216 220 217.791 220 220 c -220 222.209 221.791 224 224 224 c -226.209 224 228 222.209 228 220 c -S -190 220 m -190 208 l -220 220 l -190 232 l -h S -q -0.000 0.000 0.000 rg -1 0 0 1 192 206 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm -0 2.484 Td -(core_req_ready~not) Tj -ET -Q -0.024 0.278 0.435 RG -180 220 m -190 220 l -S -240 220 m -228 220 l -S -0.000 0.000 1.000 RG -0 220 m --14 220 l --21 227 l -S --14 220 m --21 213 l -S -q -0.000 0.000 1.000 rg -1 0 0 1 -25 236 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm --23.352 -4.308 Td -([1,3]) Tj -ET -Q -q -0.176 0.176 0.176 rg -1 0 0 1 -25 220 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm --102.708 -4.308 Td -(reduce_or_0:OUT0) Tj -ET -Q -410 220 m -410 213 l -424 213 l -431 220 l -424 227 l -410 227 l -h S -q -0.000 0.000 0.000 rg -1 0 0 1 439 220 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm -0 -4.308 Td -(core_req_ready) Tj -ET -Q -q -0.000 0.000 0.000 rg -55 250 m -57 252 l -59 255 l -60 257 l -61 260 l -62 263 l -62 267 l -61 270 l -60 273 l -59 275 l -57 278 l -55 280 l -55 280 l -70 280 l -70 280 l -73 280 l -76 279 l -79 278 l -81 277 l -84 276 l -87 274 l -89 272 l -91 270 l -93 268 l -95 265 l -95 265 l -93 262 l -91 260 l -89 258 l -87 256 l -84 254 l -81 253 l -79 252 l -76 251 l -73 250 l -70 250 l -70 250 l -h f -Q -q -0.451 0.675 0.675 rg -50 245 m -52 247 l -54 250 l -55 252 l -56 255 l -57 258 l -57 262 l -56 265 l -55 268 l -54 270 l -52 273 l -50 275 l -50 275 l -65 275 l -65 275 l -68 275 l -71 274 l -74 273 l -76 272 l -79 271 l -82 269 l -84 267 l -86 265 l -88 263 l -90 260 l -90 260 l -88 257 l -86 255 l -84 253 l -82 251 l -79 249 l -76 248 l -74 247 l -71 246 l -68 245 l -65 245 l -65 245 l -h f -Q -0.176 0.176 0.176 RG -50 275 m -50.8791 274.263 51.6918 273.451 52.4286 272.571 c -59.3716 264.287 58.2843 251.943 50 245 c -S -50 275 m -65 275 l -S -90 260 m -84.4917 268.656 75.2296 274.213 65 275 c -S -65 245 m -75.2296 245.787 84.4917 251.344 90 260 c -S -65 245 m -50 245 l -S -50 245 m -50 236 l -S -50 275 m -50 284 l -S -q -0.000 0.000 0.000 rg -1 0 0 1 52 244 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm -0 2.484 Td -(reduce_nor_10) Tj -ET -Q -0.024 0.278 0.435 RG -50 240 m -50 238.343 48.6569 237 47 237 c -45.3431 237 44 238.343 44 240 c -44 241.657 45.3431 243 47 243 c -48.6569 243 50 241.657 50 240 c -S -40 240 m -44 240 l -S -40 260 m -57 260 l -S -50 280 m -50 278.343 48.6569 277 47 277 c -45.3431 277 44 278.343 44 280 c -44 281.657 45.3431 283 47 283 c -48.6569 283 50 281.657 50 280 c -S -40 280 m -44 280 l -S -100 260 m -90 260 l -S -q -0.000 0.000 0.000 rg -195 275 m -195 290 l -220 290 l -220 290 l -223 290 l -226 289 l -228 288 l -230 286 l -233 283 l -234 281 l -235 278 l -235 275 l -235 272 l -234 269 l -233 267 l -231 265 l -228 262 l -226 261 l -223 260 l -220 260 l -220 260 l -195 260 l -h f -Q -q -0.451 0.675 0.675 rg -190 270 m -190 285 l -215 285 l -215 285 l -218 285 l -221 284 l -223 283 l -225 281 l -228 278 l -229 276 l -230 273 l -230 270 l -230 267 l -229 264 l -228 262 l -226 260 l -223 257 l -221 256 l -218 255 l -215 255 l -215 255 l -190 255 l -h f -Q -0.176 0.176 0.176 RG -190 270 m -190 285 l -215 285 l -S -215 255 m -215 255 215 255 215 255 c -223.284 255 230 261.716 230 270 c -230 278.284 223.284 285 215 285 c -S -215 255 m -190 255 l -190 270 l -S -q -0.000 0.000 0.000 rg -1 0 0 1 192 254 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm -0 2.484 Td -([5].curr_bank_dram_fill_rsp_valid) Tj -ET -Q -0.024 0.278 0.435 RG -190 260 m -190 258.343 188.657 257 187 257 c -185.343 257 184 258.343 184 260 c -184 261.657 185.343 263 187 263 c -188.657 263 190 261.657 190 260 c -S -180 260 m -184 260 l -S -180 280 m -190 280 l -S -240 270 m -230 270 l -S -0.000 0.000 1.000 RG -424 277 m -431 270 l -424 263 l -S -410 270 m -431 270 l -S -q -0.000 0.000 1.000 rg -1 0 0 1 435 286 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm -0 -4.308 Td -([1,3]) Tj -ET -Q -q -0.176 0.176 0.176 rg -1 0 0 1 435 270 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm -0 -4.308 Td -([5].curr_bank_dram_fill_rsp_valid:OUT0) Tj -ET -Q -q -0.000 0.000 0.000 rg -55 310 m -57 312 l -59 315 l -60 317 l -61 320 l -62 323 l -62 327 l -61 330 l -60 333 l -59 335 l -57 338 l -55 340 l -55 340 l -70 340 l -70 340 l -73 340 l -76 339 l -79 338 l -81 337 l -84 336 l -87 334 l -89 332 l -91 330 l -93 328 l -95 325 l -95 325 l -93 322 l -91 320 l -89 318 l -87 316 l -84 314 l -81 313 l -79 312 l -76 311 l -73 310 l -70 310 l -70 310 l -h f -Q -q -0.451 0.675 0.675 rg -50 305 m -52 307 l -54 310 l -55 312 l -56 315 l -57 318 l -57 322 l -56 325 l -55 328 l -54 330 l -52 333 l -50 335 l -50 335 l -65 335 l -65 335 l -68 335 l -71 334 l -74 333 l -76 332 l -79 331 l -82 329 l -84 327 l -86 325 l -88 323 l -90 320 l -90 320 l -88 317 l -86 315 l -84 313 l -82 311 l -79 309 l -76 308 l -74 307 l -71 306 l -68 305 l -65 305 l -65 305 l -h f -Q -0.176 0.176 0.176 RG -50 335 m -50.8791 334.263 51.6918 333.451 52.4286 332.571 c -59.3716 324.287 58.2843 311.943 50 305 c -S -50 335 m -65 335 l -S -90 320 m -84.4917 328.656 75.2296 334.213 65 335 c -S -65 305 m -75.2296 305.787 84.4917 311.344 90 320 c -S -65 305 m -50 305 l -S -50 305 m -50 296 l -S -50 335 m -50 344 l -S -q -0.000 0.000 0.000 rg -1 0 0 1 52 304 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm -0 2.484 Td -(reduce_nor_14) Tj -ET -Q -0.024 0.278 0.435 RG -50 300 m -50 298.343 48.6569 297 47 297 c -45.3431 297 44 298.343 44 300 c -44 301.657 45.3431 303 47 303 c -48.6569 303 50 301.657 50 300 c -S -40 300 m -44 300 l -S -57 320 m -57 318.343 55.6569 317 54 317 c -52.3431 317 51 318.343 51 320 c -51 321.657 52.3431 323 54 323 c -55.6569 323 57 321.657 57 320 c -S -40 320 m -51 320 l -S -50 340 m -50 338.343 48.6569 337 47 337 c -45.3431 337 44 338.343 44 340 c -44 341.657 45.3431 343 47 343 c -48.6569 343 50 341.657 50 340 c -S -40 340 m -44 340 l -S -100 320 m -90 320 l -S -q -0.000 0.000 0.000 rg -195 335 m -195 350 l -220 350 l -220 350 l -223 350 l -226 349 l -228 348 l -230 346 l -233 343 l -234 341 l -235 338 l -235 335 l -235 332 l -234 329 l -233 327 l -231 325 l -228 322 l -226 321 l -223 320 l -220 320 l -220 320 l -195 320 l -h f -Q -q -0.451 0.675 0.675 rg -190 330 m -190 345 l -215 345 l -215 345 l -218 345 l -221 344 l -223 343 l -225 341 l -228 338 l -229 336 l -230 333 l -230 330 l -230 327 l -229 324 l -228 322 l -226 320 l -223 317 l -221 316 l -218 315 l -215 315 l -215 315 l -190 315 l -h f -Q -0.176 0.176 0.176 RG -190 330 m -190 345 l -215 345 l -S -215 315 m -215 315 215 315 215 315 c -223.284 315 230 321.716 230 330 c -230 338.284 223.284 345 215 345 c -S -215 315 m -190 315 l -190 330 l -S -q -0.000 0.000 0.000 rg -1 0 0 1 192 314 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm -0 2.484 Td -([7].curr_bank_dram_fill_rsp_valid) Tj -ET -Q -0.024 0.278 0.435 RG -190 320 m -190 318.343 188.657 317 187 317 c -185.343 317 184 318.343 184 320 c -184 321.657 185.343 323 187 323 c -188.657 323 190 321.657 190 320 c -S -180 320 m -184 320 l -S -180 340 m -190 340 l -S -240 330 m -230 330 l -S -0.000 0.000 1.000 RG -424 337 m -431 330 l -424 323 l -S -410 330 m -431 330 l -S -q -0.000 0.000 1.000 rg -1 0 0 1 435 346 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm -0 -4.308 Td -([1,3]) Tj -ET -Q -q -0.176 0.176 0.176 rg -1 0 0 1 435 330 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm -0 -4.308 Td -([7].curr_bank_dram_fill_rsp_valid:OUT0) Tj -ET -Q -q -0.000 0.000 0.000 rg -55 370 m -57 372 l -59 375 l -60 377 l -61 380 l -62 383 l -62 387 l -61 390 l -60 393 l -59 395 l -57 398 l -55 400 l -55 400 l -70 400 l -70 400 l -73 400 l -76 399 l -79 398 l -81 397 l -84 396 l -87 394 l -89 392 l -91 390 l -93 388 l -95 385 l -95 385 l -93 382 l -91 380 l -89 378 l -87 376 l -84 374 l -81 373 l -79 372 l -76 371 l -73 370 l -70 370 l -70 370 l -h f -Q -q -0.451 0.675 0.675 rg -50 365 m -52 367 l -54 370 l -55 372 l -56 375 l -57 378 l -57 382 l -56 385 l -55 388 l -54 390 l -52 393 l -50 395 l -50 395 l -65 395 l -65 395 l -68 395 l -71 394 l -74 393 l -76 392 l -79 391 l -82 389 l -84 387 l -86 385 l -88 383 l -90 380 l -90 380 l -88 377 l -86 375 l -84 373 l -82 371 l -79 369 l -76 368 l -74 367 l -71 366 l -68 365 l -65 365 l -65 365 l -h f -Q -0.176 0.176 0.176 RG -50 395 m -50.8791 394.263 51.6918 393.451 52.4286 392.571 c -59.3716 384.287 58.2843 371.943 50 365 c -S -50 395 m -65 395 l -S -90 380 m -84.4917 388.656 75.2296 394.213 65 395 c -S -65 365 m -75.2296 365.787 84.4917 371.344 90 380 c -S -65 365 m -50 365 l -S -50 365 m -50 356 l -S -50 395 m -50 404 l -S -q -0.000 0.000 0.000 rg -1 0 0 1 52 364 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm -0 2.484 Td -(reduce_nor_4) Tj -ET -Q -0.024 0.278 0.435 RG -40 360 m -50 360 l -S -57 380 m -57 378.343 55.6569 377 54 377 c -52.3431 377 51 378.343 51 380 c -51 381.657 52.3431 383 54 383 c -55.6569 383 57 381.657 57 380 c -S -40 380 m -51 380 l -S -40 400 m -50 400 l -S -100 380 m -90 380 l -S -q -0.000 0.000 0.000 rg -195 395 m -195 410 l -220 410 l -220 410 l -223 410 l -226 409 l -228 408 l -230 406 l -233 403 l -234 401 l -235 398 l -235 395 l -235 392 l -234 389 l -233 387 l -231 385 l -228 382 l -226 381 l -223 380 l -220 380 l -220 380 l -195 380 l -h f -Q -q -0.451 0.675 0.675 rg -190 390 m -190 405 l -215 405 l -215 405 l -218 405 l -221 404 l -223 403 l -225 401 l -228 398 l -229 396 l -230 393 l -230 390 l -230 387 l -229 384 l -228 382 l -226 380 l -223 377 l -221 376 l -218 375 l -215 375 l -215 375 l -190 375 l -h f -Q -0.176 0.176 0.176 RG -190 390 m -190 405 l -215 405 l -S -215 375 m -215 375 215 375 215 375 c -223.284 375 230 381.716 230 390 c -230 398.284 223.284 405 215 405 c -S -215 375 m -190 375 l -190 390 l -S -q -0.000 0.000 0.000 rg -1 0 0 1 192 374 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm -0 2.484 Td -([2].curr_bank_dram_fill_rsp_valid) Tj -ET -Q -0.024 0.278 0.435 RG -190 380 m -190 378.343 188.657 377 187 377 c -185.343 377 184 378.343 184 380 c -184 381.657 185.343 383 187 383 c -188.657 383 190 381.657 190 380 c -S -180 380 m -184 380 l -S -180 400 m -190 400 l -S -240 390 m -230 390 l -S -0.000 0.000 1.000 RG -424 397 m -431 390 l -424 383 l -S -410 390 m -431 390 l -S -q -0.000 0.000 1.000 rg -1 0 0 1 435 406 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm -0 -4.308 Td -([1,3]) Tj -ET -Q -q -0.176 0.176 0.176 rg -1 0 0 1 435 390 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm -0 -4.308 Td -([2].curr_bank_dram_fill_rsp_valid:OUT0) Tj -ET -Q -q -0.000 0.000 0.000 rg -55 430 m -57 432 l -59 435 l -60 437 l -61 440 l -62 443 l -62 447 l -61 450 l -60 453 l -59 455 l -57 458 l -55 460 l -55 460 l -70 460 l -70 460 l -73 460 l -76 459 l -79 458 l -81 457 l -84 456 l -87 454 l -89 452 l -91 450 l -93 448 l -95 445 l -95 445 l -93 442 l -91 440 l -89 438 l -87 436 l -84 434 l -81 433 l -79 432 l -76 431 l -73 430 l -70 430 l -70 430 l -h f -Q -q -0.451 0.675 0.675 rg -50 425 m -52 427 l -54 430 l -55 432 l -56 435 l -57 438 l -57 442 l -56 445 l -55 448 l -54 450 l -52 453 l -50 455 l -50 455 l -65 455 l -65 455 l -68 455 l -71 454 l -74 453 l -76 452 l -79 451 l -82 449 l -84 447 l -86 445 l -88 443 l -90 440 l -90 440 l -88 437 l -86 435 l -84 433 l -82 431 l -79 429 l -76 428 l -74 427 l -71 426 l -68 425 l -65 425 l -65 425 l -h f -Q -0.176 0.176 0.176 RG -50 455 m -50.8791 454.263 51.6918 453.451 52.4286 452.571 c -59.3716 444.287 58.2843 431.943 50 425 c -S -50 455 m -65 455 l -S -90 440 m -84.4917 448.656 75.2296 454.213 65 455 c -S -65 425 m -75.2296 425.787 84.4917 431.344 90 440 c -S -65 425 m -50 425 l -S -50 425 m -50 416 l -S -50 455 m -50 464 l -S -q -0.000 0.000 0.000 rg -1 0 0 1 52 424 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm -0 2.484 Td -(reduce_nor_6) Tj -ET -Q -0.024 0.278 0.435 RG -50 420 m -50 418.343 48.6569 417 47 417 c -45.3431 417 44 418.343 44 420 c -44 421.657 45.3431 423 47 423 c -48.6569 423 50 421.657 50 420 c -S -40 420 m -44 420 l -S -57 440 m -57 438.343 55.6569 437 54 437 c -52.3431 437 51 438.343 51 440 c -51 441.657 52.3431 443 54 443 c -55.6569 443 57 441.657 57 440 c -S -40 440 m -51 440 l -S -40 460 m -50 460 l -S -100 440 m -90 440 l -S -q -0.000 0.000 0.000 rg -195 455 m -195 470 l -220 470 l -220 470 l -223 470 l -226 469 l -228 468 l -230 466 l -233 463 l -234 461 l -235 458 l -235 455 l -235 452 l -234 449 l -233 447 l -231 445 l -228 442 l -226 441 l -223 440 l -220 440 l -220 440 l -195 440 l -h f -Q -q -0.451 0.675 0.675 rg -190 450 m -190 465 l -215 465 l -215 465 l -218 465 l -221 464 l -223 463 l -225 461 l -228 458 l -229 456 l -230 453 l -230 450 l -230 447 l -229 444 l -228 442 l -226 440 l -223 437 l -221 436 l -218 435 l -215 435 l -215 435 l -190 435 l -h f -Q -0.176 0.176 0.176 RG -190 450 m -190 465 l -215 465 l -S -215 435 m -215 435 215 435 215 435 c -223.284 435 230 441.716 230 450 c -230 458.284 223.284 465 215 465 c -S -215 435 m -190 435 l -190 450 l -S -q -0.000 0.000 0.000 rg -1 0 0 1 192 434 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm -0 2.484 Td -([3].curr_bank_dram_fill_rsp_valid) Tj -ET -Q -0.024 0.278 0.435 RG -190 440 m -190 438.343 188.657 437 187 437 c -185.343 437 184 438.343 184 440 c -184 441.657 185.343 443 187 443 c -188.657 443 190 441.657 190 440 c -S -180 440 m -184 440 l -S -180 460 m -190 460 l -S -240 450 m -230 450 l -S -3 w -0.000 0.000 1.000 RG -0 560 m --7 567 l --21 567 l --21 553 l --7 553 l -h S -q -0.000 0.000 0.000 rg -1 0 0 1 -25 560 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm --114.72 -4.308 Td -(dram_rsp_addr[31..0]) Tj -ET -Q -1 w -424 457 m -431 450 l -424 443 l -S -410 450 m -431 450 l -S -q -0.000 0.000 1.000 rg -1 0 0 1 435 466 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm -0 -4.308 Td -([1,3]) Tj -ET -Q -q -0.176 0.176 0.176 rg -1 0 0 1 435 450 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm -0 -4.308 Td -([3].curr_bank_dram_fill_rsp_valid:OUT0) Tj -ET -Q -q -0.000 0.000 0.000 rg -55 490 m -57 492 l -59 495 l -60 497 l -61 500 l -62 503 l -62 507 l -61 510 l -60 513 l -59 515 l -57 518 l -55 520 l -55 520 l -70 520 l -70 520 l -73 520 l -76 519 l -79 518 l -81 517 l -84 516 l -87 514 l -89 512 l -91 510 l -93 508 l -95 505 l -95 505 l -93 502 l -91 500 l -89 498 l -87 496 l -84 494 l -81 493 l -79 492 l -76 491 l -73 490 l -70 490 l -70 490 l -h f -Q -q -0.451 0.675 0.675 rg -50 485 m -52 487 l -54 490 l -55 492 l -56 495 l -57 498 l -57 502 l -56 505 l -55 508 l -54 510 l -52 513 l -50 515 l -50 515 l -65 515 l -65 515 l -68 515 l -71 514 l -74 513 l -76 512 l -79 511 l -82 509 l -84 507 l -86 505 l -88 503 l -90 500 l -90 500 l -88 497 l -86 495 l -84 493 l -82 491 l -79 489 l -76 488 l -74 487 l -71 486 l -68 485 l -65 485 l -65 485 l -h f -Q -0.176 0.176 0.176 RG -50 515 m -50.8791 514.263 51.6918 513.451 52.4286 512.571 c -59.3716 504.287 58.2843 491.943 50 485 c -S -50 515 m -65 515 l -S -90 500 m -84.4917 508.656 75.2296 514.213 65 515 c -S -65 485 m -75.2296 485.787 84.4917 491.344 90 500 c -S -65 485 m -50 485 l -S -50 485 m -50 476 l -S -50 515 m -50 524 l -S -q -0.000 0.000 0.000 rg -1 0 0 1 52 484 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm -0 2.484 Td -(reduce_nor_8) Tj -ET -Q -0.024 0.278 0.435 RG -40 480 m -50 480 l -S -40 500 m -57 500 l -S -50 520 m -50 518.343 48.6569 517 47 517 c -45.3431 517 44 518.343 44 520 c -44 521.657 45.3431 523 47 523 c -48.6569 523 50 521.657 50 520 c -S -40 520 m -44 520 l -S -100 500 m -90 500 l -S -q -0.000 0.000 0.000 rg -195 515 m -195 530 l -220 530 l -220 530 l -223 530 l -226 529 l -228 528 l -230 526 l -233 523 l -234 521 l -235 518 l -235 515 l -235 512 l -234 509 l -233 507 l -231 505 l -228 502 l -226 501 l -223 500 l -220 500 l -220 500 l -195 500 l -h f -Q -q -0.451 0.675 0.675 rg -190 510 m -190 525 l -215 525 l -215 525 l -218 525 l -221 524 l -223 523 l -225 521 l -228 518 l -229 516 l -230 513 l -230 510 l -230 507 l -229 504 l -228 502 l -226 500 l -223 497 l -221 496 l -218 495 l -215 495 l -215 495 l -190 495 l -h f -Q -0.176 0.176 0.176 RG -190 510 m -190 525 l -215 525 l -S -215 495 m -215 495 215 495 215 495 c -223.284 495 230 501.716 230 510 c -230 518.284 223.284 525 215 525 c -S -215 495 m -190 495 l -190 510 l -S -q -0.000 0.000 0.000 rg -1 0 0 1 192 494 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm -0 2.484 Td -([4].curr_bank_dram_fill_rsp_valid) Tj -ET -Q -0.024 0.278 0.435 RG -190 500 m -190 498.343 188.657 497 187 497 c -185.343 497 184 498.343 184 500 c -184 501.657 185.343 503 187 503 c -188.657 503 190 501.657 190 500 c -S -180 500 m -184 500 l -S -180 520 m -190 520 l -S -240 510 m -230 510 l -S -0.000 0.000 1.000 RG -424 517 m -431 510 l -424 503 l -S -410 510 m -431 510 l -S -q -0.000 0.000 1.000 rg -1 0 0 1 435 526 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm -0 -4.308 Td -([1,3]) Tj -ET -Q -q -0.176 0.176 0.176 rg -1 0 0 1 435 510 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm -0 -4.308 Td -([4].curr_bank_dram_fill_rsp_valid:OUT0) Tj -ET -Q -0 540 m --7 547 l --21 547 l --21 533 l --7 533 l -h S -q -0.000 0.000 0.000 rg -1 0 0 1 -25 540 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm --82.02 -4.308 Td -(dram_rsp_valid) Tj -ET -Q -3 w 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l -84 593 l -82 591 l -79 589 l -76 588 l -74 587 l -71 586 l -68 585 l -65 585 l -65 585 l -h f -Q -1 w -0.176 0.176 0.176 RG -50 615 m -50.8791 614.263 51.6918 613.451 52.4286 612.571 c -59.3716 604.287 58.2843 591.943 50 585 c -S -50 615 m -65 615 l -S -90 600 m -84.4917 608.656 75.2296 614.213 65 615 c -S -65 585 m -75.2296 585.787 84.4917 591.344 90 600 c -S -65 585 m -50 585 l -S -50 585 m -50 576 l -S -50 615 m -50 624 l -S -q -0.000 0.000 0.000 rg -1 0 0 1 52 584 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm -0 2.484 Td -(reduce_nor_1) Tj -ET -Q -0.024 0.278 0.435 RG -40 580 m -50 580 l -S -40 600 m -57 600 l -S -40 620 m -50 620 l -S -100 600 m -90 600 l -S -q -0.000 0.000 0.000 rg -195 615 m -195 630 l -220 630 l -220 630 l -223 630 l -226 629 l -228 628 l -230 626 l -233 623 l -234 621 l -235 618 l -235 615 l -235 612 l -234 609 l -233 607 l -231 605 l -228 602 l -226 601 l -223 600 l -220 600 l -220 600 l -195 600 l -h f -Q -q -0.451 0.675 0.675 rg -190 610 m -190 625 l -215 625 l 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420 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 3198 419 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --121.73 2.07 Td -(bckE_req_if.PC_next[31..0]) Tj -ET -Q -3190 800 m -3200 800 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 3198 799 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --86.71 2.07 Td -(bckE_req_if.rd[4..0]) Tj -ET -Q -3190 820 m -3200 820 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 3198 819 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --91.71 2.07 Td -(bckE_req_if.rs1[4..0]) Tj -ET -Q -3190 840 m -3200 840 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 3198 839 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --91.71 2.07 Td -(bckE_req_if.rs2[4..0]) Tj -ET -Q -3190 880 m -3200 880 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 3198 879 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --144.51 2.07 Td -(bckE_req_if.upper_immed[19..0]) Tj -ET -Q -3190 900 m -3200 900 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 3198 899 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --98.38 2.07 Td -(bckE_req_if.valid[3..0]) Tj -ET -Q -3190 920 m -3200 920 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 3198 919 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --124.5 2.07 Td -(bckE_req_if.warp_num[2..0]) Tj -ET -Q -3190 940 m -3200 940 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 3198 939 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --90.6 2.07 Td -(bckE_req_if.wb[1..0]) Tj -ET -Q -3190 1000 m -3200 1000 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 3198 999 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --167.87 2.07 Td -(dcache_rsp_if.core_rsp_data[0][31..0]) Tj -ET -Q -3190 1020 m -3200 1020 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 3198 1019 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --167.87 2.07 Td -(dcache_rsp_if.core_rsp_data[1][31..0]) Tj -ET -Q -3190 1040 m -3200 1040 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 3198 1039 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --167.87 2.07 Td -(dcache_rsp_if.core_rsp_data[2][31..0]) Tj -ET -Q -3190 1060 m -3200 1060 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 3198 1059 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --167.87 2.07 Td -(dcache_rsp_if.core_rsp_data[3][31..0]) Tj -ET -Q -3190 1080 m -3200 1080 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 3198 1079 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --158.97 2.07 Td -(dcache_rsp_if.core_rsp_pc[0][31..0]) Tj -ET -Q -3190 1100 m -3200 1100 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 3198 1099 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --158.97 2.07 Td -(dcache_rsp_if.core_rsp_pc[1][31..0]) Tj -ET -Q -3190 1120 m -3200 1120 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 3198 1119 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --158.97 2.07 Td -(dcache_rsp_if.core_rsp_pc[2][31..0]) Tj -ET -Q -3190 1140 m -3200 1140 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 3198 1139 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --158.97 2.07 Td -(dcache_rsp_if.core_rsp_pc[3][31..0]) Tj -ET -Q -3190 1160 m -3200 1160 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 3198 1159 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --151.74 2.07 Td -(dcache_rsp_if.core_rsp_read[4..0]) Tj -ET -Q -3190 1180 m -3200 1180 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 3198 1179 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --152.29 2.07 Td -(dcache_rsp_if.core_rsp_valid[3..0]) Tj -ET -Q -3190 1200 m -3200 1200 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 3198 1199 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --178.41 2.07 Td -(dcache_rsp_if.core_rsp_warp_num[2..0]) Tj -ET -Q -3190 1220 m -3200 1220 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 3198 1219 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --152.84 2.07 Td -(dcache_rsp_if.core_rsp_write[1..0]) Tj -ET -Q -1 w -3270 820 m -3260 820 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 3266 819 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(dcache_rsp_if.core_rsp_ready) Tj -ET -Q -3270 940 m -3260 940 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 3266 939 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(mem_delay) Tj -ET -Q -3270 840 m -3260 840 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 3266 839 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(exec_delay) Tj -ET -Q -3270 860 m -3260 860 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 3266 859 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(gpr_stage_delay) Tj -ET -Q -3270 920 m -3260 920 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 3266 919 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(jal_rsp_if.jal) Tj -ET -Q -3270 320 m -3260 320 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 3266 319 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(branch_rsp_if.valid_branch) Tj -ET -Q -3270 280 m -3260 280 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 3266 279 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(branch_rsp_if.branch_dir) Tj -ET -Q -3270 980 m -3260 980 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 3266 979 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(warp_ctl_if.change_mask) Tj -ET -Q -3270 1260 m -3260 1260 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 3266 1259 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(warp_ctl_if.wspawn) Tj -ET -Q -3270 1020 m -3260 1020 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 3266 1019 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(warp_ctl_if.ebreak) Tj -ET -Q -3270 1040 m -3260 1040 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 3266 1039 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(warp_ctl_if.is_barrier) Tj -ET -Q -3270 1060 m -3260 1060 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 3266 1059 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(warp_ctl_if.is_split) Tj -ET -Q -3270 1000 m -3260 1000 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 3266 999 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(warp_ctl_if.dont_split) Tj -ET -Q -3 w -3270 260 m -3260 260 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 3266 259 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(branch_rsp_if.branch_dest[31..0]) Tj -ET -Q -3270 300 m -3260 300 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 3266 299 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(branch_rsp_if.branch_warp_num[2..0]) Tj -ET -Q -3270 340 m -3260 340 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 3266 339 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(dcache_req_if.core_req_addr[0][31..0]) Tj -ET -Q -3270 360 m -3260 360 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 3266 359 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(dcache_req_if.core_req_addr[1][31..0]) Tj -ET -Q -3270 380 m -3260 380 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 3266 379 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(dcache_req_if.core_req_addr[2][31..0]) Tj -ET -Q -3270 400 m -3260 400 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 3266 399 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(dcache_req_if.core_req_addr[3][31..0]) Tj -ET -Q -3270 420 m -3260 420 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 3266 419 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(dcache_req_if.core_req_data[0][31..0]) Tj -ET -Q -3270 440 m -3260 440 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 3266 439 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(dcache_req_if.core_req_data[1][31..0]) Tj -ET -Q -3270 460 m -3260 460 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 3266 459 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(dcache_req_if.core_req_data[2][31..0]) Tj -ET -Q -3270 480 m -3260 480 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 3266 479 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(dcache_req_if.core_req_data[3][31..0]) Tj -ET -Q -3270 500 m -3260 500 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 3266 499 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(dcache_req_if.core_req_pc[31..0]) Tj -ET -Q -3270 520 m -3260 520 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 3266 519 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(dcache_req_if.core_req_rd[4..0]) Tj -ET -Q -3270 540 m -3260 540 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 3266 539 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(dcache_req_if.core_req_read[0][2..0]) Tj -ET -Q -3270 560 m -3260 560 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 3266 559 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(dcache_req_if.core_req_read[1][2..0]) Tj -ET -Q -3270 580 m -3260 580 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 3266 579 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(dcache_req_if.core_req_read[2][2..0]) Tj -ET -Q -3270 600 m -3260 600 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 3266 599 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(dcache_req_if.core_req_read[3][2..0]) Tj -ET -Q -3270 620 m -3260 620 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 3266 619 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(dcache_req_if.core_req_valid[3..0]) Tj -ET -Q -3270 640 m -3260 640 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 3266 639 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(dcache_req_if.core_req_warp_num[2..0]) Tj -ET -Q -3270 660 m -3260 660 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 3266 659 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(dcache_req_if.core_req_wb[0][1..0]) Tj -ET -Q -3270 680 m -3260 680 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 3266 679 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(dcache_req_if.core_req_wb[1][1..0]) Tj -ET -Q -3270 700 m -3260 700 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 3266 699 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(dcache_req_if.core_req_wb[2][1..0]) Tj -ET -Q -3270 720 m -3260 720 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 3266 719 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(dcache_req_if.core_req_wb[3][1..0]) Tj -ET -Q -3270 740 m -3260 740 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 3266 739 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(dcache_req_if.core_req_write[0][2..0]) Tj -ET -Q -3270 760 m -3260 760 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 3266 759 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(dcache_req_if.core_req_write[1][2..0]) Tj -ET -Q -3270 780 m -3260 780 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 3266 779 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(dcache_req_if.core_req_write[2][2..0]) Tj -ET -Q -3270 800 m -3260 800 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 3266 799 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(dcache_req_if.core_req_write[3][2..0]) Tj -ET -Q -3270 880 m -3260 880 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 3266 879 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(jal_rsp_if.jal_dest[31..0]) Tj -ET -Q -3270 900 m -3260 900 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 3266 899 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(jal_rsp_if.jal_warp_num[2..0]) Tj -ET -Q -3270 960 m -3260 960 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 3266 959 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(warp_ctl_if.barrier_id[31..0]) Tj -ET -Q -3270 1080 m -3260 1080 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 3266 1079 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(warp_ctl_if.num_warps[3..0]) Tj -ET -Q -3270 1100 m -3260 1100 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 3266 1099 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(warp_ctl_if.split_later_mask[3..0]) Tj -ET -Q -3270 1120 m -3260 1120 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 3266 1119 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(warp_ctl_if.split_new_mask[3..0]) Tj -ET -Q -3270 1140 m -3260 1140 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 3266 1139 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(warp_ctl_if.split_save_pc[31..0]) Tj -ET -Q -3270 1160 m -3260 1160 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 3266 1159 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(warp_ctl_if.split_warp_num[2..0]) Tj -ET -Q -3270 1180 m -3260 1180 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 3266 1179 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(warp_ctl_if.thread_mask[3..0]) Tj -ET -Q -3270 1200 m -3260 1200 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 3266 1199 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(warp_ctl_if.warp_num[2..0]) Tj -ET -Q -3270 1220 m -3260 1220 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 3266 1219 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(warp_ctl_if.wspawn_new_active[7..0]) Tj -ET -Q -3270 1240 m -3260 1240 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 3266 1239 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(warp_ctl_if.wspawn_pc[31..0]) Tj -ET -Q -3270 1280 m -3260 1280 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 3266 1279 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(writeback_if.rd[4..0]) Tj -ET -Q -3270 1300 m -3260 1300 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 3266 1299 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(writeback_if.wb[1..0]) Tj -ET -Q -3270 1320 m -3260 1320 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 3266 1319 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(writeback_if.wb_pc[31..0]) Tj -ET -Q -3270 1340 m -3260 1340 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 3266 1339 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(writeback_if.wb_valid[3..0]) Tj -ET -Q -3270 1360 m -3260 1360 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 3266 1359 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(writeback_if.wb_warp_num[2..0]) Tj -ET -Q -3270 1380 m -3260 1380 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 3266 1379 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(writeback_if.write_data[0][31..0]) Tj -ET -Q -3270 1400 m -3260 1400 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 3266 1399 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(writeback_if.write_data[1][31..0]) Tj -ET -Q -3270 1420 m -3260 1420 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 3266 1419 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(writeback_if.write_data[2][31..0]) Tj -ET -Q -3270 1440 m -3260 1440 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 3266 1439 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(writeback_if.write_data[3][31..0]) Tj -ET -Q -1 w -3210 960 m -3200 960 l -S -3210 1240 m -3200 1240 l -S -3210 1260 m -3200 1260 l -S -3210 980 m -3200 980 l -S -3210 600 m -3200 600 l -S -3210 500 m -3200 500 l -S -3210 860 m -3200 860 l -S -3210 560 m -3200 560 l -S -3210 700 m -3200 700 l -S -3210 740 m -3200 740 l -S -3210 660 m -3200 660 l -S -3210 640 m -3200 640 l -S -3210 620 m -3200 620 l -S -3210 580 m -3200 580 l -S -3 w -3210 440 m -3200 440 l -S -3210 460 m -3200 460 l -S -3210 480 m -3200 480 l -S -3210 520 m -3200 520 l -S -3210 540 m -3200 540 l -S -3210 680 m -3200 680 l -S -3210 720 m -3200 720 l -S -3210 760 m -3200 760 l -S -3210 780 m -3200 780 l -S -3210 420 m -3200 420 l -S -3210 800 m -3200 800 l -S -3210 820 m -3200 820 l -S -3210 840 m -3200 840 l -S -3210 880 m -3200 880 l -S -3210 900 m -3200 900 l -S -3210 920 m -3200 920 l -S -3210 940 m -3200 940 l -S -3210 1000 m -3200 1000 l -S -3210 1020 m -3200 1020 l -S -3210 1040 m -3200 1040 l -S -3210 1060 m -3200 1060 l -S -3210 1080 m -3200 1080 l -S -3210 1100 m -3200 1100 l -S -3210 1120 m -3200 1120 l -S -3210 1140 m -3200 1140 l -S -3210 1160 m -3200 1160 l -S -3210 1180 m -3200 1180 l -S -3210 1200 m -3200 1200 l -S -3210 1220 m -3200 1220 l -S -1 w -3250 820 m -3260 820 l -S -3250 940 m -3260 940 l -S -3250 840 m -3260 840 l -S -3250 860 m -3260 860 l -S -3250 920 m -3260 920 l -S -3250 320 m -3260 320 l -S -3250 280 m -3260 280 l -S -3250 980 m -3260 980 l -S -3250 1260 m -3260 1260 l -S -3250 1020 m -3260 1020 l -S -3250 1040 m -3260 1040 l -S -3250 1060 m -3260 1060 l -S -3250 1000 m -3260 1000 l -S -3 w -3250 260 m -3260 260 l -S -3250 300 m -3260 300 l -S -3250 340 m -3260 340 l -S -3250 360 m -3260 360 l -S -3250 380 m -3260 380 l -S -3250 400 m -3260 400 l -S -3250 420 m -3260 420 l -S -3250 440 m -3260 440 l -S -3250 460 m -3260 460 l -S -3250 480 m -3260 480 l -S -3250 500 m -3260 500 l -S -3250 520 m -3260 520 l -S -3250 540 m -3260 540 l -S -3250 560 m -3260 560 l -S -3250 580 m -3260 580 l -S -3250 600 m -3260 600 l -S -3250 620 m -3260 620 l -S -3250 640 m -3260 640 l -S -3250 660 m -3260 660 l -S -3250 680 m -3260 680 l -S -3250 700 m -3260 700 l -S -3250 720 m -3260 720 l -S -3250 740 m -3260 740 l -S -3250 760 m -3260 760 l -S -3250 780 m -3260 780 l -S -3250 800 m -3260 800 l -S -3250 880 m -3260 880 l -S -3250 900 m -3260 900 l -S -3250 960 m -3260 960 l -S -3250 1080 m -3260 1080 l -S -3250 1100 m -3260 1100 l -S -3250 1120 m -3260 1120 l -S -3250 1140 m -3260 1140 l -S -3250 1160 m -3260 1160 l -S -3250 1180 m -3260 1180 l -S -3250 1200 m -3260 1200 l -S -3250 1220 m -3260 1220 l -S -3250 1240 m -3260 1240 l -S -3250 1280 m -3260 1280 l -S -3250 1300 m -3260 1300 l -S -3250 1320 m -3260 1320 l -S -3250 1340 m -3260 1340 l -S -3250 1360 m -3260 1360 l -S -3250 1380 m -3260 1380 l -S -3250 1400 m -3260 1400 l -S -3250 1420 m -3260 1420 l -S -3250 1440 m -3260 1440 l -S -1 w -0.000 0.000 1.000 RG -0 1360 m --7 1367 l --21 1367 l --21 1353 l --7 1353 l -h S -q -0.000 0.000 0.000 rg -1 0 0 1 -25 1360 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm --14.664 -4.308 Td -(clk) Tj -ET -Q -q -0.000 0.000 0.000 rg -5165 653 60 1082 re -f -Q -q -0.506 0.749 0.373 rg -5160 648 60 1082 re -f -Q -0.176 0.176 0.176 RG -5160 648 60 1082 re -S -3 w -5171 653 m -5171 665 l -S -5165 659 m -5177 659 l -S -1 w -5163 651 16 16 re -S -q -0.000 0.000 0.000 rg -1 0 0 1 5190 646 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm --44.676 2.484 Td -(dmem_controller) Tj -ET -Q -0.024 0.278 0.435 RG -5150 680 m -5160 680 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 5158 679 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --12.22 2.07 Td -(clk) Tj -ET -Q -5150 1720 m -5160 1720 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 5158 1719 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --22.23 2.07 Td -(reset) Tj -ET -Q -5150 1200 m -5160 1200 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 5158 1199 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --189.53 2.07 Td -(gpu_dcache_dram_req_if.dram_req_ready) Tj -ET -Q -5150 1320 m -5160 1320 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 5158 1319 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --183.96 2.07 Td -(gpu_dcache_dram_res_if.dram_rsp_valid) Tj -ET -Q -5150 1360 m -5160 1360 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 5158 1359 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --171.76 2.07 Td -(gpu_dcache_snp_req_if.snp_req_valid) Tj -ET -Q -5150 1380 m -5160 1380 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 5158 1379 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --186.19 2.07 Td -(gpu_icache_dram_req_if.dram_req_ready) Tj -ET -Q -5150 1500 m -5160 1500 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 5158 1499 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --180.62 2.07 Td -(gpu_icache_dram_res_if.dram_rsp_valid) Tj -ET -Q -5150 1180 m -5160 1180 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 5158 1179 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --134.5 2.07 Td -(dcache_rsp_if.core_rsp_ready) Tj -ET -Q -5150 1700 m -5160 1700 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 5158 1699 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --131.16 2.07 Td -(icache_rsp_if.core_rsp_ready) Tj -ET -Q -5150 1620 m -5160 1620 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 5158 1619 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --138.95 2.07 Td -(icache_req_if.core_req_valid[0]) Tj -ET -Q -3 w -5150 700 m -5160 700 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 5158 699 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --169.54 2.07 Td -(dcache_req_if.core_req_addr[0][31..0]) Tj -ET -Q -5150 720 m -5160 720 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 5158 719 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --169.54 2.07 Td -(dcache_req_if.core_req_addr[1][31..0]) Tj -ET -Q -5150 740 m -5160 740 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 5158 739 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --169.54 2.07 Td -(dcache_req_if.core_req_addr[2][31..0]) Tj -ET -Q -5150 760 m -5160 760 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 5158 759 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --169.54 2.07 Td -(dcache_req_if.core_req_addr[3][31..0]) Tj -ET -Q -5150 780 m -5160 780 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 5158 779 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --168.99 2.07 Td -(dcache_req_if.core_req_data[0][31..0]) Tj -ET -Q -5150 800 m -5160 800 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 5158 799 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --168.99 2.07 Td -(dcache_req_if.core_req_data[1][31..0]) Tj -ET -Q -5150 820 m -5160 820 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 5158 819 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --168.99 2.07 Td -(dcache_req_if.core_req_data[2][31..0]) Tj -ET -Q -5150 840 m -5160 840 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 5158 839 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --168.99 2.07 Td -(dcache_req_if.core_req_data[3][31..0]) Tj -ET -Q -5150 860 m -5160 860 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 5158 859 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --148.97 2.07 Td -(dcache_req_if.core_req_pc[31..0]) Tj -ET -Q -5150 880 m -5160 880 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 5158 879 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --141.74 2.07 Td -(dcache_req_if.core_req_rd[4..0]) Tj -ET -Q -5150 900 m -5160 900 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 5158 899 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --163.98 2.07 Td -(dcache_req_if.core_req_read[0][2..0]) Tj -ET -Q -5150 920 m -5160 920 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 5158 919 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --163.98 2.07 Td -(dcache_req_if.core_req_read[1][2..0]) Tj -ET -Q -5150 940 m -5160 940 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 5158 939 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --163.98 2.07 Td -(dcache_req_if.core_req_read[2][2..0]) Tj -ET -Q -5150 960 m -5160 960 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 5158 959 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --163.98 2.07 Td -(dcache_req_if.core_req_read[3][2..0]) Tj -ET -Q -5150 980 m -5160 980 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 5158 979 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --153.41 2.07 Td -(dcache_req_if.core_req_valid[3..0]) Tj -ET -Q -5150 1000 m -5160 1000 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 5158 999 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --179.53 2.07 Td -(dcache_req_if.core_req_warp_num[2..0]) Tj -ET -Q -5150 1020 m -5160 1020 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 5158 1019 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --156.75 2.07 Td -(dcache_req_if.core_req_wb[0][1..0]) Tj -ET -Q -5150 1040 m -5160 1040 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 5158 1039 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --156.75 2.07 Td -(dcache_req_if.core_req_wb[1][1..0]) Tj -ET -Q -5150 1060 m -5160 1060 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 5158 1059 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --156.75 2.07 Td -(dcache_req_if.core_req_wb[2][1..0]) Tj -ET -Q -5150 1080 m -5160 1080 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 5158 1079 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --156.75 2.07 Td -(dcache_req_if.core_req_wb[3][1..0]) Tj -ET -Q -5150 1100 m -5160 1100 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 5158 1099 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --165.08 2.07 Td -(dcache_req_if.core_req_write[0][2..0]) Tj -ET -Q -5150 1120 m -5160 1120 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 5158 1119 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --165.08 2.07 Td -(dcache_req_if.core_req_write[1][2..0]) Tj -ET -Q -5150 1140 m -5160 1140 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 5158 1139 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --165.08 2.07 Td -(dcache_req_if.core_req_write[2][2..0]) Tj -ET -Q -5150 1160 m -5160 1160 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 5158 1159 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --165.08 2.07 Td -(dcache_req_if.core_req_write[3][2..0]) Tj -ET -Q -5150 1220 m -5160 1220 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 5158 1219 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --211.21 2.07 Td -(gpu_dcache_dram_res_if.dram_rsp_addr[31..0]) Tj -ET -Q -5150 1240 m -5160 1240 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 5158 1239 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --221.78 2.07 Td -(gpu_dcache_dram_res_if.dram_rsp_data[0][31..0]) Tj -ET -Q -5150 1260 m -5160 1260 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 5158 1259 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --221.78 2.07 Td -(gpu_dcache_dram_res_if.dram_rsp_data[1][31..0]) Tj -ET -Q -5150 1280 m -5160 1280 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 5158 1279 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --221.78 2.07 Td -(gpu_dcache_dram_res_if.dram_rsp_data[2][31..0]) Tj -ET -Q -5150 1300 m -5160 1300 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 5158 1299 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --221.78 2.07 Td -(gpu_dcache_dram_res_if.dram_rsp_data[3][31..0]) Tj -ET -Q -5150 1340 m -5160 1340 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 5158 1339 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --199.01 2.07 Td -(gpu_dcache_snp_req_if.snp_req_addr[31..0]) Tj -ET -Q -5150 1400 m -5160 1400 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 5158 1399 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --207.87 2.07 Td -(gpu_icache_dram_res_if.dram_rsp_addr[31..0]) Tj -ET -Q -5150 1420 m -5160 1420 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 5158 1419 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --218.44 2.07 Td -(gpu_icache_dram_res_if.dram_rsp_data[0][31..0]) Tj -ET -Q -5150 1440 m -5160 1440 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 5158 1439 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --218.44 2.07 Td -(gpu_icache_dram_res_if.dram_rsp_data[1][31..0]) Tj -ET -Q -5150 1460 m -5160 1460 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 5158 1459 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --218.44 2.07 Td -(gpu_icache_dram_res_if.dram_rsp_data[2][31..0]) Tj -ET -Q -5150 1480 m -5160 1480 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 5158 1479 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --218.44 2.07 Td -(gpu_icache_dram_res_if.dram_rsp_data[3][31..0]) Tj -ET -Q -5150 1520 m -5160 1520 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 5158 1519 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --166.2 2.07 Td -(icache_req_if.core_req_addr[0][31..0]) Tj -ET -Q -5150 1540 m -5160 1540 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 5158 1539 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --165.65 2.07 Td -(icache_req_if.core_req_data[0][31..0]) Tj -ET -Q -5150 1560 m -5160 1560 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 5158 1559 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --145.63 2.07 Td -(icache_req_if.core_req_pc[31..0]) Tj -ET -Q -5150 1580 m -5160 1580 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 5158 1579 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --138.4 2.07 Td -(icache_req_if.core_req_rd[4..0]) Tj -ET -Q -5150 1600 m -5160 1600 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 5158 1599 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --160.64 2.07 Td -(icache_req_if.core_req_read[0][2..0]) Tj -ET -Q -5150 1640 m -5160 1640 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 5158 1639 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --176.19 2.07 Td -(icache_req_if.core_req_warp_num[2..0]) Tj -ET -Q -5150 1660 m -5160 1660 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 5158 1659 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --153.41 2.07 Td -(icache_req_if.core_req_wb[0][1..0]) Tj -ET -Q -5150 1680 m -5160 1680 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 5158 1679 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --161.74 2.07 Td -(icache_req_if.core_req_write[0][2..0]) Tj -ET -Q -1 w -5230 1220 m -5220 1220 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 5226 1219 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(gpu_dcache_dram_req_if.dram_req_write) Tj -ET -Q -5230 1200 m -5220 1200 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 5226 1199 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(gpu_dcache_dram_req_if.dram_req_read) Tj -ET -Q -5230 1240 m -5220 1240 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 5226 1239 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(gpu_dcache_dram_req_if.dram_rsp_ready) Tj -ET -Q -5230 1260 m -5220 1260 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 5226 1259 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(gpu_dcache_snp_req_if.snp_req_ready) Tj -ET -Q -5230 1400 m -5220 1400 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 5226 1399 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(gpu_icache_dram_req_if.dram_req_write) Tj -ET -Q -5230 1380 m -5220 1380 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 5226 1379 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(gpu_icache_dram_req_if.dram_req_read) Tj -ET -Q -5230 1420 m -5220 1420 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 5226 1419 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(gpu_icache_dram_req_if.dram_rsp_ready) Tj -ET -Q -5230 840 m -5220 840 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 5226 839 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(dcache_req_if.core_req_ready) Tj -ET -Q -5230 1520 m -5220 1520 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 5226 1519 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(icache_rsp_if.core_rsp_valid[0]) Tj -ET -Q -5230 1440 m -5220 1440 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 5226 1439 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(icache_req_if.core_req_ready) Tj -ET -Q -3 w -5230 860 m -5220 860 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 5226 859 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(dcache_rsp_if.core_rsp_data[0][31..0]) Tj -ET -Q -5230 880 m -5220 880 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 5226 879 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(dcache_rsp_if.core_rsp_data[1][31..0]) Tj -ET -Q -5230 900 m -5220 900 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 5226 899 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(dcache_rsp_if.core_rsp_data[2][31..0]) Tj -ET -Q -5230 920 m -5220 920 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 5226 919 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(dcache_rsp_if.core_rsp_data[3][31..0]) Tj -ET -Q -5230 940 m -5220 940 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 5226 939 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(dcache_rsp_if.core_rsp_pc[0][31..0]) Tj -ET -Q -5230 960 m -5220 960 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 5226 959 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(dcache_rsp_if.core_rsp_pc[1][31..0]) Tj -ET -Q -5230 980 m -5220 980 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 5226 979 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(dcache_rsp_if.core_rsp_pc[2][31..0]) Tj -ET -Q -5230 1000 m -5220 1000 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 5226 999 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(dcache_rsp_if.core_rsp_pc[3][31..0]) Tj -ET -Q -5230 1020 m -5220 1020 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 5226 1019 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(dcache_rsp_if.core_rsp_read[4..0]) Tj -ET -Q -5230 1040 m -5220 1040 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 5226 1039 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(dcache_rsp_if.core_rsp_valid[3..0]) Tj -ET -Q -5230 1060 m -5220 1060 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 5226 1059 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(dcache_rsp_if.core_rsp_warp_num[2..0]) Tj -ET -Q -5230 1080 m -5220 1080 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 5226 1079 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(dcache_rsp_if.core_rsp_write[1..0]) Tj -ET -Q -5230 1100 m -5220 1100 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 5226 1099 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(gpu_dcache_dram_req_if.dram_req_addr[31..0]) Tj -ET -Q -5230 1120 m -5220 1120 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 5226 1119 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(gpu_dcache_dram_req_if.dram_req_data[0][31..0]) Tj -ET -Q -5230 1140 m -5220 1140 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 5226 1139 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(gpu_dcache_dram_req_if.dram_req_data[1][31..0]) Tj -ET -Q -5230 1160 m -5220 1160 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 5226 1159 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(gpu_dcache_dram_req_if.dram_req_data[2][31..0]) Tj -ET -Q -5230 1180 m -5220 1180 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 5226 1179 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(gpu_dcache_dram_req_if.dram_req_data[3][31..0]) Tj -ET -Q -5230 1280 m -5220 1280 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 5226 1279 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(gpu_icache_dram_req_if.dram_req_addr[31..0]) Tj -ET -Q -5230 1300 m -5220 1300 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 5226 1299 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(gpu_icache_dram_req_if.dram_req_data[0][31..0]) Tj -ET -Q -5230 1320 m -5220 1320 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 5226 1319 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(gpu_icache_dram_req_if.dram_req_data[1][31..0]) Tj -ET -Q -5230 1340 m -5220 1340 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 5226 1339 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(gpu_icache_dram_req_if.dram_req_data[2][31..0]) Tj -ET -Q -5230 1360 m -5220 1360 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 5226 1359 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(gpu_icache_dram_req_if.dram_req_data[3][31..0]) Tj -ET -Q -5230 1460 m -5220 1460 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 5226 1459 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(icache_rsp_if.core_rsp_data[0][31..0]) Tj -ET -Q -5230 1480 m -5220 1480 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 5226 1479 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(icache_rsp_if.core_rsp_pc[0][31..0]) Tj -ET -Q -5230 1500 m -5220 1500 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 5226 1499 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(icache_rsp_if.core_rsp_read[4..0]) Tj -ET -Q -5230 1540 m -5220 1540 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 5226 1539 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(icache_rsp_if.core_rsp_warp_num[2..0]) Tj -ET -Q -5230 1560 m -5220 1560 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 5226 1559 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(icache_rsp_if.core_rsp_write[1..0]) Tj -ET -Q -1 w -5170 680 m -5160 680 l -S -5170 1720 m -5160 1720 l -S -5170 1200 m -5160 1200 l -S -5170 1320 m -5160 1320 l -S -5170 1360 m -5160 1360 l -S -5170 1380 m -5160 1380 l -S -5170 1500 m -5160 1500 l -S -5170 1180 m -5160 1180 l -S -5170 1700 m -5160 1700 l -S -5170 1620 m -5160 1620 l -S -3 w -5170 700 m -5160 700 l -S -5170 720 m -5160 720 l -S -5170 740 m -5160 740 l -S -5170 760 m -5160 760 l -S -5170 780 m -5160 780 l -S -5170 800 m -5160 800 l -S -5170 820 m -5160 820 l -S -5170 840 m -5160 840 l -S -5170 860 m -5160 860 l -S -5170 880 m -5160 880 l -S -5170 900 m -5160 900 l -S -5170 920 m -5160 920 l -S -5170 940 m -5160 940 l -S -5170 960 m -5160 960 l -S -5170 980 m -5160 980 l -S -5170 1000 m -5160 1000 l -S -5170 1020 m -5160 1020 l -S -5170 1040 m -5160 1040 l -S -5170 1060 m -5160 1060 l -S -5170 1080 m -5160 1080 l -S -5170 1100 m -5160 1100 l -S -5170 1120 m -5160 1120 l -S -5170 1140 m -5160 1140 l -S -5170 1160 m -5160 1160 l -S -5170 1220 m -5160 1220 l -S -5170 1240 m -5160 1240 l -S -5170 1260 m -5160 1260 l -S -5170 1280 m -5160 1280 l -S -5170 1300 m -5160 1300 l -S -5170 1340 m -5160 1340 l -S -5170 1400 m -5160 1400 l -S -5170 1420 m -5160 1420 l -S -5170 1440 m -5160 1440 l -S -5170 1460 m -5160 1460 l -S -5170 1480 m -5160 1480 l -S -5170 1520 m -5160 1520 l -S -5170 1540 m -5160 1540 l -S -5170 1560 m -5160 1560 l -S -5170 1580 m -5160 1580 l -S -5170 1600 m -5160 1600 l -S -5170 1640 m -5160 1640 l -S -5170 1660 m -5160 1660 l -S -5170 1680 m -5160 1680 l -S -1 w -5210 1220 m -5220 1220 l -S -5210 1200 m -5220 1200 l -S -5210 1240 m -5220 1240 l -S -5210 1260 m -5220 1260 l -S -5210 1400 m -5220 1400 l -S -5210 1380 m -5220 1380 l -S -5210 1420 m -5220 1420 l -S -5210 840 m -5220 840 l -S -5210 1520 m -5220 1520 l -S -5210 1440 m -5220 1440 l -S -3 w -5210 860 m -5220 860 l -S -5210 880 m -5220 880 l -S -5210 900 m -5220 900 l -S -5210 920 m -5220 920 l -S -5210 940 m -5220 940 l -S -5210 960 m -5220 960 l -S -5210 980 m -5220 980 l -S -5210 1000 m -5220 1000 l -S -5210 1020 m -5220 1020 l -S -5210 1040 m -5220 1040 l -S -5210 1060 m -5220 1060 l -S -5210 1080 m -5220 1080 l -S -5210 1100 m -5220 1100 l -S -5210 1120 m -5220 1120 l -S -5210 1140 m -5220 1140 l -S -5210 1160 m -5220 1160 l -S -5210 1180 m -5220 1180 l -S -5210 1280 m -5220 1280 l -S -5210 1300 m -5220 1300 l -S -5210 1320 m -5220 1320 l -S -5210 1340 m -5220 1340 l -S -5210 1360 m -5220 1360 l -S -5210 1460 m -5220 1460 l -S -5210 1480 m -5220 1480 l -S -5210 1500 m -5220 1500 l -S -5210 1540 m -5220 1540 l -S -5210 1560 m -5220 1560 l -S -0.000 0.000 1.000 RG -6040 1100 m -6040 1093 l -6054 1093 l -6061 1100 l -6054 1107 l -6040 1107 l -h S -q -0.000 0.000 0.000 rg -1 0 0 1 6069 1100 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm -0 -4.308 Td -(dram_req_addr[31..0]) Tj -ET -Q -6040 1440 m -6040 1433 l -6054 1433 l -6061 1440 l -6054 1447 l -6040 1447 l -h S -q -0.000 0.000 0.000 rg -1 0 0 1 6069 1440 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm -0 -4.308 Td -(dram_req_data[127..0]) Tj -ET -Q -1 w -0 2560 m --7 2567 l --21 2567 l --21 2553 l --7 2553 l -h S -q -0.000 0.000 0.000 rg -1 0 0 1 -25 2560 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm --88.032 -4.308 Td -(dram_req_ready) Tj -ET -Q -6040 1200 m -6040 1193 l -6054 1193 l -6061 1200 l -6054 1207 l -6040 1207 l -h S -q -0.000 0.000 0.000 rg -1 0 0 1 6069 1200 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm -0 -4.308 Td -(dram_req_read) Tj -ET -Q -6040 1220 m -6040 1213 l -6054 1213 l -6061 1220 l -6054 1227 l -6040 1227 l -h S -q -0.000 0.000 0.000 rg -1 0 0 1 6069 1220 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm -0 -4.308 Td -(dram_req_write) Tj -ET -Q -3 w -0 2460 m --7 2467 l --21 2467 l --21 2453 l --7 2453 l -h S -q -0.000 0.000 0.000 rg -1 0 0 1 -25 2460 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm --114.72 -4.308 Td -(dram_rsp_addr[31..0]) Tj -ET -Q -0 2480 m --7 2487 l --21 2487 l --21 2473 l --7 2473 l -h S -q -0.000 0.000 0.000 rg -1 0 0 1 -25 2480 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm --120.732 -4.308 Td -(dram_rsp_data[127..0]) Tj -ET -Q -1 w -6040 1240 m -6040 1233 l -6054 1233 l -6061 1240 l -6054 1247 l -6040 1247 l -h S -q -0.000 0.000 0.000 rg -1 0 0 1 6069 1240 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm -0 -4.308 Td -(dram_rsp_ready) Tj -ET -Q -0 2500 m --7 2507 l --21 2507 l --21 2493 l --7 2493 l -h S -q -0.000 0.000 0.000 rg -1 0 0 1 -25 2500 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm --82.02 -4.308 Td -(dram_rsp_valid) Tj -ET -Q -6040 3020 m -6040 3013 l -6054 3013 l -6061 3020 l -6054 3027 l -6040 3027 l -h S -q -0.000 0.000 0.000 rg -1 0 0 1 6069 3020 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm -0 -4.308 Td -(ebreak) Tj -ET -Q -q -0.000 0.000 0.000 rg -865 1413 60 782 re -f -Q -q -0.506 0.749 0.373 rg -860 1408 60 782 re -f -Q -0.176 0.176 0.176 RG -860 1408 60 782 re -S -3 w -871 1413 m -871 1425 l -S -865 1419 m -877 1419 l -S -1 w -863 1411 16 16 re -S -q -0.000 0.000 0.000 rg -1 0 0 1 890 1406 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm --25.35 2.484 Td -(front_end) Tj -ET -Q -0.024 0.278 0.435 RG -850 1560 m -860 1560 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 858 1559 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --12.22 2.07 Td -(clk) Tj -ET -Q -850 1780 m -860 1780 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 858 1779 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --22.23 2.07 Td -(reset) Tj -ET -Q -850 1800 m -860 1800 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 858 1799 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --69.48 2.07 Td -(schedule_delay) Tj -ET -Q -850 1840 m -860 1840 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 858 1839 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --112.82 2.07 Td -(warp_ctl_if.change_mask) Tj -ET -Q -850 2120 m -860 2120 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 858 2119 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --86.69 2.07 Td -(warp_ctl_if.wspawn) Tj -ET -Q -850 1880 m -860 1880 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 858 1879 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --81.14 2.07 Td -(warp_ctl_if.ebreak) Tj -ET -Q -850 1900 m -860 1900 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 858 1899 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --92.24 2.07 Td -(warp_ctl_if.is_barrier) Tj -ET -Q -850 1920 m -860 1920 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 858 1919 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --81.13 2.07 Td -(warp_ctl_if.is_split) Tj -ET -Q -850 1860 m -860 1860 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 858 1859 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --93.37 2.07 Td -(warp_ctl_if.dont_split) Tj -ET -Q -850 1660 m -860 1660 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 858 1659 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --137.83 2.07 Td -(icache_rsp_if.core_rsp_valid[0]) Tj -ET -Q -850 1580 m -860 1580 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 858 1579 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --132.28 2.07 Td -(icache_req_if.core_req_ready) Tj -ET -Q -850 1760 m -860 1760 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 858 1759 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --52.79 2.07 Td -(jal_rsp_if.jal) Tj -ET -Q -850 1540 m -860 1540 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 858 1539 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --120.05 2.07 Td -(branch_rsp_if.valid_branch) Tj -ET -Q -850 1500 m -860 1500 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 858 1499 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --110.6 2.07 Td -(branch_rsp_if.branch_dir) Tj -ET -Q -3 w -850 1480 m -860 1480 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 858 1479 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --146.19 2.07 Td -(branch_rsp_if.branch_dest[31..0]) Tj -ET -Q -850 1520 m -860 1520 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 858 1519 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --168.41 2.07 Td -(branch_rsp_if.branch_warp_num[2..0]) Tj -ET -Q -850 1600 m -860 1600 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 858 1599 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --164.53 2.07 Td -(icache_rsp_if.core_rsp_data[0][31..0]) Tj -ET -Q -850 1620 m -860 1620 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 858 1619 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --155.63 2.07 Td -(icache_rsp_if.core_rsp_pc[0][31..0]) Tj -ET -Q -850 1640 m -860 1640 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 858 1639 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --148.4 2.07 Td -(icache_rsp_if.core_rsp_read[4..0]) Tj -ET -Q -850 1680 m -860 1680 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 858 1679 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --175.07 2.07 Td -(icache_rsp_if.core_rsp_warp_num[2..0]) Tj -ET -Q -850 1700 m -860 1700 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 858 1699 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --149.5 2.07 Td -(icache_rsp_if.core_rsp_write[1..0]) Tj -ET -Q -850 1720 m -860 1720 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 858 1719 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --105.05 2.07 Td -(jal_rsp_if.jal_dest[31..0]) Tj -ET -Q -850 1740 m -860 1740 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 858 1739 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --127.27 2.07 Td -(jal_rsp_if.jal_warp_num[2..0]) Tj -ET -Q -850 1820 m -860 1820 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 858 1819 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --120.6 2.07 Td -(warp_ctl_if.barrier_id[31..0]) Tj -ET -Q -850 1940 m -860 1940 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 858 1939 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --124.49 2.07 Td -(warp_ctl_if.num_warps[3..0]) Tj -ET -Q -850 1960 m -860 1960 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 858 1959 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --145.05 2.07 Td -(warp_ctl_if.split_later_mask[3..0]) Tj -ET -Q -850 1980 m -860 1980 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 858 1979 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --143.94 2.07 Td -(warp_ctl_if.split_new_mask[3..0]) Tj -ET -Q -850 2000 m -860 2000 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 858 1999 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --138.95 2.07 Td -(warp_ctl_if.split_save_pc[31..0]) Tj -ET -Q -850 2020 m -860 2020 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 858 2019 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --142.83 2.07 Td -(warp_ctl_if.split_warp_num[2..0]) Tj -ET -Q -850 2040 m -860 2040 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 858 2039 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --130.61 2.07 Td -(warp_ctl_if.thread_mask[3..0]) Tj -ET -Q -850 2060 m -860 2060 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 858 2059 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --119.49 2.07 Td -(warp_ctl_if.warp_num[2..0]) Tj -ET -Q -850 2080 m -860 2080 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 858 2079 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --164.51 2.07 Td -(warp_ctl_if.wspawn_new_active[7..0]) Tj -ET -Q -850 2100 m -860 2100 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 858 2099 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --130.61 2.07 Td -(warp_ctl_if.wspawn_pc[31..0]) Tj -ET -Q -1 w -930 2180 m -920 2180 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 926 2179 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(icache_rsp_if.core_rsp_ready) Tj -ET -Q -930 2100 m -920 2100 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 926 2099 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(icache_req_if.core_req_valid[0]) Tj -ET -Q -930 1620 m -920 1620 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 926 1619 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(bckE_req_if.is_csr) Tj -ET -Q -930 1520 m -920 1520 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 926 1519 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(bckE_req_if.csr_immed) Tj -ET -Q -930 1880 m -920 1880 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 926 1879 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(bckE_req_if.rs2_src) Tj -ET -Q -930 1580 m -920 1580 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 926 1579 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(bckE_req_if.ebreak) Tj -ET -Q -930 1720 m -920 1720 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 926 1719 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(bckE_req_if.jalQual) Tj -ET -Q -930 1760 m -920 1760 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 926 1759 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(bckE_req_if.jal) Tj -ET -Q -930 1680 m -920 1680 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 926 1679 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(bckE_req_if.is_wspawn) Tj -ET -Q -930 1660 m -920 1660 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 926 1659 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(bckE_req_if.is_tmc) Tj -ET -Q -930 1640 m -920 1640 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 926 1639 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(bckE_req_if.is_split) Tj -ET -Q -930 1600 m -920 1600 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 926 1599 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(bckE_req_if.is_barrier) Tj -ET -Q -930 1980 m -920 1980 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 926 1979 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(fetch_ebreak) Tj -ET -Q -3 w -930 1460 m -920 1460 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 926 1459 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(bckE_req_if.alu_op[4..0]) Tj -ET -Q -930 1480 m -920 1480 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 926 1479 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(bckE_req_if.branch_type[2..0]) Tj -ET -Q -930 1500 m -920 1500 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 926 1499 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(bckE_req_if.csr_address[11..0]) Tj -ET -Q -930 1540 m -920 1540 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 926 1539 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(bckE_req_if.csr_mask[31..0]) Tj -ET -Q -930 1560 m -920 1560 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 926 1559 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(bckE_req_if.curr_PC[31..0]) Tj -ET -Q -930 1700 m -920 1700 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 926 1699 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(bckE_req_if.itype_immed[31..0]) Tj -ET -Q -930 1740 m -920 1740 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 926 1739 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(bckE_req_if.jal_offset[31..0]) Tj -ET -Q -930 1780 m -920 1780 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 926 1779 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(bckE_req_if.mem_read[2..0]) Tj -ET -Q -930 1800 m -920 1800 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 926 1799 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(bckE_req_if.mem_write[2..0]) Tj -ET -Q -930 1440 m -920 1440 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 926 1439 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(bckE_req_if.PC_next[31..0]) Tj -ET -Q -930 1820 m -920 1820 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 926 1819 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(bckE_req_if.rd[4..0]) Tj -ET -Q -930 1840 m -920 1840 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 926 1839 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(bckE_req_if.rs1[4..0]) Tj -ET -Q -930 1860 m -920 1860 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 926 1859 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(bckE_req_if.rs2[4..0]) Tj -ET -Q -930 1900 m -920 1900 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 926 1899 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(bckE_req_if.upper_immed[19..0]) Tj -ET -Q -930 1920 m -920 1920 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 926 1919 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(bckE_req_if.valid[3..0]) Tj -ET -Q -930 1940 m -920 1940 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 926 1939 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(bckE_req_if.warp_num[2..0]) Tj -ET -Q -930 1960 m -920 1960 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 926 1959 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(bckE_req_if.wb[1..0]) Tj -ET -Q -930 2000 m -920 2000 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 926 1999 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(icache_req_if.core_req_addr[0][31..0]) Tj -ET -Q -930 2020 m -920 2020 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 926 2019 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(icache_req_if.core_req_data[0][31..0]) Tj -ET -Q -930 2040 m -920 2040 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 926 2039 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(icache_req_if.core_req_pc[31..0]) Tj -ET -Q -930 2060 m -920 2060 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 926 2059 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(icache_req_if.core_req_rd[4..0]) Tj -ET -Q -930 2080 m -920 2080 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 926 2079 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(icache_req_if.core_req_read[0][2..0]) Tj -ET -Q -930 2120 m -920 2120 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 926 2119 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(icache_req_if.core_req_warp_num[2..0]) Tj -ET -Q -930 2140 m -920 2140 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 926 2139 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(icache_req_if.core_req_wb[0][1..0]) Tj -ET -Q -930 2160 m -920 2160 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 926 2159 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm -0 2.07 Td -(icache_req_if.core_req_write[0][2..0]) Tj -ET -Q -1 w -870 1560 m -860 1560 l -S -870 1780 m -860 1780 l -S -870 1800 m -860 1800 l -S -870 1840 m -860 1840 l -S -870 2120 m -860 2120 l -S -870 1880 m -860 1880 l -S -870 1900 m -860 1900 l -S -870 1920 m -860 1920 l -S -870 1860 m -860 1860 l -S -870 1660 m -860 1660 l -S -870 1580 m -860 1580 l -S -870 1760 m -860 1760 l -S -870 1540 m -860 1540 l -S -870 1500 m -860 1500 l -S -3 w -870 1480 m -860 1480 l -S -870 1520 m -860 1520 l -S -870 1600 m -860 1600 l -S -870 1620 m -860 1620 l -S -870 1640 m -860 1640 l -S -870 1680 m -860 1680 l -S -870 1700 m -860 1700 l -S -870 1720 m -860 1720 l -S -870 1740 m -860 1740 l -S -870 1820 m -860 1820 l -S -870 1940 m -860 1940 l -S -870 1960 m -860 1960 l -S -870 1980 m -860 1980 l -S -870 2000 m -860 2000 l -S -870 2020 m -860 2020 l -S -870 2040 m -860 2040 l -S -870 2060 m -860 2060 l -S -870 2080 m -860 2080 l -S -870 2100 m -860 2100 l -S -1 w -910 2180 m -920 2180 l -S -910 2100 m -920 2100 l -S -910 1620 m -920 1620 l -S -910 1520 m -920 1520 l -S -910 1880 m -920 1880 l -S -910 1580 m -920 1580 l -S -910 1720 m -920 1720 l -S -910 1760 m -920 1760 l -S -910 1680 m -920 1680 l -S -910 1660 m -920 1660 l -S -910 1640 m -920 1640 l -S -910 1600 m -920 1600 l -S -910 1980 m -920 1980 l -S -3 w -910 1460 m -920 1460 l -S -910 1480 m -920 1480 l -S -910 1500 m -920 1500 l -S -910 1540 m -920 1540 l -S -910 1560 m -920 1560 l -S -910 1700 m -920 1700 l -S -910 1740 m -920 1740 l -S -910 1780 m -920 1780 l -S -910 1800 m -920 1800 l -S -910 1440 m -920 1440 l -S -910 1820 m -920 1820 l -S -910 1840 m -920 1840 l -S -910 1860 m -920 1860 l -S -910 1900 m -920 1900 l -S -910 1920 m -920 1920 l -S -910 1940 m -920 1940 l -S -910 1960 m -920 1960 l -S -910 2000 m -920 2000 l -S -910 2020 m -920 2020 l -S -910 2040 m -920 2040 l -S -910 2060 m -920 2060 l -S -910 2080 m -920 2080 l -S -910 2120 m -920 2120 l -S -910 2140 m -920 2140 l -S -910 2160 m -920 2160 l -S -0.000 0.000 1.000 RG -6040 420 m -6040 413 l -6054 413 l -6061 420 l -6054 427 l -6040 427 l -h S -q -0.000 0.000 0.000 rg -1 0 0 1 6069 420 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm -0 -4.308 Td -(io_data[31..0]) Tj -ET -Q -q -0.000 0.000 0.000 rg -5165 2915 m -5165 2930 l -5190 2930 l -5190 2930 l -5193 2930 l -5196 2929 l -5198 2928 l -5200 2926 l -5203 2923 l -5204 2921 l -5205 2918 l -5205 2915 l -5205 2912 l -5204 2909 l -5203 2907 l -5201 2905 l -5198 2902 l -5196 2901 l -5193 2900 l -5190 2900 l -5190 2900 l -5165 2900 l -h f -Q -q -0.451 0.675 0.675 rg -5160 2910 m -5160 2925 l -5185 2925 l -5185 2925 l -5188 2925 l -5191 2924 l -5193 2923 l -5195 2921 l -5198 2918 l -5199 2916 l -5200 2913 l -5200 2910 l -5200 2907 l -5199 2904 l -5198 2902 l -5196 2900 l -5193 2897 l -5191 2896 l -5188 2895 l -5185 2895 l -5185 2895 l -5160 2895 l -h f -Q -1 w -0.176 0.176 0.176 RG -5160 2910 m -5160 2925 l -5185 2925 l -S -5185 2895 m -5185 2895 5185 2895 5185 2895 c -5193.28 2895 5200 2901.72 5200 2910 c -5200 2918.28 5193.28 2925 5185 2925 c -S -5185 2895 m -5160 2895 l -5160 2910 l -S -5160 2895 m -5160 2876 l -S -5160 2925 m -5160 2944 l -S -q -0.000 0.000 0.000 rg -1 0 0 1 5162 2894 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm -0 2.484 Td -(io_valid) Tj -ET -Q -0.024 0.278 0.435 RG -5160 2880 m -5160 2878.34 5158.66 2877 5157 2877 c -5155.34 2877 5154 2878.34 5154 2880 c -5154 2881.66 5155.34 2883 5157 2883 c -5158.66 2883 5160 2881.66 5160 2880 c -S -5150 2880 m -5154 2880 l -S -5150 2920 m -5160 2920 l -S -5150 2900 m -5160 2900 l -S -5160 2940 m -5160 2938.34 5158.66 2937 5157 2937 c -5155.34 2937 5154 2938.34 5154 2940 c -5154 2941.66 5155.34 2943 5157 2943 c -5158.66 2943 5160 2941.66 5160 2940 c -S -5150 2940 m -5154 2940 l -S -5210 2910 m -5200 2910 l -S -0.000 0.000 1.000 RG -6040 2910 m -6040 2903 l -6054 2903 l -6061 2910 l -6054 2917 l -6040 2917 l -h S -q -0.000 0.000 0.000 rg -1 0 0 1 6069 2910 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm -0 -4.308 Td -(io_valid) Tj -ET -Q -q -0.000 0.000 0.000 rg -4265 2645 m -4265 2660 l -4290 2660 l -4290 2660 l -4293 2660 l -4296 2659 l -4298 2658 l -4300 2656 l -4303 2653 l -4304 2651 l -4305 2648 l -4305 2645 l -4305 2642 l -4304 2639 l -4303 2637 l -4301 2635 l -4298 2632 l -4296 2631 l -4293 2630 l -4290 2630 l -4290 2630 l -4265 2630 l -h f -Q -q -0.451 0.675 0.675 rg -4260 2640 m -4260 2655 l -4285 2655 l -4285 2655 l -4288 2655 l -4291 2654 l -4293 2653 l -4295 2651 l -4298 2648 l -4299 2646 l -4300 2643 l -4300 2640 l -4300 2637 l -4299 2634 l -4298 2632 l -4296 2630 l -4293 2627 l -4291 2626 l -4288 2625 l -4285 2625 l -4285 2625 l -4260 2625 l -h f -Q -0.176 0.176 0.176 RG -4260 2640 m -4260 2655 l -4285 2655 l -S -4285 2625 m -4285 2625 4285 2625 4285 2625 c -4293.28 2625 4300 2631.72 4300 2640 c -4300 2648.28 4293.28 2655 4285 2655 c -S -4285 2625 m -4260 2625 l -4260 2640 l -S -q -0.000 0.000 0.000 rg -1 0 0 1 4262 2624 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm -0 2.484 Td -(i403) Tj -ET -Q -0.024 0.278 0.435 RG -4260 2650 m -4260 2648.34 4258.66 2647 4257 2647 c -4255.34 2647 4254 2648.34 4254 2650 c -4254 2651.66 4255.34 2653 4257 2653 c -4258.66 2653 4260 2651.66 4260 2650 c -S -4250 2650 m -4254 2650 l -S -4250 2630 m -4260 2630 l -S -4310 2640 m -4300 2640 l -S -q -0.000 0.000 0.000 rg -4265 2695 m -4265 2710 l -4290 2710 l -4290 2710 l -4293 2710 l -4296 2709 l -4298 2708 l -4300 2706 l -4303 2703 l -4304 2701 l -4305 2698 l -4305 2695 l -4305 2692 l -4304 2689 l -4303 2687 l -4301 2685 l -4298 2682 l -4296 2681 l -4293 2680 l -4290 2680 l -4290 2680 l -4265 2680 l -h f -Q -q -0.451 0.675 0.675 rg -4260 2690 m -4260 2705 l -4285 2705 l -4285 2705 l -4288 2705 l -4291 2704 l -4293 2703 l -4295 2701 l -4298 2698 l -4299 2696 l -4300 2693 l -4300 2690 l -4300 2687 l -4299 2684 l -4298 2682 l -4296 2680 l -4293 2677 l -4291 2676 l -4288 2675 l -4285 2675 l -4285 2675 l -4260 2675 l -h f -Q -0.176 0.176 0.176 RG -4260 2690 m -4260 2705 l -4285 2705 l -S -4285 2675 m -4285 2675 4285 2675 4285 2675 c -4293.28 2675 4300 2681.72 4300 2690 c -4300 2698.28 4293.28 2705 4285 2705 c -S -4285 2675 m -4260 2675 l -4260 2690 l -S -q -0.000 0.000 0.000 rg -1 0 0 1 4262 2674 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm -0 2.484 Td -(i404) Tj -ET -Q -0.024 0.278 0.435 RG -4260 2700 m -4260 2698.34 4258.66 2697 4257 2697 c -4255.34 2697 4254 2698.34 4254 2700 c -4254 2701.66 4255.34 2703 4257 2703 c -4258.66 2703 4260 2701.66 4260 2700 c -S -4250 2700 m -4254 2700 l -S -4250 2680 m -4260 2680 l -S -4310 2690 m -4300 2690 l -S -q -0.000 0.000 0.000 rg -4265 2745 m -4265 2760 l -4290 2760 l -4290 2760 l -4293 2760 l -4296 2759 l -4298 2758 l -4300 2756 l -4303 2753 l -4304 2751 l -4305 2748 l -4305 2745 l -4305 2742 l -4304 2739 l -4303 2737 l -4301 2735 l -4298 2732 l -4296 2731 l -4293 2730 l -4290 2730 l -4290 2730 l -4265 2730 l -h f -Q -q -0.451 0.675 0.675 rg -4260 2740 m -4260 2755 l -4285 2755 l -4285 2755 l -4288 2755 l -4291 2754 l -4293 2753 l -4295 2751 l -4298 2748 l -4299 2746 l -4300 2743 l -4300 2740 l -4300 2737 l -4299 2734 l -4298 2732 l -4296 2730 l -4293 2727 l -4291 2726 l -4288 2725 l -4285 2725 l -4285 2725 l -4260 2725 l -h f -Q -0.176 0.176 0.176 RG -4260 2740 m -4260 2755 l -4285 2755 l -S -4285 2725 m -4285 2725 4285 2725 4285 2725 c -4293.28 2725 4300 2731.72 4300 2740 c -4300 2748.28 4293.28 2755 4285 2755 c -S -4285 2725 m -4260 2725 l -4260 2740 l -S -q -0.000 0.000 0.000 rg -1 0 0 1 4262 2724 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm -0 2.484 Td -(i405) Tj -ET -Q -0.024 0.278 0.435 RG -4260 2750 m -4260 2748.34 4258.66 2747 4257 2747 c -4255.34 2747 4254 2748.34 4254 2750 c -4254 2751.66 4255.34 2753 4257 2753 c -4258.66 2753 4260 2751.66 4260 2750 c -S -4250 2750 m -4254 2750 l -S -4250 2730 m -4260 2730 l -S -4310 2740 m -4300 2740 l -S -q -0.000 0.000 0.000 rg -4265 2795 m -4265 2810 l -4290 2810 l -4290 2810 l -4293 2810 l -4296 2809 l -4298 2808 l -4300 2806 l -4303 2803 l -4304 2801 l -4305 2798 l -4305 2795 l -4305 2792 l -4304 2789 l -4303 2787 l -4301 2785 l -4298 2782 l -4296 2781 l -4293 2780 l -4290 2780 l -4290 2780 l -4265 2780 l -h f -Q -q -0.451 0.675 0.675 rg -4260 2790 m -4260 2805 l -4285 2805 l -4285 2805 l -4288 2805 l -4291 2804 l -4293 2803 l -4295 2801 l -4298 2798 l -4299 2796 l -4300 2793 l -4300 2790 l -4300 2787 l -4299 2784 l -4298 2782 l -4296 2780 l -4293 2777 l -4291 2776 l -4288 2775 l -4285 2775 l -4285 2775 l -4260 2775 l -h f -Q -0.176 0.176 0.176 RG -4260 2790 m -4260 2805 l -4285 2805 l -S -4285 2775 m -4285 2775 4285 2775 4285 2775 c -4293.28 2775 4300 2781.72 4300 2790 c -4300 2798.28 4293.28 2805 4285 2805 c -S -4285 2775 m -4260 2775 l -4260 2790 l -S -q -0.000 0.000 0.000 rg -1 0 0 1 4262 2774 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm -0 2.484 Td -(i406) Tj -ET -Q -0.024 0.278 0.435 RG -4260 2800 m -4260 2798.34 4258.66 2797 4257 2797 c -4255.34 2797 4254 2798.34 4254 2800 c -4254 2801.66 4255.34 2803 4257 2803 c -4258.66 2803 4260 2801.66 4260 2800 c -S -4250 2800 m -4254 2800 l -S -4250 2780 m -4260 2780 l -S -4310 2790 m -4300 2790 l -S -3 w -0.000 0.000 1.000 RG -0 2580 m --7 2587 l --21 2587 l --21 2573 l --7 2573 l -h S -q -0.000 0.000 0.000 rg -1 0 0 1 -25 2580 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm --125.4 -4.308 Td -(llc_snp_req_addr[31..0]) Tj -ET -Q -1 w -6040 1260 m -6040 1253 l -6054 1253 l -6061 1260 l -6054 1267 l -6040 1267 l -h S -q -0.000 0.000 0.000 rg -1 0 0 1 6069 1260 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm -0 -4.308 Td -(llc_snp_req_ready) Tj -ET -Q -0 2600 m --7 2607 l --21 2607 l --21 2593 l --7 2593 l -h S -q -0.000 0.000 0.000 rg -1 0 0 1 -25 2600 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm --92.7 -4.308 Td -(llc_snp_req_valid) Tj -ET -Q -q -0.000 0.000 0.000 rg -4265 160 m -4267 162 l -4269 165 l -4270 167 l -4271 170 l -4272 173 l -4272 177 l -4271 180 l -4270 183 l -4269 185 l -4267 188 l -4265 190 l -4265 190 l -4280 190 l -4280 190 l -4283 190 l -4286 189 l -4289 188 l -4291 187 l -4294 186 l -4297 184 l -4299 182 l -4301 180 l -4303 178 l -4305 175 l -4305 175 l -4303 172 l -4301 170 l -4299 168 l -4297 166 l -4294 164 l -4291 163 l -4289 162 l -4286 161 l -4283 160 l -4280 160 l -4280 160 l -h f -Q -q -0.451 0.675 0.675 rg -4260 155 m -4262 157 l -4264 160 l -4265 162 l -4266 165 l -4267 168 l -4267 172 l -4266 175 l -4265 178 l -4264 180 l -4262 183 l -4260 185 l -4260 185 l -4275 185 l -4275 185 l -4278 185 l -4281 184 l -4284 183 l -4286 182 l -4289 181 l -4292 179 l -4294 177 l -4296 175 l -4298 173 l -4300 170 l -4300 170 l -4298 167 l -4296 165 l -4294 163 l -4292 161 l -4289 159 l -4286 158 l -4284 157 l -4281 156 l -4278 155 l -4275 155 l -4275 155 l -h f -Q -0.176 0.176 0.176 RG -4260 185 m -4260.88 184.263 4261.69 183.451 4262.43 182.571 c -4269.37 174.287 4268.28 161.943 4260 155 c -S -4260 185 m -4275 185 l -S -4300 170 m -4294.49 178.656 4285.23 184.213 4275 185 c -S -4275 155 m -4285.23 155.787 4294.49 161.344 4300 170 c -S -4275 155 m -4260 155 l -S -4260 155 m -4260 6 l -S -4260 185 m -4260 324 l -S -q -0.000 0.000 0.000 rg -1 0 0 1 4262 154 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm -0 2.484 Td -(reduce_nor_0) Tj -ET -Q -0.024 0.278 0.435 RG -4250 10 m -4260 10 l -S -4250 20 m -4260 20 l -S -4250 30 m -4260 30 l -S -4250 40 m -4260 40 l -S -4250 50 m -4260 50 l -S -4250 60 m -4260 60 l -S -4250 70 m -4260 70 l -S -4250 80 m -4260 80 l -S -4250 90 m -4260 90 l -S -4250 100 m -4260 100 l -S -4250 110 m -4260 110 l -S -4250 120 m -4260 120 l -S -4250 130 m -4260 130 l -S -4250 140 m -4260 140 l -S -4250 150 m -4260 150 l -S -4263 160 m -4263 158.343 4261.66 157 4260 157 c -4258.34 157 4257 158.343 4257 160 c -4257 161.657 4258.34 163 4260 163 c -4261.66 163 4263 161.657 4263 160 c -S -4250 160 m -4257 160 l -S -4250 170 m -4267 170 l -S -4250 180 m -4264 180 l -S -4250 190 m -4260 190 l -S -4250 200 m -4260 200 l -S -4250 210 m -4260 210 l -S -4250 220 m -4260 220 l -S -4250 230 m -4260 230 l -S -4250 240 m -4260 240 l -S -4250 250 m -4260 250 l -S -4250 260 m -4260 260 l -S -4250 270 m -4260 270 l -S -4250 280 m -4260 280 l -S -4250 290 m -4260 290 l -S -4250 300 m -4260 300 l -S -4250 310 m -4260 310 l -S -4250 320 m -4260 320 l -S -4310 170 m -4300 170 l -S -q -0.000 0.000 0.000 rg -4265 2840 m -4267 2842 l -4269 2845 l -4270 2847 l -4271 2850 l -4272 2853 l -4272 2857 l -4271 2860 l -4270 2863 l -4269 2865 l -4267 2868 l -4265 2870 l -4265 2870 l -4280 2870 l -4280 2870 l -4283 2870 l -4286 2869 l -4289 2868 l -4291 2867 l -4294 2866 l -4297 2864 l -4299 2862 l -4301 2860 l -4303 2858 l -4305 2855 l -4305 2855 l -4303 2852 l -4301 2850 l -4299 2848 l -4297 2846 l -4294 2844 l -4291 2843 l -4289 2842 l -4286 2841 l -4283 2840 l -4280 2840 l -4280 2840 l -h f -Q -q -0.451 0.675 0.675 rg -4260 2835 m -4262 2837 l -4264 2840 l -4265 2842 l -4266 2845 l -4267 2848 l -4267 2852 l -4266 2855 l -4265 2858 l -4264 2860 l -4262 2863 l -4260 2865 l -4260 2865 l -4275 2865 l -4275 2865 l -4278 2865 l -4281 2864 l -4284 2863 l -4286 2862 l -4289 2861 l -4292 2859 l -4294 2857 l -4296 2855 l -4298 2853 l -4300 2850 l -4300 2850 l -4298 2847 l -4296 2845 l -4294 2843 l -4292 2841 l -4289 2839 l -4286 2838 l -4284 2837 l -4281 2836 l -4278 2835 l -4275 2835 l -4275 2835 l -h f -Q -0.176 0.176 0.176 RG -4260 2865 m -4260.88 2864.26 4261.69 2863.45 4262.43 2862.57 c -4269.37 2854.29 4268.28 2841.94 4260 2835 c -S -4260 2865 m -4275 2865 l -S -4300 2850 m -4294.49 2858.66 4285.23 2864.21 4275 2865 c -S -4275 2835 m -4285.23 2835.79 4294.49 2841.34 4300 2850 c -S -4275 2835 m -4260 2835 l -S -4260 2835 m -4260 2816 l -S -4260 2865 m -4260 2884 l -S -q -0.000 0.000 0.000 rg -1 0 0 1 4262 2834 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm -0 2.484 Td -(reduce_or_0) Tj -ET -Q -0.024 0.278 0.435 RG -4250 2820 m -4260 2820 l -S -4250 2840 m -4264 2840 l -S -4250 2860 m -4264 2860 l -S -4250 2880 m -4260 2880 l -S -4310 2850 m -4300 2850 l -S -q -0.000 0.000 0.000 rg -4265 2910 m -4267 2912 l -4269 2915 l -4270 2917 l -4271 2920 l -4272 2923 l -4272 2927 l -4271 2930 l -4270 2933 l -4269 2935 l -4267 2938 l -4265 2940 l -4265 2940 l -4280 2940 l -4280 2940 l -4283 2940 l -4286 2939 l -4289 2938 l -4291 2937 l -4294 2936 l -4297 2934 l -4299 2932 l -4301 2930 l -4303 2928 l -4305 2925 l -4305 2925 l -4303 2922 l -4301 2920 l -4299 2918 l -4297 2916 l -4294 2914 l -4291 2913 l -4289 2912 l -4286 2911 l -4283 2910 l -4280 2910 l -4280 2910 l -h f -Q -q -0.451 0.675 0.675 rg -4260 2905 m -4262 2907 l -4264 2910 l -4265 2912 l -4266 2915 l -4267 2918 l -4267 2922 l -4266 2925 l -4265 2928 l -4264 2930 l -4262 2933 l -4260 2935 l -4260 2935 l -4275 2935 l -4275 2935 l -4278 2935 l -4281 2934 l -4284 2933 l -4286 2932 l -4289 2931 l -4292 2929 l -4294 2927 l -4296 2925 l -4298 2923 l -4300 2920 l -4300 2920 l -4298 2917 l -4296 2915 l -4294 2913 l -4292 2911 l -4289 2909 l -4286 2908 l -4284 2907 l -4281 2906 l -4278 2905 l -4275 2905 l -4275 2905 l -h f -Q -0.176 0.176 0.176 RG -4260 2935 m -4260.88 2934.26 4261.69 2933.45 4262.43 2932.57 c -4269.37 2924.29 4268.28 2911.94 4260 2905 c -S -4260 2935 m -4275 2935 l -S -4300 2920 m -4294.49 2928.66 4285.23 2934.21 4275 2935 c -S -4275 2905 m -4285.23 2905.79 4294.49 2911.34 4300 2920 c -S -4275 2905 m -4260 2905 l -S -4260 2905 m -4260 2896 l -S -4260 2935 m -4260 2944 l -S -q -0.000 0.000 0.000 rg -1 0 0 1 4262 2904 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm -0 2.484 Td -(reduce_or_1) Tj -ET -Q -0.024 0.278 0.435 RG -4260 2900 m -4260 2898.34 4258.66 2897 4257 2897 c -4255.34 2897 4254 2898.34 4254 2900 c -4254 2901.66 4255.34 2903 4257 2903 c -4258.66 2903 4260 2901.66 4260 2900 c -S -4250 2900 m -4254 2900 l -S -4267 2920 m -4267 2918.34 4265.66 2917 4264 2917 c -4262.34 2917 4261 2918.34 4261 2920 c -4261 2921.66 4262.34 2923 4264 2923 c -4265.66 2923 4267 2921.66 4267 2920 c -S -4250 2920 m -4261 2920 l -S -4260 2940 m -4260 2938.34 4258.66 2937 4257 2937 c -4255.34 2937 4254 2938.34 4254 2940 c -4254 2941.66 4255.34 2943 4257 2943 c -4258.66 2943 4260 2941.66 4260 2940 c -S -4250 2940 m -4254 2940 l -S -4310 2920 m -4300 2920 l -S -0.000 0.000 1.000 RG -0 1380 m --7 1387 l --21 1387 l --21 1373 l --7 1373 l -h S -q -0.000 0.000 0.000 rg -1 0 0 1 -25 1380 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm --26.676 -4.308 Td -(reset) Tj -ET -Q -q -0.000 0.000 0.000 rg -2135 593 60 842 re -f -Q -q -0.506 0.749 0.373 rg -2130 588 60 842 re -f -Q -0.176 0.176 0.176 RG -2130 588 60 842 re -S -3 w -2141 593 m -2141 605 l -S -2135 599 m -2147 599 l -S -1 w -2133 591 16 16 re -S -q -0.000 0.000 0.000 rg -1 0 0 1 2160 586 cm -BT -/F1 12 Tf -1 0 0 -1 0 0 Tm --24.012 2.484 Td -(schedule) Tj -ET -Q -0.024 0.278 0.435 RG -2120 1160 m -2130 1160 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 2128 1159 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --12.22 2.07 Td -(clk) Tj -ET -Q -2120 1240 m -2130 1240 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 2128 1239 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --22.23 2.07 Td -(reset) Tj -ET -Q -2120 1220 m -2130 1220 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 2128 1219 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --65.57 2.07 Td -(memory_delay) Tj -ET -Q -2120 1180 m -2130 1180 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 2128 1179 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --50.58 2.07 Td -(exec_delay) Tj -ET -Q -2120 1200 m -2130 1200 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 2128 1199 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --73.93 2.07 Td -(gpr_stage_delay) Tj -ET -Q -2120 800 m -2130 800 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 2128 799 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --81.69 2.07 Td -(bckE_req_if.is_csr) Tj -ET -Q -2120 700 m -2130 700 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 2128 699 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --104.47 2.07 Td -(bckE_req_if.csr_immed) Tj -ET -Q -2120 1060 m -2130 1060 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 2128 1059 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --88.36 2.07 Td -(bckE_req_if.rs2_src) Tj -ET -Q -2120 760 m -2130 760 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 2128 759 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --86.15 2.07 Td -(bckE_req_if.ebreak) Tj -ET -Q -2120 900 m -2130 900 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 2128 899 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --86.7 2.07 Td -(bckE_req_if.jalQual) Tj -ET -Q -2120 940 m -2130 940 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 2128 939 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --65.58 2.07 Td -(bckE_req_if.jal) Tj -ET -Q -2120 860 m -2130 860 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 2128 859 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --104.48 2.07 Td -(bckE_req_if.is_wspawn) Tj -ET -Q -2120 840 m -2130 840 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 2128 839 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --84.47 2.07 Td -(bckE_req_if.is_tmc) Tj -ET -Q -2120 820 m -2130 820 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 2128 819 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --86.14 2.07 Td -(bckE_req_if.is_split) Tj -ET -Q -2120 780 m -2130 780 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 2128 779 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --97.25 2.07 Td -(bckE_req_if.is_barrier) Tj -ET -Q -3 w -2120 640 m -2130 640 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 2128 639 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --107.84 2.07 Td -(bckE_req_if.alu_op[4..0]) Tj -ET -Q -2120 660 m -2130 660 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 2128 659 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --132.85 2.07 Td -(bckE_req_if.branch_type[2..0]) Tj -ET -Q -2120 680 m -2130 680 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 2128 679 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --137.84 2.07 Td -(bckE_req_if.csr_address[11..0]) Tj -ET -Q -2120 720 m -2130 720 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 2128 719 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --126.16 2.07 Td -(bckE_req_if.csr_mask[31..0]) Tj -ET -Q -2120 740 m -2130 740 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 2128 739 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --120.05 2.07 Td -(bckE_req_if.curr_PC[31..0]) Tj -ET -Q -2120 880 m -2130 880 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 2128 879 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --140.06 2.07 Td -(bckE_req_if.itype_immed[31..0]) Tj -ET -Q -2120 920 m -2130 920 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 2128 919 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --123.4 2.07 Td -(bckE_req_if.jal_offset[31..0]) Tj -ET -Q -2120 960 m -2130 960 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 2128 959 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --125.61 2.07 Td -(bckE_req_if.mem_read[2..0]) Tj -ET -Q -2120 980 m -2130 980 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 2128 979 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --126.71 2.07 Td -(bckE_req_if.mem_write[2..0]) Tj -ET -Q -2120 620 m -2130 620 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 2128 619 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --121.73 2.07 Td -(bckE_req_if.PC_next[31..0]) Tj -ET -Q -2120 1000 m -2130 1000 l -S -q -0.024 0.278 0.435 rg -1 0 0 1 2128 999 cm -BT -/F1 10 Tf -1 0 0 -1 0 0 Tm --86.71 2.07 Td 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filename) { delete[] content; return err; +} + +extern int vx_get_perf(vx_device_h device, int core_id, size_t* cycles, size_t* instrs) { + int ret = 0; + + unsigned value; + + if (cycles) { + ret |= vx_csr_get(device, core_id, CSR_CYCLE_H, &value); + *cycles = value; + ret |= vx_csr_get(device, core_id, CSR_CYCLE, &value); + *cycles = (*cycles << 32) | value; + } + + if (instrs) { + ret |= vx_csr_get(device, core_id, CSR_INSTRET_H, &value); + *instrs = value; + ret |= vx_csr_get(device, core_id, CSR_INSTRET, &value); + *instrs = (*instrs << 32) | value; + } + + return ret; } \ No newline at end of file diff --git a/driver/include/vortex.h b/driver/include/vortex.h index a9597253..e5aa9eb6 100644 --- a/driver/include/vortex.h +++ b/driver/include/vortex.h @@ -58,10 +58,10 @@ int vx_start(vx_device_h hdevice); int vx_ready_wait(vx_device_h hdevice, long long timeout); // set device constant registers -int vx_csr_set(vx_device_h hdevice, int core, int address, unsigned value); +int vx_csr_set(vx_device_h hdevice, int core_id, int addr, unsigned value); // get device constant registers -int vx_csr_get(vx_device_h hdevice, int core, int address, unsigned* value); +int vx_csr_get(vx_device_h hdevice, int core_id, int addr, unsigned* value); ////////////////////////////// UTILITY FUNCIONS /////////////////////////////// @@ -71,6 +71,9 @@ int vx_upload_kernel_bytes(vx_device_h device, const void* content, size_t size) // upload kernel file to device int vx_upload_kernel_file(vx_device_h device, const char* filename); +// get performance counters +int vx_get_perf(vx_device_h device, int core_id, size_t* cycles, size_t* instrs); + #ifdef __cplusplus } #endif diff --git a/driver/opae/Makefile b/driver/opae/Makefile index b13b897d..9946470f 100644 --- a/driver/opae/Makefile +++ b/driver/opae/Makefile @@ -17,6 +17,9 @@ CXXFLAGS +=-fstack-protector # Position independent code CXXFLAGS += -fPIC +# Dump perf stats +CXXFLAGS += -DDUMP_PERF_STATS + # Enable scope analyzer #CXXFLAGS += -DSCOPE diff --git a/driver/opae/scope.cpp b/driver/opae/scope.cpp index 6053d353..6b12a7ab 100644 --- a/driver/opae/scope.cpp +++ b/driver/opae/scope.cpp @@ -18,6 +18,12 @@ return -1; \ } while (false) + +template +constexpr bool static_print() { + return (0 < N < 100); +} + #define MMIO_SCOPE_READ (AFU_IMAGE_MMIO_SCOPE_READ * 4) #define MMIO_SCOPE_WRITE (AFU_IMAGE_MMIO_SCOPE_WRITE * 4) @@ -27,12 +33,26 @@ struct scope_signal_t { }; constexpr int ilog2(int n) { - return (n > 1) ? 1 + ilog2(n >> 1) : 0; + return (n > 1) ? 1 + + ilog2(n >> 1) : 0; } static constexpr int NW_BITS = ilog2(NUM_WARPS); -static const scope_signal_t scope_signals[] = { +#ifdef EXT_F_ENABLE +static constexpr int NR_BITS = ilog2(64); +#else +static constexpr int NR_BITS = ilog2(32); +#endif + +static constexpr int EX_BITS = 3; +static constexpr int OP_BITS = 4; +static constexpr int MOD_BITS = 3; + +static constexpr int ICORE_TAG_WIDTH = NW_BITS; +static constexpr int DCORE_TAG_WIDTH = ilog2(LSUQ_SIZE); + +static constexpr scope_signal_t scope_signals[] = { { 32, "dram_req_addr" }, { 1, "dram_req_rw" }, @@ -47,39 +67,47 @@ static const scope_signal_t scope_signals[] = { { 16, "snp_req_tag" }, { 16, "snp_rsp_tag" }, - { NW_BITS, "icache_req_warp_num" }, + { NW_BITS, "icache_req_wid" }, { 32, "icache_req_addr" }, - { NW_BITS, "icache_req_tag" }, + { ICORE_TAG_WIDTH, "icache_req_tag" }, { 32, "icache_rsp_data" }, - { NW_BITS, "icache_rsp_tag" }, + { ICORE_TAG_WIDTH, "icache_rsp_tag" }, - { NW_BITS, "dcache_req_warp_num" }, - { 32, "dcache_req_curr_PC" }, - { 64, "dcache_req_addr" }, + { NW_BITS, "dcache_req_wid" }, + { 32, "dcache_req_pc" }, + { NUM_THREADS * 32, "dcache_req_addr" }, { 1, "dcache_req_rw" }, - { 8, "dcache_req_byteen" }, - { 64, "dcache_req_data" }, - { NW_BITS, "dcache_req_tag" }, - { 64, "dcache_rsp_data" }, - { NW_BITS, "dcache_rsp_tag" }, + { NUM_THREADS * 4, "dcache_req_byteen" }, + { NUM_THREADS * 32, "dcache_req_data" }, + { DCORE_TAG_WIDTH, "dcache_req_tag" }, + { NUM_THREADS * 32, "dcache_rsp_data" }, + { DCORE_TAG_WIDTH, "dcache_rsp_tag" }, + + { NW_BITS, "issue_wid" }, + { NUM_THREADS, "issue_tmask" }, + { 32, "issue_pc" }, + { EX_BITS, "issue_ex_type" }, + { OP_BITS, "issue_op_type" }, + { MOD_BITS, "issue_op_mod" }, + { 1, "issue_wb" }, + { NR_BITS, "issue_rd" }, + { NR_BITS, "issue_rs1" }, + { NR_BITS, "issue_rs2" }, + { NR_BITS, "issue_rs3" }, + { 32, "issue_imm" }, + { 1, "issue_rs1_is_pc" }, + { 1, "issue_rs2_is_imm" }, - { NW_BITS, "decode_warp_num" }, - { 32, "decode_curr_PC" }, - { 1, "decode_is_jal" }, - { 5, "decode_rs1" }, - { 5, "decode_rs2" }, + { NW_BITS, "gpr_rsp_wid" }, + { 32, "gpr_rsp_pc" }, + { NUM_THREADS * 32, "gpr_rsp_a" }, + { NUM_THREADS * 32, "gpr_rsp_b" }, + { NUM_THREADS * 32, "gpr_rsp_c" }, - { NW_BITS, "execute_warp_num" }, - { 32, "execute_curr_PC" }, - { 5, "execute_rd" }, - { 64, "execute_a" }, - { 64, "execute_b" }, - - { NW_BITS, "writeback_warp_num" }, - { 32, "writeback_curr_PC" }, - { 2, "writeback_wb" }, - { 5, "writeback_rd" }, - { 64, "writeback_data" }, + { NW_BITS, "writeback_wid" }, + { 32, "writeback_pc" }, + { NR_BITS, "writeback_rd" }, + { NUM_THREADS * 32, "writeback_data" }, { 32, "bank_addr_st0" }, { 32, "bank_addr_st1" }, @@ -111,23 +139,29 @@ static const scope_signal_t scope_signals[] = { { NUM_THREADS, "dcache_rsp_valid" }, { 1, "dcache_rsp_ready" }, - { NUM_THREADS, "decode_valid" }, - { NUM_THREADS, "execute_valid" }, - { NUM_THREADS, "writeback_valid" }, - - { 1, "schedule_delay" }, - { 1, "memory_delay" }, - { 1, "exec_delay" }, - { 1, "gpr_stage_delay" }, - { 1, "busy" }, - { 1, "bank_valid_st0" }, { 1, "bank_valid_st1" }, { 1, "bank_valid_st2" }, { 1, "bank_stall_pipe" }, + + { 1, "issue_valid" }, + { 1, "issue_ready" }, + { 1, "gpr_rsp_valid" }, + { 1, "writeback_valid" }, + { 1, "scoreboard_delay" }, + { 1, "gpr_delay" }, + { 1, "execute_delay" }, + { 1, "busy" }, }; -static const int num_signals = sizeof(scope_signals) / sizeof(scope_signal_t); +static constexpr int num_signals = sizeof(scope_signals) / sizeof(scope_signal_t); + +constexpr int calcFrameWidth(int index = 0) { + return (index < num_signals) ? (scope_signals[index].width + calcFrameWidth(index + 1)) : 0; +} + +static constexpr int fwidth = calcFrameWidth(); +static_assert(fwidth == 1766, "invalid size"); int vx_scope_start(fpga_handle hfpga, uint64_t delay) { if (nullptr == hfpga) @@ -159,12 +193,6 @@ int vx_scope_stop(fpga_handle hfpga, uint64_t delay) { ofs << "$timescale 1 ns $end" << std::endl; ofs << "$var reg 1 0 clk $end" << std::endl; - int fwidth = 0; - for (int i = 0; i < num_signals; ++i) { - ofs << "$var reg " << scope_signals[i].width << " " << (i+1) << " " << scope_signals[i].name << " $end" << std::endl; - fwidth += scope_signals[i].width; - } - ofs << "enddefinitions $end" << std::endl; uint64_t frame_width, max_frames, data_valid; diff --git a/driver/opae/vortex.cpp b/driver/opae/vortex.cpp index 07e0385c..e66b9afe 100755 --- a/driver/opae/vortex.cpp +++ b/driver/opae/vortex.cpp @@ -173,7 +173,7 @@ extern int vx_dev_open(vx_device_h* hdevice) { { // Load device CAPS int ret = 0; - ret |= vx_csr_get(device, 0, CSR_IMPL_ID, &device->implementation_id); + ret |= vx_csr_get(device, 0, CSR_MIMPID, &device->implementation_id); ret |= vx_csr_get(device, 0, CSR_NC, &device->num_cores); ret |= vx_csr_get(device, 0, CSR_NW, &device->num_warps); ret |= vx_csr_get(device, 0, CSR_NT, &device->num_threads); @@ -211,28 +211,29 @@ extern int vx_dev_close(vx_device_h hdevice) { vx_scope_stop(device->fpga, 0); #endif - { - // Dump performance stats +#ifdef DUMP_PERF_STATS + // Dump perf stats + if (device->num_cores > 1) { + uint64_t total_instrs = 0, total_cycles = 0; + for (unsigned core_id = 0; core_id < device->num_cores; ++core_id) { + uint64_t instrs, cycles; + int ret = vx_get_perf(hdevice, core_id, &instrs, &cycles); + assert(ret == 0); + float IPC = (float)(double(instrs) / double(cycles)); + fprintf(stdout, "PERF: core%d: instrs=%ld, cycles=%ld, IPC=%f\n", core_id, instrs, cycles, IPC); + total_instrs += instrs; + total_cycles = std::max(total_cycles, cycles); + } + float IPC = (float)(double(total_instrs) / double(total_cycles)); + fprintf(stdout, "PERF: instrs=%ld, cycles=%ld, IPC=%f\n", total_instrs, total_cycles, IPC); + } else { uint64_t instrs, cycles; - unsigned value; - - int ret = 0; - ret |= vx_csr_get(hdevice, 0, CSR_INSTR_H, &value); - instrs = value; - ret |= vx_csr_get(hdevice, 0, CSR_INSTR_L, &value); - instrs = (instrs << 32) | value; - - ret |= vx_csr_get(hdevice, 0, CSR_CYCLE_H, &value); - cycles = value; - ret |= vx_csr_get(hdevice, 0, CSR_CYCLE_L, &value); - cycles = (cycles << 32) | value; - + int ret = vx_get_perf(hdevice, 0, &instrs, &cycles); float IPC = (float)(double(instrs) / double(cycles)); - - fprintf(stdout, "PERF: instrs=%ld, cycles=%ld, IPC=%f\n", instrs, cycles, IPC); - assert(ret == 0); + fprintf(stdout, "PERF: instrs=%ld, cycles=%ld, IPC=%f\n", instrs, cycles, IPC); } +#endif fpgaClose(device->fpga); @@ -494,7 +495,7 @@ extern int vx_start(vx_device_h hdevice) { } // set device constant registers -extern int vx_csr_set(vx_device_h hdevice, int core, int address, unsigned value) { +extern int vx_csr_set(vx_device_h hdevice, int core_id, int addr, unsigned value) { if (nullptr == hdevice) return -1; @@ -505,8 +506,8 @@ extern int vx_csr_set(vx_device_h hdevice, int core, int address, unsigned value return -1; // write CSR value - CHECK_RES(fpgaWriteMMIO64(device->fpga, 0, MMIO_CSR_CORE, core)); - CHECK_RES(fpgaWriteMMIO64(device->fpga, 0, MMIO_CSR_ADDR, address)); + CHECK_RES(fpgaWriteMMIO64(device->fpga, 0, MMIO_CSR_CORE, core_id)); + CHECK_RES(fpgaWriteMMIO64(device->fpga, 0, MMIO_CSR_ADDR, addr)); CHECK_RES(fpgaWriteMMIO64(device->fpga, 0, MMIO_CSR_DATA, value)); CHECK_RES(fpgaWriteMMIO64(device->fpga, 0, MMIO_CMD_TYPE, CMD_CSR_WRITE)); @@ -514,7 +515,7 @@ extern int vx_csr_set(vx_device_h hdevice, int core, int address, unsigned value } // get device constant registers -extern int vx_csr_get(vx_device_h hdevice, int core, int address, unsigned* value) { +extern int vx_csr_get(vx_device_h hdevice, int core_id, int addr, unsigned* value) { if (nullptr == hdevice || nullptr == value) return -1; @@ -526,8 +527,8 @@ extern int vx_csr_get(vx_device_h hdevice, int core, int address, unsigned* valu // write CSR value - CHECK_RES(fpgaWriteMMIO64(device->fpga, 0, MMIO_CSR_CORE, core)); - CHECK_RES(fpgaWriteMMIO64(device->fpga, 0, MMIO_CSR_ADDR, address)); + CHECK_RES(fpgaWriteMMIO64(device->fpga, 0, MMIO_CSR_CORE, core_id)); + CHECK_RES(fpgaWriteMMIO64(device->fpga, 0, MMIO_CSR_ADDR, addr)); CHECK_RES(fpgaWriteMMIO64(device->fpga, 0, MMIO_CMD_TYPE, CMD_CSR_READ)); // Ensure ready for new command diff --git a/driver/rtlsim/Makefile b/driver/rtlsim/Makefile index d0890c4c..d3d0df94 100644 --- a/driver/rtlsim/Makefile +++ b/driver/rtlsim/Makefile @@ -13,12 +13,13 @@ DBG_PRINT_FLAGS += -DDBG_PRINT_DRAM DBG_PRINT_FLAGS += -DDBG_PRINT_PIPELINE DBG_PRINT_FLAGS += -DDBG_PRINT_OPAE -#DBG_FLAGS += $(DBG_PRINT_FLAGS) +DBG_FLAGS += $(DBG_PRINT_FLAGS) DBG_FLAGS += -DDBG_CORE_REQ_INFO #CONFIGS += -DNUM_CLUSTERS=2 -DNUM_CORES=4 -DL2_ENABLE=1 #CONFIGS += -DNUM_CLUSTERS=1 -DNUM_CORES=4 -DL2_ENABLE=1 -#CONFIGS += -DNUM_CLUSTERS=1 -DNUM_CORES=2 +#CONFIGS += -DNUM_CLUSTERS=1 -DNUM_CORES=2 -DL2_ENABLE=0 +CONFIGS += -DNUM_CLUSTERS=1 -DNUM_CORES=1 #DEBUG=1 #AFU=1 @@ -27,18 +28,23 @@ CFLAGS += -fPIC CFLAGS += -DUSE_RTLSIM $(CONFIGS) +CFLAGS += -DDUMP_PERF_STATS + LDFLAGS += -shared -pthread # LDFLAGS += -dynamiclib -pthread TOP = Vortex SRCS = vortex.cpp ../common/vx_utils.cpp ../../hw/simulate/simulator.cpp +SRCS += ../../hw/rtl/fp_cores/svdpi/float_dpi.cpp -RTL_INCLUDE = -I../../hw/rtl -I../../hw/rtl/libs -I../../hw/rtl/interfaces -I../../hw/rtl/cache +FPU_INCLUDE = -I../../hw/rtl/fp_cores -I../../hw/rtl/fp_cores/svdpi -I../../hw/rtl/fp_cores/fpnew/src/common_cells/include -I../../hw/rtl/fp_cores/fpnew/src/common_cells/src -I../../hw/rtl/fp_cores/fpnew/src/fpu_div_sqrt_mvp/hdl -I../../hw/rtl/fp_cores/fpnew/src +RTL_INCLUDE = -I../../hw/rtl -I../../hw/rtl/libs -I../../hw/rtl/interfaces -I../../hw/rtl/cache $(FPU_INCLUDE) VL_FLAGS += --language 1800-2009 --assert -Wall -Wpedantic $(CONFIGS) VL_FLAGS += -Wno-DECLFILENAME VL_FLAGS += --x-initial unique --x-assign unique +VL_FLAGS += verilator.vlt # Enable Verilator multithreaded simulation #THREADS ?= $(shell python3 -c 'import multiprocessing as mp; print(max(1, mp.cpu_count() // 2))') @@ -58,8 +64,8 @@ ifdef AFU TOP = vortex_afu_sim VL_FLAGS += -DNOPAE CFLAGS += -DNOPAE - #VL_FLAGS += -DSCOPE - #CFLAGS += -DSCOPE + VL_FLAGS += -DSCOPE + CFLAGS += -DSCOPE RTL_INCLUDE += -I../../hw/opae -I../../hw/opae/ccip endif @@ -69,7 +75,7 @@ PROJECT = libvortex.so all: $(PROJECT) $(PROJECT): $(SRCS) - verilator --exe --cc $(TOP) $(RTL_INCLUDE) $(VL_FLAGS) $(SRCS) -CFLAGS '$(CFLAGS)' -LDFLAGS '$(LDFLAGS)' -o ../$(PROJECT) + verilator --exe --cc $(TOP) --top-module $(TOP) $(RTL_INCLUDE) $(VL_FLAGS) $(SRCS) -CFLAGS '$(CFLAGS)' -LDFLAGS '$(LDFLAGS)' -o ../$(PROJECT) make -j -C obj_dir -f V$(TOP).mk clean: diff --git a/driver/rtlsim/simulator.cpp b/driver/rtlsim/simulator.cpp deleted file mode 100644 index a0b3ad5d..00000000 --- a/driver/rtlsim/simulator.cpp +++ /dev/null @@ -1,70 +0,0 @@ -#include "simulator.h" -#include -#include -#include - -uint64_t timestamp = 0; - -double sc_time_stamp() { - return timestamp; -} - -Simulator::Simulator() { - // force random values for unitialized signals - const char* args[] = {"", "+verilator+rand+reset+2", "+verilator+seed+50"}; - Verilated::commandArgs(3, args); - - vortex_ = new Vvortex_afu_sim(); - -#ifdef VCD_OUTPUT - Verilated::traceEverOn(true); - trace_ = new VerilatedVcdC; - vortex_->trace(trace_, 99); - trace_->open("trace.vcd"); -#endif -} - -Simulator::~Simulator() { -#ifdef VCD_OUTPUT - trace_->close(); -#endif - delete vortex_; -} - -void Simulator::reset() { -#ifndef NDEBUG - std::cout << timestamp << ": [sim] reset()" << std::endl; -#endif - vortex_->reset = 1; - this->step(); - vortex_->reset = 0; - - dram_rsp_vec_.clear(); -} - -void Simulator::step() { - vortex_->clk = 0; - this->eval(); - - vortex_->clk = 1; - this->eval(); - - avs_driver(); - ccip_driver(); -} - -void Simulator::eval() { - vortex_->eval(); -#ifdef VCD_OUTPUT - trace_->dump(timestamp); -#endif - ++timestamp; -} - -void Simulator::avs_driver() { - //-- -} - - void Simulator::ccip_driver() { - //-- - } \ No newline at end of file diff --git a/driver/rtlsim/simulator.h b/driver/rtlsim/simulator.h deleted file mode 100644 index 50d666d3..00000000 --- a/driver/rtlsim/simulator.h +++ /dev/null @@ -1,59 +0,0 @@ -#pragma once - -#include "Vvortex_afu_sim.h" -#include "Vvortex_afu_sim__Syms.h" -#include "verilated.h" - -#ifdef VCD_OUTPUT -#include -#endif - -#include -#include "ram.h" - -#include -#include - -#define ENABLE_DRAM_STALLS -#define DRAM_LATENCY 100 -#define DRAM_RQ_SIZE 16 -#define DRAM_STALLS_MODULO 16 - -typedef struct { - int cycles_left; - uint8_t *data; - unsigned tag; -} dram_req_t; - -class Simulator { -public: - - Simulator(); - virtual ~Simulator(); - - void reset(); - - void step(); - - int mmio_read(uint64_t addr, uint64_t* value); - - int mmio_write(uint64_t addr, uint64_t value); - -private: - - void eval(); - - void avs_driver(); - - void ccip_driver(); - - std::vector dram_rsp_vec_; - - RAM ram_; - Vvortex_afu_sim *vortex_; - - -#ifdef VCD_OUTPUT - VerilatedVcdC *trace_; -#endif -}; \ No newline at end of file diff --git a/driver/rtlsim/verilator.vlt b/driver/rtlsim/verilator.vlt new file mode 100644 index 00000000..c0cd70d7 --- /dev/null +++ b/driver/rtlsim/verilator.vlt @@ -0,0 +1,9 @@ +`verilator_config + +lint_off -rule BLKANDNBLK -file "../../hw/rtl/fp_cores/fpnew/*" +lint_off -rule UNOPTFLAT -file "../../hw/rtl/fp_cores/fpnew/*" +lint_off -rule WIDTH -file "../../hw/rtl/fp_cores/fpnew/*" +lint_off -rule UNUSED -file "../../hw/rtl/fp_cores/fpnew/*" +lint_off -rule LITENDIAN -file "../../hw/rtl/fp_cores/fpnew/*" +lint_off -rule IMPORTSTAR -file "../../hw/rtl/fp_cores/fpnew/*" +lint_off -rule PINCONNECTEMPTY -file "../../hw/rtl/fp_cores/fpnew/*" \ No newline at end of file diff --git a/driver/rtlsim/vortex.cpp b/driver/rtlsim/vortex.cpp index 51c3bb8c..788a5a9d 100644 --- a/driver/rtlsim/vortex.cpp +++ b/driver/rtlsim/vortex.cpp @@ -68,7 +68,7 @@ public: simulator_.attach_ram(&ram_); } - ~vx_device() { + ~vx_device() { if (future_.valid()) { future_.wait(); } @@ -151,6 +151,28 @@ public: return 0; } + int set_csr(int core_id, int addr, unsigned value) { + if (future_.valid()) { + future_.wait(); // ensure prior run completed + } + simulator_.set_csr(core_id, addr, value); + while (simulator_.is_busy()) { + simulator_.step(); + }; + return 0; + } + + int get_csr(int core_id, int addr, unsigned *value) { + if (future_.valid()) { + future_.wait(); // ensure prior run completed + } + simulator_.get_csr(core_id, addr, value); + while (simulator_.is_busy()) { + simulator_.step(); + }; + return 0; + } + private: size_t mem_allocation_; @@ -213,6 +235,29 @@ extern int vx_dev_close(vx_device_h hdevice) { return -1; vx_device *device = ((vx_device*)hdevice); + +#ifdef DUMP_PERF_STATS + unsigned num_cores; + vx_csr_get(hdevice, 0, CSR_NC, &num_cores); + if (num_cores > 1) { + uint64_t total_instrs = 0, total_cycles = 0; + for (unsigned core_id = 0; core_id < num_cores; ++core_id) { + uint64_t instrs, cycles; + vx_get_perf(hdevice, core_id, &instrs, &cycles); + float IPC = (float)(double(instrs) / double(cycles)); + fprintf(stdout, "PERF: core%d: instrs=%ld, cycles=%ld, IPC=%f\n", core_id, instrs, cycles, IPC); + total_instrs += instrs; + total_cycles = std::max(total_cycles, cycles); + } + float IPC = (float)(double(total_instrs) / double(total_cycles)); + fprintf(stdout, "PERF: instrs=%ld, cycles=%ld, IPC=%f\n", total_instrs, total_cycles, IPC); + } else { + uint64_t instrs, cycles; + vx_get_perf(hdevice, 0, &instrs, &cycles); + float IPC = (float)(double(instrs) / double(cycles)); + fprintf(stdout, "PERF: instrs=%ld, cycles=%ld, IPC=%f\n", instrs, cycles, IPC); + } +#endif delete device; @@ -322,3 +367,21 @@ extern int vx_ready_wait(vx_device_h hdevice, long long timeout) { return device->wait(timeout); } + +extern int vx_csr_set(vx_device_h hdevice, int core_id, int addr, unsigned value) { + if (nullptr == hdevice) + return -1; + + vx_device *device = ((vx_device*)hdevice); + + return device->set_csr(core_id, addr, value); +} + +extern int vx_csr_get(vx_device_h hdevice, int core_id, int addr, unsigned* value) { + if (nullptr == hdevice) + return -1; + + vx_device *device = ((vx_device*)hdevice); + + return device->get_csr(core_id, addr, value); +} \ No newline at end of file diff --git a/driver/simx/vortex.cpp b/driver/simx/vortex.cpp index 981ca5c1..b499803d 100644 --- a/driver/simx/vortex.cpp +++ b/driver/simx/vortex.cpp @@ -357,3 +357,11 @@ extern int vx_ready_wait(vx_device_h hdevice, long long timeout) { return device->wait(timeout); } + +extern int vx_csr_set(vx_device_h /*hdevice*/, int /*core_id*/, int /*addr*/, unsigned /*value*/) { + return -1; +} + +extern int vx_csr_get(vx_device_h /*hdevice*/, int /*core_id*/, int /*addr*/, unsigned* /*value*/) { + return -1; +} \ No newline at end of file diff --git a/driver/stub/vortex.cpp b/driver/stub/vortex.cpp index 532e64d7..f4a101f0 100644 --- a/driver/stub/vortex.cpp +++ b/driver/stub/vortex.cpp @@ -47,3 +47,11 @@ extern int vx_start(vx_device_h /*hdevice*/) { extern int vx_ready_wait(vx_device_h /*hdevice*/, long long /*timeout*/) { return -1; } + +extern int vx_csr_set(vx_device_h /*hdevice*/, int /*core_id*/, int /*addr*/, unsigned /*value*/) { + return -1; +} + +extern int vx_csr_get(vx_device_h /*hdevice*/, int /*core_id*/, int /*addr*/, unsigned* /*value*/) { + return -1; +} \ No newline at end of file diff --git a/driver/tests/Makefile b/driver/tests/Makefile new file mode 100644 index 00000000..989b3690 --- /dev/null +++ b/driver/tests/Makefile @@ -0,0 +1,15 @@ +all: + $(MAKE) -C basic + $(MAKE) -C demo + $(MAKE) -C dogfood + +run: + $(MAKE) -C basic run-rtlsim + $(MAKE) -C demo run-rtlsim + $(MAKE) -C dogfood run-rtlsim + +clean: + $(MAKE) -C basic clean + $(MAKE) -C demo clean + $(MAKE) -C dogfood clean + diff --git a/driver/tests/basic/Makefile b/driver/tests/basic/Makefile index a3792edc..2edd71cf 100644 --- a/driver/tests/basic/Makefile +++ b/driver/tests/basic/Makefile @@ -1,6 +1,8 @@ RISCV_TOOLCHAIN_PATH ?= $(wildcard ~/dev/riscv-gnu-toolchain/drops) VORTEX_RT_PATH ?= $(wildcard ../../../runtime) +OPTS ?= -n256 + VX_CC = $(RISCV_TOOLCHAIN_PATH)/bin/riscv32-unknown-elf-gcc VX_CXX = $(RISCV_TOOLCHAIN_PATH)/bin/riscv32-unknown-elf-g++ VX_DP = $(RISCV_TOOLCHAIN_PATH)/bin/riscv32-unknown-elf-objdump @@ -38,16 +40,16 @@ $(PROJECT): $(SRCS) $(CXX) $(CXXFLAGS) $^ $(LDFLAGS) -L../../stub -lvortex -o $@ run-fpga: $(PROJECT) - LD_LIBRARY_PATH=../../opae:$(LD_LIBRARY_PATH) ./$(PROJECT) -n 256 + LD_LIBRARY_PATH=../../opae:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) run-ase: $(PROJECT) - ASE_LOG=0 LD_LIBRARY_PATH=../../opae/ase:$(LD_LIBRARY_PATH) ./$(PROJECT) -n 256 + ASE_LOG=0 LD_LIBRARY_PATH=../../opae/ase:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) run-rtlsim: $(PROJECT) - LD_LIBRARY_PATH=../../rtlsim:$(LD_LIBRARY_PATH) ./$(PROJECT) -n 256 + LD_LIBRARY_PATH=../../rtlsim:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) run-simx: $(PROJECT) - LD_LIBRARY_PATH=../../simx:$(LD_LIBRARY_PATH) ./$(PROJECT) -n 256 + LD_LIBRARY_PATH=../../simx:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) .depend: $(SRCS) $(CXX) $(CXXFLAGS) -MM $^ > .depend; diff --git a/driver/tests/basic/basic.cpp b/driver/tests/basic/basic.cpp index 92a785f4..69ba7d12 100755 --- a/driver/tests/basic/basic.cpp +++ b/driver/tests/basic/basic.cpp @@ -14,6 +14,8 @@ exit(-1); \ } while (false) +/////////////////////////////////////////////////////////////////////////////// + const char* kernel_file = "kernel.bin"; int test = -1; uint32_t count = 0; @@ -153,7 +155,7 @@ int run_kernel_test(const kernel_arg_t& kernel_arg, int32_t curr = ((int32_t*)vx_host_ptr(buffer))[i]; int32_t ref = i; if (curr != ref) { - std::cout << "error at value " << i + std::cout << "error at result #" << i << ": actual 0x" << curr << ", expected 0x" << ref << std::endl; ++errors; } @@ -236,7 +238,7 @@ int main(int argc, char *argv[]) { std::cout << "cleanup" << std::endl; cleanup(); - std::cout << "Test PASSED" << std::endl; - + std::cout << "Test PASSED" << std::endl; + return 0; } diff --git a/driver/tests/demo/Makefile b/driver/tests/demo/Makefile index 0368e5b3..348e5d11 100644 --- a/driver/tests/demo/Makefile +++ b/driver/tests/demo/Makefile @@ -1,6 +1,8 @@ RISCV_TOOLCHAIN_PATH ?= $(wildcard ~/dev/riscv-gnu-toolchain/drops) VORTEX_RT_PATH ?= $(wildcard ../../../runtime) +OPTS ?= -n64 + VX_CC = $(RISCV_TOOLCHAIN_PATH)/bin/riscv32-unknown-elf-gcc VX_CXX = $(RISCV_TOOLCHAIN_PATH)/bin/riscv32-unknown-elf-g++ VX_DP = $(RISCV_TOOLCHAIN_PATH)/bin/riscv32-unknown-elf-objdump @@ -36,16 +38,16 @@ $(PROJECT): $(SRCS) $(CXX) $(CXXFLAGS) $^ $(LDFLAGS) -L../../stub -lvortex -o $@ run-fpga: $(PROJECT) - LD_LIBRARY_PATH=../../opae:$(LD_LIBRARY_PATH) ./$(PROJECT) -n 16 + LD_LIBRARY_PATH=../../opae:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) run-ase: $(PROJECT) - ASE_LOG=0 LD_LIBRARY_PATH=../../opae/ase:$(LD_LIBRARY_PATH) ./$(PROJECT) -n 16 + ASE_LOG=0 LD_LIBRARY_PATH=../../opae/ase:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) run-rtlsim: $(PROJECT) - LD_LIBRARY_PATH=../../rtlsim:$(LD_LIBRARY_PATH) ./$(PROJECT) -n 16 + LD_LIBRARY_PATH=../../rtlsim:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) run-simx: $(PROJECT) - LD_LIBRARY_PATH=../../simx:$(LD_LIBRARY_PATH) ./$(PROJECT) -n 16 + LD_LIBRARY_PATH=../../simx:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) .depend: $(SRCS) $(CXX) $(CXXFLAGS) -MM $^ > .depend; diff --git a/driver/tests/demo/demo.cpp b/driver/tests/demo/demo.cpp index 2d5b47f8..1a2a62af 100644 --- a/driver/tests/demo/demo.cpp +++ b/driver/tests/demo/demo.cpp @@ -14,6 +14,8 @@ exit(-1); \ } while (false) +/////////////////////////////////////////////////////////////////////////////// + const char* kernel_file = "kernel.bin"; uint32_t count = 0; @@ -84,7 +86,7 @@ int run_test(const kernel_arg_t& kernel_arg, int ref = i + i; int cur = buf_ptr[i]; if (cur != ref) { - std::cout << "error at value " << i + std::cout << "error at result #" << i << ": actual 0x" << cur << ", expected 0x" << ref << std::endl; ++errors; } diff --git a/driver/tests/demo/kernel.bin b/driver/tests/demo/kernel.bin old mode 100644 new mode 100755 index 06939d4c..280e5cbc Binary files a/driver/tests/demo/kernel.bin and b/driver/tests/demo/kernel.bin differ diff --git a/driver/tests/demo/kernel.dump b/driver/tests/demo/kernel.dump index b5496825..dcedb988 100644 --- a/driver/tests/demo/kernel.dump +++ b/driver/tests/demo/kernel.dump @@ -97,7 +97,7 @@ Disassembly of section .text: 80000134: 0005006b 0x5006b 80000138: 00002197 auipc gp,0x2 8000013c: d3818193 addi gp,gp,-712 # 80001e70 <__global_pointer$> -80000140: f14025f3 csrr a1,mhartid +80000140: 022025f3 csrr a1,0x22 80000144: 00a59593 slli a1,a1,0xa 80000148: 02002673 csrr a2,0x20 8000014c: 00261613 slli a2,a2,0x2 @@ -145,7 +145,7 @@ Disassembly of section .text: 800001ac: 00008067 ret 800001b0 : -800001b0: f1402573 csrr a0,mhartid +800001b0: 02202573 csrr a0,0x22 800001b4: 00008067 ret 800001b8 : diff --git a/driver/tests/demo/kernel.elf b/driver/tests/demo/kernel.elf index d91b509c..f7681ea2 100755 Binary files a/driver/tests/demo/kernel.elf and b/driver/tests/demo/kernel.elf differ diff --git a/driver/tests/dogfood/Makefile b/driver/tests/dogfood/Makefile new file mode 100644 index 00000000..b1fcb076 --- /dev/null +++ b/driver/tests/dogfood/Makefile @@ -0,0 +1,64 @@ +RISCV_TOOLCHAIN_PATH ?= $(wildcard ~/dev/riscv-gnu-toolchain/drops) +VORTEX_RT_PATH ?= $(wildcard ../../../runtime) + +OPTS ?= -n64 + +VX_CC = $(RISCV_TOOLCHAIN_PATH)/bin/riscv32-unknown-elf-gcc +VX_CXX = $(RISCV_TOOLCHAIN_PATH)/bin/riscv32-unknown-elf-g++ +VX_DP = $(RISCV_TOOLCHAIN_PATH)/bin/riscv32-unknown-elf-objdump +VX_CP = $(RISCV_TOOLCHAIN_PATH)/bin/riscv32-unknown-elf-objcopy + +VX_CFLAGS += -march=rv32imf -mabi=ilp32 -O3 -Wl,-Bstatic,-T,$(VORTEX_RT_PATH)/linker/vx_link.ld -nostartfiles -Wl,--gc-sections +VX_CFLAGS += -I$(VORTEX_RT_PATH)/include + +VX_LDFLAGS += $(VORTEX_RT_PATH)/libvortexrt.a +VX_LDFLAGS += -lm + +VX_SRCS = kernel.c + +CXXFLAGS += -std=c++11 -O0 -g -Wall -Wextra -pedantic -Wfatal-errors + +CXXFLAGS += -I../../include -I../../../hw + +PROJECT = dogfood + +SRCS = dogfood.cpp + +all: $(PROJECT) kernel.bin kernel.dump + +kernel.dump: kernel.elf + $(VX_DP) -D kernel.elf > kernel.dump + +kernel.bin: kernel.elf + $(VX_CP) -O binary kernel.elf kernel.bin + +kernel.elf: $(VX_SRCS) + $(VX_CC) $(VX_CFLAGS) $(VX_SRCS) $(VX_LDFLAGS) -o kernel.elf + +$(PROJECT): $(SRCS) + $(CXX) $(CXXFLAGS) $^ $(LDFLAGS) -L../../stub -lvortex -o $@ + +run-fpga: $(PROJECT) + LD_LIBRARY_PATH=../../opae:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) + +run-ase: $(PROJECT) + ASE_LOG=0 LD_LIBRARY_PATH=../../opae/ase:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) + +run-rtlsim: $(PROJECT) + LD_LIBRARY_PATH=../../rtlsim:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) + +run-simx: $(PROJECT) + LD_LIBRARY_PATH=../../simx:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) + +.depend: $(SRCS) + $(CXX) $(CXXFLAGS) -MM $^ > .depend; + +clean: + rm -rf $(PROJECT) *.o .depend + +clean-all: + rm -rf $(PROJECT) *.o *.elf *.bin *.dump .depend + +ifneq ($(MAKECMDGOALS),clean) + -include .depend +endif \ No newline at end of file diff --git a/driver/tests/dogfood/Memcpy/hw/rtl/_hdr b/driver/tests/dogfood/Memcpy/hw/rtl/_hdr deleted file mode 100644 index 39a1dd9e..00000000 --- a/driver/tests/dogfood/Memcpy/hw/rtl/_hdr +++ /dev/null @@ -1,603 +0,0 @@ -// -// Copyright (c) 2017, Intel Corporation -// All rights reserved. -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions are met: -// -// Redistributions of source code must retain the above copyright notice, this -// list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright notice, -// this list of conditions and the following disclaimer in the documentation -// and/or other materials provided with the distribution. -// -// Neither the name of the Intel Corporation nor the names of its contributors -// may be used to endorse or promote products derived from this software -// without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE -// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -// POSSIBILITY OF SUCH DAMAGE. - - -// Read from the memory locations first and then write to the memory locations - -`include "platform_if.vh" -`include "afu_json_info.vh" - - -module ccip_std_afu - ( - // CCI-P Clocks and Resets - input logic pClk, // 400MHz - CCI-P clock domain. Primary interface clock - input logic pClkDiv2, // 200MHz - CCI-P clock domain. - input logic pClkDiv4, // 100MHz - CCI-P clock domain. - input logic uClk_usr, // User clock domain. Refer to clock programming guide ** Currently provides fixed 300MHz clock ** - input logic uClk_usrDiv2, // User clock domain. Half the programmed frequency ** Currently provides fixed 150MHz clock ** - input logic pck_cp2af_softReset, // CCI-P ACTIVE HIGH Soft Reset - input logic [1:0] pck_cp2af_pwrState, // CCI-P AFU Power State - input logic pck_cp2af_error, // CCI-P Protocol Error Detected - - // Interface structures - input t_if_ccip_Rx pck_cp2af_sRx, // CCI-P Rx Port - output t_if_ccip_Tx pck_af2cp_sTx // CCI-P Tx Port - ); - - - // - // Run the entire design at the standard CCI-P frequency (400 MHz). - // - logic clk; - assign clk = pClk; - - logic reset; - assign reset = pck_cp2af_softReset; - - logic [511:0] wr_data; - logic [511:0] rd_data; - - logic get_write_addr; - logic do_update; - logic rd_end_of_list; - logic rd_needed; - logic wr_needed; - logic [15:0] cnt_list_length; - - // ========================================================================= - // - // Register requests. - // - // ========================================================================= - - // - // The incoming pck_cp2af_sRx and outgoing pck_af2cp_sTx must both be - // registered. Here we register pck_cp2af_sRx and assign it to sRx. - // We also assign pck_af2cp_sTx to sTx here but don't register it. - // The code below never uses combinational logic to write sTx. - // - - t_if_ccip_Rx sRx; - always_ff @(posedge clk) - begin - sRx <= pck_cp2af_sRx; - end - - t_if_ccip_Tx sTx; - assign pck_af2cp_sTx = sTx; - - - // ========================================================================= - // - // CSR (MMIO) handling. - // - // ========================================================================= - - // The AFU ID is a unique ID for a given program. Here we generated - // one with the "uuidgen" program and stored it in the AFU's JSON file. - // ASE and synthesis setup scripts automatically invoke afu_json_mgr - // to extract the UUID into afu_json_info.vh. - logic [127:0] afu_id = `AFU_ACCEL_UUID; - - // - // A valid AFU must implement a device feature list, starting at MMIO - // address 0. Every entry in the feature list begins with 5 64-bit - // words: a device feature header, two AFU UUID words and two reserved - // words. - // - - // Is a CSR read request active this cycle? - logic is_csr_read; - assign is_csr_read = sRx.c0.mmioRdValid; - - // Is a CSR write request active this cycle? - logic is_csr_write; - assign is_csr_write = sRx.c0.mmioWrValid; - - // The MMIO request header is overlayed on the normal c0 memory read - // response data structure. Cast the c0Rx header to an MMIO request - // header. - t_ccip_c0_ReqMmioHdr mmio_req_hdr; - assign mmio_req_hdr = t_ccip_c0_ReqMmioHdr'(sRx.c0.hdr); - - - // - // Implement the device feature list by responding to MMIO reads. - // - - always_ff @(posedge clk) - begin - if (reset) - begin - sTx.c2.mmioRdValid <= 1'b0; - end - else - begin - // Always respond with something for every read request - sTx.c2.mmioRdValid <= is_csr_read; - - // The unique transaction ID matches responses to requests - sTx.c2.hdr.tid <= mmio_req_hdr.tid; - - // Addresses are of 32-bit objects in MMIO space. Addresses - // of 64-bit objects are thus multiples of 2. - case (mmio_req_hdr.address) - 0: // AFU DFH (device feature header) - begin - // Here we define a trivial feature list. In this - // example, our AFU is the only entry in this list. - sTx.c2.data <= t_ccip_mmioData'(0); - // Feature type is AFU - sTx.c2.data[63:60] <= 4'h1; - // End of list (last entry in list) - sTx.c2.data[40] <= 1'b1; - end - - // AFU_ID_L - 2: sTx.c2.data <= afu_id[63:0]; - - // AFU_ID_H - 4: sTx.c2.data <= afu_id[127:64]; - - // DFH_RSVD0 - 6: sTx.c2.data <= t_ccip_mmioData'(0); - - // DFH_RSVD1 - 8: sTx.c2.data <= t_ccip_mmioData'(0); - - default: sTx.c2.data <= t_ccip_mmioData'(0); - endcase - end - end - - - // - // CSR write handling. Host software must tell the AFU the memory address - // to which it should be writing. The address is set by writing a CSR. - // - - // We use MMIO address 0 to set the memory address. The read and - // write MMIO spaces are logically separate so we are free to use - // whatever we like. This may not be good practice for cleanly - // organizing the MMIO address space, but it is legal. - logic is_mem_addr_csr_write; - assign is_mem_addr_csr_write = get_write_addr && is_csr_write && - (mmio_req_hdr.address == t_ccip_mmioAddr'(0)); - - // Memory address to which this AFU will write. - t_ccip_clAddr write_mem_addr; - - always_ff @(posedge clk) - begin - if (reset) - begin - get_write_addr <= 1'b1; - end - else if (is_mem_addr_csr_write) - begin - write_mem_addr <= t_ccip_clAddr'(sRx.c0.data); - get_write_addr <= 1'b0; - end - end - - - // We use MMIO address 0 to set the memory address for reading data. - logic is_mem_addr_csr_read; - assign is_mem_addr_csr_read = !get_write_addr && is_csr_write && - (mmio_req_hdr.address == t_ccip_mmioAddr'(0)); - - // Memory address from which this AFU will read. - logic start_read; - t_ccip_clAddr read_mem_addr; - - //logic start_traversal = 'b0; - //t_ccip_clAddr start_traversal_addr; - - always_ff @(posedge clk) - begin - if (reset) - begin - start_read <= 1'b0; - end - else if (is_mem_addr_csr_read) - begin - read_mem_addr <= t_ccip_clAddr'(sRx.c0.data); - start_read <= 'b1; - end - end - - - // ========================================================================= - // - // Main AFU logic - // - // ========================================================================= - - // - // States in our simple example. - // - //typedef enum logic [0:0] - typedef enum logic [1:0] - { - STATE_IDLE, - STATE_READ, - STATE_UPDATE, - STATE_WRITE - } - t_state; - - t_state state; - - // - // State machine - // - always_ff @(posedge clk) - begin - if (reset) - begin - state <= STATE_IDLE; - rd_end_of_list <= 1'b0; - end - else - begin - case (state) - STATE_IDLE: - begin - // Traversal begins when CSR 1 is written - if (start_read) - begin - state <= STATE_READ; - $display("AFU starting traversal at 0x%x", t_ccip_clAddr'(read_mem_addr)); - end - end - - STATE_READ: - begin - if (rd_needed) - begin - // Read data from the address and update address - state <= STATE_UPDATE; - start_read <= 'b0; - $display("AFU reading data and pointing to next read address..."); - end - end - - STATE_UPDATE: - begin - // Update the read value to be written back - if (do_update) - begin - state <= STATE_WRITE; - $display("AFU performing comutations on the read values..."); - end - end - - STATE_WRITE: - begin - // Write the updated value to the address - // Point to new address after that - // if done then point to IDLE; else read new values - if (rd_end_of_list) - begin - state <= STATE_IDLE; - $display("AFU done..."); - end - else - begin - if (wr_needed) - begin - state <= STATE_READ; - $display("AFU reading again from read address..."); - end - end - end - endcase - end - end - - - // ========================================================================= - // - // Read logic. - // - // ========================================================================= - - // - // READ REQUEST - // - - // Did a write response just arrive - logic addr_next_valid; - - // Next read address - t_ccip_clAddr addr_next; - - always_ff @(posedge clk) - begin - // Next read address is valid when we have got the write response back - // and channel is not full - //addr_next_valid <= sRx.c0TxAlmFull; - addr_next_valid <= sRx.c1.rspValid; - - // Next address is current address plus address length - // Apurve - //addr_next <= addr_next + addr_size; - addr_next <= addr_next + 0; - - // End of list reached if we have read 10 times - rd_end_of_list <= (cnt_list_length == 'h10); - end - - // - // Since back pressure may prevent an immediate read request, we must - // record whether a read is needed and hold it until the request can - // be sent to the FIU. - // - t_ccip_clAddr rd_addr; - - always_ff @(posedge clk) - begin - if (reset) - begin - rd_needed <= 1'b0; - end - else - begin - // If reads are allowed this cycle then we can safely clear - // any previously requested reads. This simple AFU has only - // one read in flight at a time since it is walking a pointer - // chain. - if (rd_needed) - begin - rd_needed <= sRx.c0TxAlmFull; - end - else - begin - // Need a read under two conditions: - // - Starting a new walk - // - A read response just arrived from a line containing - // a next pointer. - rd_needed <= (start_read || (addr_next_valid && ! rd_end_of_list)); - rd_addr <= (start_read ? read_mem_addr : addr_next); - end - end - end - - // - // Emit read requests to the FIU. - // - - // Read header defines the request to the FIU - t_cci_c0_ReqMemHdr rd_hdr; - - always_comb - begin - rd_hdr = t_cci_c0_ReqMemHdr'(0); - - // Read request type - rd_hdr.req_type = eREQ_RDLINE_I; - // Virtual address (MPF virtual addressing is enabled) - rd_hdr.address = rd_addr; - // Let the FIU pick the channel - rd_hdr.vc_sel = eVC_VA; - // Read 4 lines (the size of an entry in the list) - rd_hdr.cl_len = eCL_LEN_4; - end - - // Send read requests to the FIU - always_ff @(posedge clk) - begin - if (reset) - begin - sTx.c0.valid <= 1'b0; - cnt_list_length <= 0; - end - else - begin - // Generate a read request when needed and the FIU isn't full - sTx.c0.valid <= (rd_needed && ! sRx.c0TxAlmFull); - sTx.c0.hdr <= rd_hdr; - - if (rd_needed && ! sRx.c0TxAlmFull) - begin - cnt_list_length <= cnt_list_length + 1; - //$display(" Reading from VA 0x%x", clAddrToByteAddr(rd_addr)); - $display("Incrementing read count..."); - end - end - end - - // - // READ RESPONSE HANDLING - // - - // - // Receive data (read responses). - // - always_ff @(posedge clk) - begin - if (reset) - begin - do_update <= 1'b0; - end - else - begin - if (state == STATE_READ) - begin - rd_data <= sRx.c0.data; - do_update <= 1'b1; - end - if (state == STATE_UPDATE) - begin - // Update the read data and put it in the write data to be written - wr_data <= rd_data + 1; - do_update <= 1'b0; - end - end - end - - - // ========================================================================= - // - // Write logic. - // - // ========================================================================= - - - // - // WRITE REQUEST - // - - // Did a write response just arrive - logic wr_addr_next_valid; - - // Next write address - t_ccip_clAddr wr_addr_next; - - always_ff @(posedge clk) - begin - // Next write address is valid when we have got the read response back - // and channel is not full - //wr_addr_next_valid <= sRx.c1TxAlmFull; - wr_addr_next_valid <= sRx.c0.rspValid; - - // Next address is current address plus address length - // Apurve - //wr_addr_next <= wr_addr_next + addr_size; - wr_addr_next <= wr_addr_next + 0; - end - - // - // Since back pressure may prevent an immediate write request, we must - // record whether a write is needed and hold it until the request can - // be sent to the FIU. - // - t_ccip_clAddr wr_addr; - - always_ff @(posedge clk) - begin - if (reset) - begin - wr_needed <= 1'b0; - end - else - begin - // If writes are allowed this cycle then we can safely clear - // any previously requested writes. This simple AFU has only - // one write in flight at a time since it is walking a pointer - // chain. - if (wr_needed) - begin - wr_needed <= sRx.c1TxAlmFull; - end - else - begin - // Need a write under two conditions: - // - Starting a new walk - // - A write response just arrived from a line containing - // a next pointer. - //wr_needed <= (start_write || (wr_addr_next_valid && ! rd_end_of_list)); - wr_needed <= (start_write || wr_addr_next_valid); - wr_addr <= (start_write ? write_mem_addr : wr_addr_next); - end - end - end - - // - // Emit write requests to the FIU. - // - - // Write header defines the request to the FIU - t_ccip_c1_ReqMemHdr wr_hdr; - - always_comb - begin - wr_hdr = t_cci_c1_ReqMemHdr'(0); - - // Write request type - wr_hdr.req_type = eREQ_RDLINE_I; - // Virtual address (MPF virtual addressing is enabled) - wr_hdr.address = wr_addr; - // Let the FIU pick the channel - wr_hdr.vc_sel = eVC_VA; - // Write 4 lines (the size of an entry in the list) - wr_hdr.cl_len = eCL_LEN_4; - // Start of packet is true (single line write) - wr_hdr.sop = 1'b1; - end - - // Send write requests to the FIU - always_ff @(posedge clk) - begin - if (reset) - begin - sTx.c1.valid <= 1'b0; - //cnt_list_length <= 0; - end - else - begin - // Generate a write request when needed and the FIU isn't full - sTx.c1.valid <= (wr_needed && ! sRx.c1TxAlmFull); - sTx.c1.hdr <= wr_hdr; - sTx.c1.data = t_ccip_clData'(wr_data); - - //if (wr_needed && ! sRx.c1TxAlmFull) - //begin - // cnt_list_length <= cnt_list_length + 1; - // //$display(" Writing from VA 0x%x", clAddrToByteAddr(rd_addr)); - // $display("Incrementing write count..."); - //end - end - end - - // - // WRITE RESPONSE HANDLING - // - - // Apurve: Check if a signal is to be sent to read to start reading in case - // write response does not work - // - // Send data (write requests). - // - //always_ff @(posedge clk) - //begin - // if (state == STATE_WRITE) - // begin - // rd_data <= sRx.c0.data; - // end - // if (state == STATE_UPDATE) - // begin - // // Update the write data and put it in the write data to be written - // wr_data <= rd_data + 1; - // end - //end - -endmodule diff --git a/driver/tests/dogfood/Memcpy/hw/rtl/cci_hello.json b/driver/tests/dogfood/Memcpy/hw/rtl/cci_hello.json deleted file mode 100644 index 85d7a529..00000000 --- a/driver/tests/dogfood/Memcpy/hw/rtl/cci_hello.json +++ /dev/null @@ -1,18 +0,0 @@ -{ - "version": 1, - "afu-image": { - "power": 0, - "afu-top-interface": - { - "name": "ccip_std_afu" - }, - "accelerator-clusters": - [ - { - "name": "cci_hello", - "total-contexts": 1, - "accelerator-type-uuid": "c6aa954a-9b91-4a37-abc1-1d9f0709dcc3" - } - ] - } -} diff --git a/driver/tests/dogfood/Memcpy/hw/rtl/cci_hello_afu.sv b/driver/tests/dogfood/Memcpy/hw/rtl/cci_hello_afu.sv deleted file mode 100644 index eaee72da..00000000 --- a/driver/tests/dogfood/Memcpy/hw/rtl/cci_hello_afu.sv +++ /dev/null @@ -1,653 +0,0 @@ -// -// Copyright (c) 2017, Intel Corporation -// All rights reserved. -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions are met: -// -// Redistributions of source code must retain the above copyright notice, this -// list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright notice, -// this list of conditions and the following disclaimer in the documentation -// and/or other materials provided with the distribution. -// -// Neither the name of the Intel Corporation nor the names of its contributors -// may be used to endorse or promote products derived from this software -// without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE -// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -// POSSIBILITY OF SUCH DAMAGE. - - -// Read from the memory locations first and then write to the memory locations - -`include "platform_if.vh" -`include "afu_json_info.vh" - - -module ccip_std_afu - ( - // CCI-P Clocks and Resets - input logic pClk, // 400MHz - CCI-P clock domain. Primary interface clock - input logic pClkDiv2, // 200MHz - CCI-P clock domain. - input logic pClkDiv4, // 100MHz - CCI-P clock domain. - input logic uClk_usr, // User clock domain. Refer to clock programming guide ** Currently provides fixed 300MHz clock ** - input logic uClk_usrDiv2, // User clock domain. Half the programmed frequency ** Currently provides fixed 150MHz clock ** - input logic pck_cp2af_softReset, // CCI-P ACTIVE HIGH Soft Reset - input logic [1:0] pck_cp2af_pwrState, // CCI-P AFU Power State - input logic pck_cp2af_error, // CCI-P Protocol Error Detected - - // Interface structures - input t_if_ccip_Rx pck_cp2af_sRx, // CCI-P Rx Port - output t_if_ccip_Tx pck_af2cp_sTx // CCI-P Tx Port - ); - - - // - // Run the entire design at the standard CCI-P frequency (400 MHz). - // - logic clk; - assign clk = pClk; - - logic reset; - assign reset = pck_cp2af_softReset; - - logic [511:0] wr_data; - logic [511:0] rd_data; - - logic do_update; - logic start_read; - logic start_write; - logic wr_addr_next_valid; - logic addr_next_valid; - logic rd_end_of_list; - logic rd_needed; - logic wr_needed; - logic read_req; - logic write_req; - logic [15:0] cnt_list_length; - t_ccip_clAddr rd_addr; - t_ccip_clAddr wr_addr; - t_ccip_clAddr addr_next; - t_ccip_clAddr wr_addr_next; - - // ========================================================================= - // - // Register requests. - // - // ========================================================================= - - // - // The incoming pck_cp2af_sRx and outgoing pck_af2cp_sTx must both be - // registered. Here we register pck_cp2af_sRx and assign it to sRx. - // We also assign pck_af2cp_sTx to sTx here but don't register it. - // The code below never uses combinational logic to write sTx. - // - - t_if_ccip_Rx sRx; - always_ff @(posedge clk) - begin - sRx <= pck_cp2af_sRx; - end - - t_if_ccip_Tx sTx; - assign pck_af2cp_sTx = sTx; - - - // ========================================================================= - // - // CSR (MMIO) handling. - // - // ========================================================================= - - // The AFU ID is a unique ID for a given program. Here we generated - // one with the "uuidgen" program and stored it in the AFU's JSON file. - // ASE and synthesis setup scripts automatically invoke afu_json_mgr - // to extract the UUID into afu_json_info.vh. - logic [127:0] afu_id = `AFU_ACCEL_UUID; - - // - // A valid AFU must implement a device feature list, starting at MMIO - // address 0. Every entry in the feature list begins with 5 64-bit - // words: a device feature header, two AFU UUID words and two reserved - // words. - // - - // Is a CSR read request active this cycle? - logic is_csr_read; - assign is_csr_read = sRx.c0.mmioRdValid; - - // Is a CSR write request active this cycle? - logic is_csr_write; - assign is_csr_write = sRx.c0.mmioWrValid; - - // The MMIO request header is overlayed on the normal c0 memory read - // response data structure. Cast the c0Rx header to an MMIO request - // header. - t_ccip_c0_ReqMmioHdr mmio_req_hdr; - assign mmio_req_hdr = t_ccip_c0_ReqMmioHdr'(sRx.c0.hdr); - - - // - // Implement the device feature list by responding to MMIO reads. - // - - always_ff @(posedge clk) - begin - if (reset) - begin - sTx.c2.mmioRdValid <= 1'b0; - end - else - begin - // Always respond with something for every read request - sTx.c2.mmioRdValid <= is_csr_read; - - // The unique transaction ID matches responses to requests - sTx.c2.hdr.tid <= mmio_req_hdr.tid; - - // Addresses are of 32-bit objects in MMIO space. Addresses - // of 64-bit objects are thus multiples of 2. - case (mmio_req_hdr.address) - 0: // AFU DFH (device feature header) - begin - // Here we define a trivial feature list. In this - // example, our AFU is the only entry in this list. - sTx.c2.data <= t_ccip_mmioData'(0); - // Feature type is AFU - sTx.c2.data[63:60] <= 4'h1; - // End of list (last entry in list) - sTx.c2.data[40] <= 1'b1; - end - - // AFU_ID_L - 2: sTx.c2.data <= afu_id[63:0]; - - // AFU_ID_H - 4: sTx.c2.data <= afu_id[127:64]; - - // DFH_RSVD0 - 6: sTx.c2.data <= t_ccip_mmioData'(0); - - // DFH_RSVD1 - 8: sTx.c2.data <= t_ccip_mmioData'(0); - - // Updated by apurve to check fpgaReadMMIO - 10: sTx.c2.data <= t_ccip_mmioData'(start_read); - - default: sTx.c2.data <= t_ccip_mmioData'(0); - endcase - end - end - - - // - // CSR write handling. Host software must tell the AFU the memory address - // to which it should be writing. The address is set by writing a CSR. - // - - // We use MMIO address 0 to set the memory address. The read and - // write MMIO spaces are logically separate so we are free to use - // whatever we like. This may not be good practice for cleanly - // organizing the MMIO address space, but it is legal. - logic is_mem_addr_csr_write; - assign is_mem_addr_csr_write = is_csr_write && - (mmio_req_hdr.address == t_ccip_mmioAddr'(0)); - - // Memory address to which this AFU will write. - t_ccip_clAddr write_mem_addr; - - always_ff @(posedge clk) - begin - if (reset) - begin - start_write <= 1'b0; - end - else if (is_mem_addr_csr_write) - begin - write_mem_addr <= t_ccip_clAddr'(sRx.c0.data); - start_write <= 1'b1; - //$display("Write mem address is 0x%x", t_ccip_clAddr'(write_mem_addr)); - end - end - - - // We use MMIO address 8 to set the memory address for reading data. - logic is_mem_addr_csr_read; - assign is_mem_addr_csr_read = is_csr_write && - (mmio_req_hdr.address == t_ccip_mmioAddr'(2)); - - // Memory address from which this AFU will read. - t_ccip_clAddr read_mem_addr; - - //logic start_traversal = 'b0; - //t_ccip_clAddr start_traversal_addr; - - always_ff @(posedge clk) - begin - if (reset) - begin - start_read <= 1'b0; - end - else if (is_mem_addr_csr_read) - begin - read_mem_addr <= t_ccip_clAddr'(sRx.c0.data); - start_read <= 1'b1; - //$display("Read mem address is 0x%x", t_ccip_clAddr'(read_mem_addr)); - end - end - - - // ========================================================================= - // - // Main AFU logic - // - // ========================================================================= - - // - // States in our simple example. - // - //typedef enum logic [0:0] - typedef enum logic [1:0] - { - STATE_IDLE, - STATE_READ, - STATE_UPDATE, - STATE_WRITE - } - t_state; - - t_state state; - - // - // State machine - // - always_ff @(posedge clk) - begin - if (reset) - begin - state <= STATE_IDLE; - rd_end_of_list <= 1'b0; - end - else - begin - case (state) - STATE_IDLE: - begin - // Traversal begins when CSR 1 is written - if (start_read) - begin - state <= STATE_READ; - $display("AFU starting traversal at 0x%x", t_ccip_clAddr'(read_mem_addr)); - end - end - - STATE_READ: - begin - $display("AFU in READ..."); - $display("do_update is %d...",do_update); - $display("addr_next_valid is %d...",addr_next_valid); - $display("rd_needed is %d...",rd_needed); - if (!rd_needed && do_update) - begin - state <= STATE_UPDATE; - $display("AFU moving to UPDATE..."); - end - end - - STATE_UPDATE: - begin - // Update the read value to be written back - $display("AFU in UPDATE..."); - if (!do_update) - begin - state <= STATE_WRITE; - wr_needed <= 1'b1; - $display("AFU moving to WRITE..."); - end - end - - STATE_WRITE: - begin - // Write the updated value to the address - // Point to new address after that - // if done then point to IDLE; else read new values - $display("AFU in WRITE..."); - if (rd_end_of_list) - begin - state <= STATE_IDLE; - $display("AFU done..."); - end - else if (!wr_needed) - begin - state <= STATE_READ; - $display("AFU moving to READ from WRITE..."); - start_write <= 1'b0; - write_req <= 1'b0; - end - end - endcase - end - end - - - // ========================================================================= - // - // Read logic. - // - // ========================================================================= - - // - // READ REQUEST - // - - // Did a write response just arrive - - // Next read address - - always_ff @(posedge clk) - begin - // Next read address is valid when we have got the write response back - if (sRx.c1.rspValid) - begin - addr_next_valid <= sRx.c1.rspValid; - - //if (state == STATE_READ && !rd_needed) - //begin - // Apurve: Next address is current address plus address length - //addr_next <= addr_next + addr_size; - addr_next <= (addr_next_valid ? rd_addr + 0 : rd_addr); - - // End of list reached if we have read 5 times - rd_end_of_list <= (cnt_list_length == 'h5); - //end - end - end - - // - // Since back pressure may prevent an immediate read request, we must - // record whether a read is needed and hold it until the request can - // be sent to the FIU. - // - - always_ff @(posedge clk) - begin - if (reset) - begin - rd_needed <= 1'b0; - end - else - begin - // If reads are allowed this cycle then we can safely clear - // any previously requested reads. This simple AFU has only - // one read in flight at a time since it is walking a pointer - // chain. - if (rd_needed) - begin - //rd_needed <= sRx.c0TxAlmFull; - //rd_needed <= (!sRx.c0TxAlmFull && !sRx.c0.rspValid); - rd_needed <= !sRx.c0.rspValid; - end - else if (state == STATE_READ) - begin - // Need a read under two conditions: - // - Starting a new walk - // - A read response just arrived from a line containing - // a next pointer. - rd_needed <= (start_read || (!sRx.c0TxAlmFull && (addr_next_valid && ! rd_end_of_list))); - rd_addr <= (start_read ? read_mem_addr : addr_next); - //$display("rd_addr is 0x%x", t_ccip_clAddr'(rd_addr)); - //$display("read mem addr is 0x%x", t_ccip_clAddr'(read_mem_addr)); - //$display("start read is %d", start_read); - end - end - end - - // - // Emit read requests to the FIU. - // - - // Read header defines the request to the FIU - t_ccip_c0_ReqMemHdr rd_hdr; - - always_comb - begin - rd_hdr = t_ccip_c0_ReqMemHdr'(0); - - // Read request type (No intention to cache) - //rd_hdr.req_type = 4'h0; - - // Virtual address (MPF virtual addressing is enabled) - rd_hdr.address = rd_addr; - - // Read over channel VA - //rd_hdr.vc_sel = 2'h0; - - // Read one cache line (64 bytes) - //rd_hdr.cl_len = 2'h0; - end - - // Send read requests to the FIU - always_ff @(posedge clk) - begin - if (reset) - begin - sTx.c0.valid <= 1'b0; - cnt_list_length <= 0; - read_req <= 1'b0; - end - else - begin - // Generate a read request when needed and the FIU isn't full - if (state == STATE_READ) - begin - sTx.c0.valid <= (rd_needed && !sRx.c0TxAlmFull && !read_req); - - if (rd_needed && !sRx.c0TxAlmFull && !read_req) - begin - sTx.c0.hdr <= rd_hdr; - cnt_list_length <= cnt_list_length + 1; - read_req <= 1'b1; - $display("Incrementing read count...%d",cnt_list_length); - $display("Read address is 0x%x...",rd_hdr.address); - addr_next_valid <= 1'b0; - // Apurve: Add something to stop read once this section has been accessed - //rd_needed <= 1'b0; - end - end - end - end - - // - // READ RESPONSE HANDLING - // - - // - // Receive data (read responses). - // - always_ff @(posedge clk) - begin - if (reset) - begin - do_update <= 1'b0; - end - else - begin - if (!do_update && sRx.c0.rspValid) - begin - rd_data <= sRx.c0.data; - do_update <= 1'b1; - $display("rd data is %d...",rd_data); - end - - if ((state == STATE_UPDATE) && (do_update == 1'b1)) - begin - // Update the read data and put it in the write data to be written - wr_data <= rd_data + 2; - do_update <= 1'b0; - read_req <= 1'b0; - $display("write data is %d...",wr_data); - - // First read done. Next reads should be from the updated addresses - start_read <= 1'b0; - end - end - end - - - // ========================================================================= - // - // Write logic. - // - // ========================================================================= - - - // - // WRITE REQUEST - // - - // Did a write response just arrive - - // Next write address - - always_ff @(posedge clk) - begin - if (sRx.c0.rspValid) - begin - // Next write address is valid when we have got the read response back - wr_addr_next_valid <= sRx.c0.rspValid; - //wr_addr_next_valid <= (!start_write && sRx.c0.rspValid); - - //if (state == STATE_WRITE && !wr_needed) - //begin - // Apurve: Next address is current address plus address length - //wr_addr_next <= wr_addr + 0; - wr_addr_next <= (wr_addr_next_valid ? wr_addr + 0 : wr_addr); - //end - end - end - - // - // Since back pressure may prevent an immediate write request, we must - // record whether a write is needed and hold it until the request can - // be sent to the FIU. - // - - always_ff @(posedge clk) - begin - if (reset) - begin - wr_needed <= 1'b0; - end - else - begin - // If writes are allowed this cycle then we can safely clear - // any previously requested writes. This simple AFU has only - // one write in flight at a time since it is walking a pointer - // chain. - if (wr_needed) - begin - //wr_needed <= sRx.c1TxAlmFull; - //wr_needed <= (!sRx.c1TxAlmFull && !sRx.c1.rspValid); - wr_needed <= !sRx.c1.rspValid; - end - else - begin - // Need a write under two conditions: - // - Starting a new walk - // - A write response just arrived from a line containing - // a next pointer. - wr_needed <= (start_write || (!sRx.c1TxAlmFull && wr_addr_next_valid)); - wr_addr <= (start_write ? write_mem_addr : wr_addr_next); - //$display("Write mem address later is 0x%x", t_ccip_clAddr'(write_mem_addr)); - end - end - end - - // - // Emit write requests to the FIU. - // - - // Write header defines the request to the FIU - t_ccip_c1_ReqMemHdr wr_hdr; - - always_comb - begin - wr_hdr = t_ccip_c1_ReqMemHdr'(0); - - // Write request type - //wr_hdr.req_type = 4'h0; - - // Virtual address (MPF virtual addressing is enabled) - wr_hdr.address = wr_addr; - - // Let the FIU pick the channel - //wr_hdr.vc_sel = 2'h2; - - // Write 1 cache line (64 bytes) - //wr_hdr.cl_len = 2'h0; - - // Start of packet is true (single line write) - wr_hdr.sop = 1'b1; - end - - // Send write requests to the FIU - always_ff @(posedge clk) - begin - if (reset) - begin - sTx.c1.valid <= 1'b0; - write_req <= 1'b0; - end - else - begin - // Generate a write request when needed and the FIU isn't full - if (state == STATE_WRITE) - begin - sTx.c1.valid <= (wr_needed && !sRx.c1TxAlmFull && !write_req); - if (wr_needed && !sRx.c1TxAlmFull && !write_req) - begin - sTx.c1.hdr <= wr_hdr; - sTx.c1.data <= t_ccip_clData'(wr_data); - write_req <= 1'b1; - wr_addr_next_valid <= 1'b0; - $display("Write address is 0x%x...", wr_hdr.address); - end - end - end - end - - - // - // WRITE RESPONSE HANDLING - // - - // Apurve: Check if a signal is to be sent to read to start reading in case - // write response does not work - // - // Send data (write requests). - // - //always_ff @(posedge clk) - //begin - // if (state == STATE_WRITE) - // begin - // rd_data <= sRx.c0.data; - // end - // if (state == STATE_UPDATE) - // begin - // // Update the write data and put it in the write data to be written - // wr_data <= rd_data + 1; - // end - //end - -endmodule diff --git a/driver/tests/dogfood/Memcpy/hw/rtl/cci_hello_afu_working.sv b/driver/tests/dogfood/Memcpy/hw/rtl/cci_hello_afu_working.sv deleted file mode 100644 index 144b430e..00000000 --- a/driver/tests/dogfood/Memcpy/hw/rtl/cci_hello_afu_working.sv +++ /dev/null @@ -1,621 +0,0 @@ -// -// Copyright (c) 2017, Intel Corporation -// All rights reserved. -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions are met: -// -// Redistributions of source code must retain the above copyright notice, this -// list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright notice, -// this list of conditions and the following disclaimer in the documentation -// and/or other materials provided with the distribution. -// -// Neither the name of the Intel Corporation nor the names of its contributors -// may be used to endorse or promote products derived from this software -// without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE -// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -// POSSIBILITY OF SUCH DAMAGE. - - -// Read from the memory locations first and then write to the memory locations - -`include "platform_if.vh" -`include "afu_json_info.vh" - - -module ccip_std_afu - ( - // CCI-P Clocks and Resets - input logic pClk, // 400MHz - CCI-P clock domain. Primary interface clock - input logic pClkDiv2, // 200MHz - CCI-P clock domain. - input logic pClkDiv4, // 100MHz - CCI-P clock domain. - input logic uClk_usr, // User clock domain. Refer to clock programming guide ** Currently provides fixed 300MHz clock ** - input logic uClk_usrDiv2, // User clock domain. Half the programmed frequency ** Currently provides fixed 150MHz clock ** - input logic pck_cp2af_softReset, // CCI-P ACTIVE HIGH Soft Reset - input logic [1:0] pck_cp2af_pwrState, // CCI-P AFU Power State - input logic pck_cp2af_error, // CCI-P Protocol Error Detected - - // Interface structures - input t_if_ccip_Rx pck_cp2af_sRx, // CCI-P Rx Port - output t_if_ccip_Tx pck_af2cp_sTx // CCI-P Tx Port - ); - - - // - // Run the entire design at the standard CCI-P frequency (400 MHz). - // - logic clk; - assign clk = pClk; - - logic reset; - assign reset = pck_cp2af_softReset; - - logic [511:0] wr_data; - logic [511:0] rd_data; - - logic do_update; - logic start_read; - logic start_write; - logic wr_addr_next_valid; - logic addr_next_valid; - logic rd_end_of_list; - logic rd_needed; - logic wr_needed; - logic [15:0] cnt_list_length; - t_ccip_clAddr rd_addr; - t_ccip_clAddr wr_addr; - t_ccip_clAddr addr_next; - t_ccip_clAddr wr_addr_next; - - // ========================================================================= - // - // Register requests. - // - // ========================================================================= - - // - // The incoming pck_cp2af_sRx and outgoing pck_af2cp_sTx must both be - // registered. Here we register pck_cp2af_sRx and assign it to sRx. - // We also assign pck_af2cp_sTx to sTx here but don't register it. - // The code below never uses combinational logic to write sTx. - // - - t_if_ccip_Rx sRx; - always_ff @(posedge clk) - begin - sRx <= pck_cp2af_sRx; - end - - t_if_ccip_Tx sTx; - assign pck_af2cp_sTx = sTx; - - - // ========================================================================= - // - // CSR (MMIO) handling. - // - // ========================================================================= - - // The AFU ID is a unique ID for a given program. Here we generated - // one with the "uuidgen" program and stored it in the AFU's JSON file. - // ASE and synthesis setup scripts automatically invoke afu_json_mgr - // to extract the UUID into afu_json_info.vh. - logic [127:0] afu_id = `AFU_ACCEL_UUID; - - // - // A valid AFU must implement a device feature list, starting at MMIO - // address 0. Every entry in the feature list begins with 5 64-bit - // words: a device feature header, two AFU UUID words and two reserved - // words. - // - - // Is a CSR read request active this cycle? - logic is_csr_read; - assign is_csr_read = sRx.c0.mmioRdValid; - - // Is a CSR write request active this cycle? - logic is_csr_write; - assign is_csr_write = sRx.c0.mmioWrValid; - - // The MMIO request header is overlayed on the normal c0 memory read - // response data structure. Cast the c0Rx header to an MMIO request - // header. - t_ccip_c0_ReqMmioHdr mmio_req_hdr; - assign mmio_req_hdr = t_ccip_c0_ReqMmioHdr'(sRx.c0.hdr); - - - // - // Implement the device feature list by responding to MMIO reads. - // - - always_ff @(posedge clk) - begin - if (reset) - begin - sTx.c2.mmioRdValid <= 1'b0; - end - else - begin - // Always respond with something for every read request - sTx.c2.mmioRdValid <= is_csr_read; - - // The unique transaction ID matches responses to requests - sTx.c2.hdr.tid <= mmio_req_hdr.tid; - - // Addresses are of 32-bit objects in MMIO space. Addresses - // of 64-bit objects are thus multiples of 2. - case (mmio_req_hdr.address) - 0: // AFU DFH (device feature header) - begin - // Here we define a trivial feature list. In this - // example, our AFU is the only entry in this list. - sTx.c2.data <= t_ccip_mmioData'(0); - // Feature type is AFU - sTx.c2.data[63:60] <= 4'h1; - // End of list (last entry in list) - sTx.c2.data[40] <= 1'b1; - end - - // AFU_ID_L - 2: sTx.c2.data <= afu_id[63:0]; - - // AFU_ID_H - 4: sTx.c2.data <= afu_id[127:64]; - - // DFH_RSVD0 - 6: sTx.c2.data <= t_ccip_mmioData'(0); - - // DFH_RSVD1 - 8: sTx.c2.data <= t_ccip_mmioData'(0); - - // Updated by apurve to check fpgaReadMMIO - 10: sTx.c2.data <= t_ccip_mmioData'(start_read); - - default: sTx.c2.data <= t_ccip_mmioData'(0); - endcase - end - end - - - // - // CSR write handling. Host software must tell the AFU the memory address - // to which it should be writing. The address is set by writing a CSR. - // - - // We use MMIO address 0 to set the memory address. The read and - // write MMIO spaces are logically separate so we are free to use - // whatever we like. This may not be good practice for cleanly - // organizing the MMIO address space, but it is legal. - logic is_mem_addr_csr_write; - assign is_mem_addr_csr_write = is_csr_write && - (mmio_req_hdr.address == t_ccip_mmioAddr'(0)); - - // Memory address to which this AFU will write. - t_ccip_clAddr write_mem_addr; - - always_ff @(posedge clk) - begin - if (reset) - begin - start_write <= 1'b0; - end - else if (is_mem_addr_csr_write) - begin - write_mem_addr <= t_ccip_clAddr'(sRx.c0.data); - start_write <= 1'b1; - //$display("Write mem address is 0x%x", t_ccip_clAddr'(write_mem_addr)); - end - end - - - // We use MMIO address 8 to set the memory address for reading data. - logic is_mem_addr_csr_read; - assign is_mem_addr_csr_read = is_csr_write && - (mmio_req_hdr.address == t_ccip_mmioAddr'(2)); - - // Memory address from which this AFU will read. - t_ccip_clAddr read_mem_addr; - - //logic start_traversal = 'b0; - //t_ccip_clAddr start_traversal_addr; - - always_ff @(posedge clk) - begin - if (reset) - begin - start_read <= 1'b0; - end - else if (is_mem_addr_csr_read) - begin - read_mem_addr <= t_ccip_clAddr'(sRx.c0.data); - start_read <= 1'b1; - //$display("Read mem address is 0x%x", t_ccip_clAddr'(read_mem_addr)); - end - end - - - // ========================================================================= - // - // Main AFU logic - // - // ========================================================================= - - // - // States in our simple example. - // - //typedef enum logic [0:0] - typedef enum logic [1:0] - { - STATE_IDLE, - STATE_READ, - STATE_UPDATE, - STATE_WRITE - } - t_state; - - t_state state; - - // - // State machine - // - always_ff @(posedge clk) - begin - if (reset) - begin - state <= STATE_IDLE; - rd_end_of_list <= 1'b0; - end - else - begin - case (state) - STATE_IDLE: - begin - // Traversal begins when CSR 1 is written - if (start_read) - begin - state <= STATE_READ; - $display("AFU starting traversal at 0x%x", t_ccip_clAddr'(read_mem_addr)); - end - end - - STATE_READ: - begin - $display("AFU in READ..."); - if (!rd_needed && do_update) - begin - state <= STATE_UPDATE; - $display("AFU moving to UPDATE..."); - end - end - - STATE_UPDATE: - begin - // Update the read value to be written back - $display("AFU in UPDATE..."); - if (!do_update) - begin - state <= STATE_WRITE; - wr_needed <= 1'b1; - $display("AFU moving to WRITE..."); - end - end - - STATE_WRITE: - begin - // Write the updated value to the address - // Point to new address after that - // if done then point to IDLE; else read new values - $display("AFU in WRITE..."); - if (rd_end_of_list) - begin - state <= STATE_IDLE; - $display("AFU done..."); - end - else if (!wr_needed) - begin - state <= STATE_READ; - $display("AFU moving to READ from WRITE..."); - start_write <= 1'b0; - end - end - endcase - end - end - - - // ========================================================================= - // - // Read logic. - // - // ========================================================================= - - // - // READ REQUEST - // - - // Did a write response just arrive - - // Next read address - - always_ff @(posedge clk) - begin - // Next read address is valid when we have got the write response back - addr_next_valid <= sRx.c1.rspValid; - - // Apurve: Next address is current address plus address length - //addr_next <= addr_next + addr_size; - addr_next <= rd_addr + 0; - - // End of list reached if we have read 5 times - rd_end_of_list <= (cnt_list_length == 'h5); - end - - // - // Since back pressure may prevent an immediate read request, we must - // record whether a read is needed and hold it until the request can - // be sent to the FIU. - // - - always_ff @(posedge clk) - begin - if (reset) - begin - rd_needed <= 1'b0; - end - else - begin - // If reads are allowed this cycle then we can safely clear - // any previously requested reads. This simple AFU has only - // one read in flight at a time since it is walking a pointer - // chain. - if (rd_needed) - begin - rd_needed <= sRx.c0TxAlmFull; - end - else - begin - // Need a read under two conditions: - // - Starting a new walk - // - A read response just arrived from a line containing - // a next pointer. - rd_needed <= (start_read || (!sRx.c0TxAlmFull && (addr_next_valid && ! rd_end_of_list))); - rd_addr <= (start_read ? read_mem_addr : addr_next); - //$display("rd_addr is 0x%x", t_ccip_clAddr'(rd_addr)); - //$display("read mem addr is 0x%x", t_ccip_clAddr'(read_mem_addr)); - //$display("start read is %d", start_read); - end - end - end - - // - // Emit read requests to the FIU. - // - - // Read header defines the request to the FIU - t_ccip_c0_ReqMemHdr rd_hdr; - - always_comb - begin - rd_hdr = t_ccip_c0_ReqMemHdr'(0); - - // Read request type (No intention to cache) - //rd_hdr.req_type = 4'h0; - - // Virtual address (MPF virtual addressing is enabled) - rd_hdr.address = rd_addr; - - // Read over channel VA - //rd_hdr.vc_sel = 2'h0; - - // Read one cache line (64 bytes) - //rd_hdr.cl_len = 2'h0; - end - - // Send read requests to the FIU - always_ff @(posedge clk) - begin - if (reset) - begin - sTx.c0.valid <= 1'b0; - cnt_list_length <= 0; - end - else - begin - // Generate a read request when needed and the FIU isn't full - if (state == STATE_READ) - begin - sTx.c0.valid <= (rd_needed && !sRx.c0TxAlmFull); - - if (rd_needed && !sRx.c0TxAlmFull) - begin - sTx.c0.hdr <= rd_hdr; - cnt_list_length <= cnt_list_length + 1; - $display("Incrementing read count...%d",cnt_list_length); - $display("Read address is 0x%x...",rd_hdr.address); - // Apurve: Add something to stop read once this section has been accessed - end - end - end - end - - // - // READ RESPONSE HANDLING - // - - // - // Receive data (read responses). - // - always_ff @(posedge clk) - begin - if (reset) - begin - do_update <= 1'b0; - end - else - begin - if (sRx.c0.rspValid) - begin - rd_data <= sRx.c0.data; - do_update <= 1'b1; - //$display("rd data is %d...",rd_data); - end - - if (state == STATE_UPDATE) - begin - // Update the read data and put it in the write data to be written - wr_data <= rd_data + 2; - do_update <= 1'b0; - $display("write data is %d...",wr_data); - - // First read done. Next reads should be from the updated addresses - start_read <= 1'b0; - end - end - end - - - // ========================================================================= - // - // Write logic. - // - // ========================================================================= - - - // - // WRITE REQUEST - // - - // Did a write response just arrive - - // Next write address - - always_ff @(posedge clk) - begin - // Next write address is valid when we have got the read response back - wr_addr_next_valid <= sRx.c0.rspValid; - - // Apurve: Next address is current address plus address length - wr_addr_next <= wr_addr + 0; - - end - - // - // Since back pressure may prevent an immediate write request, we must - // record whether a write is needed and hold it until the request can - // be sent to the FIU. - // - - always_ff @(posedge clk) - begin - if (reset) - begin - wr_needed <= 1'b0; - end - else - begin - // If writes are allowed this cycle then we can safely clear - // any previously requested writes. This simple AFU has only - // one write in flight at a time since it is walking a pointer - // chain. - if (wr_needed) - begin - wr_needed <= sRx.c1TxAlmFull; - end - else - begin - // Need a write under two conditions: - // - Starting a new walk - // - A write response just arrived from a line containing - // a next pointer. - wr_needed <= (start_write || (!sRx.c1TxAlmFull && wr_addr_next_valid)); - wr_addr <= (start_write ? write_mem_addr : wr_addr_next); - //$display("Write mem address later is 0x%x", t_ccip_clAddr'(write_mem_addr)); - end - end - end - - // - // Emit write requests to the FIU. - // - - // Write header defines the request to the FIU - t_ccip_c1_ReqMemHdr wr_hdr; - - always_comb - begin - wr_hdr = t_ccip_c1_ReqMemHdr'(0); - - // Write request type - //wr_hdr.req_type = 4'h0; - - // Virtual address (MPF virtual addressing is enabled) - wr_hdr.address = wr_addr; - - // Let the FIU pick the channel - //wr_hdr.vc_sel = 2'h2; - - // Write 1 cache line (64 bytes) - //wr_hdr.cl_len = 2'h0; - - // Start of packet is true (single line write) - wr_hdr.sop = 1'b1; - end - - // Send write requests to the FIU - always_ff @(posedge clk) - begin - if (reset) - begin - sTx.c1.valid <= 1'b0; - end - else - begin - // Generate a write request when needed and the FIU isn't full - if (state == STATE_WRITE) - begin - sTx.c1.valid <= (wr_needed && !sRx.c1TxAlmFull); - if (wr_needed && !sRx.c1TxAlmFull) - begin - sTx.c1.hdr <= wr_hdr; - sTx.c1.data <= t_ccip_clData'(wr_data); - end - end - end - end - - - // - // WRITE RESPONSE HANDLING - // - - // Apurve: Check if a signal is to be sent to read to start reading in case - // write response does not work - // - // Send data (write requests). - // - //always_ff @(posedge clk) - //begin - // if (state == STATE_WRITE) - // begin - // rd_data <= sRx.c0.data; - // end - // if (state == STATE_UPDATE) - // begin - // // Update the write data and put it in the write data to be written - // wr_data <= rd_data + 1; - // end - //end - -endmodule diff --git a/driver/tests/dogfood/Memcpy/hw/rtl/sources.txt b/driver/tests/dogfood/Memcpy/hw/rtl/sources.txt deleted file mode 100644 index 8a73008b..00000000 --- a/driver/tests/dogfood/Memcpy/hw/rtl/sources.txt +++ /dev/null @@ -1,2 +0,0 @@ -cci_hello.json -cci_hello_afu.sv diff --git a/driver/tests/dogfood/Memcpy/hw/sim/setup_ase b/driver/tests/dogfood/Memcpy/hw/sim/setup_ase deleted file mode 100755 index a8414ac0..00000000 --- a/driver/tests/dogfood/Memcpy/hw/sim/setup_ase +++ /dev/null @@ -1,11 +0,0 @@ -#!/bin/sh - -## -## Setup ASE environment using ../rtl/sources.txt. -## - -# Absolute path to this script -SCRIPT=$(readlink -f "$0") -SCRIPT_PATH=$(dirname "$SCRIPT") - -afu_sim_setup --sources="${SCRIPT_PATH}/../rtl/sources.txt" $@ diff --git a/driver/tests/dogfood/Memcpy/sw/Makefile b/driver/tests/dogfood/Memcpy/sw/Makefile deleted file mode 100644 index f3b66c12..00000000 --- a/driver/tests/dogfood/Memcpy/sw/Makefile +++ /dev/null @@ -1,41 +0,0 @@ -include ../../common/sw/common_include.mk - -# Primary test name -TEST = cci_hello - -# Build directory -OBJDIR = obj -CFLAGS += -I./$(OBJDIR) -CPPFLAGS += -I./$(OBJDIR) - -# Files and folders -SRCS = $(TEST).c -OBJS = $(addprefix $(OBJDIR)/,$(patsubst %.c,%.o,$(SRCS))) - -# Targets (build only $(TEST)_ase by default) -all: $(TEST) $(TEST)_ase - -# AFU info from JSON file, including AFU UUID -AFU_JSON_INFO = $(OBJDIR)/afu_json_info.h - -$(AFU_JSON_INFO): ../hw/rtl/$(TEST).json | objdir - afu_json_mgr json-info --afu-json=$^ --c-hdr=$@ - -$(OBJS): $(AFU_JSON_INFO) - -$(TEST): $(OBJS) - $(CC) -o $@ $^ $(LDFLAGS) $(FPGA_LIBS) - -$(TEST)_ase: $(OBJS) - $(CC) -o $@ $^ $(LDFLAGS) $(ASE_LIBS) - -$(OBJDIR)/%.o: %.c | objdir - $(CC) $(CFLAGS) -c $< -o $@ - -clean: - rm -rf $(TEST) $(TEST)_ase $(OBJDIR) - -objdir: - @mkdir -p $(OBJDIR) - -.PHONY: all clean diff --git a/driver/tests/dogfood/Memcpy/sw/cci_hello.c b/driver/tests/dogfood/Memcpy/sw/cci_hello.c deleted file mode 100644 index f12d95c2..00000000 --- a/driver/tests/dogfood/Memcpy/sw/cci_hello.c +++ /dev/null @@ -1,210 +0,0 @@ -// -// Copyright (c) 2017, Intel Corporation -// All rights reserved. -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions are met: -// -// Redistributions of source code must retain the above copyright notice, this -// list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright notice, -// this list of conditions and the following disclaimer in the documentation -// and/or other materials provided with the distribution. -// -// Neither the name of the Intel Corporation nor the names of its contributors -// may be used to endorse or promote products derived from this software -// without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE -// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -// POSSIBILITY OF SUCH DAMAGE. - -#include -#include -#include -#include -#include -#include - -#include - -// State from the AFU's JSON file, extracted using OPAE's afu_json_mgr script -#include "afu_json_info.h" - -#define CACHELINE_BYTES 64 -#define CL(x) ((x) * CACHELINE_BYTES) - - -// -// Search for an accelerator matching the requested UUID and connect to it. -// -static fpga_handle connect_to_accel(const char *accel_uuid) -{ - fpga_properties filter = NULL; - fpga_guid guid; - fpga_token accel_token; - uint32_t num_matches; - fpga_handle accel_handle; - fpga_result r; - - // Don't print verbose messages in ASE by default - //setenv("ASE_LOG", "0", 0); - - // Set up a filter that will search for an accelerator - fpgaGetProperties(NULL, &filter); - fpgaPropertiesSetObjectType(filter, FPGA_ACCELERATOR); - - // Add the desired UUID to the filter - uuid_parse(accel_uuid, guid); - fpgaPropertiesSetGUID(filter, guid); - - // Do the search across the available FPGA contexts - num_matches = 1; - fpgaEnumerate(&filter, 1, &accel_token, 1, &num_matches); - - // Not needed anymore - fpgaDestroyProperties(&filter); - - if (num_matches < 1) - { - fprintf(stderr, "Accelerator %s not found!\n", accel_uuid); - return 0; - } - - // Open accelerator - r = fpgaOpen(accel_token, &accel_handle, 0); - assert(FPGA_OK == r); - - // Done with token - fpgaDestroyToken(&accel_token); - - return accel_handle; -} - - -// -// Allocate a buffer in I/O memory, shared with the FPGA. -// -static volatile void* alloc_buffer(fpga_handle accel_handle, - ssize_t size, - uint64_t *wsid, - uint64_t *io_addr) -{ - fpga_result r; - volatile void* buf; - - r = fpgaPrepareBuffer(accel_handle, size, (void*)&buf, wsid, 0); - if (FPGA_OK != r) return NULL; - - // Get the physical address of the buffer in the accelerator - r = fpgaGetIOAddress(accel_handle, *wsid, io_addr); - assert(FPGA_OK == r); - - return buf; -} - - -int main(int argc, char *argv[]) -{ - fpga_handle accel_handle; - volatile char *buf; - volatile char *buf_r; - uint64_t wsid1; - uint64_t wsid2; - uint64_t buf_pa; - uint64_t ret_buf_pa; - uint64_t buf_rpa; - uint64_t ret_buf_rpa; - fpga_result r; - - // Find and connect to the accelerator - accel_handle = connect_to_accel(AFU_ACCEL_UUID); - - // Allocate a single page memory buffer for write - buf = (volatile char*)alloc_buffer(accel_handle, 4 * getpagesize(), - &wsid1, &buf_pa); - // Allocate a single page memory buffer for read - buf_r = (volatile char*)alloc_buffer(accel_handle, 4 * getpagesize(), - &wsid2, &buf_rpa); - assert(NULL != buf); - - //// Set the low byte of the shared buffer to 0. The FPGA will write - //// a non-zero value to it. - //buf[0] = 0; - - // Set the low byte of the shared buffer buf_r to 0. The FPGA will read - // the values and write to buf address - buf[0] = 5; - buf_r[0] = 5; - - // Tell the accelerator the address of the buffer using cache line - // addresses. The accelerator will respond by writing to the buffer. - r = fpgaWriteMMIO64(accel_handle, 0, 0, buf_pa / CL(1)); - printf("Write address is %08lx\n", buf_pa); - printf("Write address div 64 is %08lx\n", buf_pa/ CL(1)); - assert(FPGA_OK == r); - - // Wait for response from FPGA. Check using fpgaReadMMIO - //r = fpgaReadMMIO64(accel_handle, 0, 0, &ret_buf_pa); - //printf("Returned write is %08lx\n", ret_buf_pa); - //assert(FPGA_OK == r); - -///////////////////// Added to check fpgaRead - // Wait for response from FPGA. Check using fpgaReadMMIO - r = fpgaReadMMIO64(accel_handle, 0, 5 * sizeof(uint64_t), &ret_buf_rpa); - printf("Returned read at 10 is %08lx\n", ret_buf_rpa); - assert(FPGA_OK == r); -/////////////////////////////////////////////// - - - // Tell the accelerator the address of the buffer using cache line - // addresses. The accelerator will read from the buffer. - // Write the address to MMIO 1 - r = fpgaWriteMMIO64(accel_handle, 0, sizeof(uint64_t), buf_rpa / CL(1)); - printf("Read address is %08lx\n", buf_rpa); - printf("Read address div64 is %08lx\n", buf_rpa / CL(1)); - assert(FPGA_OK == r); - - // Wait for response from FPGA. Check using fpgaReadMMIO - //r = fpgaReadMMIO64(accel_handle, 0, sizeof(uint64_t), &ret_buf_rpa); - //printf("Returned write is %08lx\n", ret_buf_rpa); - //assert(FPGA_OK == r); - - - - - - - - - // Update this - // Spin, waiting for the value in memory to change to something non-zero. - while (5 == buf[0]) - { - // A well-behaved program would use _mm_pause(), nanosleep() or - // equivalent to save power here. - }; - - // Print the string written by the FPGA - printf("%d\n", buf[0]); - - do { - //printf("%d\n", buf[0]); - } while (10 != buf[0]); - - // Done - fpgaReleaseBuffer(accel_handle, wsid1); - fpgaReleaseBuffer(accel_handle, wsid2); - fpgaClose(accel_handle); - - return 0; -} diff --git a/driver/tests/dogfood/Memcpy/sw/obj/afu_json_info.h b/driver/tests/dogfood/Memcpy/sw/obj/afu_json_info.h deleted file mode 100644 index e16a5349..00000000 --- a/driver/tests/dogfood/Memcpy/sw/obj/afu_json_info.h +++ /dev/null @@ -1,13 +0,0 @@ -// -// Generated by afu_json_mgr from ../hw/rtl/cci_hello.json -// - -#ifndef __AFU_JSON_INFO__ -#define __AFU_JSON_INFO__ - -#define AFU_ACCEL_NAME "cci_hello" -#define AFU_ACCEL_UUID "C6AA954A-9B91-4A37-ABC1-1D9F0709DCC3" -#define AFU_IMAGE_POWER 0 -#define AFU_TOP_IFC "ccip_std_afu" - -#endif // __AFU_JSON_INFO__ diff --git a/driver/tests/dogfood/Memcpy/sw/obj/cci_hello.o b/driver/tests/dogfood/Memcpy/sw/obj/cci_hello.o deleted file mode 100644 index a6d79f49..00000000 Binary files a/driver/tests/dogfood/Memcpy/sw/obj/cci_hello.o and /dev/null differ diff --git a/driver/tests/dogfood/common.h b/driver/tests/dogfood/common.h new file mode 100644 index 00000000..da6e77d2 --- /dev/null +++ b/driver/tests/dogfood/common.h @@ -0,0 +1,14 @@ +#ifndef _COMMON_H_ +#define _COMMON_H_ + +#define KERNEL_ARG_DEV_MEM_ADDR 0x7ffff000 + +struct kernel_arg_t { + uint32_t testid; + uint32_t count; + uint32_t src0_ptr; + uint32_t src1_ptr; + uint32_t dst_ptr; +}; + +#endif \ No newline at end of file diff --git a/driver/tests/dogfood/dogfood.cpp b/driver/tests/dogfood/dogfood.cpp new file mode 100644 index 00000000..3cbd5fea --- /dev/null +++ b/driver/tests/dogfood/dogfood.cpp @@ -0,0 +1,276 @@ +#include +#include +#include +#include +#include +#include +#include "testcases.h" +#include "common.h" + +#define RT_CHECK(_expr) \ + do { \ + int _ret = _expr; \ + if (0 == _ret) \ + break; \ + printf("Error: '%s' returned %d!\n", #_expr, (int)_ret); \ + cleanup(); \ + exit(-1); \ + } while (false) + +/////////////////////////////////////////////////////////////////////////////// + +class TestMngr { +public: + TestMngr() { + this->add_test("iadd", new Test_IADD()); + this->add_test("imul", new Test_IMUL()); + this->add_test("idiv", new Test_IDIV()); + this->add_test("idiv-mul", new Test_IDIV_MUL()); + #ifdef EXT_F_ENABLE + this->add_test("fadd", new Test_FADD()); + this->add_test("fsub", new Test_FSUB()); + this->add_test("fmul", new Test_FMUL()); + this->add_test("fmadd", new Test_FMADD()); + this->add_test("fmsub", new Test_FMSUB()); + this->add_test("fnmadd", new Test_FNMADD()); + this->add_test("fnmsub", new Test_FNMSUB()); + this->add_test("fnmadd-madd", new Test_FNMADD_MADD()); + this->add_test("fdiv", new Test_FDIV()); + this->add_test("fdiv2", new Test_FDIV2()); + this->add_test("fsqrt", new Test_FSQRT()); + this->add_test("ftoi", new Test_FTOI()); + this->add_test("ftou", new Test_FTOU()); + this->add_test("itof", new Test_ITOF()); + this->add_test("utof", new Test_UTOF()); + #endif + } + + ~TestMngr() { + for (size_t i = 0; i < _tests.size(); ++i) { + delete _tests[i]; + } + } + + const std::string& get_name(int testid) const { + return _names.at(testid); + } + + ITestCase* get_test(int testid) const { + return _tests.at(testid); + } + + void add_test(const char* name, ITestCase* test) { + _names.push_back(name); + _tests.push_back(test); + } + + size_t size() const { + return _tests.size(); + } + +private: + std::vector _names; + std::vector _tests; +}; + +/////////////////////////////////////////////////////////////////////////////// + +TestMngr testMngr; +const char* kernel_file = "kernel.bin"; +int count = 0; +int testid_s = 0; +int testid_e = (testMngr.size() - 1); +bool stop_on_error = true; + +vx_device_h device = nullptr; +vx_buffer_h arg_buf = nullptr; +vx_buffer_h src1_buf = nullptr; +vx_buffer_h src2_buf = nullptr; +vx_buffer_h dst_buf = nullptr; + +static void show_usage() { + std::cout << "Vortex Driver Test." << std::endl; + std::cout << "Usage: [-s:testid] [-e:testid] [-k: kernel] [-n words] [-c] [-h: help]" << std::endl; +} + +static void parse_args(int argc, char **argv) { + int c; + while ((c = getopt(argc, argv, "n:s:e:k:ch?")) != -1) { + switch (c) { + case 'n': + count = atoi(optarg); + break; + case 's': + testid_s = atoi(optarg); + break; + case 'e': + testid_e = atoi(optarg); + break; + case 'k': + kernel_file = optarg; + break; + case 'c': + stop_on_error = false; + break; + case 'h': + case '?': { + show_usage(); + exit(0); + } break; + default: + show_usage(); + exit(-1); + } + } +} + +void cleanup() { + if (arg_buf) { + vx_buf_release(arg_buf); + } + if (src1_buf) { + vx_buf_release(src1_buf); + } + if (src2_buf) { + vx_buf_release(src2_buf); + } + if (dst_buf) { + vx_buf_release(dst_buf); + } + if (device) { + vx_dev_close(device); + } +} + +int main(int argc, char *argv[]) { + int exitcode = 0; + size_t value; + kernel_arg_t kernel_arg; + + // parse command arguments + parse_args(argc, argv); + + if (count == 0) { + count = 1; + } + + std::cout << std::dec; + + std::cout << "test ids: " << testid_s << " - " << testid_e << std::endl; + std::cout << "workitem size: " << count << std::endl; + std::cout << "using kernel: " << kernel_file << std::endl; + + // open device connection + std::cout << "open device connection" << std::endl; + RT_CHECK(vx_dev_open(&device)); + + unsigned max_cores, max_warps, max_threads; + RT_CHECK(vx_dev_caps(device, VX_CAPS_MAX_CORES, &max_cores)); + RT_CHECK(vx_dev_caps(device, VX_CAPS_MAX_WARPS, &max_warps)); + RT_CHECK(vx_dev_caps(device, VX_CAPS_MAX_THREADS, &max_threads)); + + int num_points = count * max_cores * max_warps * max_threads; + size_t buf_size = num_points * sizeof(uint32_t); + + std::cout << "number of points: " << num_points << std::endl; + std::cout << "buffer size: " << std::hex << buf_size << std::dec << " bytes" << std::endl; + + // upload program + std::cout << "upload kernel" << std::endl; + RT_CHECK(vx_upload_kernel_file(device, kernel_file)); + + // allocate device memory + std::cout << "allocate device memory" << std::endl; + + RT_CHECK(vx_alloc_dev_mem(device, buf_size, &value)); + kernel_arg.src0_ptr = value; + RT_CHECK(vx_alloc_dev_mem(device, buf_size, &value)); + kernel_arg.src1_ptr = value; + RT_CHECK(vx_alloc_dev_mem(device, buf_size, &value)); + kernel_arg.dst_ptr = value; + + kernel_arg.count = count; + + std::cout << "dev_src0=" << std::hex << kernel_arg.src0_ptr << std::dec << std::endl; + std::cout << "dev_src1=" << std::hex << kernel_arg.src1_ptr << std::dec << std::endl; + std::cout << "dev_dst=" << std::hex << kernel_arg.dst_ptr << std::dec << std::endl; + + // allocate shared memory + std::cout << "allocate shared memory" << std::endl; + RT_CHECK(vx_alloc_shared_mem(device, sizeof(kernel_arg_t), &arg_buf)); + RT_CHECK(vx_alloc_shared_mem(device, buf_size, &src1_buf)); + RT_CHECK(vx_alloc_shared_mem(device, buf_size, &src2_buf)); + RT_CHECK(vx_alloc_shared_mem(device, buf_size, &dst_buf)); + + for (int t = testid_s; t <= testid_e; ++t) { + auto name = testMngr.get_name(t); + auto test = testMngr.get_test(t); + + std::cout << "Test" << t << ": " << name << std::endl; + + // upload kernel argument + std::cout << "upload kernel argument" << std::endl; + kernel_arg.testid = t; + memcpy((void*)vx_host_ptr(arg_buf), &kernel_arg, sizeof(kernel_arg_t)); + RT_CHECK(vx_copy_to_dev(arg_buf, KERNEL_ARG_DEV_MEM_ADDR, sizeof(kernel_arg_t), 0)); + + // get test arguments + std::cout << "get test arguments" << std::endl; + test->setup(num_points, (void*)vx_host_ptr(src1_buf), (void*)vx_host_ptr(src2_buf)); + + // upload source buffer0 + std::cout << "upload source buffer0" << std::endl; + RT_CHECK(vx_copy_to_dev(src1_buf, kernel_arg.src0_ptr, buf_size, 0)); + + // upload source buffer1 + std::cout << "upload source buffer1" << std::endl; + RT_CHECK(vx_copy_to_dev(src2_buf, kernel_arg.src1_ptr, buf_size, 0)); + + // clear destination buffer + std::cout << "clear destination buffer" << std::endl; + for (int i = 0; i < num_points; ++i) { + ((uint32_t*)vx_host_ptr(dst_buf))[i] = 0xdeadbeef; + } + RT_CHECK(vx_copy_to_dev(dst_buf, kernel_arg.dst_ptr, buf_size, 0)); + + // start device + std::cout << "start device" << std::endl; + RT_CHECK(vx_start(device)); + + // wait for completion + std::cout << "wait for completion" << std::endl; + RT_CHECK(vx_ready_wait(device, -1)); + + // flush the destination buffer caches + std::cout << "flush the destination buffer caches" << std::endl; + RT_CHECK(vx_flush_caches(device, kernel_arg.dst_ptr, buf_size)); + + // download destination buffer + std::cout << "download destination buffer" << std::endl; + RT_CHECK(vx_copy_from_dev(dst_buf, kernel_arg.dst_ptr, buf_size, 0)); + + // verify destination + std::cout << "verify test result" << std::endl; + int errors = test->verify(num_points, + (void*)vx_host_ptr(dst_buf), + (void*)vx_host_ptr(src1_buf), + (void*)vx_host_ptr(src2_buf)); + if (errors != 0) { + std::cout << "found " << errors << " errors!" << std::endl; + std::cout << "Test" << t << "-" << name << " FAILED!" << std::endl << std::flush; + if (stop_on_error) { + cleanup(); + exit(1); + } + exitcode = 1; + } else { + std::cout << "Test" << t << "-" << name << " PASSED!" << std::endl << std::flush; + } + } + + // cleanup + std::cout << "cleanup" << std::endl; + cleanup(); + + return exitcode; +} \ No newline at end of file diff --git a/driver/tests/dogfood/kernel.bin b/driver/tests/dogfood/kernel.bin new file mode 100755 index 00000000..c7e138bf Binary files /dev/null and b/driver/tests/dogfood/kernel.bin differ diff --git a/driver/tests/dogfood/kernel.c b/driver/tests/dogfood/kernel.c new file mode 100644 index 00000000..d902b5e8 --- /dev/null +++ b/driver/tests/dogfood/kernel.c @@ -0,0 +1,350 @@ +#include +#include +#include +#include +#include "common.h" + +typedef void (*PFN_Kernel)(void* arg); + +void kernel_iadd(void* arg) { + struct kernel_arg_t* _arg = (struct kernel_arg_t*)(arg); + uint32_t count = _arg->count; + int32_t* src0_ptr = (int32_t*)_arg->src0_ptr; + int32_t* src1_ptr = (int32_t*)_arg->src1_ptr; + int32_t* dst_ptr = (int32_t*)_arg->dst_ptr; + uint32_t offset = vx_thread_gid() * count; + + for (uint32_t i = 0; i < count; ++i) { + int32_t a = src0_ptr[offset+i]; + int32_t b = src1_ptr[offset+i]; + int32_t c = a + b; + dst_ptr[offset+i] = c; + } +} + +void kernel_imul(void* arg) { + struct kernel_arg_t* _arg = (struct kernel_arg_t*)(arg); + uint32_t count = _arg->count; + int32_t* src0_ptr = (int32_t*)_arg->src0_ptr; + int32_t* src1_ptr = (int32_t*)_arg->src1_ptr; + int32_t* dst_ptr = (int32_t*)_arg->dst_ptr; + uint32_t offset = vx_thread_gid() * count; + + for (uint32_t i = 0; i < count; ++i) { + int32_t a = src0_ptr[offset+i]; + int32_t b = src1_ptr[offset+i]; + int32_t c = a * b; + dst_ptr[offset+i] = c; + } +} + +void kernel_idiv(void* arg) { + struct kernel_arg_t* _arg = (struct kernel_arg_t*)(arg); + uint32_t count = _arg->count; + int32_t* src0_ptr = (int32_t*)_arg->src0_ptr; + int32_t* src1_ptr = (int32_t*)_arg->src1_ptr; + int32_t* dst_ptr = (int32_t*)_arg->dst_ptr; + uint32_t offset = vx_thread_gid() * count; + + for (uint32_t i = 0; i < count; ++i) { + int32_t a = src0_ptr[offset+i]; + int32_t b = src1_ptr[offset+i]; + int32_t c = a / b; + dst_ptr[offset+i] = c; + } +} + +void kernel_idiv_mul(void* arg) { + struct kernel_arg_t* _arg = (struct kernel_arg_t*)(arg); + uint32_t count = _arg->count; + int32_t* src0_ptr = (int32_t*)_arg->src0_ptr; + int32_t* src1_ptr = (int32_t*)_arg->src1_ptr; + int32_t* dst_ptr = (int32_t*)_arg->dst_ptr; + uint32_t offset = vx_thread_gid() * count; + + for (uint32_t i = 0; i < count; ++i) { + int32_t a = src0_ptr[offset+i]; + int32_t b = src1_ptr[offset+i]; + int32_t c = a / b; + int32_t d = a * b; + int32_t e = c + d; + dst_ptr[offset+i] = e; + } +} + +void kernel_fadd(void* arg) { + struct kernel_arg_t* _arg = (struct kernel_arg_t*)(arg); + uint32_t count = _arg->count; + float* src0_ptr = (float*)_arg->src0_ptr; + float* src1_ptr = (float*)_arg->src1_ptr; + float* dst_ptr = (float*)_arg->dst_ptr; + uint32_t offset = vx_thread_gid() * count; + + for (uint32_t i = 0; i < count; ++i) { + float a = src0_ptr[offset+i]; + float b = src1_ptr[offset+i]; + float c = a + b; + dst_ptr[offset+i] = c; + } +} + +void kernel_fsub(void* arg) { + struct kernel_arg_t* _arg = (struct kernel_arg_t*)(arg); + uint32_t count = _arg->count; + float* src0_ptr = (float*)_arg->src0_ptr; + float* src1_ptr = (float*)_arg->src1_ptr; + float* dst_ptr = (float*)_arg->dst_ptr; + uint32_t offset = vx_thread_gid() * count; + + for (uint32_t i = 0; i < count; ++i) { + float a = src0_ptr[offset+i]; + float b = src1_ptr[offset+i]; + float c = a - b; + dst_ptr[offset+i] = c; + } +} + +void kernel_fmul(void* arg) { + struct kernel_arg_t* _arg = (struct kernel_arg_t*)(arg); + uint32_t count = _arg->count; + float* src0_ptr = (float*)_arg->src0_ptr; + float* src1_ptr = (float*)_arg->src1_ptr; + float* dst_ptr = (float*)_arg->dst_ptr; + uint32_t offset = vx_thread_gid() * count; + + for (uint32_t i = 0; i < count; ++i) { + float a = src0_ptr[offset+i]; + float b = src1_ptr[offset+i]; + float c = a * b; + dst_ptr[offset+i] = c; + } +} + +void kernel_fmadd(void* arg) { + struct kernel_arg_t* _arg = (struct kernel_arg_t*)(arg); + uint32_t count = _arg->count; + float* src0_ptr = (float*)_arg->src0_ptr; + float* src1_ptr = (float*)_arg->src1_ptr; + float* dst_ptr = (float*)_arg->dst_ptr; + uint32_t offset = vx_thread_gid() * count; + + for (uint32_t i = 0; i < count; ++i) { + float a = src0_ptr[offset+i]; + float b = src1_ptr[offset+i]; + float c = a * b + 0.5f; + dst_ptr[offset+i] = c; + } +} + +void kernel_fmsub(void* arg) { + struct kernel_arg_t* _arg = (struct kernel_arg_t*)(arg); + uint32_t count = _arg->count; + float* src0_ptr = (float*)_arg->src0_ptr; + float* src1_ptr = (float*)_arg->src1_ptr; + float* dst_ptr = (float*)_arg->dst_ptr; + uint32_t offset = vx_thread_gid() * count; + + for (uint32_t i = 0; i < count; ++i) { + float a = src0_ptr[offset+i]; + float b = src1_ptr[offset+i]; + float c = a * b - 0.5f; + dst_ptr[offset+i] = c; + } +} + +void kernel_fnmadd(void* arg) { + struct kernel_arg_t* _arg = (struct kernel_arg_t*)(arg); + uint32_t count = _arg->count; + float* src0_ptr = (float*)_arg->src0_ptr; + float* src1_ptr = (float*)_arg->src1_ptr; + float* dst_ptr = (float*)_arg->dst_ptr; + uint32_t offset = vx_thread_gid() * count; + + for (uint32_t i = 0; i < count; ++i) { + float a = src0_ptr[offset+i]; + float b = src1_ptr[offset+i]; + float c = -a * b - 0.5f; + dst_ptr[offset+i] = c; + } +} + +void kernel_fnmsub(void* arg) { + struct kernel_arg_t* _arg = (struct kernel_arg_t*)(arg); + uint32_t count = _arg->count; + float* src0_ptr = (float*)_arg->src0_ptr; + float* src1_ptr = (float*)_arg->src1_ptr; + float* dst_ptr = (float*)_arg->dst_ptr; + uint32_t offset = vx_thread_gid() * count; + + for (uint32_t i = 0; i < count; ++i) { + float a = src0_ptr[offset+i]; + float b = src1_ptr[offset+i]; + float c = -a * b + 0.5f; + dst_ptr[offset+i] = c; + } +} + +void kernel_fnmadd_madd(void* arg) { + struct kernel_arg_t* _arg = (struct kernel_arg_t*)(arg); + uint32_t count = _arg->count; + float* src0_ptr = (float*)_arg->src0_ptr; + float* src1_ptr = (float*)_arg->src1_ptr; + float* dst_ptr = (float*)_arg->dst_ptr; + uint32_t offset = vx_thread_gid() * count; + + for (uint32_t i = 0; i < count; ++i) { + float a = src0_ptr[offset+i]; + float b = src1_ptr[offset+i]; + float c =-a * b - 0.5f; + float d = a * b + 0.5f; + float e = c + d; + dst_ptr[offset+i] = e; + } +} + +void kernel_fdiv(void* arg) { + struct kernel_arg_t* _arg = (struct kernel_arg_t*)(arg); + uint32_t count = _arg->count; + float* src0_ptr = (float*)_arg->src0_ptr; + float* src1_ptr = (float*)_arg->src1_ptr; + float* dst_ptr = (float*)_arg->dst_ptr; + uint32_t offset = vx_thread_gid() * count; + + for (uint32_t i = 0; i < count; ++i) { + float a = src0_ptr[offset+i]; + float b = src1_ptr[offset+i]; + float c = a / b; + dst_ptr[offset+i] = c; + } +} + +void kernel_fdiv2(void* arg) { + struct kernel_arg_t* _arg = (struct kernel_arg_t*)(arg); + uint32_t count = _arg->count; + float* src0_ptr = (float*)_arg->src0_ptr; + float* src1_ptr = (float*)_arg->src1_ptr; + float* dst_ptr = (float*)_arg->dst_ptr; + uint32_t offset = vx_thread_gid() * count; + + for (uint32_t i = 0; i < count; ++i) { + float a = src0_ptr[offset+i]; + float b = src1_ptr[offset+i]; + float c = a / b; + float d = b / a; + float e = c + d; + dst_ptr[offset+i] = e; + } +} + +void kernel_fsqrt(void* arg) { + struct kernel_arg_t* _arg = (struct kernel_arg_t*)(arg); + uint32_t count = _arg->count; + float* src0_ptr = (float*)_arg->src0_ptr; + float* src1_ptr = (float*)_arg->src1_ptr; + float* dst_ptr = (float*)_arg->dst_ptr; + uint32_t offset = vx_thread_gid() * count; + + for (uint32_t i = 0; i < count; ++i) { + float a = src0_ptr[offset+i]; + float b = src1_ptr[offset+i]; + float c = sqrtf(a * b); + dst_ptr[offset+i] = c; + } +} + +void kernel_ftoi(void* arg) { + struct kernel_arg_t* _arg = (struct kernel_arg_t*)(arg); + uint32_t count = _arg->count; + float* src0_ptr = (float*)_arg->src0_ptr; + float* src1_ptr = (float*)_arg->src1_ptr; + int32_t* dst_ptr = (int32_t*)_arg->dst_ptr; + uint32_t offset = vx_thread_gid() * count; + + for (uint32_t i = 0; i < count; ++i) { + float a = src0_ptr[offset+i]; + float b = src1_ptr[offset+i]; + float c = a + b; + int32_t d = (int32_t)c; + dst_ptr[offset+i] = d; + } +} + +void kernel_ftou(void* arg) { + struct kernel_arg_t* _arg = (struct kernel_arg_t*)(arg); + uint32_t count = _arg->count; + float* src0_ptr = (float*)_arg->src0_ptr; + float* src1_ptr = (float*)_arg->src1_ptr; + uint32_t* dst_ptr = (uint32_t*)_arg->dst_ptr; + uint32_t offset = vx_thread_gid() * count; + + for (uint32_t i = 0; i < count; ++i) { + float a = src0_ptr[offset+i]; + float b = src1_ptr[offset+i]; + float c = a + b; + uint32_t d = (uint32_t)c; + dst_ptr[offset+i] = d; + } +} + +void kernel_itof(void* arg) { + struct kernel_arg_t* _arg = (struct kernel_arg_t*)(arg); + uint32_t count = _arg->count; + int32_t* src0_ptr = (int32_t*)_arg->src0_ptr; + int32_t* src1_ptr = (int32_t*)_arg->src1_ptr; + float* dst_ptr = (float*)_arg->dst_ptr; + uint32_t offset = vx_thread_gid() * count; + + for (uint32_t i = 0; i < count; ++i) { + int32_t a = src0_ptr[offset+i]; + int32_t b = src1_ptr[offset+i]; + int32_t c = a + b; + float d = (float)c; + dst_ptr[offset+i] = d; + } +} + +void kernel_utof(void* arg) { + struct kernel_arg_t* _arg = (struct kernel_arg_t*)(arg); + uint32_t count = _arg->count; + int32_t* src0_ptr = (int32_t*)_arg->src0_ptr; + int32_t* src1_ptr = (int32_t*)_arg->src1_ptr; + float* dst_ptr = (float*)_arg->dst_ptr; + uint32_t offset = vx_thread_gid() * count; + + for (uint32_t i = 0; i < count; ++i) { + int32_t a = src0_ptr[offset+i]; + int32_t b = src1_ptr[offset+i]; + uint32_t c = a + b; + float d = (float)c; + dst_ptr[offset+i] = d; + } +} + +static const PFN_Kernel sc_tests[] = { + kernel_iadd, + kernel_imul, + kernel_idiv, + kernel_idiv_mul, + kernel_fadd, + kernel_fsub, + kernel_fmul, + kernel_fmadd, + kernel_fmsub, + kernel_fnmadd, + kernel_fnmsub, + kernel_fnmadd_madd, + kernel_fdiv, + kernel_fdiv2, + kernel_fsqrt, + kernel_ftoi, + kernel_ftou, + kernel_itof, + kernel_utof, +}; + +void main() { + struct kernel_arg_t* arg = (struct kernel_arg_t*)KERNEL_ARG_DEV_MEM_ADDR; + int num_warps = vx_num_warps(); + int num_threads = vx_num_threads(); + vx_spawn_warps(num_warps, num_threads, sc_tests[arg->testid], arg); +} \ No newline at end of file diff --git a/driver/tests/dogfood/kernel.dump b/driver/tests/dogfood/kernel.dump new file mode 100644 index 00000000..e8930fd2 --- /dev/null +++ b/driver/tests/dogfood/kernel.dump @@ -0,0 +1,19367 @@ + +kernel.elf: file format elf32-littleriscv + + +Disassembly of section .init: + +80000000 <_start>: +80000000: 00001597 auipc a1,0x1 +80000004: ba458593 addi a1,a1,-1116 # 80000ba4 +80000008: 02602573 csrr a0,0x26 +8000000c: 00b5106b 0xb5106b +80000010: 395000ef jal ra,80000ba4 +80000014: 00100513 li a0,1 +80000018: 0005006b 0x5006b +8000001c: c3818513 addi a0,gp,-968 # 800038a0 +80000020: c4018613 addi a2,gp,-960 # 800038a8 <__BSS_END__> +80000024: 40a60633 sub a2,a2,a0 +80000028: 00000593 li a1,0 +8000002c: 7e1010ef jal ra,8000200c +80000030: 00002517 auipc a0,0x2 +80000034: ee450513 addi a0,a0,-284 # 80001f14 <__libc_fini_array> +80000038: 691010ef jal ra,80001ec8 +8000003c: 735010ef jal ra,80001f70 <__libc_init_array> +80000040: 008000ef jal ra,80000048
+80000044: 6a10106f j 80001ee4 + +Disassembly of section .text: + +80000048
: +80000048: ff010113 addi sp,sp,-16 +8000004c: 00112623 sw ra,12(sp) +80000050: 00812423 sw s0,8(sp) +80000054: 3e9000ef jal ra,80000c3c +80000058: 00050413 mv s0,a0 +8000005c: 3d9000ef jal ra,80000c34 +80000060: 7ffff7b7 lui a5,0x7ffff +80000064: 0007a783 lw a5,0(a5) # 7ffff000 <_start-0x1000> +80000068: 00050593 mv a1,a0 +8000006c: 00040513 mv a0,s0 +80000070: 00279713 slli a4,a5,0x2 +80000074: 800027b7 lui a5,0x80002 +80000078: 2a078793 addi a5,a5,672 # 800022a0 <__global_pointer$+0xffffe638> +8000007c: 00812403 lw s0,8(sp) +80000080: 00e787b3 add a5,a5,a4 +80000084: 00c12083 lw ra,12(sp) +80000088: 0007a603 lw a2,0(a5) +8000008c: 7ffff6b7 lui a3,0x7ffff +80000090: 01010113 addi sp,sp,16 +80000094: 4090006f j 80000c9c + +80000098 : +80000098: 00000793 li a5,0 +8000009c: 00078863 beqz a5,800000ac +800000a0: 80002537 lui a0,0x80002 +800000a4: f1450513 addi a0,a0,-236 # 80001f14 <__global_pointer$+0xffffe2ac> +800000a8: 6210106f j 80001ec8 +800000ac: 00008067 ret + +800000b0 : +800000b0: fe010113 addi sp,sp,-32 +800000b4: 00812c23 sw s0,24(sp) +800000b8: 00452403 lw s0,4(a0) +800000bc: 00912a23 sw s1,20(sp) +800000c0: 01212823 sw s2,16(sp) +800000c4: 01312623 sw s3,12(sp) +800000c8: 00c52483 lw s1,12(a0) +800000cc: 00852983 lw s3,8(a0) +800000d0: 01052903 lw s2,16(a0) +800000d4: 00112e23 sw ra,28(sp) +800000d8: 34d000ef jal ra,80000c24 +800000dc: 02850533 mul a0,a0,s0 +800000e0: 04040063 beqz s0,80000120 +800000e4: 00a406b3 add a3,s0,a0 +800000e8: 00269693 slli a3,a3,0x2 +800000ec: 00251513 slli a0,a0,0x2 +800000f0: 013507b3 add a5,a0,s3 +800000f4: 013686b3 add a3,a3,s3 +800000f8: 41390833 sub a6,s2,s3 +800000fc: 41348533 sub a0,s1,s3 +80000100: 00f50733 add a4,a0,a5 +80000104: 0007a583 lw a1,0(a5) +80000108: 00072703 lw a4,0(a4) +8000010c: 00f80633 add a2,a6,a5 +80000110: 00478793 addi a5,a5,4 +80000114: 00b70733 add a4,a4,a1 +80000118: 00e62023 sw a4,0(a2) +8000011c: fef692e3 bne a3,a5,80000100 +80000120: 01c12083 lw ra,28(sp) +80000124: 01812403 lw s0,24(sp) +80000128: 01412483 lw s1,20(sp) +8000012c: 01012903 lw s2,16(sp) +80000130: 00c12983 lw s3,12(sp) +80000134: 02010113 addi sp,sp,32 +80000138: 00008067 ret + +8000013c : +8000013c: fe010113 addi sp,sp,-32 +80000140: 00812c23 sw s0,24(sp) +80000144: 00452403 lw s0,4(a0) +80000148: 00912a23 sw s1,20(sp) +8000014c: 01212823 sw s2,16(sp) +80000150: 01312623 sw s3,12(sp) +80000154: 00c52483 lw s1,12(a0) +80000158: 00852983 lw s3,8(a0) +8000015c: 01052903 lw s2,16(a0) +80000160: 00112e23 sw ra,28(sp) +80000164: 2c1000ef jal ra,80000c24 +80000168: 02850533 mul a0,a0,s0 +8000016c: 04040063 beqz s0,800001ac +80000170: 00a406b3 add a3,s0,a0 +80000174: 00269693 slli a3,a3,0x2 +80000178: 00251513 slli a0,a0,0x2 +8000017c: 013507b3 add a5,a0,s3 +80000180: 013686b3 add a3,a3,s3 +80000184: 41390833 sub a6,s2,s3 +80000188: 41348533 sub a0,s1,s3 +8000018c: 00f50733 add a4,a0,a5 +80000190: 0007a583 lw a1,0(a5) +80000194: 00072703 lw a4,0(a4) +80000198: 00f80633 add a2,a6,a5 +8000019c: 00478793 addi a5,a5,4 +800001a0: 02b70733 mul a4,a4,a1 +800001a4: 00e62023 sw a4,0(a2) +800001a8: fef692e3 bne a3,a5,8000018c +800001ac: 01c12083 lw ra,28(sp) +800001b0: 01812403 lw s0,24(sp) +800001b4: 01412483 lw s1,20(sp) +800001b8: 01012903 lw s2,16(sp) +800001bc: 00c12983 lw s3,12(sp) +800001c0: 02010113 addi sp,sp,32 +800001c4: 00008067 ret + +800001c8 : +800001c8: fe010113 addi sp,sp,-32 +800001cc: 00812c23 sw s0,24(sp) +800001d0: 00452403 lw s0,4(a0) +800001d4: 00912a23 sw s1,20(sp) +800001d8: 01212823 sw s2,16(sp) +800001dc: 01312623 sw s3,12(sp) +800001e0: 00c52483 lw s1,12(a0) +800001e4: 00852983 lw s3,8(a0) +800001e8: 01052903 lw s2,16(a0) +800001ec: 00112e23 sw ra,28(sp) +800001f0: 235000ef jal ra,80000c24 +800001f4: 02850533 mul a0,a0,s0 +800001f8: 04040063 beqz s0,80000238 +800001fc: 00a406b3 add a3,s0,a0 +80000200: 00269693 slli a3,a3,0x2 +80000204: 00251513 slli a0,a0,0x2 +80000208: 013507b3 add a5,a0,s3 +8000020c: 013686b3 add a3,a3,s3 +80000210: 41390833 sub a6,s2,s3 +80000214: 41348533 sub a0,s1,s3 +80000218: 00f50633 add a2,a0,a5 +8000021c: 0007a703 lw a4,0(a5) +80000220: 00062583 lw a1,0(a2) +80000224: 00f80633 add a2,a6,a5 +80000228: 00478793 addi a5,a5,4 +8000022c: 02b74733 div a4,a4,a1 +80000230: 00e62023 sw a4,0(a2) +80000234: fef692e3 bne a3,a5,80000218 +80000238: 01c12083 lw ra,28(sp) +8000023c: 01812403 lw s0,24(sp) +80000240: 01412483 lw s1,20(sp) +80000244: 01012903 lw s2,16(sp) +80000248: 00c12983 lw s3,12(sp) +8000024c: 02010113 addi sp,sp,32 +80000250: 00008067 ret + +80000254 : +80000254: fe010113 addi sp,sp,-32 +80000258: 00812c23 sw s0,24(sp) +8000025c: 00452403 lw s0,4(a0) +80000260: 00912a23 sw s1,20(sp) +80000264: 01212823 sw s2,16(sp) +80000268: 01312623 sw s3,12(sp) +8000026c: 00c52903 lw s2,12(a0) +80000270: 00852983 lw s3,8(a0) +80000274: 01052483 lw s1,16(a0) +80000278: 00112e23 sw ra,28(sp) +8000027c: 1a9000ef jal ra,80000c24 +80000280: 02850533 mul a0,a0,s0 +80000284: 04040463 beqz s0,800002cc +80000288: 00a405b3 add a1,s0,a0 +8000028c: 00259593 slli a1,a1,0x2 +80000290: 00251513 slli a0,a0,0x2 +80000294: 013507b3 add a5,a0,s3 +80000298: 013585b3 add a1,a1,s3 +8000029c: 413908b3 sub a7,s2,s3 +800002a0: 41348833 sub a6,s1,s3 +800002a4: 00f886b3 add a3,a7,a5 +800002a8: 0007a703 lw a4,0(a5) +800002ac: 0006a603 lw a2,0(a3) # 7ffff000 <_start-0x1000> +800002b0: 00f80533 add a0,a6,a5 +800002b4: 00478793 addi a5,a5,4 +800002b8: 02c746b3 div a3,a4,a2 +800002bc: 02c70733 mul a4,a4,a2 +800002c0: 00e68733 add a4,a3,a4 +800002c4: 00e52023 sw a4,0(a0) +800002c8: fcf59ee3 bne a1,a5,800002a4 +800002cc: 01c12083 lw ra,28(sp) +800002d0: 01812403 lw s0,24(sp) +800002d4: 01412483 lw s1,20(sp) +800002d8: 01012903 lw s2,16(sp) +800002dc: 00c12983 lw s3,12(sp) +800002e0: 02010113 addi sp,sp,32 +800002e4: 00008067 ret + +800002e8 : +800002e8: fe010113 addi sp,sp,-32 +800002ec: 00812c23 sw s0,24(sp) +800002f0: 00452403 lw s0,4(a0) +800002f4: 00912a23 sw s1,20(sp) +800002f8: 01212823 sw s2,16(sp) +800002fc: 01312623 sw s3,12(sp) +80000300: 00c52483 lw s1,12(a0) +80000304: 00852983 lw s3,8(a0) +80000308: 01052903 lw s2,16(a0) +8000030c: 00112e23 sw ra,28(sp) +80000310: 115000ef jal ra,80000c24 +80000314: 02850533 mul a0,a0,s0 +80000318: 04040063 beqz s0,80000358 +8000031c: 00a40733 add a4,s0,a0 +80000320: 00271713 slli a4,a4,0x2 +80000324: 00251513 slli a0,a0,0x2 +80000328: 013507b3 add a5,a0,s3 +8000032c: 01370733 add a4,a4,s3 +80000330: 413905b3 sub a1,s2,s3 +80000334: 41348633 sub a2,s1,s3 +80000338: 00f606b3 add a3,a2,a5 +8000033c: 0007a707 flw fa4,0(a5) +80000340: 0006a787 flw fa5,0(a3) +80000344: 00f586b3 add a3,a1,a5 +80000348: 00478793 addi a5,a5,4 +8000034c: 00e7f7d3 fadd.s fa5,fa5,fa4 +80000350: 00f6a027 fsw fa5,0(a3) +80000354: fef712e3 bne a4,a5,80000338 +80000358: 01c12083 lw ra,28(sp) +8000035c: 01812403 lw s0,24(sp) +80000360: 01412483 lw s1,20(sp) +80000364: 01012903 lw s2,16(sp) +80000368: 00c12983 lw s3,12(sp) +8000036c: 02010113 addi sp,sp,32 +80000370: 00008067 ret + +80000374 : +80000374: fe010113 addi sp,sp,-32 +80000378: 00812c23 sw s0,24(sp) +8000037c: 00452403 lw s0,4(a0) +80000380: 00912a23 sw s1,20(sp) +80000384: 01212823 sw s2,16(sp) +80000388: 01312623 sw s3,12(sp) +8000038c: 00c52483 lw s1,12(a0) +80000390: 00852983 lw s3,8(a0) +80000394: 01052903 lw s2,16(a0) +80000398: 00112e23 sw ra,28(sp) +8000039c: 089000ef jal ra,80000c24 +800003a0: 02850533 mul a0,a0,s0 +800003a4: 04040063 beqz s0,800003e4 +800003a8: 00a40733 add a4,s0,a0 +800003ac: 00271713 slli a4,a4,0x2 +800003b0: 00251513 slli a0,a0,0x2 +800003b4: 013507b3 add a5,a0,s3 +800003b8: 01370733 add a4,a4,s3 +800003bc: 413905b3 sub a1,s2,s3 +800003c0: 41348633 sub a2,s1,s3 +800003c4: 00f606b3 add a3,a2,a5 +800003c8: 0007a787 flw fa5,0(a5) +800003cc: 0006a707 flw fa4,0(a3) +800003d0: 00f586b3 add a3,a1,a5 +800003d4: 00478793 addi a5,a5,4 +800003d8: 08e7f7d3 fsub.s fa5,fa5,fa4 +800003dc: 00f6a027 fsw fa5,0(a3) +800003e0: fef712e3 bne a4,a5,800003c4 +800003e4: 01c12083 lw ra,28(sp) +800003e8: 01812403 lw s0,24(sp) +800003ec: 01412483 lw s1,20(sp) +800003f0: 01012903 lw s2,16(sp) +800003f4: 00c12983 lw s3,12(sp) +800003f8: 02010113 addi sp,sp,32 +800003fc: 00008067 ret + +80000400 : +80000400: fe010113 addi sp,sp,-32 +80000404: 00812c23 sw s0,24(sp) +80000408: 00452403 lw s0,4(a0) +8000040c: 00912a23 sw s1,20(sp) +80000410: 01212823 sw s2,16(sp) +80000414: 01312623 sw s3,12(sp) +80000418: 00c52483 lw s1,12(a0) +8000041c: 00852983 lw s3,8(a0) +80000420: 01052903 lw s2,16(a0) +80000424: 00112e23 sw ra,28(sp) +80000428: 7fc000ef jal ra,80000c24 +8000042c: 02850533 mul a0,a0,s0 +80000430: 04040063 beqz s0,80000470 +80000434: 00a40733 add a4,s0,a0 +80000438: 00271713 slli a4,a4,0x2 +8000043c: 00251513 slli a0,a0,0x2 +80000440: 013507b3 add a5,a0,s3 +80000444: 01370733 add a4,a4,s3 +80000448: 413905b3 sub a1,s2,s3 +8000044c: 41348633 sub a2,s1,s3 +80000450: 00f606b3 add a3,a2,a5 +80000454: 0007a707 flw fa4,0(a5) +80000458: 0006a787 flw fa5,0(a3) +8000045c: 00f586b3 add a3,a1,a5 +80000460: 00478793 addi a5,a5,4 +80000464: 10e7f7d3 fmul.s fa5,fa5,fa4 +80000468: 00f6a027 fsw fa5,0(a3) +8000046c: fef712e3 bne a4,a5,80000450 +80000470: 01c12083 lw ra,28(sp) +80000474: 01812403 lw s0,24(sp) +80000478: 01412483 lw s1,20(sp) +8000047c: 01012903 lw s2,16(sp) +80000480: 00c12983 lw s3,12(sp) +80000484: 02010113 addi sp,sp,32 +80000488: 00008067 ret + +8000048c : +8000048c: fe010113 addi sp,sp,-32 +80000490: 00812c23 sw s0,24(sp) +80000494: 00452403 lw s0,4(a0) +80000498: 00912a23 sw s1,20(sp) +8000049c: 01212823 sw s2,16(sp) +800004a0: 01312623 sw s3,12(sp) +800004a4: 00c52903 lw s2,12(a0) +800004a8: 00852983 lw s3,8(a0) +800004ac: 01052483 lw s1,16(a0) +800004b0: 00112e23 sw ra,28(sp) +800004b4: 770000ef jal ra,80000c24 +800004b8: 02850533 mul a0,a0,s0 +800004bc: 04040263 beqz s0,80000500 +800004c0: 00a40733 add a4,s0,a0 +800004c4: 00251513 slli a0,a0,0x2 +800004c8: 00271713 slli a4,a4,0x2 +800004cc: c281a687 flw fa3,-984(gp) # 80003890 <__SDATA_BEGIN__> +800004d0: 01370733 add a4,a4,s3 +800004d4: 013507b3 add a5,a0,s3 +800004d8: 413905b3 sub a1,s2,s3 +800004dc: 41348633 sub a2,s1,s3 +800004e0: 00f586b3 add a3,a1,a5 +800004e4: 0007a787 flw fa5,0(a5) +800004e8: 0006a707 flw fa4,0(a3) +800004ec: 00f606b3 add a3,a2,a5 +800004f0: 00478793 addi a5,a5,4 +800004f4: 68e7f7c3 fmadd.s fa5,fa5,fa4,fa3 +800004f8: 00f6a027 fsw fa5,0(a3) +800004fc: fef712e3 bne a4,a5,800004e0 +80000500: 01c12083 lw ra,28(sp) +80000504: 01812403 lw s0,24(sp) +80000508: 01412483 lw s1,20(sp) +8000050c: 01012903 lw s2,16(sp) +80000510: 00c12983 lw s3,12(sp) +80000514: 02010113 addi sp,sp,32 +80000518: 00008067 ret + +8000051c : +8000051c: fe010113 addi sp,sp,-32 +80000520: 00812c23 sw s0,24(sp) +80000524: 00452403 lw s0,4(a0) +80000528: 00912a23 sw s1,20(sp) +8000052c: 01212823 sw s2,16(sp) +80000530: 01312623 sw s3,12(sp) +80000534: 00c52903 lw s2,12(a0) +80000538: 00852983 lw s3,8(a0) +8000053c: 01052483 lw s1,16(a0) +80000540: 00112e23 sw ra,28(sp) +80000544: 6e0000ef jal ra,80000c24 +80000548: 02850533 mul a0,a0,s0 +8000054c: 04040263 beqz s0,80000590 +80000550: 00a40733 add a4,s0,a0 +80000554: 00251513 slli a0,a0,0x2 +80000558: 00271713 slli a4,a4,0x2 +8000055c: c2c1a687 flw fa3,-980(gp) # 80003894 <__SDATA_BEGIN__+0x4> +80000560: 01370733 add a4,a4,s3 +80000564: 013507b3 add a5,a0,s3 +80000568: 413905b3 sub a1,s2,s3 +8000056c: 41348633 sub a2,s1,s3 +80000570: 00f586b3 add a3,a1,a5 +80000574: 0007a787 flw fa5,0(a5) +80000578: 0006a707 flw fa4,0(a3) +8000057c: 00f606b3 add a3,a2,a5 +80000580: 00478793 addi a5,a5,4 +80000584: 68e7f7c3 fmadd.s fa5,fa5,fa4,fa3 +80000588: 00f6a027 fsw fa5,0(a3) +8000058c: fef712e3 bne a4,a5,80000570 +80000590: 01c12083 lw ra,28(sp) +80000594: 01812403 lw s0,24(sp) +80000598: 01412483 lw s1,20(sp) +8000059c: 01012903 lw s2,16(sp) +800005a0: 00c12983 lw s3,12(sp) +800005a4: 02010113 addi sp,sp,32 +800005a8: 00008067 ret + +800005ac : +800005ac: fe010113 addi sp,sp,-32 +800005b0: 00812c23 sw s0,24(sp) +800005b4: 00452403 lw s0,4(a0) +800005b8: 00912a23 sw s1,20(sp) +800005bc: 01212823 sw s2,16(sp) +800005c0: 01312623 sw s3,12(sp) +800005c4: 00c52903 lw s2,12(a0) +800005c8: 00852983 lw s3,8(a0) +800005cc: 01052483 lw s1,16(a0) +800005d0: 00112e23 sw ra,28(sp) +800005d4: 650000ef jal ra,80000c24 +800005d8: 02850533 mul a0,a0,s0 +800005dc: 04040263 beqz s0,80000620 +800005e0: 00a40733 add a4,s0,a0 +800005e4: 00251513 slli a0,a0,0x2 +800005e8: 00271713 slli a4,a4,0x2 +800005ec: c2c1a687 flw fa3,-980(gp) # 80003894 <__SDATA_BEGIN__+0x4> +800005f0: 01370733 add a4,a4,s3 +800005f4: 013507b3 add a5,a0,s3 +800005f8: 413905b3 sub a1,s2,s3 +800005fc: 41348633 sub a2,s1,s3 +80000600: 00f586b3 add a3,a1,a5 +80000604: 0007a787 flw fa5,0(a5) +80000608: 0006a707 flw fa4,0(a3) +8000060c: 00f606b3 add a3,a2,a5 +80000610: 00478793 addi a5,a5,4 +80000614: 68e7f7cb fnmsub.s fa5,fa5,fa4,fa3 +80000618: 00f6a027 fsw fa5,0(a3) +8000061c: fef712e3 bne a4,a5,80000600 +80000620: 01c12083 lw ra,28(sp) +80000624: 01812403 lw s0,24(sp) +80000628: 01412483 lw s1,20(sp) +8000062c: 01012903 lw s2,16(sp) +80000630: 00c12983 lw s3,12(sp) +80000634: 02010113 addi sp,sp,32 +80000638: 00008067 ret + +8000063c : +8000063c: fe010113 addi sp,sp,-32 +80000640: 00812c23 sw s0,24(sp) +80000644: 00452403 lw s0,4(a0) +80000648: 00912a23 sw s1,20(sp) +8000064c: 01212823 sw s2,16(sp) +80000650: 01312623 sw s3,12(sp) +80000654: 00c52903 lw s2,12(a0) +80000658: 00852983 lw s3,8(a0) +8000065c: 01052483 lw s1,16(a0) +80000660: 00112e23 sw ra,28(sp) +80000664: 5c0000ef jal ra,80000c24 +80000668: 02850533 mul a0,a0,s0 +8000066c: 04040263 beqz s0,800006b0 +80000670: 00a40733 add a4,s0,a0 +80000674: 00251513 slli a0,a0,0x2 +80000678: 00271713 slli a4,a4,0x2 +8000067c: c281a687 flw fa3,-984(gp) # 80003890 <__SDATA_BEGIN__> +80000680: 01370733 add a4,a4,s3 +80000684: 013507b3 add a5,a0,s3 +80000688: 413905b3 sub a1,s2,s3 +8000068c: 41348633 sub a2,s1,s3 +80000690: 00f586b3 add a3,a1,a5 +80000694: 0007a787 flw fa5,0(a5) +80000698: 0006a707 flw fa4,0(a3) +8000069c: 00f606b3 add a3,a2,a5 +800006a0: 00478793 addi a5,a5,4 +800006a4: 68e7f7cb fnmsub.s fa5,fa5,fa4,fa3 +800006a8: 00f6a027 fsw fa5,0(a3) +800006ac: fef712e3 bne a4,a5,80000690 +800006b0: 01c12083 lw ra,28(sp) +800006b4: 01812403 lw s0,24(sp) +800006b8: 01412483 lw s1,20(sp) +800006bc: 01012903 lw s2,16(sp) +800006c0: 00c12983 lw s3,12(sp) +800006c4: 02010113 addi sp,sp,32 +800006c8: 00008067 ret + +800006cc : +800006cc: fe010113 addi sp,sp,-32 +800006d0: 00812c23 sw s0,24(sp) +800006d4: 00452403 lw s0,4(a0) +800006d8: 00912a23 sw s1,20(sp) +800006dc: 01212823 sw s2,16(sp) +800006e0: 01312623 sw s3,12(sp) +800006e4: 00c52903 lw s2,12(a0) +800006e8: 00852983 lw s3,8(a0) +800006ec: 01052483 lw s1,16(a0) +800006f0: 00112e23 sw ra,28(sp) +800006f4: 530000ef jal ra,80000c24 +800006f8: 02850533 mul a0,a0,s0 +800006fc: 04040863 beqz s0,8000074c +80000700: 00a40733 add a4,s0,a0 +80000704: c2c1a587 flw fa1,-980(gp) # 80003894 <__SDATA_BEGIN__+0x4> +80000708: 00251513 slli a0,a0,0x2 +8000070c: 00271713 slli a4,a4,0x2 +80000710: c281a607 flw fa2,-984(gp) # 80003890 <__SDATA_BEGIN__> +80000714: 01370733 add a4,a4,s3 +80000718: 013507b3 add a5,a0,s3 +8000071c: 413905b3 sub a1,s2,s3 +80000720: 41348633 sub a2,s1,s3 +80000724: 00f586b3 add a3,a1,a5 +80000728: 0007a787 flw fa5,0(a5) +8000072c: 0006a687 flw fa3,0(a3) +80000730: 00f606b3 add a3,a2,a5 +80000734: 00478793 addi a5,a5,4 +80000738: 58d7f74b fnmsub.s fa4,fa5,fa3,fa1 +8000073c: 60d7f7c3 fmadd.s fa5,fa5,fa3,fa2 +80000740: 00f777d3 fadd.s fa5,fa4,fa5 +80000744: 00f6a027 fsw fa5,0(a3) +80000748: fcf71ee3 bne a4,a5,80000724 +8000074c: 01c12083 lw ra,28(sp) +80000750: 01812403 lw s0,24(sp) +80000754: 01412483 lw s1,20(sp) +80000758: 01012903 lw s2,16(sp) +8000075c: 00c12983 lw s3,12(sp) +80000760: 02010113 addi sp,sp,32 +80000764: 00008067 ret + +80000768 : +80000768: fe010113 addi sp,sp,-32 +8000076c: 00812c23 sw s0,24(sp) +80000770: 00452403 lw s0,4(a0) +80000774: 00912a23 sw s1,20(sp) +80000778: 01212823 sw s2,16(sp) +8000077c: 01312623 sw s3,12(sp) +80000780: 00c52483 lw s1,12(a0) +80000784: 00852983 lw s3,8(a0) +80000788: 01052903 lw s2,16(a0) +8000078c: 00112e23 sw ra,28(sp) +80000790: 494000ef jal ra,80000c24 +80000794: 02850533 mul a0,a0,s0 +80000798: 04040063 beqz s0,800007d8 +8000079c: 00a40733 add a4,s0,a0 +800007a0: 00271713 slli a4,a4,0x2 +800007a4: 00251513 slli a0,a0,0x2 +800007a8: 013507b3 add a5,a0,s3 +800007ac: 01370733 add a4,a4,s3 +800007b0: 413905b3 sub a1,s2,s3 +800007b4: 41348633 sub a2,s1,s3 +800007b8: 00f606b3 add a3,a2,a5 +800007bc: 0007a787 flw fa5,0(a5) +800007c0: 0006a707 flw fa4,0(a3) +800007c4: 00f586b3 add a3,a1,a5 +800007c8: 00478793 addi a5,a5,4 +800007cc: 18e7f7d3 fdiv.s fa5,fa5,fa4 +800007d0: 00f6a027 fsw fa5,0(a3) +800007d4: fef712e3 bne a4,a5,800007b8 +800007d8: 01c12083 lw ra,28(sp) +800007dc: 01812403 lw s0,24(sp) +800007e0: 01412483 lw s1,20(sp) +800007e4: 01012903 lw s2,16(sp) +800007e8: 00c12983 lw s3,12(sp) +800007ec: 02010113 addi sp,sp,32 +800007f0: 00008067 ret + +800007f4 : +800007f4: fe010113 addi sp,sp,-32 +800007f8: 00812c23 sw s0,24(sp) +800007fc: 00452403 lw s0,4(a0) +80000800: 00912a23 sw s1,20(sp) +80000804: 01212823 sw s2,16(sp) +80000808: 01312623 sw s3,12(sp) +8000080c: 00c52903 lw s2,12(a0) +80000810: 00852983 lw s3,8(a0) +80000814: 01052483 lw s1,16(a0) +80000818: 00112e23 sw ra,28(sp) +8000081c: 408000ef jal ra,80000c24 +80000820: 02850533 mul a0,a0,s0 +80000824: 04040463 beqz s0,8000086c +80000828: 00a40733 add a4,s0,a0 +8000082c: 00271713 slli a4,a4,0x2 +80000830: 00251513 slli a0,a0,0x2 +80000834: 013507b3 add a5,a0,s3 +80000838: 01370733 add a4,a4,s3 +8000083c: 413905b3 sub a1,s2,s3 +80000840: 41348633 sub a2,s1,s3 +80000844: 00f586b3 add a3,a1,a5 +80000848: 0007a687 flw fa3,0(a5) +8000084c: 0006a787 flw fa5,0(a3) +80000850: 00f606b3 add a3,a2,a5 +80000854: 00478793 addi a5,a5,4 +80000858: 18f6f753 fdiv.s fa4,fa3,fa5 +8000085c: 18d7f7d3 fdiv.s fa5,fa5,fa3 +80000860: 00f777d3 fadd.s fa5,fa4,fa5 +80000864: 00f6a027 fsw fa5,0(a3) +80000868: fcf71ee3 bne a4,a5,80000844 +8000086c: 01c12083 lw ra,28(sp) +80000870: 01812403 lw s0,24(sp) +80000874: 01412483 lw s1,20(sp) +80000878: 01012903 lw s2,16(sp) +8000087c: 00c12983 lw s3,12(sp) +80000880: 02010113 addi sp,sp,32 +80000884: 00008067 ret + +80000888 : +80000888: fe010113 addi sp,sp,-32 +8000088c: 00812c23 sw s0,24(sp) +80000890: 00452403 lw s0,4(a0) +80000894: 00912a23 sw s1,20(sp) +80000898: 01212823 sw s2,16(sp) +8000089c: 01312623 sw s3,12(sp) +800008a0: 00c52483 lw s1,12(a0) +800008a4: 00852983 lw s3,8(a0) +800008a8: 01052903 lw s2,16(a0) +800008ac: 00112e23 sw ra,28(sp) +800008b0: 374000ef jal ra,80000c24 +800008b4: 02850533 mul a0,a0,s0 +800008b8: 04040263 beqz s0,800008fc +800008bc: 00a406b3 add a3,s0,a0 +800008c0: 00269693 slli a3,a3,0x2 +800008c4: 00251513 slli a0,a0,0x2 +800008c8: 013507b3 add a5,a0,s3 +800008cc: 013686b3 add a3,a3,s3 +800008d0: 41390533 sub a0,s2,s3 +800008d4: 413485b3 sub a1,s1,s3 +800008d8: 00f58733 add a4,a1,a5 +800008dc: 0007a707 flw fa4,0(a5) +800008e0: 00072787 flw fa5,0(a4) +800008e4: 00f50633 add a2,a0,a5 +800008e8: 00478793 addi a5,a5,4 +800008ec: 00e7f7d3 fadd.s fa5,fa5,fa4 +800008f0: c0079753 fcvt.w.s a4,fa5,rtz +800008f4: 00e62023 sw a4,0(a2) +800008f8: fef690e3 bne a3,a5,800008d8 +800008fc: 01c12083 lw ra,28(sp) +80000900: 01812403 lw s0,24(sp) +80000904: 01412483 lw s1,20(sp) +80000908: 01012903 lw s2,16(sp) +8000090c: 00c12983 lw s3,12(sp) +80000910: 02010113 addi sp,sp,32 +80000914: 00008067 ret + +80000918 : +80000918: fe010113 addi sp,sp,-32 +8000091c: 00812c23 sw s0,24(sp) +80000920: 00452403 lw s0,4(a0) +80000924: 00912a23 sw s1,20(sp) +80000928: 01212823 sw s2,16(sp) +8000092c: 01312623 sw s3,12(sp) +80000930: 00c52483 lw s1,12(a0) +80000934: 00852983 lw s3,8(a0) +80000938: 01052903 lw s2,16(a0) +8000093c: 00112e23 sw ra,28(sp) +80000940: 2e4000ef jal ra,80000c24 +80000944: 02850533 mul a0,a0,s0 +80000948: 04040263 beqz s0,8000098c +8000094c: 00a406b3 add a3,s0,a0 +80000950: 00269693 slli a3,a3,0x2 +80000954: 00251513 slli a0,a0,0x2 +80000958: 013507b3 add a5,a0,s3 +8000095c: 013686b3 add a3,a3,s3 +80000960: 41390533 sub a0,s2,s3 +80000964: 413485b3 sub a1,s1,s3 +80000968: 00f58733 add a4,a1,a5 +8000096c: 0007a707 flw fa4,0(a5) +80000970: 00072787 flw fa5,0(a4) +80000974: 00f50633 add a2,a0,a5 +80000978: 00478793 addi a5,a5,4 +8000097c: 00e7f7d3 fadd.s fa5,fa5,fa4 +80000980: c0179753 fcvt.wu.s a4,fa5,rtz +80000984: 00e62023 sw a4,0(a2) +80000988: fef690e3 bne a3,a5,80000968 +8000098c: 01c12083 lw ra,28(sp) +80000990: 01812403 lw s0,24(sp) +80000994: 01412483 lw s1,20(sp) +80000998: 01012903 lw s2,16(sp) +8000099c: 00c12983 lw s3,12(sp) +800009a0: 02010113 addi sp,sp,32 +800009a4: 00008067 ret + +800009a8 : +800009a8: fe010113 addi sp,sp,-32 +800009ac: 00812c23 sw s0,24(sp) +800009b0: 00452403 lw s0,4(a0) +800009b4: 00912a23 sw s1,20(sp) +800009b8: 01212823 sw s2,16(sp) +800009bc: 01312623 sw s3,12(sp) +800009c0: 00c52483 lw s1,12(a0) +800009c4: 00852983 lw s3,8(a0) +800009c8: 01052903 lw s2,16(a0) +800009cc: 00112e23 sw ra,28(sp) +800009d0: 254000ef jal ra,80000c24 +800009d4: 02850533 mul a0,a0,s0 +800009d8: 04040263 beqz s0,80000a1c +800009dc: 00a406b3 add a3,s0,a0 +800009e0: 00269693 slli a3,a3,0x2 +800009e4: 00251513 slli a0,a0,0x2 +800009e8: 013507b3 add a5,a0,s3 +800009ec: 013686b3 add a3,a3,s3 +800009f0: 41390833 sub a6,s2,s3 +800009f4: 41348533 sub a0,s1,s3 +800009f8: 00f50733 add a4,a0,a5 +800009fc: 0007a583 lw a1,0(a5) +80000a00: 00072703 lw a4,0(a4) +80000a04: 00f80633 add a2,a6,a5 +80000a08: 00478793 addi a5,a5,4 +80000a0c: 00b70733 add a4,a4,a1 +80000a10: d00777d3 fcvt.s.w fa5,a4 +80000a14: 00f62027 fsw fa5,0(a2) +80000a18: fef690e3 bne a3,a5,800009f8 +80000a1c: 01c12083 lw ra,28(sp) +80000a20: 01812403 lw s0,24(sp) +80000a24: 01412483 lw s1,20(sp) +80000a28: 01012903 lw s2,16(sp) +80000a2c: 00c12983 lw s3,12(sp) +80000a30: 02010113 addi sp,sp,32 +80000a34: 00008067 ret + +80000a38 : +80000a38: fe010113 addi sp,sp,-32 +80000a3c: 00812c23 sw s0,24(sp) +80000a40: 00452403 lw s0,4(a0) +80000a44: 00912a23 sw s1,20(sp) +80000a48: 01212823 sw s2,16(sp) +80000a4c: 01312623 sw s3,12(sp) +80000a50: 00c52483 lw s1,12(a0) +80000a54: 00852983 lw s3,8(a0) +80000a58: 01052903 lw s2,16(a0) +80000a5c: 00112e23 sw ra,28(sp) +80000a60: 1c4000ef jal ra,80000c24 +80000a64: 02850533 mul a0,a0,s0 +80000a68: 04040263 beqz s0,80000aac +80000a6c: 00a406b3 add a3,s0,a0 +80000a70: 00269693 slli a3,a3,0x2 +80000a74: 00251513 slli a0,a0,0x2 +80000a78: 013507b3 add a5,a0,s3 +80000a7c: 013686b3 add a3,a3,s3 +80000a80: 41390833 sub a6,s2,s3 +80000a84: 41348533 sub a0,s1,s3 +80000a88: 00f50733 add a4,a0,a5 +80000a8c: 0007a583 lw a1,0(a5) +80000a90: 00072703 lw a4,0(a4) +80000a94: 00f80633 add a2,a6,a5 +80000a98: 00478793 addi a5,a5,4 +80000a9c: 00b70733 add a4,a4,a1 +80000aa0: d01777d3 fcvt.s.wu fa5,a4 +80000aa4: 00f62027 fsw fa5,0(a2) +80000aa8: fef690e3 bne a3,a5,80000a88 +80000aac: 01c12083 lw ra,28(sp) +80000ab0: 01812403 lw s0,24(sp) +80000ab4: 01412483 lw s1,20(sp) +80000ab8: 01012903 lw s2,16(sp) +80000abc: 00c12983 lw s3,12(sp) +80000ac0: 02010113 addi sp,sp,32 +80000ac4: 00008067 ret + +80000ac8 : +80000ac8: fd010113 addi sp,sp,-48 +80000acc: 02912223 sw s1,36(sp) +80000ad0: 00452483 lw s1,4(a0) +80000ad4: 03212023 sw s2,32(sp) +80000ad8: 01312e23 sw s3,28(sp) +80000adc: 01412c23 sw s4,24(sp) +80000ae0: 00c52983 lw s3,12(a0) +80000ae4: 00852a03 lw s4,8(a0) +80000ae8: 01052903 lw s2,16(a0) +80000aec: 02112623 sw ra,44(sp) +80000af0: 02812423 sw s0,40(sp) +80000af4: 130000ef jal ra,80000c24 +80000af8: 02950533 mul a0,a0,s1 +80000afc: 04048c63 beqz s1,80000b54 +80000b00: 00a484b3 add s1,s1,a0 +80000b04: f00006d3 fmv.w.x fa3,zero +80000b08: 00251513 slli a0,a0,0x2 +80000b0c: 00249493 slli s1,s1,0x2 +80000b10: 01450433 add s0,a0,s4 +80000b14: 014484b3 add s1,s1,s4 +80000b18: 414989b3 sub s3,s3,s4 +80000b1c: 41490933 sub s2,s2,s4 +80000b20: 008987b3 add a5,s3,s0 +80000b24: 00042707 flw fa4,0(s0) +80000b28: 0007a787 flw fa5,0(a5) +80000b2c: 00890733 add a4,s2,s0 +80000b30: 10e7f7d3 fmul.s fa5,fa5,fa4 +80000b34: 001026f3 frflags a3 +80000b38: a0d797d3 flt.s a5,fa5,fa3 +80000b3c: 00169073 fsflags a3 +80000b40: 5807f753 fsqrt.s fa4,fa5 +80000b44: 02079863 bnez a5,80000b74 +80000b48: 00440413 addi s0,s0,4 +80000b4c: 00e72027 fsw fa4,0(a4) +80000b50: fc9418e3 bne s0,s1,80000b20 +80000b54: 02c12083 lw ra,44(sp) +80000b58: 02812403 lw s0,40(sp) +80000b5c: 02412483 lw s1,36(sp) +80000b60: 02012903 lw s2,32(sp) +80000b64: 01c12983 lw s3,28(sp) +80000b68: 01812a03 lw s4,24(sp) +80000b6c: 03010113 addi sp,sp,48 +80000b70: 00008067 ret +80000b74: e0078553 fmv.x.w a0,fa5 +80000b78: 00e12627 fsw fa4,12(sp) +80000b7c: 190000ef jal ra,80000d0c +80000b80: 00c12707 flw fa4,12(sp) +80000b84: 008907b3 add a5,s2,s0 +80000b88: 00440413 addi s0,s0,4 +80000b8c: 00e7a027 fsw fa4,0(a5) +80000b90: f00006d3 fmv.w.x fa3,zero +80000b94: f88496e3 bne s1,s0,80000b20 +80000b98: fbdff06f j 80000b54 + +80000b9c <_exit>: +80000b9c: 00000513 li a0,0 +80000ba0: 0005006b 0x5006b + +80000ba4 : +80000ba4: 02502573 csrr a0,0x25 +80000ba8: 0005006b 0x5006b +80000bac: 00003197 auipc gp,0x3 +80000bb0: 0bc18193 addi gp,gp,188 # 80003c68 <__global_pointer$> +80000bb4: 022025f3 csrr a1,0x22 +80000bb8: 00a59593 slli a1,a1,0xa +80000bbc: 02002673 csrr a2,0x20 +80000bc0: 00261613 slli a2,a2,0x2 +80000bc4: 6ffff137 lui sp,0x6ffff +80000bc8: 40b10133 sub sp,sp,a1 +80000bcc: 00c10133 add sp,sp,a2 +80000bd0: 021026f3 csrr a3,0x21 +80000bd4: 00068663 beqz a3,80000be0 +80000bd8: 00000513 li a0,0 +80000bdc: 0005006b 0x5006b + +80000be0 : +80000be0: 00008067 ret + +80000be4 : +80000be4: 00b5106b 0xb5106b +80000be8: 00008067 ret + +80000bec : +80000bec: 0005006b 0x5006b +80000bf0: 00008067 ret + +80000bf4 : +80000bf4: 00b5406b 0xb5406b +80000bf8: 00008067 ret + +80000bfc : +80000bfc: 0005206b 0x5206b +80000c00: 00008067 ret + +80000c04 : +80000c04: 0000306b 0x306b +80000c08: 00008067 ret + +80000c0c : +80000c0c: 02102573 csrr a0,0x21 +80000c10: 00008067 ret + +80000c14 : +80000c14: 02302573 csrr a0,0x23 +80000c18: 00008067 ret + +80000c1c : +80000c1c: 02002573 csrr a0,0x20 +80000c20: 00008067 ret + +80000c24 : +80000c24: 02202573 csrr a0,0x22 +80000c28: 00008067 ret + +80000c2c : +80000c2c: 02402573 csrr a0,0x24 +80000c30: 00008067 ret + +80000c34 : +80000c34: 02502573 csrr a0,0x25 +80000c38: 00008067 ret + +80000c3c : +80000c3c: 02602573 csrr a0,0x26 +80000c40: 00008067 ret + +80000c44 : +80000c44: 02702573 csrr a0,0x27 +80000c48: 00008067 ret + +80000c4c : +80000c4c: c0002573 rdcycle a0 +80000c50: 00008067 ret + +80000c54 : +80000c54: c0202573 rdinstret a0 +80000c58: 00008067 ret + +80000c5c : +80000c5c: ff010113 addi sp,sp,-16 # 6fffeff0 <_start-0x10001010> +80000c60: 00812423 sw s0,8(sp) +80000c64: c381a783 lw a5,-968(gp) # 800038a0 +80000c68: 00112623 sw ra,12(sp) +80000c6c: 0087a503 lw a0,8(a5) +80000c70: f7dff0ef jal ra,80000bec +80000c74: c381a783 lw a5,-968(gp) # 800038a0 +80000c78: 0047a503 lw a0,4(a5) +80000c7c: 0007a783 lw a5,0(a5) +80000c80: 000780e7 jalr a5 +80000c84: f89ff0ef jal ra,80000c0c +80000c88: 00812403 lw s0,8(sp) +80000c8c: 00c12083 lw ra,12(sp) +80000c90: 00153513 seqz a0,a0 +80000c94: 01010113 addi sp,sp,16 +80000c98: f55ff06f j 80000bec + +80000c9c : +80000c9c: fe010113 addi sp,sp,-32 +80000ca0: 00410793 addi a5,sp,4 +80000ca4: 00812c23 sw s0,24(sp) +80000ca8: c2f1ac23 sw a5,-968(gp) # 800038a0 +80000cac: 00112e23 sw ra,28(sp) +80000cb0: 00c12223 sw a2,4(sp) +80000cb4: 00d12423 sw a3,8(sp) +80000cb8: 00b12623 sw a1,12(sp) +80000cbc: 00100793 li a5,1 +80000cc0: 00a7dc63 bge a5,a0,80000cd8 +80000cc4: 800015b7 lui a1,0x80001 +80000cc8: c5c58593 addi a1,a1,-932 # 80000c5c <__global_pointer$+0xffffcff4> +80000ccc: f19ff0ef jal ra,80000be4 +80000cd0: c381a783 lw a5,-968(gp) # 800038a0 +80000cd4: 0087a583 lw a1,8(a5) +80000cd8: 00058513 mv a0,a1 +80000cdc: f11ff0ef jal ra,80000bec +80000ce0: c381a783 lw a5,-968(gp) # 800038a0 +80000ce4: 0047a503 lw a0,4(a5) +80000ce8: 0007a783 lw a5,0(a5) +80000cec: 000780e7 jalr a5 +80000cf0: f1dff0ef jal ra,80000c0c +80000cf4: 00153513 seqz a0,a0 +80000cf8: ef5ff0ef jal ra,80000bec +80000cfc: 01c12083 lw ra,28(sp) +80000d00: 01812403 lw s0,24(sp) +80000d04: 02010113 addi sp,sp,32 +80000d08: 00008067 ret + +80000d0c : +80000d0c: ff010113 addi sp,sp,-16 +80000d10: 00812423 sw s0,8(sp) +80000d14: 00912223 sw s1,4(sp) +80000d18: 00112623 sw ra,12(sp) +80000d1c: 00050413 mv s0,a0 +80000d20: 080000ef jal ra,80000da0 <__ieee754_sqrtf> +80000d24: c3c1a703 lw a4,-964(gp) # 800038a4 <__fdlib_version> +80000d28: fff00793 li a5,-1 +80000d2c: 00050493 mv s1,a0 +80000d30: 02f70263 beq a4,a5,80000d54 +80000d34: 00040593 mv a1,s0 +80000d38: 00040513 mv a0,s0 +80000d3c: 0fc010ef jal ra,80001e38 <__unordsf2> +80000d40: 00051a63 bnez a0,80000d54 +80000d44: 00000593 li a1,0 +80000d48: 00040513 mv a0,s0 +80000d4c: 0f5000ef jal ra,80001640 <__lesf2> +80000d50: 00054e63 bltz a0,80000d6c +80000d54: 00c12083 lw ra,12(sp) +80000d58: 00812403 lw s0,8(sp) +80000d5c: 00048513 mv a0,s1 +80000d60: 00412483 lw s1,4(sp) +80000d64: 01010113 addi sp,sp,16 +80000d68: 00008067 ret +80000d6c: 170010ef jal ra,80001edc <__errno> +80000d70: 02100793 li a5,33 +80000d74: 00000593 li a1,0 +80000d78: 00f52023 sw a5,0(a0) +80000d7c: 00058513 mv a0,a1 +80000d80: 594000ef jal ra,80001314 <__divsf3> +80000d84: 00c12083 lw ra,12(sp) +80000d88: 00812403 lw s0,8(sp) +80000d8c: 00050493 mv s1,a0 +80000d90: 00048513 mv a0,s1 +80000d94: 00412483 lw s1,4(sp) +80000d98: 01010113 addi sp,sp,16 +80000d9c: 00008067 ret + +80000da0 <__ieee754_sqrtf>: +80000da0: ff010113 addi sp,sp,-16 +80000da4: 00151713 slli a4,a0,0x1 +80000da8: 00812423 sw s0,8(sp) +80000dac: 00112623 sw ra,12(sp) +80000db0: 00175713 srli a4,a4,0x1 +80000db4: 7f800637 lui a2,0x7f800 +80000db8: 00050413 mv s0,a0 +80000dbc: 00050593 mv a1,a0 +80000dc0: 0cc77663 bgeu a4,a2,80000e8c <__ieee754_sqrtf+0xec> +80000dc4: 0a070a63 beqz a4,80000e78 <__ieee754_sqrtf+0xd8> +80000dc8: 00050693 mv a3,a0 +80000dcc: 0e054663 bltz a0,80000eb8 <__ieee754_sqrtf+0x118> +80000dd0: 00a67633 and a2,a2,a0 +80000dd4: 41755793 srai a5,a0,0x17 +80000dd8: 02061463 bnez a2,80000e00 <__ieee754_sqrtf+0x60> +80000ddc: 008005b7 lui a1,0x800 +80000de0: 00a5f433 and s0,a1,a0 +80000de4: 0e041c63 bnez s0,80000edc <__ieee754_sqrtf+0x13c> +80000de8: 00169693 slli a3,a3,0x1 +80000dec: 00869613 slli a2,a3,0x8 +80000df0: 00040713 mv a4,s0 +80000df4: 00140413 addi s0,s0,1 +80000df8: fe0658e3 bgez a2,80000de8 <__ieee754_sqrtf+0x48> +80000dfc: 40e787b3 sub a5,a5,a4 +80000e00: 00800637 lui a2,0x800 +80000e04: fff60593 addi a1,a2,-1 # 7fffff <_start-0x7f800001> +80000e08: f8178713 addi a4,a5,-127 +80000e0c: 00b6f6b3 and a3,a3,a1 +80000e10: 00c6e6b3 or a3,a3,a2 +80000e14: 00177613 andi a2,a4,1 +80000e18: 00169793 slli a5,a3,0x1 +80000e1c: 08061a63 bnez a2,80000eb0 <__ieee754_sqrtf+0x110> +80000e20: 40175813 srai a6,a4,0x1 +80000e24: 01900693 li a3,25 +80000e28: 00000513 li a0,0 +80000e2c: 00000593 li a1,0 +80000e30: 01000737 lui a4,0x1000 +80000e34: 00e58633 add a2,a1,a4 +80000e38: fff68693 addi a3,a3,-1 +80000e3c: 00c7c863 blt a5,a2,80000e4c <__ieee754_sqrtf+0xac> +80000e40: 00e605b3 add a1,a2,a4 +80000e44: 40c787b3 sub a5,a5,a2 +80000e48: 00e50533 add a0,a0,a4 +80000e4c: 00179793 slli a5,a5,0x1 +80000e50: 00175713 srli a4,a4,0x1 +80000e54: fe0690e3 bnez a3,80000e34 <__ieee754_sqrtf+0x94> +80000e58: 00078663 beqz a5,80000e64 <__ieee754_sqrtf+0xc4> +80000e5c: 00150513 addi a0,a0,1 +80000e60: ffe57513 andi a0,a0,-2 +80000e64: 40155513 srai a0,a0,0x1 +80000e68: 3f0005b7 lui a1,0x3f000 +80000e6c: 00b505b3 add a1,a0,a1 +80000e70: 01781793 slli a5,a6,0x17 +80000e74: 00b785b3 add a1,a5,a1 +80000e78: 00c12083 lw ra,12(sp) +80000e7c: 00812403 lw s0,8(sp) +80000e80: 00058513 mv a0,a1 +80000e84: 01010113 addi sp,sp,16 +80000e88: 00008067 ret +80000e8c: 069000ef jal ra,800016f4 <__mulsf3> +80000e90: 00040593 mv a1,s0 +80000e94: 054000ef jal ra,80000ee8 <__addsf3> +80000e98: 00c12083 lw ra,12(sp) +80000e9c: 00812403 lw s0,8(sp) +80000ea0: 00050593 mv a1,a0 +80000ea4: 00058513 mv a0,a1 +80000ea8: 01010113 addi sp,sp,16 +80000eac: 00008067 ret +80000eb0: 00269793 slli a5,a3,0x2 +80000eb4: f6dff06f j 80000e20 <__ieee754_sqrtf+0x80> +80000eb8: 335000ef jal ra,800019ec <__subsf3> +80000ebc: 00050593 mv a1,a0 +80000ec0: 454000ef jal ra,80001314 <__divsf3> +80000ec4: 00c12083 lw ra,12(sp) +80000ec8: 00812403 lw s0,8(sp) +80000ecc: 00050593 mv a1,a0 +80000ed0: 00058513 mv a0,a1 +80000ed4: 01010113 addi sp,sp,16 +80000ed8: 00008067 ret +80000edc: fff00713 li a4,-1 +80000ee0: 40e787b3 sub a5,a5,a4 +80000ee4: f1dff06f j 80000e00 <__ieee754_sqrtf+0x60> + +80000ee8 <__addsf3>: +80000ee8: ff010113 addi sp,sp,-16 +80000eec: 01755713 srli a4,a0,0x17 +80000ef0: 00800637 lui a2,0x800 +80000ef4: fff60613 addi a2,a2,-1 # 7fffff <_start-0x7f800001> +80000ef8: 01212023 sw s2,0(sp) +80000efc: 0ff77913 andi s2,a4,255 +80000f00: 0175d713 srli a4,a1,0x17 +80000f04: 00a677b3 and a5,a2,a0 +80000f08: 00912223 sw s1,4(sp) +80000f0c: 00b67633 and a2,a2,a1 +80000f10: 0ff77713 andi a4,a4,255 +80000f14: 00112623 sw ra,12(sp) +80000f18: 00812423 sw s0,8(sp) +80000f1c: 01f55493 srli s1,a0,0x1f +80000f20: 01f5d593 srli a1,a1,0x1f +80000f24: 00379793 slli a5,a5,0x3 +80000f28: 00361613 slli a2,a2,0x3 +80000f2c: 40e906b3 sub a3,s2,a4 +80000f30: 18b49463 bne s1,a1,800010b8 <__addsf3+0x1d0> +80000f34: 08d05c63 blez a3,80000fcc <__addsf3+0xe4> +80000f38: 04071c63 bnez a4,80000f90 <__addsf3+0xa8> +80000f3c: 34060463 beqz a2,80001284 <__addsf3+0x39c> +80000f40: fff68693 addi a3,a3,-1 +80000f44: 02069e63 bnez a3,80000f80 <__addsf3+0x98> +80000f48: 00c787b3 add a5,a5,a2 +80000f4c: 00090713 mv a4,s2 +80000f50: 00579693 slli a3,a5,0x5 +80000f54: 1006dc63 bgez a3,8000106c <__addsf3+0x184> +80000f58: 00170713 addi a4,a4,1 # 1000001 <_start-0x7effffff> +80000f5c: 0ff00693 li a3,255 +80000f60: 32d70c63 beq a4,a3,80001298 <__addsf3+0x3b0> +80000f64: 7e0006b7 lui a3,0x7e000 +80000f68: 0017f613 andi a2,a5,1 +80000f6c: fff68693 addi a3,a3,-1 # 7dffffff <_start-0x2000001> +80000f70: 0017d793 srli a5,a5,0x1 +80000f74: 00d7f7b3 and a5,a5,a3 +80000f78: 00c7e7b3 or a5,a5,a2 +80000f7c: 0f00006f j 8000106c <__addsf3+0x184> +80000f80: 0ff00713 li a4,255 +80000f84: 00e91e63 bne s2,a4,80000fa0 <__addsf3+0xb8> +80000f88: 0ff00713 li a4,255 +80000f8c: 0e00006f j 8000106c <__addsf3+0x184> +80000f90: 0ff00713 li a4,255 +80000f94: fee90ae3 beq s2,a4,80000f88 <__addsf3+0xa0> +80000f98: 04000737 lui a4,0x4000 +80000f9c: 00e66633 or a2,a2,a4 +80000fa0: 01b00593 li a1,27 +80000fa4: 00100713 li a4,1 +80000fa8: 00d5ce63 blt a1,a3,80000fc4 <__addsf3+0xdc> +80000fac: 02000593 li a1,32 +80000fb0: 00d65733 srl a4,a2,a3 +80000fb4: 40d586b3 sub a3,a1,a3 +80000fb8: 00d61633 sll a2,a2,a3 +80000fbc: 00c03633 snez a2,a2 +80000fc0: 00c76733 or a4,a4,a2 +80000fc4: 00e787b3 add a5,a5,a4 +80000fc8: f85ff06f j 80000f4c <__addsf3+0x64> +80000fcc: 06068663 beqz a3,80001038 <__addsf3+0x150> +80000fd0: 412705b3 sub a1,a4,s2 +80000fd4: 02091463 bnez s2,80000ffc <__addsf3+0x114> +80000fd8: 00078e63 beqz a5,80000ff4 <__addsf3+0x10c> +80000fdc: fff58593 addi a1,a1,-1 # 3effffff <_start-0x41000001> +80000fe0: 00059663 bnez a1,80000fec <__addsf3+0x104> +80000fe4: 00c787b3 add a5,a5,a2 +80000fe8: f69ff06f j 80000f50 <__addsf3+0x68> +80000fec: 0ff00693 li a3,255 +80000ff0: 00d71e63 bne a4,a3,8000100c <__addsf3+0x124> +80000ff4: 00060793 mv a5,a2 +80000ff8: 0740006f j 8000106c <__addsf3+0x184> +80000ffc: 0ff00693 li a3,255 +80001000: fed70ae3 beq a4,a3,80000ff4 <__addsf3+0x10c> +80001004: 040006b7 lui a3,0x4000 +80001008: 00d7e7b3 or a5,a5,a3 +8000100c: 01b00513 li a0,27 +80001010: 00100693 li a3,1 +80001014: 00b54e63 blt a0,a1,80001030 <__addsf3+0x148> +80001018: 02000693 li a3,32 +8000101c: 40b686b3 sub a3,a3,a1 +80001020: 00b7d533 srl a0,a5,a1 +80001024: 00d797b3 sll a5,a5,a3 +80001028: 00f037b3 snez a5,a5 +8000102c: 00f566b3 or a3,a0,a5 +80001030: 00c687b3 add a5,a3,a2 +80001034: f1dff06f j 80000f50 <__addsf3+0x68> +80001038: 00190593 addi a1,s2,1 +8000103c: 0fe5f713 andi a4,a1,254 +80001040: 06071063 bnez a4,800010a0 <__addsf3+0x1b8> +80001044: 04091263 bnez s2,80001088 <__addsf3+0x1a0> +80001048: fa0786e3 beqz a5,80000ff4 <__addsf3+0x10c> +8000104c: 02060063 beqz a2,8000106c <__addsf3+0x184> +80001050: 00c787b3 add a5,a5,a2 +80001054: 00579693 slli a3,a5,0x5 +80001058: 0006da63 bgez a3,8000106c <__addsf3+0x184> +8000105c: fc000737 lui a4,0xfc000 +80001060: fff70713 addi a4,a4,-1 # fbffffff <__global_pointer$+0x7bffc397> +80001064: 00e7f7b3 and a5,a5,a4 +80001068: 00100713 li a4,1 +8000106c: 0077f693 andi a3,a5,7 +80001070: 22068663 beqz a3,8000129c <__addsf3+0x3b4> +80001074: 00f7f693 andi a3,a5,15 +80001078: 00400613 li a2,4 +8000107c: 22c68063 beq a3,a2,8000129c <__addsf3+0x3b4> +80001080: 00478793 addi a5,a5,4 +80001084: 2180006f j 8000129c <__addsf3+0x3b4> +80001088: 20078263 beqz a5,8000128c <__addsf3+0x3a4> +8000108c: ee060ee3 beqz a2,80000f88 <__addsf3+0xa0> +80001090: 00000493 li s1,0 +80001094: 020007b7 lui a5,0x2000 +80001098: 0ff00713 li a4,255 +8000109c: 2000006f j 8000129c <__addsf3+0x3b4> +800010a0: 0ff00713 li a4,255 +800010a4: 1ee58863 beq a1,a4,80001294 <__addsf3+0x3ac> +800010a8: 00c787b3 add a5,a5,a2 +800010ac: 0017d793 srli a5,a5,0x1 +800010b0: 00058713 mv a4,a1 +800010b4: fb9ff06f j 8000106c <__addsf3+0x184> +800010b8: 08d05663 blez a3,80001144 <__addsf3+0x25c> +800010bc: 06071863 bnez a4,8000112c <__addsf3+0x244> +800010c0: 00090713 mv a4,s2 +800010c4: fa0604e3 beqz a2,8000106c <__addsf3+0x184> +800010c8: fff68693 addi a3,a3,-1 # 3ffffff <_start-0x7c000001> +800010cc: 02069263 bnez a3,800010f0 <__addsf3+0x208> +800010d0: 40c787b3 sub a5,a5,a2 +800010d4: 00579693 slli a3,a5,0x5 +800010d8: f806dae3 bgez a3,8000106c <__addsf3+0x184> +800010dc: 04000437 lui s0,0x4000 +800010e0: fff40413 addi s0,s0,-1 # 3ffffff <_start-0x7c000001> +800010e4: 0087f433 and s0,a5,s0 +800010e8: 00070913 mv s2,a4 +800010ec: 1380006f j 80001224 <__addsf3+0x33c> +800010f0: 0ff00593 li a1,255 +800010f4: 0ff00713 li a4,255 +800010f8: f6b90ae3 beq s2,a1,8000106c <__addsf3+0x184> +800010fc: 01b00593 li a1,27 +80001100: 00100713 li a4,1 +80001104: 00d5ce63 blt a1,a3,80001120 <__addsf3+0x238> +80001108: 02000593 li a1,32 +8000110c: 00d65733 srl a4,a2,a3 +80001110: 40d586b3 sub a3,a1,a3 +80001114: 00d61633 sll a2,a2,a3 +80001118: 00c03633 snez a2,a2 +8000111c: 00c76733 or a4,a4,a2 +80001120: 40e787b3 sub a5,a5,a4 +80001124: 00090713 mv a4,s2 +80001128: fadff06f j 800010d4 <__addsf3+0x1ec> +8000112c: 0ff00593 li a1,255 +80001130: 0ff00713 li a4,255 +80001134: f2b90ce3 beq s2,a1,8000106c <__addsf3+0x184> +80001138: 04000737 lui a4,0x4000 +8000113c: 00e66633 or a2,a2,a4 +80001140: fbdff06f j 800010fc <__addsf3+0x214> +80001144: 06068a63 beqz a3,800011b8 <__addsf3+0x2d0> +80001148: 41270533 sub a0,a4,s2 +8000114c: 02091863 bnez s2,8000117c <__addsf3+0x294> +80001150: 02078063 beqz a5,80001170 <__addsf3+0x288> +80001154: fff50513 addi a0,a0,-1 +80001158: 00051863 bnez a0,80001168 <__addsf3+0x280> +8000115c: 40f607b3 sub a5,a2,a5 +80001160: 00058493 mv s1,a1 +80001164: f71ff06f j 800010d4 <__addsf3+0x1ec> +80001168: 0ff00693 li a3,255 +8000116c: 02d71063 bne a4,a3,8000118c <__addsf3+0x2a4> +80001170: 00060793 mv a5,a2 +80001174: 00058493 mv s1,a1 +80001178: ef5ff06f j 8000106c <__addsf3+0x184> +8000117c: 0ff00693 li a3,255 +80001180: fed708e3 beq a4,a3,80001170 <__addsf3+0x288> +80001184: 040006b7 lui a3,0x4000 +80001188: 00d7e7b3 or a5,a5,a3 +8000118c: 01b00813 li a6,27 +80001190: 00100693 li a3,1 +80001194: 00a84e63 blt a6,a0,800011b0 <__addsf3+0x2c8> +80001198: 02000693 li a3,32 +8000119c: 40a686b3 sub a3,a3,a0 +800011a0: 00a7d833 srl a6,a5,a0 +800011a4: 00d797b3 sll a5,a5,a3 +800011a8: 00f037b3 snez a5,a5 +800011ac: 00f866b3 or a3,a6,a5 +800011b0: 40d607b3 sub a5,a2,a3 +800011b4: fadff06f j 80001160 <__addsf3+0x278> +800011b8: 00190713 addi a4,s2,1 +800011bc: 0fe77713 andi a4,a4,254 +800011c0: 04071863 bnez a4,80001210 <__addsf3+0x328> +800011c4: 02091c63 bnez s2,800011fc <__addsf3+0x314> +800011c8: 00079a63 bnez a5,800011dc <__addsf3+0x2f4> +800011cc: fa0612e3 bnez a2,80001170 <__addsf3+0x288> +800011d0: 00000793 li a5,0 +800011d4: 00000493 li s1,0 +800011d8: 0c40006f j 8000129c <__addsf3+0x3b4> +800011dc: e80608e3 beqz a2,8000106c <__addsf3+0x184> +800011e0: 40c786b3 sub a3,a5,a2 +800011e4: 00569513 slli a0,a3,0x5 +800011e8: 40f607b3 sub a5,a2,a5 +800011ec: f80544e3 bltz a0,80001174 <__addsf3+0x28c> +800011f0: fe0680e3 beqz a3,800011d0 <__addsf3+0x2e8> +800011f4: 00068793 mv a5,a3 +800011f8: e75ff06f j 8000106c <__addsf3+0x184> +800011fc: e80798e3 bnez a5,8000108c <__addsf3+0x1a4> +80001200: e80608e3 beqz a2,80001090 <__addsf3+0x1a8> +80001204: 00060793 mv a5,a2 +80001208: 00058493 mv s1,a1 +8000120c: d7dff06f j 80000f88 <__addsf3+0xa0> +80001210: 40c78433 sub s0,a5,a2 +80001214: 00541713 slli a4,s0,0x5 +80001218: 04075463 bgez a4,80001260 <__addsf3+0x378> +8000121c: 40f60433 sub s0,a2,a5 +80001220: 00058493 mv s1,a1 +80001224: 00040513 mv a0,s0 +80001228: 455000ef jal ra,80001e7c <__clzsi2> +8000122c: ffb50713 addi a4,a0,-5 +80001230: 00e41433 sll s0,s0,a4 +80001234: 03274e63 blt a4,s2,80001270 <__addsf3+0x388> +80001238: 41270733 sub a4,a4,s2 +8000123c: 00170713 addi a4,a4,1 # 4000001 <_start-0x7bffffff> +80001240: 02000693 li a3,32 +80001244: 00e457b3 srl a5,s0,a4 +80001248: 40e68733 sub a4,a3,a4 +8000124c: 00e41433 sll s0,s0,a4 +80001250: 00803433 snez s0,s0 +80001254: 0087e7b3 or a5,a5,s0 +80001258: 00000713 li a4,0 +8000125c: e11ff06f j 8000106c <__addsf3+0x184> +80001260: fc0412e3 bnez s0,80001224 <__addsf3+0x33c> +80001264: 00000793 li a5,0 +80001268: 00000713 li a4,0 +8000126c: f69ff06f j 800011d4 <__addsf3+0x2ec> +80001270: fc0007b7 lui a5,0xfc000 +80001274: fff78793 addi a5,a5,-1 # fbffffff <__global_pointer$+0x7bffc397> +80001278: 40e90733 sub a4,s2,a4 +8000127c: 00f477b3 and a5,s0,a5 +80001280: dedff06f j 8000106c <__addsf3+0x184> +80001284: 00090713 mv a4,s2 +80001288: de5ff06f j 8000106c <__addsf3+0x184> +8000128c: 00060793 mv a5,a2 +80001290: cf9ff06f j 80000f88 <__addsf3+0xa0> +80001294: 0ff00713 li a4,255 +80001298: 00000793 li a5,0 +8000129c: 00579693 slli a3,a5,0x5 +800012a0: 0006de63 bgez a3,800012bc <__addsf3+0x3d4> +800012a4: 00170713 addi a4,a4,1 +800012a8: 0ff00693 li a3,255 +800012ac: 06d70063 beq a4,a3,8000130c <__addsf3+0x424> +800012b0: fc0006b7 lui a3,0xfc000 +800012b4: fff68693 addi a3,a3,-1 # fbffffff <__global_pointer$+0x7bffc397> +800012b8: 00d7f7b3 and a5,a5,a3 +800012bc: 0ff00693 li a3,255 +800012c0: 0037d793 srli a5,a5,0x3 +800012c4: 00d71863 bne a4,a3,800012d4 <__addsf3+0x3ec> +800012c8: 00078663 beqz a5,800012d4 <__addsf3+0x3ec> +800012cc: 004007b7 lui a5,0x400 +800012d0: 00000493 li s1,0 +800012d4: 00c12083 lw ra,12(sp) +800012d8: 00812403 lw s0,8(sp) +800012dc: 7f800537 lui a0,0x7f800 +800012e0: 01771713 slli a4,a4,0x17 +800012e4: 00979793 slli a5,a5,0x9 +800012e8: 00a77733 and a4,a4,a0 +800012ec: 0097d793 srli a5,a5,0x9 +800012f0: 01f49513 slli a0,s1,0x1f +800012f4: 00f767b3 or a5,a4,a5 +800012f8: 00412483 lw s1,4(sp) +800012fc: 00012903 lw s2,0(sp) +80001300: 00a7e533 or a0,a5,a0 +80001304: 01010113 addi sp,sp,16 +80001308: 00008067 ret +8000130c: 00000793 li a5,0 +80001310: fadff06f j 800012bc <__addsf3+0x3d4> + +80001314 <__divsf3>: +80001314: fe010113 addi sp,sp,-32 +80001318: 00912a23 sw s1,20(sp) +8000131c: 01755493 srli s1,a0,0x17 +80001320: 01212823 sw s2,16(sp) +80001324: 01312623 sw s3,12(sp) +80001328: 01412423 sw s4,8(sp) +8000132c: 00951993 slli s3,a0,0x9 +80001330: 00112e23 sw ra,28(sp) +80001334: 00812c23 sw s0,24(sp) +80001338: 01512223 sw s5,4(sp) +8000133c: 0ff4f493 andi s1,s1,255 +80001340: 00058a13 mv s4,a1 +80001344: 0099d993 srli s3,s3,0x9 +80001348: 01f55913 srli s2,a0,0x1f +8000134c: 08048463 beqz s1,800013d4 <__divsf3+0xc0> +80001350: 0ff00793 li a5,255 +80001354: 0af48063 beq s1,a5,800013f4 <__divsf3+0xe0> +80001358: 00399993 slli s3,s3,0x3 +8000135c: 040007b7 lui a5,0x4000 +80001360: 00f9e9b3 or s3,s3,a5 +80001364: f8148493 addi s1,s1,-127 +80001368: 00000a93 li s5,0 +8000136c: 017a5793 srli a5,s4,0x17 +80001370: 009a1413 slli s0,s4,0x9 +80001374: 0ff7f793 andi a5,a5,255 +80001378: 00945413 srli s0,s0,0x9 +8000137c: 01fa5a13 srli s4,s4,0x1f +80001380: 08078a63 beqz a5,80001414 <__divsf3+0x100> +80001384: 0ff00713 li a4,255 +80001388: 0ae78663 beq a5,a4,80001434 <__divsf3+0x120> +8000138c: 00341413 slli s0,s0,0x3 +80001390: 04000737 lui a4,0x4000 +80001394: 00e46433 or s0,s0,a4 +80001398: f8178793 addi a5,a5,-127 # 3ffff81 <_start-0x7c00007f> +8000139c: 00000693 li a3,0 +800013a0: 002a9613 slli a2,s5,0x2 +800013a4: 00d66633 or a2,a2,a3 +800013a8: 40f484b3 sub s1,s1,a5 +800013ac: fff60613 addi a2,a2,-1 +800013b0: 00e00793 li a5,14 +800013b4: 01494533 xor a0,s2,s4 +800013b8: 08c7ee63 bltu a5,a2,80001454 <__divsf3+0x140> +800013bc: 800027b7 lui a5,0x80002 +800013c0: 2ec78793 addi a5,a5,748 # 800022ec <__global_pointer$+0xffffe684> +800013c4: 00261613 slli a2,a2,0x2 +800013c8: 00f60633 add a2,a2,a5 +800013cc: 00062783 lw a5,0(a2) +800013d0: 00078067 jr a5 +800013d4: 02098a63 beqz s3,80001408 <__divsf3+0xf4> +800013d8: 00098513 mv a0,s3 +800013dc: 2a1000ef jal ra,80001e7c <__clzsi2> +800013e0: ffb50793 addi a5,a0,-5 # 7f7ffffb <_start-0x800005> +800013e4: f8a00493 li s1,-118 +800013e8: 00f999b3 sll s3,s3,a5 +800013ec: 40a484b3 sub s1,s1,a0 +800013f0: f79ff06f j 80001368 <__divsf3+0x54> +800013f4: 0ff00493 li s1,255 +800013f8: 00200a93 li s5,2 +800013fc: f60988e3 beqz s3,8000136c <__divsf3+0x58> +80001400: 00300a93 li s5,3 +80001404: f69ff06f j 8000136c <__divsf3+0x58> +80001408: 00000493 li s1,0 +8000140c: 00100a93 li s5,1 +80001410: f5dff06f j 8000136c <__divsf3+0x58> +80001414: 02040a63 beqz s0,80001448 <__divsf3+0x134> +80001418: 00040513 mv a0,s0 +8000141c: 261000ef jal ra,80001e7c <__clzsi2> +80001420: ffb50793 addi a5,a0,-5 +80001424: 00f41433 sll s0,s0,a5 +80001428: f8a00793 li a5,-118 +8000142c: 40a787b3 sub a5,a5,a0 +80001430: f6dff06f j 8000139c <__divsf3+0x88> +80001434: 0ff00793 li a5,255 +80001438: 00200693 li a3,2 +8000143c: f60402e3 beqz s0,800013a0 <__divsf3+0x8c> +80001440: 00300693 li a3,3 +80001444: f5dff06f j 800013a0 <__divsf3+0x8c> +80001448: 00000793 li a5,0 +8000144c: 00100693 li a3,1 +80001450: f51ff06f j 800013a0 <__divsf3+0x8c> +80001454: 00541593 slli a1,s0,0x5 +80001458: 1289f263 bgeu s3,s0,8000157c <__divsf3+0x268> +8000145c: fff48493 addi s1,s1,-1 +80001460: 00000693 li a3,0 +80001464: 0105d413 srli s0,a1,0x10 +80001468: 0289d8b3 divu a7,s3,s0 +8000146c: 000107b7 lui a5,0x10 +80001470: fff78793 addi a5,a5,-1 # ffff <_start-0x7fff0001> +80001474: 00f5f7b3 and a5,a1,a5 +80001478: 0106d693 srli a3,a3,0x10 +8000147c: 0289f733 remu a4,s3,s0 +80001480: 00088613 mv a2,a7 +80001484: 03178833 mul a6,a5,a7 +80001488: 01071713 slli a4,a4,0x10 +8000148c: 00e6e733 or a4,a3,a4 +80001490: 01077e63 bgeu a4,a6,800014ac <__divsf3+0x198> +80001494: 00b70733 add a4,a4,a1 +80001498: fff88613 addi a2,a7,-1 +8000149c: 00b76863 bltu a4,a1,800014ac <__divsf3+0x198> +800014a0: 01077663 bgeu a4,a6,800014ac <__divsf3+0x198> +800014a4: ffe88613 addi a2,a7,-2 +800014a8: 00b70733 add a4,a4,a1 +800014ac: 41070733 sub a4,a4,a6 +800014b0: 02875833 divu a6,a4,s0 +800014b4: 02877733 remu a4,a4,s0 +800014b8: 030786b3 mul a3,a5,a6 +800014bc: 01071793 slli a5,a4,0x10 +800014c0: 00080713 mv a4,a6 +800014c4: 00d7fe63 bgeu a5,a3,800014e0 <__divsf3+0x1cc> +800014c8: 00b787b3 add a5,a5,a1 +800014cc: fff80713 addi a4,a6,-1 +800014d0: 00b7e863 bltu a5,a1,800014e0 <__divsf3+0x1cc> +800014d4: 00d7f663 bgeu a5,a3,800014e0 <__divsf3+0x1cc> +800014d8: ffe80713 addi a4,a6,-2 +800014dc: 00b787b3 add a5,a5,a1 +800014e0: 01061413 slli s0,a2,0x10 +800014e4: 40d787b3 sub a5,a5,a3 +800014e8: 00e46433 or s0,s0,a4 +800014ec: 00f037b3 snez a5,a5 +800014f0: 00f46433 or s0,s0,a5 +800014f4: 07f48713 addi a4,s1,127 +800014f8: 0ce05c63 blez a4,800015d0 <__divsf3+0x2bc> +800014fc: 00747793 andi a5,s0,7 +80001500: 00078a63 beqz a5,80001514 <__divsf3+0x200> +80001504: 00f47793 andi a5,s0,15 +80001508: 00400693 li a3,4 +8000150c: 00d78463 beq a5,a3,80001514 <__divsf3+0x200> +80001510: 00440413 addi s0,s0,4 +80001514: 00441793 slli a5,s0,0x4 +80001518: 0007da63 bgez a5,8000152c <__divsf3+0x218> +8000151c: f80007b7 lui a5,0xf8000 +80001520: fff78793 addi a5,a5,-1 # f7ffffff <__global_pointer$+0x77ffc397> +80001524: 00f47433 and s0,s0,a5 +80001528: 08048713 addi a4,s1,128 +8000152c: 0fe00793 li a5,254 +80001530: 00345413 srli s0,s0,0x3 +80001534: 06e7cc63 blt a5,a4,800015ac <__divsf3+0x298> +80001538: 01771713 slli a4,a4,0x17 +8000153c: 7f8007b7 lui a5,0x7f800 +80001540: 00941413 slli s0,s0,0x9 +80001544: 00f77733 and a4,a4,a5 +80001548: 00945413 srli s0,s0,0x9 +8000154c: 00876433 or s0,a4,s0 +80001550: 01f51513 slli a0,a0,0x1f +80001554: 01c12083 lw ra,28(sp) +80001558: 00a46533 or a0,s0,a0 +8000155c: 01812403 lw s0,24(sp) +80001560: 01412483 lw s1,20(sp) +80001564: 01012903 lw s2,16(sp) +80001568: 00c12983 lw s3,12(sp) +8000156c: 00812a03 lw s4,8(sp) +80001570: 00412a83 lw s5,4(sp) +80001574: 02010113 addi sp,sp,32 +80001578: 00008067 ret +8000157c: 01f99693 slli a3,s3,0x1f +80001580: 0019d993 srli s3,s3,0x1 +80001584: ee1ff06f j 80001464 <__divsf3+0x150> +80001588: 00090513 mv a0,s2 +8000158c: 00098413 mv s0,s3 +80001590: 000a8693 mv a3,s5 +80001594: 00300793 li a5,3 +80001598: 08f68663 beq a3,a5,80001624 <__divsf3+0x310> +8000159c: 00100793 li a5,1 +800015a0: 08f68a63 beq a3,a5,80001634 <__divsf3+0x320> +800015a4: 00200793 li a5,2 +800015a8: f4f696e3 bne a3,a5,800014f4 <__divsf3+0x1e0> +800015ac: 00000413 li s0,0 +800015b0: 0ff00713 li a4,255 +800015b4: f85ff06f j 80001538 <__divsf3+0x224> +800015b8: 000a0513 mv a0,s4 +800015bc: fd9ff06f j 80001594 <__divsf3+0x280> +800015c0: 00400437 lui s0,0x400 +800015c4: 00000513 li a0,0 +800015c8: 00300693 li a3,3 +800015cc: fc9ff06f j 80001594 <__divsf3+0x280> +800015d0: 00100793 li a5,1 +800015d4: 40e787b3 sub a5,a5,a4 +800015d8: 01b00713 li a4,27 +800015dc: 04f74c63 blt a4,a5,80001634 <__divsf3+0x320> +800015e0: 09e48493 addi s1,s1,158 +800015e4: 00f457b3 srl a5,s0,a5 +800015e8: 00941433 sll s0,s0,s1 +800015ec: 00803433 snez s0,s0 +800015f0: 0087e433 or s0,a5,s0 +800015f4: 00747793 andi a5,s0,7 +800015f8: 00078a63 beqz a5,8000160c <__divsf3+0x2f8> +800015fc: 00f47793 andi a5,s0,15 +80001600: 00400713 li a4,4 +80001604: 00e78463 beq a5,a4,8000160c <__divsf3+0x2f8> +80001608: 00440413 addi s0,s0,4 # 400004 <_start-0x7fbffffc> +8000160c: 00541793 slli a5,s0,0x5 +80001610: 00345413 srli s0,s0,0x3 +80001614: 0207d263 bgez a5,80001638 <__divsf3+0x324> +80001618: 00000413 li s0,0 +8000161c: 00100713 li a4,1 +80001620: f19ff06f j 80001538 <__divsf3+0x224> +80001624: 00400437 lui s0,0x400 +80001628: 0ff00713 li a4,255 +8000162c: 00000513 li a0,0 +80001630: f09ff06f j 80001538 <__divsf3+0x224> +80001634: 00000413 li s0,0 +80001638: 00000713 li a4,0 +8000163c: efdff06f j 80001538 <__divsf3+0x224> + +80001640 <__lesf2>: +80001640: 01755693 srli a3,a0,0x17 +80001644: 008007b7 lui a5,0x800 +80001648: fff78793 addi a5,a5,-1 # 7fffff <_start-0x7f800001> +8000164c: 0175d713 srli a4,a1,0x17 +80001650: 0ff6f693 andi a3,a3,255 +80001654: 0ff00813 li a6,255 +80001658: 00a7f633 and a2,a5,a0 +8000165c: 0ff77713 andi a4,a4,255 +80001660: 00b7f7b3 and a5,a5,a1 +80001664: 01f55513 srli a0,a0,0x1f +80001668: 01f5d593 srli a1,a1,0x1f +8000166c: 01069863 bne a3,a6,8000167c <__lesf2+0x3c> +80001670: 06060a63 beqz a2,800016e4 <__lesf2+0xa4> +80001674: 00200513 li a0,2 +80001678: 00008067 ret +8000167c: 01071463 bne a4,a6,80001684 <__lesf2+0x44> +80001680: fe079ae3 bnez a5,80001674 <__lesf2+0x34> +80001684: 06069263 bnez a3,800016e8 <__lesf2+0xa8> +80001688: 00071463 bnez a4,80001690 <__lesf2+0x50> +8000168c: 04078863 beqz a5,800016dc <__lesf2+0x9c> +80001690: 00060c63 beqz a2,800016a8 <__lesf2+0x68> +80001694: 00b51463 bne a0,a1,8000169c <__lesf2+0x5c> +80001698: 02d75063 bge a4,a3,800016b8 <__lesf2+0x78> +8000169c: 02050c63 beqz a0,800016d4 <__lesf2+0x94> +800016a0: fff00513 li a0,-1 +800016a4: 00008067 ret +800016a8: fff00513 li a0,-1 +800016ac: 00058a63 beqz a1,800016c0 <__lesf2+0x80> +800016b0: 00058513 mv a0,a1 +800016b4: 00008067 ret +800016b8: 00e6d663 bge a3,a4,800016c4 <__lesf2+0x84> +800016bc: fe0502e3 beqz a0,800016a0 <__lesf2+0x60> +800016c0: 00008067 ret +800016c4: fcc7ece3 bltu a5,a2,8000169c <__lesf2+0x5c> +800016c8: fef66ae3 bltu a2,a5,800016bc <__lesf2+0x7c> +800016cc: 00000513 li a0,0 +800016d0: 00008067 ret +800016d4: 00100513 li a0,1 +800016d8: 00008067 ret +800016dc: fe0608e3 beqz a2,800016cc <__lesf2+0x8c> +800016e0: fbdff06f j 8000169c <__lesf2+0x5c> +800016e4: f8d70ee3 beq a4,a3,80001680 <__lesf2+0x40> +800016e8: fa0716e3 bnez a4,80001694 <__lesf2+0x54> +800016ec: fa0788e3 beqz a5,8000169c <__lesf2+0x5c> +800016f0: fa5ff06f j 80001694 <__lesf2+0x54> + +800016f4 <__mulsf3>: +800016f4: fe010113 addi sp,sp,-32 +800016f8: 01212823 sw s2,16(sp) +800016fc: 01755913 srli s2,a0,0x17 +80001700: 00912a23 sw s1,20(sp) +80001704: 01312623 sw s3,12(sp) +80001708: 01412423 sw s4,8(sp) +8000170c: 00951493 slli s1,a0,0x9 +80001710: 00112e23 sw ra,28(sp) +80001714: 00812c23 sw s0,24(sp) +80001718: 01512223 sw s5,4(sp) +8000171c: 0ff97913 andi s2,s2,255 +80001720: 00058a13 mv s4,a1 +80001724: 0094d493 srli s1,s1,0x9 +80001728: 01f55993 srli s3,a0,0x1f +8000172c: 08090663 beqz s2,800017b8 <__mulsf3+0xc4> +80001730: 0ff00793 li a5,255 +80001734: 0af90263 beq s2,a5,800017d8 <__mulsf3+0xe4> +80001738: 00349493 slli s1,s1,0x3 +8000173c: 040007b7 lui a5,0x4000 +80001740: 00f4e4b3 or s1,s1,a5 +80001744: f8190913 addi s2,s2,-127 +80001748: 00000a93 li s5,0 +8000174c: 017a5793 srli a5,s4,0x17 +80001750: 009a1413 slli s0,s4,0x9 +80001754: 0ff7f793 andi a5,a5,255 +80001758: 00945413 srli s0,s0,0x9 +8000175c: 01fa5a13 srli s4,s4,0x1f +80001760: 08078c63 beqz a5,800017f8 <__mulsf3+0x104> +80001764: 0ff00713 li a4,255 +80001768: 0ae78863 beq a5,a4,80001818 <__mulsf3+0x124> +8000176c: 00341413 slli s0,s0,0x3 +80001770: 04000737 lui a4,0x4000 +80001774: 00e46433 or s0,s0,a4 +80001778: f8178793 addi a5,a5,-127 # 3ffff81 <_start-0x7c00007f> +8000177c: 00000713 li a4,0 +80001780: 002a9693 slli a3,s5,0x2 +80001784: 00e6e6b3 or a3,a3,a4 +80001788: 00f907b3 add a5,s2,a5 +8000178c: fff68693 addi a3,a3,-1 +80001790: 00e00593 li a1,14 +80001794: 0149c533 xor a0,s3,s4 +80001798: 00178613 addi a2,a5,1 +8000179c: 08d5ee63 bltu a1,a3,80001838 <__mulsf3+0x144> +800017a0: 800027b7 lui a5,0x80002 +800017a4: 32878793 addi a5,a5,808 # 80002328 <__global_pointer$+0xffffe6c0> +800017a8: 00269693 slli a3,a3,0x2 +800017ac: 00f686b3 add a3,a3,a5 +800017b0: 0006a783 lw a5,0(a3) +800017b4: 00078067 jr a5 +800017b8: 02048a63 beqz s1,800017ec <__mulsf3+0xf8> +800017bc: 00048513 mv a0,s1 +800017c0: 6bc000ef jal ra,80001e7c <__clzsi2> +800017c4: ffb50793 addi a5,a0,-5 +800017c8: f8a00913 li s2,-118 +800017cc: 00f494b3 sll s1,s1,a5 +800017d0: 40a90933 sub s2,s2,a0 +800017d4: f75ff06f j 80001748 <__mulsf3+0x54> +800017d8: 0ff00913 li s2,255 +800017dc: 00200a93 li s5,2 +800017e0: f60486e3 beqz s1,8000174c <__mulsf3+0x58> +800017e4: 00300a93 li s5,3 +800017e8: f65ff06f j 8000174c <__mulsf3+0x58> +800017ec: 00000913 li s2,0 +800017f0: 00100a93 li s5,1 +800017f4: f59ff06f j 8000174c <__mulsf3+0x58> +800017f8: 02040a63 beqz s0,8000182c <__mulsf3+0x138> +800017fc: 00040513 mv a0,s0 +80001800: 67c000ef jal ra,80001e7c <__clzsi2> +80001804: ffb50793 addi a5,a0,-5 +80001808: 00f41433 sll s0,s0,a5 +8000180c: f8a00793 li a5,-118 +80001810: 40a787b3 sub a5,a5,a0 +80001814: f69ff06f j 8000177c <__mulsf3+0x88> +80001818: 0ff00793 li a5,255 +8000181c: 00200713 li a4,2 +80001820: f60400e3 beqz s0,80001780 <__mulsf3+0x8c> +80001824: 00300713 li a4,3 +80001828: f59ff06f j 80001780 <__mulsf3+0x8c> +8000182c: 00000793 li a5,0 +80001830: 00100713 li a4,1 +80001834: f4dff06f j 80001780 <__mulsf3+0x8c> +80001838: 00010737 lui a4,0x10 +8000183c: fff70893 addi a7,a4,-1 # ffff <_start-0x7fff0001> +80001840: 0104d693 srli a3,s1,0x10 +80001844: 01045593 srli a1,s0,0x10 +80001848: 0114f4b3 and s1,s1,a7 +8000184c: 01147433 and s0,s0,a7 +80001850: 02940833 mul a6,s0,s1 +80001854: 02868433 mul s0,a3,s0 +80001858: 02b686b3 mul a3,a3,a1 +8000185c: 029585b3 mul a1,a1,s1 +80001860: 01085493 srli s1,a6,0x10 +80001864: 008585b3 add a1,a1,s0 +80001868: 00b484b3 add s1,s1,a1 +8000186c: 0084f463 bgeu s1,s0,80001874 <__mulsf3+0x180> +80001870: 00e686b3 add a3,a3,a4 +80001874: 0114f733 and a4,s1,a7 +80001878: 01071713 slli a4,a4,0x10 +8000187c: 01187833 and a6,a6,a7 +80001880: 01070733 add a4,a4,a6 +80001884: 00671413 slli s0,a4,0x6 +80001888: 0104d493 srli s1,s1,0x10 +8000188c: 00803433 snez s0,s0 +80001890: 01a75713 srli a4,a4,0x1a +80001894: 00d484b3 add s1,s1,a3 +80001898: 00e46733 or a4,s0,a4 +8000189c: 00649493 slli s1,s1,0x6 +800018a0: 00e4e433 or s0,s1,a4 +800018a4: 00449713 slli a4,s1,0x4 +800018a8: 08075c63 bgez a4,80001940 <__mulsf3+0x24c> +800018ac: 00145793 srli a5,s0,0x1 +800018b0: 00147413 andi s0,s0,1 +800018b4: 0087e433 or s0,a5,s0 +800018b8: 07f60713 addi a4,a2,127 +800018bc: 08e05663 blez a4,80001948 <__mulsf3+0x254> +800018c0: 00747793 andi a5,s0,7 +800018c4: 00078a63 beqz a5,800018d8 <__mulsf3+0x1e4> +800018c8: 00f47793 andi a5,s0,15 +800018cc: 00400693 li a3,4 +800018d0: 00d78463 beq a5,a3,800018d8 <__mulsf3+0x1e4> +800018d4: 00440413 addi s0,s0,4 # 400004 <_start-0x7fbffffc> +800018d8: 00441793 slli a5,s0,0x4 +800018dc: 0007da63 bgez a5,800018f0 <__mulsf3+0x1fc> +800018e0: f80007b7 lui a5,0xf8000 +800018e4: fff78793 addi a5,a5,-1 # f7ffffff <__global_pointer$+0x77ffc397> +800018e8: 00f47433 and s0,s0,a5 +800018ec: 08060713 addi a4,a2,128 +800018f0: 0fe00793 li a5,254 +800018f4: 00345413 srli s0,s0,0x3 +800018f8: 0ae7d863 bge a5,a4,800019a8 <__mulsf3+0x2b4> +800018fc: 00000413 li s0,0 +80001900: 0ff00713 li a4,255 +80001904: 0a40006f j 800019a8 <__mulsf3+0x2b4> +80001908: 00098513 mv a0,s3 +8000190c: 00048413 mv s0,s1 +80001910: 000a8713 mv a4,s5 +80001914: 00200793 li a5,2 +80001918: fef702e3 beq a4,a5,800018fc <__mulsf3+0x208> +8000191c: 00300793 li a5,3 +80001920: 06f70e63 beq a4,a5,8000199c <__mulsf3+0x2a8> +80001924: 00100793 li a5,1 +80001928: f8f718e3 bne a4,a5,800018b8 <__mulsf3+0x1c4> +8000192c: 00000413 li s0,0 +80001930: 00000713 li a4,0 +80001934: 0740006f j 800019a8 <__mulsf3+0x2b4> +80001938: 000a0513 mv a0,s4 +8000193c: fd9ff06f j 80001914 <__mulsf3+0x220> +80001940: 00078613 mv a2,a5 +80001944: f75ff06f j 800018b8 <__mulsf3+0x1c4> +80001948: 00100793 li a5,1 +8000194c: 40e787b3 sub a5,a5,a4 +80001950: 01b00713 li a4,27 +80001954: fcf74ce3 blt a4,a5,8000192c <__mulsf3+0x238> +80001958: 09e60613 addi a2,a2,158 +8000195c: 00f457b3 srl a5,s0,a5 +80001960: 00c41433 sll s0,s0,a2 +80001964: 00803433 snez s0,s0 +80001968: 0087e433 or s0,a5,s0 +8000196c: 00747793 andi a5,s0,7 +80001970: 00078a63 beqz a5,80001984 <__mulsf3+0x290> +80001974: 00f47793 andi a5,s0,15 +80001978: 00400713 li a4,4 +8000197c: 00e78463 beq a5,a4,80001984 <__mulsf3+0x290> +80001980: 00440413 addi s0,s0,4 +80001984: 00541793 slli a5,s0,0x5 +80001988: 00345413 srli s0,s0,0x3 +8000198c: fa07d2e3 bgez a5,80001930 <__mulsf3+0x23c> +80001990: 00000413 li s0,0 +80001994: 00100713 li a4,1 +80001998: 0100006f j 800019a8 <__mulsf3+0x2b4> +8000199c: 00400437 lui s0,0x400 +800019a0: 0ff00713 li a4,255 +800019a4: 00000513 li a0,0 +800019a8: 01771713 slli a4,a4,0x17 +800019ac: 7f8007b7 lui a5,0x7f800 +800019b0: 00941413 slli s0,s0,0x9 +800019b4: 00f77733 and a4,a4,a5 +800019b8: 00945413 srli s0,s0,0x9 +800019bc: 00876433 or s0,a4,s0 +800019c0: 01f51513 slli a0,a0,0x1f +800019c4: 01c12083 lw ra,28(sp) +800019c8: 00a46533 or a0,s0,a0 +800019cc: 01812403 lw s0,24(sp) +800019d0: 01412483 lw s1,20(sp) +800019d4: 01012903 lw s2,16(sp) +800019d8: 00c12983 lw s3,12(sp) +800019dc: 00812a03 lw s4,8(sp) +800019e0: 00412a83 lw s5,4(sp) +800019e4: 02010113 addi sp,sp,32 +800019e8: 00008067 ret + +800019ec <__subsf3>: +800019ec: 008006b7 lui a3,0x800 +800019f0: ff010113 addi sp,sp,-16 +800019f4: fff68693 addi a3,a3,-1 # 7fffff <_start-0x7f800001> +800019f8: 01755613 srli a2,a0,0x17 +800019fc: 0175d893 srli a7,a1,0x17 +80001a00: 00a6f7b3 and a5,a3,a0 +80001a04: 00912223 sw s1,4(sp) +80001a08: 00b6f6b3 and a3,a3,a1 +80001a0c: 01212023 sw s2,0(sp) +80001a10: 0ff67613 andi a2,a2,255 +80001a14: 01f55493 srli s1,a0,0x1f +80001a18: 0ff8f893 andi a7,a7,255 +80001a1c: 00112623 sw ra,12(sp) +80001a20: 00812423 sw s0,8(sp) +80001a24: 0ff00513 li a0,255 +80001a28: 00060913 mv s2,a2 +80001a2c: 00379793 slli a5,a5,0x3 +80001a30: 00088713 mv a4,a7 +80001a34: 01f5d593 srli a1,a1,0x1f +80001a38: 00369693 slli a3,a3,0x3 +80001a3c: 00a89463 bne a7,a0,80001a44 <__subsf3+0x58> +80001a40: 00069463 bnez a3,80001a48 <__subsf3+0x5c> +80001a44: 0015c593 xori a1,a1,1 +80001a48: 41160833 sub a6,a2,a7 +80001a4c: 16959e63 bne a1,s1,80001bc8 <__subsf3+0x1dc> +80001a50: 09005c63 blez a6,80001ae8 <__subsf3+0xfc> +80001a54: 04089c63 bnez a7,80001aac <__subsf3+0xc0> +80001a58: 34068463 beqz a3,80001da0 <__subsf3+0x3b4> +80001a5c: fff80813 addi a6,a6,-1 +80001a60: 02081e63 bnez a6,80001a9c <__subsf3+0xb0> +80001a64: 00d787b3 add a5,a5,a3 +80001a68: 00060713 mv a4,a2 +80001a6c: 00579693 slli a3,a5,0x5 +80001a70: 1006dc63 bgez a3,80001b88 <__subsf3+0x19c> +80001a74: 00170713 addi a4,a4,1 +80001a78: 0ff00693 li a3,255 +80001a7c: 32d70c63 beq a4,a3,80001db4 <__subsf3+0x3c8> +80001a80: 7e0006b7 lui a3,0x7e000 +80001a84: 0017f613 andi a2,a5,1 +80001a88: fff68693 addi a3,a3,-1 # 7dffffff <_start-0x2000001> +80001a8c: 0017d793 srli a5,a5,0x1 +80001a90: 00d7f7b3 and a5,a5,a3 +80001a94: 00c7e7b3 or a5,a5,a2 +80001a98: 0f00006f j 80001b88 <__subsf3+0x19c> +80001a9c: 0ff00713 li a4,255 +80001aa0: 00e61e63 bne a2,a4,80001abc <__subsf3+0xd0> +80001aa4: 0ff00713 li a4,255 +80001aa8: 0e00006f j 80001b88 <__subsf3+0x19c> +80001aac: 0ff00713 li a4,255 +80001ab0: fee60ae3 beq a2,a4,80001aa4 <__subsf3+0xb8> +80001ab4: 04000737 lui a4,0x4000 +80001ab8: 00e6e6b3 or a3,a3,a4 +80001abc: 01b00593 li a1,27 +80001ac0: 00100713 li a4,1 +80001ac4: 0105ce63 blt a1,a6,80001ae0 <__subsf3+0xf4> +80001ac8: 02000713 li a4,32 +80001acc: 0106d5b3 srl a1,a3,a6 +80001ad0: 41070833 sub a6,a4,a6 +80001ad4: 010696b3 sll a3,a3,a6 +80001ad8: 00d036b3 snez a3,a3 +80001adc: 00d5e733 or a4,a1,a3 +80001ae0: 00e787b3 add a5,a5,a4 +80001ae4: f85ff06f j 80001a68 <__subsf3+0x7c> +80001ae8: 06080663 beqz a6,80001b54 <__subsf3+0x168> +80001aec: 40c885b3 sub a1,a7,a2 +80001af0: 02061463 bnez a2,80001b18 <__subsf3+0x12c> +80001af4: 2a078a63 beqz a5,80001da8 <__subsf3+0x3bc> +80001af8: fff58593 addi a1,a1,-1 +80001afc: 00059663 bnez a1,80001b08 <__subsf3+0x11c> +80001b00: 00d787b3 add a5,a5,a3 +80001b04: f69ff06f j 80001a6c <__subsf3+0x80> +80001b08: 0ff00613 li a2,255 +80001b0c: 00c89e63 bne a7,a2,80001b28 <__subsf3+0x13c> +80001b10: 00068793 mv a5,a3 +80001b14: f91ff06f j 80001aa4 <__subsf3+0xb8> +80001b18: 0ff00613 li a2,255 +80001b1c: fec88ae3 beq a7,a2,80001b10 <__subsf3+0x124> +80001b20: 04000637 lui a2,0x4000 +80001b24: 00c7e7b3 or a5,a5,a2 +80001b28: 01b00513 li a0,27 +80001b2c: 00100613 li a2,1 +80001b30: 00b54e63 blt a0,a1,80001b4c <__subsf3+0x160> +80001b34: 02000613 li a2,32 +80001b38: 40b60633 sub a2,a2,a1 +80001b3c: 00b7d533 srl a0,a5,a1 +80001b40: 00c797b3 sll a5,a5,a2 +80001b44: 00f037b3 snez a5,a5 +80001b48: 00f56633 or a2,a0,a5 +80001b4c: 00d607b3 add a5,a2,a3 +80001b50: f1dff06f j 80001a6c <__subsf3+0x80> +80001b54: 00160593 addi a1,a2,1 # 4000001 <_start-0x7bffffff> +80001b58: 0fe5f713 andi a4,a1,254 +80001b5c: 04071a63 bnez a4,80001bb0 <__subsf3+0x1c4> +80001b60: 04061263 bnez a2,80001ba4 <__subsf3+0x1b8> +80001b64: 24078263 beqz a5,80001da8 <__subsf3+0x3bc> +80001b68: 02068063 beqz a3,80001b88 <__subsf3+0x19c> +80001b6c: 00d787b3 add a5,a5,a3 +80001b70: 00579693 slli a3,a5,0x5 +80001b74: 0006da63 bgez a3,80001b88 <__subsf3+0x19c> +80001b78: fc000737 lui a4,0xfc000 +80001b7c: fff70713 addi a4,a4,-1 # fbffffff <__global_pointer$+0x7bffc397> +80001b80: 00e7f7b3 and a5,a5,a4 +80001b84: 00100713 li a4,1 +80001b88: 0077f693 andi a3,a5,7 +80001b8c: 22068663 beqz a3,80001db8 <__subsf3+0x3cc> +80001b90: 00f7f693 andi a3,a5,15 +80001b94: 00400613 li a2,4 +80001b98: 22c68063 beq a3,a2,80001db8 <__subsf3+0x3cc> +80001b9c: 00478793 addi a5,a5,4 # 7f800004 <_start-0x7ffffc> +80001ba0: 2180006f j 80001db8 <__subsf3+0x3cc> +80001ba4: f60786e3 beqz a5,80001b10 <__subsf3+0x124> +80001ba8: ee068ee3 beqz a3,80001aa4 <__subsf3+0xb8> +80001bac: 1700006f j 80001d1c <__subsf3+0x330> +80001bb0: 0ff00713 li a4,255 +80001bb4: 1ee58e63 beq a1,a4,80001db0 <__subsf3+0x3c4> +80001bb8: 00d787b3 add a5,a5,a3 +80001bbc: 0017d793 srli a5,a5,0x1 +80001bc0: 00058713 mv a4,a1 +80001bc4: fc5ff06f j 80001b88 <__subsf3+0x19c> +80001bc8: 09005663 blez a6,80001c54 <__subsf3+0x268> +80001bcc: 06089863 bnez a7,80001c3c <__subsf3+0x250> +80001bd0: 00060713 mv a4,a2 +80001bd4: fa068ae3 beqz a3,80001b88 <__subsf3+0x19c> +80001bd8: fff80813 addi a6,a6,-1 +80001bdc: 02081263 bnez a6,80001c00 <__subsf3+0x214> +80001be0: 40d787b3 sub a5,a5,a3 +80001be4: 00579693 slli a3,a5,0x5 +80001be8: fa06d0e3 bgez a3,80001b88 <__subsf3+0x19c> +80001bec: 04000437 lui s0,0x4000 +80001bf0: fff40413 addi s0,s0,-1 # 3ffffff <_start-0x7c000001> +80001bf4: 0087f433 and s0,a5,s0 +80001bf8: 00070913 mv s2,a4 +80001bfc: 1440006f j 80001d40 <__subsf3+0x354> +80001c00: 0ff00593 li a1,255 +80001c04: 0ff00713 li a4,255 +80001c08: f8b600e3 beq a2,a1,80001b88 <__subsf3+0x19c> +80001c0c: 01b00593 li a1,27 +80001c10: 00100713 li a4,1 +80001c14: 0105ce63 blt a1,a6,80001c30 <__subsf3+0x244> +80001c18: 02000713 li a4,32 +80001c1c: 0106d5b3 srl a1,a3,a6 +80001c20: 41070833 sub a6,a4,a6 +80001c24: 010696b3 sll a3,a3,a6 +80001c28: 00d036b3 snez a3,a3 +80001c2c: 00d5e733 or a4,a1,a3 +80001c30: 40e787b3 sub a5,a5,a4 +80001c34: 00060713 mv a4,a2 +80001c38: fadff06f j 80001be4 <__subsf3+0x1f8> +80001c3c: 0ff00593 li a1,255 +80001c40: 0ff00713 li a4,255 +80001c44: f4b602e3 beq a2,a1,80001b88 <__subsf3+0x19c> +80001c48: 04000737 lui a4,0x4000 +80001c4c: 00e6e6b3 or a3,a3,a4 +80001c50: fbdff06f j 80001c0c <__subsf3+0x220> +80001c54: 06080a63 beqz a6,80001cc8 <__subsf3+0x2dc> +80001c58: 40c88533 sub a0,a7,a2 +80001c5c: 02061863 bnez a2,80001c8c <__subsf3+0x2a0> +80001c60: 08078063 beqz a5,80001ce0 <__subsf3+0x2f4> +80001c64: fff50513 addi a0,a0,-1 +80001c68: 00051863 bnez a0,80001c78 <__subsf3+0x28c> +80001c6c: 40f687b3 sub a5,a3,a5 +80001c70: 00058493 mv s1,a1 +80001c74: f71ff06f j 80001be4 <__subsf3+0x1f8> +80001c78: 0ff00613 li a2,255 +80001c7c: 02c89063 bne a7,a2,80001c9c <__subsf3+0x2b0> +80001c80: 00068793 mv a5,a3 +80001c84: 00058493 mv s1,a1 +80001c88: e1dff06f j 80001aa4 <__subsf3+0xb8> +80001c8c: 0ff00613 li a2,255 +80001c90: fec888e3 beq a7,a2,80001c80 <__subsf3+0x294> +80001c94: 04000637 lui a2,0x4000 +80001c98: 00c7e7b3 or a5,a5,a2 +80001c9c: 01b00813 li a6,27 +80001ca0: 00100613 li a2,1 +80001ca4: 00a84e63 blt a6,a0,80001cc0 <__subsf3+0x2d4> +80001ca8: 02000613 li a2,32 +80001cac: 40a60633 sub a2,a2,a0 +80001cb0: 00a7d833 srl a6,a5,a0 +80001cb4: 00c797b3 sll a5,a5,a2 +80001cb8: 00f037b3 snez a5,a5 +80001cbc: 00f86633 or a2,a6,a5 +80001cc0: 40c687b3 sub a5,a3,a2 +80001cc4: fadff06f j 80001c70 <__subsf3+0x284> +80001cc8: 00160713 addi a4,a2,1 # 4000001 <_start-0x7bffffff> +80001ccc: 0fe77713 andi a4,a4,254 +80001cd0: 04071e63 bnez a4,80001d2c <__subsf3+0x340> +80001cd4: 04061063 bnez a2,80001d14 <__subsf3+0x328> +80001cd8: 00079863 bnez a5,80001ce8 <__subsf3+0x2fc> +80001cdc: 02068663 beqz a3,80001d08 <__subsf3+0x31c> +80001ce0: 00068793 mv a5,a3 +80001ce4: 0180006f j 80001cfc <__subsf3+0x310> +80001ce8: ea0680e3 beqz a3,80001b88 <__subsf3+0x19c> +80001cec: 40d78633 sub a2,a5,a3 +80001cf0: 00561513 slli a0,a2,0x5 +80001cf4: 00055863 bgez a0,80001d04 <__subsf3+0x318> +80001cf8: 40f687b3 sub a5,a3,a5 +80001cfc: 00058493 mv s1,a1 +80001d00: e89ff06f j 80001b88 <__subsf3+0x19c> +80001d04: 12061263 bnez a2,80001e28 <__subsf3+0x43c> +80001d08: 00000793 li a5,0 +80001d0c: 00000493 li s1,0 +80001d10: 0a80006f j 80001db8 <__subsf3+0x3cc> +80001d14: e8079ae3 bnez a5,80001ba8 <__subsf3+0x1bc> +80001d18: f60694e3 bnez a3,80001c80 <__subsf3+0x294> +80001d1c: 00000493 li s1,0 +80001d20: 020007b7 lui a5,0x2000 +80001d24: 0ff00713 li a4,255 +80001d28: 0900006f j 80001db8 <__subsf3+0x3cc> +80001d2c: 40d78433 sub s0,a5,a3 +80001d30: 00541713 slli a4,s0,0x5 +80001d34: 04075463 bgez a4,80001d7c <__subsf3+0x390> +80001d38: 40f68433 sub s0,a3,a5 +80001d3c: 00058493 mv s1,a1 +80001d40: 00040513 mv a0,s0 +80001d44: 138000ef jal ra,80001e7c <__clzsi2> +80001d48: ffb50713 addi a4,a0,-5 +80001d4c: 00e41433 sll s0,s0,a4 +80001d50: 03274e63 blt a4,s2,80001d8c <__subsf3+0x3a0> +80001d54: 41270733 sub a4,a4,s2 +80001d58: 00170713 addi a4,a4,1 # 4000001 <_start-0x7bffffff> +80001d5c: 02000693 li a3,32 +80001d60: 00e457b3 srl a5,s0,a4 +80001d64: 40e68733 sub a4,a3,a4 +80001d68: 00e41433 sll s0,s0,a4 +80001d6c: 00803433 snez s0,s0 +80001d70: 0087e7b3 or a5,a5,s0 +80001d74: 00000713 li a4,0 +80001d78: e11ff06f j 80001b88 <__subsf3+0x19c> +80001d7c: fc0412e3 bnez s0,80001d40 <__subsf3+0x354> +80001d80: 00000793 li a5,0 +80001d84: 00000713 li a4,0 +80001d88: f85ff06f j 80001d0c <__subsf3+0x320> +80001d8c: fc0007b7 lui a5,0xfc000 +80001d90: fff78793 addi a5,a5,-1 # fbffffff <__global_pointer$+0x7bffc397> +80001d94: 40e90733 sub a4,s2,a4 +80001d98: 00f477b3 and a5,s0,a5 +80001d9c: dedff06f j 80001b88 <__subsf3+0x19c> +80001da0: 00060713 mv a4,a2 +80001da4: de5ff06f j 80001b88 <__subsf3+0x19c> +80001da8: 00068793 mv a5,a3 +80001dac: dddff06f j 80001b88 <__subsf3+0x19c> +80001db0: 0ff00713 li a4,255 +80001db4: 00000793 li a5,0 +80001db8: 00579693 slli a3,a5,0x5 +80001dbc: 0006de63 bgez a3,80001dd8 <__subsf3+0x3ec> +80001dc0: 00170713 addi a4,a4,1 +80001dc4: 0ff00693 li a3,255 +80001dc8: 06d70463 beq a4,a3,80001e30 <__subsf3+0x444> +80001dcc: fc0006b7 lui a3,0xfc000 +80001dd0: fff68693 addi a3,a3,-1 # fbffffff <__global_pointer$+0x7bffc397> +80001dd4: 00d7f7b3 and a5,a5,a3 +80001dd8: 0ff00693 li a3,255 +80001ddc: 0037d793 srli a5,a5,0x3 +80001de0: 00d71863 bne a4,a3,80001df0 <__subsf3+0x404> +80001de4: 00078663 beqz a5,80001df0 <__subsf3+0x404> +80001de8: 004007b7 lui a5,0x400 +80001dec: 00000493 li s1,0 +80001df0: 00c12083 lw ra,12(sp) +80001df4: 00812403 lw s0,8(sp) +80001df8: 7f800537 lui a0,0x7f800 +80001dfc: 01771713 slli a4,a4,0x17 +80001e00: 00979793 slli a5,a5,0x9 +80001e04: 00a77733 and a4,a4,a0 +80001e08: 0097d793 srli a5,a5,0x9 +80001e0c: 01f49513 slli a0,s1,0x1f +80001e10: 00f767b3 or a5,a4,a5 +80001e14: 00412483 lw s1,4(sp) +80001e18: 00012903 lw s2,0(sp) +80001e1c: 00a7e533 or a0,a5,a0 +80001e20: 01010113 addi sp,sp,16 +80001e24: 00008067 ret +80001e28: 00060793 mv a5,a2 +80001e2c: d5dff06f j 80001b88 <__subsf3+0x19c> +80001e30: 00000793 li a5,0 +80001e34: fa5ff06f j 80001dd8 <__subsf3+0x3ec> + +80001e38 <__unordsf2>: +80001e38: 008007b7 lui a5,0x800 +80001e3c: fff78793 addi a5,a5,-1 # 7fffff <_start-0x7f800001> +80001e40: 00a7f733 and a4,a5,a0 +80001e44: 01755513 srli a0,a0,0x17 +80001e48: 00b7f7b3 and a5,a5,a1 +80001e4c: 0ff57513 andi a0,a0,255 +80001e50: 0175d593 srli a1,a1,0x17 +80001e54: 0ff00693 li a3,255 +80001e58: 0ff5f593 andi a1,a1,255 +80001e5c: 00d51663 bne a0,a3,80001e68 <__unordsf2+0x30> +80001e60: 00100513 li a0,1 +80001e64: 00071a63 bnez a4,80001e78 <__unordsf2+0x40> +80001e68: 0ff00713 li a4,255 +80001e6c: 00000513 li a0,0 +80001e70: 00e59463 bne a1,a4,80001e78 <__unordsf2+0x40> +80001e74: 00f03533 snez a0,a5 +80001e78: 00008067 ret + +80001e7c <__clzsi2>: +80001e7c: 000107b7 lui a5,0x10 +80001e80: 02f57a63 bgeu a0,a5,80001eb4 <__clzsi2+0x38> +80001e84: 0ff00793 li a5,255 +80001e88: 00a7b7b3 sltu a5,a5,a0 +80001e8c: 00379793 slli a5,a5,0x3 +80001e90: 80002737 lui a4,0x80002 +80001e94: 02000693 li a3,32 +80001e98: 40f686b3 sub a3,a3,a5 +80001e9c: 00f55533 srl a0,a0,a5 +80001ea0: 36470793 addi a5,a4,868 # 80002364 <__global_pointer$+0xffffe6fc> +80001ea4: 00a78533 add a0,a5,a0 +80001ea8: 00054503 lbu a0,0(a0) # 7f800000 <_start-0x800000> +80001eac: 40a68533 sub a0,a3,a0 +80001eb0: 00008067 ret +80001eb4: 01000737 lui a4,0x1000 +80001eb8: 01000793 li a5,16 +80001ebc: fce56ae3 bltu a0,a4,80001e90 <__clzsi2+0x14> +80001ec0: 01800793 li a5,24 +80001ec4: fcdff06f j 80001e90 <__clzsi2+0x14> + +80001ec8 : +80001ec8: 00050593 mv a1,a0 +80001ecc: 00000693 li a3,0 +80001ed0: 00000613 li a2,0 +80001ed4: 00000513 li a0,0 +80001ed8: 2100006f j 800020e8 <__register_exitproc> + +80001edc <__errno>: +80001edc: c341a503 lw a0,-972(gp) # 8000389c <_impure_ptr> +80001ee0: 00008067 ret + +80001ee4 : +80001ee4: ff010113 addi sp,sp,-16 +80001ee8: 00000593 li a1,0 +80001eec: 00812423 sw s0,8(sp) +80001ef0: 00112623 sw ra,12(sp) +80001ef4: 00050413 mv s0,a0 +80001ef8: 288000ef jal ra,80002180 <__call_exitprocs> +80001efc: c301a503 lw a0,-976(gp) # 80003898 <_global_impure_ptr> +80001f00: 03c52783 lw a5,60(a0) +80001f04: 00078463 beqz a5,80001f0c +80001f08: 000780e7 jalr a5 # 10000 <_start-0x7fff0000> +80001f0c: 00040513 mv a0,s0 +80001f10: c8dfe0ef jal ra,80000b9c <_exit> + +80001f14 <__libc_fini_array>: +80001f14: ff010113 addi sp,sp,-16 +80001f18: 00812423 sw s0,8(sp) +80001f1c: 800037b7 lui a5,0x80003 +80001f20: 80003437 lui s0,0x80003 +80001f24: 46840413 addi s0,s0,1128 # 80003468 <__global_pointer$+0xfffff800> +80001f28: 46878793 addi a5,a5,1128 # 80003468 <__global_pointer$+0xfffff800> +80001f2c: 408787b3 sub a5,a5,s0 +80001f30: 00912223 sw s1,4(sp) +80001f34: 00112623 sw ra,12(sp) +80001f38: 4027d493 srai s1,a5,0x2 +80001f3c: 02048063 beqz s1,80001f5c <__libc_fini_array+0x48> +80001f40: ffc78793 addi a5,a5,-4 +80001f44: 00878433 add s0,a5,s0 +80001f48: 00042783 lw a5,0(s0) +80001f4c: fff48493 addi s1,s1,-1 +80001f50: ffc40413 addi s0,s0,-4 +80001f54: 000780e7 jalr a5 +80001f58: fe0498e3 bnez s1,80001f48 <__libc_fini_array+0x34> +80001f5c: 00c12083 lw ra,12(sp) +80001f60: 00812403 lw s0,8(sp) +80001f64: 00412483 lw s1,4(sp) +80001f68: 01010113 addi sp,sp,16 +80001f6c: 00008067 ret + +80001f70 <__libc_init_array>: +80001f70: ff010113 addi sp,sp,-16 +80001f74: 00812423 sw s0,8(sp) +80001f78: 01212023 sw s2,0(sp) +80001f7c: 80003437 lui s0,0x80003 +80001f80: 80003937 lui s2,0x80003 +80001f84: 46440793 addi a5,s0,1124 # 80003464 <__global_pointer$+0xfffff7fc> +80001f88: 46490913 addi s2,s2,1124 # 80003464 <__global_pointer$+0xfffff7fc> +80001f8c: 40f90933 sub s2,s2,a5 +80001f90: 00112623 sw ra,12(sp) +80001f94: 00912223 sw s1,4(sp) +80001f98: 40295913 srai s2,s2,0x2 +80001f9c: 02090063 beqz s2,80001fbc <__libc_init_array+0x4c> +80001fa0: 46440413 addi s0,s0,1124 +80001fa4: 00000493 li s1,0 +80001fa8: 00042783 lw a5,0(s0) +80001fac: 00148493 addi s1,s1,1 +80001fb0: 00440413 addi s0,s0,4 +80001fb4: 000780e7 jalr a5 +80001fb8: fe9918e3 bne s2,s1,80001fa8 <__libc_init_array+0x38> +80001fbc: 80003437 lui s0,0x80003 +80001fc0: 80003937 lui s2,0x80003 +80001fc4: 46440793 addi a5,s0,1124 # 80003464 <__global_pointer$+0xfffff7fc> +80001fc8: 46890913 addi s2,s2,1128 # 80003468 <__global_pointer$+0xfffff800> +80001fcc: 40f90933 sub s2,s2,a5 +80001fd0: 40295913 srai s2,s2,0x2 +80001fd4: 02090063 beqz s2,80001ff4 <__libc_init_array+0x84> +80001fd8: 46440413 addi s0,s0,1124 +80001fdc: 00000493 li s1,0 +80001fe0: 00042783 lw a5,0(s0) +80001fe4: 00148493 addi s1,s1,1 +80001fe8: 00440413 addi s0,s0,4 +80001fec: 000780e7 jalr a5 +80001ff0: fe9918e3 bne s2,s1,80001fe0 <__libc_init_array+0x70> +80001ff4: 00c12083 lw ra,12(sp) +80001ff8: 00812403 lw s0,8(sp) +80001ffc: 00412483 lw s1,4(sp) +80002000: 00012903 lw s2,0(sp) +80002004: 01010113 addi sp,sp,16 +80002008: 00008067 ret + +8000200c : +8000200c: 00f00313 li t1,15 +80002010: 00050713 mv a4,a0 +80002014: 02c37e63 bgeu t1,a2,80002050 +80002018: 00f77793 andi a5,a4,15 +8000201c: 0a079063 bnez a5,800020bc +80002020: 08059263 bnez a1,800020a4 +80002024: ff067693 andi a3,a2,-16 +80002028: 00f67613 andi a2,a2,15 +8000202c: 00e686b3 add a3,a3,a4 +80002030: 00b72023 sw a1,0(a4) # 1000000 <_start-0x7f000000> +80002034: 00b72223 sw a1,4(a4) +80002038: 00b72423 sw a1,8(a4) +8000203c: 00b72623 sw a1,12(a4) +80002040: 01070713 addi a4,a4,16 +80002044: fed766e3 bltu a4,a3,80002030 +80002048: 00061463 bnez a2,80002050 +8000204c: 00008067 ret +80002050: 40c306b3 sub a3,t1,a2 +80002054: 00269693 slli a3,a3,0x2 +80002058: 00000297 auipc t0,0x0 +8000205c: 005686b3 add a3,a3,t0 +80002060: 00c68067 jr 12(a3) +80002064: 00b70723 sb a1,14(a4) +80002068: 00b706a3 sb a1,13(a4) +8000206c: 00b70623 sb a1,12(a4) +80002070: 00b705a3 sb a1,11(a4) +80002074: 00b70523 sb a1,10(a4) +80002078: 00b704a3 sb a1,9(a4) +8000207c: 00b70423 sb a1,8(a4) +80002080: 00b703a3 sb a1,7(a4) +80002084: 00b70323 sb a1,6(a4) +80002088: 00b702a3 sb a1,5(a4) +8000208c: 00b70223 sb a1,4(a4) +80002090: 00b701a3 sb a1,3(a4) +80002094: 00b70123 sb a1,2(a4) +80002098: 00b700a3 sb a1,1(a4) +8000209c: 00b70023 sb a1,0(a4) +800020a0: 00008067 ret +800020a4: 0ff5f593 andi a1,a1,255 +800020a8: 00859693 slli a3,a1,0x8 +800020ac: 00d5e5b3 or a1,a1,a3 +800020b0: 01059693 slli a3,a1,0x10 +800020b4: 00d5e5b3 or a1,a1,a3 +800020b8: f6dff06f j 80002024 +800020bc: 00279693 slli a3,a5,0x2 +800020c0: 00000297 auipc t0,0x0 +800020c4: 005686b3 add a3,a3,t0 +800020c8: 00008293 mv t0,ra +800020cc: fa0680e7 jalr -96(a3) +800020d0: 00028093 mv ra,t0 +800020d4: ff078793 addi a5,a5,-16 +800020d8: 40f70733 sub a4,a4,a5 +800020dc: 00f60633 add a2,a2,a5 +800020e0: f6c378e3 bgeu t1,a2,80002050 +800020e4: f3dff06f j 80002020 + +800020e8 <__register_exitproc>: +800020e8: c301a703 lw a4,-976(gp) # 80003898 <_global_impure_ptr> +800020ec: 14872783 lw a5,328(a4) +800020f0: 04078c63 beqz a5,80002148 <__register_exitproc+0x60> +800020f4: 0047a703 lw a4,4(a5) +800020f8: 01f00813 li a6,31 +800020fc: 06e84e63 blt a6,a4,80002178 <__register_exitproc+0x90> +80002100: 00271813 slli a6,a4,0x2 +80002104: 02050663 beqz a0,80002130 <__register_exitproc+0x48> +80002108: 01078333 add t1,a5,a6 +8000210c: 08c32423 sw a2,136(t1) +80002110: 1887a883 lw a7,392(a5) +80002114: 00100613 li a2,1 +80002118: 00e61633 sll a2,a2,a4 +8000211c: 00c8e8b3 or a7,a7,a2 +80002120: 1917a423 sw a7,392(a5) +80002124: 10d32423 sw a3,264(t1) +80002128: 00200693 li a3,2 +8000212c: 02d50463 beq a0,a3,80002154 <__register_exitproc+0x6c> +80002130: 00170713 addi a4,a4,1 +80002134: 00e7a223 sw a4,4(a5) +80002138: 010787b3 add a5,a5,a6 +8000213c: 00b7a423 sw a1,8(a5) +80002140: 00000513 li a0,0 +80002144: 00008067 ret +80002148: 14c70793 addi a5,a4,332 +8000214c: 14f72423 sw a5,328(a4) +80002150: fa5ff06f j 800020f4 <__register_exitproc+0xc> +80002154: 18c7a683 lw a3,396(a5) +80002158: 00170713 addi a4,a4,1 +8000215c: 00e7a223 sw a4,4(a5) +80002160: 00c6e633 or a2,a3,a2 +80002164: 18c7a623 sw a2,396(a5) +80002168: 010787b3 add a5,a5,a6 +8000216c: 00b7a423 sw a1,8(a5) +80002170: 00000513 li a0,0 +80002174: 00008067 ret +80002178: fff00513 li a0,-1 +8000217c: 00008067 ret + +80002180 <__call_exitprocs>: +80002180: fd010113 addi sp,sp,-48 +80002184: 01412c23 sw s4,24(sp) +80002188: c301aa03 lw s4,-976(gp) # 80003898 <_global_impure_ptr> +8000218c: 03212023 sw s2,32(sp) +80002190: 02112623 sw ra,44(sp) +80002194: 148a2903 lw s2,328(s4) +80002198: 02812423 sw s0,40(sp) +8000219c: 02912223 sw s1,36(sp) +800021a0: 01312e23 sw s3,28(sp) +800021a4: 01512a23 sw s5,20(sp) +800021a8: 01612823 sw s6,16(sp) +800021ac: 01712623 sw s7,12(sp) +800021b0: 01812423 sw s8,8(sp) +800021b4: 04090063 beqz s2,800021f4 <__call_exitprocs+0x74> +800021b8: 00050b13 mv s6,a0 +800021bc: 00058b93 mv s7,a1 +800021c0: 00100a93 li s5,1 +800021c4: fff00993 li s3,-1 +800021c8: 00492483 lw s1,4(s2) +800021cc: fff48413 addi s0,s1,-1 +800021d0: 02044263 bltz s0,800021f4 <__call_exitprocs+0x74> +800021d4: 00249493 slli s1,s1,0x2 +800021d8: 009904b3 add s1,s2,s1 +800021dc: 040b8463 beqz s7,80002224 <__call_exitprocs+0xa4> +800021e0: 1044a783 lw a5,260(s1) +800021e4: 05778063 beq a5,s7,80002224 <__call_exitprocs+0xa4> +800021e8: fff40413 addi s0,s0,-1 +800021ec: ffc48493 addi s1,s1,-4 +800021f0: ff3416e3 bne s0,s3,800021dc <__call_exitprocs+0x5c> +800021f4: 02c12083 lw ra,44(sp) +800021f8: 02812403 lw s0,40(sp) +800021fc: 02412483 lw s1,36(sp) +80002200: 02012903 lw s2,32(sp) +80002204: 01c12983 lw s3,28(sp) +80002208: 01812a03 lw s4,24(sp) +8000220c: 01412a83 lw s5,20(sp) +80002210: 01012b03 lw s6,16(sp) +80002214: 00c12b83 lw s7,12(sp) +80002218: 00812c03 lw s8,8(sp) +8000221c: 03010113 addi sp,sp,48 +80002220: 00008067 ret +80002224: 00492783 lw a5,4(s2) +80002228: 0044a683 lw a3,4(s1) +8000222c: fff78793 addi a5,a5,-1 +80002230: 04878e63 beq a5,s0,8000228c <__call_exitprocs+0x10c> +80002234: 0004a223 sw zero,4(s1) +80002238: fa0688e3 beqz a3,800021e8 <__call_exitprocs+0x68> +8000223c: 18892783 lw a5,392(s2) +80002240: 008a9733 sll a4,s5,s0 +80002244: 00492c03 lw s8,4(s2) +80002248: 00f777b3 and a5,a4,a5 +8000224c: 02079263 bnez a5,80002270 <__call_exitprocs+0xf0> +80002250: 000680e7 jalr a3 +80002254: 00492703 lw a4,4(s2) +80002258: 148a2783 lw a5,328(s4) +8000225c: 01871463 bne a4,s8,80002264 <__call_exitprocs+0xe4> +80002260: f8f904e3 beq s2,a5,800021e8 <__call_exitprocs+0x68> +80002264: f80788e3 beqz a5,800021f4 <__call_exitprocs+0x74> +80002268: 00078913 mv s2,a5 +8000226c: f5dff06f j 800021c8 <__call_exitprocs+0x48> +80002270: 18c92783 lw a5,396(s2) +80002274: 0844a583 lw a1,132(s1) +80002278: 00f77733 and a4,a4,a5 +8000227c: 00071c63 bnez a4,80002294 <__call_exitprocs+0x114> +80002280: 000b0513 mv a0,s6 +80002284: 000680e7 jalr a3 +80002288: fcdff06f j 80002254 <__call_exitprocs+0xd4> +8000228c: 00892223 sw s0,4(s2) +80002290: fa9ff06f j 80002238 <__call_exitprocs+0xb8> +80002294: 00058513 mv a0,a1 +80002298: 000680e7 jalr a3 +8000229c: fb9ff06f j 80002254 <__call_exitprocs+0xd4> + +Disassembly of section .rodata: + +800022a0 : +800022a0: 00b0 addi a2,sp,72 +800022a2: 8000 0x8000 +800022a4: 013c addi a5,sp,136 +800022a6: 8000 0x8000 +800022a8: 01c8 addi a0,sp,196 +800022aa: 8000 0x8000 +800022ac: 0254 addi a3,sp,260 +800022ae: 8000 0x8000 +800022b0: 02e8 addi a0,sp,332 +800022b2: 8000 0x8000 +800022b4: 0374 addi a3,sp,396 +800022b6: 8000 0x8000 +800022b8: 0400 addi s0,sp,512 +800022ba: 8000 0x8000 +800022bc: 048c addi a1,sp,576 +800022be: 8000 0x8000 +800022c0: 051c addi a5,sp,640 +800022c2: 8000 0x8000 +800022c4: 05ac addi a1,sp,712 +800022c6: 8000 0x8000 +800022c8: 063c addi a5,sp,776 +800022ca: 8000 0x8000 +800022cc: 06cc addi a1,sp,836 +800022ce: 8000 0x8000 +800022d0: 0768 addi a0,sp,908 +800022d2: 8000 0x8000 +800022d4: 07f4 addi a3,sp,972 +800022d6: 8000 0x8000 +800022d8: 0ac8 addi a0,sp,340 +800022da: 8000 0x8000 +800022dc: 0888 addi a0,sp,80 +800022de: 8000 0x8000 +800022e0: 0918 addi a4,sp,144 +800022e2: 8000 0x8000 +800022e4: 09a8 addi a0,sp,216 +800022e6: 8000 0x8000 +800022e8: 0a38 addi a4,sp,280 +800022ea: 8000 0x8000 +800022ec: 15ac addi a1,sp,744 +800022ee: 8000 0x8000 +800022f0: 1634 addi a3,sp,808 +800022f2: 8000 0x8000 +800022f4: 15b8 addi a4,sp,744 +800022f6: 8000 0x8000 +800022f8: 1634 addi a3,sp,808 +800022fa: 8000 0x8000 +800022fc: 1624 addi s1,sp,808 +800022fe: 8000 0x8000 +80002300: 1634 addi a3,sp,808 +80002302: 8000 0x8000 +80002304: 15b8 addi a4,sp,744 +80002306: 8000 0x8000 +80002308: 15ac addi a1,sp,744 +8000230a: 8000 0x8000 +8000230c: 15ac addi a1,sp,744 +8000230e: 8000 0x8000 +80002310: 1624 addi s1,sp,808 +80002312: 8000 0x8000 +80002314: 15b8 addi a4,sp,744 +80002316: 8000 0x8000 +80002318: 1588 addi a0,sp,736 +8000231a: 8000 0x8000 +8000231c: 1588 addi a0,sp,736 +8000231e: 8000 0x8000 +80002320: 1588 addi a0,sp,736 +80002322: 8000 0x8000 +80002324: 15c0 addi s0,sp,740 +80002326: 8000 0x8000 +80002328: 1914 addi a3,sp,176 +8000232a: 8000 0x8000 +8000232c: 1914 addi a3,sp,176 +8000232e: 8000 0x8000 +80002330: 1938 addi a4,sp,184 +80002332: 8000 0x8000 +80002334: 190c addi a1,sp,176 +80002336: 8000 0x8000 +80002338: 190c addi a1,sp,176 +8000233a: 8000 0x8000 +8000233c: 199c addi a5,sp,240 +8000233e: 8000 0x8000 +80002340: 1938 addi a4,sp,184 +80002342: 8000 0x8000 +80002344: 190c addi a1,sp,176 +80002346: 8000 0x8000 +80002348: 199c addi a5,sp,240 +8000234a: 8000 0x8000 +8000234c: 190c addi a1,sp,176 +8000234e: 8000 0x8000 +80002350: 1938 addi a4,sp,184 +80002352: 8000 0x8000 +80002354: 1908 addi a0,sp,176 +80002356: 8000 0x8000 +80002358: 1908 addi a0,sp,176 +8000235a: 8000 0x8000 +8000235c: 1908 addi a0,sp,176 +8000235e: 8000 0x8000 +80002360: 199c addi a5,sp,240 +80002362: 8000 0x8000 + +80002364 <__clz_tab>: +80002364: 0100 addi s0,sp,128 +80002366: 0202 c.slli64 tp +80002368: 03030303 lb t1,48(t1) +8000236c: 0404 addi s1,sp,512 +8000236e: 0404 addi s1,sp,512 +80002370: 0404 addi s1,sp,512 +80002372: 0404 addi s1,sp,512 +80002374: 0505 addi a0,a0,1 +80002376: 0505 addi a0,a0,1 +80002378: 0505 addi a0,a0,1 +8000237a: 0505 addi a0,a0,1 +8000237c: 0505 addi a0,a0,1 +8000237e: 0505 addi a0,a0,1 +80002380: 0505 addi a0,a0,1 +80002382: 0505 addi a0,a0,1 +80002384: 0606 slli a2,a2,0x1 +80002386: 0606 slli a2,a2,0x1 +80002388: 0606 slli a2,a2,0x1 +8000238a: 0606 slli a2,a2,0x1 +8000238c: 0606 slli a2,a2,0x1 +8000238e: 0606 slli a2,a2,0x1 +80002390: 0606 slli a2,a2,0x1 +80002392: 0606 slli a2,a2,0x1 +80002394: 0606 slli a2,a2,0x1 +80002396: 0606 slli a2,a2,0x1 +80002398: 0606 slli a2,a2,0x1 +8000239a: 0606 slli a2,a2,0x1 +8000239c: 0606 slli a2,a2,0x1 +8000239e: 0606 slli a2,a2,0x1 +800023a0: 0606 slli a2,a2,0x1 +800023a2: 0606 slli a2,a2,0x1 +800023a4: 07070707 0x7070707 +800023a8: 07070707 0x7070707 +800023ac: 07070707 0x7070707 +800023b0: 07070707 0x7070707 +800023b4: 07070707 0x7070707 +800023b8: 07070707 0x7070707 +800023bc: 07070707 0x7070707 +800023c0: 07070707 0x7070707 +800023c4: 07070707 0x7070707 +800023c8: 07070707 0x7070707 +800023cc: 07070707 0x7070707 +800023d0: 07070707 0x7070707 +800023d4: 07070707 0x7070707 +800023d8: 07070707 0x7070707 +800023dc: 07070707 0x7070707 +800023e0: 07070707 0x7070707 +800023e4: 0808 addi a0,sp,16 +800023e6: 0808 addi a0,sp,16 +800023e8: 0808 addi a0,sp,16 +800023ea: 0808 addi a0,sp,16 +800023ec: 0808 addi a0,sp,16 +800023ee: 0808 addi a0,sp,16 +800023f0: 0808 addi a0,sp,16 +800023f2: 0808 addi a0,sp,16 +800023f4: 0808 addi a0,sp,16 +800023f6: 0808 addi a0,sp,16 +800023f8: 0808 addi a0,sp,16 +800023fa: 0808 addi a0,sp,16 +800023fc: 0808 addi a0,sp,16 +800023fe: 0808 addi a0,sp,16 +80002400: 0808 addi a0,sp,16 +80002402: 0808 addi a0,sp,16 +80002404: 0808 addi a0,sp,16 +80002406: 0808 addi a0,sp,16 +80002408: 0808 addi a0,sp,16 +8000240a: 0808 addi a0,sp,16 +8000240c: 0808 addi a0,sp,16 +8000240e: 0808 addi a0,sp,16 +80002410: 0808 addi a0,sp,16 +80002412: 0808 addi a0,sp,16 +80002414: 0808 addi a0,sp,16 +80002416: 0808 addi a0,sp,16 +80002418: 0808 addi a0,sp,16 +8000241a: 0808 addi a0,sp,16 +8000241c: 0808 addi a0,sp,16 +8000241e: 0808 addi a0,sp,16 +80002420: 0808 addi a0,sp,16 +80002422: 0808 addi a0,sp,16 +80002424: 0808 addi a0,sp,16 +80002426: 0808 addi a0,sp,16 +80002428: 0808 addi a0,sp,16 +8000242a: 0808 addi a0,sp,16 +8000242c: 0808 addi a0,sp,16 +8000242e: 0808 addi a0,sp,16 +80002430: 0808 addi a0,sp,16 +80002432: 0808 addi a0,sp,16 +80002434: 0808 addi a0,sp,16 +80002436: 0808 addi a0,sp,16 +80002438: 0808 addi a0,sp,16 +8000243a: 0808 addi a0,sp,16 +8000243c: 0808 addi a0,sp,16 +8000243e: 0808 addi a0,sp,16 +80002440: 0808 addi a0,sp,16 +80002442: 0808 addi a0,sp,16 +80002444: 0808 addi a0,sp,16 +80002446: 0808 addi a0,sp,16 +80002448: 0808 addi a0,sp,16 +8000244a: 0808 addi a0,sp,16 +8000244c: 0808 addi a0,sp,16 +8000244e: 0808 addi a0,sp,16 +80002450: 0808 addi a0,sp,16 +80002452: 0808 addi a0,sp,16 +80002454: 0808 addi a0,sp,16 +80002456: 0808 addi a0,sp,16 +80002458: 0808 addi a0,sp,16 +8000245a: 0808 addi a0,sp,16 +8000245c: 0808 addi a0,sp,16 +8000245e: 0808 addi a0,sp,16 +80002460: 0808 addi a0,sp,16 +80002462: 0808 addi a0,sp,16 + +Disassembly of section .init_array: + +80003464 <__init_array_start>: +80003464: 0098 addi a4,sp,64 +80003466: 8000 0x8000 + +Disassembly of section .data: + +80003468 : +80003468: 0000 unimp +8000346a: 0000 unimp +8000346c: 3754 fld fa3,168(a4) +8000346e: 8000 0x8000 +80003470: 37bc fld fa5,104(a5) +80003472: 8000 0x8000 +80003474: 3824 fld fs1,112(s0) +80003476: 8000 0x8000 + ... +80003510: 0001 nop +80003512: 0000 unimp +80003514: 0000 unimp +80003516: 0000 unimp +80003518: 330e fld ft6,224(sp) +8000351a: abcd j 80003b0c <__BSS_END__+0x264> +8000351c: 1234 addi a3,sp,296 +8000351e: e66d bnez a2,80003608 +80003520: deec sw a1,124(a3) +80003522: 0005 c.nop 1 +80003524: 0000000b 0xb + ... + +Disassembly of section .sdata: + +80003890 <__SDATA_BEGIN__>: +80003890: 0000 unimp +80003892: 3f00 fld fs0,56(a4) +80003894: 0000 unimp +80003896: bf00 fsd fs0,56(a4) + +80003898 <_global_impure_ptr>: +80003898: 3468 fld fa0,232(s0) +8000389a: 8000 0x8000 + +8000389c <_impure_ptr>: +8000389c: 3468 fld fa0,232(s0) +8000389e: 8000 0x8000 + +Disassembly of section .sbss: + +800038a0 : +800038a0: 0000 unimp + ... + +800038a4 <__fdlib_version>: +800038a4: 0000 unimp + ... + +Disassembly of section .comment: + +00000000 <.comment>: + 0: 3a434347 fmsub.d ft6,ft6,ft4,ft7,rmm + 4: 2820 fld fs0,80(s0) + 6: 29554e47 fmsub.s ft8,fa0,fs5,ft5,rmm + a: 3920 fld fs0,112(a0) + c: 322e fld ft4,232(sp) + e: 302e fld ft0,232(sp) + ... + +Disassembly of section .riscv.attributes: + +00000000 <.riscv.attributes>: + 0: 2541 jal 680 <_start-0x7ffff980> + 2: 0000 unimp + 4: 7200 flw fs0,32(a2) + 6: 7369 lui t1,0xffffa + 8: 01007663 bgeu zero,a6,14 <_start-0x7fffffec> + c: 0000001b 0x1b + 10: 1004 addi s1,sp,32 + 12: 7205 lui tp,0xfffe1 + 14: 3376 fld ft6,376(sp) + 16: 6932 flw fs2,12(sp) + 18: 7032 flw ft0,44(sp) + 1a: 5f30 lw a2,120(a4) + 1c: 326d jal fffff9c6 <__global_pointer$+0x7fffbd5e> + 1e: 3070 fld fa2,224(s0) + 20: 665f 7032 0030 0x307032665f + +Disassembly of section .debug_aranges: + +00000000 <.debug_aranges>: + 0: 001c 0x1c + 2: 0000 unimp + 4: 0002 c.slli64 zero + 6: 0000 unimp + 8: 0000 unimp + a: 0004 0x4 + c: 0000 unimp + e: 0000 unimp + 10: 0ee8 addi a0,sp,860 + 12: 8000 0x8000 + 14: 042c addi a1,sp,520 + ... + 1e: 0000 unimp + 20: 001c 0x1c + 22: 0000 unimp + 24: 0002 c.slli64 zero + 26: 035d addi t1,t1,23 + 28: 0000 unimp + 2a: 0004 0x4 + 2c: 0000 unimp + 2e: 0000 unimp + 30: 1314 addi a3,sp,416 + 32: 8000 0x8000 + 34: 032c addi a1,sp,392 + ... + 3e: 0000 unimp + 40: 001c 0x1c + 42: 0000 unimp + 44: 0002 c.slli64 zero + 46: 0718 addi a4,sp,896 + 48: 0000 unimp + 4a: 0004 0x4 + 4c: 0000 unimp + 4e: 0000 unimp + 50: 1640 addi s0,sp,804 + 52: 8000 0x8000 + 54: 00b4 addi a3,sp,72 + ... + 5e: 0000 unimp + 60: 001c 0x1c + 62: 0000 unimp + 64: 0002 c.slli64 zero + 66: 097f 0x97f + 68: 0000 unimp + 6a: 0004 0x4 + 6c: 0000 unimp + 6e: 0000 unimp + 70: 16f4 addi a3,sp,876 + 72: 8000 0x8000 + 74: 02f8 addi a4,sp,332 + ... + 7e: 0000 unimp + 80: 001c 0x1c + 82: 0000 unimp + 84: 0002 c.slli64 zero + 86: 00000d2b 0xd2b + 8a: 0004 0x4 + 8c: 0000 unimp + 8e: 0000 unimp + 90: 19ec addi a1,sp,252 + 92: 8000 0x8000 + 94: 044c addi a1,sp,516 + ... + 9e: 0000 unimp + a0: 001c 0x1c + a2: 0000 unimp + a4: 0002 c.slli64 zero + a6: 1088 addi a0,sp,96 + a8: 0000 unimp + aa: 0004 0x4 + ac: 0000 unimp + ae: 0000 unimp + b0: 1e38 addi a4,sp,824 + b2: 8000 0x8000 + b4: 0044 addi s1,sp,4 + ... + be: 0000 unimp + c0: 001c 0x1c + c2: 0000 unimp + c4: 0002 c.slli64 zero + c6: 000012db 0x12db + ca: 0004 0x4 + cc: 0000 unimp + ce: 0000 unimp + d0: 1e7c addi a5,sp,828 + d2: 8000 0x8000 + d4: 004c addi a1,sp,4 + ... + de: 0000 unimp + e0: 0014 0x14 + e2: 0000 unimp + e4: 0002 c.slli64 zero + e6: 1eb2 slli t4,t4,0x2c + e8: 0000 unimp + ea: 0004 0x4 + ... + +Disassembly of section .debug_info: + +00000000 <.debug_info>: + 0: 0359 addi t1,t1,22 + 2: 0000 unimp + 4: 0004 0x4 + 6: 0000 unimp + 8: 0000 unimp + a: 0104 addi s1,sp,128 + c: 0182 c.slli64 gp + e: 0000 unimp + 10: 3e0c fld fa1,56(a2) + 12: 0002 c.slli64 zero + 14: f600 fsw fs0,40(a2) + 16: 0000 unimp + 18: e800 fsw fs0,16(s0) + 1a: 000e c.slli zero,0x3 + 1c: 2c80 fld fs0,24(s1) + 1e: 0004 0x4 + 20: 0000 unimp + 22: 0000 unimp + 24: 0200 addi s0,sp,256 + 26: 0404 addi s1,sp,512 + 28: 000008cb fnmsub.s fa7,ft0,ft0,ft0,rne + 2c: 69050403 lb s0,1680(a0) + 30: 746e flw fs0,248(sp) + 32: 0200 addi s0,sp,256 + 34: 0601 addi a2,a2,0 + 36: 0062 c.slli zero,0x18 + 38: 0000 unimp + 3a: 0802 c.slli64 a6 + 3c: 7405 lui s0,0xfffe1 + 3e: 0001 nop + 40: 0400 addi s0,sp,512 + 42: 00c8 addi a0,sp,68 + 44: 0000 unimp + 46: 4a02 lw s4,0(sp) + 48: 1601 addi a2,a2,-32 + 4a: 00000053 fadd.s ft0,ft0,ft0,rne + 4e: 4105 li sp,1 + 50: 0000 unimp + 52: 0200 addi s0,sp,256 + 54: 0801 addi a6,a6,0 + 56: 0060 addi s0,sp,12 + 58: 0000 unimp + 5a: 0402 c.slli64 s0 + 5c: 0000e907 0xe907 + 60: 0200 addi s0,sp,256 + 62: 0708 addi a0,sp,896 + 64: 00df 0000 0202 0x202000000df + 6a: 00008c07 0x8c07 + 6e: 0600 addi s0,sp,768 + 70: 004e c.slli zero,0x13 + 72: 0000 unimp + 74: 007f 0x7f + 76: 0000 unimp + 78: 00005a07 0x5a07 + 7c: ff00 fsw fs0,56(a4) + 7e: 0500 addi s0,sp,640 + 80: 0000006f j 80 <_start-0x7fffff80> + 84: d008 sw a0,32(s0) + 86: 0000 unimp + 88: 0400 addi s0,sp,512 + 8a: 163c addi a5,sp,808 + 8c: 007f 0x7f + 8e: 0000 unimp + 90: 8709 srai a4,a4,0x2 + 92: 0002 c.slli64 zero + 94: 0300 addi s0,sp,384 + 96: 0f45 addi t5,t5,17 + 98: 0025 c.nop 9 + 9a: 0000 unimp + 9c: 040a slli s0,s0,0x2 + 9e: d6034a03 lbu s4,-672(t1) # ffff9d60 <__global_pointer$+0x7fff60f8> + a2: 0000 unimp + a4: 0b00 addi s0,sp,400 + a6: 00da slli ra,ra,0x16 + a8: 0000 unimp + aa: 5a0e5103 lhu sp,1440(t3) + ae: 0000 unimp + b0: 0400 addi s0,sp,512 + b2: 0c000917 auipc s2,0xc000 + b6: 7865 lui a6,0xffff9 + b8: 0070 addi a2,sp,12 + ba: 5a0e5203 lhu tp,1440(t3) + be: 0000 unimp + c0: 0400 addi s0,sp,512 + c2: 0108 addi a0,sp,128 + c4: 0b00 addi s0,sp,400 + c6: 0781 addi a5,a5,0 + c8: 0000 unimp + ca: 5a0e5303 lhu t1,1440(t3) + ce: 0000 unimp + d0: 0400 addi s0,sp,512 + d2: 0001 nop + d4: 0000 unimp + d6: 7b0d lui s6,0xfffe3 + d8: 0002 c.slli64 zero + da: 0400 addi s0,sp,512 + dc: fc074703 lbu a4,-64(a4) + e0: 0000 unimp + e2: 0e00 addi s0,sp,784 + e4: 6c66 flw fs8,88(sp) + e6: 0074 addi a3,sp,12 + e8: 900a4903 lbu s2,-1792(s4) + ec: 0000 unimp + ee: 0f00 addi s0,sp,912 + f0: 0239 addi tp,tp,14 + f2: 0000 unimp + f4: 9c055503 lhu a0,-1600(a0) + f8: 0000 unimp + fa: 0000 unimp + fc: 8310 0x8310 + fe: 0000 unimp + 100: 0100 addi s0,sp,128 + 102: 00900123 sb s1,2(zero) # 2 <_start-0x7ffffffe> + 106: 0000 unimp + 108: 0ee8 addi a0,sp,860 + 10a: 8000 0x8000 + 10c: 042c addi a1,sp,520 + 10e: 0000 unimp + 110: 9c01 0x9c01 + 112: 034e slli t1,t1,0x13 + 114: 0000 unimp + 116: 6111 addi sp,sp,256 + 118: 0100 addi s0,sp,128 + 11a: 00901223 sh s1,4(zero) # 4 <_start-0x7ffffffc> + 11e: 0000 unimp + 120: 0000 unimp + 122: 0000 unimp + 124: 6211 lui tp,0x4 + 126: 0100 addi s0,sp,128 + 128: 00901c23 sh s1,24(zero) # 18 <_start-0x7fffffe8> + 12c: 0000 unimp + 12e: 0116 slli sp,sp,0x5 + 130: 0000 unimp + 132: 2812 fld fa6,256(sp) + 134: 0000 unimp + 136: 0100 addi s0,sp,128 + 138: 0325 addi t1,t1,9 + 13a: 002c addi a1,sp,8 + 13c: 0000 unimp + 13e: 0139 addi sp,sp,14 + 140: 0000 unimp + 142: 0002a713 slti a4,t0,0 + 146: 0100 addi s0,sp,128 + 148: 0325 addi t1,t1,9 + 14a: 002c addi a1,sp,8 + 14c: 0000 unimp + 14e: 1400 addi s0,sp,544 + 150: 5f41 li t5,-16 + 152: 26010063 beqz sp,3b2 <_start-0x7ffffc4e> + 156: 00034e03 lbu t3,0(t1) + 15a: 1500 addi s0,sp,672 + 15c: 5f41 li t5,-16 + 15e: 26010073 0x26010073 + 162: 00034e03 lbu t3,0(t1) + 166: 7d00 flw fs0,56(a0) + 168: 0001 nop + 16a: 1500 addi s0,sp,672 + 16c: 5f41 li t5,-16 + 16e: 0065 c.nop 25 + 170: 2601 jal 470 <_start-0x7ffffb90> + 172: 00034e03 lbu t3,0(t1) + 176: 2b00 fld fs0,16(a4) + 178: 0002 c.slli64 zero + 17a: 1500 addi s0,sp,672 + 17c: 5f41 li t5,-16 + 17e: 0066 c.slli zero,0x19 + 180: 2601 jal 480 <_start-0x7ffffb80> + 182: 00035503 lhu a0,0(t1) + 186: 8b00 0x8b00 + 188: 0002 c.slli64 zero + 18a: 1400 addi s0,sp,544 + 18c: 5f42 lw t5,48(sp) + 18e: 27010063 beq sp,a6,3ee <_start-0x7ffffc12> + 192: 00034e03 lbu t3,0(t1) + 196: 1500 addi s0,sp,672 + 198: 5f42 lw t5,48(sp) + 19a: 27010073 0x27010073 + 19e: 00034e03 lbu t3,0(t1) + 1a2: 8c00 0x8c00 + 1a4: 0004 0x4 + 1a6: 1500 addi s0,sp,672 + 1a8: 5f42 lw t5,48(sp) + 1aa: 0065 c.nop 25 + 1ac: 2701 jal 8ac <_start-0x7ffff754> + 1ae: 00034e03 lbu t3,0(t1) + 1b2: 0d00 addi s0,sp,656 + 1b4: 0005 c.nop 1 + 1b6: 1500 addi s0,sp,672 + 1b8: 5f42 lw t5,48(sp) + 1ba: 0066 c.slli zero,0x19 + 1bc: 2701 jal 8bc <_start-0x7ffff744> + 1be: 00035503 lhu a0,0(t1) + 1c2: 8300 0x8300 + 1c4: 0005 c.nop 1 + 1c6: 1400 addi s0,sp,544 + 1c8: 5f52 lw t5,52(sp) + 1ca: 28010063 beqz sp,44a <_start-0x7ffffbb6> + 1ce: 00034e03 lbu t3,0(t1) + 1d2: 1500 addi s0,sp,672 + 1d4: 5f52 lw t5,52(sp) + 1d6: 28010073 0x28010073 + 1da: 00034e03 lbu t3,0(t1) + 1de: f900 fsw fs0,48(a0) + 1e0: 0005 c.nop 1 + 1e2: 1500 addi s0,sp,672 + 1e4: 5f52 lw t5,52(sp) + 1e6: 0065 c.nop 25 + 1e8: 2801 jal 1f8 <_start-0x7ffffe08> + 1ea: 00034e03 lbu t3,0(t1) + 1ee: 7a00 flw fs0,48(a2) + 1f0: 0006 c.slli zero,0x1 + 1f2: 1500 addi s0,sp,672 + 1f4: 5f52 lw t5,52(sp) + 1f6: 0066 c.slli zero,0x19 + 1f8: 2801 jal 208 <_start-0x7ffffdf8> + 1fa: 00035503 lhu a0,0(t1) + 1fe: ce00 sw s0,24(a2) + 200: 15000007 0x15000007 + 204: 0072 c.slli zero,0x1c + 206: 2901 jal 616 <_start-0x7ffff9ea> + 208: 900a c.add zero,sp + 20a: 0000 unimp + 20c: 5f00 lw s0,56(a4) + 20e: 0009 c.nop 2 + 210: 1600 addi s0,sp,800 + 212: 0000 unimp + 214: 0000 unimp + 216: 00000227 0x227 + 21a: 00006e17 auipc t3,0x6 + 21e: 0100 addi s0,sp,128 + 220: 032c addi a1,sp,392 + 222: 00d6 slli ra,ra,0x15 + 224: 0000 unimp + 226: 1600 addi s0,sp,800 + 228: 0048 addi a0,sp,4 + 22a: 0000 unimp + 22c: 023d addi tp,tp,15 + 22e: 0000 unimp + 230: 00006e17 auipc t3,0x6 + 234: 0100 addi s0,sp,128 + 236: 032d addi t1,t1,11 + 238: 00d6 slli ra,ra,0x15 + 23a: 0000 unimp + 23c: 1600 addi s0,sp,800 + 23e: 0068 addi a0,sp,12 + 240: 0000 unimp + 242: 00000287 0x287 + 246: 6c18 flw fa4,24(s0) + 248: 0002 c.slli64 zero + 24a: 0100 addi s0,sp,128 + 24c: 032e slli t1,t1,0xb + 24e: 0fa0 addi s0,sp,984 + 250: 8000 0x8000 + 252: 7118 flw fa4,32(a0) + 254: 0002 c.slli64 zero + 256: 0100 addi s0,sp,128 + 258: 032e slli t1,t1,0xb + 25a: 100c addi a1,sp,32 + 25c: 8000 0x8000 + 25e: 7618 flw fa4,40(a2) + 260: 0002 c.slli64 zero + 262: 0100 addi s0,sp,128 + 264: 032e slli t1,t1,0xb + 266: 0f50 addi a2,sp,916 + 268: 8000 0x8000 + 26a: 5718 lw a4,40(a4) + 26c: 0000 unimp + 26e: 0100 addi s0,sp,128 + 270: 032e slli t1,t1,0xb + 272: 106c addi a1,sp,44 + 274: 8000 0x8000 + 276: 2212 fld ft4,256(sp) + 278: 0002 c.slli64 zero + 27a: 0100 addi s0,sp,128 + 27c: 032e slli t1,t1,0xb + 27e: 002c addi a1,sp,8 + 280: 0000 unimp + 282: 0984 addi s1,sp,208 + 284: 0000 unimp + 286: 1600 addi s0,sp,800 + 288: 00a8 addi a0,sp,72 + 28a: 0000 unimp + 28c: 000002f3 0x2f3 + 290: 9f18 0x9f18 + 292: 0000 unimp + 294: 0100 addi s0,sp,128 + 296: 032e slli t1,t1,0xb + 298: 10fc addi a5,sp,108 + 29a: 8000 0x8000 + 29c: a418 fsd fa4,8(s0) + 29e: 0000 unimp + 2a0: 0100 addi s0,sp,128 + 2a2: 032e slli t1,t1,0xb + 2a4: 118c addi a1,sp,224 + 2a6: 8000 0x8000 + 2a8: a918 fsd fa4,16(a0) + 2aa: 0000 unimp + 2ac: 0100 addi s0,sp,128 + 2ae: 032e slli t1,t1,0xb + 2b0: 10d4 addi a3,sp,100 + 2b2: 8000 0x8000 + 2b4: c318 sw a4,0(a4) + 2b6: 0000 unimp + 2b8: 0100 addi s0,sp,128 + 2ba: 032e slli t1,t1,0xb + 2bc: 1224 addi s1,sp,296 + 2be: 8000 0x8000 + 2c0: 5518 lw a4,40(a0) + 2c2: 0001 nop + 2c4: 0100 addi s0,sp,128 + 2c6: 032e slli t1,t1,0xb + 2c8: 106c addi a1,sp,44 + 2ca: 8000 0x8000 + 2cc: 2212 fld ft4,256(sp) + 2ce: 0002 c.slli64 zero + 2d0: 0100 addi s0,sp,128 + 2d2: 032e slli t1,t1,0xb + 2d4: 002c addi a1,sp,8 + 2d6: 0000 unimp + 2d8: 09fa slli s3,s3,0x1e + 2da: 0000 unimp + 2dc: e819 bnez s0,2f2 <_start-0x7ffffd0e> + 2de: 0000 unimp + 2e0: 1200 addi s0,sp,288 + 2e2: 015e slli sp,sp,0x17 + 2e4: 0000 unimp + 2e6: 2e01 jal 5f6 <_start-0x7ffffa0a> + 2e8: 00002c03 lw s8,0(zero) # 0 <_start-0x80000000> + 2ec: 6e00 flw fs0,24(a2) + 2ee: 000a c.slli zero,0x2 + 2f0: 0000 unimp + 2f2: 1600 addi s0,sp,800 + 2f4: 0108 addi a0,sp,128 + 2f6: 0000 unimp + 2f8: 0000033b 0x33b + 2fc: 00028e17 auipc t3,0x28 + 300: 0100 addi s0,sp,128 + 302: 002c032f 0x2c032f + 306: 0000 unimp + 308: 171a slli a4,a4,0x26 + 30a: 002d c.nop 11 + 30c: 0000 unimp + 30e: 2f01 jal a1e <_start-0x7ffff5e2> + 310: 00034e03 lbu t3,0(t1) + 314: 1700 addi s0,sp,928 + 316: 00000013 nop + 31a: 2f01 jal a2a <_start-0x7ffff5d6> + 31c: 00034e03 lbu t3,0(t1) + 320: 1700 addi s0,sp,928 + 322: 00ae slli ra,ra,0xb + 324: 0000 unimp + 326: 2f01 jal a36 <_start-0x7ffff5ca> + 328: 00034e03 lbu t3,0(t1) + 32c: 1700 addi s0,sp,928 + 32e: 0042 c.slli zero,0x10 + 330: 0000 unimp + 332: 2f01 jal a42 <_start-0x7ffff5be> + 334: 00035503 lhu a0,0(t1) + 338: 0000 unimp + 33a: 1900 addi s0,sp,176 + 33c: 0128 addi a0,sp,136 + 33e: 0000 unimp + 340: 00000017 auipc zero,0x0 + 344: 0100 addi s0,sp,128 + 346: 00d6032f 0xd6032f + 34a: 0000 unimp + 34c: 0000 unimp + 34e: 0402 c.slli64 s0 + 350: 7905 lui s2,0xfffe1 + 352: 0001 nop + 354: 0200 addi s0,sp,256 + 356: 0704 addi s1,sp,896 + 358: 00e4 addi s1,sp,76 + 35a: 0000 unimp + 35c: b700 fsd fs0,40(a4) + 35e: 04000003 lb zero,64(zero) # 40 <_start-0x7fffffc0> + 362: 8400 0x8400 + 364: 0001 nop + 366: 0400 addi s0,sp,512 + 368: 8201 c.srli64 a2 + 36a: 0001 nop + 36c: 0c00 addi s0,sp,528 + 36e: 000002db 0x2db + 372: 00f6 slli ra,ra,0x1d + 374: 0000 unimp + 376: 1314 addi a3,sp,416 + 378: 8000 0x8000 + 37a: 032c addi a1,sp,392 + 37c: 0000 unimp + 37e: 0a4e slli s4,s4,0x13 + 380: 0000 unimp + 382: 0402 c.slli64 s0 + 384: cb04 sw s1,16(a4) + 386: 0008 0x8 + 388: 0300 addi s0,sp,384 + 38a: 0504 addi s1,sp,640 + 38c: 6e69 lui t3,0x1a + 38e: 0074 addi a3,sp,12 + 390: 0102 c.slli64 sp + 392: 6206 flw ft4,64(sp) + 394: 0000 unimp + 396: 0200 addi s0,sp,256 + 398: 0508 addi a0,sp,640 + 39a: 0174 addi a3,sp,140 + 39c: 0000 unimp + 39e: c804 sw s1,16(s0) + 3a0: 0000 unimp + 3a2: 0200 addi s0,sp,256 + 3a4: 014a slli sp,sp,0x12 + 3a6: 5316 lw t1,100(sp) + 3a8: 0000 unimp + 3aa: 0500 addi s0,sp,640 + 3ac: 0041 c.nop 16 + 3ae: 0000 unimp + 3b0: 0102 c.slli64 sp + 3b2: 6008 flw fa0,0(s0) + 3b4: 0000 unimp + 3b6: 0200 addi s0,sp,256 + 3b8: 0704 addi s1,sp,896 + 3ba: 00e9 addi ra,ra,26 + 3bc: 0000 unimp + 3be: 0802 c.slli64 a6 + 3c0: 0000df07 0xdf07 + 3c4: 0200 addi s0,sp,256 + 3c6: 0702 c.slli64 a4 + 3c8: 008c addi a1,sp,64 + 3ca: 0000 unimp + 3cc: 4e06 lw t3,64(sp) + 3ce: 0000 unimp + 3d0: 7f00 flw fs0,56(a4) + 3d2: 0000 unimp + 3d4: 0700 addi s0,sp,896 + 3d6: 005a c.slli zero,0x16 + 3d8: 0000 unimp + 3da: 00ff 0xff + 3dc: 6f05 lui t5,0x1 + 3de: 0000 unimp + 3e0: 0800 addi s0,sp,16 + 3e2: 00d0 addi a2,sp,68 + 3e4: 0000 unimp + 3e6: 3c04 fld fs1,56(s0) + 3e8: 7f16 flw ft10,100(sp) + 3ea: 0000 unimp + 3ec: 0900 addi s0,sp,144 + 3ee: 00000287 0x287 + 3f2: 250f4503 lbu a0,592(t5) # 1250 <_start-0x7fffedb0> + 3f6: 0000 unimp + 3f8: 0a00 addi s0,sp,272 + 3fa: 0304 addi s1,sp,384 + 3fc: 034a slli t1,t1,0x12 + 3fe: 00d6 slli ra,ra,0x15 + 400: 0000 unimp + 402: 0000da0b 0xda0b + 406: 0300 addi s0,sp,384 + 408: 0e51 addi t3,t3,20 + 40a: 005a c.slli zero,0x16 + 40c: 0000 unimp + 40e: 1704 addi s1,sp,928 + 410: 0009 c.nop 2 + 412: 650c flw fa1,8(a0) + 414: 7078 flw fa4,100(s0) + 416: 0300 addi s0,sp,384 + 418: 0e52 slli t3,t3,0x14 + 41a: 005a c.slli zero,0x16 + 41c: 0000 unimp + 41e: 0804 addi s1,sp,16 + 420: 0001 nop + 422: 0007810b 0x7810b + 426: 0300 addi s0,sp,384 + 428: 005a0e53 fadd.s ft8,fs4,ft5,rne + 42c: 0000 unimp + 42e: 0104 addi s1,sp,128 + 430: 0000 unimp + 432: 0d00 addi s0,sp,656 + 434: 0000027b 0x27b + 438: 0304 addi s1,sp,384 + 43a: 00fc0747 fmsub.s fa4,fs8,fa5,ft0,rne + 43e: 0000 unimp + 440: 660e flw fa2,192(sp) + 442: 746c flw fa1,108(s0) + 444: 0300 addi s0,sp,384 + 446: 0a49 addi s4,s4,18 + 448: 0090 addi a2,sp,64 + 44a: 0000 unimp + 44c: 0002390f 0x2390f + 450: 0300 addi s0,sp,384 + 452: 0555 addi a0,a0,21 + 454: 009c addi a5,sp,64 + 456: 0000 unimp + 458: 1000 addi s0,sp,32 + 45a: 0325 addi t1,t1,9 + 45c: 0000 unimp + 45e: 2301 jal 95e <_start-0x7ffff6a2> + 460: 9001 srli s0,s0,0x20 + 462: 0000 unimp + 464: 1400 addi s0,sp,544 + 466: 2c800013 li zero,712 + 46a: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> + 46e: ac9c fsd fa5,24(s1) + 470: 11000003 lb zero,272(zero) # 110 <_start-0x7ffffef0> + 474: 0061 c.nop 24 + 476: 2301 jal 976 <_start-0x7ffff68a> + 478: 9012 c.add zero,tp + 47a: 0000 unimp + 47c: ce00 sw s0,24(a2) + 47e: 000a c.slli zero,0x2 + 480: 1100 addi s0,sp,160 + 482: 0062 c.slli zero,0x18 + 484: 2301 jal 984 <_start-0x7ffff67c> + 486: 901c 0x901c + 488: 0000 unimp + 48a: 2700 fld fs0,8(a4) + 48c: 1200000b 0x1200000b + 490: 0028 addi a0,sp,8 + 492: 0000 unimp + 494: 2501 jal a94 <_start-0x7ffff56c> + 496: 00002c03 lw s8,0(zero) # 0 <_start-0x80000000> + 49a: 8600 0x8600 + 49c: 1300000b 0x1300000b + 4a0: 000002a7 0x2a7 + 4a4: 2501 jal aa4 <_start-0x7ffff55c> + 4a6: 00002c03 lw s8,0(zero) # 0 <_start-0x80000000> + 4aa: 0000 unimp + 4ac: 4114 lw a3,0(a0) + 4ae: 635f 0100 0326 0x3260100635f + 4b4: 03ac addi a1,sp,456 + 4b6: 0000 unimp + 4b8: 0ba6 slli s7,s7,0x9 + 4ba: 0000 unimp + 4bc: 4114 lw a3,0(a0) + 4be: 735f 0100 0326 0x3260100735f + 4c4: 03ac addi a1,sp,456 + 4c6: 0000 unimp + 4c8: 00000bdb 0xbdb + 4cc: 4114 lw a3,0(a0) + 4ce: 655f 0100 0326 0x3260100655f + 4d4: 03ac addi a1,sp,456 + 4d6: 0000 unimp + 4d8: 00000c03 lb s8,0(zero) # 0 <_start-0x80000000> + 4dc: 4114 lw a3,0(a0) + 4de: 665f 0100 0326 0x3260100665f + 4e4: 000003b3 add t2,zero,zero + 4e8: 0c85 addi s9,s9,1 + 4ea: 0000 unimp + 4ec: 4214 lw a3,0(a2) + 4ee: 635f 0100 0327 0x3270100635f + 4f4: 03ac addi a1,sp,456 + 4f6: 0000 unimp + 4f8: 0cf5 addi s9,s9,29 + 4fa: 0000 unimp + 4fc: 4214 lw a3,0(a2) + 4fe: 735f 0100 0327 0x3270100735f + 504: 03ac addi a1,sp,456 + 506: 0000 unimp + 508: 0d40 addi s0,sp,660 + 50a: 0000 unimp + 50c: 4214 lw a3,0(a2) + 50e: 655f 0100 0327 0x3270100655f + 514: 03ac addi a1,sp,456 + 516: 0000 unimp + 518: 0d78 addi a4,sp,668 + 51a: 0000 unimp + 51c: 4214 lw a3,0(a2) + 51e: 665f 0100 0327 0x3270100665f + 524: 000003b3 add t2,zero,zero + 528: 00000dcb fnmsub.s fs11,ft0,ft0,ft0,rne + 52c: 5214 lw a3,32(a2) + 52e: 635f 0100 0328 0x3280100635f + 534: 03ac addi a1,sp,456 + 536: 0000 unimp + 538: 00000e1b 0xe1b + 53c: 5214 lw a3,32(a2) + 53e: 735f 0100 0328 0x3280100735f + 544: 03ac addi a1,sp,456 + 546: 0000 unimp + 548: 0e5c addi a5,sp,788 + 54a: 0000 unimp + 54c: 5214 lw a3,32(a2) + 54e: 655f 0100 0328 0x3280100655f + 554: 03ac addi a1,sp,456 + 556: 0000 unimp + 558: 0ee1 addi t4,t4,24 + 55a: 0000 unimp + 55c: 5214 lw a3,32(a2) + 55e: 665f 0100 0328 0x3280100665f + 564: 000003b3 add t2,zero,zero + 568: 00000f63 beqz zero,586 <_start-0x7ffffa7a> + 56c: 7214 flw fa3,32(a2) + 56e: 0100 addi s0,sp,128 + 570: 0a29 addi s4,s4,10 + 572: 0090 addi a2,sp,64 + 574: 0000 unimp + 576: 00000fc7 fmsub.s ft11,ft0,ft0,ft0,rne + 57a: 4015 c.li zero,5 + 57c: 0001 nop + 57e: 3300 fld fs0,32(a4) + 580: 0002 c.slli64 zero + 582: 1600 addi s0,sp,800 + 584: 006e c.slli zero,0x1b + 586: 0000 unimp + 588: 2c01 jal 798 <_start-0x7ffff868> + 58a: 0000d603 lhu a2,0(ra) + 58e: 0000 unimp + 590: 6815 lui a6,0x5 + 592: 0001 nop + 594: 4d00 lw s0,24(a0) + 596: 0002 c.slli64 zero + 598: 1200 addi s0,sp,288 + 59a: 0401 addi s0,s0,0 + 59c: 0000 unimp + 59e: 2c01 jal 7ae <_start-0x7ffff852> + 5a0: 0003ac03 lw s8,0(t2) + 5a4: ec00 fsw fs0,24(s0) + 5a6: 0000000f fence unknown,unknown + 5aa: 8015 srli s0,s0,0x5 + 5ac: 0001 nop + 5ae: 6300 flw fs0,0(a4) + 5b0: 0002 c.slli64 zero + 5b2: 1600 addi s0,sp,800 + 5b4: 006e c.slli zero,0x1b + 5b6: 0000 unimp + 5b8: 2d01 jal bc8 <_start-0x7ffff438> + 5ba: 0000d603 lhu a2,0(ra) + 5be: 0000 unimp + 5c0: 9815 andi s0,s0,-27 + 5c2: 0001 nop + 5c4: 7d00 flw fs0,56(a0) + 5c6: 0002 c.slli64 zero + 5c8: 1200 addi s0,sp,288 + 5ca: 0401 addi s0,s0,0 + 5cc: 0000 unimp + 5ce: 2d01 jal bde <_start-0x7ffff422> + 5d0: 0003ac03 lw s8,0(t2) + 5d4: 0100 addi s0,sp,128 + 5d6: 0010 0x10 + 5d8: 0000 unimp + 5da: b015 j fffffdfe <__global_pointer$+0x7fffc196> + 5dc: 0001 nop + 5de: 4d00 lw s0,24(a0) + 5e0: 12000003 lb zero,288(zero) # 120 <_start-0x7ffffee0> + 5e4: 0345 addi t1,t1,17 + 5e6: 0000 unimp + 5e8: 2e01 jal 8f8 <_start-0x7ffff708> + 5ea: 0003b303 0x3b303 + 5ee: 1600 addi s0,sp,800 + 5f0: 0010 0x10 + 5f2: 1200 addi s0,sp,288 + 5f4: 03e5 addi t2,t2,25 + 5f6: 0000 unimp + 5f8: 2e01 jal 908 <_start-0x7ffff6f8> + 5fa: 0003b303 0x3b303 + 5fe: 3400 fld fs0,40(s0) + 600: 0010 0x10 + 602: 1200 addi s0,sp,288 + 604: 000003af 0x3af + 608: 2e01 jal 918 <_start-0x7ffff6e8> + 60a: 0003b303 0x3b303 + 60e: 5e00 lw s0,56(a2) + 610: 0010 0x10 + 612: 1200 addi s0,sp,288 + 614: 0361 addi t1,t1,24 + 616: 0000 unimp + 618: 2e01 jal 928 <_start-0x7ffff6d8> + 61a: 0003b303 0x3b303 + 61e: 8300 0x8300 + 620: 0010 0x10 + 622: 1200 addi s0,sp,288 + 624: 03ca slli t2,t2,0x12 + 626: 0000 unimp + 628: 2e01 jal 938 <_start-0x7ffff6c8> + 62a: 0003b303 0x3b303 + 62e: a600 fsd fs0,8(a2) + 630: 0010 0x10 + 632: 1700 addi s0,sp,928 + 634: 01c8 addi a0,sp,196 + 636: 0000 unimp + 638: 2012 fld ft0,256(sp) + 63a: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> + 63e: 032e slli t1,t1,0xb + 640: 000003b3 add t2,zero,zero + 644: 10c4 addi s1,sp,100 + 646: 0000 unimp + 648: aa12 fsd ft4,272(sp) + 64a: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> + 64e: 032e slli t1,t1,0xb + 650: 000003b3 add t2,zero,zero + 654: 10e6 slli ra,ra,0x39 + 656: 0000 unimp + 658: b612 fsd ft4,296(sp) + 65a: 0002 c.slli64 zero + 65c: 0100 addi s0,sp,128 + 65e: 032e slli t1,t1,0xb + 660: 000003b3 add t2,zero,zero + 664: 110a slli sp,sp,0x22 + 666: 0000 unimp + 668: b112 fsd ft4,160(sp) + 66a: 0002 c.slli64 zero + 66c: 0100 addi s0,sp,128 + 66e: 032e slli t1,t1,0xb + 670: 000003b3 add t2,zero,zero + 674: 1128 addi a0,sp,168 + 676: 0000 unimp + 678: bb12 fsd ft4,432(sp) + 67a: 0002 c.slli64 zero + 67c: 0100 addi s0,sp,128 + 67e: 032e slli t1,t1,0xb + 680: 000003b3 add t2,zero,zero + 684: 1146 slli sp,sp,0x31 + 686: 0000 unimp + 688: ac12 fsd ft4,24(sp) + 68a: 0002 c.slli64 zero + 68c: 0100 addi s0,sp,128 + 68e: 032e slli t1,t1,0xb + 690: 000003b3 add t2,zero,zero + 694: 11a4 addi s1,sp,232 + 696: 0000 unimp + 698: 5f14 lw a3,56(a4) + 69a: 6d5f 0100 032e 0x32e01006d5f + 6a0: 000003b3 add t2,zero,zero + 6a4: 11f8 addi a4,sp,236 + 6a6: 0000 unimp + 6a8: 0000 unimp + 6aa: e815 bnez s0,6de <_start-0x7ffff922> + 6ac: 0001 nop + 6ae: 9500 0x9500 + 6b0: 16000003 lb zero,352(zero) # 160 <_start-0x7ffffea0> + 6b4: 02c0 addi s0,sp,324 + 6b6: 0000 unimp + 6b8: 2f01 jal dc8 <_start-0x7ffff238> + 6ba: 00002c03 lw s8,0(zero) # 0 <_start-0x80000000> + 6be: 1800 addi s0,sp,48 + 6c0: 7c16 flw fs8,100(sp) + 6c2: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> + 6c6: 03ac032f 0x3ac032f + 6ca: 0000 unimp + 6cc: 9316 add t1,t1,t0 + 6ce: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> + 6d2: 03ac032f 0x3ac032f + 6d6: 0000 unimp + 6d8: 2e16 fld ft8,320(sp) + 6da: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> + 6de: 03ac032f 0x3ac032f + 6e2: 0000 unimp + 6e4: 0916 slli s2,s2,0x5 + 6e6: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> + 6ea: 03b3032f 0x3b3032f + 6ee: 0000 unimp + 6f0: 0000 unimp + 6f2: 3819 jal ffffff08 <__global_pointer$+0x7fffc2a0> + 6f4: 0015 c.nop 5 + 6f6: 1c80 addi s0,sp,624 + 6f8: 0000 unimp + 6fa: 1600 addi s0,sp,800 + 6fc: 0000 unimp + 6fe: 0000 unimp + 700: 2f01 jal e10 <_start-0x7ffff1f0> + 702: 0000d603 lhu a2,0(ra) + 706: 0000 unimp + 708: 0200 addi s0,sp,256 + 70a: 0504 addi s1,sp,640 + 70c: 0179 addi sp,sp,30 + 70e: 0000 unimp + 710: 0402 c.slli64 s0 + 712: 0000e407 0xe407 + 716: 0000 unimp + 718: 00000263 beqz zero,71c <_start-0x7ffff8e4> + 71c: 0004 0x4 + 71e: 000002f3 0x2f3 + 722: 0104 addi s1,sp,128 + 724: 0182 c.slli64 gp + 726: 0000 unimp + 728: 430c lw a1,0(a4) + 72a: 0004 0x4 + 72c: f600 fsw fs0,40(a2) + 72e: 0000 unimp + 730: 4000 lw s0,0(s0) + 732: 0016 c.slli zero,0x5 + 734: b480 fsd fs0,40(s1) + 736: 0000 unimp + 738: d000 sw s0,32(s0) + 73a: 0012 c.slli zero,0x4 + 73c: 0200 addi s0,sp,256 + 73e: 0404 addi s1,sp,512 + 740: 000008cb fnmsub.s fa7,ft0,ft0,ft0,rne + 744: 00041c03 lh s8,0(s0) # fffe1000 <__global_pointer$+0x7ffdd398> + 748: 0200 addi s0,sp,256 + 74a: 0d50 addi a2,sp,660 + 74c: 0038 addi a4,sp,8 + 74e: 0000 unimp + 750: 0404 addi s1,sp,512 + 752: 6905 lui s2,0x1 + 754: 746e flw fs0,248(sp) + 756: 0200 addi s0,sp,256 + 758: 0601 addi a2,a2,0 + 75a: 0062 c.slli zero,0x18 + 75c: 0000 unimp + 75e: 0802 c.slli64 a6 + 760: 7405 lui s0,0xfffe1 + 762: 0001 nop + 764: 0500 addi s0,sp,640 + 766: 00c8 addi a0,sp,68 + 768: 0000 unimp + 76a: 16014a03 lbu s4,352(sp) + 76e: 005f 0000 4d06 0x4d060000005f + 774: 0000 unimp + 776: 0200 addi s0,sp,256 + 778: 0801 addi a6,a6,0 + 77a: 0060 addi s0,sp,12 + 77c: 0000 unimp + 77e: 0402 c.slli64 s0 + 780: 0000e907 0xe907 + 784: 0200 addi s0,sp,256 + 786: 0708 addi a0,sp,896 + 788: 00df 0000 0202 0x202000000df + 78e: 00008c07 0x8c07 + 792: 0700 addi s0,sp,896 + 794: 005a c.slli zero,0x16 + 796: 0000 unimp + 798: 0000008b 0x8b + 79c: 6608 flw fa0,8(a2) + 79e: 0000 unimp + 7a0: ff00 fsw fs0,56(a4) + 7a2: 0600 addi s0,sp,768 + 7a4: 0000007b 0x7b + 7a8: d009 beqz s0,6aa <_start-0x7ffff956> + 7aa: 0000 unimp + 7ac: 0500 addi s0,sp,640 + 7ae: 163c addi a5,sp,808 + 7b0: 0000008b 0x8b + 7b4: 00028703 lb a4,0(t0) # 800020c0 + 7b8: 0400 addi s0,sp,512 + 7ba: 0f45 addi t5,t5,17 + 7bc: 0025 c.nop 9 + 7be: 0000 unimp + 7c0: 040a slli s0,s0,0x2 + 7c2: 4a04 lw s1,16(a2) + 7c4: 0000e203 0xe203 + 7c8: 0b00 addi s0,sp,400 + 7ca: 00da slli ra,ra,0x16 + 7cc: 0000 unimp + 7ce: 5104 lw s1,32(a0) + 7d0: 660e flw fa2,192(sp) + 7d2: 0000 unimp + 7d4: 0400 addi s0,sp,512 + 7d6: 0c000917 auipc s2,0xc000 + 7da: 7865 lui a6,0xffff9 + 7dc: 0070 addi a2,sp,12 + 7de: 5204 lw s1,32(a2) + 7e0: 660e flw fa2,192(sp) + 7e2: 0000 unimp + 7e4: 0400 addi s0,sp,512 + 7e6: 0108 addi a0,sp,128 + 7e8: 0b00 addi s0,sp,400 + 7ea: 0781 addi a5,a5,0 + 7ec: 0000 unimp + 7ee: 5304 lw s1,32(a4) + 7f0: 660e flw fa2,192(sp) + 7f2: 0000 unimp + 7f4: 0400 addi s0,sp,512 + 7f6: 0001 nop + 7f8: 0000 unimp + 7fa: 7b0d lui s6,0xfffe3 + 7fc: 0002 c.slli64 zero + 7fe: 0400 addi s0,sp,512 + 800: 4704 lw s1,8(a4) + 802: 00010807 0x10807 + 806: 0e00 addi s0,sp,784 + 808: 6c66 flw fs8,88(sp) + 80a: 0074 addi a3,sp,12 + 80c: 4904 lw s1,16(a0) + 80e: 9c0a add s8,s8,sp + 810: 0000 unimp + 812: 0f00 addi s0,sp,912 + 814: 0239 addi tp,tp,14 + 816: 0000 unimp + 818: 5504 lw s1,40(a0) + 81a: a805 j 84a <_start-0x7ffff7b6> + 81c: 0000 unimp + 81e: 0000 unimp + 820: 3b10 fld fa2,48(a4) + 822: 0004 0x4 + 824: 0100 addi s0,sp,128 + 826: 002c0123 sb sp,2(s8) + 82a: 0000 unimp + 82c: 1640 addi s0,sp,804 + 82e: 8000 0x8000 + 830: 00b4 addi a3,sp,72 + 832: 0000 unimp + 834: 9c01 0x9c01 + 836: 0258 addi a4,sp,260 + 838: 0000 unimp + 83a: 6111 addi sp,sp,256 + 83c: 0100 addi s0,sp,128 + 83e: 009c1123 sh s1,2(s8) + 842: 0000 unimp + 844: 1226 slli tp,tp,0x29 + 846: 0000 unimp + 848: 6211 lui tp,0x4 + 84a: 0100 addi s0,sp,128 + 84c: 009c1b23 sh s1,22(s8) + 850: 0000 unimp + 852: 1249 addi tp,tp,-14 + 854: 0000 unimp + 856: 2812 fld fa6,256(sp) + 858: 0000 unimp + 85a: 0100 addi s0,sp,128 + 85c: 0325 addi t1,t1,9 + 85e: 0038 addi a4,sp,8 + 860: 0000 unimp + 862: 126c addi a1,sp,300 + 864: 0000 unimp + 866: 0002a713 slti a4,t0,0 + 86a: 0100 addi s0,sp,128 + 86c: 0325 addi t1,t1,9 + 86e: 0038 addi a4,sp,8 + 870: 0000 unimp + 872: 1400 addi s0,sp,544 + 874: 5f41 li t5,-16 + 876: 26010063 beqz sp,ad6 <_start-0x7ffff52a> + 87a: 00025803 lhu a6,0(tp) # 4000 <_start-0x7fffc000> + 87e: 1500 addi s0,sp,672 + 880: 5f41 li t5,-16 + 882: 26010073 0x26010073 + 886: 00025803 lhu a6,0(tp) # 0 <_start-0x80000000> + 88a: 8c00 0x8c00 + 88c: 0012 c.slli zero,0x4 + 88e: 1600 addi s0,sp,800 + 890: 5f41 li t5,-16 + 892: 0065 c.nop 25 + 894: 2601 jal b94 <_start-0x7ffff46c> + 896: 00025803 lhu a6,0(tp) # 0 <_start-0x80000000> + 89a: 0600 addi s0,sp,768 + 89c: 007d c.nop 31 + 89e: ff08 fsw fa0,56(a4) + 8a0: 9f1a add t5,t5,t1 + 8a2: 4116 lw sp,68(sp) + 8a4: 665f 0100 0326 0x3260100665f + 8aa: 025f 0000 5c01 0x5c010000025f + 8b0: 4214 lw a3,0(a2) + 8b2: 635f 0100 0327 0x3270100635f + 8b8: 0258 addi a4,sp,260 + 8ba: 0000 unimp + 8bc: 4216 lw tp,68(sp) + 8be: 735f 0100 0327 0x3270100735f + 8c4: 0258 addi a4,sp,260 + 8c6: 0000 unimp + 8c8: 5b01 li s6,-32 + 8ca: 4216 lw tp,68(sp) + 8cc: 655f 0100 0327 0x3270100655f + 8d2: 0258 addi a4,sp,260 + 8d4: 0000 unimp + 8d6: 7e06 flw ft8,96(sp) + 8d8: 0800 addi s0,sp,16 + 8da: 1aff 0x1aff + 8dc: 169f 5f42 0066 0x665f42169f + 8e2: 2701 jal fe2 <_start-0x7ffff01e> + 8e4: 00025f03 lhu t5,0(tp) # 0 <_start-0x80000000> + 8e8: 0100 addi s0,sp,128 + 8ea: 155f 0072 2801 0x28010072155f + 8f0: 00002c0b 0x2c0b + 8f4: e100 fsw fs0,0(a0) + 8f6: 0012 c.slli zero,0x4 + 8f8: 1700 addi s0,sp,928 + 8fa: 0200 addi s0,sp,256 + 8fc: 0000 unimp + 8fe: 000001f7 0x1f7 + 902: 6e18 flw fa4,24(a2) + 904: 0000 unimp + 906: 0100 addi s0,sp,128 + 908: 00e2032b 0xe2032b + 90c: 0000 unimp + 90e: 1700 addi s0,sp,928 + 910: 0220 addi s0,sp,264 + 912: 0000 unimp + 914: 020d addi tp,tp,3 + 916: 0000 unimp + 918: 6e18 flw fa4,24(a2) + 91a: 0000 unimp + 91c: 0100 addi s0,sp,128 + 91e: 032c addi a1,sp,392 + 920: 00e2 slli ra,ra,0x18 + 922: 0000 unimp + 924: 1900 addi s0,sp,176 + 926: 021f 0000 2a18 0x2a180000021f + 92c: 0004 0x4 + 92e: 0100 addi s0,sp,128 + 930: 032d addi t1,t1,11 + 932: 0038 addi a4,sp,8 + 934: 0000 unimp + 936: 1900 addi s0,sp,176 + 938: 0231 addi tp,tp,12 + 93a: 0000 unimp + 93c: 2a18 fld fa4,16(a2) + 93e: 0004 0x4 + 940: 0100 addi s0,sp,128 + 942: 032d addi t1,t1,11 + 944: 0038 addi a4,sp,8 + 946: 0000 unimp + 948: 1a00 addi s0,sp,304 + 94a: 0238 addi a4,sp,264 + 94c: 0000 unimp + 94e: 7012 flw ft0,36(sp) + 950: 0004 0x4 + 952: 0100 addi s0,sp,128 + 954: 032d addi t1,t1,11 + 956: 0038 addi a4,sp,8 + 958: 0000 unimp + 95a: 12f5 addi t0,t0,-3 + 95c: 0000 unimp + 95e: 8212 mv tp,tp + 960: 0004 0x4 + 962: 0100 addi s0,sp,128 + 964: 032d addi t1,t1,11 + 966: 0038 addi a4,sp,8 + 968: 0000 unimp + 96a: 0000133f 04020000 0x40200000000133f + 972: 7905 lui s2,0xfffe1 + 974: 0001 nop + 976: 0200 addi s0,sp,256 + 978: 0704 addi s1,sp,896 + 97a: 00e4 addi s1,sp,76 + 97c: 0000 unimp + 97e: a800 fsd fs0,16(s0) + 980: 04000003 lb zero,64(zero) # 40 <_start-0x7fffffc0> + 984: 7b00 flw fs0,48(a4) + 986: 0004 0x4 + 988: 0400 addi s0,sp,512 + 98a: 8201 c.srli64 a2 + 98c: 0001 nop + 98e: 0c00 addi s0,sp,528 + 990: 04dd addi s1,s1,23 + 992: 0000 unimp + 994: 00f6 slli ra,ra,0x1d + 996: 0000 unimp + 998: 16f4 addi a3,sp,876 + 99a: 8000 0x8000 + 99c: 02f8 addi a4,sp,332 + 99e: 0000 unimp + 9a0: 000015ef jal a1,19a0 <_start-0x7fffe660> + 9a4: 0402 c.slli64 s0 + 9a6: cb04 sw s1,16(a4) + 9a8: 0008 0x8 + 9aa: 0300 addi s0,sp,384 + 9ac: 0504 addi s1,sp,640 + 9ae: 6e69 lui t3,0x1a + 9b0: 0074 addi a3,sp,12 + 9b2: 0102 c.slli64 sp + 9b4: 6206 flw ft4,64(sp) + 9b6: 0000 unimp + 9b8: 0200 addi s0,sp,256 + 9ba: 0508 addi a0,sp,640 + 9bc: 0174 addi a3,sp,140 + 9be: 0000 unimp + 9c0: c804 sw s1,16(s0) + 9c2: 0000 unimp + 9c4: 0200 addi s0,sp,256 + 9c6: 014a slli sp,sp,0x12 + 9c8: 5316 lw t1,100(sp) + 9ca: 0000 unimp + 9cc: 0500 addi s0,sp,640 + 9ce: 0041 c.nop 16 + 9d0: 0000 unimp + 9d2: 0102 c.slli64 sp + 9d4: 6008 flw fa0,0(s0) + 9d6: 0000 unimp + 9d8: 0200 addi s0,sp,256 + 9da: 0704 addi s1,sp,896 + 9dc: 00e9 addi ra,ra,26 + 9de: 0000 unimp + 9e0: 0802 c.slli64 a6 + 9e2: 0000df07 0xdf07 + 9e6: 0400 addi s0,sp,512 + 9e8: 04d0 addi a2,sp,580 + 9ea: 0000 unimp + 9ec: 4e02 lw t3,0(sp) + 9ee: 1601 addi a2,a2,-32 + 9f0: 0075 c.nop 29 + 9f2: 0000 unimp + 9f4: 0202 c.slli64 tp + 9f6: 00008c07 0x8c07 + 9fa: 0600 addi s0,sp,768 + 9fc: 004e c.slli zero,0x13 + 9fe: 0000 unimp + a00: 008c addi a1,sp,64 + a02: 0000 unimp + a04: 00005a07 0x5a07 + a08: ff00 fsw fs0,56(a4) + a0a: 0500 addi s0,sp,640 + a0c: 007c addi a5,sp,12 + a0e: 0000 unimp + a10: d008 sw a0,32(s0) + a12: 0000 unimp + a14: 0400 addi s0,sp,512 + a16: 163c addi a5,sp,808 + a18: 008c addi a1,sp,64 + a1a: 0000 unimp + a1c: 8709 srai a4,a4,0x2 + a1e: 0002 c.slli64 zero + a20: 0300 addi s0,sp,384 + a22: 0f45 addi t5,t5,17 + a24: 0025 c.nop 9 + a26: 0000 unimp + a28: 040a slli s0,s0,0x2 + a2a: e3034a03 lbu s4,-464(t1) + a2e: 0000 unimp + a30: 0b00 addi s0,sp,400 + a32: 00da slli ra,ra,0x16 + a34: 0000 unimp + a36: 5a0e5103 lhu sp,1440(t3) # 1a5a0 <_start-0x7ffe5a60> + a3a: 0000 unimp + a3c: 0400 addi s0,sp,512 + a3e: 0c000917 auipc s2,0xc000 + a42: 7865 lui a6,0xffff9 + a44: 0070 addi a2,sp,12 + a46: 5a0e5203 lhu tp,1440(t3) + a4a: 0000 unimp + a4c: 0400 addi s0,sp,512 + a4e: 0108 addi a0,sp,128 + a50: 0b00 addi s0,sp,400 + a52: 0781 addi a5,a5,0 + a54: 0000 unimp + a56: 5a0e5303 lhu t1,1440(t3) + a5a: 0000 unimp + a5c: 0400 addi s0,sp,512 + a5e: 0001 nop + a60: 0000 unimp + a62: 7b0d lui s6,0xfffe3 + a64: 0002 c.slli64 zero + a66: 0400 addi s0,sp,512 + a68: 09074703 lbu a4,144(a4) + a6c: 0001 nop + a6e: 0e00 addi s0,sp,784 + a70: 6c66 flw fs8,88(sp) + a72: 0074 addi a3,sp,12 + a74: 9d0a4903 lbu s2,-1584(s4) + a78: 0000 unimp + a7a: 0f00 addi s0,sp,912 + a7c: 0239 addi tp,tp,14 + a7e: 0000 unimp + a80: a9055503 lhu a0,-1392(a0) + a84: 0000 unimp + a86: 0000 unimp + a88: 2410 fld fa2,8(s0) + a8a: 0005 c.nop 1 + a8c: 0100 addi s0,sp,128 + a8e: 009d0123 sb s1,2(s10) + a92: 0000 unimp + a94: 16f4 addi a3,sp,876 + a96: 8000 0x8000 + a98: 02f8 addi a4,sp,332 + a9a: 0000 unimp + a9c: 9c01 0x9c01 + a9e: 039d addi t2,t2,7 + aa0: 0000 unimp + aa2: 6111 addi sp,sp,256 + aa4: 0100 addi s0,sp,128 + aa6: 009d1223 sh s1,4(s10) + aaa: 0000 unimp + aac: 0000136b 0x136b + ab0: 6211 lui tp,0x4 + ab2: 0100 addi s0,sp,128 + ab4: 009d1c23 sh s1,24(s10) + ab8: 0000 unimp + aba: 13c4 addi s1,sp,484 + abc: 0000 unimp + abe: 2812 fld fa6,256(sp) + ac0: 0000 unimp + ac2: 0100 addi s0,sp,128 + ac4: 0325 addi t1,t1,9 + ac6: 002c addi a1,sp,8 + ac8: 0000 unimp + aca: 00001423 sh zero,8(zero) # 8 <_start-0x7ffffff8> + ace: 0002a713 slti a4,t0,0 + ad2: 0100 addi s0,sp,128 + ad4: 0325 addi t1,t1,9 + ad6: 002c addi a1,sp,8 + ad8: 0000 unimp + ada: 1400 addi s0,sp,544 + adc: 5f41 li t5,-16 + ade: 26010063 beqz sp,d3e <_start-0x7ffff2c2> + ae2: 00039d03 lh s10,0(t2) + ae6: 4300 lw s0,0(a4) + ae8: 0014 0x14 + aea: 1400 addi s0,sp,544 + aec: 5f41 li t5,-16 + aee: 26010073 0x26010073 + af2: 00039d03 lh s10,0(t2) + af6: 6d00 flw fs0,24(a0) + af8: 0014 0x14 + afa: 1400 addi s0,sp,544 + afc: 5f41 li t5,-16 + afe: 0065 c.nop 25 + b00: 2601 jal e00 <_start-0x7ffff200> + b02: 00039d03 lh s10,0(t2) + b06: 8500 0x8500 + b08: 0014 0x14 + b0a: 1400 addi s0,sp,544 + b0c: 5f41 li t5,-16 + b0e: 0066 c.slli zero,0x19 + b10: 2601 jal e10 <_start-0x7ffff1f0> + b12: 0003a403 lw s0,0(t2) + b16: 0700 addi s0,sp,896 + b18: 0015 c.nop 5 + b1a: 1400 addi s0,sp,544 + b1c: 5f42 lw t5,48(sp) + b1e: 27010063 beq sp,a6,d7e <_start-0x7ffff282> + b22: 00039d03 lh s10,0(t2) + b26: 6c00 flw fs0,24(s0) + b28: 0015 c.nop 5 + b2a: 1400 addi s0,sp,544 + b2c: 5f42 lw t5,48(sp) + b2e: 27010073 0x27010073 + b32: 00039d03 lh s10,0(t2) + b36: ac00 fsd fs0,24(s0) + b38: 0015 c.nop 5 + b3a: 1400 addi s0,sp,544 + b3c: 5f42 lw t5,48(sp) + b3e: 0065 c.nop 25 + b40: 2701 jal 1240 <_start-0x7fffedc0> + b42: 00039d03 lh s10,0(t2) + b46: d400 sw s0,40(s0) + b48: 0015 c.nop 5 + b4a: 1400 addi s0,sp,544 + b4c: 5f42 lw t5,48(sp) + b4e: 0066 c.slli zero,0x19 + b50: 2701 jal 1250 <_start-0x7fffedb0> + b52: 0003a403 lw s0,0(t2) + b56: 2700 fld fs0,8(a4) + b58: 0016 c.slli zero,0x5 + b5a: 1400 addi s0,sp,544 + b5c: 5f52 lw t5,52(sp) + b5e: 28010063 beqz sp,dde <_start-0x7ffff222> + b62: 00039d03 lh s10,0(t2) + b66: 7700 flw fs0,40(a4) + b68: 0016 c.slli zero,0x5 + b6a: 1400 addi s0,sp,544 + b6c: 5f52 lw t5,52(sp) + b6e: 28010073 0x28010073 + b72: 00039d03 lh s10,0(t2) + b76: a200 fsd fs0,0(a2) + b78: 0016 c.slli zero,0x5 + b7a: 1400 addi s0,sp,544 + b7c: 5f52 lw t5,52(sp) + b7e: 0065 c.nop 25 + b80: 2801 jal b90 <_start-0x7ffff470> + b82: 00039d03 lh s10,0(t2) + b86: f600 fsw fs0,40(a2) + b88: 0016 c.slli zero,0x5 + b8a: 1400 addi s0,sp,544 + b8c: 5f52 lw t5,52(sp) + b8e: 0066 c.slli zero,0x19 + b90: 2801 jal ba0 <_start-0x7ffff460> + b92: 0003a403 lw s0,0(t2) + b96: 9000 0x9000 + b98: 14000017 auipc zero,0x14000 + b9c: 0072 c.slli zero,0x1c + b9e: 2901 jal fae <_start-0x7ffff052> + ba0: 9d0a add s10,s10,sp + ba2: 0000 unimp + ba4: f400 fsw fs0,40(s0) + ba6: 15000017 auipc zero,0x15000 + baa: 0260 addi s0,sp,268 + bac: 0000 unimp + bae: 0240 addi s0,sp,260 + bb0: 0000 unimp + bb2: 6e16 flw ft8,68(sp) + bb4: 0000 unimp + bb6: 0100 addi s0,sp,128 + bb8: 032c addi a1,sp,392 + bba: 000000e3 beqz zero,13ba <_start-0x7fffec46> + bbe: 1500 addi s0,sp,672 + bc0: 0288 addi a0,sp,320 + bc2: 0000 unimp + bc4: 025a slli tp,tp,0x16 + bc6: 0000 unimp + bc8: 0112 slli sp,sp,0x4 + bca: 0004 0x4 + bcc: 0100 addi s0,sp,128 + bce: 032c addi a1,sp,392 + bd0: 039d addi t2,t2,7 + bd2: 0000 unimp + bd4: 1819 addi a6,a6,-26 + bd6: 0000 unimp + bd8: 1500 addi s0,sp,672 + bda: 02a0 addi s0,sp,328 + bdc: 0000 unimp + bde: 0270 addi a2,sp,268 + be0: 0000 unimp + be2: 6e16 flw ft8,68(sp) + be4: 0000 unimp + be6: 0100 addi s0,sp,128 + be8: 032d addi t1,t1,11 + bea: 000000e3 beqz zero,13ea <_start-0x7fffec16> + bee: 1500 addi s0,sp,672 + bf0: 02b8 addi a4,sp,328 + bf2: 0000 unimp + bf4: 028a slli t0,t0,0x2 + bf6: 0000 unimp + bf8: 0112 slli sp,sp,0x4 + bfa: 0004 0x4 + bfc: 0100 addi s0,sp,128 + bfe: 032d addi t1,t1,11 + c00: 039d addi t2,t2,7 + c02: 0000 unimp + c04: 182e slli a6,a6,0x2b + c06: 0000 unimp + c08: 1700 addi s0,sp,928 + c0a: 1838 addi a4,sp,56 + c0c: 8000 0x8000 + c0e: 006c addi a1,sp,12 + c10: 0000 unimp + c12: 033e slli t1,t1,0xf + c14: 0000 unimp + c16: 9412 add s0,s0,tp + c18: 0004 0x4 + c1a: 0100 addi s0,sp,128 + c1c: 032e slli t1,t1,0xb + c1e: 03a4 addi s1,sp,456 + c20: 0000 unimp + c22: 00001843 fmadd.s fa6,ft0,ft0,ft0,rtz + c26: ad12 fsd ft4,152(sp) + c28: 0004 0x4 + c2a: 0100 addi s0,sp,128 + c2c: 032e slli t1,t1,0xb + c2e: 03a4 addi s1,sp,456 + c30: 0000 unimp + c32: 186c addi a1,sp,60 + c34: 0000 unimp + c36: d018 sw a4,32(s0) + c38: 0002 c.slli64 zero + c3a: 1200 addi s0,sp,288 + c3c: 04d8 addi a4,sp,580 + c3e: 0000 unimp + c40: 2e01 jal f50 <_start-0x7ffff0b0> + c42: 0003a403 lw s0,0(t2) + c46: 9100 0x9100 + c48: 0018 0x18 + c4a: 1200 addi s0,sp,288 + c4c: 0000050b 0x50b + c50: 2e01 jal f60 <_start-0x7ffff0a0> + c52: 0003a403 lw s0,0(t2) + c56: a400 fsd fs0,8(s0) + c58: 0018 0x18 + c5a: 1200 addi s0,sp,288 + c5c: 0510 addi a2,sp,640 + c5e: 0000 unimp + c60: 2e01 jal f70 <_start-0x7ffff090> + c62: 0003a403 lw s0,0(t2) + c66: d200 sw s0,32(a2) + c68: 0018 0x18 + c6a: 1200 addi s0,sp,288 + c6c: 0515 addi a0,a0,5 + c6e: 0000 unimp + c70: 2e01 jal f80 <_start-0x7ffff080> + c72: 0003a403 lw s0,0(t2) + c76: e500 fsw fs0,8(a0) + c78: 0018 0x18 + c7a: 1200 addi s0,sp,288 + c7c: 000004cb fnmsub.s fs1,ft0,ft0,ft0,rne + c80: 2e01 jal f90 <_start-0x7ffff070> + c82: 00006803 0x6803 + c86: 0300 addi s0,sp,384 + c88: 0019 c.nop 6 + c8a: 1200 addi s0,sp,288 + c8c: 051f 0000 2e01 0x2e010000051f + c92: 00006803 0x6803 + c96: 1600 addi s0,sp,800 + c98: 0019 c.nop 6 + c9a: 1200 addi s0,sp,288 + c9c: 04c6 slli s1,s1,0x11 + c9e: 0000 unimp + ca0: 2e01 jal fb0 <_start-0x7ffff050> + ca2: 00006803 0x6803 + ca6: 2900 fld fs0,16(a0) + ca8: 0019 c.nop 6 + caa: 1200 addi s0,sp,288 + cac: 051a slli a0,a0,0x6 + cae: 0000 unimp + cb0: 2e01 jal fc0 <_start-0x7ffff040> + cb2: 00006803 0x6803 + cb6: 3c00 fld fs0,56(s0) + cb8: 0019 c.nop 6 + cba: 0000 unimp + cbc: 1500 addi s0,sp,672 + cbe: 02f0 addi a2,sp,332 + cc0: 0000 unimp + cc2: 0386 slli t2,t2,0x1 + cc4: 0000 unimp + cc6: c016 sw t0,0(sp) + cc8: 0002 c.slli64 zero + cca: 0100 addi s0,sp,128 + ccc: 002c032f 0x2c032f + cd0: 0000 unimp + cd2: 1619 addi a2,a2,-26 + cd4: 037c addi a5,sp,396 + cd6: 0000 unimp + cd8: 2f01 jal 13e8 <_start-0x7fffec18> + cda: 00039d03 lh s10,0(t2) + cde: 1600 addi s0,sp,800 + ce0: 00000393 li t2,0 + ce4: 2f01 jal 13f4 <_start-0x7fffec0c> + ce6: 00039d03 lh s10,0(t2) + cea: 1600 addi s0,sp,800 + cec: 032e slli t1,t1,0xb + cee: 0000 unimp + cf0: 2f01 jal 1400 <_start-0x7fffec00> + cf2: 00039d03 lh s10,0(t2) + cf6: 1600 addi s0,sp,800 + cf8: 0309 addi t1,t1,2 + cfa: 0000 unimp + cfc: 2f01 jal 140c <_start-0x7fffebf4> + cfe: 0003a403 lw s0,0(t2) + d02: 0000 unimp + d04: 1a00 addi s0,sp,304 + d06: 19a8 addi a0,sp,248 + d08: 8000 0x8000 + d0a: 001c 0x1c + d0c: 0000 unimp + d0e: 0016 c.slli zero,0x5 + d10: 0000 unimp + d12: 0100 addi s0,sp,128 + d14: 00e3032f 0xe3032f + d18: 0000 unimp + d1a: 0000 unimp + d1c: 0402 c.slli64 s0 + d1e: 7905 lui s2,0xfffe1 + d20: 0001 nop + d22: 0200 addi s0,sp,256 + d24: 0704 addi s1,sp,896 + d26: 00e4 addi s1,sp,76 + d28: 0000 unimp + d2a: 5900 lw s0,48(a0) + d2c: 04000003 lb zero,64(zero) # 40 <_start-0x7fffffc0> + d30: f500 fsw fs0,40(a0) + d32: 0005 c.nop 1 + d34: 0400 addi s0,sp,512 + d36: 8201 c.srli64 a2 + d38: 0001 nop + d3a: 0c00 addi s0,sp,528 + d3c: 052d addi a0,a0,11 + d3e: 0000 unimp + d40: 00f6 slli ra,ra,0x1d + d42: 0000 unimp + d44: 19ec addi a1,sp,252 + d46: 8000 0x8000 + d48: 044c addi a1,sp,516 + d4a: 0000 unimp + d4c: 1d75 addi s10,s10,-3 + d4e: 0000 unimp + d50: 0402 c.slli64 s0 + d52: cb04 sw s1,16(a4) + d54: 0008 0x8 + d56: 0300 addi s0,sp,384 + d58: 0504 addi s1,sp,640 + d5a: 6e69 lui t3,0x1a + d5c: 0074 addi a3,sp,12 + d5e: 0102 c.slli64 sp + d60: 6206 flw ft4,64(sp) + d62: 0000 unimp + d64: 0200 addi s0,sp,256 + d66: 0508 addi a0,sp,640 + d68: 0174 addi a3,sp,140 + d6a: 0000 unimp + d6c: c804 sw s1,16(s0) + d6e: 0000 unimp + d70: 0200 addi s0,sp,256 + d72: 014a slli sp,sp,0x12 + d74: 5316 lw t1,100(sp) + d76: 0000 unimp + d78: 0500 addi s0,sp,640 + d7a: 0041 c.nop 16 + d7c: 0000 unimp + d7e: 0102 c.slli64 sp + d80: 6008 flw fa0,0(s0) + d82: 0000 unimp + d84: 0200 addi s0,sp,256 + d86: 0704 addi s1,sp,896 + d88: 00e9 addi ra,ra,26 + d8a: 0000 unimp + d8c: 0802 c.slli64 a6 + d8e: 0000df07 0xdf07 + d92: 0200 addi s0,sp,256 + d94: 0702 c.slli64 a4 + d96: 008c addi a1,sp,64 + d98: 0000 unimp + d9a: 4e06 lw t3,64(sp) + d9c: 0000 unimp + d9e: 7f00 flw fs0,56(a4) + da0: 0000 unimp + da2: 0700 addi s0,sp,896 + da4: 005a c.slli zero,0x16 + da6: 0000 unimp + da8: 00ff 0xff + daa: 6f05 lui t5,0x1 + dac: 0000 unimp + dae: 0800 addi s0,sp,16 + db0: 00d0 addi a2,sp,68 + db2: 0000 unimp + db4: 3c04 fld fs1,56(s0) + db6: 7f16 flw ft10,100(sp) + db8: 0000 unimp + dba: 0900 addi s0,sp,144 + dbc: 00000287 0x287 + dc0: 250f4503 lbu a0,592(t5) # 1250 <_start-0x7fffedb0> + dc4: 0000 unimp + dc6: 0a00 addi s0,sp,272 + dc8: 0304 addi s1,sp,384 + dca: 034a slli t1,t1,0x12 + dcc: 00d6 slli ra,ra,0x15 + dce: 0000 unimp + dd0: 0000da0b 0xda0b + dd4: 0300 addi s0,sp,384 + dd6: 0e51 addi t3,t3,20 + dd8: 005a c.slli zero,0x16 + dda: 0000 unimp + ddc: 1704 addi s1,sp,928 + dde: 0009 c.nop 2 + de0: 650c flw fa1,8(a0) + de2: 7078 flw fa4,100(s0) + de4: 0300 addi s0,sp,384 + de6: 0e52 slli t3,t3,0x14 + de8: 005a c.slli zero,0x16 + dea: 0000 unimp + dec: 0804 addi s1,sp,16 + dee: 0001 nop + df0: 0007810b 0x7810b + df4: 0300 addi s0,sp,384 + df6: 005a0e53 fadd.s ft8,fs4,ft5,rne + dfa: 0000 unimp + dfc: 0104 addi s1,sp,128 + dfe: 0000 unimp + e00: 0d00 addi s0,sp,656 + e02: 0000027b 0x27b + e06: 0304 addi s1,sp,384 + e08: 00fc0747 fmsub.s fa4,fs8,fa5,ft0,rne + e0c: 0000 unimp + e0e: 660e flw fa2,192(sp) + e10: 746c flw fa1,108(s0) + e12: 0300 addi s0,sp,384 + e14: 0a49 addi s4,s4,18 + e16: 0090 addi a2,sp,64 + e18: 0000 unimp + e1a: 0002390f 0x2390f + e1e: 0300 addi s0,sp,384 + e20: 0555 addi a0,a0,21 + e22: 009c addi a5,sp,64 + e24: 0000 unimp + e26: 1000 addi s0,sp,32 + e28: 0000055b 0x55b + e2c: 2301 jal 132c <_start-0x7fffecd4> + e2e: 9001 srli s0,s0,0x20 + e30: 0000 unimp + e32: ec00 fsw fs0,24(s0) + e34: 0019 c.nop 6 + e36: 4c80 lw s0,24(s1) + e38: 0004 0x4 + e3a: 0100 addi s0,sp,128 + e3c: 4e9c lw a5,24(a3) + e3e: 11000003 lb zero,272(zero) # 110 <_start-0x7ffffef0> + e42: 0061 c.nop 24 + e44: 2301 jal 1344 <_start-0x7fffecbc> + e46: 9012 c.add zero,tp + e48: 0000 unimp + e4a: 4f00 lw s0,24(a4) + e4c: 0019 c.nop 6 + e4e: 1100 addi s0,sp,160 + e50: 0062 c.slli zero,0x18 + e52: 2301 jal 1352 <_start-0x7fffecae> + e54: 901c 0x901c + e56: 0000 unimp + e58: 7200 flw fs0,32(a2) + e5a: 0019 c.nop 6 + e5c: 1200 addi s0,sp,288 + e5e: 0028 addi a0,sp,8 + e60: 0000 unimp + e62: 2501 jal 1462 <_start-0x7fffeb9e> + e64: 00002c03 lw s8,0(zero) # 0 <_start-0x80000000> + e68: 9500 0x9500 + e6a: 0019 c.nop 6 + e6c: 1300 addi s0,sp,416 + e6e: 000002a7 0x2a7 + e72: 2501 jal 1472 <_start-0x7fffeb8e> + e74: 00002c03 lw s8,0(zero) # 0 <_start-0x80000000> + e78: 0000 unimp + e7a: 4114 lw a3,0(a0) + e7c: 635f 0100 0326 0x3260100635f + e82: 034e slli t1,t1,0x13 + e84: 0000 unimp + e86: 4115 li sp,5 + e88: 735f 0100 0326 0x3260100735f + e8e: 034e slli t1,t1,0x13 + e90: 0000 unimp + e92: 19f1 addi s3,s3,-4 + e94: 0000 unimp + e96: 4115 li sp,5 + e98: 655f 0100 0326 0x3260100655f + e9e: 034e slli t1,t1,0x13 + ea0: 0000 unimp + ea2: 1a7d addi s4,s4,-1 + ea4: 0000 unimp + ea6: 4115 li sp,5 + ea8: 665f 0100 0326 0x3260100665f + eae: 0355 addi t1,t1,21 + eb0: 0000 unimp + eb2: 1b8d addi s7,s7,-29 + eb4: 0000 unimp + eb6: 4214 lw a3,0(a2) + eb8: 635f 0100 0327 0x3270100635f + ebe: 034e slli t1,t1,0x13 + ec0: 0000 unimp + ec2: 4215 li tp,5 + ec4: 735f 0100 0327 0x3270100735f + eca: 034e slli t1,t1,0x13 + ecc: 0000 unimp + ece: 1c9d addi s9,s9,-25 + ed0: 0000 unimp + ed2: 4215 li tp,5 + ed4: 655f 0100 0327 0x3270100655f + eda: 034e slli t1,t1,0x13 + edc: 0000 unimp + ede: 1d44 addi s1,sp,692 + ee0: 0000 unimp + ee2: 4215 li tp,5 + ee4: 665f 0100 0327 0x3270100665f + eea: 0355 addi t1,t1,21 + eec: 0000 unimp + eee: 1e49 addi t3,t3,-14 + ef0: 0000 unimp + ef2: 5214 lw a3,32(a2) + ef4: 635f 0100 0328 0x3280100635f + efa: 034e slli t1,t1,0x13 + efc: 0000 unimp + efe: 5215 li tp,-27 + f00: 735f 0100 0328 0x3280100735f + f06: 034e slli t1,t1,0x13 + f08: 0000 unimp + f0a: 1eca slli t4,t4,0x32 + f0c: 0000 unimp + f0e: 5215 li tp,-27 + f10: 655f 0100 0328 0x3280100655f + f16: 034e slli t1,t1,0x13 + f18: 0000 unimp + f1a: 1f6c addi a1,sp,956 + f1c: 0000 unimp + f1e: 5215 li tp,-27 + f20: 665f 0100 0328 0x3280100665f + f26: 0355 addi t1,t1,21 + f28: 0000 unimp + f2a: 20e1 jal ff2 <_start-0x7ffff00e> + f2c: 0000 unimp + f2e: 7215 lui tp,0xfffe5 + f30: 0100 addi s0,sp,128 + f32: 0a29 addi s4,s4,10 + f34: 0090 addi a2,sp,64 + f36: 0000 unimp + f38: 2279 jal 10c6 <_start-0x7fffef3a> + f3a: 0000 unimp + f3c: 0816 slli a6,a6,0x5 + f3e: 27000003 lb zero,624(zero) # 270 <_start-0x7ffffd90> + f42: 0002 c.slli64 zero + f44: 1700 addi s0,sp,928 + f46: 006e c.slli zero,0x1b + f48: 0000 unimp + f4a: 2c01 jal 115a <_start-0x7fffeea6> + f4c: 0000d603 lhu a2,0(ra) + f50: 0000 unimp + f52: 5016 0x5016 + f54: 3d000003 lb zero,976(zero) # 3d0 <_start-0x7ffffc30> + f58: 0002 c.slli64 zero + f5a: 1700 addi s0,sp,928 + f5c: 006e c.slli zero,0x1b + f5e: 0000 unimp + f60: 2d01 jal 1570 <_start-0x7fffea90> + f62: 0000d603 lhu a2,0(ra) + f66: 0000 unimp + f68: 6816 flw fa6,68(sp) + f6a: 87000003 lb zero,-1936(zero) # fffff870 <__global_pointer$+0x7fffbc08> + f6e: 0002 c.slli64 zero + f70: 1800 addi s0,sp,48 + f72: 026c addi a1,sp,268 + f74: 0000 unimp + f76: 2e01 jal 1286 <_start-0x7fffed7a> + f78: 001abc03 0x1abc03 + f7c: 1880 addi s0,sp,112 + f7e: 0271 addi tp,tp,28 + f80: 0000 unimp + f82: 2e01 jal 1292 <_start-0x7fffed6e> + f84: 001b2803 lw a6,1(s6) # fffe3001 <__global_pointer$+0x7ffdf399> + f88: 1880 addi s0,sp,112 + f8a: 0276 slli tp,tp,0x1d + f8c: 0000 unimp + f8e: 2e01 jal 129e <_start-0x7fffed62> + f90: 001a6c03 0x1a6c03 + f94: 1880 addi s0,sp,112 + f96: 00000057 0x57 + f9a: 2e01 jal 12aa <_start-0x7fffed56> + f9c: 001b8803 lb a6,1(s7) + fa0: 1280 addi s0,sp,352 + fa2: 0222 slli tp,tp,0x8 + fa4: 0000 unimp + fa6: 2e01 jal 12b6 <_start-0x7fffed4a> + fa8: 00002c03 lw s8,0(zero) # 0 <_start-0x80000000> + fac: 9e00 0x9e00 + fae: 0022 c.slli zero,0x8 + fb0: 0000 unimp + fb2: a816 fsd ft5,16(sp) + fb4: f3000003 lb zero,-208(zero) # ffffff30 <__global_pointer$+0x7fffc2c8> + fb8: 0002 c.slli64 zero + fba: 1800 addi s0,sp,48 + fbc: 009f 0000 2e01 0x2e010000009f + fc2: 001c0c03 lb s8,1(s8) + fc6: 1880 addi s0,sp,112 + fc8: 00a4 addi s1,sp,72 + fca: 0000 unimp + fcc: 2e01 jal 12dc <_start-0x7fffed24> + fce: 001c9c03 lh s8,1(s9) + fd2: 1880 addi s0,sp,112 + fd4: 00a9 addi ra,ra,10 + fd6: 0000 unimp + fd8: 2e01 jal 12e8 <_start-0x7fffed18> + fda: 001be403 0x1be403 + fde: 1880 addi s0,sp,112 + fe0: 000000c3 fmadd.s ft1,ft0,ft0,ft0,rne + fe4: 2e01 jal 12f4 <_start-0x7fffed0c> + fe6: 001d4003 lbu zero,1(s10) + fea: 1880 addi s0,sp,112 + fec: 0155 addi sp,sp,21 + fee: 0000 unimp + ff0: 2e01 jal 1300 <_start-0x7fffed00> + ff2: 001b8803 lb a6,1(s7) + ff6: 1280 addi s0,sp,352 + ff8: 0222 slli tp,tp,0x8 + ffa: 0000 unimp + ffc: 2e01 jal 130c <_start-0x7fffecf4> + ffe: 00002c03 lw s8,0(zero) # 0 <_start-0x80000000> + 1002: 8d00 0x8d00 + 1004: 19000023 sb a6,384(zero) # 180 <_start-0x7ffffe80> + 1008: 03f8 addi a4,sp,460 + 100a: 0000 unimp + 100c: 5e12 lw t3,36(sp) + 100e: 0001 nop + 1010: 0100 addi s0,sp,128 + 1012: 032e slli t1,t1,0xb + 1014: 002c addi a1,sp,8 + 1016: 0000 unimp + 1018: 24a1 jal 1260 <_start-0x7fffeda0> + 101a: 0000 unimp + 101c: 0000 unimp + 101e: 1816 slli a6,a6,0x25 + 1020: 0004 0x4 + 1022: 3b00 fld fs0,48(a4) + 1024: 17000003 lb zero,368(zero) # 170 <_start-0x7ffffe90> + 1028: 028e slli t0,t0,0x3 + 102a: 0000 unimp + 102c: 2f01 jal 173c <_start-0x7fffe8c4> + 102e: 00002c03 lw s8,0(zero) # 0 <_start-0x80000000> + 1032: 1a00 addi s0,sp,304 + 1034: 00002d17 auipc s10,0x2 + 1038: 0100 addi s0,sp,128 + 103a: 034e032f 0x34e032f + 103e: 0000 unimp + 1040: 00001317 auipc t1,0x1 + 1044: 0100 addi s0,sp,128 + 1046: 034e032f 0x34e032f + 104a: 0000 unimp + 104c: 0000ae17 auipc t3,0xa + 1050: 0100 addi s0,sp,128 + 1052: 034e032f 0x34e032f + 1056: 0000 unimp + 1058: 00004217 auipc tp,0x4 + 105c: 0100 addi s0,sp,128 + 105e: 0355032f 0x355032f + 1062: 0000 unimp + 1064: 0000 unimp + 1066: 3819 jal 87c <_start-0x7ffff784> + 1068: 0004 0x4 + 106a: 1700 addi s0,sp,928 + 106c: 0000 unimp + 106e: 0000 unimp + 1070: 2f01 jal 1780 <_start-0x7fffe880> + 1072: 0000d603 lhu a2,0(ra) + 1076: 0000 unimp + 1078: 0200 addi s0,sp,256 + 107a: 0504 addi s1,sp,640 + 107c: 0179 addi sp,sp,30 + 107e: 0000 unimp + 1080: 0402 c.slli64 s0 + 1082: 0000e407 0xe407 + 1086: 0000 unimp + 1088: 0000024f fnmadd.s ft4,ft0,ft0,ft0,rne + 108c: 0004 0x4 + 108e: 0779 addi a4,a4,30 + 1090: 0000 unimp + 1092: 0104 addi s1,sp,128 + 1094: 0182 c.slli64 gp + 1096: 0000 unimp + 1098: 640c flw fa1,8(s0) + 109a: 0005 c.nop 1 + 109c: f600 fsw fs0,40(a2) + 109e: 0000 unimp + 10a0: 3800 fld fs0,48(s0) + 10a2: 001e c.slli zero,0x7 + 10a4: 4480 lw s0,8(s1) + 10a6: 0000 unimp + 10a8: 2300 fld fs0,0(a4) + 10aa: 0028 addi a0,sp,8 + 10ac: 0200 addi s0,sp,256 + 10ae: 0404 addi s1,sp,512 + 10b0: 000008cb fnmsub.s fa7,ft0,ft0,ft0,rne + 10b4: 00041c03 lh s8,0(s0) # fffe1000 <__global_pointer$+0x7ffdd398> + 10b8: 0200 addi s0,sp,256 + 10ba: 0d50 addi a2,sp,660 + 10bc: 0038 addi a4,sp,8 + 10be: 0000 unimp + 10c0: 0404 addi s1,sp,512 + 10c2: 6905 lui s2,0x1 + 10c4: 746e flw fs0,248(sp) + 10c6: 0200 addi s0,sp,256 + 10c8: 0601 addi a2,a2,0 + 10ca: 0062 c.slli zero,0x18 + 10cc: 0000 unimp + 10ce: 0802 c.slli64 a6 + 10d0: 7405 lui s0,0xfffe1 + 10d2: 0001 nop + 10d4: 0500 addi s0,sp,640 + 10d6: 00c8 addi a0,sp,68 + 10d8: 0000 unimp + 10da: 16014a03 lbu s4,352(sp) + 10de: 005f 0000 4d06 0x4d060000005f + 10e4: 0000 unimp + 10e6: 0200 addi s0,sp,256 + 10e8: 0801 addi a6,a6,0 + 10ea: 0060 addi s0,sp,12 + 10ec: 0000 unimp + 10ee: 0402 c.slli64 s0 + 10f0: 0000e907 0xe907 + 10f4: 0200 addi s0,sp,256 + 10f6: 0708 addi a0,sp,896 + 10f8: 00df 0000 0202 0x202000000df + 10fe: 00008c07 0x8c07 + 1102: 0700 addi s0,sp,896 + 1104: 005a c.slli zero,0x16 + 1106: 0000 unimp + 1108: 0000008b 0x8b + 110c: 6608 flw fa0,8(a2) + 110e: 0000 unimp + 1110: ff00 fsw fs0,56(a4) + 1112: 0600 addi s0,sp,768 + 1114: 0000007b 0x7b + 1118: d009 beqz s0,101a <_start-0x7fffefe6> + 111a: 0000 unimp + 111c: 0500 addi s0,sp,640 + 111e: 163c addi a5,sp,808 + 1120: 0000008b 0x8b + 1124: 00028703 lb a4,0(t0) + 1128: 0400 addi s0,sp,512 + 112a: 0f45 addi t5,t5,17 + 112c: 0025 c.nop 9 + 112e: 0000 unimp + 1130: 040a slli s0,s0,0x2 + 1132: 4a04 lw s1,16(a2) + 1134: 0000e203 0xe203 + 1138: 0b00 addi s0,sp,400 + 113a: 00da slli ra,ra,0x16 + 113c: 0000 unimp + 113e: 5104 lw s1,32(a0) + 1140: 660e flw fa2,192(sp) + 1142: 0000 unimp + 1144: 0400 addi s0,sp,512 + 1146: 0c000917 auipc s2,0xc000 + 114a: 7865 lui a6,0xffff9 + 114c: 0070 addi a2,sp,12 + 114e: 5204 lw s1,32(a2) + 1150: 660e flw fa2,192(sp) + 1152: 0000 unimp + 1154: 0400 addi s0,sp,512 + 1156: 0108 addi a0,sp,128 + 1158: 0b00 addi s0,sp,400 + 115a: 0781 addi a5,a5,0 + 115c: 0000 unimp + 115e: 5304 lw s1,32(a4) + 1160: 660e flw fa2,192(sp) + 1162: 0000 unimp + 1164: 0400 addi s0,sp,512 + 1166: 0001 nop + 1168: 0000 unimp + 116a: 7b0d lui s6,0xfffe3 + 116c: 0002 c.slli64 zero + 116e: 0400 addi s0,sp,512 + 1170: 4704 lw s1,8(a4) + 1172: 00010807 0x10807 + 1176: 0e00 addi s0,sp,784 + 1178: 6c66 flw fs8,88(sp) + 117a: 0074 addi a3,sp,12 + 117c: 4904 lw s1,16(a0) + 117e: 9c0a add s8,s8,sp + 1180: 0000 unimp + 1182: 0f00 addi s0,sp,912 + 1184: 0239 addi tp,tp,14 + 1186: 0000 unimp + 1188: 5504 lw s1,40(a0) + 118a: a805 j 11ba <_start-0x7fffee46> + 118c: 0000 unimp + 118e: 0000 unimp + 1190: 9410 0x9410 + 1192: 0005 c.nop 1 + 1194: 0100 addi s0,sp,128 + 1196: 0122 slli sp,sp,0x8 + 1198: 002c addi a1,sp,8 + 119a: 0000 unimp + 119c: 1e38 addi a4,sp,824 + 119e: 8000 0x8000 + 11a0: 0044 addi s1,sp,4 + 11a2: 0000 unimp + 11a4: 9c01 0x9c01 + 11a6: 0244 addi s1,sp,260 + 11a8: 0000 unimp + 11aa: 6111 addi sp,sp,256 + 11ac: 0100 addi s0,sp,128 + 11ae: 1422 slli s0,s0,0x28 + 11b0: 009c addi a5,sp,64 + 11b2: 0000 unimp + 11b4: 2501 jal 17b4 <_start-0x7fffe84c> + 11b6: 0000 unimp + 11b8: 6211 lui tp,0x4 + 11ba: 0100 addi s0,sp,128 + 11bc: 1e22 slli t3,t3,0x28 + 11be: 009c addi a5,sp,64 + 11c0: 0000 unimp + 11c2: 2524 fld fs1,72(a0) + 11c4: 0000 unimp + 11c6: 2812 fld fa6,256(sp) + 11c8: 0000 unimp + 11ca: 0100 addi s0,sp,128 + 11cc: 0324 addi s1,sp,392 + 11ce: 0038 addi a4,sp,8 + 11d0: 0000 unimp + 11d2: 1200 addi s0,sp,288 + 11d4: 000002a7 0x2a7 + 11d8: 2401 jal 13d8 <_start-0x7fffec28> + 11da: 00003803 0x3803 + 11de: 0000 unimp + 11e0: 635f4113 xori sp,t5,1589 + 11e4: 0100 addi s0,sp,128 + 11e6: 0325 addi t1,t1,9 + 11e8: 0244 addi s1,sp,260 + 11ea: 0000 unimp + 11ec: 735f4113 xori sp,t5,1845 + 11f0: 0100 addi s0,sp,128 + 11f2: 0325 addi t1,t1,9 + 11f4: 0244 addi s1,sp,260 + 11f6: 0000 unimp + 11f8: 655f4113 xori sp,t5,1621 + 11fc: 0100 addi s0,sp,128 + 11fe: 0325 addi t1,t1,9 + 1200: 0244 addi s1,sp,260 + 1202: 0000 unimp + 1204: 4114 lw a3,0(a0) + 1206: 665f 0100 0325 0x3250100665f + 120c: 0000024b fnmsub.s ft4,ft0,ft0,ft0,rne + 1210: 00002547 fmsub.s fa0,ft0,ft0,ft0,rdn + 1214: 635f4213 xori tp,t5,1589 + 1218: 0100 addi s0,sp,128 + 121a: 0326 slli t1,t1,0x9 + 121c: 0244 addi s1,sp,260 + 121e: 0000 unimp + 1220: 735f4213 xori tp,t5,1845 + 1224: 0100 addi s0,sp,128 + 1226: 0326 slli t1,t1,0x9 + 1228: 0244 addi s1,sp,260 + 122a: 0000 unimp + 122c: 4215 li tp,5 + 122e: 655f 0100 0326 0x3260100655f + 1234: 0244 addi s1,sp,260 + 1236: 0000 unimp + 1238: 7b06 flw fs6,96(sp) + 123a: 0800 addi s0,sp,16 + 123c: 1aff 0x1aff + 123e: 159f 5f42 0066 0x665f42159f + 1244: 2601 jal 1544 <_start-0x7fffeabc> + 1246: 00024b03 lbu s6,0(tp) # 4000 <_start-0x7fffc000> + 124a: 0100 addi s0,sp,128 + 124c: 135f 0072 2701 0x27010072135f + 1252: 00002c0b 0x2c0b + 1256: 1600 addi s0,sp,800 + 1258: 1e38 addi a4,sp,824 + 125a: 8000 0x8000 + 125c: 000c 0xc + 125e: 0000 unimp + 1260: 01e9 addi gp,gp,26 + 1262: 0000 unimp + 1264: 00006e17 auipc t3,0x6 + 1268: 0100 addi s0,sp,128 + 126a: 032a slli t1,t1,0xa + 126c: 00e2 slli ra,ra,0x18 + 126e: 0000 unimp + 1270: 1800 addi s0,sp,48 + 1272: 0450 addi a2,sp,516 + 1274: 0000 unimp + 1276: 01ff 0x1ff + 1278: 0000 unimp + 127a: 00006e17 auipc t3,0x6 + 127e: 0100 addi s0,sp,128 + 1280: 00e2032b 0xe2032b + 1284: 0000 unimp + 1286: 1900 addi s0,sp,176 + 1288: 0211 addi tp,tp,4 + 128a: 0000 unimp + 128c: 00042a17 auipc s4,0x42 + 1290: 0100 addi s0,sp,128 + 1292: 032c addi a1,sp,392 + 1294: 0038 addi a4,sp,8 + 1296: 0000 unimp + 1298: 1900 addi s0,sp,176 + 129a: 00000223 sb zero,4(zero) # 4 <_start-0x7ffffffc> + 129e: 00042a17 auipc s4,0x42 + 12a2: 0100 addi s0,sp,128 + 12a4: 032c addi a1,sp,392 + 12a6: 0038 addi a4,sp,8 + 12a8: 0000 unimp + 12aa: 1900 addi s0,sp,176 + 12ac: 0235 addi tp,tp,13 + 12ae: 0000 unimp + 12b0: 00042a17 auipc s4,0x42 + 12b4: 0100 addi s0,sp,128 + 12b6: 032c addi a1,sp,392 + 12b8: 0038 addi a4,sp,8 + 12ba: 0000 unimp + 12bc: 1a00 addi s0,sp,304 + 12be: 00042a17 auipc s4,0x42 + 12c2: 0100 addi s0,sp,128 + 12c4: 032c addi a1,sp,392 + 12c6: 0038 addi a4,sp,8 + 12c8: 0000 unimp + 12ca: 0000 unimp + 12cc: 0402 c.slli64 s0 + 12ce: 7905 lui s2,0xfffe1 + 12d0: 0001 nop + 12d2: 0200 addi s0,sp,256 + 12d4: 0704 addi s1,sp,896 + 12d6: 00e4 addi s1,sp,76 + 12d8: 0000 unimp + 12da: d300 sw s0,32(a4) + 12dc: 0400000b 0x400000b + 12e0: f900 fsw fs0,48(a0) + 12e2: 0008 0x8 + 12e4: 0400 addi s0,sp,512 + 12e6: 8201 c.srli64 a2 + 12e8: 0001 nop + 12ea: 0c00 addi s0,sp,528 + 12ec: 0935 addi s2,s2,13 + 12ee: 0000 unimp + 12f0: 00f6 slli ra,ra,0x1d + 12f2: 0000 unimp + 12f4: 1e7c addi a5,sp,828 + 12f6: 8000 0x8000 + 12f8: 004c addi a1,sp,4 + 12fa: 0000 unimp + 12fc: 29ea fld fs3,152(sp) + 12fe: 0000 unimp + 1300: 0402 c.slli64 s0 + 1302: 6905 lui s2,0x1 + 1304: 746e flw fs0,248(sp) + 1306: 0300 addi s0,sp,384 + 1308: 0704 addi s1,sp,896 + 130a: 00e9 addi ra,ra,26 + 130c: 0000 unimp + 130e: 74050803 lb a6,1856(a0) + 1312: 0001 nop + 1314: 0300 addi s0,sp,384 + 1316: 0410 addi a2,sp,512 + 1318: 064e slli a2,a2,0x13 + 131a: 0000 unimp + 131c: 62060103 lb sp,1568(a2) + 1320: 0000 unimp + 1322: 0300 addi s0,sp,384 + 1324: 0801 addi a6,a6,0 + 1326: 0060 addi s0,sp,12 + 1328: 0000 unimp + 132a: 9f050203 lb tp,-1552(a0) + 132e: 0005 c.nop 1 + 1330: 0300 addi s0,sp,384 + 1332: 0702 c.slli64 a4 + 1334: 008c addi a1,sp,64 + 1336: 0000 unimp + 1338: 79050403 lb s0,1936(a0) + 133c: 0001 nop + 133e: 0300 addi s0,sp,384 + 1340: 0704 addi s1,sp,896 + 1342: 00e4 addi s1,sp,76 + 1344: 0000 unimp + 1346: df070803 lb a6,-528(a4) + 134a: 0000 unimp + 134c: 0400 addi s0,sp,512 + 134e: 0832 slli a6,a6,0xc + 1350: 0000 unimp + 1352: 5e02 lw t3,32(sp) + 1354: 1701 addi a4,a4,-32 + 1356: 002c addi a1,sp,8 + 1358: 0000 unimp + 135a: f705 bnez a4,1282 <_start-0x7fffed7e> + 135c: 0008 0x8 + 135e: 0300 addi s0,sp,384 + 1360: 0e2e slli t3,t3,0xb + 1362: 005d c.nop 23 + 1364: 0000 unimp + 1366: 5905 li s2,-31 + 1368: 000a c.slli zero,0x2 + 136a: 0300 addi s0,sp,384 + 136c: 0e74 addi a3,sp,796 + 136e: 005d c.nop 23 + 1370: 0000 unimp + 1372: f305 bnez a4,1292 <_start-0x7fffed6e> + 1374: 000a c.slli zero,0x2 + 1376: 0300 addi s0,sp,384 + 1378: 00251793 slli a5,a0,0x2 + 137c: 0000 unimp + 137e: 0406 slli s0,s0,0x1 + 1380: c503a503 lw a0,-944(t2) + 1384: 0000 unimp + 1386: 0700 addi s0,sp,896 + 1388: 0824 addi s1,sp,24 + 138a: 0000 unimp + 138c: 720ca703 lw a4,1824(s9) + 1390: 0000 unimp + 1392: 0700 addi s0,sp,896 + 1394: 000007cb fnmsub.s fa5,ft0,ft0,ft0,rne + 1398: c513a803 lw a6,-943(t2) + 139c: 0000 unimp + 139e: 0000 unimp + 13a0: 4808 lw a0,16(s0) + 13a2: 0000 unimp + 13a4: d500 sw s0,40(a0) + 13a6: 0000 unimp + 13a8: 0900 addi s0,sp,144 + 13aa: 002c addi a1,sp,8 + 13ac: 0000 unimp + 13ae: 080a0003 lb zero,128(s4) # 4333e <_start-0x7ffbccc2> + 13b2: f909a203 lw tp,-112(s3) + 13b6: 0000 unimp + 13b8: 0b00 addi s0,sp,400 + 13ba: 00000a43 fmadd.s fs4,ft0,ft0,ft0,rne + 13be: 2507a403 lw s0,592(a5) + 13c2: 0000 unimp + 13c4: 0000 unimp + 13c6: 000a4b0b 0xa4b0b + 13ca: 0300 addi s0,sp,384 + 13cc: 05a9 addi a1,a1,10 + 13ce: 000000a3 sb zero,1(zero) # 1 <_start-0x7fffffff> + 13d2: 0004 0x4 + 13d4: 1205 addi tp,tp,-31 + 13d6: 0009 c.nop 2 + 13d8: 0300 addi s0,sp,384 + 13da: 03aa slli t2,t2,0xa + 13dc: 00d5 addi ra,ra,21 + 13de: 0000 unimp + 13e0: 040c addi a1,sp,512 + 13e2: a405 j 1602 <_start-0x7fffe9fe> + 13e4: 000a c.slli zero,0x2 + 13e6: 0400 addi s0,sp,512 + 13e8: 1916 slli s2,s2,0x25 + 13ea: 0064 addi s1,sp,12 + 13ec: 0000 unimp + 13ee: 1d05 addi s10,s10,-31 + 13f0: 0009 c.nop 2 + 13f2: 0500 addi s0,sp,640 + 13f4: 0d0c addi a1,sp,656 + 13f6: 0025 c.nop 9 + 13f8: 0000 unimp + 13fa: 9305 srli a4,a4,0x21 + 13fc: 0009 c.nop 2 + 13fe: 0400 addi s0,sp,512 + 1400: 01131b23 sh a7,22(t1) # 2056 <_start-0x7fffdfaa> + 1404: 0000 unimp + 1406: 8e0d sub a2,a2,a1 + 1408: 18000007 0x18000007 + 140c: 3404 fld fs1,40(s0) + 140e: 8508 0x8508 + 1410: 0001 nop + 1412: 0b00 addi s0,sp,400 + 1414: 09e6 slli s3,s3,0x19 + 1416: 0000 unimp + 1418: 3604 fld fs1,40(a2) + 141a: 00018513 mv a0,gp + 141e: 0000 unimp + 1420: 5f0e lw t5,224(sp) + 1422: 3704006b 0x3704006b + 1426: 00002507 flw fa0,0(zero) # 0 <_start-0x80000000> + 142a: 0400 addi s0,sp,512 + 142c: 000a2e0b 0xa2e0b + 1430: 0400 addi s0,sp,512 + 1432: 00250b37 lui s6,0x250 + 1436: 0000 unimp + 1438: 0b08 addi a0,sp,400 + 143a: 0780 addi s0,sp,960 + 143c: 0000 unimp + 143e: 3704 fld fs1,40(a4) + 1440: 2514 fld fa3,8(a0) + 1442: 0000 unimp + 1444: 0c00 addi s0,sp,528 + 1446: 0006fc0b 0x6fc0b + 144a: 0400 addi s0,sp,512 + 144c: 00251b37 lui s6,0x251 + 1450: 0000 unimp + 1452: 0e10 addi a2,sp,784 + 1454: 785f 0400 0b38 0xb380400785f + 145a: 0000018b 0x18b + 145e: 0014 0x14 + 1460: 012b040f 0x12b040f + 1464: 0000 unimp + 1466: 0708 addi a0,sp,896 + 1468: 0001 nop + 146a: 9b00 0x9b00 + 146c: 0001 nop + 146e: 0900 addi s0,sp,144 + 1470: 002c addi a1,sp,8 + 1472: 0000 unimp + 1474: 0000 unimp + 1476: ae0d j 17a8 <_start-0x7fffe858> + 1478: 24000007 0x24000007 + 147c: 3c04 fld fs1,56(s0) + 147e: 1e08 addi a0,sp,816 + 1480: 0002 c.slli64 zero + 1482: 0b00 addi s0,sp,400 + 1484: 0694 addi a3,sp,832 + 1486: 0000 unimp + 1488: 3e04 fld fs1,56(a2) + 148a: 2509 jal 1a8c <_start-0x7fffe574> + 148c: 0000 unimp + 148e: 0000 unimp + 1490: 000b470b 0xb470b + 1494: 0400 addi s0,sp,512 + 1496: 0025093f 0b040000 0xb0400000025093f + 149e: 06b0 addi a2,sp,840 + 14a0: 0000 unimp + 14a2: 4004 lw s1,0(s0) + 14a4: 2509 jal 1aa6 <_start-0x7fffe55a> + 14a6: 0000 unimp + 14a8: 0800 addi s0,sp,16 + 14aa: 000b830b 0xb830b + 14ae: 0400 addi s0,sp,512 + 14b0: 0941 addi s2,s2,16 + 14b2: 0025 c.nop 9 + 14b4: 0000 unimp + 14b6: 0b0c addi a1,sp,400 + 14b8: 08d1 addi a7,a7,20 + 14ba: 0000 unimp + 14bc: 4204 lw s1,0(a2) + 14be: 2509 jal 1ac0 <_start-0x7fffe540> + 14c0: 0000 unimp + 14c2: 1000 addi s0,sp,32 + 14c4: 00087a0b 0x87a0b + 14c8: 0400 addi s0,sp,512 + 14ca: 00250943 fmadd.s fs2,fa0,ft2,ft0,rne + 14ce: 0000 unimp + 14d0: 0b14 addi a3,sp,400 + 14d2: 0adc addi a5,sp,340 + 14d4: 0000 unimp + 14d6: 4404 lw s1,8(s0) + 14d8: 2509 jal 1ada <_start-0x7fffe526> + 14da: 0000 unimp + 14dc: 1800 addi s0,sp,48 + 14de: 00099c0b 0x99c0b + 14e2: 0400 addi s0,sp,512 + 14e4: 0945 addi s2,s2,17 + 14e6: 0025 c.nop 9 + 14e8: 0000 unimp + 14ea: 0b1c addi a5,sp,400 + 14ec: 0b2d addi s6,s6,11 + 14ee: 0000 unimp + 14f0: 4604 lw s1,8(a2) + 14f2: 2509 jal 1af4 <_start-0x7fffe50c> + 14f4: 0000 unimp + 14f6: 2000 fld fs0,0(s0) + 14f8: 1000 addi s0,sp,32 + 14fa: 000006cf fnmadd.s fa3,ft0,ft0,ft0,rne + 14fe: 0108 addi a0,sp,128 + 1500: 4f04 lw s1,24(a4) + 1502: 6308 flw fa0,0(a4) + 1504: 0002 c.slli64 zero + 1506: 0b00 addi s0,sp,400 + 1508: 00000773 0x773 + 150c: 5004 lw s1,32(s0) + 150e: 630a flw ft6,128(sp) + 1510: 0002 c.slli64 zero + 1512: 0000 unimp + 1514: 00096f0b 0x96f0b + 1518: 0400 addi s0,sp,512 + 151a: 0951 addi s2,s2,20 + 151c: 00000263 beqz zero,1520 <_start-0x7fffeae0> + 1520: 1180 addi s0,sp,224 + 1522: 0a96 slli s5,s5,0x5 + 1524: 0000 unimp + 1526: 5304 lw s1,32(a4) + 1528: 070a slli a4,a4,0x2 + 152a: 0001 nop + 152c: 0000 unimp + 152e: 1101 addi sp,sp,-32 + 1530: 06f4 addi a3,sp,844 + 1532: 0000 unimp + 1534: 5604 lw s1,40(a2) + 1536: 070a slli a4,a4,0x2 + 1538: 0001 nop + 153a: 0400 addi s0,sp,512 + 153c: 0001 nop + 153e: 0508 addi a0,sp,640 + 1540: 0001 nop + 1542: 7300 flw fs0,32(a4) + 1544: 0002 c.slli64 zero + 1546: 0900 addi s0,sp,144 + 1548: 002c addi a1,sp,8 + 154a: 0000 unimp + 154c: 001f da10 0008 0x8da10001f + 1552: 9000 0x9000 + 1554: 0401 addi s0,s0,0 + 1556: 0862 slli a6,a6,0x18 + 1558: 02b6 slli t0,t0,0xd + 155a: 0000 unimp + 155c: 0009e60b 0x9e60b + 1560: 0400 addi s0,sp,512 + 1562: 02b61263 bne a2,a1,1586 <_start-0x7fffea7a> + 1566: 0000 unimp + 1568: 0b00 addi s0,sp,400 + 156a: 09fe slli s3,s3,0x1f + 156c: 0000 unimp + 156e: 6404 flw fs1,8(s0) + 1570: 2506 fld fa0,64(sp) + 1572: 0000 unimp + 1574: 0400 addi s0,sp,512 + 1576: 00077b0b 0x77b0b + 157a: 0400 addi s0,sp,512 + 157c: 0966 slli s2,s2,0x19 + 157e: 02bc addi a5,sp,328 + 1580: 0000 unimp + 1582: 0b08 addi a0,sp,400 + 1584: 000006cf fnmadd.s fa3,ft0,ft0,ft0,rne + 1588: 6704 flw fs1,8(a4) + 158a: 1e1e slli t3,t3,0x27 + 158c: 0002 c.slli64 zero + 158e: 8800 0x8800 + 1590: 0f00 addi s0,sp,912 + 1592: 7304 flw fs1,32(a4) + 1594: 0002 c.slli64 zero + 1596: 0800 addi s0,sp,16 + 1598: 02cc addi a1,sp,324 + 159a: 0000 unimp + 159c: 02cc addi a1,sp,324 + 159e: 0000 unimp + 15a0: 2c09 jal 17b2 <_start-0x7fffe84e> + 15a2: 0000 unimp + 15a4: 1f00 addi s0,sp,944 + 15a6: 0f00 addi s0,sp,912 + 15a8: d204 sw s1,32(a2) + 15aa: 0002 c.slli64 zero + 15ac: 1200 addi s0,sp,288 + 15ae: a60d j 18d0 <_start-0x7fffe730> + 15b0: 0009 c.nop 2 + 15b2: 0800 addi s0,sp,16 + 15b4: 7a04 flw fs1,48(a2) + 15b6: fb08 fsw fa0,48(a4) + 15b8: 0002 c.slli64 zero + 15ba: 0b00 addi s0,sp,400 + 15bc: 06aa slli a3,a3,0xa + 15be: 0000 unimp + 15c0: 7b04 flw fs1,48(a4) + 15c2: fb11 bnez a4,14d6 <_start-0x7fffeb2a> + 15c4: 0002 c.slli64 zero + 15c6: 0000 unimp + 15c8: 0005bb0b 0x5bb0b + 15cc: 0400 addi s0,sp,512 + 15ce: 067c addi a5,sp,780 + 15d0: 0025 c.nop 9 + 15d2: 0000 unimp + 15d4: 0004 0x4 + 15d6: 0048040f 0x48040f + 15da: 0000 unimp + 15dc: cf0d beqz a4,1616 <_start-0x7fffe9ea> + 15de: 0009 c.nop 2 + 15e0: 6800 flw fs0,16(s0) + 15e2: ba04 fsd fs1,48(a2) + 15e4: 4408 lw a0,8(s0) + 15e6: 0004 0x4 + 15e8: 0e00 addi s0,sp,784 + 15ea: 705f 0400 12bb 0x12bb0400705f + 15f0: 000002fb 0x2fb + 15f4: 0e00 addi s0,sp,784 + 15f6: 725f 0400 07bc 0x7bc0400725f + 15fc: 0025 c.nop 9 + 15fe: 0000 unimp + 1600: 0e04 addi s1,sp,784 + 1602: 775f 0400 07bd 0x7bd0400775f + 1608: 0025 c.nop 9 + 160a: 0000 unimp + 160c: 0b08 addi a0,sp,400 + 160e: 06ed addi a3,a3,27 + 1610: 0000 unimp + 1612: be04 fsd fs1,56(a2) + 1614: 4f09 li t5,2 + 1616: 0000 unimp + 1618: 0c00 addi s0,sp,528 + 161a: 0007da0b 0x7da0b + 161e: 0400 addi s0,sp,512 + 1620: 004f09bf 0e0e0000 0xe0e0000004f09bf + 1628: 625f 0066 c004 0xc0040066625f + 162e: d311 beqz a4,1532 <_start-0x7fffeace> + 1630: 0002 c.slli64 zero + 1632: 1000 addi s0,sp,32 + 1634: 00063d0b 0x63d0b + 1638: 0400 addi s0,sp,512 + 163a: 07c1 addi a5,a5,16 + 163c: 0025 c.nop 9 + 163e: 0000 unimp + 1640: 0b18 addi a4,sp,400 + 1642: 06dd addi a3,a3,23 + 1644: 0000 unimp + 1646: c804 sw s1,16(s0) + 1648: 050a slli a0,a0,0x2 + 164a: 0001 nop + 164c: 1c00 addi s0,sp,560 + 164e: 00092f0b 0x92f0b + 1652: 0400 addi s0,sp,512 + 1654: 1dca slli s11,s11,0x32 + 1656: 05c8 addi a0,sp,708 + 1658: 0000 unimp + 165a: 0b20 addi s0,sp,408 + 165c: 00000873 0x873 + 1660: cc04 sw s1,24(s0) + 1662: f71d bnez a4,1590 <_start-0x7fffea70> + 1664: 0005 c.nop 1 + 1666: 2400 fld fs0,8(s0) + 1668: 000a530b 0xa530b + 166c: 0400 addi s0,sp,512 + 166e: 061b0dcf fnmadd.q fs11,fs6,ft1,ft0,rne + 1672: 0000 unimp + 1674: 0b28 addi a0,sp,408 + 1676: 069d addi a3,a3,7 + 1678: 0000 unimp + 167a: d004 sw s1,32(s0) + 167c: 3509 jal 147e <_start-0x7fffeb82> + 167e: 0006 c.slli zero,0x1 + 1680: 2c00 fld fs0,24(s0) + 1682: 5f0e lw t5,224(sp) + 1684: 6275 lui tp,0x1d + 1686: 0400 addi s0,sp,512 + 1688: 02d311d3 fadd.d ft3,ft6,fa3,rtz + 168c: 0000 unimp + 168e: 0e30 addi a2,sp,792 + 1690: 755f 0070 d404 0xd4040070755f + 1696: fb12 fsw ft4,180(sp) + 1698: 0002 c.slli64 zero + 169a: 3800 fld fs0,48(s0) + 169c: 5f0e lw t5,224(sp) + 169e: 7275 lui tp,0xffffd + 16a0: 0400 addi s0,sp,512 + 16a2: 07d5 addi a5,a5,21 + 16a4: 0025 c.nop 9 + 16a6: 0000 unimp + 16a8: 0b3c addi a5,sp,408 + 16aa: 06a4 addi s1,sp,840 + 16ac: 0000 unimp + 16ae: d804 sw s1,48(s0) + 16b0: 3b11 jal 13c4 <_start-0x7fffec3c> + 16b2: 0006 c.slli zero,0x1 + 16b4: 4000 lw s0,0(s0) + 16b6: 000b1f0b 0xb1f0b + 16ba: 0400 addi s0,sp,512 + 16bc: 11d9 addi gp,gp,-10 + 16be: 0000064b fnmsub.s fa2,ft0,ft0,ft0,rne + 16c2: 6c5f0e43 0x6c5f0e43 + 16c6: 0062 c.slli zero,0x18 + 16c8: dc04 sw s1,56(s0) + 16ca: d311 beqz a4,15ce <_start-0x7fffea32> + 16cc: 0002 c.slli64 zero + 16ce: 4400 lw s0,8(s0) + 16d0: 000a6a0b 0xa6a0b + 16d4: 0400 addi s0,sp,512 + 16d6: 07df 0025 0000 0x2507df + 16dc: 0b4c addi a1,sp,404 + 16de: 08ad addi a7,a7,11 + 16e0: 0000 unimp + 16e2: e004 fsw fs1,0(s0) + 16e4: 7f0a flw ft10,160(sp) + 16e6: 0000 unimp + 16e8: 5000 lw s0,32(s0) + 16ea: 0005fa0b 0x5fa0b + 16ee: 0400 addi s0,sp,512 + 16f0: 046212e3 bne tp,t1,1f34 <_start-0x7fffe0cc> + 16f4: 0000 unimp + 16f6: 0b54 addi a3,sp,404 + 16f8: 0839 addi a6,a6,14 + 16fa: 0000 unimp + 16fc: e704 fsw fs1,8(a4) + 16fe: 1f0c addi a1,sp,944 + 1700: 0001 nop + 1702: 5800 lw s0,48(s0) + 1704: 0007c20b 0x7c20b + 1708: 0400 addi s0,sp,512 + 170a: 0ee9 addi t4,t4,26 + 170c: 00f9 addi ra,ra,30 + 170e: 0000 unimp + 1710: 0b5c addi a5,sp,404 + 1712: 09ad addi s3,s3,11 + 1714: 0000 unimp + 1716: ea04 fsw fs1,16(a2) + 1718: 2509 jal 1d1a <_start-0x7fffe2e6> + 171a: 0000 unimp + 171c: 6400 flw fs0,8(s0) + 171e: 1300 addi s0,sp,416 + 1720: 00000097 auipc ra,0x0 + 1724: 0462 slli s0,s0,0x18 + 1726: 0000 unimp + 1728: 6214 flw fa3,0(a2) + 172a: 0004 0x4 + 172c: 1400 addi s0,sp,544 + 172e: 0105 addi sp,sp,1 + 1730: 0000 unimp + 1732: b614 fsd fa3,40(a2) + 1734: 0005 c.nop 1 + 1736: 1400 addi s0,sp,544 + 1738: 0025 c.nop 9 + 173a: 0000 unimp + 173c: 0f00 addi s0,sp,912 + 173e: 6d04 flw fs1,24(a0) + 1740: 0004 0x4 + 1742: 1500 addi s0,sp,672 + 1744: 0462 slli s0,s0,0x18 + 1746: 0000 unimp + 1748: 3616 fld fa2,352(sp) + 174a: 000a c.slli zero,0x2 + 174c: 2800 fld fs0,16(s0) + 174e: 0404 addi s1,sp,512 + 1750: 0265 addi tp,tp,25 + 1752: b608 fsd fa0,40(a2) + 1754: 0005 c.nop 1 + 1756: 1700 addi s0,sp,928 + 1758: 098c addi a1,sp,208 + 175a: 0000 unimp + 175c: 6704 flw fs1,8(a4) + 175e: 0702 c.slli64 a4 + 1760: 0025 c.nop 9 + 1762: 0000 unimp + 1764: 1700 addi s0,sp,928 + 1766: 0aec addi a1,sp,348 + 1768: 0000 unimp + 176a: 6c04 flw fs1,24(s0) + 176c: 0b02 c.slli64 s6 + 176e: 000006a7 0x6a7 + 1772: 1704 addi s1,sp,928 + 1774: 0ad4 addi a3,sp,340 + 1776: 0000 unimp + 1778: 6c04 flw fs1,24(s0) + 177a: 1402 slli s0,s0,0x20 + 177c: 000006a7 0x6a7 + 1780: 1708 addi a0,sp,928 + 1782: 0786 slli a5,a5,0x1 + 1784: 0000 unimp + 1786: 6c04 flw fs1,24(s0) + 1788: 1e02 slli t3,t3,0x20 + 178a: 000006a7 0x6a7 + 178e: 170c addi a1,sp,928 + 1790: 09f9 addi s3,s3,30 + 1792: 0000 unimp + 1794: 6e04 flw fs1,24(a2) + 1796: 0802 c.slli64 a6 + 1798: 0025 c.nop 9 + 179a: 0000 unimp + 179c: 1710 addi a2,sp,928 + 179e: 05c9 addi a1,a1,18 + 17a0: 0000 unimp + 17a2: 6f04 flw fs1,24(a4) + 17a4: 0802 c.slli64 a6 + 17a6: 000008a7 0x8a7 + 17aa: 1714 addi a3,sp,928 + 17ac: 0a15 addi s4,s4,5 + 17ae: 0000 unimp + 17b0: 7204 flw fs1,32(a2) + 17b2: 0702 c.slli64 a4 + 17b4: 0025 c.nop 9 + 17b6: 0000 unimp + 17b8: 1730 addi a2,sp,936 + 17ba: 00000a03 lb s4,0(zero) # 0 <_start-0x80000000> + 17be: 7304 flw fs1,32(a4) + 17c0: 1602 slli a2,a2,0x20 + 17c2: 08bc addi a5,sp,88 + 17c4: 0000 unimp + 17c6: 1734 addi a3,sp,936 + 17c8: 08ec addi a1,sp,92 + 17ca: 0000 unimp + 17cc: 7504 flw fs1,40(a0) + 17ce: 0702 c.slli64 a4 + 17d0: 0025 c.nop 9 + 17d2: 0000 unimp + 17d4: 1738 addi a4,sp,936 + 17d6: 00000a0b 0xa0b + 17da: 7704 flw fs1,40(a4) + 17dc: 0a02 c.slli64 s4 + 17de: 08cd addi a7,a7,19 + 17e0: 0000 unimp + 17e2: 173c addi a5,sp,936 + 17e4: 081c addi a5,sp,16 + 17e6: 0000 unimp + 17e8: 7a04 flw fs1,48(a2) + 17ea: 1302 slli t1,t1,0x20 + 17ec: 0185 addi gp,gp,1 + 17ee: 0000 unimp + 17f0: 1740 addi s0,sp,932 + 17f2: 0708 addi a0,sp,896 + 17f4: 0000 unimp + 17f6: 7b04 flw fs1,48(a4) + 17f8: 0702 c.slli64 a4 + 17fa: 0025 c.nop 9 + 17fc: 0000 unimp + 17fe: 1744 addi s1,sp,932 + 1800: 0b7e slli s6,s6,0x1f + 1802: 0000 unimp + 1804: 7c04 flw fs1,56(s0) + 1806: 1302 slli t1,t1,0x20 + 1808: 0185 addi gp,gp,1 + 180a: 0000 unimp + 180c: 1748 addi a0,sp,932 + 180e: 08fe slli a7,a7,0x1f + 1810: 0000 unimp + 1812: 7d04 flw fs1,56(a0) + 1814: 1402 slli s0,s0,0x20 + 1816: 000008d3 fadd.s fa7,ft0,ft0,rne + 181a: 174c addi a1,sp,932 + 181c: 07d2 slli a5,a5,0x14 + 181e: 0000 unimp + 1820: 8004 0x8004 + 1822: 0702 c.slli64 a4 + 1824: 0025 c.nop 9 + 1826: 0000 unimp + 1828: 1750 addi a2,sp,932 + 182a: 0000073f 09028104 0x90281040000073f + 1832: 05b6 slli a1,a1,0xd + 1834: 0000 unimp + 1836: 1754 addi a3,sp,932 + 1838: 0985 addi s3,s3,1 + 183a: 0000 unimp + 183c: a404 fsd fs1,8(s0) + 183e: 0702 c.slli64 a4 + 1840: 0882 c.slli64 a7 + 1842: 0000 unimp + 1844: 1858 addi a4,sp,52 + 1846: 08da slli a7,a7,0x16 + 1848: 0000 unimp + 184a: a804 fsd fs1,16(s0) + 184c: 1302 slli t1,t1,0x20 + 184e: 02b6 slli t0,t0,0xd + 1850: 0000 unimp + 1852: 0148 addi a0,sp,132 + 1854: fa18 fsw fa4,48(a2) + 1856: 04000007 0x4000007 + 185a: 02a9 addi t0,t0,10 + 185c: 7312 flw ft6,36(sp) + 185e: 0002 c.slli64 zero + 1860: 4c00 lw s0,24(s0) + 1862: 1801 addi a6,a6,-32 + 1864: 0b06 slli s6,s6,0x1 + 1866: 0000 unimp + 1868: ad04 fsd fs1,24(a0) + 186a: 0c02 c.slli64 s8 + 186c: 08e4 addi s1,sp,92 + 186e: 0000 unimp + 1870: 02dc addi a5,sp,324 + 1872: e518 fsw fa4,8(a0) + 1874: 0006 c.slli zero,0x1 + 1876: 0400 addi s0,sp,512 + 1878: 02b2 slli t0,t0,0xc + 187a: 6810 flw fa2,16(s0) + 187c: 0006 c.slli zero,0x1 + 187e: e000 fsw fs0,0(s0) + 1880: 1802 slli a6,a6,0x20 + 1882: 06ca slli a3,a3,0x12 + 1884: 0000 unimp + 1886: b404 fsd fs1,40(s0) + 1888: 0a02 c.slli64 s4 + 188a: 08f0 addi a2,sp,92 + 188c: 0000 unimp + 188e: 02ec addi a1,sp,332 + 1890: 0f00 addi s0,sp,912 + 1892: bc04 fsd fs1,56(s0) + 1894: 0005 c.nop 1 + 1896: 0300 addi s0,sp,384 + 1898: 0801 addi a6,a6,0 + 189a: 0069 c.nop 26 + 189c: 0000 unimp + 189e: bc15 j 12d2 <_start-0x7fffed2e> + 18a0: 0005 c.nop 1 + 18a2: 0f00 addi s0,sp,912 + 18a4: 4404 lw s1,8(s0) + 18a6: 0004 0x4 + 18a8: 1300 addi s0,sp,416 + 18aa: 00000097 auipc ra,0x0 + 18ae: 05ec addi a1,sp,716 + 18b0: 0000 unimp + 18b2: 6214 flw fa3,0(a2) + 18b4: 0004 0x4 + 18b6: 1400 addi s0,sp,544 + 18b8: 0105 addi sp,sp,1 + 18ba: 0000 unimp + 18bc: ec14 fsw fa3,24(s0) + 18be: 0005 c.nop 1 + 18c0: 1400 addi s0,sp,544 + 18c2: 0025 c.nop 9 + 18c4: 0000 unimp + 18c6: 0f00 addi s0,sp,912 + 18c8: c304 sw s1,0(a4) + 18ca: 0005 c.nop 1 + 18cc: 1500 addi s0,sp,672 + 18ce: 05ec addi a1,sp,716 + 18d0: 0000 unimp + 18d2: 05ce040f 0x5ce040f + 18d6: 0000 unimp + 18d8: 00008b13 mv s6,ra + 18dc: 1b00 addi s0,sp,432 + 18de: 0006 c.slli zero,0x1 + 18e0: 1400 addi s0,sp,544 + 18e2: 0462 slli s0,s0,0x18 + 18e4: 0000 unimp + 18e6: 0514 addi a3,sp,640 + 18e8: 0001 nop + 18ea: 1400 addi s0,sp,544 + 18ec: 0000008b 0x8b + 18f0: 2514 fld fa3,8(a0) + 18f2: 0000 unimp + 18f4: 0000 unimp + 18f6: 05fd040f 0x5fd040f + 18fa: 0000 unimp + 18fc: 00002513 slti a0,zero,0 + 1900: 3500 fld fs0,40(a0) + 1902: 0006 c.slli zero,0x1 + 1904: 1400 addi s0,sp,544 + 1906: 0462 slli s0,s0,0x18 + 1908: 0000 unimp + 190a: 0514 addi a3,sp,640 + 190c: 0001 nop + 190e: 0000 unimp + 1910: 0621040f 0x621040f + 1914: 0000 unimp + 1916: 4808 lw a0,16(s0) + 1918: 0000 unimp + 191a: 4b00 lw s0,16(a4) + 191c: 0006 c.slli zero,0x1 + 191e: 0900 addi s0,sp,144 + 1920: 002c addi a1,sp,8 + 1922: 0000 unimp + 1924: 0002 c.slli64 zero + 1926: 4808 lw a0,16(s0) + 1928: 0000 unimp + 192a: 5b00 lw s0,48(a4) + 192c: 0006 c.slli zero,0x1 + 192e: 0900 addi s0,sp,144 + 1930: 002c addi a1,sp,8 + 1932: 0000 unimp + 1934: 0000 unimp + 1936: 0104 addi s1,sp,128 + 1938: 04000007 0x4000007 + 193c: 0124 addi s1,sp,136 + 193e: 011a slli sp,sp,0x6 + 1940: 19000003 lb zero,400(zero) # 190 <_start-0x7ffffe70> + 1944: 0ae6 slli s5,s5,0x19 + 1946: 0000 unimp + 1948: 040c addi a1,sp,512 + 194a: 0128 addi a0,sp,136 + 194c: a108 fsd fa0,0(a0) + 194e: 0006 c.slli zero,0x1 + 1950: 1700 addi s0,sp,928 + 1952: 09e6 slli s3,s3,0x19 + 1954: 0000 unimp + 1956: 2a04 fld fs1,16(a2) + 1958: 1101 addi sp,sp,-32 + 195a: 06a1 addi a3,a3,8 + 195c: 0000 unimp + 195e: 1700 addi s0,sp,928 + 1960: 07ea slli a5,a5,0x1a + 1962: 0000 unimp + 1964: 2b04 fld fs1,16(a4) + 1966: 0701 addi a4,a4,0 + 1968: 0025 c.nop 9 + 196a: 0000 unimp + 196c: 1704 addi s1,sp,928 + 196e: 09b5 addi s3,s3,13 + 1970: 0000 unimp + 1972: 2c04 fld fs1,24(s0) + 1974: 0b01 addi s6,s6,0 + 1976: 000006a7 0x6a7 + 197a: 0008 0x8 + 197c: 0668040f 0x668040f + 1980: 0000 unimp + 1982: 065b040f 0x65b040f + 1986: 0000 unimp + 1988: c119 beqz a0,198e <_start-0x7fffe672> + 198a: 0005 c.nop 1 + 198c: 0e00 addi s0,sp,784 + 198e: 4404 lw s1,8(s0) + 1990: 0801 addi a6,a6,0 + 1992: 06e6 slli a3,a3,0x19 + 1994: 0000 unimp + 1996: 000a3d17 auipc s10,0xa3 + 199a: 0400 addi s0,sp,512 + 199c: 0145 addi sp,sp,17 + 199e: e612 fsw ft4,12(sp) + 19a0: 0006 c.slli zero,0x1 + 19a2: 0000 unimp + 19a4: 00085517 auipc a0,0x85 + 19a8: 0400 addi s0,sp,512 + 19aa: 0146 slli sp,sp,0x11 + 19ac: e612 fsw ft4,12(sp) + 19ae: 0006 c.slli zero,0x1 + 19b0: 0600 addi s0,sp,768 + 19b2: 000a9f17 auipc t5,0xa9 + 19b6: 0400 addi s0,sp,512 + 19b8: 56120147 fmsub.q ft2,ft4,ft1,fa0,rne + 19bc: 0000 unimp + 19be: 0c00 addi s0,sp,528 + 19c0: 0800 addi s0,sp,16 + 19c2: 0056 c.slli zero,0x15 + 19c4: 0000 unimp + 19c6: 06f6 slli a3,a3,0x1d + 19c8: 0000 unimp + 19ca: 2c09 jal 1bdc <_start-0x7fffe424> + 19cc: 0000 unimp + 19ce: 0200 addi s0,sp,256 + 19d0: 1a00 addi s0,sp,304 + 19d2: 04d0 addi a2,sp,580 + 19d4: 0285 addi t0,t0,1 + 19d6: 00080b07 0x80b07 + 19da: 1700 addi s0,sp,928 + 19dc: 0000088f 0x88f + 19e0: 8704 0x8704 + 19e2: 1802 slli a6,a6,0x20 + 19e4: 002c addi a1,sp,8 + 19e6: 0000 unimp + 19e8: 1700 addi s0,sp,928 + 19ea: 0a82 c.slli64 s5 + 19ec: 0000 unimp + 19ee: 8804 0x8804 + 19f0: 1202 slli tp,tp,0x20 + 19f2: 05b6 slli a1,a1,0xd + 19f4: 0000 unimp + 19f6: 1704 addi s1,sp,928 + 19f8: 0000080f 0x80f + 19fc: 8904 0x8904 + 19fe: 1002 c.slli zero,0x20 + 1a00: 0000080b 0x80b + 1a04: 1708 addi a0,sp,928 + 1a06: 0b38 addi a4,sp,408 + 1a08: 0000 unimp + 1a0a: 8a04 0x8a04 + 1a0c: 1702 slli a4,a4,0x20 + 1a0e: 0000019b 0x19b + 1a12: 1724 addi s1,sp,936 + 1a14: 0796 slli a5,a5,0x5 + 1a16: 0000 unimp + 1a18: 8b04 0x8b04 + 1a1a: 0f02 c.slli64 t5 + 1a1c: 0025 c.nop 9 + 1a1e: 0000 unimp + 1a20: 1748 addi a0,sp,932 + 1a22: 09e1 addi s3,s3,24 + 1a24: 0000 unimp + 1a26: 8c04 0x8c04 + 1a28: 2c02 fld fs8,0(sp) + 1a2a: 0000006b 0x6b + 1a2e: 1750 addi a2,sp,932 + 1a30: 0b50 addi a2,sp,404 + 1a32: 0000 unimp + 1a34: 8d04 0x8d04 + 1a36: 1a02 slli s4,s4,0x20 + 1a38: 06ad addi a3,a3,11 + 1a3a: 0000 unimp + 1a3c: 1758 addi a4,sp,932 + 1a3e: 09ec addi a1,sp,220 + 1a40: 0000 unimp + 1a42: 8e04 0x8e04 + 1a44: 1602 slli a2,a2,0x20 + 1a46: 00f9 addi ra,ra,30 + 1a48: 0000 unimp + 1a4a: 1768 addi a0,sp,940 + 1a4c: 0b70 addi a2,sp,412 + 1a4e: 0000 unimp + 1a50: 8f04 0x8f04 + 1a52: 1602 slli a2,a2,0x20 + 1a54: 00f9 addi ra,ra,30 + 1a56: 0000 unimp + 1a58: 1770 addi a2,sp,940 + 1a5a: 0686 slli a3,a3,0x1 + 1a5c: 0000 unimp + 1a5e: 9004 0x9004 + 1a60: 1602 slli a2,a2,0x20 + 1a62: 00f9 addi ra,ra,30 + 1a64: 0000 unimp + 1a66: 1778 addi a4,sp,940 + 1a68: 0afc addi a5,sp,348 + 1a6a: 0000 unimp + 1a6c: 9104 0x9104 + 1a6e: 1002 c.slli zero,0x20 + 1a70: 0000081b 0x81b + 1a74: 1780 addi s0,sp,992 + 1a76: 00000803 lb a6,0(zero) # 0 <_start-0x80000000> + 1a7a: 9204 0x9204 + 1a7c: 1002 c.slli zero,0x20 + 1a7e: 0000082b 0x82b + 1a82: 1788 addi a0,sp,992 + 1a84: 05ed addi a1,a1,27 + 1a86: 0000 unimp + 1a88: 9304 0x9304 + 1a8a: 0f02 c.slli64 t5 + 1a8c: 0025 c.nop 9 + 1a8e: 0000 unimp + 1a90: 17a0 addi s0,sp,1000 + 1a92: 0758 addi a4,sp,900 + 1a94: 0000 unimp + 1a96: 9404 0x9404 + 1a98: 1602 slli a2,a2,0x20 + 1a9a: 00f9 addi ra,ra,30 + 1a9c: 0000 unimp + 1a9e: 17a4 addi s1,sp,1000 + 1aa0: 0000066f jal a2,1aa0 <_start-0x7fffe560> + 1aa4: 9504 0x9504 + 1aa6: 1602 slli a2,a2,0x20 + 1aa8: 00f9 addi ra,ra,30 + 1aaa: 0000 unimp + 1aac: 17ac addi a1,sp,1000 + 1aae: 00000747 fmsub.s fa4,ft0,ft0,ft0,rne + 1ab2: 9604 0x9604 + 1ab4: 1602 slli a2,a2,0x20 + 1ab6: 00f9 addi ra,ra,30 + 1ab8: 0000 unimp + 1aba: 17b4 addi a3,sp,1000 + 1abc: 0600 addi s0,sp,768 + 1abe: 0000 unimp + 1ac0: 9704 0x9704 + 1ac2: 1602 slli a2,a2,0x20 + 1ac4: 00f9 addi ra,ra,30 + 1ac6: 0000 unimp + 1ac8: 17bc addi a5,sp,1000 + 1aca: 062c addi a1,sp,776 + 1acc: 0000 unimp + 1ace: 9804 0x9804 + 1ad0: 1602 slli a2,a2,0x20 + 1ad2: 00f9 addi ra,ra,30 + 1ad4: 0000 unimp + 1ad6: 17c4 addi s1,sp,996 + 1ad8: 098a slli s3,s3,0x2 + 1ada: 0000 unimp + 1adc: 9904 0x9904 + 1ade: 0802 c.slli64 a6 + 1ae0: 0025 c.nop 9 + 1ae2: 0000 unimp + 1ae4: 00cc addi a1,sp,68 + 1ae6: bc08 fsd fa0,56(s0) + 1ae8: 0005 c.nop 1 + 1aea: 1b00 addi s0,sp,432 + 1aec: 0008 0x8 + 1aee: 0900 addi s0,sp,144 + 1af0: 002c addi a1,sp,8 + 1af2: 0000 unimp + 1af4: 0019 c.nop 6 + 1af6: bc08 fsd fa0,56(s0) + 1af8: 0005 c.nop 1 + 1afa: 2b00 fld fs0,16(a4) + 1afc: 0008 0x8 + 1afe: 0900 addi s0,sp,144 + 1b00: 002c addi a1,sp,8 + 1b02: 0000 unimp + 1b04: bc080007 0xbc080007 + 1b08: 0005 c.nop 1 + 1b0a: 3b00 fld fs0,48(a4) + 1b0c: 0008 0x8 + 1b0e: 0900 addi s0,sp,144 + 1b10: 002c addi a1,sp,8 + 1b12: 0000 unimp + 1b14: f01a0017 auipc zero,0xf01a0 + 1b18: 9e04 0x9e04 + 1b1a: 0702 c.slli64 a4 + 1b1c: 0862 slli a6,a6,0x18 + 1b1e: 0000 unimp + 1b20: 0008bc17 auipc s8,0x8b + 1b24: 0400 addi s0,sp,512 + 1b26: 02a1 addi t0,t0,8 + 1b28: 0008621b 0x8621b + 1b2c: 0000 unimp + 1b2e: 0007a517 auipc a0,0x7a + 1b32: 0400 addi s0,sp,512 + 1b34: 02a2 slli t0,t0,0x8 + 1b36: 7218 flw fa4,32(a2) + 1b38: 0008 0x8 + 1b3a: 7800 flw fs0,48(s0) + 1b3c: 0800 addi s0,sp,16 + 1b3e: 000002fb 0x2fb + 1b42: 0872 slli a6,a6,0x1c + 1b44: 0000 unimp + 1b46: 2c09 jal 1d58 <_start-0x7fffe2a8> + 1b48: 0000 unimp + 1b4a: 1d00 addi s0,sp,688 + 1b4c: 0800 addi s0,sp,16 + 1b4e: 002c addi a1,sp,8 + 1b50: 0000 unimp + 1b52: 0882 c.slli64 a7 + 1b54: 0000 unimp + 1b56: 2c09 jal 1d68 <_start-0x7fffe298> + 1b58: 0000 unimp + 1b5a: 1d00 addi s0,sp,688 + 1b5c: 1b00 addi s0,sp,432 + 1b5e: 04f0 addi a2,sp,588 + 1b60: a7030283 lb t0,-1424(t1) + 1b64: 0008 0x8 + 1b66: 1c00 addi s0,sp,560 + 1b68: 0a36 slli s4,s4,0xd + 1b6a: 0000 unimp + 1b6c: 9a04 0x9a04 + 1b6e: 0b02 c.slli64 s6 + 1b70: 06f6 slli a3,a3,0x1d + 1b72: 0000 unimp + 1b74: 251c fld fa5,8(a0) + 1b76: 0400000b 0x400000b + 1b7a: 3b0b02a3 sb a6,933(s6) # 2513a5 <_start-0x7fdaec5b> + 1b7e: 0008 0x8 + 1b80: 0000 unimp + 1b82: bc08 fsd fa0,56(s0) + 1b84: 0005 c.nop 1 + 1b86: b700 fsd fs0,40(a4) + 1b88: 0008 0x8 + 1b8a: 0900 addi s0,sp,144 + 1b8c: 002c addi a1,sp,8 + 1b8e: 0000 unimp + 1b90: 0018 0x18 + 1b92: 641d lui s0,0x7 + 1b94: 0006 c.slli zero,0x1 + 1b96: 0f00 addi s0,sp,912 + 1b98: b704 fsd fs1,40(a4) + 1b9a: 0008 0x8 + 1b9c: 1e00 addi s0,sp,816 + 1b9e: 08cd addi a7,a7,19 + 1ba0: 0000 unimp + 1ba2: 6214 flw fa3,0(a2) + 1ba4: 0004 0x4 + 1ba6: 0000 unimp + 1ba8: 08c2040f 0x8c2040f + 1bac: 0000 unimp + 1bae: 0185040f 0x185040f + 1bb2: 0000 unimp + 1bb4: e41e fsw ft7,8(sp) + 1bb6: 0008 0x8 + 1bb8: 1400 addi s0,sp,544 + 1bba: 0025 c.nop 9 + 1bbc: 0000 unimp + 1bbe: 0f00 addi s0,sp,912 + 1bc0: ea04 fsw fs1,16(a2) + 1bc2: 0008 0x8 + 1bc4: 0f00 addi s0,sp,912 + 1bc6: d904 sw s1,48(a0) + 1bc8: 0008 0x8 + 1bca: 0800 addi s0,sp,16 + 1bcc: 0000065b 0x65b + 1bd0: 0900 addi s0,sp,144 + 1bd2: 0000 unimp + 1bd4: 2c09 jal 1de6 <_start-0x7fffe21a> + 1bd6: 0000 unimp + 1bd8: 0200 addi s0,sp,256 + 1bda: 1f00 addi s0,sp,944 + 1bdc: 0ac8 addi a0,sp,340 + 1bde: 0000 unimp + 1be0: 3304 fld fs1,32(a4) + 1be2: 04621703 lh a4,70(tp) # ffffd046 <__global_pointer$+0x7fff93de> + 1be6: 0000 unimp + 1be8: c11f 000a 0400 0x400000ac11f + 1bee: 0334 addi a3,sp,392 + 1bf0: 681d lui a6,0x7 + 1bf2: 0004 0x4 + 1bf4: 0800 addi s0,sp,16 + 1bf6: 05f2 slli a1,a1,0x1c + 1bf8: 0000 unimp + 1bfa: 0925 addi s2,s2,9 + 1bfc: 0000 unimp + 1bfe: 0020 addi s0,sp,8 + 1c00: 1a15 addi s4,s4,-27 + 1c02: 0009 c.nop 2 + 1c04: 2100 fld fs0,0(a0) + 1c06: 0732 slli a4,a4,0xc + 1c08: 0000 unimp + 1c0a: 1406 slli s0,s0,0x21 + 1c0c: 2524 fld fs1,72(a0) + 1c0e: 0009 c.nop 2 + 1c10: 2100 fld fs0,0(a0) + 1c12: 000009d7 0x9d7 + 1c16: 1506 slli a0,a0,0x21 + 1c18: 2515 jal 223c <_start-0x7fffddc4> + 1c1a: 0000 unimp + 1c1c: 0f00 addi s0,sp,912 + 1c1e: 4804 lw s1,16(s0) + 1c20: 0009 c.nop 2 + 1c22: 1300 addi s0,sp,416 + 1c24: 0025 c.nop 9 + 1c26: 0000 unimp + 1c28: 095c addi a5,sp,148 + 1c2a: 0000 unimp + 1c2c: 5c14 lw a3,56(s0) + 1c2e: 0009 c.nop 2 + 1c30: 1400 addi s0,sp,544 + 1c32: 095c addi a5,sp,148 + 1c34: 0000 unimp + 1c36: 0f00 addi s0,sp,912 + 1c38: 6204 flw fs1,0(a2) + 1c3a: 0009 c.nop 2 + 1c3c: 2200 fld fs0,0(a2) + 1c3e: e221 bnez a2,1c7e <_start-0x7fffe382> + 1c40: 0008 0x8 + 1c42: 0700 addi s0,sp,896 + 1c44: 05b60e67 jalr t3,91(a2) + 1c48: 0000 unimp + 1c4a: 2a21 jal 1d62 <_start-0x7fffe29e> + 1c4c: 0008 0x8 + 1c4e: 0800 addi s0,sp,16 + 1c50: 0f10 addi a2,sp,912 + 1c52: 0000097b 0x97b + 1c56: 05b6040f 0x5b6040f + 1c5a: 0000 unimp + 1c5c: e521 bnez a0,1ca4 <_start-0x7fffe35c> + 1c5e: 0008 0x8 + 1c60: 0800 addi s0,sp,16 + 1c62: 0efc addi a5,sp,860 + 1c64: 05b6 slli a1,a1,0xd + 1c66: 0000 unimp + 1c68: b521 j 1a70 <_start-0x7fffe590> + 1c6a: 0008 0x8 + 1c6c: 0800 addi s0,sp,16 + 1c6e: 0cfd addi s9,s9,31 + 1c70: 0025 c.nop 9 + 1c72: 0000 unimp + 1c74: 7b21 lui s6,0xfffe8 + 1c76: 000a c.slli zero,0x2 + 1c78: 0800 addi s0,sp,16 + 1c7a: 14fd addi s1,s1,-1 + 1c7c: 0025 c.nop 9 + 1c7e: 0000 unimp + 1c80: 5f21 li t5,-24 + 1c82: 0800000b 0x800000b + 1c86: 1cfd addi s9,s9,-1 + 1c88: 0025 c.nop 9 + 1c8a: 0000 unimp + 1c8c: 6a21 lui s4,0x8 + 1c8e: 0008 0x8 + 1c90: 0800 addi s0,sp,16 + 1c92: 0cff 0xcff + 1c94: 0025 c.nop 9 + 1c96: 0000 unimp + 1c98: 0821 addi a6,a6,8 + 1c9a: 0009 c.nop 2 + 1c9c: 0900 addi s0,sp,144 + 1c9e: 169a slli a3,a3,0x26 + 1ca0: 005d c.nop 23 + 1ca2: 0000 unimp + 1ca4: d421 beqz s0,1bec <_start-0x7fffe414> + 1ca6: 0005 c.nop 1 + 1ca8: 0900 addi s0,sp,144 + 1caa: 0025159b 0x25159b + 1cae: 0000 unimp + 1cb0: b608 fsd fa0,40(a2) + 1cb2: 0005 c.nop 1 + 1cb4: e500 fsw fs0,8(a0) + 1cb6: 0009 c.nop 2 + 1cb8: 0900 addi s0,sp,144 + 1cba: 002c addi a1,sp,8 + 1cbc: 0000 unimp + 1cbe: 0001 nop + 1cc0: 7e21 lui t3,0xfffe8 + 1cc2: 0006 c.slli zero,0x1 + 1cc4: 0900 addi s0,sp,144 + 1cc6: 179e slli a5,a5,0x27 + 1cc8: 09d5 addi s3,s3,21 + 1cca: 0000 unimp + 1ccc: e005 bnez s0,1cec <_start-0x7fffe314> + 1cce: 0a000007 0xa000007 + 1cd2: 162a slli a2,a2,0x2a + 1cd4: 002c addi a1,sp,8 + 1cd6: 0000 unimp + 1cd8: c505 beqz a0,1d00 <_start-0x7fffe300> + 1cda: 0009 c.nop 2 + 1cdc: 0a00 addi s0,sp,272 + 1cde: 0a09152f 0xa09152f + 1ce2: 0000 unimp + 1ce4: 0a0f040f 0xa0f040f + 1ce8: 0000 unimp + 1cea: 0009f113 andi sp,s3,0 + 1cee: 1e00 addi s0,sp,816 + 1cf0: 000a c.slli zero,0x2 + 1cf2: 1400 addi s0,sp,544 + 1cf4: 095c addi a5,sp,148 + 1cf6: 0000 unimp + 1cf8: 0500 addi s0,sp,640 + 1cfa: 0b8d addi s7,s7,3 + 1cfc: 0000 unimp + 1cfe: 360a fld fa2,160(sp) + 1d00: 0009420f 0x9420f + 1d04: 2100 fld fs0,0(a0) + 1d06: 05a9 addi a1,a1,10 + 1d08: 0000 unimp + 1d0a: bb0a fsd ft2,432(sp) + 1d0c: fd12 fsw ft4,184(sp) + 1d0e: 0009 c.nop 2 + 1d10: 2100 fld fs0,0(a0) + 1d12: 0aac addi a1,sp,344 + 1d14: 0000 unimp + 1d16: be0a fsd ft2,312(sp) + 1d18: 1e10 addi a2,sp,816 + 1d1a: 000a c.slli zero,0x2 + 1d1c: 2300 fld fs0,0(a4) + 1d1e: 000007b3 add a5,zero,zero + 1d22: 002c0407 0x2c0407 + 1d26: 0000 unimp + 1d28: 7f06180b 0x7f06180b + 1d2c: 000a c.slli zero,0x2 + 1d2e: 2400 fld fs0,8(s0) + 1d30: 0965 addi s2,s2,25 + 1d32: 0000 unimp + 1d34: 2400 fld fs0,8(s0) + 1d36: 084a slli a6,a6,0x12 + 1d38: 0000 unimp + 1d3a: 2401 jal 1f3a <_start-0x7fffe0c6> + 1d3c: 0884 addi s1,sp,80 + 1d3e: 0000 unimp + 1d40: 2402 fld fs0,0(sp) + 1d42: 0000083f 095c2403 0x95c24030000083f + 1d4a: 0000 unimp + 1d4c: 2404 fld fs1,8(s0) + 1d4e: 0b66 slli s6,s6,0x19 + 1d50: 0000 unimp + 1d52: 2405 jal 1f72 <_start-0x7fffe08e> + 1d54: 0b55 addi s6,s6,21 + 1d56: 0000 unimp + 1d58: 0006 c.slli zero,0x1 + 1d5a: 5a21 li s4,-24 + 1d5c: 0006 c.slli zero,0x1 + 1d5e: 0b00 addi s0,sp,400 + 1d60: 1c21 addi s8,s8,-24 + 1d62: 0a42 slli s4,s4,0x10 + 1d64: 0000 unimp + 1d66: 00089c23 sh zero,24(a7) + 1d6a: 0700 addi s0,sp,896 + 1d6c: 2c04 fld fs1,24(s0) + 1d6e: 0000 unimp + 1d70: 0b00 addi s0,sp,400 + 1d72: 0ab00623 sb a1,172(zero) # ac <_start-0x7fffff54> + 1d76: 0000 unimp + 1d78: bb24 fsd fs1,112(a4) + 1d7a: 0009 c.nop 2 + 1d7c: 0000 unimp + 1d7e: 7b24 flw fs1,112(a4) + 1d80: 0009 c.nop 2 + 1d82: 0100 addi s0,sp,128 + 1d84: 8f24 0x8f24 + 1d86: 000a c.slli zero,0x2 + 1d88: 0200 addi s0,sp,256 + 1d8a: 2100 fld fs0,0(a0) + 1d8c: 0766 slli a4,a4,0x19 + 1d8e: 0000 unimp + 1d90: 8b1e280b 0x8b1e280b + 1d94: 000a c.slli zero,0x2 + 1d96: 2300 fld fs0,0(a4) + 1d98: 0000060f 0x60f + 1d9c: 002c0407 0x2c0407 + 1da0: 0000 unimp + 1da2: db062b0b 0xdb062b0b + 1da6: 000a c.slli zero,0x2 + 1da8: 2400 fld fs0,8(s0) + 1daa: 00000a73 0xa73 + 1dae: 2400 fld fs0,8(s0) + 1db0: 0a61 addi s4,s4,24 + 1db2: 0000 unimp + 1db4: 0001 nop + 1db6: 1a21 addi s4,s4,-24 + 1db8: 0b000007 0xb000007 + 1dbc: 0abc2a2f amoswap.w.rl s4,a1,(s8) + 1dc0: 0000 unimp + 1dc2: 5b21 li s6,-24 + 1dc4: 0008 0x8 + 1dc6: 0c00 addi s0,sp,528 + 1dc8: 1a29 addi s4,s4,-22 + 1dca: 0925 addi s2,s2,9 + 1dcc: 0000 unimp + 1dce: ba21 j 16e6 <_start-0x7fffe91a> + 1dd0: 0006 c.slli zero,0x1 + 1dd2: 0c00 addi s0,sp,528 + 1dd4: 1a38 addi a4,sp,312 + 1dd6: 0925 addi s2,s2,9 + 1dd8: 0000 unimp + 1dda: c805 beqz s0,1e0a <_start-0x7fffe1f6> + 1ddc: 0000 unimp + 1dde: 0d00 addi s0,sp,656 + 1de0: 0048167b 0x48167b + 1de4: 0000 unimp + 1de6: ff15 bnez a4,1d22 <_start-0x7fffe2de> + 1de8: 000a c.slli zero,0x2 + 1dea: 0500 addi s0,sp,640 + 1dec: 00000713 li a4,0 + 1df0: 800d srli s0,s0,0x3 + 1df2: 0000250f 0x250f + 1df6: 0500 addi s0,sp,640 + 1df8: 0712 slli a4,a4,0x4 + 1dfa: 0000 unimp + 1dfc: 810d srli a0,a0,0x3 + 1dfe: 2c16 fld fs8,320(sp) + 1e00: 0000 unimp + 1e02: 0300 addi s0,sp,384 + 1e04: 0404 addi s1,sp,512 + 1e06: 000008cb fnmsub.s fa7,ft0,ft0,ft0,rne + 1e0a: c3030803 lb a6,-976(t1) + 1e0e: 0008 0x8 + 1e10: 0300 addi s0,sp,384 + 1e12: 0408 addi a0,sp,512 + 1e14: 00000653 fadd.s fa2,ft0,ft0,rne + 1e18: de031003 lh zero,-544(t1) + 1e1c: 0005 c.nop 1 + 1e1e: 0300 addi s0,sp,384 + 1e20: 0320 addi s0,sp,392 + 1e22: 0646 slli a2,a2,0x11 + 1e24: 0000 unimp + 1e26: 0b08 addi a0,sp,400 + 1e28: 5b00000b 0x5b00000b + 1e2c: 0900000b 0x900000b + 1e30: 002c addi a1,sp,8 + 1e32: 0000 unimp + 1e34: 00ff 0xff + 1e36: 4b15 li s6,5 + 1e38: 1f00000b 0x1f00000b + 1e3c: 0b10 addi a2,sp,400 + 1e3e: 0000 unimp + 1e40: fc0d bnez s0,1d7a <_start-0x7fffe286> + 1e42: 1601 addi a2,a2,-32 + 1e44: 00000b5b 0xb5b + 1e48: d01f 0000 0d00 0xd000000d01f + 1e4e: 0202 c.slli64 tp + 1e50: 5b16 lw s6,100(sp) + 1e52: 2500000b 0x2500000b + 1e56: 07f1 addi a5,a5,28 + 1e58: 0000 unimp + 1e5a: c201 beqz a2,1e5a <_start-0x7fffe1a6> + 1e5c: 0102 c.slli64 sp + 1e5e: 0025 c.nop 9 + 1e60: 0000 unimp + 1e62: 1e7c addi a5,sp,828 + 1e64: 8000 0x8000 + 1e66: 004c addi a1,sp,4 + 1e68: 0000 unimp + 1e6a: 9c01 0x9c01 + 1e6c: 7826 flw fa6,104(sp) + 1e6e: 0100 addi s0,sp,128 + 1e70: 02c2 slli t0,t0,0x10 + 1e72: 1c12 slli s8,s8,0x24 + 1e74: 5a00000b 0x5a00000b + 1e78: 0025 c.nop 9 + 1e7a: 2700 fld fs0,8(a4) + 1e7c: 6572 flw fa0,28(sp) + 1e7e: 0074 addi a3,sp,12 + 1e80: c401 beqz s0,1e88 <_start-0x7fffe178> + 1e82: 0902 c.slli64 s2 + 1e84: 0b10 addi a2,sp,400 + 1e86: 0000 unimp + 1e88: 7028 flw fa0,96(s0) + 1e8a: 0004 0x4 + 1e8c: 2900 fld fs0,16(a0) + 1e8e: 0abc addi a5,sp,344 + 1e90: 0000 unimp + 1e92: c601 beqz a2,1e9a <_start-0x7fffe166> + 1e94: 0302 c.slli64 t1 + 1e96: 0b1c addi a5,sp,400 + 1e98: 0000 unimp + 1e9a: 2586 fld fa1,64(sp) + 1e9c: 0000 unimp + 1e9e: 5f2a lw t5,168(sp) + 1ea0: 615f 0100 02c6 0x2c60100615f + 1ea6: 000b1c03 lh s8,0(s6) # fffe8000 <__global_pointer$+0x7ffe4398> + 1eaa: b200 fsd fs0,32(a2) + 1eac: 0025 c.nop 9 + 1eae: 0000 unimp + 1eb0: 0000 unimp + 1eb2: 0b66 slli s6,s6,0x19 + 1eb4: 0000 unimp + 1eb6: 0004 0x4 + 1eb8: 00000b3b 0xb3b + 1ebc: 0104 addi s1,sp,128 + 1ebe: 0182 c.slli64 gp + 1ec0: 0000 unimp + 1ec2: 350c fld fa1,40(a0) + 1ec4: 0009 c.nop 2 + 1ec6: f600 fsw fs0,40(a2) + 1ec8: 0000 unimp + 1eca: 9e00 0x9e00 + 1ecc: 002c addi a1,sp,8 + 1ece: 0200 addi s0,sp,256 + 1ed0: 0504 addi s1,sp,640 + 1ed2: 6e69 lui t3,0x1a + 1ed4: 0074 addi a3,sp,12 + 1ed6: e9070403 lb s0,-368(a4) + 1eda: 0000 unimp + 1edc: 0300 addi s0,sp,384 + 1ede: 0508 addi a0,sp,640 + 1ee0: 0174 addi a3,sp,140 + 1ee2: 0000 unimp + 1ee4: 4e041003 lh zero,1248(s0) # 74e0 <_start-0x7fff8b20> + 1ee8: 0006 c.slli zero,0x1 + 1eea: 0300 addi s0,sp,384 + 1eec: 0601 addi a2,a2,0 + 1eee: 0062 c.slli zero,0x18 + 1ef0: 0000 unimp + 1ef2: 60080103 lb sp,1536(a6) # 7600 <_start-0x7fff8a00> + 1ef6: 0000 unimp + 1ef8: 0300 addi s0,sp,384 + 1efa: 0502 c.slli64 a0 + 1efc: 059f 0000 0203 0x2030000059f + 1f02: 00008c07 0x8c07 + 1f06: 0300 addi s0,sp,384 + 1f08: 0504 addi s1,sp,640 + 1f0a: 0179 addi sp,sp,30 + 1f0c: 0000 unimp + 1f0e: e4070403 lb s0,-448(a4) + 1f12: 0000 unimp + 1f14: 0300 addi s0,sp,384 + 1f16: 0708 addi a0,sp,896 + 1f18: 00df 0000 3204 0x3204000000df + 1f1e: 0008 0x8 + 1f20: 0100 addi s0,sp,128 + 1f22: 015e slli sp,sp,0x17 + 1f24: 00002417 auipc s0,0x2 + 1f28: 0500 addi s0,sp,640 + 1f2a: 000008f7 0x8f7 + 1f2e: 2e02 fld ft8,0(sp) + 1f30: 550e lw a0,224(sp) + 1f32: 0000 unimp + 1f34: 0500 addi s0,sp,640 + 1f36: 0a59 addi s4,s4,22 + 1f38: 0000 unimp + 1f3a: 7402 flw fs0,32(sp) + 1f3c: 550e lw a0,224(sp) + 1f3e: 0000 unimp + 1f40: 0500 addi s0,sp,640 + 1f42: 00000af3 0xaf3 + 1f46: 9302 jalr t1 + 1f48: 00001d17 auipc s10,0x1 + 1f4c: 0600 addi s0,sp,768 + 1f4e: 0204 addi s1,sp,256 + 1f50: 03a5 addi t2,t2,9 + 1f52: 00bd addi ra,ra,15 + 1f54: 0000 unimp + 1f56: 00082407 flw fs0,0(a6) + 1f5a: 0200 addi s0,sp,256 + 1f5c: 006a0ca7 0x6a0ca7 + 1f60: 0000 unimp + 1f62: 0007cb07 flq fs6,0(a5) + 1f66: 0200 addi s0,sp,256 + 1f68: 13a8 addi a0,sp,488 + 1f6a: 00bd addi ra,ra,15 + 1f6c: 0000 unimp + 1f6e: 0800 addi s0,sp,16 + 1f70: 0040 addi s0,sp,4 + 1f72: 0000 unimp + 1f74: 00cd addi ra,ra,19 + 1f76: 0000 unimp + 1f78: 2409 jal 217a <_start-0x7fffde86> + 1f7a: 0000 unimp + 1f7c: 0300 addi s0,sp,384 + 1f7e: 0a00 addi s0,sp,272 + 1f80: 0208 addi a0,sp,256 + 1f82: 09a2 slli s3,s3,0x8 + 1f84: 00f1 addi ra,ra,28 + 1f86: 0000 unimp + 1f88: 000a430b 0xa430b + 1f8c: 0200 addi s0,sp,256 + 1f8e: 07a4 addi s1,sp,968 + 1f90: 001d c.nop 7 + 1f92: 0000 unimp + 1f94: 0b00 addi s0,sp,400 + 1f96: 00000a4b fnmsub.s fs4,ft0,ft0,ft0,rne + 1f9a: a902 fsd ft0,144(sp) + 1f9c: 9b05 andi a4,a4,-31 + 1f9e: 0000 unimp + 1fa0: 0400 addi s0,sp,512 + 1fa2: 0500 addi s0,sp,640 + 1fa4: 0912 slli s2,s2,0x4 + 1fa6: 0000 unimp + 1fa8: aa02 fsd ft0,272(sp) + 1faa: 0000cd03 lbu s10,0(ra) # 18aa <_start-0x7fffe756> + 1fae: 0c00 addi s0,sp,528 + 1fb0: 0504 addi s1,sp,640 + 1fb2: 0aa4 addi s1,sp,344 + 1fb4: 0000 unimp + 1fb6: 5c191603 lh a2,1473(s2) # 15c1 <_start-0x7fffea3f> + 1fba: 0000 unimp + 1fbc: 0500 addi s0,sp,640 + 1fbe: 091d addi s2,s2,7 + 1fc0: 0000 unimp + 1fc2: 0c04 addi s1,sp,528 + 1fc4: 1d0d addi s10,s10,-29 + 1fc6: 0000 unimp + 1fc8: 0500 addi s0,sp,640 + 1fca: 00000993 li s3,0 + 1fce: 0b1b2303 lw t1,177(s6) + 1fd2: 0001 nop + 1fd4: 0d00 addi s0,sp,656 + 1fd6: 078e slli a5,a5,0x3 + 1fd8: 0000 unimp + 1fda: 0318 addi a4,sp,384 + 1fdc: 0834 addi a3,sp,24 + 1fde: 017d addi sp,sp,31 + 1fe0: 0000 unimp + 1fe2: 0009e60b 0x9e60b + 1fe6: 0300 addi s0,sp,384 + 1fe8: 1336 slli t1,t1,0x2d + 1fea: 017d addi sp,sp,31 + 1fec: 0000 unimp + 1fee: 0e00 addi s0,sp,784 + 1ff0: 6b5f 0300 0737 0x73703006b5f + 1ff6: 001d c.nop 7 + 1ff8: 0000 unimp + 1ffa: 0b04 addi s1,sp,400 + 1ffc: 0a2e slli s4,s4,0xb + 1ffe: 0000 unimp + 2000: 1d0b3703 0x1d0b3703 + 2004: 0000 unimp + 2006: 0800 addi s0,sp,16 + 2008: 0007800b 0x7800b + 200c: 0300 addi s0,sp,384 + 200e: 001d1437 lui s0,0x1d1 + 2012: 0000 unimp + 2014: 0b0c addi a1,sp,400 + 2016: 06fc addi a5,sp,844 + 2018: 0000 unimp + 201a: 1d1b3703 0x1d1b3703 + 201e: 0000 unimp + 2020: 1000 addi s0,sp,32 + 2022: 5f0e lw t5,224(sp) + 2024: 0078 addi a4,sp,12 + 2026: 830b3803 0x830b3803 + 202a: 0001 nop + 202c: 1400 addi s0,sp,544 + 202e: 0f00 addi s0,sp,912 + 2030: 2304 fld fs1,0(a4) + 2032: 0001 nop + 2034: 0800 addi s0,sp,16 + 2036: 00ff 0xff + 2038: 0000 unimp + 203a: 00000193 li gp,0 + 203e: 2409 jal 2240 <_start-0x7fffddc0> + 2040: 0000 unimp + 2042: 0000 unimp + 2044: 0d00 addi s0,sp,656 + 2046: 07ae slli a5,a5,0xb + 2048: 0000 unimp + 204a: 0324 addi s1,sp,392 + 204c: 083c addi a5,sp,24 + 204e: 0216 slli tp,tp,0x5 + 2050: 0000 unimp + 2052: 0006940b 0x6940b + 2056: 0300 addi s0,sp,384 + 2058: 093e slli s2,s2,0xf + 205a: 001d c.nop 7 + 205c: 0000 unimp + 205e: 0b00 addi s0,sp,400 + 2060: 00000b47 fmsub.s fs6,ft0,ft0,ft0,rne + 2064: 1d093f03 0x1d093f03 + 2068: 0000 unimp + 206a: 0400 addi s0,sp,512 + 206c: 0006b00b 0x6b00b + 2070: 0300 addi s0,sp,384 + 2072: 0940 addi s0,sp,148 + 2074: 001d c.nop 7 + 2076: 0000 unimp + 2078: 0b08 addi a0,sp,400 + 207a: 00000b83 lb s7,0(zero) # 0 <_start-0x80000000> + 207e: 1d094103 lbu sp,464(s2) + 2082: 0000 unimp + 2084: 0c00 addi s0,sp,528 + 2086: 0008d10b 0x8d10b + 208a: 0300 addi s0,sp,384 + 208c: 0942 slli s2,s2,0x10 + 208e: 001d c.nop 7 + 2090: 0000 unimp + 2092: 0b10 addi a2,sp,400 + 2094: 087a slli a6,a6,0x1e + 2096: 0000 unimp + 2098: 1d094303 lbu t1,464(s2) + 209c: 0000 unimp + 209e: 1400 addi s0,sp,544 + 20a0: 000adc0b 0xadc0b + 20a4: 0300 addi s0,sp,384 + 20a6: 0944 addi s1,sp,148 + 20a8: 001d c.nop 7 + 20aa: 0000 unimp + 20ac: 0b18 addi a4,sp,400 + 20ae: 099c addi a5,sp,208 + 20b0: 0000 unimp + 20b2: 1d094503 lbu a0,464(s2) + 20b6: 0000 unimp + 20b8: 1c00 addi s0,sp,560 + 20ba: 000b2d0b 0xb2d0b + 20be: 0300 addi s0,sp,384 + 20c0: 0946 slli s2,s2,0x11 + 20c2: 001d c.nop 7 + 20c4: 0000 unimp + 20c6: 0020 addi s0,sp,8 + 20c8: cf10 sw a2,24(a4) + 20ca: 0006 c.slli zero,0x1 + 20cc: 0800 addi s0,sp,16 + 20ce: 0301 addi t1,t1,0 + 20d0: 025b084f fnmadd.d fa6,fs6,ft5,ft0,rne + 20d4: 0000 unimp + 20d6: 0007730b 0x7730b + 20da: 0300 addi s0,sp,384 + 20dc: 0a50 addi a2,sp,276 + 20de: 0000025b 0x25b + 20e2: 0b00 addi s0,sp,400 + 20e4: 0000096f jal s2,20e4 <_start-0x7fffdf1c> + 20e8: 5b095103 lhu sp,1456(s2) + 20ec: 0002 c.slli64 zero + 20ee: 8000 0x8000 + 20f0: 9611 srai a2,a2,0x24 + 20f2: 000a c.slli zero,0x2 + 20f4: 0300 addi s0,sp,384 + 20f6: 00ff0a53 fadd.s fs4,ft10,fa5,rne + 20fa: 0000 unimp + 20fc: 0100 addi s0,sp,128 + 20fe: f411 bnez s0,200a <_start-0x7fffdff6> + 2100: 0006 c.slli zero,0x1 + 2102: 0300 addi s0,sp,384 + 2104: 0a56 slli s4,s4,0x15 + 2106: 00ff 0xff + 2108: 0000 unimp + 210a: 0104 addi s1,sp,128 + 210c: 0800 addi s0,sp,16 + 210e: 00fd addi ra,ra,31 + 2110: 0000 unimp + 2112: 0000026b 0x26b + 2116: 2409 jal 2318 <_start-0x7fffdce8> + 2118: 0000 unimp + 211a: 1f00 addi s0,sp,944 + 211c: 1000 addi s0,sp,32 + 211e: 08da slli a7,a7,0x16 + 2120: 0000 unimp + 2122: 0190 addi a2,sp,192 + 2124: ae086203 0xae086203 + 2128: 0002 c.slli64 zero + 212a: 0b00 addi s0,sp,400 + 212c: 09e6 slli s3,s3,0x19 + 212e: 0000 unimp + 2130: ae126303 0xae126303 + 2134: 0002 c.slli64 zero + 2136: 0000 unimp + 2138: 0009fe0b 0x9fe0b + 213c: 0300 addi s0,sp,384 + 213e: 0664 addi s1,sp,780 + 2140: 001d c.nop 7 + 2142: 0000 unimp + 2144: 0b04 addi s1,sp,400 + 2146: 0000077b 0x77b + 214a: b4096603 0xb4096603 + 214e: 0002 c.slli64 zero + 2150: 0800 addi s0,sp,16 + 2152: 0006cf0b 0x6cf0b + 2156: 0300 addi s0,sp,384 + 2158: 02161e67 0x2161e67 + 215c: 0000 unimp + 215e: 0088 addi a0,sp,64 + 2160: 026b040f 0x26b040f + 2164: 0000 unimp + 2166: c408 sw a0,8(s0) + 2168: 0002 c.slli64 zero + 216a: c400 sw s0,8(s0) + 216c: 0002 c.slli64 zero + 216e: 0900 addi s0,sp,144 + 2170: 0024 addi s1,sp,8 + 2172: 0000 unimp + 2174: 001f 040f 02ca 0x2ca040f001f + 217a: 0000 unimp + 217c: 0d12 slli s10,s10,0x4 + 217e: 09a6 slli s3,s3,0x9 + 2180: 0000 unimp + 2182: 0308 addi a0,sp,384 + 2184: 087a slli a6,a6,0x1e + 2186: 000002f3 0x2f3 + 218a: 0006aa0b 0x6aa0b + 218e: 0300 addi s0,sp,384 + 2190: 02f3117b 0x2f3117b + 2194: 0000 unimp + 2196: 0b00 addi s0,sp,400 + 2198: 000005bb 0x5bb + 219c: 1d067c03 0x1d067c03 + 21a0: 0000 unimp + 21a2: 0400 addi s0,sp,512 + 21a4: 0f00 addi s0,sp,912 + 21a6: 4004 lw s1,0(s0) + 21a8: 0000 unimp + 21aa: 0d00 addi s0,sp,656 + 21ac: 000009cf fnmadd.s fs3,ft0,ft0,ft0,rne + 21b0: 0368 addi a0,sp,396 + 21b2: 08ba slli a7,a7,0xe + 21b4: 043c addi a5,sp,520 + 21b6: 0000 unimp + 21b8: 5f0e lw t5,224(sp) + 21ba: 0070 addi a2,sp,12 + 21bc: f312bb03 0xf312bb03 + 21c0: 0002 c.slli64 zero + 21c2: 0000 unimp + 21c4: 5f0e lw t5,224(sp) + 21c6: 0072 c.slli zero,0x1c + 21c8: 1d07bc03 0x1d07bc03 + 21cc: 0000 unimp + 21ce: 0400 addi s0,sp,512 + 21d0: 5f0e lw t5,224(sp) + 21d2: bd030077 0xbd030077 + 21d6: 00001d07 0x1d07 + 21da: 0800 addi s0,sp,16 + 21dc: 0006ed0b 0x6ed0b + 21e0: 0300 addi s0,sp,384 + 21e2: 09be slli s3,s3,0xf + 21e4: 00000047 fmsub.s ft0,ft0,ft0,ft0,rne + 21e8: 0b0c addi a1,sp,400 + 21ea: 07da slli a5,a5,0x16 + 21ec: 0000 unimp + 21ee: 4709bf03 0x4709bf03 + 21f2: 0000 unimp + 21f4: 0e00 addi s0,sp,784 + 21f6: 5f0e lw t5,224(sp) + 21f8: 6662 flw fa2,24(sp) + 21fa: 0300 addi s0,sp,384 + 21fc: 11c0 addi s0,sp,228 + 21fe: 000002cb fnmsub.s ft5,ft0,ft0,ft0,rne + 2202: 0b10 addi a2,sp,400 + 2204: 063d addi a2,a2,15 + 2206: 0000 unimp + 2208: 1d07c103 lbu sp,464(a5) + 220c: 0000 unimp + 220e: 1800 addi s0,sp,48 + 2210: 0006dd0b 0x6dd0b + 2214: 0300 addi s0,sp,384 + 2216: 0ac8 addi a0,sp,340 + 2218: 00fd addi ra,ra,31 + 221a: 0000 unimp + 221c: 0b1c addi a5,sp,400 + 221e: 0000092f 0x92f + 2222: c01dca03 lbu s4,-1023(s11) + 2226: 0005 c.nop 1 + 2228: 2000 fld fs0,0(s0) + 222a: 0008730b 0x8730b + 222e: 0300 addi s0,sp,384 + 2230: 1dcc addi a1,sp,756 + 2232: 000005ef jal a1,2232 <_start-0x7fffddce> + 2236: 0b24 addi s1,sp,408 + 2238: 00000a53 fadd.s fs4,ft0,ft0,rne + 223c: 130dcf03 lbu t5,304(s11) + 2240: 0006 c.slli zero,0x1 + 2242: 2800 fld fs0,16(s0) + 2244: 00069d0b 0x69d0b + 2248: 0300 addi s0,sp,384 + 224a: 09d0 addi a2,sp,212 + 224c: 062d addi a2,a2,11 + 224e: 0000 unimp + 2250: 0e2c addi a1,sp,792 + 2252: 755f 0062 d303 0xd3030062755f + 2258: cb11 beqz a4,226c <_start-0x7fffdd94> + 225a: 0002 c.slli64 zero + 225c: 3000 fld fs0,32(s0) + 225e: 5f0e lw t5,224(sp) + 2260: 7075 c.lui zero,0xffffd + 2262: 0300 addi s0,sp,384 + 2264: 12d4 addi a3,sp,356 + 2266: 000002f3 0x2f3 + 226a: 0e38 addi a4,sp,792 + 226c: 755f 0072 d503 0xd5030072755f + 2272: 00001d07 0x1d07 + 2276: 3c00 fld fs0,56(s0) + 2278: 0006a40b 0x6a40b + 227c: 0300 addi s0,sp,384 + 227e: 11d8 addi a4,sp,228 + 2280: 00000633 add a2,zero,zero + 2284: 0b40 addi s0,sp,404 + 2286: 0b1f 0000 d903 0xd90300000b1f + 228c: 4311 li t1,4 + 228e: 0006 c.slli zero,0x1 + 2290: 4300 lw s0,0(a4) + 2292: 5f0e lw t5,224(sp) + 2294: 626c flw fa1,68(a2) + 2296: 0300 addi s0,sp,384 + 2298: 11dc addi a5,sp,228 + 229a: 000002cb fnmsub.s ft5,ft0,ft0,ft0,rne + 229e: 0b44 addi s1,sp,404 + 22a0: 0a6a slli s4,s4,0x1a + 22a2: 0000 unimp + 22a4: 1d07df03 lhu t5,464(a5) + 22a8: 0000 unimp + 22aa: 4c00 lw s0,24(s0) + 22ac: 0008ad0b 0x8ad0b + 22b0: 0300 addi s0,sp,384 + 22b2: 0ae0 addi s0,sp,348 + 22b4: 00000077 0x77 + 22b8: 0b50 addi a2,sp,404 + 22ba: 05fa slli a1,a1,0x1e + 22bc: 0000 unimp + 22be: 5a12e303 0x5a12e303 + 22c2: 0004 0x4 + 22c4: 5400 lw s0,40(s0) + 22c6: 0008390b 0x8390b + 22ca: 0300 addi s0,sp,384 + 22cc: 01170ce7 jalr s9,17(a4) + 22d0: 0000 unimp + 22d2: 0b58 addi a4,sp,404 + 22d4: 07c2 slli a5,a5,0x10 + 22d6: 0000 unimp + 22d8: f10ee903 0xf10ee903 + 22dc: 0000 unimp + 22de: 5c00 lw s0,56(s0) + 22e0: 0009ad0b 0x9ad0b + 22e4: 0300 addi s0,sp,384 + 22e6: 09ea slli s3,s3,0x1a + 22e8: 001d c.nop 7 + 22ea: 0000 unimp + 22ec: 0064 addi s1,sp,12 + 22ee: 00008f13 mv t5,ra + 22f2: 5a00 lw s0,48(a2) + 22f4: 0004 0x4 + 22f6: 1400 addi s0,sp,544 + 22f8: 045a slli s0,s0,0x16 + 22fa: 0000 unimp + 22fc: fd14 fsw fa3,56(a0) + 22fe: 0000 unimp + 2300: 1400 addi s0,sp,544 + 2302: 05ae slli a1,a1,0xb + 2304: 0000 unimp + 2306: 1d14 addi a3,sp,688 + 2308: 0000 unimp + 230a: 0000 unimp + 230c: 0465040f 0x465040f + 2310: 0000 unimp + 2312: 5a15 li s4,-27 + 2314: 0004 0x4 + 2316: 1600 addi s0,sp,800 + 2318: 0a36 slli s4,s4,0xd + 231a: 0000 unimp + 231c: 0428 addi a0,sp,520 + 231e: 08026503 0x8026503 + 2322: 05ae slli a1,a1,0xb + 2324: 0000 unimp + 2326: 00098c17 auipc s8,0x98 + 232a: 0300 addi s0,sp,384 + 232c: 1d070267 jalr tp,464(a4) + 2330: 0000 unimp + 2332: 0000 unimp + 2334: 000aec17 auipc s8,0xae + 2338: 0300 addi s0,sp,384 + 233a: 026c addi a1,sp,268 + 233c: 00069f0b 0x69f0b + 2340: 0400 addi s0,sp,512 + 2342: 000ad417 auipc s0,0xad + 2346: 0300 addi s0,sp,384 + 2348: 026c addi a1,sp,268 + 234a: 9f14 0x9f14 + 234c: 0006 c.slli zero,0x1 + 234e: 0800 addi s0,sp,16 + 2350: 00078617 auipc a2,0x78 + 2354: 0300 addi s0,sp,384 + 2356: 026c addi a1,sp,268 + 2358: 9f1e add t5,t5,t2 + 235a: 0006 c.slli zero,0x1 + 235c: 0c00 addi s0,sp,528 + 235e: 0009f917 auipc s2,0x9f + 2362: 0300 addi s0,sp,384 + 2364: 026e slli tp,tp,0x1b + 2366: 1d08 addi a0,sp,688 + 2368: 0000 unimp + 236a: 1000 addi s0,sp,32 + 236c: 0005c917 auipc s2,0x5c + 2370: 0300 addi s0,sp,384 + 2372: 9f08026f jal tp,fff82562 <__global_pointer$+0x7ff7e8fa> + 2376: 0008 0x8 + 2378: 1400 addi s0,sp,544 + 237a: 000a1517 auipc a0,0xa1 + 237e: 0300 addi s0,sp,384 + 2380: 0272 slli tp,tp,0x1c + 2382: 00001d07 0x1d07 + 2386: 3000 fld fs0,32(s0) + 2388: 000a0317 auipc t1,0xa0 + 238c: 0300 addi s0,sp,384 + 238e: b4160273 0xb4160273 + 2392: 0008 0x8 + 2394: 3400 fld fs0,40(s0) + 2396: 0008ec17 auipc s8,0x8e + 239a: 0300 addi s0,sp,384 + 239c: 0275 addi tp,tp,29 + 239e: 00001d07 0x1d07 + 23a2: 3800 fld fs0,48(s0) + 23a4: 000a0b17 auipc s6,0xa0 + 23a8: 0300 addi s0,sp,384 + 23aa: c50a0277 0xc50a0277 + 23ae: 0008 0x8 + 23b0: 3c00 fld fs0,56(s0) + 23b2: 00081c17 auipc s8,0x81 + 23b6: 0300 addi s0,sp,384 + 23b8: 027a slli tp,tp,0x1e + 23ba: 00017d13 andi s10,sp,0 + 23be: 4000 lw s0,0(s0) + 23c0: 00070817 auipc a6,0x70 + 23c4: 0300 addi s0,sp,384 + 23c6: 1d07027b 0x1d07027b + 23ca: 0000 unimp + 23cc: 4400 lw s0,8(s0) + 23ce: 000b7e17 auipc t3,0xb7 + 23d2: 0300 addi s0,sp,384 + 23d4: 027c addi a5,sp,268 + 23d6: 00017d13 andi s10,sp,0 + 23da: 4800 lw s0,16(s0) + 23dc: 0008fe17 auipc t3,0x8f + 23e0: 0300 addi s0,sp,384 + 23e2: 027d addi tp,tp,31 + 23e4: cb14 sw a3,16(a4) + 23e6: 0008 0x8 + 23e8: 4c00 lw s0,24(s0) + 23ea: 0007d217 auipc tp,0x7d + 23ee: 0300 addi s0,sp,384 + 23f0: 0280 addi s0,sp,320 + 23f2: 00001d07 0x1d07 + 23f6: 5000 lw s0,32(s0) + 23f8: 00073f17 auipc t5,0x73 + 23fc: 0300 addi s0,sp,384 + 23fe: 0281 addi t0,t0,0 + 2400: ae09 j 2712 <_start-0x7fffd8ee> + 2402: 0005 c.nop 1 + 2404: 5400 lw s0,40(s0) + 2406: 00098517 auipc a0,0x98 + 240a: 0300 addi s0,sp,384 + 240c: 02a4 addi s1,sp,328 + 240e: 00087a07 0x87a07 + 2412: 5800 lw s0,48(s0) + 2414: da18 sw a4,48(a2) + 2416: 0008 0x8 + 2418: 0300 addi s0,sp,384 + 241a: 02a8 addi a0,sp,328 + 241c: 0002ae13 slti t3,t0,0 + 2420: 4800 lw s0,16(s0) + 2422: 1801 addi a6,a6,-32 + 2424: 07fa slli a5,a5,0x1e + 2426: 0000 unimp + 2428: 1202a903 lw s2,288(t0) + 242c: 0000026b 0x26b + 2430: 014c addi a1,sp,132 + 2432: 0618 addi a4,sp,768 + 2434: 0300000b 0x300000b + 2438: 02ad addi t0,t0,11 + 243a: dc0c sw a1,56(s0) + 243c: 0008 0x8 + 243e: dc00 sw s0,56(s0) + 2440: 1802 slli a6,a6,0x20 + 2442: 06e5 addi a3,a3,25 + 2444: 0000 unimp + 2446: 1002b203 0x1002b203 + 244a: 0660 addi s0,sp,780 + 244c: 0000 unimp + 244e: 02e0 addi s0,sp,332 + 2450: ca18 sw a4,16(a2) + 2452: 0006 c.slli zero,0x1 + 2454: 0300 addi s0,sp,384 + 2456: 02b4 addi a3,sp,328 + 2458: e80a fsw ft2,16(sp) + 245a: 0008 0x8 + 245c: ec00 fsw fs0,24(s0) + 245e: 0002 c.slli64 zero + 2460: 05b4040f 0x5b4040f + 2464: 0000 unimp + 2466: 69080103 lb sp,1680(a6) # 72a50 <_start-0x7ff8d5b0> + 246a: 0000 unimp + 246c: 1500 addi s0,sp,672 + 246e: 05b4 addi a3,sp,712 + 2470: 0000 unimp + 2472: 043c040f 0x43c040f + 2476: 0000 unimp + 2478: 00008f13 mv t5,ra + 247c: e400 fsw fs0,8(s0) + 247e: 0005 c.nop 1 + 2480: 1400 addi s0,sp,544 + 2482: 045a slli s0,s0,0x16 + 2484: 0000 unimp + 2486: fd14 fsw fa3,56(a0) + 2488: 0000 unimp + 248a: 1400 addi s0,sp,544 + 248c: 05e4 addi s1,sp,716 + 248e: 0000 unimp + 2490: 1d14 addi a3,sp,688 + 2492: 0000 unimp + 2494: 0000 unimp + 2496: 05bb040f 0x5bb040f + 249a: 0000 unimp + 249c: e415 bnez s0,24c8 <_start-0x7fffdb38> + 249e: 0005 c.nop 1 + 24a0: 0f00 addi s0,sp,912 + 24a2: c604 sw s1,8(a2) + 24a4: 0005 c.nop 1 + 24a6: 1300 addi s0,sp,416 + 24a8: 00000083 lb ra,0(zero) # 0 <_start-0x80000000> + 24ac: 00000613 li a2,0 + 24b0: 5a14 lw a3,48(a2) + 24b2: 0004 0x4 + 24b4: 1400 addi s0,sp,544 + 24b6: 00fd addi ra,ra,31 + 24b8: 0000 unimp + 24ba: 8314 0x8314 + 24bc: 0000 unimp + 24be: 1400 addi s0,sp,544 + 24c0: 001d c.nop 7 + 24c2: 0000 unimp + 24c4: 0f00 addi s0,sp,912 + 24c6: f504 fsw fs1,40(a0) + 24c8: 0005 c.nop 1 + 24ca: 1300 addi s0,sp,416 + 24cc: 001d c.nop 7 + 24ce: 0000 unimp + 24d0: 062d addi a2,a2,11 + 24d2: 0000 unimp + 24d4: 5a14 lw a3,48(a2) + 24d6: 0004 0x4 + 24d8: 1400 addi s0,sp,544 + 24da: 00fd addi ra,ra,31 + 24dc: 0000 unimp + 24de: 0f00 addi s0,sp,912 + 24e0: 1904 addi s1,sp,176 + 24e2: 0006 c.slli zero,0x1 + 24e4: 0800 addi s0,sp,16 + 24e6: 0040 addi s0,sp,4 + 24e8: 0000 unimp + 24ea: 00000643 fmadd.s fa2,ft0,ft0,ft0,rne + 24ee: 2409 jal 26f0 <_start-0x7fffd910> + 24f0: 0000 unimp + 24f2: 0200 addi s0,sp,256 + 24f4: 0800 addi s0,sp,16 + 24f6: 0040 addi s0,sp,4 + 24f8: 0000 unimp + 24fa: 00000653 fadd.s fa2,ft0,ft0,rne + 24fe: 2409 jal 2700 <_start-0x7fffd900> + 2500: 0000 unimp + 2502: 0000 unimp + 2504: 0400 addi s0,sp,512 + 2506: 0701 addi a4,a4,0 + 2508: 0000 unimp + 250a: 1a012403 lw s0,416(sp) + 250e: 02f9 addi t0,t0,30 + 2510: 0000 unimp + 2512: e619 bnez a2,2520 <_start-0x7fffdae0> + 2514: 000a c.slli zero,0x2 + 2516: 0c00 addi s0,sp,528 + 2518: 08012803 lw a6,128(sp) + 251c: 0699 addi a3,a3,6 + 251e: 0000 unimp + 2520: 0009e617 auipc a2,0x9e + 2524: 0300 addi s0,sp,384 + 2526: 012a slli sp,sp,0xa + 2528: 9911 andi a0,a0,-28 + 252a: 0006 c.slli zero,0x1 + 252c: 0000 unimp + 252e: 0007ea17 auipc s4,0x7e + 2532: 0300 addi s0,sp,384 + 2534: 1d07012b 0x1d07012b + 2538: 0000 unimp + 253a: 0400 addi s0,sp,512 + 253c: 0009b517 auipc a0,0x9b + 2540: 0300 addi s0,sp,384 + 2542: 012c addi a1,sp,136 + 2544: 00069f0b 0x69f0b + 2548: 0800 addi s0,sp,16 + 254a: 0f00 addi s0,sp,912 + 254c: 6004 flw fs1,0(s0) + 254e: 0006 c.slli zero,0x1 + 2550: 0f00 addi s0,sp,912 + 2552: 5304 lw s1,32(a4) + 2554: 0006 c.slli zero,0x1 + 2556: 1900 addi s0,sp,176 + 2558: 05c1 addi a1,a1,16 + 255a: 0000 unimp + 255c: 030e slli t1,t1,0x3 + 255e: 0144 addi s1,sp,132 + 2560: de08 sw a0,56(a2) + 2562: 0006 c.slli zero,0x1 + 2564: 1700 addi s0,sp,928 + 2566: 0a3d addi s4,s4,15 + 2568: 0000 unimp + 256a: 12014503 lbu a0,288(sp) + 256e: 06de slli a3,a3,0x17 + 2570: 0000 unimp + 2572: 1700 addi s0,sp,928 + 2574: 0855 addi a6,a6,21 + 2576: 0000 unimp + 2578: 12014603 lbu a2,288(sp) + 257c: 06de slli a3,a3,0x17 + 257e: 0000 unimp + 2580: 1706 slli a4,a4,0x21 + 2582: 0a9f 0000 4703 0x470300000a9f + 2588: 1201 addi tp,tp,-32 + 258a: 004e c.slli zero,0x13 + 258c: 0000 unimp + 258e: 000c 0xc + 2590: 4e08 lw a0,24(a2) + 2592: 0000 unimp + 2594: ee00 fsw fs0,24(a2) + 2596: 0006 c.slli zero,0x1 + 2598: 0900 addi s0,sp,144 + 259a: 0024 addi s1,sp,8 + 259c: 0000 unimp + 259e: 0002 c.slli64 zero + 25a0: d01a sw t1,32(sp) + 25a2: 07028503 lb a0,112(t0) + 25a6: 00000803 lb a6,0(zero) # 0 <_start-0x80000000> + 25aa: 00088f17 auipc t5,0x88 + 25ae: 0300 addi s0,sp,384 + 25b0: 24180287 0x24180287 + 25b4: 0000 unimp + 25b6: 0000 unimp + 25b8: 000a8217 auipc tp,0xa8 + 25bc: 0300 addi s0,sp,384 + 25be: 0288 addi a0,sp,320 + 25c0: ae12 fsd ft4,280(sp) + 25c2: 0005 c.nop 1 + 25c4: 0400 addi s0,sp,512 + 25c6: 00080f17 auipc t5,0x80 + 25ca: 0300 addi s0,sp,384 + 25cc: 0289 addi t0,t0,2 + 25ce: 0310 addi a2,sp,384 + 25d0: 0008 0x8 + 25d2: 0800 addi s0,sp,16 + 25d4: 000b3817 auipc a6,0xb3 + 25d8: 0300 addi s0,sp,384 + 25da: 028a slli t0,t0,0x2 + 25dc: 00019317 auipc t1,0x19 + 25e0: 2400 fld fs0,8(s0) + 25e2: 00079617 auipc a2,0x79 + 25e6: 0300 addi s0,sp,384 + 25e8: 1d0f028b 0x1d0f028b + 25ec: 0000 unimp + 25ee: 4800 lw s0,16(s0) + 25f0: 0009e117 auipc sp,0x9e + 25f4: 0300 addi s0,sp,384 + 25f6: 028c addi a1,sp,320 + 25f8: 632c flw fa1,64(a4) + 25fa: 0000 unimp + 25fc: 5000 lw s0,32(s0) + 25fe: 000b5017 auipc zero,0xb5 + 2602: 0300 addi s0,sp,384 + 2604: 028d addi t0,t0,3 + 2606: a51a fsd ft6,136(sp) + 2608: 0006 c.slli zero,0x1 + 260a: 5800 lw s0,48(s0) + 260c: 0009ec17 auipc s8,0x9e + 2610: 0300 addi s0,sp,384 + 2612: 028e slli t0,t0,0x3 + 2614: f116 fsw ft5,160(sp) + 2616: 0000 unimp + 2618: 6800 flw fs0,16(s0) + 261a: 000b7017 auipc zero,0xb7 + 261e: 0300 addi s0,sp,384 + 2620: f116028f 0xf116028f + 2624: 0000 unimp + 2626: 7000 flw fs0,32(s0) + 2628: 00068617 auipc a2,0x68 + 262c: 0300 addi s0,sp,384 + 262e: 0290 addi a2,sp,320 + 2630: f116 fsw ft5,160(sp) + 2632: 0000 unimp + 2634: 7800 flw fs0,48(s0) + 2636: 000afc17 auipc s8,0xaf + 263a: 0300 addi s0,sp,384 + 263c: 0291 addi t0,t0,4 + 263e: 1310 addi a2,sp,416 + 2640: 0008 0x8 + 2642: 8000 0x8000 + 2644: 00080317 auipc t1,0x80 + 2648: 0300 addi s0,sp,384 + 264a: 0292 slli t0,t0,0x4 + 264c: 2310 fld fa2,0(a4) + 264e: 0008 0x8 + 2650: 8800 0x8800 + 2652: 0005ed17 auipc s10,0x5e + 2656: 0300 addi s0,sp,384 + 2658: 1d0f0293 addi t0,t5,464 # 82796 <_start-0x7ff7d86a> + 265c: 0000 unimp + 265e: a000 fsd fs0,0(s0) + 2660: 00075817 auipc a6,0x75 + 2664: 0300 addi s0,sp,384 + 2666: 0294 addi a3,sp,320 + 2668: f116 fsw ft5,160(sp) + 266a: 0000 unimp + 266c: a400 fsd fs0,8(s0) + 266e: 00066f17 auipc t5,0x66 + 2672: 0300 addi s0,sp,384 + 2674: 0295 addi t0,t0,5 + 2676: f116 fsw ft5,160(sp) + 2678: 0000 unimp + 267a: ac00 fsd fs0,24(s0) + 267c: 00074717 auipc a4,0x74 + 2680: 0300 addi s0,sp,384 + 2682: 0296 slli t0,t0,0x5 + 2684: f116 fsw ft5,160(sp) + 2686: 0000 unimp + 2688: b400 fsd fs0,40(s0) + 268a: 00060017 auipc zero,0x60 + 268e: 0300 addi s0,sp,384 + 2690: f1160297 auipc t0,0xf1160 + 2694: 0000 unimp + 2696: bc00 fsd fs0,56(s0) + 2698: 00062c17 auipc s8,0x62 + 269c: 0300 addi s0,sp,384 + 269e: 0298 addi a4,sp,320 + 26a0: f116 fsw ft5,160(sp) + 26a2: 0000 unimp + 26a4: c400 sw s0,8(s0) + 26a6: 00098a17 auipc s4,0x98 + 26aa: 0300 addi s0,sp,384 + 26ac: 0299 addi t0,t0,6 + 26ae: 1d08 addi a0,sp,688 + 26b0: 0000 unimp + 26b2: cc00 sw s0,24(s0) + 26b4: 0800 addi s0,sp,16 + 26b6: 05b4 addi a3,sp,712 + 26b8: 0000 unimp + 26ba: 00000813 li a6,0 + 26be: 2409 jal 28c0 <_start-0x7fffd740> + 26c0: 0000 unimp + 26c2: 1900 addi s0,sp,176 + 26c4: 0800 addi s0,sp,16 + 26c6: 05b4 addi a3,sp,712 + 26c8: 0000 unimp + 26ca: 00000823 sb zero,16(zero) # 10 <_start-0x7ffffff0> + 26ce: 2409 jal 28d0 <_start-0x7fffd730> + 26d0: 0000 unimp + 26d2: 0700 addi s0,sp,896 + 26d4: 0800 addi s0,sp,16 + 26d6: 05b4 addi a3,sp,712 + 26d8: 0000 unimp + 26da: 00000833 add a6,zero,zero + 26de: 2409 jal 28e0 <_start-0x7fffd720> + 26e0: 0000 unimp + 26e2: 1700 addi s0,sp,928 + 26e4: 1a00 addi s0,sp,304 + 26e6: 03f0 addi a2,sp,460 + 26e8: 029e slli t0,t0,0x7 + 26ea: 00085a07 0x85a07 + 26ee: 1700 addi s0,sp,928 + 26f0: 08bc addi a5,sp,88 + 26f2: 0000 unimp + 26f4: 1b02a103 lw sp,432(t0) # f1162840 <__global_pointer$+0x7115ebd8> + 26f8: 085a slli a6,a6,0x16 + 26fa: 0000 unimp + 26fc: 1700 addi s0,sp,928 + 26fe: 07a5 addi a5,a5,9 + 2700: 0000 unimp + 2702: 1802a203 lw tp,384(t0) + 2706: 086a slli a6,a6,0x1a + 2708: 0000 unimp + 270a: 0078 addi a4,sp,12 + 270c: f308 fsw fa0,32(a4) + 270e: 0002 c.slli64 zero + 2710: 6a00 flw fs0,16(a2) + 2712: 0008 0x8 + 2714: 0900 addi s0,sp,144 + 2716: 0024 addi s1,sp,8 + 2718: 0000 unimp + 271a: 001d c.nop 7 + 271c: 2408 fld fa0,8(s0) + 271e: 0000 unimp + 2720: 7a00 flw fs0,48(a2) + 2722: 0008 0x8 + 2724: 0900 addi s0,sp,144 + 2726: 0024 addi s1,sp,8 + 2728: 0000 unimp + 272a: 001d c.nop 7 + 272c: 8303f01b 0x8303f01b + 2730: 0302 c.slli64 t1 + 2732: 089f 0000 361c 0x361c0000089f + 2738: 000a c.slli zero,0x2 + 273a: 0300 addi s0,sp,384 + 273c: 029a slli t0,t0,0x6 + 273e: 0006ee0b 0x6ee0b + 2742: 1c00 addi s0,sp,560 + 2744: 0b25 addi s6,s6,9 + 2746: 0000 unimp + 2748: 0b02a303 lw t1,176(t0) + 274c: 00000833 add a6,zero,zero + 2750: 0800 addi s0,sp,16 + 2752: 05b4 addi a3,sp,712 + 2754: 0000 unimp + 2756: 000008af 0x8af + 275a: 2409 jal 295c <_start-0x7fffd6a4> + 275c: 0000 unimp + 275e: 1800 addi s0,sp,48 + 2760: 1d00 addi s0,sp,688 + 2762: 0664 addi s1,sp,780 + 2764: 0000 unimp + 2766: 08af040f 0x8af040f + 276a: 0000 unimp + 276c: c51e sw t2,136(sp) + 276e: 0008 0x8 + 2770: 1400 addi s0,sp,544 + 2772: 045a slli s0,s0,0x16 + 2774: 0000 unimp + 2776: 0f00 addi s0,sp,912 + 2778: ba04 fsd fs1,48(a2) + 277a: 0008 0x8 + 277c: 0f00 addi s0,sp,912 + 277e: 7d04 flw fs1,56(a0) + 2780: 0001 nop + 2782: 1e00 addi s0,sp,816 + 2784: 08dc addi a5,sp,84 + 2786: 0000 unimp + 2788: 1d14 addi a3,sp,688 + 278a: 0000 unimp + 278c: 0000 unimp + 278e: 08e2040f 0x8e2040f + 2792: 0000 unimp + 2794: 08d1040f 0x8d1040f + 2798: 0000 unimp + 279a: 5308 lw a0,32(a4) + 279c: 0006 c.slli zero,0x1 + 279e: f800 fsw fs0,48(s0) + 27a0: 0008 0x8 + 27a2: 0900 addi s0,sp,144 + 27a4: 0024 addi s1,sp,8 + 27a6: 0000 unimp + 27a8: 0002 c.slli64 zero + 27aa: c81f 000a 0300 0x300000ac81f + 27b0: 5a170333 0x5a170333 + 27b4: 0004 0x4 + 27b6: 1f00 addi s0,sp,944 + 27b8: 0ac1 addi s5,s5,16 + 27ba: 0000 unimp + 27bc: 1d033403 0x1d033403 + 27c0: 0460 addi s0,sp,524 + 27c2: 0000 unimp + 27c4: ea08 fsw fa0,16(a2) + 27c6: 0005 c.nop 1 + 27c8: 1d00 addi s0,sp,688 + 27ca: 0009 c.nop 2 + 27cc: 2000 fld fs0,0(s0) + 27ce: 1500 addi s0,sp,672 + 27d0: 0912 slli s2,s2,0x4 + 27d2: 0000 unimp + 27d4: 3221 jal 20dc <_start-0x7fffdf24> + 27d6: 05000007 0x5000007 + 27da: 2414 fld fa3,8(s0) + 27dc: 091d addi s2,s2,7 + 27de: 0000 unimp + 27e0: d721 beqz a4,2728 <_start-0x7fffd8d8> + 27e2: 0009 c.nop 2 + 27e4: 0500 addi s0,sp,640 + 27e6: 1515 addi a0,a0,-27 + 27e8: 001d c.nop 7 + 27ea: 0000 unimp + 27ec: 0940040f 0x940040f + 27f0: 0000 unimp + 27f2: 00001d13 slli s10,zero,0x0 + 27f6: 5400 lw s0,40(s0) + 27f8: 0009 c.nop 2 + 27fa: 1400 addi s0,sp,544 + 27fc: 0954 addi a3,sp,148 + 27fe: 0000 unimp + 2800: 5414 lw a3,40(s0) + 2802: 0009 c.nop 2 + 2804: 0000 unimp + 2806: 095a040f 0x95a040f + 280a: 0000 unimp + 280c: 2122 fld ft2,8(sp) + 280e: 08e2 slli a7,a7,0x18 + 2810: 0000 unimp + 2812: 6706 flw fa4,64(sp) + 2814: ae0e fsd ft3,280(sp) + 2816: 0005 c.nop 1 + 2818: 2100 fld fs0,0(a0) + 281a: 082a slli a6,a6,0xa + 281c: 0000 unimp + 281e: 730f1007 0x730f1007 + 2822: 0009 c.nop 2 + 2824: 0f00 addi s0,sp,912 + 2826: ae04 fsd fs1,24(a2) + 2828: 0005 c.nop 1 + 282a: 2100 fld fs0,0(a0) + 282c: 08e5 addi a7,a7,25 + 282e: 0000 unimp + 2830: ae0efc07 0xae0efc07 + 2834: 0005 c.nop 1 + 2836: 2100 fld fs0,0(a0) + 2838: 08b5 addi a7,a7,13 + 283a: 0000 unimp + 283c: 1d0cfd07 0x1d0cfd07 + 2840: 0000 unimp + 2842: 2100 fld fs0,0(a0) + 2844: 00000a7b 0xa7b + 2848: 1d14fd07 0x1d14fd07 + 284c: 0000 unimp + 284e: 2100 fld fs0,0(a0) + 2850: 0b5f 0000 fd07 0xfd0700000b5f + 2856: 1d1c addi a5,sp,688 + 2858: 0000 unimp + 285a: 2100 fld fs0,0(a0) + 285c: 086a slli a6,a6,0x1a + 285e: 0000 unimp + 2860: 1d0cff07 0x1d0cff07 + 2864: 0000 unimp + 2866: 2100 fld fs0,0(a0) + 2868: 0908 addi a0,sp,144 + 286a: 0000 unimp + 286c: 9a08 0x9a08 + 286e: 5516 lw a0,100(sp) + 2870: 0000 unimp + 2872: 2100 fld fs0,0(a0) + 2874: 05d4 addi a3,sp,708 + 2876: 0000 unimp + 2878: 9b08 0x9b08 + 287a: 1d15 addi s10,s10,-27 + 287c: 0000 unimp + 287e: 0800 addi s0,sp,16 + 2880: 05ae slli a1,a1,0xb + 2882: 0000 unimp + 2884: 09dd addi s3,s3,23 + 2886: 0000 unimp + 2888: 2409 jal 2a8a <_start-0x7fffd576> + 288a: 0000 unimp + 288c: 0100 addi s0,sp,128 + 288e: 2100 fld fs0,0(a0) + 2890: 067e slli a2,a2,0x1f + 2892: 0000 unimp + 2894: 9e08 0x9e08 + 2896: 0009cd17 auipc s10,0x9c + 289a: 0500 addi s0,sp,640 + 289c: 07e0 addi s0,sp,972 + 289e: 0000 unimp + 28a0: 2a09 jal 29b2 <_start-0x7fffd64e> + 28a2: 2416 fld fs0,320(sp) + 28a4: 0000 unimp + 28a6: 0500 addi s0,sp,640 + 28a8: 09c5 addi s3,s3,17 + 28aa: 0000 unimp + 28ac: 2f09 jal 2fbe <_start-0x7fffd042> + 28ae: 0115 addi sp,sp,5 + 28b0: 000a c.slli zero,0x2 + 28b2: 0f00 addi s0,sp,912 + 28b4: 0704 addi s1,sp,896 + 28b6: 000a c.slli zero,0x2 + 28b8: 1300 addi s0,sp,416 + 28ba: 09e9 addi s3,s3,26 + 28bc: 0000 unimp + 28be: 0a16 slli s4,s4,0x5 + 28c0: 0000 unimp + 28c2: 5414 lw a3,40(s0) + 28c4: 0009 c.nop 2 + 28c6: 0000 unimp + 28c8: 8d05 sub a0,a0,s1 + 28ca: 0900000b 0x900000b + 28ce: 0f36 slli t5,t5,0xd + 28d0: 093a slli s2,s2,0xe + 28d2: 0000 unimp + 28d4: a921 j 2cec <_start-0x7fffd314> + 28d6: 0005 c.nop 1 + 28d8: 0900 addi s0,sp,144 + 28da: 09f512bb 0x9f512bb + 28de: 0000 unimp + 28e0: ac21 j 2af8 <_start-0x7fffd508> + 28e2: 000a c.slli zero,0x2 + 28e4: 0900 addi s0,sp,144 + 28e6: 10be slli ra,ra,0x2f + 28e8: 0a16 slli s4,s4,0x5 + 28ea: 0000 unimp + 28ec: 0007b323 0x7b323 + 28f0: 0700 addi s0,sp,896 + 28f2: 2404 fld fs1,8(s0) + 28f4: 0000 unimp + 28f6: 0a00 addi s0,sp,272 + 28f8: 0618 addi a4,sp,768 + 28fa: 00000a77 0xa77 + 28fe: 6524 flw fs1,72(a0) + 2900: 0009 c.nop 2 + 2902: 0000 unimp + 2904: 4a24 lw s1,80(a2) + 2906: 0008 0x8 + 2908: 0100 addi s0,sp,128 + 290a: 8424 0x8424 + 290c: 0008 0x8 + 290e: 0200 addi s0,sp,256 + 2910: 3f24 fld fs1,120(a4) + 2912: 0008 0x8 + 2914: 0300 addi s0,sp,384 + 2916: 5c24 lw s1,120(s0) + 2918: 0009 c.nop 2 + 291a: 0400 addi s0,sp,512 + 291c: 6624 flw fs1,72(a2) + 291e: 0500000b 0x500000b + 2922: 5524 lw s1,104(a0) + 2924: 0600000b 0x600000b + 2928: 2100 fld fs0,0(a0) + 292a: 065a slli a2,a2,0x16 + 292c: 0000 unimp + 292e: 210a fld ft2,128(sp) + 2930: 3a1c fld fa5,48(a2) + 2932: 000a c.slli zero,0x2 + 2934: 2300 fld fs0,0(a4) + 2936: 089c addi a5,sp,80 + 2938: 0000 unimp + 293a: 00240407 0x240407 + 293e: 0000 unimp + 2940: 230a fld ft6,128(sp) + 2942: a806 fsd ft1,16(sp) + 2944: 000a c.slli zero,0x2 + 2946: 2400 fld fs0,8(s0) + 2948: 000009bb 0x9bb + 294c: 2400 fld fs0,8(s0) + 294e: 0000097b 0x97b + 2952: 2401 jal 2b52 <_start-0x7fffd4ae> + 2954: 00000a8f 0xa8f + 2958: 0002 c.slli64 zero + 295a: 6621 lui a2,0x8 + 295c: 0a000007 0xa000007 + 2960: 1e28 addi a0,sp,824 + 2962: 00000a83 lb s5,0(zero) # 0 <_start-0x80000000> + 2966: 00060f23 sb zero,30(a2) # 801e <_start-0x7fff7fe2> + 296a: 0700 addi s0,sp,896 + 296c: 2404 fld fs1,8(s0) + 296e: 0000 unimp + 2970: 0a00 addi s0,sp,272 + 2972: 0ad3062b 0xad3062b + 2976: 0000 unimp + 2978: 7324 flw fs1,96(a4) + 297a: 000a c.slli zero,0x2 + 297c: 0000 unimp + 297e: 6124 flw fs1,64(a0) + 2980: 000a c.slli zero,0x2 + 2982: 0100 addi s0,sp,128 + 2984: 2100 fld fs0,0(a0) + 2986: 071a slli a4,a4,0x6 + 2988: 0000 unimp + 298a: 2f0a fld ft10,128(sp) + 298c: b42a fsd fa0,40(sp) + 298e: 000a c.slli zero,0x2 + 2990: 2100 fld fs0,0(a0) + 2992: 0000085b 0x85b + 2996: 1d1a290b 0x1d1a290b + 299a: 0009 c.nop 2 + 299c: 2100 fld fs0,0(a0) + 299e: 06ba slli a3,a3,0xe + 29a0: 0000 unimp + 29a2: 1d1a380b 0x1d1a380b + 29a6: 0009 c.nop 2 + 29a8: 0500 addi s0,sp,640 + 29aa: 00c8 addi a0,sp,68 + 29ac: 0000 unimp + 29ae: 7b0c flw fa1,48(a4) + 29b0: 4016 0x4016 + 29b2: 0000 unimp + 29b4: 1500 addi s0,sp,672 + 29b6: 00000af7 0xaf7 + 29ba: cb040403 lb s0,-848(s0) # aeff2 <_start-0x7ff5100e> + 29be: 0008 0x8 + 29c0: 0300 addi s0,sp,384 + 29c2: 0308 addi a0,sp,384 + 29c4: 000008c3 fmadd.s fa7,ft0,ft0,ft0,rne + 29c8: 53040803 lb a6,1328(s0) + 29cc: 0006 c.slli zero,0x1 + 29ce: 0300 addi s0,sp,384 + 29d0: 0310 addi a2,sp,384 + 29d2: 05de slli a1,a1,0x17 + 29d4: 0000 unimp + 29d6: 46032003 lw zero,1120(t1) # 82aa4 <_start-0x7ff7d55c> + 29da: 0006 c.slli zero,0x1 + 29dc: 0800 addi s0,sp,16 + 29de: 00000b03 lb s6,0(zero) # 0 <_start-0x80000000> + 29e2: 00000b3b 0xb3b + 29e6: 2409 jal 2be8 <_start-0x7fffd418> + 29e8: 0000 unimp + 29ea: ff00 fsw fs0,56(a4) + 29ec: 1500 addi s0,sp,672 + 29ee: 00000b2b 0xb2b + 29f2: 101f 000b 0c00 0xc00000b101f + 29f8: 01fc addi a5,sp,204 + 29fa: 3b16 fld fs6,352(sp) + 29fc: 1f00000b 0x1f00000b + 2a00: 00d0 addi a2,sp,68 + 2a02: 0000 unimp + 2a04: 020c addi a1,sp,256 + 2a06: 1602 slli a2,a2,0x20 + 2a08: 00000b3b 0xb3b + 2a0c: 4d25 li s10,9 + 2a0e: 0d00000b 0xd00000b + 2a12: 02b2 slli t0,t0,0xc + 2a14: 6403050f 0x6403050f + 2a18: 00800023 sb s0,0(zero) # 0 <_start-0x80000000> + +Disassembly of section .debug_abbrev: + +00000000 <.debug_abbrev>: + 0: 1101 addi sp,sp,-32 + 2: 2501 jal 602 <_start-0x7ffff9fe> + 4: 130e slli t1,t1,0x23 + 6: 1b0e030b 0x1b0e030b + a: 110e slli sp,sp,0x23 + c: 1201 addi tp,tp,-32 + e: 1006 c.slli zero,0x21 + 10: 02000017 auipc zero,0x2000 + 14: 0024 addi s1,sp,8 + 16: 0b3e0b0b 0xb3e0b0b + 1a: 00000e03 lb t3,0(zero) # 0 <_start-0x80000000> + 1e: 0b002403 lw s0,176(zero) # b0 <_start-0x7fffff50> + 22: 030b3e0b 0x30b3e0b + 26: 0008 0x8 + 28: 0400 addi s0,sp,512 + 2a: 0016 c.slli zero,0x5 + 2c: 0b3a0e03 lb t3,179(s4) # 9a759 <_start-0x7ff658a7> + 30: 0b39053b 0xb39053b + 34: 1349 addi t1,t1,-14 + 36: 0000 unimp + 38: 2605 jal 358 <_start-0x7ffffca8> + 3a: 4900 lw s0,16(a0) + 3c: 06000013 li zero,96 + 40: 0101 addi sp,sp,0 + 42: 1349 addi t1,t1,-14 + 44: 1301 addi t1,t1,-32 + 46: 0000 unimp + 48: 49002107 flw ft2,1168(zero) # 490 <_start-0x7ffffb70> + 4c: 000b2f13 slti t5,s6,0 + 50: 0800 addi s0,sp,16 + 52: 0034 addi a3,sp,8 + 54: 0b3a0e03 lb t3,179(s4) + 58: 0b390b3b 0xb390b3b + 5c: 1349 addi t1,t1,-14 + 5e: 193c193f 16090000 0x16090000193c193f + 66: 0300 addi s0,sp,384 + 68: 3a0e fld fs4,224(sp) + 6a: 390b3b0b 0x390b3b0b + 6e: 0013490b 0x13490b + 72: 0a00 addi s0,sp,272 + 74: 0b0b0113 addi sp,s6,176 # a2454 <_start-0x7ff5dbac> + 78: 0b3a slli s6,s6,0xe + 7a: 0b390b3b 0xb390b3b + 7e: 1301 addi t1,t1,-32 + 80: 0000 unimp + 82: 03000d0b 0x3000d0b + 86: 3a0e fld fs4,224(sp) + 88: 390b3b0b 0x390b3b0b + 8c: 0b13490b 0xb13490b + 90: 0c0b0d0b 0xc0b0d0b + 94: 000b380b 0xb380b + 98: 0c00 addi s0,sp,528 + 9a: 000d c.nop 3 + 9c: 0b3a0803 lb a6,179(s4) + a0: 0b390b3b 0xb390b3b + a4: 1349 addi t1,t1,-14 + a6: 0b0d0b0b 0xb0d0b0b + aa: 0b0c addi a1,sp,400 + ac: 0b38 addi a4,sp,408 + ae: 0000 unimp + b0: 170d addi a4,a4,-29 + b2: 0301 addi t1,t1,0 + b4: 0b0e slli s6,s6,0x3 + b6: 3b0b3a0b 0x3b0b3a0b + ba: 010b390b 0x10b390b + be: 0e000013 li zero,224 + c2: 000d c.nop 3 + c4: 0b3a0803 lb a6,179(s4) + c8: 0b390b3b 0xb390b3b + cc: 1349 addi t1,t1,-14 + ce: 0000 unimp + d0: 03000d0f 0x3000d0f + d4: 3a0e fld fs4,224(sp) + d6: 390b3b0b 0x390b3b0b + da: 0013490b 0x13490b + de: 1000 addi s0,sp,32 + e0: 012e slli sp,sp,0xb + e2: 0e03193f 0b3b0b3a 0xb3b0b3a0e03193f + ea: 0b39 addi s6,s6,14 + ec: 13491927 0x13491927 + f0: 0111 addi sp,sp,4 + f2: 0612 slli a2,a2,0x4 + f4: 1840 addi s0,sp,52 + f6: 4296 lw t0,68(sp) + f8: 0119 addi sp,sp,6 + fa: 11000013 li zero,272 + fe: 0005 c.nop 1 + 100: 0b3a0803 lb a6,179(s4) + 104: 0b390b3b 0xb390b3b + 108: 1349 addi t1,t1,-14 + 10a: 1702 slli a4,a4,0x20 + 10c: 0000 unimp + 10e: 3412 fld fs0,288(sp) + 110: 0300 addi s0,sp,384 + 112: 3a0e fld fs4,224(sp) + 114: 390b3b0b 0x390b3b0b + 118: 0213490b 0x213490b + 11c: 13000017 auipc zero,0x13000 + 120: 0034 addi a3,sp,8 + 122: 0b3a0e03 lb t3,179(s4) + 126: 0b390b3b 0xb390b3b + 12a: 1349 addi t1,t1,-14 + 12c: 0b1c addi a5,sp,400 + 12e: 0000 unimp + 130: 3414 fld fa3,40(s0) + 132: 0300 addi s0,sp,384 + 134: 3a08 fld fa0,48(a2) + 136: 390b3b0b 0x390b3b0b + 13a: 0013490b 0x13490b + 13e: 1500 addi s0,sp,672 + 140: 0034 addi a3,sp,8 + 142: 0b3a0803 lb a6,179(s4) + 146: 0b390b3b 0xb390b3b + 14a: 1349 addi t1,t1,-14 + 14c: 1702 slli a4,a4,0x20 + 14e: 0000 unimp + 150: 0b16 slli s6,s6,0x5 + 152: 5501 li a0,-32 + 154: 00130117 auipc sp,0x130 + 158: 1700 addi s0,sp,928 + 15a: 0034 addi a3,sp,8 + 15c: 0b3a0e03 lb t3,179(s4) + 160: 0b390b3b 0xb390b3b + 164: 1349 addi t1,t1,-14 + 166: 0000 unimp + 168: 0a18 addi a4,sp,272 + 16a: 0300 addi s0,sp,384 + 16c: 3a0e fld fs4,224(sp) + 16e: 390b3b0b 0x390b3b0b + 172: 0001110b 0x1110b + 176: 1900 addi s0,sp,176 + 178: 1755010b 0x1755010b + 17c: 0000 unimp + 17e: 0b1a slli s6,s6,0x6 + 180: 0001 nop + 182: 0000 unimp + 184: 1101 addi sp,sp,-32 + 186: 2501 jal 786 <_start-0x7ffff87a> + 188: 130e slli t1,t1,0x23 + 18a: 1b0e030b 0x1b0e030b + 18e: 110e slli sp,sp,0x23 + 190: 1201 addi tp,tp,-32 + 192: 1006 c.slli zero,0x21 + 194: 02000017 auipc zero,0x2000 + 198: 0024 addi s1,sp,8 + 19a: 0b3e0b0b 0xb3e0b0b + 19e: 00000e03 lb t3,0(zero) # 0 <_start-0x80000000> + 1a2: 0b002403 lw s0,176(zero) # b0 <_start-0x7fffff50> + 1a6: 030b3e0b 0x30b3e0b + 1aa: 0008 0x8 + 1ac: 0400 addi s0,sp,512 + 1ae: 0016 c.slli zero,0x5 + 1b0: 0b3a0e03 lb t3,179(s4) + 1b4: 0b39053b 0xb39053b + 1b8: 1349 addi t1,t1,-14 + 1ba: 0000 unimp + 1bc: 2605 jal 4dc <_start-0x7ffffb24> + 1be: 4900 lw s0,16(a0) + 1c0: 06000013 li zero,96 + 1c4: 0101 addi sp,sp,0 + 1c6: 1349 addi t1,t1,-14 + 1c8: 1301 addi t1,t1,-32 + 1ca: 0000 unimp + 1cc: 49002107 flw ft2,1168(zero) # 490 <_start-0x7ffffb70> + 1d0: 000b2f13 slti t5,s6,0 + 1d4: 0800 addi s0,sp,16 + 1d6: 0034 addi a3,sp,8 + 1d8: 0b3a0e03 lb t3,179(s4) + 1dc: 0b390b3b 0xb390b3b + 1e0: 1349 addi t1,t1,-14 + 1e2: 193c193f 16090000 0x16090000193c193f + 1ea: 0300 addi s0,sp,384 + 1ec: 3a0e fld fs4,224(sp) + 1ee: 390b3b0b 0x390b3b0b + 1f2: 0013490b 0x13490b + 1f6: 0a00 addi s0,sp,272 + 1f8: 0b0b0113 addi sp,s6,176 + 1fc: 0b3a slli s6,s6,0xe + 1fe: 0b390b3b 0xb390b3b + 202: 1301 addi t1,t1,-32 + 204: 0000 unimp + 206: 03000d0b 0x3000d0b + 20a: 3a0e fld fs4,224(sp) + 20c: 390b3b0b 0x390b3b0b + 210: 0b13490b 0xb13490b + 214: 0c0b0d0b 0xc0b0d0b + 218: 000b380b 0xb380b + 21c: 0c00 addi s0,sp,528 + 21e: 000d c.nop 3 + 220: 0b3a0803 lb a6,179(s4) + 224: 0b390b3b 0xb390b3b + 228: 1349 addi t1,t1,-14 + 22a: 0b0d0b0b 0xb0d0b0b + 22e: 0b0c addi a1,sp,400 + 230: 0b38 addi a4,sp,408 + 232: 0000 unimp + 234: 170d addi a4,a4,-29 + 236: 0301 addi t1,t1,0 + 238: 0b0e slli s6,s6,0x3 + 23a: 3b0b3a0b 0x3b0b3a0b + 23e: 010b390b 0x10b390b + 242: 0e000013 li zero,224 + 246: 000d c.nop 3 + 248: 0b3a0803 lb a6,179(s4) + 24c: 0b390b3b 0xb390b3b + 250: 1349 addi t1,t1,-14 + 252: 0000 unimp + 254: 03000d0f 0x3000d0f + 258: 3a0e fld fs4,224(sp) + 25a: 390b3b0b 0x390b3b0b + 25e: 0013490b 0x13490b + 262: 1000 addi s0,sp,32 + 264: 012e slli sp,sp,0xb + 266: 0e03193f 0b3b0b3a 0xb3b0b3a0e03193f + 26e: 0b39 addi s6,s6,14 + 270: 13491927 0x13491927 + 274: 0111 addi sp,sp,4 + 276: 0612 slli a2,a2,0x4 + 278: 1840 addi s0,sp,52 + 27a: 4296 lw t0,68(sp) + 27c: 0119 addi sp,sp,6 + 27e: 11000013 li zero,272 + 282: 0005 c.nop 1 + 284: 0b3a0803 lb a6,179(s4) + 288: 0b390b3b 0xb390b3b + 28c: 1349 addi t1,t1,-14 + 28e: 1702 slli a4,a4,0x20 + 290: 0000 unimp + 292: 3412 fld fs0,288(sp) + 294: 0300 addi s0,sp,384 + 296: 3a0e fld fs4,224(sp) + 298: 390b3b0b 0x390b3b0b + 29c: 0213490b 0x213490b + 2a0: 13000017 auipc zero,0x13000 + 2a4: 0034 addi a3,sp,8 + 2a6: 0b3a0e03 lb t3,179(s4) + 2aa: 0b390b3b 0xb390b3b + 2ae: 1349 addi t1,t1,-14 + 2b0: 0b1c addi a5,sp,400 + 2b2: 0000 unimp + 2b4: 3414 fld fa3,40(s0) + 2b6: 0300 addi s0,sp,384 + 2b8: 3a08 fld fa0,48(a2) + 2ba: 390b3b0b 0x390b3b0b + 2be: 0213490b 0x213490b + 2c2: 15000017 auipc zero,0x15000 + 2c6: 1755010b 0x1755010b + 2ca: 1301 addi t1,t1,-32 + 2cc: 0000 unimp + 2ce: 3416 fld fs0,352(sp) + 2d0: 0300 addi s0,sp,384 + 2d2: 3a0e fld fs4,224(sp) + 2d4: 390b3b0b 0x390b3b0b + 2d8: 0013490b 0x13490b + 2dc: 1700 addi s0,sp,928 + 2de: 1755010b 0x1755010b + 2e2: 0000 unimp + 2e4: 0b18 addi a4,sp,400 + 2e6: 0001 nop + 2e8: 1900 addi s0,sp,176 + 2ea: 0111010b 0x111010b + 2ee: 0612 slli a2,a2,0x4 + 2f0: 0000 unimp + 2f2: 0100 addi s0,sp,128 + 2f4: 0111 addi sp,sp,4 + 2f6: 0e25 addi t3,t3,9 + 2f8: 0e030b13 addi s6,t1,224 + 2fc: 01110e1b 0x1110e1b + 300: 0612 slli a2,a2,0x4 + 302: 1710 addi a2,sp,928 + 304: 0000 unimp + 306: 2402 fld fs0,0(sp) + 308: 0b00 addi s0,sp,400 + 30a: 030b3e0b 0x30b3e0b + 30e: 000e c.slli zero,0x3 + 310: 0300 addi s0,sp,384 + 312: 0016 c.slli zero,0x5 + 314: 0b3a0e03 lb t3,179(s4) + 318: 0b390b3b 0xb390b3b + 31c: 1349 addi t1,t1,-14 + 31e: 0000 unimp + 320: 2404 fld fs1,8(s0) + 322: 0b00 addi s0,sp,400 + 324: 030b3e0b 0x30b3e0b + 328: 0008 0x8 + 32a: 0500 addi s0,sp,640 + 32c: 0016 c.slli zero,0x5 + 32e: 0b3a0e03 lb t3,179(s4) + 332: 0b39053b 0xb39053b + 336: 1349 addi t1,t1,-14 + 338: 0000 unimp + 33a: 2606 fld fa2,64(sp) + 33c: 4900 lw s0,16(a0) + 33e: 07000013 li zero,112 + 342: 0101 addi sp,sp,0 + 344: 1349 addi t1,t1,-14 + 346: 1301 addi t1,t1,-32 + 348: 0000 unimp + 34a: 2108 fld fa0,0(a0) + 34c: 4900 lw s0,16(a0) + 34e: 000b2f13 slti t5,s6,0 + 352: 0900 addi s0,sp,144 + 354: 0034 addi a3,sp,8 + 356: 0b3a0e03 lb t3,179(s4) + 35a: 0b390b3b 0xb390b3b + 35e: 1349 addi t1,t1,-14 + 360: 193c193f 130a0000 0x130a0000193c193f + 368: 0b01 addi s6,s6,0 + 36a: 3b0b3a0b 0x3b0b3a0b + 36e: 010b390b 0x10b390b + 372: 0b000013 li zero,176 + 376: 000d c.nop 3 + 378: 0b3a0e03 lb t3,179(s4) + 37c: 0b390b3b 0xb390b3b + 380: 1349 addi t1,t1,-14 + 382: 0b0d0b0b 0xb0d0b0b + 386: 0b0c addi a1,sp,400 + 388: 0b38 addi a4,sp,408 + 38a: 0000 unimp + 38c: 0d0c addi a1,sp,656 + 38e: 0300 addi s0,sp,384 + 390: 3a08 fld fa0,48(a2) + 392: 390b3b0b 0x390b3b0b + 396: 0b13490b 0xb13490b + 39a: 0c0b0d0b 0xc0b0d0b + 39e: 000b380b 0xb380b + 3a2: 0d00 addi s0,sp,656 + 3a4: 0e030117 auipc sp,0xe030 + 3a8: 0b3a0b0b 0xb3a0b0b + 3ac: 0b390b3b 0xb390b3b + 3b0: 1301 addi t1,t1,-32 + 3b2: 0000 unimp + 3b4: 0d0e slli s10,s10,0x3 + 3b6: 0300 addi s0,sp,384 + 3b8: 3a08 fld fa0,48(a2) + 3ba: 390b3b0b 0x390b3b0b + 3be: 0013490b 0x13490b + 3c2: 0f00 addi s0,sp,912 + 3c4: 000d c.nop 3 + 3c6: 0b3a0e03 lb t3,179(s4) + 3ca: 0b390b3b 0xb390b3b + 3ce: 1349 addi t1,t1,-14 + 3d0: 0000 unimp + 3d2: 2e10 fld fa2,24(a2) + 3d4: 3f01 jal 2e4 <_start-0x7ffffd1c> + 3d6: 0319 addi t1,t1,6 + 3d8: 3a0e fld fs4,224(sp) + 3da: 390b3b0b 0x390b3b0b + 3de: 4919270b 0x4919270b + 3e2: 12011113 0x12011113 + 3e6: 4006 0x4006 + 3e8: 9718 0x9718 + 3ea: 1942 slli s2,s2,0x30 + 3ec: 1301 addi t1,t1,-32 + 3ee: 0000 unimp + 3f0: 0511 addi a0,a0,4 + 3f2: 0300 addi s0,sp,384 + 3f4: 3a08 fld fa0,48(a2) + 3f6: 390b3b0b 0x390b3b0b + 3fa: 0213490b 0x213490b + 3fe: 12000017 auipc zero,0x12000 + 402: 0034 addi a3,sp,8 + 404: 0b3a0e03 lb t3,179(s4) + 408: 0b390b3b 0xb390b3b + 40c: 1349 addi t1,t1,-14 + 40e: 1702 slli a4,a4,0x20 + 410: 0000 unimp + 412: 03003413 sltiu s0,zero,48 + 416: 3a0e fld fs4,224(sp) + 418: 390b3b0b 0x390b3b0b + 41c: 1c13490b 0x1c13490b + 420: 1400000b 0x1400000b + 424: 0034 addi a3,sp,8 + 426: 0b3a0803 lb a6,179(s4) + 42a: 0b390b3b 0xb390b3b + 42e: 1349 addi t1,t1,-14 + 430: 0000 unimp + 432: 3415 jal fffffe56 <__global_pointer$+0x7fffc1ee> + 434: 0300 addi s0,sp,384 + 436: 3a08 fld fa0,48(a2) + 438: 390b3b0b 0x390b3b0b + 43c: 0213490b 0x213490b + 440: 16000017 auipc zero,0x16000 + 444: 0034 addi a3,sp,8 + 446: 0b3a0803 lb a6,179(s4) + 44a: 0b390b3b 0xb390b3b + 44e: 1349 addi t1,t1,-14 + 450: 1802 slli a6,a6,0x20 + 452: 0000 unimp + 454: 55010b17 auipc s6,0x55010 + 458: 00130117 auipc sp,0x130 + 45c: 1800 addi s0,sp,48 + 45e: 0034 addi a3,sp,8 + 460: 0b3a0e03 lb t3,179(s4) + 464: 0b390b3b 0xb390b3b + 468: 1349 addi t1,t1,-14 + 46a: 0000 unimp + 46c: 0b19 addi s6,s6,6 + 46e: 0101 addi sp,sp,0 + 470: 1a000013 li zero,416 + 474: 1755010b 0x1755010b + 478: 0000 unimp + 47a: 0100 addi s0,sp,128 + 47c: 0111 addi sp,sp,4 + 47e: 0e25 addi t3,t3,9 + 480: 0e030b13 addi s6,t1,224 + 484: 01110e1b 0x1110e1b + 488: 0612 slli a2,a2,0x4 + 48a: 1710 addi a2,sp,928 + 48c: 0000 unimp + 48e: 2402 fld fs0,0(sp) + 490: 0b00 addi s0,sp,400 + 492: 030b3e0b 0x30b3e0b + 496: 000e c.slli zero,0x3 + 498: 0300 addi s0,sp,384 + 49a: 0024 addi s1,sp,8 + 49c: 0b3e0b0b 0xb3e0b0b + 4a0: 00000803 lb a6,0(zero) # 0 <_start-0x80000000> + 4a4: 1604 addi s1,sp,800 + 4a6: 0300 addi s0,sp,384 + 4a8: 3a0e fld fs4,224(sp) + 4aa: 39053b0b 0x39053b0b + 4ae: 0013490b 0x13490b + 4b2: 0500 addi s0,sp,640 + 4b4: 0026 c.slli zero,0x9 + 4b6: 1349 addi t1,t1,-14 + 4b8: 0000 unimp + 4ba: 0106 slli sp,sp,0x1 + 4bc: 4901 li s2,0 + 4be: 00130113 addi sp,t1,1 + 4c2: 0700 addi s0,sp,896 + 4c4: 0021 c.nop 8 + 4c6: 1349 addi t1,t1,-14 + 4c8: 00000b2f 0xb2f + 4cc: 3408 fld fa0,40(s0) + 4ce: 0300 addi s0,sp,384 + 4d0: 3a0e fld fs4,224(sp) + 4d2: 390b3b0b 0x390b3b0b + 4d6: 3f13490b 0x3f13490b + 4da: 3c19 jal fffffef0 <__global_pointer$+0x7fffc288> + 4dc: 0019 c.nop 6 + 4de: 0900 addi s0,sp,144 + 4e0: 0016 c.slli zero,0x5 + 4e2: 0b3a0e03 lb t3,179(s4) + 4e6: 0b390b3b 0xb390b3b + 4ea: 1349 addi t1,t1,-14 + 4ec: 0000 unimp + 4ee: 130a slli t1,t1,0x22 + 4f0: 0b01 addi s6,s6,0 + 4f2: 3b0b3a0b 0x3b0b3a0b + 4f6: 010b390b 0x10b390b + 4fa: 0b000013 li zero,176 + 4fe: 000d c.nop 3 + 500: 0b3a0e03 lb t3,179(s4) + 504: 0b390b3b 0xb390b3b + 508: 1349 addi t1,t1,-14 + 50a: 0b0d0b0b 0xb0d0b0b + 50e: 0b0c addi a1,sp,400 + 510: 0b38 addi a4,sp,408 + 512: 0000 unimp + 514: 0d0c addi a1,sp,656 + 516: 0300 addi s0,sp,384 + 518: 3a08 fld fa0,48(a2) + 51a: 390b3b0b 0x390b3b0b + 51e: 0b13490b 0xb13490b + 522: 0c0b0d0b 0xc0b0d0b + 526: 000b380b 0xb380b + 52a: 0d00 addi s0,sp,656 + 52c: 0e030117 auipc sp,0xe030 + 530: 0b3a0b0b 0xb3a0b0b + 534: 0b390b3b 0xb390b3b + 538: 1301 addi t1,t1,-32 + 53a: 0000 unimp + 53c: 0d0e slli s10,s10,0x3 + 53e: 0300 addi s0,sp,384 + 540: 3a08 fld fa0,48(a2) + 542: 390b3b0b 0x390b3b0b + 546: 0013490b 0x13490b + 54a: 0f00 addi s0,sp,912 + 54c: 000d c.nop 3 + 54e: 0b3a0e03 lb t3,179(s4) + 552: 0b390b3b 0xb390b3b + 556: 1349 addi t1,t1,-14 + 558: 0000 unimp + 55a: 2e10 fld fa2,24(a2) + 55c: 3f01 jal 46c <_start-0x7ffffb94> + 55e: 0319 addi t1,t1,6 + 560: 3a0e fld fs4,224(sp) + 562: 390b3b0b 0x390b3b0b + 566: 4919270b 0x4919270b + 56a: 12011113 0x12011113 + 56e: 4006 0x4006 + 570: 9618 0x9618 + 572: 1942 slli s2,s2,0x30 + 574: 1301 addi t1,t1,-32 + 576: 0000 unimp + 578: 0511 addi a0,a0,4 + 57a: 0300 addi s0,sp,384 + 57c: 3a08 fld fa0,48(a2) + 57e: 390b3b0b 0x390b3b0b + 582: 0213490b 0x213490b + 586: 12000017 auipc zero,0x12000 + 58a: 0034 addi a3,sp,8 + 58c: 0b3a0e03 lb t3,179(s4) + 590: 0b390b3b 0xb390b3b + 594: 1349 addi t1,t1,-14 + 596: 1702 slli a4,a4,0x20 + 598: 0000 unimp + 59a: 03003413 sltiu s0,zero,48 + 59e: 3a0e fld fs4,224(sp) + 5a0: 390b3b0b 0x390b3b0b + 5a4: 1c13490b 0x1c13490b + 5a8: 1400000b 0x1400000b + 5ac: 0034 addi a3,sp,8 + 5ae: 0b3a0803 lb a6,179(s4) + 5b2: 0b390b3b 0xb390b3b + 5b6: 1349 addi t1,t1,-14 + 5b8: 1702 slli a4,a4,0x20 + 5ba: 0000 unimp + 5bc: 0b15 addi s6,s6,5 + 5be: 5501 li a0,-32 + 5c0: 00130117 auipc sp,0x130 + 5c4: 1600 addi s0,sp,800 + 5c6: 0034 addi a3,sp,8 + 5c8: 0b3a0e03 lb t3,179(s4) + 5cc: 0b390b3b 0xb390b3b + 5d0: 1349 addi t1,t1,-14 + 5d2: 0000 unimp + 5d4: 11010b17 auipc s6,0x11010 + 5d8: 1201 addi tp,tp,-32 + 5da: 0106 slli sp,sp,0x1 + 5dc: 18000013 li zero,384 + 5e0: 1755010b 0x1755010b + 5e4: 0000 unimp + 5e6: 0b19 addi s6,s6,6 + 5e8: 0001 nop + 5ea: 1a00 addi s0,sp,304 + 5ec: 0111010b 0x111010b + 5f0: 0612 slli a2,a2,0x4 + 5f2: 0000 unimp + 5f4: 0100 addi s0,sp,128 + 5f6: 0111 addi sp,sp,4 + 5f8: 0e25 addi t3,t3,9 + 5fa: 0e030b13 addi s6,t1,224 + 5fe: 01110e1b 0x1110e1b + 602: 0612 slli a2,a2,0x4 + 604: 1710 addi a2,sp,928 + 606: 0000 unimp + 608: 2402 fld fs0,0(sp) + 60a: 0b00 addi s0,sp,400 + 60c: 030b3e0b 0x30b3e0b + 610: 000e c.slli zero,0x3 + 612: 0300 addi s0,sp,384 + 614: 0024 addi s1,sp,8 + 616: 0b3e0b0b 0xb3e0b0b + 61a: 00000803 lb a6,0(zero) # 0 <_start-0x80000000> + 61e: 1604 addi s1,sp,800 + 620: 0300 addi s0,sp,384 + 622: 3a0e fld fs4,224(sp) + 624: 39053b0b 0x39053b0b + 628: 0013490b 0x13490b + 62c: 0500 addi s0,sp,640 + 62e: 0026 c.slli zero,0x9 + 630: 1349 addi t1,t1,-14 + 632: 0000 unimp + 634: 0106 slli sp,sp,0x1 + 636: 4901 li s2,0 + 638: 00130113 addi sp,t1,1 + 63c: 0700 addi s0,sp,896 + 63e: 0021 c.nop 8 + 640: 1349 addi t1,t1,-14 + 642: 00000b2f 0xb2f + 646: 3408 fld fa0,40(s0) + 648: 0300 addi s0,sp,384 + 64a: 3a0e fld fs4,224(sp) + 64c: 390b3b0b 0x390b3b0b + 650: 3f13490b 0x3f13490b + 654: 3c19 jal 6a <_start-0x7fffff96> + 656: 0019 c.nop 6 + 658: 0900 addi s0,sp,144 + 65a: 0016 c.slli zero,0x5 + 65c: 0b3a0e03 lb t3,179(s4) + 660: 0b390b3b 0xb390b3b + 664: 1349 addi t1,t1,-14 + 666: 0000 unimp + 668: 130a slli t1,t1,0x22 + 66a: 0b01 addi s6,s6,0 + 66c: 3b0b3a0b 0x3b0b3a0b + 670: 010b390b 0x10b390b + 674: 0b000013 li zero,176 + 678: 000d c.nop 3 + 67a: 0b3a0e03 lb t3,179(s4) + 67e: 0b390b3b 0xb390b3b + 682: 1349 addi t1,t1,-14 + 684: 0b0d0b0b 0xb0d0b0b + 688: 0b0c addi a1,sp,400 + 68a: 0b38 addi a4,sp,408 + 68c: 0000 unimp + 68e: 0d0c addi a1,sp,656 + 690: 0300 addi s0,sp,384 + 692: 3a08 fld fa0,48(a2) + 694: 390b3b0b 0x390b3b0b + 698: 0b13490b 0xb13490b + 69c: 0c0b0d0b 0xc0b0d0b + 6a0: 000b380b 0xb380b + 6a4: 0d00 addi s0,sp,656 + 6a6: 0e030117 auipc sp,0xe030 + 6aa: 0b3a0b0b 0xb3a0b0b + 6ae: 0b390b3b 0xb390b3b + 6b2: 1301 addi t1,t1,-32 + 6b4: 0000 unimp + 6b6: 0d0e slli s10,s10,0x3 + 6b8: 0300 addi s0,sp,384 + 6ba: 3a08 fld fa0,48(a2) + 6bc: 390b3b0b 0x390b3b0b + 6c0: 0013490b 0x13490b + 6c4: 0f00 addi s0,sp,912 + 6c6: 000d c.nop 3 + 6c8: 0b3a0e03 lb t3,179(s4) + 6cc: 0b390b3b 0xb390b3b + 6d0: 1349 addi t1,t1,-14 + 6d2: 0000 unimp + 6d4: 2e10 fld fa2,24(a2) + 6d6: 3f01 jal 5e6 <_start-0x7ffffa1a> + 6d8: 0319 addi t1,t1,6 + 6da: 3a0e fld fs4,224(sp) + 6dc: 390b3b0b 0x390b3b0b + 6e0: 4919270b 0x4919270b + 6e4: 12011113 0x12011113 + 6e8: 4006 0x4006 + 6ea: 9618 0x9618 + 6ec: 1942 slli s2,s2,0x30 + 6ee: 1301 addi t1,t1,-32 + 6f0: 0000 unimp + 6f2: 0511 addi a0,a0,4 + 6f4: 0300 addi s0,sp,384 + 6f6: 3a08 fld fa0,48(a2) + 6f8: 390b3b0b 0x390b3b0b + 6fc: 0213490b 0x213490b + 700: 12000017 auipc zero,0x12000 + 704: 0034 addi a3,sp,8 + 706: 0b3a0e03 lb t3,179(s4) + 70a: 0b390b3b 0xb390b3b + 70e: 1349 addi t1,t1,-14 + 710: 1702 slli a4,a4,0x20 + 712: 0000 unimp + 714: 03003413 sltiu s0,zero,48 + 718: 3a0e fld fs4,224(sp) + 71a: 390b3b0b 0x390b3b0b + 71e: 1c13490b 0x1c13490b + 722: 1400000b 0x1400000b + 726: 0034 addi a3,sp,8 + 728: 0b3a0803 lb a6,179(s4) + 72c: 0b390b3b 0xb390b3b + 730: 1349 addi t1,t1,-14 + 732: 0000 unimp + 734: 3415 jal 158 <_start-0x7ffffea8> + 736: 0300 addi s0,sp,384 + 738: 3a08 fld fa0,48(a2) + 73a: 390b3b0b 0x390b3b0b + 73e: 0213490b 0x213490b + 742: 16000017 auipc zero,0x16000 + 746: 1755010b 0x1755010b + 74a: 1301 addi t1,t1,-32 + 74c: 0000 unimp + 74e: 03003417 auipc s0,0x3003 + 752: 3a0e fld fs4,224(sp) + 754: 390b3b0b 0x390b3b0b + 758: 0013490b 0x13490b + 75c: 1800 addi s0,sp,48 + 75e: 000a c.slli zero,0x2 + 760: 0b3a0e03 lb t3,179(s4) + 764: 0b390b3b 0xb390b3b + 768: 0111 addi sp,sp,4 + 76a: 0000 unimp + 76c: 0b19 addi s6,s6,6 + 76e: 5501 li a0,-32 + 770: 1a000017 auipc zero,0x1a000 + 774: 0000010b 0x10b + 778: 0100 addi s0,sp,128 + 77a: 0111 addi sp,sp,4 + 77c: 0e25 addi t3,t3,9 + 77e: 0e030b13 addi s6,t1,224 + 782: 01110e1b 0x1110e1b + 786: 0612 slli a2,a2,0x4 + 788: 1710 addi a2,sp,928 + 78a: 0000 unimp + 78c: 2402 fld fs0,0(sp) + 78e: 0b00 addi s0,sp,400 + 790: 030b3e0b 0x30b3e0b + 794: 000e c.slli zero,0x3 + 796: 0300 addi s0,sp,384 + 798: 0016 c.slli zero,0x5 + 79a: 0b3a0e03 lb t3,179(s4) + 79e: 0b390b3b 0xb390b3b + 7a2: 1349 addi t1,t1,-14 + 7a4: 0000 unimp + 7a6: 2404 fld fs1,8(s0) + 7a8: 0b00 addi s0,sp,400 + 7aa: 030b3e0b 0x30b3e0b + 7ae: 0008 0x8 + 7b0: 0500 addi s0,sp,640 + 7b2: 0016 c.slli zero,0x5 + 7b4: 0b3a0e03 lb t3,179(s4) + 7b8: 0b39053b 0xb39053b + 7bc: 1349 addi t1,t1,-14 + 7be: 0000 unimp + 7c0: 2606 fld fa2,64(sp) + 7c2: 4900 lw s0,16(a0) + 7c4: 07000013 li zero,112 + 7c8: 0101 addi sp,sp,0 + 7ca: 1349 addi t1,t1,-14 + 7cc: 1301 addi t1,t1,-32 + 7ce: 0000 unimp + 7d0: 2108 fld fa0,0(a0) + 7d2: 4900 lw s0,16(a0) + 7d4: 000b2f13 slti t5,s6,0 + 7d8: 0900 addi s0,sp,144 + 7da: 0034 addi a3,sp,8 + 7dc: 0b3a0e03 lb t3,179(s4) + 7e0: 0b390b3b 0xb390b3b + 7e4: 1349 addi t1,t1,-14 + 7e6: 193c193f 130a0000 0x130a0000193c193f + 7ee: 0b01 addi s6,s6,0 + 7f0: 3b0b3a0b 0x3b0b3a0b + 7f4: 010b390b 0x10b390b + 7f8: 0b000013 li zero,176 + 7fc: 000d c.nop 3 + 7fe: 0b3a0e03 lb t3,179(s4) + 802: 0b390b3b 0xb390b3b + 806: 1349 addi t1,t1,-14 + 808: 0b0d0b0b 0xb0d0b0b + 80c: 0b0c addi a1,sp,400 + 80e: 0b38 addi a4,sp,408 + 810: 0000 unimp + 812: 0d0c addi a1,sp,656 + 814: 0300 addi s0,sp,384 + 816: 3a08 fld fa0,48(a2) + 818: 390b3b0b 0x390b3b0b + 81c: 0b13490b 0xb13490b + 820: 0c0b0d0b 0xc0b0d0b + 824: 000b380b 0xb380b + 828: 0d00 addi s0,sp,656 + 82a: 0e030117 auipc sp,0xe030 + 82e: 0b3a0b0b 0xb3a0b0b + 832: 0b390b3b 0xb390b3b + 836: 1301 addi t1,t1,-32 + 838: 0000 unimp + 83a: 0d0e slli s10,s10,0x3 + 83c: 0300 addi s0,sp,384 + 83e: 3a08 fld fa0,48(a2) + 840: 390b3b0b 0x390b3b0b + 844: 0013490b 0x13490b + 848: 0f00 addi s0,sp,912 + 84a: 000d c.nop 3 + 84c: 0b3a0e03 lb t3,179(s4) + 850: 0b390b3b 0xb390b3b + 854: 1349 addi t1,t1,-14 + 856: 0000 unimp + 858: 2e10 fld fa2,24(a2) + 85a: 3f01 jal 76a <_start-0x7ffff896> + 85c: 0319 addi t1,t1,6 + 85e: 3a0e fld fs4,224(sp) + 860: 390b3b0b 0x390b3b0b + 864: 4919270b 0x4919270b + 868: 12011113 0x12011113 + 86c: 4006 0x4006 + 86e: 9718 0x9718 + 870: 1942 slli s2,s2,0x30 + 872: 1301 addi t1,t1,-32 + 874: 0000 unimp + 876: 0511 addi a0,a0,4 + 878: 0300 addi s0,sp,384 + 87a: 3a08 fld fa0,48(a2) + 87c: 390b3b0b 0x390b3b0b + 880: 0213490b 0x213490b + 884: 12000017 auipc zero,0x12000 + 888: 0034 addi a3,sp,8 + 88a: 0b3a0e03 lb t3,179(s4) + 88e: 0b390b3b 0xb390b3b + 892: 1349 addi t1,t1,-14 + 894: 0b1c addi a5,sp,400 + 896: 0000 unimp + 898: 03003413 sltiu s0,zero,48 + 89c: 3a08 fld fa0,48(a2) + 89e: 390b3b0b 0x390b3b0b + 8a2: 0013490b 0x13490b + 8a6: 1400 addi s0,sp,544 + 8a8: 0034 addi a3,sp,8 + 8aa: 0b3a0803 lb a6,179(s4) + 8ae: 0b390b3b 0xb390b3b + 8b2: 1349 addi t1,t1,-14 + 8b4: 1702 slli a4,a4,0x20 + 8b6: 0000 unimp + 8b8: 3415 jal 2dc <_start-0x7ffffd24> + 8ba: 0300 addi s0,sp,384 + 8bc: 3a08 fld fa0,48(a2) + 8be: 390b3b0b 0x390b3b0b + 8c2: 0213490b 0x213490b + 8c6: 0018 0x18 + 8c8: 1600 addi s0,sp,800 + 8ca: 0111010b 0x111010b + 8ce: 0612 slli a2,a2,0x4 + 8d0: 1301 addi t1,t1,-32 + 8d2: 0000 unimp + 8d4: 03003417 auipc s0,0x3003 + 8d8: 3a0e fld fs4,224(sp) + 8da: 390b3b0b 0x390b3b0b + 8de: 0013490b 0x13490b + 8e2: 1800 addi s0,sp,48 + 8e4: 1755010b 0x1755010b + 8e8: 1301 addi t1,t1,-32 + 8ea: 0000 unimp + 8ec: 0b19 addi s6,s6,6 + 8ee: 0101 addi sp,sp,0 + 8f0: 1a000013 li zero,416 + 8f4: 0000010b 0x10b + 8f8: 0100 addi s0,sp,128 + 8fa: 0111 addi sp,sp,4 + 8fc: 0e25 addi t3,t3,9 + 8fe: 0e030b13 addi s6,t1,224 + 902: 01110e1b 0x1110e1b + 906: 0612 slli a2,a2,0x4 + 908: 1710 addi a2,sp,928 + 90a: 0000 unimp + 90c: 2402 fld fs0,0(sp) + 90e: 0b00 addi s0,sp,400 + 910: 030b3e0b 0x30b3e0b + 914: 0008 0x8 + 916: 0300 addi s0,sp,384 + 918: 0024 addi s1,sp,8 + 91a: 0b3e0b0b 0xb3e0b0b + 91e: 00000e03 lb t3,0(zero) # 0 <_start-0x80000000> + 922: 1604 addi s1,sp,800 + 924: 0300 addi s0,sp,384 + 926: 3a0e fld fs4,224(sp) + 928: 39053b0b 0x39053b0b + 92c: 0013490b 0x13490b + 930: 0500 addi s0,sp,640 + 932: 0016 c.slli zero,0x5 + 934: 0b3a0e03 lb t3,179(s4) + 938: 0b390b3b 0xb390b3b + 93c: 1349 addi t1,t1,-14 + 93e: 0000 unimp + 940: 1706 slli a4,a4,0x21 + 942: 0b01 addi s6,s6,0 + 944: 3b0b3a0b 0x3b0b3a0b + 948: 010b390b 0x10b390b + 94c: 07000013 li zero,112 + 950: 000d c.nop 3 + 952: 0b3a0e03 lb t3,179(s4) + 956: 0b390b3b 0xb390b3b + 95a: 1349 addi t1,t1,-14 + 95c: 0000 unimp + 95e: 0108 addi a0,sp,128 + 960: 4901 li s2,0 + 962: 00130113 addi sp,t1,1 + 966: 0900 addi s0,sp,144 + 968: 0021 c.nop 8 + 96a: 1349 addi t1,t1,-14 + 96c: 00000b2f 0xb2f + 970: 130a slli t1,t1,0x22 + 972: 0b01 addi s6,s6,0 + 974: 3b0b3a0b 0x3b0b3a0b + 978: 010b390b 0x10b390b + 97c: 0b000013 li zero,176 + 980: 000d c.nop 3 + 982: 0b3a0e03 lb t3,179(s4) + 986: 0b390b3b 0xb390b3b + 98a: 1349 addi t1,t1,-14 + 98c: 0b38 addi a4,sp,408 + 98e: 0000 unimp + 990: 0f0c addi a1,sp,912 + 992: 0b00 addi s0,sp,400 + 994: 0d00000b 0xd00000b + 998: 0e030113 addi sp,t1,224 + 99c: 0b3a0b0b 0xb3a0b0b + 9a0: 0b390b3b 0xb390b3b + 9a4: 1301 addi t1,t1,-32 + 9a6: 0000 unimp + 9a8: 0d0e slli s10,s10,0x3 + 9aa: 0300 addi s0,sp,384 + 9ac: 3a08 fld fa0,48(a2) + 9ae: 390b3b0b 0x390b3b0b + 9b2: 3813490b 0x3813490b + 9b6: 0f00000b 0xf00000b + 9ba: 0b0b000f 0xb0b000f + 9be: 1349 addi t1,t1,-14 + 9c0: 0000 unimp + 9c2: 1310 addi a2,sp,416 + 9c4: 0301 addi t1,t1,0 + 9c6: 0b0e slli s6,s6,0x3 + 9c8: 3a05 jal 2f8 <_start-0x7ffffd08> + 9ca: 390b3b0b 0x390b3b0b + 9ce: 0013010b 0x13010b + 9d2: 1100 addi s0,sp,160 + 9d4: 000d c.nop 3 + 9d6: 0b3a0e03 lb t3,179(s4) + 9da: 0b390b3b 0xb390b3b + 9de: 1349 addi t1,t1,-14 + 9e0: 0538 addi a4,sp,648 + 9e2: 0000 unimp + 9e4: 1512 slli a0,a0,0x24 + 9e6: 2700 fld fs0,8(a4) + 9e8: 0019 c.nop 6 + 9ea: 1300 addi s0,sp,416 + 9ec: 0115 addi sp,sp,5 + 9ee: 13491927 0x13491927 + 9f2: 1301 addi t1,t1,-32 + 9f4: 0000 unimp + 9f6: 0514 addi a3,sp,640 + 9f8: 4900 lw s0,16(a0) + 9fa: 15000013 li zero,336 + 9fe: 0026 c.slli zero,0x9 + a00: 1349 addi t1,t1,-14 + a02: 0000 unimp + a04: 1316 slli t1,t1,0x25 + a06: 0301 addi t1,t1,0 + a08: 0b0e slli s6,s6,0x3 + a0a: 3a05 jal 33a <_start-0x7ffffcc6> + a0c: 39053b0b 0x39053b0b + a10: 0013010b 0x13010b + a14: 1700 addi s0,sp,928 + a16: 000d c.nop 3 + a18: 0b3a0e03 lb t3,179(s4) + a1c: 0b39053b 0xb39053b + a20: 1349 addi t1,t1,-14 + a22: 0b38 addi a4,sp,408 + a24: 0000 unimp + a26: 0d18 addi a4,sp,656 + a28: 0300 addi s0,sp,384 + a2a: 3a0e fld fs4,224(sp) + a2c: 39053b0b 0x39053b0b + a30: 3813490b 0x3813490b + a34: 0005 c.nop 1 + a36: 1900 addi s0,sp,176 + a38: 0e030113 addi sp,t1,224 + a3c: 0b3a0b0b 0xb3a0b0b + a40: 0b39053b 0xb39053b + a44: 1301 addi t1,t1,-32 + a46: 0000 unimp + a48: 131a slli t1,t1,0x26 + a4a: 0b01 addi s6,s6,0 + a4c: 3b0b3a0b 0x3b0b3a0b + a50: 3905 jal 680 <_start-0x7ffff980> + a52: 0013010b 0x13010b + a56: 1b00 addi s0,sp,432 + a58: 0b0b0117 auipc sp,0xb0b0 + a5c: 0b3a slli s6,s6,0xe + a5e: 0b39053b 0xb39053b + a62: 1301 addi t1,t1,-32 + a64: 0000 unimp + a66: 0d1c addi a5,sp,656 + a68: 0300 addi s0,sp,384 + a6a: 3a0e fld fs4,224(sp) + a6c: 39053b0b 0x39053b0b + a70: 0013490b 0x13490b + a74: 1d00 addi s0,sp,688 + a76: 0e030013 addi zero,t1,224 + a7a: 193c addi a5,sp,184 + a7c: 0000 unimp + a7e: 151e slli a0,a0,0x27 + a80: 2701 jal 1180 <_start-0x7fffee80> + a82: 0119 addi sp,sp,6 + a84: 1f000013 li zero,496 + a88: 0034 addi a3,sp,8 + a8a: 0b3a0e03 lb t3,179(s4) + a8e: 0b39053b 0xb39053b + a92: 1349 addi t1,t1,-14 + a94: 193c193f 21200000 0x21200000193c193f + a9c: 0000 unimp + a9e: 2100 fld fs0,0(a0) + aa0: 0034 addi a3,sp,8 + aa2: 0b3a0e03 lb t3,179(s4) + aa6: 0b390b3b 0xb390b3b + aaa: 1349 addi t1,t1,-14 + aac: 193c193f 26220000 0x26220000193c193f + ab4: 0000 unimp + ab6: 2300 fld fs0,0(a4) + ab8: 0104 addi s1,sp,128 + aba: 0b3e0e03 lb t3,179(t3) # 9148f <_start-0x7ff6eb71> + abe: 13490b0b 0x13490b0b + ac2: 0b3a slli s6,s6,0xe + ac4: 0b390b3b 0xb390b3b + ac8: 1301 addi t1,t1,-32 + aca: 0000 unimp + acc: 2824 fld fs1,80(s0) + ace: 0300 addi s0,sp,384 + ad0: 1c0e slli s8,s8,0x23 + ad2: 2500000b 0x2500000b + ad6: 012e slli sp,sp,0xb + ad8: 0e03193f 053b0b3a 0x53b0b3a0e03193f + ae0: 0b39 addi s6,s6,14 + ae2: 13491927 0x13491927 + ae6: 0111 addi sp,sp,4 + ae8: 0612 slli a2,a2,0x4 + aea: 1840 addi s0,sp,52 + aec: 00194297 auipc t0,0x194 + af0: 2600 fld fs0,8(a2) + af2: 0005 c.nop 1 + af4: 0b3a0803 lb a6,179(s4) + af8: 0b39053b 0xb39053b + afc: 1349 addi t1,t1,-14 + afe: 1702 slli a4,a4,0x20 + b00: 0000 unimp + b02: 03003427 fsd fa6,40(zero) # 28 <_start-0x7fffffd8> + b06: 3a08 fld fa0,48(a2) + b08: 39053b0b 0x39053b0b + b0c: 0013490b 0x13490b + b10: 2800 fld fs0,16(s0) + b12: 1755010b 0x1755010b + b16: 0000 unimp + b18: 3429 jal 522 <_start-0x7ffffade> + b1a: 0300 addi s0,sp,384 + b1c: 3a0e fld fs4,224(sp) + b1e: 39053b0b 0x39053b0b + b22: 0213490b 0x213490b + b26: 2a000017 auipc zero,0x2a000 + b2a: 0034 addi a3,sp,8 + b2c: 0b3a0803 lb a6,179(s4) + b30: 0b39053b 0xb39053b + b34: 1349 addi t1,t1,-14 + b36: 1702 slli a4,a4,0x20 + b38: 0000 unimp + b3a: 0100 addi s0,sp,128 + b3c: 0111 addi sp,sp,4 + b3e: 0e25 addi t3,t3,9 + b40: 0e030b13 addi s6,t1,224 + b44: 17100e1b 0x17100e1b + b48: 0000 unimp + b4a: 2402 fld fs0,0(sp) + b4c: 0b00 addi s0,sp,400 + b4e: 030b3e0b 0x30b3e0b + b52: 0008 0x8 + b54: 0300 addi s0,sp,384 + b56: 0024 addi s1,sp,8 + b58: 0b3e0b0b 0xb3e0b0b + b5c: 00000e03 lb t3,0(zero) # 0 <_start-0x80000000> + b60: 1604 addi s1,sp,800 + b62: 0300 addi s0,sp,384 + b64: 3a0e fld fs4,224(sp) + b66: 39053b0b 0x39053b0b + b6a: 0013490b 0x13490b + b6e: 0500 addi s0,sp,640 + b70: 0016 c.slli zero,0x5 + b72: 0b3a0e03 lb t3,179(s4) + b76: 0b390b3b 0xb390b3b + b7a: 1349 addi t1,t1,-14 + b7c: 0000 unimp + b7e: 1706 slli a4,a4,0x21 + b80: 0b01 addi s6,s6,0 + b82: 3b0b3a0b 0x3b0b3a0b + b86: 010b390b 0x10b390b + b8a: 07000013 li zero,112 + b8e: 000d c.nop 3 + b90: 0b3a0e03 lb t3,179(s4) + b94: 0b390b3b 0xb390b3b + b98: 1349 addi t1,t1,-14 + b9a: 0000 unimp + b9c: 0108 addi a0,sp,128 + b9e: 4901 li s2,0 + ba0: 00130113 addi sp,t1,1 + ba4: 0900 addi s0,sp,144 + ba6: 0021 c.nop 8 + ba8: 1349 addi t1,t1,-14 + baa: 00000b2f 0xb2f + bae: 130a slli t1,t1,0x22 + bb0: 0b01 addi s6,s6,0 + bb2: 3b0b3a0b 0x3b0b3a0b + bb6: 010b390b 0x10b390b + bba: 0b000013 li zero,176 + bbe: 000d c.nop 3 + bc0: 0b3a0e03 lb t3,179(s4) + bc4: 0b390b3b 0xb390b3b + bc8: 1349 addi t1,t1,-14 + bca: 0b38 addi a4,sp,408 + bcc: 0000 unimp + bce: 0f0c addi a1,sp,912 + bd0: 0b00 addi s0,sp,400 + bd2: 0d00000b 0xd00000b + bd6: 0e030113 addi sp,t1,224 + bda: 0b3a0b0b 0xb3a0b0b + bde: 0b390b3b 0xb390b3b + be2: 1301 addi t1,t1,-32 + be4: 0000 unimp + be6: 0d0e slli s10,s10,0x3 + be8: 0300 addi s0,sp,384 + bea: 3a08 fld fa0,48(a2) + bec: 390b3b0b 0x390b3b0b + bf0: 3813490b 0x3813490b + bf4: 0f00000b 0xf00000b + bf8: 0b0b000f 0xb0b000f + bfc: 1349 addi t1,t1,-14 + bfe: 0000 unimp + c00: 1310 addi a2,sp,416 + c02: 0301 addi t1,t1,0 + c04: 0b0e slli s6,s6,0x3 + c06: 3a05 jal 536 <_start-0x7ffffaca> + c08: 390b3b0b 0x390b3b0b + c0c: 0013010b 0x13010b + c10: 1100 addi s0,sp,160 + c12: 000d c.nop 3 + c14: 0b3a0e03 lb t3,179(s4) + c18: 0b390b3b 0xb390b3b + c1c: 1349 addi t1,t1,-14 + c1e: 0538 addi a4,sp,648 + c20: 0000 unimp + c22: 1512 slli a0,a0,0x24 + c24: 2700 fld fs0,8(a4) + c26: 0019 c.nop 6 + c28: 1300 addi s0,sp,416 + c2a: 0115 addi sp,sp,5 + c2c: 13491927 0x13491927 + c30: 1301 addi t1,t1,-32 + c32: 0000 unimp + c34: 0514 addi a3,sp,640 + c36: 4900 lw s0,16(a0) + c38: 15000013 li zero,336 + c3c: 0026 c.slli zero,0x9 + c3e: 1349 addi t1,t1,-14 + c40: 0000 unimp + c42: 1316 slli t1,t1,0x25 + c44: 0301 addi t1,t1,0 + c46: 0b0e slli s6,s6,0x3 + c48: 3a05 jal 578 <_start-0x7ffffa88> + c4a: 39053b0b 0x39053b0b + c4e: 0013010b 0x13010b + c52: 1700 addi s0,sp,928 + c54: 000d c.nop 3 + c56: 0b3a0e03 lb t3,179(s4) + c5a: 0b39053b 0xb39053b + c5e: 1349 addi t1,t1,-14 + c60: 0b38 addi a4,sp,408 + c62: 0000 unimp + c64: 0d18 addi a4,sp,656 + c66: 0300 addi s0,sp,384 + c68: 3a0e fld fs4,224(sp) + c6a: 39053b0b 0x39053b0b + c6e: 3813490b 0x3813490b + c72: 0005 c.nop 1 + c74: 1900 addi s0,sp,176 + c76: 0e030113 addi sp,t1,224 + c7a: 0b3a0b0b 0xb3a0b0b + c7e: 0b39053b 0xb39053b + c82: 1301 addi t1,t1,-32 + c84: 0000 unimp + c86: 131a slli t1,t1,0x26 + c88: 0b01 addi s6,s6,0 + c8a: 3b0b3a0b 0x3b0b3a0b + c8e: 3905 jal 8be <_start-0x7ffff742> + c90: 0013010b 0x13010b + c94: 1b00 addi s0,sp,432 + c96: 0b0b0117 auipc sp,0xb0b0 + c9a: 0b3a slli s6,s6,0xe + c9c: 0b39053b 0xb39053b + ca0: 1301 addi t1,t1,-32 + ca2: 0000 unimp + ca4: 0d1c addi a5,sp,656 + ca6: 0300 addi s0,sp,384 + ca8: 3a0e fld fs4,224(sp) + caa: 39053b0b 0x39053b0b + cae: 0013490b 0x13490b + cb2: 1d00 addi s0,sp,688 + cb4: 0e030013 addi zero,t1,224 + cb8: 193c addi a5,sp,184 + cba: 0000 unimp + cbc: 151e slli a0,a0,0x27 + cbe: 2701 jal 13be <_start-0x7fffec42> + cc0: 0119 addi sp,sp,6 + cc2: 1f000013 li zero,496 + cc6: 0034 addi a3,sp,8 + cc8: 0b3a0e03 lb t3,179(s4) + ccc: 0b39053b 0xb39053b + cd0: 1349 addi t1,t1,-14 + cd2: 193c193f 21200000 0x21200000193c193f + cda: 0000 unimp + cdc: 2100 fld fs0,0(a0) + cde: 0034 addi a3,sp,8 + ce0: 0b3a0e03 lb t3,179(s4) + ce4: 0b390b3b 0xb390b3b + ce8: 1349 addi t1,t1,-14 + cea: 193c193f 26220000 0x26220000193c193f + cf2: 0000 unimp + cf4: 2300 fld fs0,0(a4) + cf6: 0104 addi s1,sp,128 + cf8: 0b3e0e03 lb t3,179(t3) + cfc: 13490b0b 0x13490b0b + d00: 0b3a slli s6,s6,0xe + d02: 0b390b3b 0xb390b3b + d06: 1301 addi t1,t1,-32 + d08: 0000 unimp + d0a: 2824 fld fs1,80(s0) + d0c: 0300 addi s0,sp,384 + d0e: 1c0e slli s8,s8,0x23 + d10: 2500000b 0x2500000b + d14: 0034 addi a3,sp,8 + d16: 0b3a1347 fmsub.d ft6,fs4,fs3,ft1,rtz + d1a: 0b39053b 0xb39053b + d1e: 1802 slli a6,a6,0x20 + d20: 0000 unimp + ... + +Disassembly of section .debug_line: + +00000000 <.debug_line>: + 0: 0a4a slli s4,s4,0x12 + 2: 0000 unimp + 4: 00930003 lb zero,9(t1) + 8: 0000 unimp + a: 0101 addi sp,sp,0 + c: 000d0efb 0xd0efb + 10: 0101 addi sp,sp,0 + 12: 0101 addi sp,sp,0 + 14: 0000 unimp + 16: 0100 addi s0,sp,128 + 18: 0000 unimp + 1a: 2e01 jal 32a <_start-0x7ffffcd6> + 1c: 2f2e fld ft10,200(sp) + 1e: 2e2e fld ft8,200(sp) + 20: 2f2e2e2f 0x2f2e2e2f + 24: 2e2e fld ft8,200(sp) + 26: 7369722f 0x7369722f + 2a: 672d7663 bgeu s10,s2,696 <_start-0x7ffff96a> + 2e: 6c2f6363 bltu t5,sp,6f4 <_start-0x7ffff90c> + 32: 6269 lui tp,0x1a + 34: 2f636367 0x2f636367 + 38: 74666f73 csrrsi t5,0x746,12 + 3c: 662d lui a2,0xb + 3e: 0070 addi a2,sp,12 + 40: 2e2e fld ft8,200(sp) + 42: 2f2e2e2f 0x2f2e2e2f + 46: 2e2e fld ft8,200(sp) + 48: 2f2e2e2f 0x2f2e2e2f + 4c: 6972 flw fs2,28(sp) + 4e: 2d766373 csrrsi t1,0x2d7,12 + 52: 2f636367 0x2f636367 + 56: 696c flw fa1,84(a0) + 58: 6762 flw fa4,24(sp) + 5a: 2e2f6363 bltu t5,sp,340 <_start-0x7ffffcc0> + 5e: 2f2e fld ft10,200(sp) + 60: 6e69 lui t3,0x1a + 62: 64756c63 bltu a0,t2,6ba <_start-0x7ffff946> + 66: 0065 c.nop 25 + 68: 6100 flw fs0,0(a0) + 6a: 6464 flw fs1,76(s0) + 6c: 2e336673 csrrsi a2,0x2e3,6 + 70: 00010063 beqz sp,70 <_start-0x7fffff90> + 74: 7300 flw fs0,32(a4) + 76: 2d74666f jal a2,46b4c <_start-0x7ffb94b4> + 7a: 7066 flw ft0,120(sp) + 7c: 682e flw fa6,200(sp) + 7e: 0100 addi s0,sp,128 + 80: 0000 unimp + 82: 676e6973 csrrsi s2,0x676,28 + 86: 656c flw fa1,76(a0) + 88: 682e flw fa6,200(sp) + 8a: 0100 addi s0,sp,128 + 8c: 0000 unimp + 8e: 6f6c flw fa1,92(a4) + 90: 676e flw fa4,216(sp) + 92: 6f6c flw fa1,92(a4) + 94: 676e flw fa4,216(sp) + 96: 682e flw fa6,200(sp) + 98: 0200 addi s0,sp,256 + 9a: 0000 unimp + 9c: 0500 addi s0,sp,640 + 9e: 0001 nop + a0: 0205 addi tp,tp,1 + a2: 0ee8 addi a0,sp,860 + a4: 8000 0x8000 + a6: 05012303 lw t1,80(sp) # b0b0ce6 <_start-0x74f4f31a> + aa: 09010303 lb t1,144(sp) + ae: 0000 unimp + b0: 0301 addi t1,t1,0 + b2: 0900 addi s0,sp,144 + b4: 0000 unimp + b6: 0501 addi a0,a0,0 + b8: 030d addi t1,t1,3 + ba: 0900 addi s0,sp,144 + bc: 0000 unimp + be: 0501 addi a0,a0,0 + c0: 09010303 lb t1,144(sp) + c4: 0000 unimp + c6: 0301 addi t1,t1,0 + c8: 0900 addi s0,sp,144 + ca: 0000 unimp + cc: 0301 addi t1,t1,0 + ce: 0900 addi s0,sp,144 + d0: 0000 unimp + d2: 0301 addi t1,t1,0 + d4: 0900 addi s0,sp,144 + d6: 0000 unimp + d8: 0301 addi t1,t1,0 + da: 0901 addi s2,s2,0 + dc: 0000 unimp + de: 0301 addi t1,t1,0 + e0: 0900 addi s0,sp,144 + e2: 0000 unimp + e4: 0301 addi t1,t1,0 + e6: 0900 addi s0,sp,144 + e8: 0000 unimp + ea: 0301 addi t1,t1,0 + ec: 0900 addi s0,sp,144 + ee: 0000 unimp + f0: 0301 addi t1,t1,0 + f2: 0901 addi s2,s2,0 + f4: 0000 unimp + f6: 0301 addi t1,t1,0 + f8: 0900 addi s0,sp,144 + fa: 0000 unimp + fc: 0301 addi t1,t1,0 + fe: 0900 addi s0,sp,144 + 100: 0000 unimp + 102: 0301 addi t1,t1,0 + 104: 0900 addi s0,sp,144 + 106: 0000 unimp + 108: 0301 addi t1,t1,0 + 10a: 0901 addi s2,s2,0 + 10c: 0000 unimp + 10e: 0301 addi t1,t1,0 + 110: 0902 c.slli64 s2 + 112: 0000 unimp + 114: 0301 addi t1,t1,0 + 116: 0901 addi s2,s2,0 + 118: 0000 unimp + 11a: 0301 addi t1,t1,0 + 11c: 0900 addi s0,sp,144 + 11e: 0000 unimp + 120: 0301 addi t1,t1,0 + 122: 0900 addi s0,sp,144 + 124: 0000 unimp + 126: 0301 addi t1,t1,0 + 128: 0900 addi s0,sp,144 + 12a: 0000 unimp + 12c: 0301 addi t1,t1,0 + 12e: 0900 addi s0,sp,144 + 130: 0000 unimp + 132: 0501 addi a0,a0,0 + 134: 0601 addi a2,a2,0 + 136: 00097803 0x97803 + 13a: 0100 addi s0,sp,128 + 13c: 0305 addi t1,t1,1 + 13e: 08090803 lb a6,128(s2) # 5e3ec <_start-0x7ffa1c14> + 142: 0100 addi s0,sp,128 + 144: 0105 addi sp,sp,1 + 146: 08097803 0x8097803 + 14a: 0100 addi s0,sp,128 + 14c: 0305 addi t1,t1,1 + 14e: 0c090803 lb a6,192(s2) + 152: 0100 addi s0,sp,128 + 154: 0306 slli t1,t1,0x1 + 156: 0900 addi s0,sp,144 + 158: 0004 0x4 + 15a: 0301 addi t1,t1,0 + 15c: 0900 addi s0,sp,144 + 15e: 0000 unimp + 160: 0501 addi a0,a0,0 + 162: 0601 addi a2,a2,0 + 164: 00097803 0x97803 + 168: 0100 addi s0,sp,128 + 16a: 0305 addi t1,t1,1 + 16c: 04090903 lb s2,64(s2) + 170: 0100 addi s0,sp,128 + 172: 0105 addi sp,sp,1 + 174: 08097703 0x8097703 + 178: 0100 addi s0,sp,128 + 17a: 0305 addi t1,t1,1 + 17c: 08090803 lb a6,128(s2) + 180: 0100 addi s0,sp,128 + 182: 0306 slli t1,t1,0x1 + 184: 0900 addi s0,sp,144 + 186: 0004 0x4 + 188: 0301 addi t1,t1,0 + 18a: 0900 addi s0,sp,144 + 18c: 0000 unimp + 18e: 0301 addi t1,t1,0 + 190: 0900 addi s0,sp,144 + 192: 0000 unimp + 194: 0301 addi t1,t1,0 + 196: 0900 addi s0,sp,144 + 198: 0000 unimp + 19a: 0601 addi a2,a2,0 + 19c: 00090103 lb sp,0(s2) + 1a0: 0100 addi s0,sp,128 + 1a2: 04097f03 0x4097f03 + 1a6: 0100 addi s0,sp,128 + 1a8: 0306 slli t1,t1,0x1 + 1aa: 0900 addi s0,sp,144 + 1ac: 0004 0x4 + 1ae: 0301 addi t1,t1,0 + 1b0: 0900 addi s0,sp,144 + 1b2: 0000 unimp + 1b4: 0301 addi t1,t1,0 + 1b6: 0901 addi s2,s2,0 + 1b8: 0000 unimp + 1ba: 0301 addi t1,t1,0 + 1bc: 0900 addi s0,sp,144 + 1be: 0000 unimp + 1c0: 0301 addi t1,t1,0 + 1c2: 0900 addi s0,sp,144 + 1c4: 0000 unimp + 1c6: 0301 addi t1,t1,0 + 1c8: 0900 addi s0,sp,144 + 1ca: 0000 unimp + 1cc: 0301 addi t1,t1,0 + 1ce: 0900 addi s0,sp,144 + 1d0: 0000 unimp + 1d2: 0301 addi t1,t1,0 + 1d4: 0900 addi s0,sp,144 + 1d6: 0000 unimp + 1d8: 0301 addi t1,t1,0 + 1da: 0900 addi s0,sp,144 + 1dc: 0000 unimp + 1de: 0301 addi t1,t1,0 + 1e0: 0900 addi s0,sp,144 + 1e2: 0000 unimp + 1e4: 0301 addi t1,t1,0 + 1e6: 0900 addi s0,sp,144 + 1e8: 0000 unimp + 1ea: 0301 addi t1,t1,0 + 1ec: 0900 addi s0,sp,144 + 1ee: 0000 unimp + 1f0: 0301 addi t1,t1,0 + 1f2: 0900 addi s0,sp,144 + 1f4: 0000 unimp + 1f6: 0301 addi t1,t1,0 + 1f8: 0900 addi s0,sp,144 + 1fa: 0004 0x4 + 1fc: 0301 addi t1,t1,0 + 1fe: 0900 addi s0,sp,144 + 200: 0000 unimp + 202: 0301 addi t1,t1,0 + 204: 0901 addi s2,s2,0 + 206: 0000 unimp + 208: 0301 addi t1,t1,0 + 20a: 0900 addi s0,sp,144 + 20c: 0000 unimp + 20e: 0301 addi t1,t1,0 + 210: 0900 addi s0,sp,144 + 212: 0000 unimp + 214: 0301 addi t1,t1,0 + 216: 0900 addi s0,sp,144 + 218: 0000 unimp + 21a: 0301 addi t1,t1,0 + 21c: 0900 addi s0,sp,144 + 21e: 0000 unimp + 220: 0301 addi t1,t1,0 + 222: 0900 addi s0,sp,144 + 224: 0000 unimp + 226: 0301 addi t1,t1,0 + 228: 0900 addi s0,sp,144 + 22a: 0000 unimp + 22c: 0301 addi t1,t1,0 + 22e: 0900 addi s0,sp,144 + 230: 0000 unimp + 232: 0001 nop + 234: 0402 c.slli64 s0 + 236: 09000307 0x9000307 + 23a: 0008 0x8 + 23c: 0001 nop + 23e: 0402 c.slli64 s0 + 240: 09000307 0x9000307 + 244: 0000 unimp + 246: 0001 nop + 248: 0402 c.slli64 s0 + 24a: 09000307 0x9000307 + 24e: 0000 unimp + 250: 0001 nop + 252: 0402 c.slli64 s0 + 254: 0309 addi t1,t1,2 + 256: 0900 addi s0,sp,144 + 258: 0004 0x4 + 25a: 0001 nop + 25c: 0402 c.slli64 s0 + 25e: 0309 addi t1,t1,2 + 260: 0900 addi s0,sp,144 + 262: 0000 unimp + 264: 0001 nop + 266: 0402 c.slli64 s0 + 268: 0900030b 0x900030b + 26c: 0004 0x4 + 26e: 0001 nop + 270: 0402 c.slli64 s0 + 272: 030e slli t1,t1,0x3 + 274: 0900 addi s0,sp,144 + 276: 0004 0x4 + 278: 0001 nop + 27a: 0402 c.slli64 s0 + 27c: 030e slli t1,t1,0x3 + 27e: 0900 addi s0,sp,144 + 280: 0000 unimp + 282: 0001 nop + 284: 0402 c.slli64 s0 + 286: 030e slli t1,t1,0x3 + 288: 0900 addi s0,sp,144 + 28a: 0004 0x4 + 28c: 0001 nop + 28e: 0402 c.slli64 s0 + 290: 09000317 auipc t1,0x9000 + 294: 0004 0x4 + 296: 0001 nop + 298: 0402 c.slli64 s0 + 29a: 09000317 auipc t1,0x9000 + 29e: 0004 0x4 + 2a0: 0001 nop + 2a2: 0402 c.slli64 s0 + 2a4: 7e03063b 0x7e03063b + 2a8: 0009 c.nop 2 + 2aa: 0100 addi s0,sp,128 + 2ac: 0200 addi s0,sp,256 + 2ae: 7004 flw fs1,32(s0) + 2b0: 0306 slli t1,t1,0x1 + 2b2: 0902 c.slli64 s2 + 2b4: 0004 0x4 + 2b6: 0001 nop + 2b8: 01ab0403 lb s0,26(s6) # 110105ee <_start-0x6efefa12> + 2bc: 08090003 lb zero,128(s2) + 2c0: 0100 addi s0,sp,128 + 2c2: 0300 addi s0,sp,384 + 2c4: ab04 fsd fs1,16(a4) + 2c6: 0301 addi t1,t1,0 + 2c8: 0900 addi s0,sp,144 + 2ca: 0000 unimp + 2cc: 0001 nop + 2ce: 01ab0403 lb s0,26(s6) + 2d2: 04090003 lb zero,64(s2) + 2d6: 0100 addi s0,sp,128 + 2d8: 0300 addi s0,sp,384 + 2da: ab04 fsd fs1,16(a4) + 2dc: 0301 addi t1,t1,0 + 2de: 0900 addi s0,sp,144 + 2e0: 0000 unimp + 2e2: 0601 addi a2,a2,0 + 2e4: 08090003 lb zero,128(s2) + 2e8: 0100 addi s0,sp,128 + 2ea: 0200 addi s0,sp,256 + 2ec: 1804 addi s1,sp,48 + 2ee: 0306 slli t1,t1,0x1 + 2f0: 0900 addi s0,sp,144 + 2f2: 001c 0x1c + 2f4: 0601 addi a2,a2,0 + 2f6: 08090003 lb zero,128(s2) + 2fa: 0100 addi s0,sp,128 + 2fc: 0200 addi s0,sp,256 + 2fe: 0c04 addi s1,sp,528 + 300: 0306 slli t1,t1,0x1 + 302: 0900 addi s0,sp,144 + 304: 0008 0x8 + 306: 0001 nop + 308: 0402 c.slli64 s0 + 30a: 0326 slli t1,t1,0x9 + 30c: 0900 addi s0,sp,144 + 30e: 0008 0x8 + 310: 0001 nop + 312: 0402 c.slli64 s0 + 314: 0900032f 0x900032f + 318: 0008 0x8 + 31a: 0001 nop + 31c: 0402 c.slli64 s0 + 31e: 0330 addi a2,sp,392 + 320: 0900 addi s0,sp,144 + 322: 000c 0xc + 324: 0001 nop + 326: 0402 c.slli64 s0 + 328: 0900033b 0x900033b + 32c: 0018 0x18 + 32e: 0001 nop + 330: 0402 c.slli64 s0 + 332: 030a slli t1,t1,0x2 + 334: 0900 addi s0,sp,144 + 336: 0008 0x8 + 338: 0001 nop + 33a: 0402 c.slli64 s0 + 33c: 033d addi t1,t1,15 + 33e: 0900 addi s0,sp,144 + 340: 0004 0x4 + 342: 0001 nop + 344: 0402 c.slli64 s0 + 346: 033d addi t1,t1,15 + 348: 0900 addi s0,sp,144 + 34a: 0004 0x4 + 34c: 0001 nop + 34e: 0402 c.slli64 s0 + 350: 033d addi t1,t1,15 + 352: 0900 addi s0,sp,144 + 354: 0000 unimp + 356: 0001 nop + 358: 0402 c.slli64 s0 + 35a: 0900033f 00010004 0x100040900033f + 362: 0402 c.slli64 s0 + 364: 0342 slli t1,t1,0x10 + 366: 0900 addi s0,sp,144 + 368: 0004 0x4 + 36a: 0001 nop + 36c: 0402 c.slli64 s0 + 36e: 0342 slli t1,t1,0x10 + 370: 0900 addi s0,sp,144 + 372: 0000 unimp + 374: 0001 nop + 376: 0402 c.slli64 s0 + 378: 0342 slli t1,t1,0x10 + 37a: 0900 addi s0,sp,144 + 37c: 0004 0x4 + 37e: 0001 nop + 380: 0402 c.slli64 s0 + 382: 0900034b fnmsub.s ft6,ft0,fa6,ft1,rne + 386: 0004 0x4 + 388: 0001 nop + 38a: 0402 c.slli64 s0 + 38c: 0900034b fnmsub.s ft6,ft0,fa6,ft1,rne + 390: 0004 0x4 + 392: 0001 nop + 394: 0402 c.slli64 s0 + 396: 034c addi a1,sp,388 + 398: 0900 addi s0,sp,144 + 39a: 0004 0x4 + 39c: 0601 addi a2,a2,0 + 39e: 08097f03 0x8097f03 + 3a2: 0100 addi s0,sp,128 + 3a4: 0200 addi s0,sp,256 + 3a6: 4004 lw s1,0(s0) + 3a8: 0306 slli t1,t1,0x1 + 3aa: 0901 addi s2,s2,0 + 3ac: 0008 0x8 + 3ae: 0001 nop + 3b0: 0402 c.slli64 s0 + 3b2: 035a slli t1,t1,0x16 + 3b4: 0900 addi s0,sp,144 + 3b6: 0008 0x8 + 3b8: 0001 nop + 3ba: 0402 c.slli64 s0 + 3bc: 09000363 beq zero,a6,442 <_start-0x7ffffbbe> + 3c0: 0008 0x8 + 3c2: 0001 nop + 3c4: 0402 c.slli64 s0 + 3c6: 0364 addi s1,sp,396 + 3c8: 0900 addi s0,sp,144 + 3ca: 000c 0xc + 3cc: 0001 nop + 3ce: 0402 c.slli64 s0 + 3d0: 0900036f jal t1,460 <_start-0x7ffffba0> + 3d4: 0018 0x18 + 3d6: 0001 nop + 3d8: 0402 c.slli64 s0 + 3da: 033e slli t1,t1,0xf + 3dc: 0900 addi s0,sp,144 + 3de: 0008 0x8 + 3e0: 0001 nop + 3e2: 0402 c.slli64 s0 + 3e4: 0371 addi t1,t1,28 + 3e6: 0900 addi s0,sp,144 + 3e8: 000c 0xc + 3ea: 0001 nop + 3ec: 0402 c.slli64 s0 + 3ee: 09000373 0x9000373 + 3f2: 0004 0x4 + 3f4: 0001 nop + 3f6: 0402 c.slli64 s0 + 3f8: 09000373 0x9000373 + 3fc: 0000 unimp + 3fe: 0001 nop + 400: 0402 c.slli64 s0 + 402: 0376 slli t1,t1,0x1d + 404: 0900 addi s0,sp,144 + 406: 0004 0x4 + 408: 0001 nop + 40a: 0402 c.slli64 s0 + 40c: 037c addi a5,sp,396 + 40e: 0900 addi s0,sp,144 + 410: 0004 0x4 + 412: 0001 nop + 414: 0402 c.slli64 s0 + 416: 037c addi a5,sp,396 + 418: 0900 addi s0,sp,144 + 41a: 0000 unimp + 41c: 0001 nop + 41e: 0402 c.slli64 s0 + 420: 037c addi a5,sp,396 + 422: 0900 addi s0,sp,144 + 424: 0004 0x4 + 426: 0001 nop + 428: 0402 c.slli64 s0 + 42a: 037e slli t1,t1,0x1f + 42c: 0900 addi s0,sp,144 + 42e: 0008 0x8 + 430: 0001 nop + 432: 0402 c.slli64 s0 + 434: 037e slli t1,t1,0x1f + 436: 0900 addi s0,sp,144 + 438: 000c 0xc + 43a: 0001 nop + 43c: 02f80403 lb s0,47(a6) # 7768f <_start-0x7ff88971> + 440: 04090003 lb zero,64(s2) + 444: 0100 addi s0,sp,128 + 446: 0300 addi s0,sp,384 + 448: f804 fsw fs1,48(s0) + 44a: 0302 c.slli64 t1 + 44c: 0900 addi s0,sp,144 + 44e: 0000 unimp + 450: 0001 nop + 452: 02f80403 lb s0,47(a6) + 456: 00090103 lb sp,0(s2) + 45a: 0100 addi s0,sp,128 + 45c: 0300 addi s0,sp,384 + 45e: f804 fsw fs1,48(s0) + 460: 0302 c.slli64 t1 + 462: 0900 addi s0,sp,144 + 464: 0000 unimp + 466: 0001 nop + 468: 02f80403 lb s0,47(a6) + 46c: 00090003 lb zero,0(s2) + 470: 0100 addi s0,sp,128 + 472: 0300 addi s0,sp,384 + 474: f804 fsw fs1,48(s0) + 476: 0302 c.slli64 t1 + 478: 0900 addi s0,sp,144 + 47a: 0000 unimp + 47c: 0001 nop + 47e: 02f80403 lb s0,47(a6) + 482: 00090003 lb zero,0(s2) + 486: 0100 addi s0,sp,128 + 488: 0200 addi s0,sp,256 + 48a: 2504 fld fs1,8(a0) + 48c: 08090003 lb zero,128(s2) + 490: 0100 addi s0,sp,128 + 492: 0200 addi s0,sp,256 + 494: 2504 fld fs1,8(a0) + 496: 00090003 lb zero,0(s2) + 49a: 0100 addi s0,sp,128 + 49c: 0200 addi s0,sp,256 + 49e: 2504 fld fs1,8(a0) + 4a0: 00090003 lb zero,0(s2) + 4a4: 0100 addi s0,sp,128 + 4a6: 0200 addi s0,sp,256 + 4a8: 2504 fld fs1,8(a0) + 4aa: 00090003 lb zero,0(s2) + 4ae: 0100 addi s0,sp,128 + 4b0: 0200 addi s0,sp,256 + 4b2: 2c04 fld fs1,24(s0) + 4b4: 0c090003 lb zero,192(s2) + 4b8: 0100 addi s0,sp,128 + 4ba: 0300 addi s0,sp,384 + 4bc: 8f04 0x8f04 + 4be: 0301 addi t1,t1,0 + 4c0: 097f 0x97f + 4c2: 0008 0x8 + 4c4: 0001 nop + 4c6: 018f0403 lb s0,24(t5) # 68686 <_start-0x7ff9797a> + 4ca: 00090003 lb zero,0(s2) + 4ce: 0100 addi s0,sp,128 + 4d0: 0300 addi s0,sp,384 + 4d2: 8f04 0x8f04 + 4d4: 0301 addi t1,t1,0 + 4d6: 0900 addi s0,sp,144 + 4d8: 0000 unimp + 4da: 0001 nop + 4dc: 018f0403 lb s0,24(t5) + 4e0: 00090003 lb zero,0(s2) + 4e4: 0100 addi s0,sp,128 + 4e6: 0300 addi s0,sp,384 + 4e8: 8f04 0x8f04 + 4ea: 0301 addi t1,t1,0 + 4ec: 0900 addi s0,sp,144 + 4ee: 0000 unimp + 4f0: 0001 nop + 4f2: 018f0403 lb s0,24(t5) + 4f6: 00090003 lb zero,0(s2) + 4fa: 0100 addi s0,sp,128 + 4fc: 0300 addi s0,sp,384 + 4fe: 8f04 0x8f04 + 500: 0301 addi t1,t1,0 + 502: 0900 addi s0,sp,144 + 504: 0000 unimp + 506: 0001 nop + 508: 018f0403 lb s0,24(t5) + 50c: 00090003 lb zero,0(s2) + 510: 0100 addi s0,sp,128 + 512: 0300 addi s0,sp,384 + 514: c904 sw s1,16(a0) + 516: 0302 c.slli64 t1 + 518: 0900 addi s0,sp,144 + 51a: 0004 0x4 + 51c: 0601 addi a2,a2,0 + 51e: 04090003 lb zero,64(s2) + 522: 0100 addi s0,sp,128 + 524: 0200 addi s0,sp,256 + 526: 7204 flw fs1,32(a2) + 528: 0306 slli t1,t1,0x1 + 52a: 0900 addi s0,sp,144 + 52c: 0010 0x10 + 52e: 0001 nop + 530: 0402 c.slli64 s0 + 532: 0372 slli t1,t1,0x1c + 534: 0900 addi s0,sp,144 + 536: 0000 unimp + 538: 0001 nop + 53a: 0402 c.slli64 s0 + 53c: 0372 slli t1,t1,0x1c + 53e: 0900 addi s0,sp,144 + 540: 0000 unimp + 542: 0001 nop + 544: 0402 c.slli64 s0 + 546: 0372 slli t1,t1,0x1c + 548: 0900 addi s0,sp,144 + 54a: 0000 unimp + 54c: 0601 addi a2,a2,0 + 54e: 08090003 lb zero,128(s2) + 552: 0100 addi s0,sp,128 + 554: 0200 addi s0,sp,256 + 556: 0804 addi s1,sp,16 + 558: 0306 slli t1,t1,0x1 + 55a: 0900 addi s0,sp,144 + 55c: 0010 0x10 + 55e: 0001 nop + 560: 0402 c.slli64 s0 + 562: 0308 addi a0,sp,384 + 564: 0900 addi s0,sp,144 + 566: 0000 unimp + 568: 0001 nop + 56a: 01bd0403 lb s0,27(s10) # 9e8b1 <_start-0x7ff6174f> + 56e: 04090003 lb zero,64(s2) + 572: 0100 addi s0,sp,128 + 574: 0300 addi s0,sp,384 + 576: bd04 fsd fs1,56(a0) + 578: 0301 addi t1,t1,0 + 57a: 0900 addi s0,sp,144 + 57c: 0000 unimp + 57e: 0001 nop + 580: 01bd0403 lb s0,27(s10) + 584: 00090003 lb zero,0(s2) + 588: 0100 addi s0,sp,128 + 58a: 0300 addi s0,sp,384 + 58c: bf04 fsd fs1,56(a4) + 58e: 0301 addi t1,t1,0 + 590: 0900 addi s0,sp,144 + 592: 0004 0x4 + 594: 0001 nop + 596: 01bf0403 lb s0,27(t5) + 59a: 0306 slli t1,t1,0x1 + 59c: 097e slli s2,s2,0x1f + 59e: 0000 unimp + 5a0: 0001 nop + 5a2: 01bf0403 lb s0,27(t5) + 5a6: 04090203 lb tp,64(s2) + 5aa: 0100 addi s0,sp,128 + 5ac: 0300 addi s0,sp,384 + 5ae: c204 sw s1,0(a2) + 5b0: 0601 addi a2,a2,0 + 5b2: 04090003 lb zero,64(s2) + 5b6: 0100 addi s0,sp,128 + 5b8: 0300 addi s0,sp,384 + 5ba: c204 sw s1,0(a2) + 5bc: 0301 addi t1,t1,0 + 5be: 0900 addi s0,sp,144 + 5c0: 0000 unimp + 5c2: 0001 nop + 5c4: 01c20403 lb s0,28(tp) # 1a01c <_start-0x7ffe5fe4> + 5c8: 04090003 lb zero,64(s2) + 5cc: 0100 addi s0,sp,128 + 5ce: 0300 addi s0,sp,384 + 5d0: cb04 sw s1,16(a4) + 5d2: 0301 addi t1,t1,0 + 5d4: 0900 addi s0,sp,144 + 5d6: 0004 0x4 + 5d8: 0001 nop + 5da: 01cb0403 lb s0,28(s6) + 5de: 04090003 lb zero,64(s2) + 5e2: 0100 addi s0,sp,128 + 5e4: 0300 addi s0,sp,384 + 5e6: a404 fsd fs1,8(s0) + 5e8: 0302 c.slli64 t1 + 5ea: 0900 addi s0,sp,144 + 5ec: 0000 unimp + 5ee: 0001 nop + 5f0: 02df0403 lb s0,45(t5) + 5f4: 08090003 lb zero,128(s2) + 5f8: 0100 addi s0,sp,128 + 5fa: 0300 addi s0,sp,384 + 5fc: df04 sw s1,56(a4) + 5fe: 0302 c.slli64 t1 + 600: 0900 addi s0,sp,144 + 602: 0000 unimp + 604: 0001 nop + 606: 01cc0403 lb s0,28(s8) # 646b4 <_start-0x7ff9b94c> + 60a: 14090003 lb zero,320(s2) + 60e: 0100 addi s0,sp,128 + 610: 0300 addi s0,sp,384 + 612: e304 fsw fs1,0(a4) + 614: 0301 addi t1,t1,0 + 616: 0900 addi s0,sp,144 + 618: 000c 0xc + 61a: 0001 nop + 61c: 01e40403 lb s0,30(s0) # 30038f2 <_start-0x7cffc70e> + 620: 0c090003 lb zero,192(s2) + 624: 0100 addi s0,sp,128 + 626: 0300 addi s0,sp,384 + 628: ef04 fsw fs1,24(a4) + 62a: 0301 addi t1,t1,0 + 62c: 0900 addi s0,sp,144 + 62e: 0018 0x18 + 630: 0001 nop + 632: 01ef0403 lb s0,30(t5) + 636: 0306 slli t1,t1,0x1 + 638: 097e slli s2,s2,0x1f + 63a: 0004 0x4 + 63c: 0001 nop + 63e: 01c00403 lb s0,28(zero) # 1c <_start-0x7fffffe4> + 642: 0306 slli t1,t1,0x1 + 644: 0902 c.slli64 s2 + 646: 0008 0x8 + 648: 0001 nop + 64a: 01da0403 lb s0,29(s4) + 64e: 0c090003 lb zero,192(s2) + 652: 0100 addi s0,sp,128 + 654: 0300 addi s0,sp,384 + 656: be04 fsd fs1,56(a2) + 658: 0301 addi t1,t1,0 + 65a: 0900 addi s0,sp,144 + 65c: 000c 0xc + 65e: 0001 nop + 660: 01f10403 lb s0,31(sp) + 664: 04090003 lb zero,64(s2) + 668: 0100 addi s0,sp,128 + 66a: 0300 addi s0,sp,384 + 66c: f104 fsw fs1,32(a0) + 66e: 0301 addi t1,t1,0 + 670: 0900 addi s0,sp,144 + 672: 0004 0x4 + 674: 0001 nop + 676: 01f10403 lb s0,31(sp) + 67a: 00090003 lb zero,0(s2) + 67e: 0100 addi s0,sp,128 + 680: 0300 addi s0,sp,384 + 682: f104 fsw fs1,32(a0) + 684: 0301 addi t1,t1,0 + 686: 0900 addi s0,sp,144 + 688: 0000 unimp + 68a: 0001 nop + 68c: 01f30403 lb s0,31(t1) # 90002b9 <_start-0x76fffd47> + 690: 04090003 lb zero,64(s2) + 694: 0100 addi s0,sp,128 + 696: 0300 addi s0,sp,384 + 698: f604 fsw fs1,40(a2) + 69a: 0301 addi t1,t1,0 + 69c: 0900 addi s0,sp,144 + 69e: 0004 0x4 + 6a0: 0001 nop + 6a2: 01f60403 lb s0,31(a2) # b01f <_start-0x7fff4fe1> + 6a6: 00090003 lb zero,0(s2) + 6aa: 0100 addi s0,sp,128 + 6ac: 0300 addi s0,sp,384 + 6ae: f604 fsw fs1,40(a2) + 6b0: 0301 addi t1,t1,0 + 6b2: 0900 addi s0,sp,144 + 6b4: 0004 0x4 + 6b6: 0001 nop + 6b8: 01ff0403 lb s0,31(t5) + 6bc: 04090003 lb zero,64(s2) + 6c0: 0100 addi s0,sp,128 + 6c2: 0300 addi s0,sp,384 + 6c4: ff04 fsw fs1,56(a4) + 6c6: 0301 addi t1,t1,0 + 6c8: 0900 addi s0,sp,144 + 6ca: 0004 0x4 + 6cc: 0001 nop + 6ce: 02800403 lb s0,40(zero) # 28 <_start-0x7fffffd8> + 6d2: 08090003 lb zero,128(s2) + 6d6: 0100 addi s0,sp,128 + 6d8: 0306 slli t1,t1,0x1 + 6da: 097f 0x97f + 6dc: 0008 0x8 + 6de: 0001 nop + 6e0: 01f40403 lb s0,31(s0) + 6e4: 0306 slli t1,t1,0x1 + 6e6: 0901 addi s2,s2,0 + 6e8: 000c 0xc + 6ea: 0001 nop + 6ec: 028e0403 lb s0,40(t3) # 1a028 <_start-0x7ffe5fd8> + 6f0: 08090003 lb zero,128(s2) + 6f4: 0100 addi s0,sp,128 + 6f6: 0300 addi s0,sp,384 + 6f8: 9704 0x9704 + 6fa: 0302 c.slli64 t1 + 6fc: 0900 addi s0,sp,144 + 6fe: 0008 0x8 + 700: 0001 nop + 702: 02980403 lb s0,41(a6) + 706: 0c090003 lb zero,192(s2) + 70a: 0100 addi s0,sp,128 + 70c: 0300 addi s0,sp,384 + 70e: a304 fsd fs1,0(a4) + 710: 0302 c.slli64 t1 + 712: 0900 addi s0,sp,144 + 714: 0018 0x18 + 716: 0001 nop + 718: 01f20403 lb s0,31(tp) # 1f <_start-0x7fffffe1> + 71c: 08090003 lb zero,128(s2) + 720: 0100 addi s0,sp,128 + 722: 0300 addi s0,sp,384 + 724: a504 fsd fs1,8(a0) + 726: 0302 c.slli64 t1 + 728: 0900 addi s0,sp,144 + 72a: 000c 0xc + 72c: 0001 nop + 72e: 02a70403 lb s0,42(a4) # 766a6 <_start-0x7ff8995a> + 732: 04090003 lb zero,64(s2) + 736: 0100 addi s0,sp,128 + 738: 0300 addi s0,sp,384 + 73a: a704 fsd fs1,8(a4) + 73c: 0302 c.slli64 t1 + 73e: 0900 addi s0,sp,144 + 740: 0000 unimp + 742: 0001 nop + 744: 02a90403 lb s0,42(s2) + 748: 04090003 lb zero,64(s2) + 74c: 0100 addi s0,sp,128 + 74e: 0300 addi s0,sp,384 + 750: a904 fsd fs1,16(a0) + 752: 0302 c.slli64 t1 + 754: 0900 addi s0,sp,144 + 756: 0000 unimp + 758: 0601 addi a2,a2,0 + 75a: 04090003 lb zero,64(s2) + 75e: 0100 addi s0,sp,128 + 760: 0300 addi s0,sp,384 + 762: aa04 fsd fs1,16(a2) + 764: 0602 c.slli64 a2 + 766: 0c090003 lb zero,192(s2) + 76a: 0100 addi s0,sp,128 + 76c: 0300 addi s0,sp,384 + 76e: b104 fsd fs1,32(a0) + 770: 0302 c.slli64 t1 + 772: 0900 addi s0,sp,144 + 774: 0004 0x4 + 776: 0001 nop + 778: 02b10403 lb s0,43(sp) + 77c: 00090003 lb zero,0(s2) + 780: 0100 addi s0,sp,128 + 782: 0300 addi s0,sp,384 + 784: b104 fsd fs1,32(a0) + 786: 0302 c.slli64 t1 + 788: 0900 addi s0,sp,144 + 78a: 0004 0x4 + 78c: 0001 nop + 78e: 02b10403 lb s0,43(sp) + 792: 00090003 lb zero,0(s2) + 796: 0100 addi s0,sp,128 + 798: 0300 addi s0,sp,384 + 79a: b404 fsd fs1,40(s0) + 79c: 0302 c.slli64 t1 + 79e: 0900 addi s0,sp,144 + 7a0: 000c 0xc + 7a2: 0001 nop + 7a4: 02c70403 lb s0,44(a4) + 7a8: 0c090003 lb zero,192(s2) + 7ac: 0100 addi s0,sp,128 + 7ae: 0300 addi s0,sp,384 + 7b0: c704 sw s1,8(a4) + 7b2: 0302 c.slli64 t1 + 7b4: 0900 addi s0,sp,144 + 7b6: 0000 unimp + 7b8: 0001 nop + 7ba: 02c70403 lb s0,44(a4) + 7be: 00090003 lb zero,0(s2) + 7c2: 0100 addi s0,sp,128 + 7c4: 0300 addi s0,sp,384 + 7c6: c704 sw s1,8(a4) + 7c8: 0302 c.slli64 t1 + 7ca: 0900 addi s0,sp,144 + 7cc: 0000 unimp + 7ce: 0001 nop + 7d0: 02c70403 lb s0,44(a4) + 7d4: 00090003 lb zero,0(s2) + 7d8: 0100 addi s0,sp,128 + 7da: 0300 addi s0,sp,384 + 7dc: c704 sw s1,8(a4) + 7de: 0302 c.slli64 t1 + 7e0: 0900 addi s0,sp,144 + 7e2: 0000 unimp + 7e4: 0001 nop + 7e6: 02c70403 lb s0,44(a4) + 7ea: 00090003 lb zero,0(s2) + 7ee: 0100 addi s0,sp,128 + 7f0: 0300 addi s0,sp,384 + 7f2: c704 sw s1,8(a4) + 7f4: 0302 c.slli64 t1 + 7f6: 0900 addi s0,sp,144 + 7f8: 0000 unimp + 7fa: 0001 nop + 7fc: 02c80403 lb s0,44(a6) + 800: 04090003 lb zero,64(s2) + 804: 0100 addi s0,sp,128 + 806: 0306 slli t1,t1,0x1 + 808: 0900 addi s0,sp,144 + 80a: 0004 0x4 + 80c: 0001 nop + 80e: 02a60403 lb s0,42(a2) + 812: 0306 slli t1,t1,0x1 + 814: 0900 addi s0,sp,144 + 816: 000c 0xc + 818: 0001 nop + 81a: 02a60403 lb s0,42(a2) + 81e: 00090003 lb zero,0(s2) + 822: 0100 addi s0,sp,128 + 824: 0300 addi s0,sp,384 + 826: a604 fsd fs1,8(a2) + 828: 0302 c.slli64 t1 + 82a: 0900 addi s0,sp,144 + 82c: 0004 0x4 + 82e: 0001 nop + 830: 02a60403 lb s0,42(a2) + 834: 00090003 lb zero,0(s2) + 838: 0100 addi s0,sp,128 + 83a: 0300 addi s0,sp,384 + 83c: d804 sw s1,48(s0) + 83e: 0302 c.slli64 t1 + 840: 0900 addi s0,sp,144 + 842: 0008 0x8 + 844: 0001 nop + 846: 02d80403 lb s0,45(a6) + 84a: 04090003 lb zero,64(s2) + 84e: 0100 addi s0,sp,128 + 850: 0300 addi s0,sp,384 + 852: e204 fsw fs1,0(a2) + 854: 0302 c.slli64 t1 + 856: 0900 addi s0,sp,144 + 858: 0004 0x4 + 85a: 0001 nop + 85c: 02e20403 lb s0,46(tp) # 2e <_start-0x7fffffd2> + 860: 00090003 lb zero,0(s2) + 864: 0100 addi s0,sp,128 + 866: 0300 addi s0,sp,384 + 868: e204 fsw fs1,0(a2) + 86a: 0302 c.slli64 t1 + 86c: 0900 addi s0,sp,144 + 86e: 0000 unimp + 870: 0001 nop + 872: 02e20403 lb s0,46(tp) # 2e <_start-0x7fffffd2> + 876: 00090003 lb zero,0(s2) + 87a: 0100 addi s0,sp,128 + 87c: 0300 addi s0,sp,384 + 87e: e204 fsw fs1,0(a2) + 880: 0302 c.slli64 t1 + 882: 0900 addi s0,sp,144 + 884: 0008 0x8 + 886: 0001 nop + 888: 02e20403 lb s0,46(tp) # 2e <_start-0x7fffffd2> + 88c: 00090003 lb zero,0(s2) + 890: 0100 addi s0,sp,128 + 892: 0300 addi s0,sp,384 + 894: e204 fsw fs1,0(a2) + 896: 0302 c.slli64 t1 + 898: 0900 addi s0,sp,144 + 89a: 0004 0x4 + 89c: 0001 nop + 89e: 02e20403 lb s0,46(tp) # 2e <_start-0x7fffffd2> + 8a2: 00090003 lb zero,0(s2) + 8a6: 0100 addi s0,sp,128 + 8a8: 0300 addi s0,sp,384 + 8aa: e204 fsw fs1,0(a2) + 8ac: 0302 c.slli64 t1 + 8ae: 0900 addi s0,sp,144 + 8b0: 0000 unimp + 8b2: 0001 nop + 8b4: 02e20403 lb s0,46(tp) # 2e <_start-0x7fffffd2> + 8b8: 04090003 lb zero,64(s2) + 8bc: 0100 addi s0,sp,128 + 8be: 0300 addi s0,sp,384 + 8c0: e204 fsw fs1,0(a2) + 8c2: 0302 c.slli64 t1 + 8c4: 0900 addi s0,sp,144 + 8c6: 0000 unimp + 8c8: 0001 nop + 8ca: 02ef0403 lb s0,46(t5) + 8ce: 04090003 lb zero,64(s2) + 8d2: 0100 addi s0,sp,128 + 8d4: 0300 addi s0,sp,384 + 8d6: ef04 fsw fs1,24(a4) + 8d8: 0302 c.slli64 t1 + 8da: 0900 addi s0,sp,144 + 8dc: 0008 0x8 + 8de: 0001 nop + 8e0: 02ef0403 lb s0,46(t5) + 8e4: 18090003 lb zero,384(s2) + 8e8: 0100 addi s0,sp,128 + 8ea: 0300 addi s0,sp,384 + 8ec: d904 sw s1,48(a0) + 8ee: 0302 c.slli64 t1 + 8f0: 0900 addi s0,sp,144 + 8f2: 0008 0x8 + 8f4: 0601 addi a2,a2,0 + 8f6: 04090003 lb zero,64(s2) + 8fa: 0100 addi s0,sp,128 + 8fc: 0300 addi s0,sp,384 + 8fe: f004 fsw fs1,32(s0) + 900: 0602 c.slli64 a2 + 902: 0c090003 lb zero,192(s2) + 906: 0100 addi s0,sp,128 + 908: 0300 addi s0,sp,384 + 90a: f004 fsw fs1,32(s0) + 90c: 0302 c.slli64 t1 + 90e: 0900 addi s0,sp,144 + 910: 000c 0xc + 912: 0601 addi a2,a2,0 + 914: 08097e03 0x8097e03 + 918: 0100 addi s0,sp,128 + 91a: 08090103 lb sp,128(s2) + 91e: 0100 addi s0,sp,128 + 920: 0200 addi s0,sp,256 + 922: 2f04 fld fs1,24(a4) + 924: 0306 slli t1,t1,0x1 + 926: 0902 c.slli64 s2 + 928: 0010 0x10 + 92a: 0001 nop + 92c: 0402 c.slli64 s0 + 92e: 0900032f 0x900032f + 932: 0000 unimp + 934: 0001 nop + 936: 0402 c.slli64 s0 + 938: 0900032f 0x900032f + 93c: 0000 unimp + 93e: 0001 nop + 940: 0402 c.slli64 s0 + 942: 0900033f 00010008 0x100080900033f + 94a: 0402 c.slli64 s0 + 94c: 0900033f 00010000 0x100000900033f + 954: 0402 c.slli64 s0 + 956: 0900033f 06010004 0x60100040900033f + 95e: 08090003 lb zero,128(s2) + 962: 0100 addi s0,sp,128 + 964: 0200 addi s0,sp,256 + 966: 4f04 lw s1,24(a4) + 968: 0306 slli t1,t1,0x1 + 96a: 0900 addi s0,sp,144 + 96c: 000c 0xc + 96e: 0001 nop + 970: 0402 c.slli64 s0 + 972: 0900034f fnmadd.s ft6,ft0,fa6,ft1,rne + 976: 0000 unimp + 978: 0001 nop + 97a: 0402 c.slli64 s0 + 97c: 0900034f fnmadd.s ft6,ft0,fa6,ft1,rne + 980: 0008 0x8 + 982: 0001 nop + 984: 0402 c.slli64 s0 + 986: 0650 addi a2,sp,772 + 988: 04090003 lb zero,64(s2) + 98c: 0100 addi s0,sp,128 + 98e: 04090003 lb zero,64(s2) + 992: 0100 addi s0,sp,128 + 994: 0200 addi s0,sp,256 + 996: 5a04 lw s1,48(a2) + 998: 0306 slli t1,t1,0x1 + 99a: 0900 addi s0,sp,144 + 99c: 0008 0x8 + 99e: 0001 nop + 9a0: 0402 c.slli64 s0 + 9a2: 035a slli t1,t1,0x16 + 9a4: 0900 addi s0,sp,144 + 9a6: 0000 unimp + 9a8: 0001 nop + 9aa: 0402 c.slli64 s0 + 9ac: 035a slli t1,t1,0x16 + 9ae: 0900 addi s0,sp,144 + 9b0: 0000 unimp + 9b2: 0001 nop + 9b4: 0402 c.slli64 s0 + 9b6: 035a slli t1,t1,0x16 + 9b8: 0900 addi s0,sp,144 + 9ba: 0000 unimp + 9bc: 0001 nop + 9be: 0402 c.slli64 s0 + 9c0: 035a slli t1,t1,0x16 + 9c2: 0900 addi s0,sp,144 + 9c4: 0000 unimp + 9c6: 0001 nop + 9c8: 0402 c.slli64 s0 + 9ca: 035a slli t1,t1,0x16 + 9cc: 0900 addi s0,sp,144 + 9ce: 0000 unimp + 9d0: 0001 nop + 9d2: 0402 c.slli64 s0 + 9d4: 035a slli t1,t1,0x16 + 9d6: 0900 addi s0,sp,144 + 9d8: 0000 unimp + 9da: 0501 addi a0,a0,0 + 9dc: 0001 nop + 9de: 0402 c.slli64 s0 + 9e0: 065a slli a2,a2,0x16 + 9e2: 00090403 lb s0,0(s2) + 9e6: 0100 addi s0,sp,128 + 9e8: 0305 addi t1,t1,1 + 9ea: 0200 addi s0,sp,256 + 9ec: 5a04 lw s1,48(a2) + 9ee: 08097c03 0x8097c03 + 9f2: 0100 addi s0,sp,128 + 9f4: 0200 addi s0,sp,256 + 9f6: 5a04 lw s1,48(a2) + 9f8: 0306 slli t1,t1,0x1 + 9fa: 0900 addi s0,sp,144 + 9fc: 001c 0x1c + 9fe: 0001 nop + a00: 0402 c.slli64 s0 + a02: 035a slli t1,t1,0x16 + a04: 0900 addi s0,sp,144 + a06: 0000 unimp + a08: 0001 nop + a0a: 0402 c.slli64 s0 + a0c: 035a slli t1,t1,0x16 + a0e: 0900 addi s0,sp,144 + a10: 0000 unimp + a12: 0001 nop + a14: 0402 c.slli64 s0 + a16: 035a slli t1,t1,0x16 + a18: 0901 addi s2,s2,0 + a1a: 0000 unimp + a1c: 0001 nop + a1e: 0402 c.slli64 s0 + a20: 035a slli t1,t1,0x16 + a22: 0900 addi s0,sp,144 + a24: 0000 unimp + a26: 0001 nop + a28: 0402 c.slli64 s0 + a2a: 035a slli t1,t1,0x16 + a2c: 0900 addi s0,sp,144 + a2e: 0000 unimp + a30: 0001 nop + a32: 0402 c.slli64 s0 + a34: 035a slli t1,t1,0x16 + a36: 0902 c.slli64 s2 + a38: 0000 unimp + a3a: 0501 addi a0,a0,0 + a3c: 0001 nop + a3e: 0402 c.slli64 s0 + a40: 065a slli a2,a2,0x16 + a42: 00090103 lb sp,0(s2) + a46: 0100 addi s0,sp,128 + a48: 1c09 addi s8,s8,-30 + a4a: 0000 unimp + a4c: 0101 addi sp,sp,0 + a4e: 087e slli a6,a6,0x1f + a50: 0000 unimp + a52: 00930003 lb zero,9(t1) + a56: 0000 unimp + a58: 0101 addi sp,sp,0 + a5a: 000d0efb 0xd0efb + a5e: 0101 addi sp,sp,0 + a60: 0101 addi sp,sp,0 + a62: 0000 unimp + a64: 0100 addi s0,sp,128 + a66: 0000 unimp + a68: 2e01 jal d78 <_start-0x7ffff288> + a6a: 2f2e fld ft10,200(sp) + a6c: 2e2e fld ft8,200(sp) + a6e: 2f2e2e2f 0x2f2e2e2f + a72: 2e2e fld ft8,200(sp) + a74: 7369722f 0x7369722f + a78: 672d7663 bgeu s10,s2,10e4 <_start-0x7fffef1c> + a7c: 6c2f6363 bltu t5,sp,1142 <_start-0x7fffeebe> + a80: 6269 lui tp,0x1a + a82: 2f636367 0x2f636367 + a86: 74666f73 csrrsi t5,0x746,12 + a8a: 662d lui a2,0xb + a8c: 0070 addi a2,sp,12 + a8e: 2e2e fld ft8,200(sp) + a90: 2f2e2e2f 0x2f2e2e2f + a94: 2e2e fld ft8,200(sp) + a96: 2f2e2e2f 0x2f2e2e2f + a9a: 6972 flw fs2,28(sp) + a9c: 2d766373 csrrsi t1,0x2d7,12 + aa0: 2f636367 0x2f636367 + aa4: 696c flw fa1,84(a0) + aa6: 6762 flw fa4,24(sp) + aa8: 2e2f6363 bltu t5,sp,d8e <_start-0x7ffff272> + aac: 2f2e fld ft10,200(sp) + aae: 6e69 lui t3,0x1a + ab0: 64756c63 bltu a0,t2,1108 <_start-0x7fffeef8> + ab4: 0065 c.nop 25 + ab6: 6400 flw fs0,8(s0) + ab8: 7669 lui a2,0xffffa + aba: 2e336673 csrrsi a2,0x2e3,6 + abe: 00010063 beqz sp,abe <_start-0x7ffff542> + ac2: 7300 flw fs0,32(a4) + ac4: 2d74666f jal a2,4759a <_start-0x7ffb8a66> + ac8: 7066 flw ft0,120(sp) + aca: 682e flw fa6,200(sp) + acc: 0100 addi s0,sp,128 + ace: 0000 unimp + ad0: 676e6973 csrrsi s2,0x676,28 + ad4: 656c flw fa1,76(a0) + ad6: 682e flw fa6,200(sp) + ad8: 0100 addi s0,sp,128 + ada: 0000 unimp + adc: 6f6c flw fa1,92(a4) + ade: 676e flw fa4,216(sp) + ae0: 6f6c flw fa1,92(a4) + ae2: 676e flw fa4,216(sp) + ae4: 682e flw fa6,200(sp) + ae6: 0200 addi s0,sp,256 + ae8: 0000 unimp + aea: 0500 addi s0,sp,640 + aec: 0001 nop + aee: 0205 addi tp,tp,1 + af0: 1314 addi a3,sp,416 + af2: 8000 0x8000 + af4: 05012303 lw t1,80(sp) + af8: 09010303 lb t1,144(sp) + afc: 0000 unimp + afe: 0301 addi t1,t1,0 + b00: 0900 addi s0,sp,144 + b02: 0000 unimp + b04: 0501 addi a0,a0,0 + b06: 030d addi t1,t1,3 + b08: 0900 addi s0,sp,144 + b0a: 0000 unimp + b0c: 0501 addi a0,a0,0 + b0e: 09010303 lb t1,144(sp) + b12: 0000 unimp + b14: 0301 addi t1,t1,0 + b16: 0900 addi s0,sp,144 + b18: 0000 unimp + b1a: 0301 addi t1,t1,0 + b1c: 0900 addi s0,sp,144 + b1e: 0000 unimp + b20: 0301 addi t1,t1,0 + b22: 0900 addi s0,sp,144 + b24: 0000 unimp + b26: 0301 addi t1,t1,0 + b28: 0901 addi s2,s2,0 + b2a: 0000 unimp + b2c: 0301 addi t1,t1,0 + b2e: 0900 addi s0,sp,144 + b30: 0000 unimp + b32: 0301 addi t1,t1,0 + b34: 0900 addi s0,sp,144 + b36: 0000 unimp + b38: 0301 addi t1,t1,0 + b3a: 0900 addi s0,sp,144 + b3c: 0000 unimp + b3e: 0301 addi t1,t1,0 + b40: 0901 addi s2,s2,0 + b42: 0000 unimp + b44: 0301 addi t1,t1,0 + b46: 0900 addi s0,sp,144 + b48: 0000 unimp + b4a: 0301 addi t1,t1,0 + b4c: 0900 addi s0,sp,144 + b4e: 0000 unimp + b50: 0301 addi t1,t1,0 + b52: 0900 addi s0,sp,144 + b54: 0000 unimp + b56: 0301 addi t1,t1,0 + b58: 0901 addi s2,s2,0 + b5a: 0000 unimp + b5c: 0301 addi t1,t1,0 + b5e: 0902 c.slli64 s2 + b60: 0000 unimp + b62: 0301 addi t1,t1,0 + b64: 0901 addi s2,s2,0 + b66: 0000 unimp + b68: 0301 addi t1,t1,0 + b6a: 0900 addi s0,sp,144 + b6c: 0000 unimp + b6e: 0301 addi t1,t1,0 + b70: 0900 addi s0,sp,144 + b72: 0000 unimp + b74: 0301 addi t1,t1,0 + b76: 0900 addi s0,sp,144 + b78: 0000 unimp + b7a: 0301 addi t1,t1,0 + b7c: 0900 addi s0,sp,144 + b7e: 0000 unimp + b80: 0501 addi a0,a0,0 + b82: 0601 addi a2,a2,0 + b84: 00097803 0x97803 + b88: 0100 addi s0,sp,128 + b8a: 0305 addi t1,t1,1 + b8c: 18090803 lb a6,384(s2) + b90: 0100 addi s0,sp,128 + b92: 0105 addi sp,sp,1 + b94: 04097803 0x4097803 + b98: 0100 addi s0,sp,128 + b9a: 10090003 lb zero,256(s2) + b9e: 0100 addi s0,sp,128 + ba0: 0305 addi t1,t1,1 + ba2: 04090803 lb a6,64(s2) + ba6: 0100 addi s0,sp,128 + ba8: 0306 slli t1,t1,0x1 + baa: 0900 addi s0,sp,144 + bac: 0004 0x4 + bae: 0301 addi t1,t1,0 + bb0: 0900 addi s0,sp,144 + bb2: 0000 unimp + bb4: 0301 addi t1,t1,0 + bb6: 0900 addi s0,sp,144 + bb8: 0004 0x4 + bba: 0301 addi t1,t1,0 + bbc: 0900 addi s0,sp,144 + bbe: 0000 unimp + bc0: 0301 addi t1,t1,0 + bc2: 0900 addi s0,sp,144 + bc4: 0000 unimp + bc6: 0001 nop + bc8: 0402 c.slli64 s0 + bca: 0301 addi t1,t1,0 + bcc: 0900 addi s0,sp,144 + bce: 000c 0xc + bd0: 0001 nop + bd2: 0402 c.slli64 s0 + bd4: 0301 addi t1,t1,0 + bd6: 0900 addi s0,sp,144 + bd8: 0000 unimp + bda: 0001 nop + bdc: 0402 c.slli64 s0 + bde: 0301 addi t1,t1,0 + be0: 0900 addi s0,sp,144 + be2: 0000 unimp + be4: 0001 nop + be6: 0402 c.slli64 s0 + be8: 0301 addi t1,t1,0 + bea: 0900 addi s0,sp,144 + bec: 0000 unimp + bee: 0001 nop + bf0: 0402 c.slli64 s0 + bf2: 0301 addi t1,t1,0 + bf4: 0900 addi s0,sp,144 + bf6: 000c 0xc + bf8: 0001 nop + bfa: 0402 c.slli64 s0 + bfc: 0301 addi t1,t1,0 + bfe: 0900 addi s0,sp,144 + c00: 0000 unimp + c02: 0001 nop + c04: 0402 c.slli64 s0 + c06: 0301 addi t1,t1,0 + c08: 0900 addi s0,sp,144 + c0a: 0004 0x4 + c0c: 0001 nop + c0e: 0402 c.slli64 s0 + c10: 0301 addi t1,t1,0 + c12: 0900 addi s0,sp,144 + c14: 0000 unimp + c16: 0001 nop + c18: 0402 c.slli64 s0 + c1a: 0900030f 0x900030f + c1e: 0000 unimp + c20: 0001 nop + c22: 0402 c.slli64 s0 + c24: 0900030f 0x900030f + c28: 0000 unimp + c2a: 0001 nop + c2c: 0402 c.slli64 s0 + c2e: 0308 addi a0,sp,384 + c30: 0900 addi s0,sp,144 + c32: 0004 0x4 + c34: 0001 nop + c36: 0402 c.slli64 s0 + c38: 0308 addi a0,sp,384 + c3a: 0900 addi s0,sp,144 + c3c: 0000 unimp + c3e: 0001 nop + c40: 0402 c.slli64 s0 + c42: 0308 addi a0,sp,384 + c44: 0901 addi s2,s2,0 + c46: 0000 unimp + c48: 0001 nop + c4a: 0402 c.slli64 s0 + c4c: 0308 addi a0,sp,384 + c4e: 0900 addi s0,sp,144 + c50: 0000 unimp + c52: 0001 nop + c54: 0402 c.slli64 s0 + c56: 0308 addi a0,sp,384 + c58: 0900 addi s0,sp,144 + c5a: 0000 unimp + c5c: 0001 nop + c5e: 0402 c.slli64 s0 + c60: 0308 addi a0,sp,384 + c62: 0900 addi s0,sp,144 + c64: 0000 unimp + c66: 0001 nop + c68: 0402 c.slli64 s0 + c6a: 0308 addi a0,sp,384 + c6c: 0900 addi s0,sp,144 + c6e: 0000 unimp + c70: 0001 nop + c72: 0402 c.slli64 s0 + c74: 0308 addi a0,sp,384 + c76: 0900 addi s0,sp,144 + c78: 0010 0x10 + c7a: 0001 nop + c7c: 0402 c.slli64 s0 + c7e: 0308 addi a0,sp,384 + c80: 0900 addi s0,sp,144 + c82: 0000 unimp + c84: 0001 nop + c86: 0402 c.slli64 s0 + c88: 0308 addi a0,sp,384 + c8a: 0900 addi s0,sp,144 + c8c: 0004 0x4 + c8e: 0001 nop + c90: 0402 c.slli64 s0 + c92: 0308 addi a0,sp,384 + c94: 0900 addi s0,sp,144 + c96: 0000 unimp + c98: 0001 nop + c9a: 0402 c.slli64 s0 + c9c: 0308 addi a0,sp,384 + c9e: 0900 addi s0,sp,144 + ca0: 0000 unimp + ca2: 0601 addi a2,a2,0 + ca4: 04090003 lb zero,64(s2) + ca8: 0100 addi s0,sp,128 + caa: 0200 addi s0,sp,256 + cac: 0104 addi s1,sp,128 + cae: 0306 slli t1,t1,0x1 + cb0: 0900 addi s0,sp,144 + cb2: 0008 0x8 + cb4: 0001 nop + cb6: 0402 c.slli64 s0 + cb8: 0301 addi t1,t1,0 + cba: 0900 addi s0,sp,144 + cbc: 0000 unimp + cbe: 0001 nop + cc0: 0402 c.slli64 s0 + cc2: 0301 addi t1,t1,0 + cc4: 0900 addi s0,sp,144 + cc6: 0000 unimp + cc8: 0001 nop + cca: 0402 c.slli64 s0 + ccc: 0301 addi t1,t1,0 + cce: 0900 addi s0,sp,144 + cd0: 0000 unimp + cd2: 0001 nop + cd4: 0402 c.slli64 s0 + cd6: 0301 addi t1,t1,0 + cd8: 0900 addi s0,sp,144 + cda: 000c 0xc + cdc: 0001 nop + cde: 0402 c.slli64 s0 + ce0: 0301 addi t1,t1,0 + ce2: 0900 addi s0,sp,144 + ce4: 0000 unimp + ce6: 0001 nop + ce8: 0402 c.slli64 s0 + cea: 0301 addi t1,t1,0 + cec: 0900 addi s0,sp,144 + cee: 0004 0x4 + cf0: 0001 nop + cf2: 0402 c.slli64 s0 + cf4: 0301 addi t1,t1,0 + cf6: 0900 addi s0,sp,144 + cf8: 0000 unimp + cfa: 0001 nop + cfc: 0402 c.slli64 s0 + cfe: 0900030f 0x900030f + d02: 0000 unimp + d04: 0001 nop + d06: 0402 c.slli64 s0 + d08: 0900030f 0x900030f + d0c: 0000 unimp + d0e: 0001 nop + d10: 0402 c.slli64 s0 + d12: 0308 addi a0,sp,384 + d14: 0900 addi s0,sp,144 + d16: 0004 0x4 + d18: 0001 nop + d1a: 0402 c.slli64 s0 + d1c: 0308 addi a0,sp,384 + d1e: 0900 addi s0,sp,144 + d20: 0000 unimp + d22: 0001 nop + d24: 0402 c.slli64 s0 + d26: 0308 addi a0,sp,384 + d28: 0901 addi s2,s2,0 + d2a: 0000 unimp + d2c: 0001 nop + d2e: 0402 c.slli64 s0 + d30: 0308 addi a0,sp,384 + d32: 0900 addi s0,sp,144 + d34: 0000 unimp + d36: 0001 nop + d38: 0402 c.slli64 s0 + d3a: 0308 addi a0,sp,384 + d3c: 0900 addi s0,sp,144 + d3e: 0018 0x18 + d40: 0001 nop + d42: 0402 c.slli64 s0 + d44: 0308 addi a0,sp,384 + d46: 0900 addi s0,sp,144 + d48: 0000 unimp + d4a: 0001 nop + d4c: 0402 c.slli64 s0 + d4e: 0302 c.slli64 t1 + d50: 097e slli s2,s2,0x1f + d52: 001c 0x1c + d54: 0001 nop + d56: 0402 c.slli64 s0 + d58: 0900030f 0x900030f + d5c: 0004 0x4 + d5e: 0001 nop + d60: 0402 c.slli64 s0 + d62: 0900030f 0x900030f + d66: 0000 unimp + d68: 0001 nop + d6a: 0402 c.slli64 s0 + d6c: 0900030f 0x900030f + d70: 0000 unimp + d72: 0001 nop + d74: 0402 c.slli64 s0 + d76: 0900030f 0x900030f + d7a: 0000 unimp + d7c: 0001 nop + d7e: 0402 c.slli64 s0 + d80: 0900030f 0x900030f + d84: 0000 unimp + d86: 0001 nop + d88: 0402 c.slli64 s0 + d8a: 0900030f 0x900030f + d8e: 0000 unimp + d90: 0001 nop + d92: 0402 c.slli64 s0 + d94: 0900030f 0x900030f + d98: 0008 0x8 + d9a: 0001 nop + d9c: 0402 c.slli64 s0 + d9e: 0900030f 0x900030f + da2: 0000 unimp + da4: 0001 nop + da6: 0402 c.slli64 s0 + da8: 0900030f 0x900030f + dac: 0000 unimp + dae: 0001 nop + db0: 0402 c.slli64 s0 + db2: 0900030f 0x900030f + db6: 0000 unimp + db8: 0001 nop + dba: 0402 c.slli64 s0 + dbc: 0900030f 0x900030f + dc0: 0000 unimp + dc2: 0001 nop + dc4: 0402 c.slli64 s0 + dc6: 0900030f 0x900030f + dca: 000c 0xc + dcc: 0001 nop + dce: 0402 c.slli64 s0 + dd0: 0900030f 0x900030f + dd4: 0000 unimp + dd6: 0001 nop + dd8: 0402 c.slli64 s0 + dda: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> + dde: 0008 0x8 + de0: 0601 addi a2,a2,0 + de2: 0c090003 lb zero,192(s2) + de6: 0100 addi s0,sp,128 + de8: 0200 addi s0,sp,256 + dea: 0204 addi s1,sp,256 + dec: 0306 slli t1,t1,0x1 + dee: 0901 addi s2,s2,0 + df0: 0014 0x14 + df2: 0001 nop + df4: 0402 c.slli64 s0 + df6: 0900030f 0x900030f + dfa: 0004 0x4 + dfc: 0001 nop + dfe: 0402 c.slli64 s0 + e00: 0900030f 0x900030f + e04: 0000 unimp + e06: 0001 nop + e08: 0402 c.slli64 s0 + e0a: 0900030f 0x900030f + e0e: 0000 unimp + e10: 0001 nop + e12: 0402 c.slli64 s0 + e14: 0900030f 0x900030f + e18: 0000 unimp + e1a: 0001 nop + e1c: 0402 c.slli64 s0 + e1e: 0900030f 0x900030f + e22: 0000 unimp + e24: 0001 nop + e26: 0402 c.slli64 s0 + e28: 0900030f 0x900030f + e2c: 0000 unimp + e2e: 0001 nop + e30: 0402 c.slli64 s0 + e32: 0900030f 0x900030f + e36: 0008 0x8 + e38: 0001 nop + e3a: 0402 c.slli64 s0 + e3c: 0900030f 0x900030f + e40: 0000 unimp + e42: 0001 nop + e44: 0402 c.slli64 s0 + e46: 0900030f 0x900030f + e4a: 0000 unimp + e4c: 0001 nop + e4e: 0402 c.slli64 s0 + e50: 0900030f 0x900030f + e54: 0000 unimp + e56: 0001 nop + e58: 0402 c.slli64 s0 + e5a: 0900030f 0x900030f + e5e: 0000 unimp + e60: 0001 nop + e62: 0402 c.slli64 s0 + e64: 0900030f 0x900030f + e68: 0008 0x8 + e6a: 0001 nop + e6c: 0402 c.slli64 s0 + e6e: 0900030f 0x900030f + e72: 0000 unimp + e74: 0001 nop + e76: 0402 c.slli64 s0 + e78: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> + e7c: 000c 0xc + e7e: 0601 addi a2,a2,0 + e80: 0c090003 lb zero,192(s2) + e84: 0100 addi s0,sp,128 + e86: 0200 addi s0,sp,256 + e88: 0204 addi s1,sp,256 + e8a: 0306 slli t1,t1,0x1 + e8c: 0901 addi s2,s2,0 + e8e: 0014 0x14 + e90: 0001 nop + e92: 0402 c.slli64 s0 + e94: 0302 c.slli64 t1 + e96: 0900 addi s0,sp,144 + e98: 0000 unimp + e9a: 0001 nop + e9c: 0402 c.slli64 s0 + e9e: 0302 c.slli64 t1 + ea0: 0900 addi s0,sp,144 + ea2: 0000 unimp + ea4: 0001 nop + ea6: 0402 c.slli64 s0 + ea8: 0302 c.slli64 t1 + eaa: 0900 addi s0,sp,144 + eac: 0000 unimp + eae: 0001 nop + eb0: 0402 c.slli64 s0 + eb2: 0302 c.slli64 t1 + eb4: 0900 addi s0,sp,144 + eb6: 0000 unimp + eb8: 0001 nop + eba: 0402 c.slli64 s0 + ebc: 0302 c.slli64 t1 + ebe: 0900 addi s0,sp,144 + ec0: 0000 unimp + ec2: 0001 nop + ec4: 0402 c.slli64 s0 + ec6: 0302 c.slli64 t1 + ec8: 0900 addi s0,sp,144 + eca: 0000 unimp + ecc: 0001 nop + ece: 0402 c.slli64 s0 + ed0: 0302 c.slli64 t1 + ed2: 0900 addi s0,sp,144 + ed4: 0000 unimp + ed6: 0001 nop + ed8: 0402 c.slli64 s0 + eda: 0302 c.slli64 t1 + edc: 0900 addi s0,sp,144 + ede: 0004 0x4 + ee0: 0001 nop + ee2: 0402 c.slli64 s0 + ee4: 030a slli t1,t1,0x2 + ee6: 0900 addi s0,sp,144 + ee8: 0004 0x4 + eea: 0001 nop + eec: 0402 c.slli64 s0 + eee: 030a slli t1,t1,0x2 + ef0: 0900 addi s0,sp,144 + ef2: 0004 0x4 + ef4: 0001 nop + ef6: 0402 c.slli64 s0 + ef8: 030a slli t1,t1,0x2 + efa: 0900 addi s0,sp,144 + efc: 0000 unimp + efe: 0001 nop + f00: 0402 c.slli64 s0 + f02: 030d addi t1,t1,3 + f04: 0900 addi s0,sp,144 + f06: 0004 0x4 + f08: 0001 nop + f0a: 0402 c.slli64 s0 + f0c: 030d addi t1,t1,3 + f0e: 0900 addi s0,sp,144 + f10: 0000 unimp + f12: 0001 nop + f14: 0402 c.slli64 s0 + f16: 030d addi t1,t1,3 + f18: 0900 addi s0,sp,144 + f1a: 0000 unimp + f1c: 0001 nop + f1e: 0402 c.slli64 s0 + f20: 030d addi t1,t1,3 + f22: 0900 addi s0,sp,144 + f24: 0000 unimp + f26: 0001 nop + f28: 0402 c.slli64 s0 + f2a: 030d addi t1,t1,3 + f2c: 0900 addi s0,sp,144 + f2e: 0004 0x4 + f30: 0001 nop + f32: 0402 c.slli64 s0 + f34: 030d addi t1,t1,3 + f36: 0900 addi s0,sp,144 + f38: 0010 0x10 + f3a: 0001 nop + f3c: 0402 c.slli64 s0 + f3e: 030d addi t1,t1,3 + f40: 0900 addi s0,sp,144 + f42: 0000 unimp + f44: 0001 nop + f46: 0402 c.slli64 s0 + f48: 030d addi t1,t1,3 + f4a: 0900 addi s0,sp,144 + f4c: 0000 unimp + f4e: 0001 nop + f50: 0402 c.slli64 s0 + f52: 030d addi t1,t1,3 + f54: 0900 addi s0,sp,144 + f56: 0010 0x10 + f58: 0001 nop + f5a: 0402 c.slli64 s0 + f5c: 030d addi t1,t1,3 + f5e: 0900 addi s0,sp,144 + f60: 0008 0x8 + f62: 0001 nop + f64: 0402 c.slli64 s0 + f66: 030e slli t1,t1,0x3 + f68: 0900 addi s0,sp,144 + f6a: 0004 0x4 + f6c: 0001 nop + f6e: 0402 c.slli64 s0 + f70: 030e slli t1,t1,0x3 + f72: 0900 addi s0,sp,144 + f74: 0008 0x8 + f76: 0001 nop + f78: 0402 c.slli64 s0 + f7a: 0310 addi a2,sp,384 + f7c: 0900 addi s0,sp,144 + f7e: 0004 0x4 + f80: 0001 nop + f82: 0402 c.slli64 s0 + f84: 0312 slli t1,t1,0x4 + f86: 0900 addi s0,sp,144 + f88: 0004 0x4 + f8a: 0001 nop + f8c: 0402 c.slli64 s0 + f8e: 0314 addi a3,sp,384 + f90: 0900 addi s0,sp,144 + f92: 0008 0x8 + f94: 0001 nop + f96: 0402 c.slli64 s0 + f98: 0314 addi a3,sp,384 + f9a: 0900 addi s0,sp,144 + f9c: 0004 0x4 + f9e: 0001 nop + fa0: 0402 c.slli64 s0 + fa2: 0314 addi a3,sp,384 + fa4: 0900 addi s0,sp,144 + fa6: 0000 unimp + fa8: 0001 nop + faa: 0402 c.slli64 s0 + fac: 0314 addi a3,sp,384 + fae: 0900 addi s0,sp,144 + fb0: 0004 0x4 + fb2: 0001 nop + fb4: 0402 c.slli64 s0 + fb6: 0314 addi a3,sp,384 + fb8: 0900 addi s0,sp,144 + fba: 0008 0x8 + fbc: 0001 nop + fbe: 0402 c.slli64 s0 + fc0: 0314 addi a3,sp,384 + fc2: 0900 addi s0,sp,144 + fc4: 0004 0x4 + fc6: 0001 nop + fc8: 0402 c.slli64 s0 + fca: 0315 addi t1,t1,5 + fcc: 0900 addi s0,sp,144 + fce: 0008 0x8 + fd0: 0001 nop + fd2: 0402 c.slli64 s0 + fd4: 0315 addi t1,t1,5 + fd6: 0900 addi s0,sp,144 + fd8: 0008 0x8 + fda: 0001 nop + fdc: 0402 c.slli64 s0 + fde: 09000317 auipc t1,0x9000 + fe2: 0004 0x4 + fe4: 0001 nop + fe6: 0402 c.slli64 s0 + fe8: 0319 addi t1,t1,6 + fea: 0900 addi s0,sp,144 + fec: 0004 0x4 + fee: 0001 nop + ff0: 0402 c.slli64 s0 + ff2: 0900031b 0x900031b + ff6: 0008 0x8 + ff8: 0001 nop + ffa: 0402 c.slli64 s0 + ffc: 0900031b 0x900031b + 1000: 0000 unimp + 1002: 0001 nop + 1004: 0402 c.slli64 s0 + 1006: 0900031b 0x900031b + 100a: 0000 unimp + 100c: 0001 nop + 100e: 0402 c.slli64 s0 + 1010: 0900031b 0x900031b + 1014: 0000 unimp + 1016: 0001 nop + 1018: 0402 c.slli64 s0 + 101a: 0900031b 0x900031b + 101e: 0000 unimp + 1020: 0001 nop + 1022: 0402 c.slli64 s0 + 1024: 0900031b 0x900031b + 1028: 0014 0x14 + 102a: 0001 nop + 102c: 0402 c.slli64 s0 + 102e: 0900031b 0x900031b + 1032: 0000 unimp + 1034: 0001 nop + 1036: 0402 c.slli64 s0 + 1038: 0900031b 0x900031b + 103c: 0000 unimp + 103e: 0001 nop + 1040: 0402 c.slli64 s0 + 1042: 0901031b 0x901031b + 1046: 0000 unimp + 1048: 0001 nop + 104a: 0402 c.slli64 s0 + 104c: 0900031b 0x900031b + 1050: 0000 unimp + 1052: 0001 nop + 1054: 0402 c.slli64 s0 + 1056: 0900031b 0x900031b + 105a: 0000 unimp + 105c: 0001 nop + 105e: 0402 c.slli64 s0 + 1060: 0302 c.slli64 t1 + 1062: 0900 addi s0,sp,144 + 1064: 0000 unimp + 1066: 0001 nop + 1068: 0402 c.slli64 s0 + 106a: 0302 c.slli64 t1 + 106c: 0900 addi s0,sp,144 + 106e: 0004 0x4 + 1070: 0001 nop + 1072: 0402 c.slli64 s0 + 1074: 0306 slli t1,t1,0x1 + 1076: 0900 addi s0,sp,144 + 1078: 0004 0x4 + 107a: 0001 nop + 107c: 0402 c.slli64 s0 + 107e: 0306 slli t1,t1,0x1 + 1080: 0900 addi s0,sp,144 + 1082: 0000 unimp + 1084: 0001 nop + 1086: 0402 c.slli64 s0 + 1088: 0308 addi a0,sp,384 + 108a: 0900 addi s0,sp,144 + 108c: 0008 0x8 + 108e: 0001 nop + 1090: 0402 c.slli64 s0 + 1092: 0308 addi a0,sp,384 + 1094: 0900 addi s0,sp,144 + 1096: 0000 unimp + 1098: 0001 nop + 109a: 0402 c.slli64 s0 + 109c: 0308 addi a0,sp,384 + 109e: 0900 addi s0,sp,144 + 10a0: 0000 unimp + 10a2: 0001 nop + 10a4: 0402 c.slli64 s0 + 10a6: 0308 addi a0,sp,384 + 10a8: 0900 addi s0,sp,144 + 10aa: 0000 unimp + 10ac: 0001 nop + 10ae: 0402 c.slli64 s0 + 10b0: 030a slli t1,t1,0x2 + 10b2: 0900 addi s0,sp,144 + 10b4: 000c 0xc + 10b6: 0001 nop + 10b8: 0402 c.slli64 s0 + 10ba: 0309 addi t1,t1,2 + 10bc: 0900 addi s0,sp,144 + 10be: 0004 0x4 + 10c0: 0001 nop + 10c2: 0402 c.slli64 s0 + 10c4: 0309 addi t1,t1,2 + 10c6: 0900 addi s0,sp,144 + 10c8: 0000 unimp + 10ca: 0001 nop + 10cc: 0402 c.slli64 s0 + 10ce: 0318 addi a4,sp,384 + 10d0: 0900 addi s0,sp,144 + 10d2: 0008 0x8 + 10d4: 0001 nop + 10d6: 0402 c.slli64 s0 + 10d8: 0318 addi a4,sp,384 + 10da: 0900 addi s0,sp,144 + 10dc: 000c 0xc + 10de: 0001 nop + 10e0: 0402 c.slli64 s0 + 10e2: 031a slli t1,t1,0x6 + 10e4: 0900 addi s0,sp,144 + 10e6: 0004 0x4 + 10e8: 0001 nop + 10ea: 0402 c.slli64 s0 + 10ec: 031a slli t1,t1,0x6 + 10ee: 0900 addi s0,sp,144 + 10f0: 0000 unimp + 10f2: 0001 nop + 10f4: 0402 c.slli64 s0 + 10f6: 0900036f jal t1,1186 <_start-0x7fffee7a> + 10fa: 000c 0xc + 10fc: 0001 nop + 10fe: 0402 c.slli64 s0 + 1100: 0900036f jal t1,1190 <_start-0x7fffee70> + 1104: 0000 unimp + 1106: 0001 nop + 1108: 0402 c.slli64 s0 + 110a: 0900036f jal t1,119a <_start-0x7fffee66> + 110e: 0000 unimp + 1110: 0001 nop + 1112: 0402 c.slli64 s0 + 1114: 0900036f jal t1,11a4 <_start-0x7fffee5c> + 1118: 0000 unimp + 111a: 0001 nop + 111c: 0402 c.slli64 s0 + 111e: 0900036f jal t1,11ae <_start-0x7fffee52> + 1122: 0000 unimp + 1124: 0001 nop + 1126: 0402 c.slli64 s0 + 1128: 0900036f jal t1,11b8 <_start-0x7fffee48> + 112c: 0000 unimp + 112e: 0001 nop + 1130: 0402 c.slli64 s0 + 1132: 0900036f jal t1,11c2 <_start-0x7fffee3e> + 1136: 001c 0x1c + 1138: 0001 nop + 113a: 0402 c.slli64 s0 + 113c: 0900036f jal t1,11cc <_start-0x7fffee34> + 1140: 0000 unimp + 1142: 0001 nop + 1144: 0402 c.slli64 s0 + 1146: 0900036f jal t1,11d6 <_start-0x7fffee2a> + 114a: 0000 unimp + 114c: 0001 nop + 114e: 0402 c.slli64 s0 + 1150: 0901036f jal t1,111e0 <_start-0x7ffeee20> + 1154: 0000 unimp + 1156: 0001 nop + 1158: 0402 c.slli64 s0 + 115a: 0900036f jal t1,11ea <_start-0x7fffee16> + 115e: 0000 unimp + 1160: 0001 nop + 1162: 0402 c.slli64 s0 + 1164: 0900036f jal t1,11f4 <_start-0x7fffee0c> + 1168: 0000 unimp + 116a: 0001 nop + 116c: 0402 c.slli64 s0 + 116e: 0902036f jal t1,211fe <_start-0x7ffdee02> + 1172: 0000 unimp + 1174: 0501 addi a0,a0,0 + 1176: 0001 nop + 1178: 0402 c.slli64 s0 + 117a: 0103066f jal a2,3118a <_start-0x7ffcee76> + 117e: 0009 c.nop 2 + 1180: 0100 addi s0,sp,128 + 1182: 0305 addi t1,t1,1 + 1184: 0200 addi s0,sp,256 + 1186: 0b04 addi s1,sp,400 + 1188: 0306 slli t1,t1,0x1 + 118a: 0028097b 0x28097b + 118e: 0001 nop + 1190: 0402 c.slli64 s0 + 1192: 0900030b 0x900030b + 1196: 0004 0x4 + 1198: 0001 nop + 119a: 0402 c.slli64 s0 + 119c: 0608 addi a0,sp,768 + 119e: 08097e03 0x8097e03 + 11a2: 0100 addi s0,sp,128 + 11a4: 0200 addi s0,sp,256 + 11a6: 0804 addi s1,sp,16 + 11a8: 0306 slli t1,t1,0x1 + 11aa: 0902 c.slli64 s2 + 11ac: 0004 0x4 + 11ae: 0001 nop + 11b0: 0402 c.slli64 s0 + 11b2: 0308 addi a0,sp,384 + 11b4: 0900 addi s0,sp,144 + 11b6: 0000 unimp + 11b8: 0001 nop + 11ba: 0402 c.slli64 s0 + 11bc: 0308 addi a0,sp,384 + 11be: 0900 addi s0,sp,144 + 11c0: 0000 unimp + 11c2: 0001 nop + 11c4: 0402 c.slli64 s0 + 11c6: 0308 addi a0,sp,384 + 11c8: 0900 addi s0,sp,144 + 11ca: 0000 unimp + 11cc: 0001 nop + 11ce: 0402 c.slli64 s0 + 11d0: 09000323 sb a6,134(zero) # 86 <_start-0x7fffff7a> + 11d4: 0008 0x8 + 11d6: 0001 nop + 11d8: 0402 c.slli64 s0 + 11da: 09010323 sb a6,134(sp) + 11de: 0000 unimp + 11e0: 0001 nop + 11e2: 0402 c.slli64 s0 + 11e4: 09000323 sb a6,134(zero) # 86 <_start-0x7fffff7a> + 11e8: 0000 unimp + 11ea: 0001 nop + 11ec: 0402 c.slli64 s0 + 11ee: 09000323 sb a6,134(zero) # 86 <_start-0x7fffff7a> + 11f2: 0000 unimp + 11f4: 0601 addi a2,a2,0 + 11f6: 08090003 lb zero,128(s2) + 11fa: 0100 addi s0,sp,128 + 11fc: 0200 addi s0,sp,256 + 11fe: 0504 addi s1,sp,640 + 1200: 1c097e03 0x1c097e03 + 1204: 0100 addi s0,sp,128 + 1206: 0200 addi s0,sp,256 + 1208: 0504 addi s1,sp,640 + 120a: 0306 slli t1,t1,0x1 + 120c: 0901 addi s2,s2,0 + 120e: 0004 0x4 + 1210: 0001 nop + 1212: 0402 c.slli64 s0 + 1214: 0305 addi t1,t1,1 + 1216: 0900 addi s0,sp,144 + 1218: 0000 unimp + 121a: 0001 nop + 121c: 0402 c.slli64 s0 + 121e: 0305 addi t1,t1,1 + 1220: 0900 addi s0,sp,144 + 1222: 0000 unimp + 1224: 0001 nop + 1226: 0402 c.slli64 s0 + 1228: 0305 addi t1,t1,1 + 122a: 0900 addi s0,sp,144 + 122c: 0000 unimp + 122e: 0601 addi a2,a2,0 + 1230: 04090003 lb zero,64(s2) + 1234: 0100 addi s0,sp,128 + 1236: 0200 addi s0,sp,256 + 1238: 3b04 fld fs1,48(a4) + 123a: 0306 slli t1,t1,0x1 + 123c: 0901 addi s2,s2,0 + 123e: 0010 0x10 + 1240: 0001 nop + 1242: 0402 c.slli64 s0 + 1244: 0900033b 0x900033b + 1248: 0000 unimp + 124a: 0001 nop + 124c: 0402 c.slli64 s0 + 124e: 0900033b 0x900033b + 1252: 0000 unimp + 1254: 0001 nop + 1256: 0402 c.slli64 s0 + 1258: 0900033b 0x900033b + 125c: 0008 0x8 + 125e: 0001 nop + 1260: 0402 c.slli64 s0 + 1262: 033c addi a5,sp,392 + 1264: 0900 addi s0,sp,144 + 1266: 0008 0x8 + 1268: 0001 nop + 126a: 0402 c.slli64 s0 + 126c: 033c addi a5,sp,392 + 126e: 0900 addi s0,sp,144 + 1270: 0014 0x14 + 1272: 0001 nop + 1274: 0402 c.slli64 s0 + 1276: 033c addi a5,sp,392 + 1278: 0900 addi s0,sp,144 + 127a: 0000 unimp + 127c: 0001 nop + 127e: 0402 c.slli64 s0 + 1280: 0344 addi s1,sp,388 + 1282: 0900 addi s0,sp,144 + 1284: 0008 0x8 + 1286: 0001 nop + 1288: 0402 c.slli64 s0 + 128a: 0344 addi s1,sp,388 + 128c: 0900 addi s0,sp,144 + 128e: 0000 unimp + 1290: 0001 nop + 1292: 0402 c.slli64 s0 + 1294: 0344 addi s1,sp,388 + 1296: 0900 addi s0,sp,144 + 1298: 0000 unimp + 129a: 0001 nop + 129c: 0402 c.slli64 s0 + 129e: 0344 addi s1,sp,388 + 12a0: 0900 addi s0,sp,144 + 12a2: 0000 unimp + 12a4: 0001 nop + 12a6: 0402 c.slli64 s0 + 12a8: 0346 slli t1,t1,0x11 + 12aa: 0900 addi s0,sp,144 + 12ac: 000c 0xc + 12ae: 0001 nop + 12b0: 0402 c.slli64 s0 + 12b2: 0345 addi t1,t1,17 + 12b4: 0900 addi s0,sp,144 + 12b6: 0004 0x4 + 12b8: 0001 nop + 12ba: 0402 c.slli64 s0 + 12bc: 0345 addi t1,t1,17 + 12be: 0900 addi s0,sp,144 + 12c0: 0000 unimp + 12c2: 0601 addi a2,a2,0 + 12c4: 0c090003 lb zero,192(s2) + 12c8: 0100 addi s0,sp,128 + 12ca: 2809 jal 12dc <_start-0x7fffed24> + 12cc: 0000 unimp + 12ce: 0101 addi sp,sp,0 + 12d0: 0000031b 0x31b + 12d4: 00a50003 lb zero,10(a0) # 9d546 <_start-0x7ff62aba> + 12d8: 0000 unimp + 12da: 0101 addi sp,sp,0 + 12dc: 000d0efb 0xd0efb + 12e0: 0101 addi sp,sp,0 + 12e2: 0101 addi sp,sp,0 + 12e4: 0000 unimp + 12e6: 0100 addi s0,sp,128 + 12e8: 0000 unimp + 12ea: 2e01 jal 15fa <_start-0x7fffea06> + 12ec: 2f2e fld ft10,200(sp) + 12ee: 2e2e fld ft8,200(sp) + 12f0: 2f2e2e2f 0x2f2e2e2f + 12f4: 2e2e fld ft8,200(sp) + 12f6: 7369722f 0x7369722f + 12fa: 672d7663 bgeu s10,s2,1966 <_start-0x7fffe69a> + 12fe: 6c2f6363 bltu t5,sp,19c4 <_start-0x7fffe63c> + 1302: 6269 lui tp,0x1a + 1304: 2f636367 0x2f636367 + 1308: 74666f73 csrrsi t5,0x746,12 + 130c: 662d lui a2,0xb + 130e: 0070 addi a2,sp,12 + 1310: 002e c.slli zero,0xb + 1312: 2e2e fld ft8,200(sp) + 1314: 2f2e2e2f 0x2f2e2e2f + 1318: 2e2e fld ft8,200(sp) + 131a: 2f2e2e2f 0x2f2e2e2f + 131e: 6972 flw fs2,28(sp) + 1320: 2d766373 csrrsi t1,0x2d7,12 + 1324: 2f636367 0x2f636367 + 1328: 696c flw fa1,84(a0) + 132a: 6762 flw fa4,24(sp) + 132c: 2e2f6363 bltu t5,sp,1612 <_start-0x7fffe9ee> + 1330: 2f2e fld ft10,200(sp) + 1332: 6e69 lui t3,0x1a + 1334: 64756c63 bltu a0,t2,198c <_start-0x7fffe674> + 1338: 0065 c.nop 25 + 133a: 6c00 flw fs0,24(s0) + 133c: 7365 lui t1,0xffff9 + 133e: 3266 fld ft4,120(sp) + 1340: 632e flw ft6,200(sp) + 1342: 0100 addi s0,sp,128 + 1344: 0000 unimp + 1346: 2d706673 csrrsi a2,0x2d7,0 + 134a: 616d addi sp,sp,240 + 134c: 6e696863 bltu s2,t1,1a3c <_start-0x7fffe5c4> + 1350: 2e65 jal 1708 <_start-0x7fffe8f8> + 1352: 0068 addi a0,sp,12 + 1354: 0002 c.slli64 zero + 1356: 7300 flw fs0,32(a4) + 1358: 2d74666f jal a2,47e2e <_start-0x7ffb81d2> + 135c: 7066 flw ft0,120(sp) + 135e: 682e flw fa6,200(sp) + 1360: 0100 addi s0,sp,128 + 1362: 0000 unimp + 1364: 676e6973 csrrsi s2,0x676,28 + 1368: 656c flw fa1,76(a0) + 136a: 682e flw fa6,200(sp) + 136c: 0100 addi s0,sp,128 + 136e: 0000 unimp + 1370: 6f6c flw fa1,92(a4) + 1372: 676e flw fa4,216(sp) + 1374: 6f6c flw fa1,92(a4) + 1376: 676e flw fa4,216(sp) + 1378: 682e flw fa6,200(sp) + 137a: 0300 addi s0,sp,384 + 137c: 0000 unimp + 137e: 0500 addi s0,sp,640 + 1380: 0001 nop + 1382: 0205 addi tp,tp,1 + 1384: 1640 addi s0,sp,804 + 1386: 8000 0x8000 + 1388: 05012303 lw t1,80(sp) + 138c: 09010303 lb t1,144(sp) + 1390: 0000 unimp + 1392: 0301 addi t1,t1,0 + 1394: 0900 addi s0,sp,144 + 1396: 0000 unimp + 1398: 0501 addi a0,a0,0 + 139a: 030d addi t1,t1,3 + 139c: 0900 addi s0,sp,144 + 139e: 0000 unimp + 13a0: 0501 addi a0,a0,0 + 13a2: 09010303 lb t1,144(sp) + 13a6: 0000 unimp + 13a8: 0301 addi t1,t1,0 + 13aa: 0900 addi s0,sp,144 + 13ac: 0000 unimp + 13ae: 0301 addi t1,t1,0 + 13b0: 0900 addi s0,sp,144 + 13b2: 0000 unimp + 13b4: 0301 addi t1,t1,0 + 13b6: 0900 addi s0,sp,144 + 13b8: 0000 unimp + 13ba: 0301 addi t1,t1,0 + 13bc: 0901 addi s2,s2,0 + 13be: 0000 unimp + 13c0: 0301 addi t1,t1,0 + 13c2: 0900 addi s0,sp,144 + 13c4: 0000 unimp + 13c6: 0301 addi t1,t1,0 + 13c8: 0900 addi s0,sp,144 + 13ca: 0000 unimp + 13cc: 0301 addi t1,t1,0 + 13ce: 0900 addi s0,sp,144 + 13d0: 0000 unimp + 13d2: 0301 addi t1,t1,0 + 13d4: 0901 addi s2,s2,0 + 13d6: 0000 unimp + 13d8: 0301 addi t1,t1,0 + 13da: 0902 c.slli64 s2 + 13dc: 0000 unimp + 13de: 0301 addi t1,t1,0 + 13e0: 0901 addi s2,s2,0 + 13e2: 0000 unimp + 13e4: 0301 addi t1,t1,0 + 13e6: 0900 addi s0,sp,144 + 13e8: 0000 unimp + 13ea: 0301 addi t1,t1,0 + 13ec: 0900 addi s0,sp,144 + 13ee: 0000 unimp + 13f0: 0301 addi t1,t1,0 + 13f2: 0900 addi s0,sp,144 + 13f4: 0000 unimp + 13f6: 0601 addi a2,a2,0 + 13f8: 14090203 lb tp,320(s2) + 13fc: 0100 addi s0,sp,128 + 13fe: 04097e03 0x4097e03 + 1402: 0100 addi s0,sp,128 + 1404: 0306 slli t1,t1,0x1 + 1406: 0900 addi s0,sp,144 + 1408: 0004 0x4 + 140a: 0301 addi t1,t1,0 + 140c: 0900 addi s0,sp,144 + 140e: 0000 unimp + 1410: 0601 addi a2,a2,0 + 1412: 04090103 lb sp,64(s2) + 1416: 0100 addi s0,sp,128 + 1418: 04097f03 0x4097f03 + 141c: 0100 addi s0,sp,128 + 141e: 0306 slli t1,t1,0x1 + 1420: 0900 addi s0,sp,144 + 1422: 0004 0x4 + 1424: 0301 addi t1,t1,0 + 1426: 0901 addi s2,s2,0 + 1428: 0000 unimp + 142a: 0301 addi t1,t1,0 + 142c: 0900 addi s0,sp,144 + 142e: 0000 unimp + 1430: 0301 addi t1,t1,0 + 1432: 0900 addi s0,sp,144 + 1434: 0000 unimp + 1436: 0301 addi t1,t1,0 + 1438: 0900 addi s0,sp,144 + 143a: 0000 unimp + 143c: 0301 addi t1,t1,0 + 143e: 0900 addi s0,sp,144 + 1440: 0000 unimp + 1442: 0301 addi t1,t1,0 + 1444: 0900 addi s0,sp,144 + 1446: 0000 unimp + 1448: 0301 addi t1,t1,0 + 144a: 0900 addi s0,sp,144 + 144c: 0004 0x4 + 144e: 0301 addi t1,t1,0 + 1450: 0901 addi s2,s2,0 + 1452: 0000 unimp + 1454: 0301 addi t1,t1,0 + 1456: 0900 addi s0,sp,144 + 1458: 0000 unimp + 145a: 0301 addi t1,t1,0 + 145c: 0900 addi s0,sp,144 + 145e: 0000 unimp + 1460: 0301 addi t1,t1,0 + 1462: 0900 addi s0,sp,144 + 1464: 0000 unimp + 1466: 0301 addi t1,t1,0 + 1468: 0900 addi s0,sp,144 + 146a: 0000 unimp + 146c: 0001 nop + 146e: 0402 c.slli64 s0 + 1470: 0614 addi a3,sp,768 + 1472: 04090003 lb zero,64(s2) + 1476: 0100 addi s0,sp,128 + 1478: 04090003 lb zero,64(s2) + 147c: 0100 addi s0,sp,128 + 147e: 0200 addi s0,sp,256 + 1480: 1704 addi s1,sp,928 + 1482: 08090003 lb zero,128(s2) + 1486: 0100 addi s0,sp,128 + 1488: 0200 addi s0,sp,256 + 148a: 1804 addi s1,sp,48 + 148c: 04090003 lb zero,64(s2) + 1490: 0100 addi s0,sp,128 + 1492: 0200 addi s0,sp,256 + 1494: 3e04 fld fs1,56(a2) + 1496: 0306 slli t1,t1,0x1 + 1498: 0900 addi s0,sp,144 + 149a: 0004 0x4 + 149c: 0001 nop + 149e: 0402 c.slli64 s0 + 14a0: 033e slli t1,t1,0xf + 14a2: 0900 addi s0,sp,144 + 14a4: 0000 unimp + 14a6: 0001 nop + 14a8: 0402 c.slli64 s0 + 14aa: 033e slli t1,t1,0xf + 14ac: 0900 addi s0,sp,144 + 14ae: 0000 unimp + 14b0: 0001 nop + 14b2: 0402 c.slli64 s0 + 14b4: 033e slli t1,t1,0xf + 14b6: 0900 addi s0,sp,144 + 14b8: 0000 unimp + 14ba: 0001 nop + 14bc: 0402 c.slli64 s0 + 14be: 033e slli t1,t1,0xf + 14c0: 0900 addi s0,sp,144 + 14c2: 0000 unimp + 14c4: 0001 nop + 14c6: 0402 c.slli64 s0 + 14c8: 033e slli t1,t1,0xf + 14ca: 0900 addi s0,sp,144 + 14cc: 0000 unimp + 14ce: 0001 nop + 14d0: 0402 c.slli64 s0 + 14d2: 033e slli t1,t1,0xf + 14d4: 0900 addi s0,sp,144 + 14d6: 0000 unimp + 14d8: 0001 nop + 14da: 0402 c.slli64 s0 + 14dc: 033e slli t1,t1,0xf + 14de: 0900 addi s0,sp,144 + 14e0: 0000 unimp + 14e2: 0001 nop + 14e4: 0402 c.slli64 s0 + 14e6: 033e slli t1,t1,0xf + 14e8: 0900 addi s0,sp,144 + 14ea: 0000 unimp + 14ec: 0001 nop + 14ee: 0402 c.slli64 s0 + 14f0: 033e slli t1,t1,0xf + 14f2: 0900 addi s0,sp,144 + 14f4: 0000 unimp + 14f6: 0001 nop + 14f8: 0402 c.slli64 s0 + 14fa: 033e slli t1,t1,0xf + 14fc: 0900 addi s0,sp,144 + 14fe: 0000 unimp + 1500: 0001 nop + 1502: 0402 c.slli64 s0 + 1504: 033e slli t1,t1,0xf + 1506: 0900 addi s0,sp,144 + 1508: 0000 unimp + 150a: 0001 nop + 150c: 0402 c.slli64 s0 + 150e: 0900033f 00010004 0x100040900033f + 1516: 0402 c.slli64 s0 + 1518: 0645 addi a2,a2,17 + 151a: 04090003 lb zero,64(s2) + 151e: 0100 addi s0,sp,128 + 1520: 0306 slli t1,t1,0x1 + 1522: 0900 addi s0,sp,144 + 1524: 0004 0x4 + 1526: 0301 addi t1,t1,0 + 1528: 0900 addi s0,sp,144 + 152a: 0004 0x4 + 152c: 0301 addi t1,t1,0 + 152e: 0900 addi s0,sp,144 + 1530: 0000 unimp + 1532: 0301 addi t1,t1,0 + 1534: 0900 addi s0,sp,144 + 1536: 0000 unimp + 1538: 0001 nop + 153a: 0402 c.slli64 s0 + 153c: 035f 0900 0004 0x40900035f + 1542: 0001 nop + 1544: 0402 c.slli64 s0 + 1546: 09000373 0x9000373 + 154a: 0004 0x4 + 154c: 0601 addi a2,a2,0 + 154e: 04090003 lb zero,64(s2) + 1552: 0100 addi s0,sp,128 + 1554: 0200 addi s0,sp,256 + 1556: 5004 lw s1,32(s0) + 1558: 0306 slli t1,t1,0x1 + 155a: 0900 addi s0,sp,144 + 155c: 0008 0x8 + 155e: 0001 nop + 1560: 0402 c.slli64 s0 + 1562: 0350 addi a2,sp,388 + 1564: 0900 addi s0,sp,144 + 1566: 0000 unimp + 1568: 0601 addi a2,a2,0 + 156a: 08090003 lb zero,128(s2) + 156e: 0100 addi s0,sp,128 + 1570: 0200 addi s0,sp,256 + 1572: 6604 flw fs1,8(a2) + 1574: 0306 slli t1,t1,0x1 + 1576: 0900 addi s0,sp,144 + 1578: 0008 0x8 + 157a: 0001 nop + 157c: 0402 c.slli64 s0 + 157e: 037a slli t1,t1,0x1e + 1580: 0900 addi s0,sp,144 + 1582: 0004 0x4 + 1584: 0501 addi a0,a0,0 + 1586: 0601 addi a2,a2,0 + 1588: 04090403 lb s0,64(s2) + 158c: 0100 addi s0,sp,128 + 158e: 0305 addi t1,t1,1 + 1590: 0200 addi s0,sp,256 + 1592: 6d04 flw fs1,24(a0) + 1594: 0306 slli t1,t1,0x1 + 1596: 097c addi a5,sp,156 + 1598: 0004 0x4 + 159a: 0001 nop + 159c: 0402 c.slli64 s0 + 159e: 0374 addi a3,sp,396 + 15a0: 0900 addi s0,sp,144 + 15a2: 0004 0x4 + 15a4: 0601 addi a2,a2,0 + 15a6: 04090003 lb zero,64(s2) + 15aa: 0100 addi s0,sp,128 + 15ac: 0306 slli t1,t1,0x1 + 15ae: 0900 addi s0,sp,144 + 15b0: 0004 0x4 + 15b2: 0301 addi t1,t1,0 + 15b4: 0901 addi s2,s2,0 + 15b6: 0000 unimp + 15b8: 0301 addi t1,t1,0 + 15ba: 0900 addi s0,sp,144 + 15bc: 0000 unimp + 15be: 0301 addi t1,t1,0 + 15c0: 0900 addi s0,sp,144 + 15c2: 0000 unimp + 15c4: 0301 addi t1,t1,0 + 15c6: 0902 c.slli64 s2 + 15c8: 0000 unimp + 15ca: 0501 addi a0,a0,0 + 15cc: 060a slli a2,a2,0x2 + 15ce: 00090003 lb zero,0(s2) + 15d2: 0100 addi s0,sp,128 + 15d4: 0305 addi t1,t1,1 + 15d6: 04097d03 0x4097d03 + 15da: 0100 addi s0,sp,128 + 15dc: 0306 slli t1,t1,0x1 + 15de: 0900 addi s0,sp,144 + 15e0: 0008 0x8 + 15e2: 0301 addi t1,t1,0 + 15e4: 0900 addi s0,sp,144 + 15e6: 000c 0xc + 15e8: 0901 addi s2,s2,0 + 15ea: 000c 0xc + 15ec: 0100 addi s0,sp,128 + 15ee: 8201 c.srli64 a2 + 15f0: 03000007 0x3000007 + 15f4: 9300 0x9300 + 15f6: 0000 unimp + 15f8: 0100 addi s0,sp,128 + 15fa: fb01 bnez a4,150a <_start-0x7fffeaf6> + 15fc: 0d0e slli s10,s10,0x3 + 15fe: 0100 addi s0,sp,128 + 1600: 0101 addi sp,sp,0 + 1602: 0001 nop + 1604: 0000 unimp + 1606: 0001 nop + 1608: 0100 addi s0,sp,128 + 160a: 2e2e fld ft8,200(sp) + 160c: 2f2e2e2f 0x2f2e2e2f + 1610: 2e2e fld ft8,200(sp) + 1612: 2f2e2e2f 0x2f2e2e2f + 1616: 6972 flw fs2,28(sp) + 1618: 2d766373 csrrsi t1,0x2d7,12 + 161c: 2f636367 0x2f636367 + 1620: 696c flw fa1,84(a0) + 1622: 6762 flw fa4,24(sp) + 1624: 732f6363 bltu t5,s2,1d4a <_start-0x7fffe2b6> + 1628: 2d74666f jal a2,480fe <_start-0x7ffb7f02> + 162c: 7066 flw ft0,120(sp) + 162e: 2e00 fld fs0,24(a2) + 1630: 2f2e fld ft10,200(sp) + 1632: 2e2e fld ft8,200(sp) + 1634: 2f2e2e2f 0x2f2e2e2f + 1638: 2e2e fld ft8,200(sp) + 163a: 7369722f 0x7369722f + 163e: 672d7663 bgeu s10,s2,1caa <_start-0x7fffe356> + 1642: 6c2f6363 bltu t5,sp,1d08 <_start-0x7fffe2f8> + 1646: 6269 lui tp,0x1a + 1648: 2f636367 0x2f636367 + 164c: 2e2e fld ft8,200(sp) + 164e: 636e692f 0x636e692f + 1652: 756c flw fa1,108(a0) + 1654: 6564 flw fs1,76(a0) + 1656: 0000 unimp + 1658: 756d lui a0,0xffffb + 165a: 736c flw fa1,100(a4) + 165c: 3366 fld ft6,120(sp) + 165e: 632e flw ft6,200(sp) + 1660: 0100 addi s0,sp,128 + 1662: 0000 unimp + 1664: 74666f73 csrrsi t5,0x746,12 + 1668: 662d lui a2,0xb + 166a: 2e70 fld fa2,216(a2) + 166c: 0068 addi a0,sp,12 + 166e: 0001 nop + 1670: 7300 flw fs0,32(a4) + 1672: 6e69 lui t3,0x1a + 1674: 2e656c67 0x2e656c67 + 1678: 0068 addi a0,sp,12 + 167a: 0001 nop + 167c: 6c00 flw fs0,24(s0) + 167e: 6c676e6f jal t3,77d44 <_start-0x7ff882bc> + 1682: 2e676e6f jal t3,77968 <_start-0x7ff88698> + 1686: 0068 addi a0,sp,12 + 1688: 0002 c.slli64 zero + 168a: 0000 unimp + 168c: 0105 addi sp,sp,1 + 168e: 0500 addi s0,sp,640 + 1690: f402 fsw ft0,40(sp) + 1692: 0016 c.slli zero,0x5 + 1694: 0380 addi s0,sp,448 + 1696: 03050123 sb a6,34(a0) # ffffb022 <__global_pointer$+0x7fff73ba> + 169a: 00090103 lb sp,0(s2) + 169e: 0100 addi s0,sp,128 + 16a0: 00090003 lb zero,0(s2) + 16a4: 0100 addi s0,sp,128 + 16a6: 0d05 addi s10,s10,1 + 16a8: 00090003 lb zero,0(s2) + 16ac: 0100 addi s0,sp,128 + 16ae: 0305 addi t1,t1,1 + 16b0: 00090103 lb sp,0(s2) + 16b4: 0100 addi s0,sp,128 + 16b6: 00090003 lb zero,0(s2) + 16ba: 0100 addi s0,sp,128 + 16bc: 00090003 lb zero,0(s2) + 16c0: 0100 addi s0,sp,128 + 16c2: 00090003 lb zero,0(s2) + 16c6: 0100 addi s0,sp,128 + 16c8: 00090103 lb sp,0(s2) + 16cc: 0100 addi s0,sp,128 + 16ce: 00090003 lb zero,0(s2) + 16d2: 0100 addi s0,sp,128 + 16d4: 00090003 lb zero,0(s2) + 16d8: 0100 addi s0,sp,128 + 16da: 00090003 lb zero,0(s2) + 16de: 0100 addi s0,sp,128 + 16e0: 00090103 lb sp,0(s2) + 16e4: 0100 addi s0,sp,128 + 16e6: 00090003 lb zero,0(s2) + 16ea: 0100 addi s0,sp,128 + 16ec: 00090003 lb zero,0(s2) + 16f0: 0100 addi s0,sp,128 + 16f2: 00090003 lb zero,0(s2) + 16f6: 0100 addi s0,sp,128 + 16f8: 00090103 lb sp,0(s2) + 16fc: 0100 addi s0,sp,128 + 16fe: 00090203 lb tp,0(s2) + 1702: 0100 addi s0,sp,128 + 1704: 00090103 lb sp,0(s2) + 1708: 0100 addi s0,sp,128 + 170a: 00090003 lb zero,0(s2) + 170e: 0100 addi s0,sp,128 + 1710: 00090003 lb zero,0(s2) + 1714: 0100 addi s0,sp,128 + 1716: 00090003 lb zero,0(s2) + 171a: 0100 addi s0,sp,128 + 171c: 00090003 lb zero,0(s2) + 1720: 0100 addi s0,sp,128 + 1722: 0105 addi sp,sp,1 + 1724: 0306 slli t1,t1,0x1 + 1726: 0978 addi a4,sp,156 + 1728: 0000 unimp + 172a: 0501 addi a0,a0,0 + 172c: 09080303 lb t1,144(a6) + 1730: 0018 0x18 + 1732: 0501 addi a0,a0,0 + 1734: 0301 addi t1,t1,0 + 1736: 0978 addi a4,sp,156 + 1738: 0004 0x4 + 173a: 0301 addi t1,t1,0 + 173c: 0900 addi s0,sp,144 + 173e: 0010 0x10 + 1740: 0501 addi a0,a0,0 + 1742: 09080303 lb t1,144(a6) + 1746: 0004 0x4 + 1748: 0601 addi a2,a2,0 + 174a: 04090003 lb zero,64(s2) + 174e: 0100 addi s0,sp,128 + 1750: 00090003 lb zero,0(s2) + 1754: 0100 addi s0,sp,128 + 1756: 04090003 lb zero,64(s2) + 175a: 0100 addi s0,sp,128 + 175c: 00090003 lb zero,0(s2) + 1760: 0100 addi s0,sp,128 + 1762: 00090003 lb zero,0(s2) + 1766: 0100 addi s0,sp,128 + 1768: 0200 addi s0,sp,256 + 176a: 0104 addi s1,sp,128 + 176c: 0c090003 lb zero,192(s2) + 1770: 0100 addi s0,sp,128 + 1772: 0200 addi s0,sp,256 + 1774: 0104 addi s1,sp,128 + 1776: 00090003 lb zero,0(s2) + 177a: 0100 addi s0,sp,128 + 177c: 0200 addi s0,sp,256 + 177e: 0104 addi s1,sp,128 + 1780: 00090003 lb zero,0(s2) + 1784: 0100 addi s0,sp,128 + 1786: 0200 addi s0,sp,256 + 1788: 0104 addi s1,sp,128 + 178a: 00090003 lb zero,0(s2) + 178e: 0100 addi s0,sp,128 + 1790: 0200 addi s0,sp,256 + 1792: 0104 addi s1,sp,128 + 1794: 0c090003 lb zero,192(s2) + 1798: 0100 addi s0,sp,128 + 179a: 0200 addi s0,sp,256 + 179c: 0104 addi s1,sp,128 + 179e: 00090003 lb zero,0(s2) + 17a2: 0100 addi s0,sp,128 + 17a4: 0200 addi s0,sp,256 + 17a6: 0104 addi s1,sp,128 + 17a8: 04090003 lb zero,64(s2) + 17ac: 0100 addi s0,sp,128 + 17ae: 0200 addi s0,sp,256 + 17b0: 0104 addi s1,sp,128 + 17b2: 00090003 lb zero,0(s2) + 17b6: 0100 addi s0,sp,128 + 17b8: 0200 addi s0,sp,256 + 17ba: 0f04 addi s1,sp,912 + 17bc: 00090003 lb zero,0(s2) + 17c0: 0100 addi s0,sp,128 + 17c2: 0200 addi s0,sp,256 + 17c4: 0f04 addi s1,sp,912 + 17c6: 00090003 lb zero,0(s2) + 17ca: 0100 addi s0,sp,128 + 17cc: 0200 addi s0,sp,256 + 17ce: 0804 addi s1,sp,16 + 17d0: 04090003 lb zero,64(s2) + 17d4: 0100 addi s0,sp,128 + 17d6: 0200 addi s0,sp,256 + 17d8: 0804 addi s1,sp,16 + 17da: 00090003 lb zero,0(s2) + 17de: 0100 addi s0,sp,128 + 17e0: 0200 addi s0,sp,256 + 17e2: 0804 addi s1,sp,16 + 17e4: 00090103 lb sp,0(s2) + 17e8: 0100 addi s0,sp,128 + 17ea: 0200 addi s0,sp,256 + 17ec: 0804 addi s1,sp,16 + 17ee: 00090003 lb zero,0(s2) + 17f2: 0100 addi s0,sp,128 + 17f4: 0200 addi s0,sp,256 + 17f6: 0804 addi s1,sp,16 + 17f8: 00090003 lb zero,0(s2) + 17fc: 0100 addi s0,sp,128 + 17fe: 0200 addi s0,sp,256 + 1800: 0804 addi s1,sp,16 + 1802: 00090003 lb zero,0(s2) + 1806: 0100 addi s0,sp,128 + 1808: 0200 addi s0,sp,256 + 180a: 0804 addi s1,sp,16 + 180c: 00090003 lb zero,0(s2) + 1810: 0100 addi s0,sp,128 + 1812: 0200 addi s0,sp,256 + 1814: 0804 addi s1,sp,16 + 1816: 10090003 lb zero,256(s2) + 181a: 0100 addi s0,sp,128 + 181c: 0200 addi s0,sp,256 + 181e: 0804 addi s1,sp,16 + 1820: 00090003 lb zero,0(s2) + 1824: 0100 addi s0,sp,128 + 1826: 0200 addi s0,sp,256 + 1828: 0804 addi s1,sp,16 + 182a: 04090003 lb zero,64(s2) + 182e: 0100 addi s0,sp,128 + 1830: 0200 addi s0,sp,256 + 1832: 0804 addi s1,sp,16 + 1834: 00090003 lb zero,0(s2) + 1838: 0100 addi s0,sp,128 + 183a: 0200 addi s0,sp,256 + 183c: 0804 addi s1,sp,16 + 183e: 00090003 lb zero,0(s2) + 1842: 0100 addi s0,sp,128 + 1844: 0306 slli t1,t1,0x1 + 1846: 0900 addi s0,sp,144 + 1848: 0004 0x4 + 184a: 0001 nop + 184c: 0402 c.slli64 s0 + 184e: 0601 addi a2,a2,0 + 1850: 08090003 lb zero,128(s2) + 1854: 0100 addi s0,sp,128 + 1856: 0200 addi s0,sp,256 + 1858: 0104 addi s1,sp,128 + 185a: 00090003 lb zero,0(s2) + 185e: 0100 addi s0,sp,128 + 1860: 0200 addi s0,sp,256 + 1862: 0104 addi s1,sp,128 + 1864: 00090003 lb zero,0(s2) + 1868: 0100 addi s0,sp,128 + 186a: 0200 addi s0,sp,256 + 186c: 0104 addi s1,sp,128 + 186e: 00090003 lb zero,0(s2) + 1872: 0100 addi s0,sp,128 + 1874: 0200 addi s0,sp,256 + 1876: 0104 addi s1,sp,128 + 1878: 0c090003 lb zero,192(s2) + 187c: 0100 addi s0,sp,128 + 187e: 0200 addi s0,sp,256 + 1880: 0104 addi s1,sp,128 + 1882: 00090003 lb zero,0(s2) + 1886: 0100 addi s0,sp,128 + 1888: 0200 addi s0,sp,256 + 188a: 0104 addi s1,sp,128 + 188c: 04090003 lb zero,64(s2) + 1890: 0100 addi s0,sp,128 + 1892: 0200 addi s0,sp,256 + 1894: 0104 addi s1,sp,128 + 1896: 00090003 lb zero,0(s2) + 189a: 0100 addi s0,sp,128 + 189c: 0200 addi s0,sp,256 + 189e: 0f04 addi s1,sp,912 + 18a0: 00090003 lb zero,0(s2) + 18a4: 0100 addi s0,sp,128 + 18a6: 0200 addi s0,sp,256 + 18a8: 0f04 addi s1,sp,912 + 18aa: 00090003 lb zero,0(s2) + 18ae: 0100 addi s0,sp,128 + 18b0: 0200 addi s0,sp,256 + 18b2: 0804 addi s1,sp,16 + 18b4: 04090003 lb zero,64(s2) + 18b8: 0100 addi s0,sp,128 + 18ba: 0200 addi s0,sp,256 + 18bc: 0804 addi s1,sp,16 + 18be: 00090003 lb zero,0(s2) + 18c2: 0100 addi s0,sp,128 + 18c4: 0200 addi s0,sp,256 + 18c6: 0804 addi s1,sp,16 + 18c8: 00090103 lb sp,0(s2) + 18cc: 0100 addi s0,sp,128 + 18ce: 0200 addi s0,sp,256 + 18d0: 0804 addi s1,sp,16 + 18d2: 00090003 lb zero,0(s2) + 18d6: 0100 addi s0,sp,128 + 18d8: 0200 addi s0,sp,256 + 18da: 0804 addi s1,sp,16 + 18dc: 18090003 lb zero,384(s2) + 18e0: 0100 addi s0,sp,128 + 18e2: 0200 addi s0,sp,256 + 18e4: 0804 addi s1,sp,16 + 18e6: 04090003 lb zero,64(s2) + 18ea: 0100 addi s0,sp,128 + 18ec: 0200 addi s0,sp,256 + 18ee: 0204 addi s1,sp,256 + 18f0: 1c097e03 0x1c097e03 + 18f4: 0100 addi s0,sp,128 + 18f6: 0200 addi s0,sp,256 + 18f8: 0f04 addi s1,sp,912 + 18fa: 04090003 lb zero,64(s2) + 18fe: 0100 addi s0,sp,128 + 1900: 0200 addi s0,sp,256 + 1902: 0f04 addi s1,sp,912 + 1904: 00090003 lb zero,0(s2) + 1908: 0100 addi s0,sp,128 + 190a: 0200 addi s0,sp,256 + 190c: 0f04 addi s1,sp,912 + 190e: 00090003 lb zero,0(s2) + 1912: 0100 addi s0,sp,128 + 1914: 0200 addi s0,sp,256 + 1916: 0f04 addi s1,sp,912 + 1918: 00090003 lb zero,0(s2) + 191c: 0100 addi s0,sp,128 + 191e: 0200 addi s0,sp,256 + 1920: 0f04 addi s1,sp,912 + 1922: 00090003 lb zero,0(s2) + 1926: 0100 addi s0,sp,128 + 1928: 0200 addi s0,sp,256 + 192a: 0f04 addi s1,sp,912 + 192c: 00090003 lb zero,0(s2) + 1930: 0100 addi s0,sp,128 + 1932: 0200 addi s0,sp,256 + 1934: 0f04 addi s1,sp,912 + 1936: 08090003 lb zero,128(s2) + 193a: 0100 addi s0,sp,128 + 193c: 0200 addi s0,sp,256 + 193e: 0f04 addi s1,sp,912 + 1940: 00090003 lb zero,0(s2) + 1944: 0100 addi s0,sp,128 + 1946: 0200 addi s0,sp,256 + 1948: 0f04 addi s1,sp,912 + 194a: 00090003 lb zero,0(s2) + 194e: 0100 addi s0,sp,128 + 1950: 0200 addi s0,sp,256 + 1952: 0f04 addi s1,sp,912 + 1954: 00090003 lb zero,0(s2) + 1958: 0100 addi s0,sp,128 + 195a: 0200 addi s0,sp,256 + 195c: 0f04 addi s1,sp,912 + 195e: 00090003 lb zero,0(s2) + 1962: 0100 addi s0,sp,128 + 1964: 0200 addi s0,sp,256 + 1966: 0f04 addi s1,sp,912 + 1968: 0c090003 lb zero,192(s2) + 196c: 0100 addi s0,sp,128 + 196e: 0200 addi s0,sp,256 + 1970: 0f04 addi s1,sp,912 + 1972: 00090003 lb zero,0(s2) + 1976: 0100 addi s0,sp,128 + 1978: 0200 addi s0,sp,256 + 197a: 0304 addi s1,sp,384 + 197c: 08090003 lb zero,128(s2) + 1980: 0100 addi s0,sp,128 + 1982: 0306 slli t1,t1,0x1 + 1984: 0900 addi s0,sp,144 + 1986: 000c 0xc + 1988: 0001 nop + 198a: 0402 c.slli64 s0 + 198c: 0602 c.slli64 a2 + 198e: 14090103 lb sp,320(s2) + 1992: 0100 addi s0,sp,128 + 1994: 0200 addi s0,sp,256 + 1996: 0f04 addi s1,sp,912 + 1998: 04090003 lb zero,64(s2) + 199c: 0100 addi s0,sp,128 + 199e: 0200 addi s0,sp,256 + 19a0: 0f04 addi s1,sp,912 + 19a2: 00090003 lb zero,0(s2) + 19a6: 0100 addi s0,sp,128 + 19a8: 0200 addi s0,sp,256 + 19aa: 0f04 addi s1,sp,912 + 19ac: 00090003 lb zero,0(s2) + 19b0: 0100 addi s0,sp,128 + 19b2: 0200 addi s0,sp,256 + 19b4: 0f04 addi s1,sp,912 + 19b6: 00090003 lb zero,0(s2) + 19ba: 0100 addi s0,sp,128 + 19bc: 0200 addi s0,sp,256 + 19be: 0f04 addi s1,sp,912 + 19c0: 00090003 lb zero,0(s2) + 19c4: 0100 addi s0,sp,128 + 19c6: 0200 addi s0,sp,256 + 19c8: 0f04 addi s1,sp,912 + 19ca: 00090003 lb zero,0(s2) + 19ce: 0100 addi s0,sp,128 + 19d0: 0200 addi s0,sp,256 + 19d2: 0f04 addi s1,sp,912 + 19d4: 08090003 lb zero,128(s2) + 19d8: 0100 addi s0,sp,128 + 19da: 0200 addi s0,sp,256 + 19dc: 0f04 addi s1,sp,912 + 19de: 00090003 lb zero,0(s2) + 19e2: 0100 addi s0,sp,128 + 19e4: 0200 addi s0,sp,256 + 19e6: 0f04 addi s1,sp,912 + 19e8: 00090003 lb zero,0(s2) + 19ec: 0100 addi s0,sp,128 + 19ee: 0200 addi s0,sp,256 + 19f0: 0f04 addi s1,sp,912 + 19f2: 00090003 lb zero,0(s2) + 19f6: 0100 addi s0,sp,128 + 19f8: 0200 addi s0,sp,256 + 19fa: 0f04 addi s1,sp,912 + 19fc: 00090003 lb zero,0(s2) + 1a00: 0100 addi s0,sp,128 + 1a02: 0200 addi s0,sp,256 + 1a04: 0f04 addi s1,sp,912 + 1a06: 08090003 lb zero,128(s2) + 1a0a: 0100 addi s0,sp,128 + 1a0c: 0200 addi s0,sp,256 + 1a0e: 0f04 addi s1,sp,912 + 1a10: 00090003 lb zero,0(s2) + 1a14: 0100 addi s0,sp,128 + 1a16: 0200 addi s0,sp,256 + 1a18: 0304 addi s1,sp,384 + 1a1a: 0c090003 lb zero,192(s2) + 1a1e: 0100 addi s0,sp,128 + 1a20: 0306 slli t1,t1,0x1 + 1a22: 0900 addi s0,sp,144 + 1a24: 000c 0xc + 1a26: 0001 nop + 1a28: 0402 c.slli64 s0 + 1a2a: 0602 c.slli64 a2 + 1a2c: 14090103 lb sp,320(s2) + 1a30: 0100 addi s0,sp,128 + 1a32: 0200 addi s0,sp,256 + 1a34: 0204 addi s1,sp,256 + 1a36: 00090003 lb zero,0(s2) + 1a3a: 0100 addi s0,sp,128 + 1a3c: 0200 addi s0,sp,256 + 1a3e: 0204 addi s1,sp,256 + 1a40: 00090003 lb zero,0(s2) + 1a44: 0100 addi s0,sp,128 + 1a46: 0200 addi s0,sp,256 + 1a48: 0204 addi s1,sp,256 + 1a4a: 00090003 lb zero,0(s2) + 1a4e: 0100 addi s0,sp,128 + 1a50: 0200 addi s0,sp,256 + 1a52: 0204 addi s1,sp,256 + 1a54: 00090003 lb zero,0(s2) + 1a58: 0100 addi s0,sp,128 + 1a5a: 0200 addi s0,sp,256 + 1a5c: 0204 addi s1,sp,256 + 1a5e: 00090003 lb zero,0(s2) + 1a62: 0100 addi s0,sp,128 + 1a64: 0200 addi s0,sp,256 + 1a66: 0204 addi s1,sp,256 + 1a68: 00090003 lb zero,0(s2) + 1a6c: 0100 addi s0,sp,128 + 1a6e: 0200 addi s0,sp,256 + 1a70: 0204 addi s1,sp,256 + 1a72: 00090003 lb zero,0(s2) + 1a76: 0100 addi s0,sp,128 + 1a78: 0200 addi s0,sp,256 + 1a7a: 0204 addi s1,sp,256 + 1a7c: 00090003 lb zero,0(s2) + 1a80: 0100 addi s0,sp,128 + 1a82: 0200 addi s0,sp,256 + 1a84: 0204 addi s1,sp,256 + 1a86: 0c090003 lb zero,192(s2) + 1a8a: 0100 addi s0,sp,128 + 1a8c: 0200 addi s0,sp,256 + 1a8e: 0204 addi s1,sp,256 + 1a90: 00090003 lb zero,0(s2) + 1a94: 0100 addi s0,sp,128 + 1a96: 0200 addi s0,sp,256 + 1a98: 0204 addi s1,sp,256 + 1a9a: 04090003 lb zero,64(s2) + 1a9e: 0100 addi s0,sp,128 + 1aa0: 0200 addi s0,sp,256 + 1aa2: 0204 addi s1,sp,256 + 1aa4: 0c090003 lb zero,192(s2) + 1aa8: 0100 addi s0,sp,128 + 1aaa: 0200 addi s0,sp,256 + 1aac: 0204 addi s1,sp,256 + 1aae: 00090003 lb zero,0(s2) + 1ab2: 0100 addi s0,sp,128 + 1ab4: 0200 addi s0,sp,256 + 1ab6: 0204 addi s1,sp,256 + 1ab8: 04090003 lb zero,64(s2) + 1abc: 0100 addi s0,sp,128 + 1abe: 0200 addi s0,sp,256 + 1ac0: 0204 addi s1,sp,256 + 1ac2: 04090003 lb zero,64(s2) + 1ac6: 0100 addi s0,sp,128 + 1ac8: 0200 addi s0,sp,256 + 1aca: 0204 addi s1,sp,256 + 1acc: 0c090003 lb zero,192(s2) + 1ad0: 0100 addi s0,sp,128 + 1ad2: 0200 addi s0,sp,256 + 1ad4: 0204 addi s1,sp,256 + 1ad6: 04090003 lb zero,64(s2) + 1ada: 0100 addi s0,sp,128 + 1adc: 0200 addi s0,sp,256 + 1ade: 0904 addi s1,sp,144 + 1ae0: 04090003 lb zero,64(s2) + 1ae4: 0100 addi s0,sp,128 + 1ae6: 0200 addi s0,sp,256 + 1ae8: 0b04 addi s1,sp,400 + 1aea: 04090003 lb zero,64(s2) + 1aee: 0100 addi s0,sp,128 + 1af0: 0200 addi s0,sp,256 + 1af2: 0b04 addi s1,sp,400 + 1af4: 00090003 lb zero,0(s2) + 1af8: 0100 addi s0,sp,128 + 1afa: 0200 addi s0,sp,256 + 1afc: 0b04 addi s1,sp,400 + 1afe: 10090003 lb zero,256(s2) + 1b02: 0100 addi s0,sp,128 + 1b04: 0200 addi s0,sp,256 + 1b06: 0b04 addi s1,sp,400 + 1b08: 00090003 lb zero,0(s2) + 1b0c: 0100 addi s0,sp,128 + 1b0e: 0200 addi s0,sp,256 + 1b10: 0b04 addi s1,sp,400 + 1b12: 00090003 lb zero,0(s2) + 1b16: 0100 addi s0,sp,128 + 1b18: 0200 addi s0,sp,256 + 1b1a: 0b04 addi s1,sp,400 + 1b1c: 00090003 lb zero,0(s2) + 1b20: 0100 addi s0,sp,128 + 1b22: 0200 addi s0,sp,256 + 1b24: 0b04 addi s1,sp,400 + 1b26: 20090003 lb zero,512(s2) + 1b2a: 0100 addi s0,sp,128 + 1b2c: 0200 addi s0,sp,256 + 1b2e: 0b04 addi s1,sp,400 + 1b30: 00090003 lb zero,0(s2) + 1b34: 0100 addi s0,sp,128 + 1b36: 0200 addi s0,sp,256 + 1b38: 0b04 addi s1,sp,400 + 1b3a: 00090003 lb zero,0(s2) + 1b3e: 0100 addi s0,sp,128 + 1b40: 0200 addi s0,sp,256 + 1b42: 0b04 addi s1,sp,400 + 1b44: 00090003 lb zero,0(s2) + 1b48: 0100 addi s0,sp,128 + 1b4a: 0200 addi s0,sp,256 + 1b4c: 0c04 addi s1,sp,528 + 1b4e: 08090003 lb zero,128(s2) + 1b52: 0100 addi s0,sp,128 + 1b54: 0200 addi s0,sp,256 + 1b56: 0204 addi s1,sp,256 + 1b58: 0c090103 lb sp,192(s2) + 1b5c: 0100 addi s0,sp,128 + 1b5e: 0200 addi s0,sp,256 + 1b60: 0204 addi s1,sp,256 + 1b62: 04090003 lb zero,64(s2) + 1b66: 0100 addi s0,sp,128 + 1b68: 0200 addi s0,sp,256 + 1b6a: 0604 addi s1,sp,768 + 1b6c: 04090003 lb zero,64(s2) + 1b70: 0100 addi s0,sp,128 + 1b72: 0200 addi s0,sp,256 + 1b74: 0604 addi s1,sp,768 + 1b76: 00090003 lb zero,0(s2) + 1b7a: 0100 addi s0,sp,128 + 1b7c: 0200 addi s0,sp,256 + 1b7e: 0804 addi s1,sp,16 + 1b80: 08090003 lb zero,128(s2) + 1b84: 0100 addi s0,sp,128 + 1b86: 0200 addi s0,sp,256 + 1b88: 0804 addi s1,sp,16 + 1b8a: 00090003 lb zero,0(s2) + 1b8e: 0100 addi s0,sp,128 + 1b90: 0200 addi s0,sp,256 + 1b92: 0804 addi s1,sp,16 + 1b94: 00090003 lb zero,0(s2) + 1b98: 0100 addi s0,sp,128 + 1b9a: 0200 addi s0,sp,256 + 1b9c: 0804 addi s1,sp,16 + 1b9e: 00090003 lb zero,0(s2) + 1ba2: 0100 addi s0,sp,128 + 1ba4: 0200 addi s0,sp,256 + 1ba6: 0a04 addi s1,sp,272 + 1ba8: 0c090003 lb zero,192(s2) + 1bac: 0100 addi s0,sp,128 + 1bae: 0200 addi s0,sp,256 + 1bb0: 0904 addi s1,sp,144 + 1bb2: 04090003 lb zero,64(s2) + 1bb6: 0100 addi s0,sp,128 + 1bb8: 0200 addi s0,sp,256 + 1bba: 0904 addi s1,sp,144 + 1bbc: 00090003 lb zero,0(s2) + 1bc0: 0100 addi s0,sp,128 + 1bc2: 0200 addi s0,sp,256 + 1bc4: 1804 addi s1,sp,48 + 1bc6: 08090003 lb zero,128(s2) + 1bca: 0100 addi s0,sp,128 + 1bcc: 0200 addi s0,sp,256 + 1bce: 1804 addi s1,sp,48 + 1bd0: 0c090003 lb zero,192(s2) + 1bd4: 0100 addi s0,sp,128 + 1bd6: 0200 addi s0,sp,256 + 1bd8: 1a04 addi s1,sp,304 + 1bda: 04090003 lb zero,64(s2) + 1bde: 0100 addi s0,sp,128 + 1be0: 0200 addi s0,sp,256 + 1be2: 1a04 addi s1,sp,304 + 1be4: 00090003 lb zero,0(s2) + 1be8: 0100 addi s0,sp,128 + 1bea: 0200 addi s0,sp,256 + 1bec: 0704 addi s1,sp,896 + 1bee: 0306 slli t1,t1,0x1 + 1bf0: 097d addi s2,s2,31 + 1bf2: 0018 0x18 + 1bf4: 0001 nop + 1bf6: 0402 c.slli64 s0 + 1bf8: 02030607 0x2030607 + 1bfc: 0409 addi s0,s0,2 + 1bfe: 0100 addi s0,sp,128 + 1c00: 0200 addi s0,sp,256 + 1c02: 1504 addi s1,sp,672 + 1c04: 08090003 lb zero,128(s2) + 1c08: 0100 addi s0,sp,128 + 1c0a: 0200 addi s0,sp,256 + 1c0c: 1504 addi s1,sp,672 + 1c0e: 00090103 lb sp,0(s2) + 1c12: 0100 addi s0,sp,128 + 1c14: 0200 addi s0,sp,256 + 1c16: 1504 addi s1,sp,672 + 1c18: 00090003 lb zero,0(s2) + 1c1c: 0100 addi s0,sp,128 + 1c1e: 0200 addi s0,sp,256 + 1c20: 1504 addi s1,sp,672 + 1c22: 00090003 lb zero,0(s2) + 1c26: 0100 addi s0,sp,128 + 1c28: 0306 slli t1,t1,0x1 + 1c2a: 0900 addi s0,sp,144 + 1c2c: 0008 0x8 + 1c2e: 0001 nop + 1c30: 0402 c.slli64 s0 + 1c32: 0304 addi s1,sp,384 + 1c34: 097e slli s2,s2,0x1f + 1c36: 001c 0x1c + 1c38: 0001 nop + 1c3a: 0402 c.slli64 s0 + 1c3c: 0604 addi s1,sp,768 + 1c3e: 04090103 lb sp,64(s2) + 1c42: 0100 addi s0,sp,128 + 1c44: 0306 slli t1,t1,0x1 + 1c46: 0900 addi s0,sp,144 + 1c48: 0004 0x4 + 1c4a: 0001 nop + 1c4c: 0402 c.slli64 s0 + 1c4e: 0103063b 0x103063b + 1c52: 0809 addi a6,a6,2 + 1c54: 0100 addi s0,sp,128 + 1c56: 0200 addi s0,sp,256 + 1c58: 3b04 fld fs1,48(a4) + 1c5a: 00090003 lb zero,0(s2) + 1c5e: 0100 addi s0,sp,128 + 1c60: 0200 addi s0,sp,256 + 1c62: 3b04 fld fs1,48(a4) + 1c64: 00090003 lb zero,0(s2) + 1c68: 0100 addi s0,sp,128 + 1c6a: 0200 addi s0,sp,256 + 1c6c: 3b04 fld fs1,48(a4) + 1c6e: 08090003 lb zero,128(s2) + 1c72: 0100 addi s0,sp,128 + 1c74: 0200 addi s0,sp,256 + 1c76: 3c04 fld fs1,56(s0) + 1c78: 08090003 lb zero,128(s2) + 1c7c: 0100 addi s0,sp,128 + 1c7e: 0200 addi s0,sp,256 + 1c80: 3c04 fld fs1,56(s0) + 1c82: 14090003 lb zero,320(s2) + 1c86: 0100 addi s0,sp,128 + 1c88: 0200 addi s0,sp,256 + 1c8a: 3c04 fld fs1,56(s0) + 1c8c: 00090003 lb zero,0(s2) + 1c90: 0100 addi s0,sp,128 + 1c92: 0200 addi s0,sp,256 + 1c94: 4404 lw s1,8(s0) + 1c96: 08090003 lb zero,128(s2) + 1c9a: 0100 addi s0,sp,128 + 1c9c: 0200 addi s0,sp,256 + 1c9e: 4404 lw s1,8(s0) + 1ca0: 00090003 lb zero,0(s2) + 1ca4: 0100 addi s0,sp,128 + 1ca6: 0200 addi s0,sp,256 + 1ca8: 4404 lw s1,8(s0) + 1caa: 00090003 lb zero,0(s2) + 1cae: 0100 addi s0,sp,128 + 1cb0: 0200 addi s0,sp,256 + 1cb2: 4404 lw s1,8(s0) + 1cb4: 00090003 lb zero,0(s2) + 1cb8: 0100 addi s0,sp,128 + 1cba: 0200 addi s0,sp,256 + 1cbc: 4604 lw s1,8(a2) + 1cbe: 0c090003 lb zero,192(s2) + 1cc2: 0100 addi s0,sp,128 + 1cc4: 0200 addi s0,sp,256 + 1cc6: 4504 lw s1,8(a0) + 1cc8: 04090003 lb zero,64(s2) + 1ccc: 0100 addi s0,sp,128 + 1cce: 0200 addi s0,sp,256 + 1cd0: 4504 lw s1,8(a0) + 1cd2: 00090003 lb zero,0(s2) + 1cd6: 0100 addi s0,sp,128 + 1cd8: 0306 slli t1,t1,0x1 + 1cda: 0900 addi s0,sp,144 + 1cdc: 000c 0xc + 1cde: 0001 nop + 1ce0: 0402 c.slli64 s0 + 1ce2: 0003066f jal a2,31ce2 <_start-0x7ffce31e> + 1ce6: 1809 addi a6,a6,-30 + 1ce8: 0100 addi s0,sp,128 + 1cea: 0200 addi s0,sp,256 + 1cec: 6f04 flw fs1,24(a4) + 1cee: 00090003 lb zero,0(s2) + 1cf2: 0100 addi s0,sp,128 + 1cf4: 0200 addi s0,sp,256 + 1cf6: 6f04 flw fs1,24(a4) + 1cf8: 00090003 lb zero,0(s2) + 1cfc: 0100 addi s0,sp,128 + 1cfe: 0200 addi s0,sp,256 + 1d00: 6f04 flw fs1,24(a4) + 1d02: 00090003 lb zero,0(s2) + 1d06: 0100 addi s0,sp,128 + 1d08: 0200 addi s0,sp,256 + 1d0a: 6f04 flw fs1,24(a4) + 1d0c: 00090003 lb zero,0(s2) + 1d10: 0100 addi s0,sp,128 + 1d12: 0200 addi s0,sp,256 + 1d14: 6f04 flw fs1,24(a4) + 1d16: 00090003 lb zero,0(s2) + 1d1a: 0100 addi s0,sp,128 + 1d1c: 0200 addi s0,sp,256 + 1d1e: 6f04 flw fs1,24(a4) + 1d20: 1c090003 lb zero,448(s2) + 1d24: 0100 addi s0,sp,128 + 1d26: 0200 addi s0,sp,256 + 1d28: 6f04 flw fs1,24(a4) + 1d2a: 00090003 lb zero,0(s2) + 1d2e: 0100 addi s0,sp,128 + 1d30: 0200 addi s0,sp,256 + 1d32: 6f04 flw fs1,24(a4) + 1d34: 00090003 lb zero,0(s2) + 1d38: 0100 addi s0,sp,128 + 1d3a: 0200 addi s0,sp,256 + 1d3c: 6f04 flw fs1,24(a4) + 1d3e: 00090103 lb sp,0(s2) + 1d42: 0100 addi s0,sp,128 + 1d44: 0200 addi s0,sp,256 + 1d46: 6f04 flw fs1,24(a4) + 1d48: 00090003 lb zero,0(s2) + 1d4c: 0100 addi s0,sp,128 + 1d4e: 0200 addi s0,sp,256 + 1d50: 6f04 flw fs1,24(a4) + 1d52: 00090003 lb zero,0(s2) + 1d56: 0100 addi s0,sp,128 + 1d58: 0200 addi s0,sp,256 + 1d5a: 6f04 flw fs1,24(a4) + 1d5c: 00090203 lb tp,0(s2) + 1d60: 0100 addi s0,sp,128 + 1d62: 0105 addi sp,sp,1 + 1d64: 0200 addi s0,sp,256 + 1d66: 6f04 flw fs1,24(a4) + 1d68: 0306 slli t1,t1,0x1 + 1d6a: 0901 addi s2,s2,0 + 1d6c: 0000 unimp + 1d6e: 0901 addi s2,s2,0 + 1d70: 0028 addi a0,sp,8 + 1d72: 0100 addi s0,sp,128 + 1d74: aa01 j 1e84 <_start-0x7fffe17c> + 1d76: 000a c.slli zero,0x2 + 1d78: 0300 addi s0,sp,384 + 1d7a: 9300 0x9300 + 1d7c: 0000 unimp + 1d7e: 0100 addi s0,sp,128 + 1d80: fb01 bnez a4,1c90 <_start-0x7fffe370> + 1d82: 0d0e slli s10,s10,0x3 + 1d84: 0100 addi s0,sp,128 + 1d86: 0101 addi sp,sp,0 + 1d88: 0001 nop + 1d8a: 0000 unimp + 1d8c: 0001 nop + 1d8e: 0100 addi s0,sp,128 + 1d90: 2e2e fld ft8,200(sp) + 1d92: 2f2e2e2f 0x2f2e2e2f + 1d96: 2e2e fld ft8,200(sp) + 1d98: 2f2e2e2f 0x2f2e2e2f + 1d9c: 6972 flw fs2,28(sp) + 1d9e: 2d766373 csrrsi t1,0x2d7,12 + 1da2: 2f636367 0x2f636367 + 1da6: 696c flw fa1,84(a0) + 1da8: 6762 flw fa4,24(sp) + 1daa: 732f6363 bltu t5,s2,24d0 <_start-0x7fffdb30> + 1dae: 2d74666f jal a2,48884 <_start-0x7ffb777c> + 1db2: 7066 flw ft0,120(sp) + 1db4: 2e00 fld fs0,24(a2) + 1db6: 2f2e fld ft10,200(sp) + 1db8: 2e2e fld ft8,200(sp) + 1dba: 2f2e2e2f 0x2f2e2e2f + 1dbe: 2e2e fld ft8,200(sp) + 1dc0: 7369722f 0x7369722f + 1dc4: 672d7663 bgeu s10,s2,2430 <_start-0x7fffdbd0> + 1dc8: 6c2f6363 bltu t5,sp,248e <_start-0x7fffdb72> + 1dcc: 6269 lui tp,0x1a + 1dce: 2f636367 0x2f636367 + 1dd2: 2e2e fld ft8,200(sp) + 1dd4: 636e692f 0x636e692f + 1dd8: 756c flw fa1,108(a0) + 1dda: 6564 flw fs1,76(a0) + 1ddc: 0000 unimp + 1dde: 73627573 csrrci a0,0x736,4 + 1de2: 3366 fld ft6,120(sp) + 1de4: 632e flw ft6,200(sp) + 1de6: 0100 addi s0,sp,128 + 1de8: 0000 unimp + 1dea: 74666f73 csrrsi t5,0x746,12 + 1dee: 662d lui a2,0xb + 1df0: 2e70 fld fa2,216(a2) + 1df2: 0068 addi a0,sp,12 + 1df4: 0001 nop + 1df6: 7300 flw fs0,32(a4) + 1df8: 6e69 lui t3,0x1a + 1dfa: 2e656c67 0x2e656c67 + 1dfe: 0068 addi a0,sp,12 + 1e00: 0001 nop + 1e02: 6c00 flw fs0,24(s0) + 1e04: 6c676e6f jal t3,784ca <_start-0x7ff87b36> + 1e08: 2e676e6f jal t3,780ee <_start-0x7ff87f12> + 1e0c: 0068 addi a0,sp,12 + 1e0e: 0002 c.slli64 zero + 1e10: 0000 unimp + 1e12: 0105 addi sp,sp,1 + 1e14: 0500 addi s0,sp,640 + 1e16: ec02 fsw ft0,24(sp) + 1e18: 0019 c.nop 6 + 1e1a: 0380 addi s0,sp,448 + 1e1c: 03050123 sb a6,34(a0) + 1e20: 00090103 lb sp,0(s2) + 1e24: 0100 addi s0,sp,128 + 1e26: 00090003 lb zero,0(s2) + 1e2a: 0100 addi s0,sp,128 + 1e2c: 0d05 addi s10,s10,1 + 1e2e: 00090003 lb zero,0(s2) + 1e32: 0100 addi s0,sp,128 + 1e34: 0305 addi t1,t1,1 + 1e36: 00090103 lb sp,0(s2) + 1e3a: 0100 addi s0,sp,128 + 1e3c: 00090003 lb zero,0(s2) + 1e40: 0100 addi s0,sp,128 + 1e42: 00090003 lb zero,0(s2) + 1e46: 0100 addi s0,sp,128 + 1e48: 00090003 lb zero,0(s2) + 1e4c: 0100 addi s0,sp,128 + 1e4e: 00090103 lb sp,0(s2) + 1e52: 0100 addi s0,sp,128 + 1e54: 00090003 lb zero,0(s2) + 1e58: 0100 addi s0,sp,128 + 1e5a: 00090003 lb zero,0(s2) + 1e5e: 0100 addi s0,sp,128 + 1e60: 00090003 lb zero,0(s2) + 1e64: 0100 addi s0,sp,128 + 1e66: 00090103 lb sp,0(s2) + 1e6a: 0100 addi s0,sp,128 + 1e6c: 00090003 lb zero,0(s2) + 1e70: 0100 addi s0,sp,128 + 1e72: 00090003 lb zero,0(s2) + 1e76: 0100 addi s0,sp,128 + 1e78: 00090003 lb zero,0(s2) + 1e7c: 0100 addi s0,sp,128 + 1e7e: 00090103 lb sp,0(s2) + 1e82: 0100 addi s0,sp,128 + 1e84: 00090203 lb tp,0(s2) + 1e88: 0100 addi s0,sp,128 + 1e8a: 00090103 lb sp,0(s2) + 1e8e: 0100 addi s0,sp,128 + 1e90: 00090003 lb zero,0(s2) + 1e94: 0100 addi s0,sp,128 + 1e96: 00090003 lb zero,0(s2) + 1e9a: 0100 addi s0,sp,128 + 1e9c: 00090003 lb zero,0(s2) + 1ea0: 0100 addi s0,sp,128 + 1ea2: 00090003 lb zero,0(s2) + 1ea6: 0100 addi s0,sp,128 + 1ea8: 0105 addi sp,sp,1 + 1eaa: 0306 slli t1,t1,0x1 + 1eac: 0978 addi a4,sp,156 + 1eae: 0004 0x4 + 1eb0: 0501 addi a0,a0,0 + 1eb2: 09080303 lb t1,144(a6) + 1eb6: 0004 0x4 + 1eb8: 0601 addi a2,a2,0 + 1eba: 10090003 lb zero,256(s2) + 1ebe: 0100 addi s0,sp,128 + 1ec0: 0105 addi sp,sp,1 + 1ec2: 0306 slli t1,t1,0x1 + 1ec4: 0978 addi a4,sp,156 + 1ec6: 0000 unimp + 1ec8: 0501 addi a0,a0,0 + 1eca: 09090303 lb t1,144(s2) + 1ece: 0004 0x4 + 1ed0: 0501 addi a0,a0,0 + 1ed2: 0301 addi t1,t1,0 + 1ed4: 00040977 0x40977 + 1ed8: 0501 addi a0,a0,0 + 1eda: 09080303 lb t1,144(a6) + 1ede: 0008 0x8 + 1ee0: 0501 addi a0,a0,0 + 1ee2: 0301 addi t1,t1,0 + 1ee4: 0978 addi a4,sp,156 + 1ee6: 0008 0x8 + 1ee8: 0501 addi a0,a0,0 + 1eea: 090a0303 lb t1,144(s4) + 1eee: 0008 0x8 + 1ef0: 0301 addi t1,t1,0 + 1ef2: 097e slli s2,s2,0x1f + 1ef4: 0004 0x4 + 1ef6: 0601 addi a2,a2,0 + 1ef8: 04090003 lb zero,64(s2) + 1efc: 0100 addi s0,sp,128 + 1efe: 00090003 lb zero,0(s2) + 1f02: 0100 addi s0,sp,128 + 1f04: 00090003 lb zero,0(s2) + 1f08: 0100 addi s0,sp,128 + 1f0a: 00090003 lb zero,0(s2) + 1f0e: 0100 addi s0,sp,128 + 1f10: 00090003 lb zero,0(s2) + 1f14: 0100 addi s0,sp,128 + 1f16: 04090003 lb zero,64(s2) + 1f1a: 0100 addi s0,sp,128 + 1f1c: 00090003 lb zero,0(s2) + 1f20: 0100 addi s0,sp,128 + 1f22: 00090103 lb sp,0(s2) + 1f26: 0100 addi s0,sp,128 + 1f28: 00090003 lb zero,0(s2) + 1f2c: 0100 addi s0,sp,128 + 1f2e: 00090003 lb zero,0(s2) + 1f32: 0100 addi s0,sp,128 + 1f34: 00090003 lb zero,0(s2) + 1f38: 0100 addi s0,sp,128 + 1f3a: 00090003 lb zero,0(s2) + 1f3e: 0100 addi s0,sp,128 + 1f40: 00090003 lb zero,0(s2) + 1f44: 0100 addi s0,sp,128 + 1f46: 04090003 lb zero,64(s2) + 1f4a: 0100 addi s0,sp,128 + 1f4c: 04090003 lb zero,64(s2) + 1f50: 0100 addi s0,sp,128 + 1f52: 00090003 lb zero,0(s2) + 1f56: 0100 addi s0,sp,128 + 1f58: 00090003 lb zero,0(s2) + 1f5c: 0100 addi s0,sp,128 + 1f5e: 00090003 lb zero,0(s2) + 1f62: 0100 addi s0,sp,128 + 1f64: 04090003 lb zero,64(s2) + 1f68: 0100 addi s0,sp,128 + 1f6a: 00090003 lb zero,0(s2) + 1f6e: 0100 addi s0,sp,128 + 1f70: 00090103 lb sp,0(s2) + 1f74: 0100 addi s0,sp,128 + 1f76: 00090003 lb zero,0(s2) + 1f7a: 0100 addi s0,sp,128 + 1f7c: 0200 addi s0,sp,256 + 1f7e: 0204 addi s1,sp,256 + 1f80: 0306 slli t1,t1,0x1 + 1f82: 0900 addi s0,sp,144 + 1f84: 0004 0x4 + 1f86: 0001 nop + 1f88: 0402 c.slli64 s0 + 1f8a: 00030603 lb a2,0(t1) # ffff9000 <__global_pointer$+0x7fff5398> + 1f8e: 0409 addi s0,s0,2 + 1f90: 0100 addi s0,sp,128 + 1f92: 0200 addi s0,sp,256 + 1f94: 0b04 addi s1,sp,400 + 1f96: 04090003 lb zero,64(s2) + 1f9a: 0100 addi s0,sp,128 + 1f9c: 0200 addi s0,sp,256 + 1f9e: 0b04 addi s1,sp,400 + 1fa0: 00090003 lb zero,0(s2) + 1fa4: 0100 addi s0,sp,128 + 1fa6: 0200 addi s0,sp,256 + 1fa8: 0b04 addi s1,sp,400 + 1faa: 00090003 lb zero,0(s2) + 1fae: 0100 addi s0,sp,128 + 1fb0: 0200 addi s0,sp,256 + 1fb2: 0b04 addi s1,sp,400 + 1fb4: 00090003 lb zero,0(s2) + 1fb8: 0100 addi s0,sp,128 + 1fba: 0200 addi s0,sp,256 + 1fbc: 0b04 addi s1,sp,400 + 1fbe: 00090003 lb zero,0(s2) + 1fc2: 0100 addi s0,sp,128 + 1fc4: 0200 addi s0,sp,256 + 1fc6: 0b04 addi s1,sp,400 + 1fc8: 00090003 lb zero,0(s2) + 1fcc: 0100 addi s0,sp,128 + 1fce: 0200 addi s0,sp,256 + 1fd0: 0b04 addi s1,sp,400 + 1fd2: 00090003 lb zero,0(s2) + 1fd6: 0100 addi s0,sp,128 + 1fd8: 0200 addi s0,sp,256 + 1fda: 0b04 addi s1,sp,400 + 1fdc: 00090003 lb zero,0(s2) + 1fe0: 0100 addi s0,sp,128 + 1fe2: 0200 addi s0,sp,256 + 1fe4: 0c04 addi s1,sp,528 + 1fe6: 08090003 lb zero,128(s2) + 1fea: 0100 addi s0,sp,128 + 1fec: 0200 addi s0,sp,256 + 1fee: 0c04 addi s1,sp,528 + 1ff0: 00090003 lb zero,0(s2) + 1ff4: 0100 addi s0,sp,128 + 1ff6: 0200 addi s0,sp,256 + 1ff8: 0c04 addi s1,sp,528 + 1ffa: 00090003 lb zero,0(s2) + 1ffe: 0100 addi s0,sp,128 + 2000: 0200 addi s0,sp,256 + 2002: 0e04 addi s1,sp,784 + 2004: 04090003 lb zero,64(s2) + 2008: 0100 addi s0,sp,128 + 200a: 0200 addi s0,sp,256 + 200c: 0e04 addi s1,sp,784 + 200e: 00090003 lb zero,0(s2) + 2012: 0100 addi s0,sp,128 + 2014: 0200 addi s0,sp,256 + 2016: 1004 addi s1,sp,32 + 2018: 04090003 lb zero,64(s2) + 201c: 0100 addi s0,sp,128 + 201e: 0200 addi s0,sp,256 + 2020: 1304 addi s1,sp,416 + 2022: 04090003 lb zero,64(s2) + 2026: 0100 addi s0,sp,128 + 2028: 0200 addi s0,sp,256 + 202a: 1304 addi s1,sp,416 + 202c: 00090003 lb zero,0(s2) + 2030: 0100 addi s0,sp,128 + 2032: 0200 addi s0,sp,256 + 2034: 1304 addi s1,sp,416 + 2036: 04090003 lb zero,64(s2) + 203a: 0100 addi s0,sp,128 + 203c: 0200 addi s0,sp,256 + 203e: 1c04 addi s1,sp,560 + 2040: 04090003 lb zero,64(s2) + 2044: 0100 addi s0,sp,128 + 2046: 0200 addi s0,sp,256 + 2048: 1c04 addi s1,sp,560 + 204a: 04090003 lb zero,64(s2) + 204e: 0100 addi s0,sp,128 + 2050: 0200 addi s0,sp,256 + 2052: 4004 lw s1,0(s0) + 2054: 0306 slli t1,t1,0x1 + 2056: 097e slli s2,s2,0x1f + 2058: 0000 unimp + 205a: 0001 nop + 205c: 0402 c.slli64 s0 + 205e: 0675 addi a2,a2,29 + 2060: 04090203 lb tp,64(s2) + 2064: 0100 addi s0,sp,128 + 2066: 0300 addi s0,sp,384 + 2068: b004 fsd fs1,32(s0) + 206a: 0301 addi t1,t1,0 + 206c: 0900 addi s0,sp,144 + 206e: 0008 0x8 + 2070: 0001 nop + 2072: 01b00403 lb s0,27(zero) # 1b <_start-0x7fffffe5> + 2076: 00090003 lb zero,0(s2) + 207a: 0100 addi s0,sp,128 + 207c: 0300 addi s0,sp,384 + 207e: b004 fsd fs1,32(s0) + 2080: 0301 addi t1,t1,0 + 2082: 0900 addi s0,sp,144 + 2084: 0004 0x4 + 2086: 0001 nop + 2088: 01b00403 lb s0,27(zero) # 1b <_start-0x7fffffe5> + 208c: 00090003 lb zero,0(s2) + 2090: 0100 addi s0,sp,128 + 2092: 0306 slli t1,t1,0x1 + 2094: 0900 addi s0,sp,144 + 2096: 0008 0x8 + 2098: 0001 nop + 209a: 0402 c.slli64 s0 + 209c: 061d addi a2,a2,7 + 209e: 1c090003 lb zero,448(s2) + 20a2: 0100 addi s0,sp,128 + 20a4: 0306 slli t1,t1,0x1 + 20a6: 0900 addi s0,sp,144 + 20a8: 0008 0x8 + 20aa: 0001 nop + 20ac: 0402 c.slli64 s0 + 20ae: 0611 addi a2,a2,4 + 20b0: 08090003 lb zero,128(s2) + 20b4: 0100 addi s0,sp,128 + 20b6: 0200 addi s0,sp,256 + 20b8: 2b04 fld fs1,16(a4) + 20ba: 08090003 lb zero,128(s2) + 20be: 0100 addi s0,sp,128 + 20c0: 0200 addi s0,sp,256 + 20c2: 3404 fld fs1,40(s0) + 20c4: 08090003 lb zero,128(s2) + 20c8: 0100 addi s0,sp,128 + 20ca: 0200 addi s0,sp,256 + 20cc: 3504 fld fs1,40(a0) + 20ce: 0c090003 lb zero,192(s2) + 20d2: 0100 addi s0,sp,128 + 20d4: 0200 addi s0,sp,256 + 20d6: 4004 lw s1,0(s0) + 20d8: 18090003 lb zero,384(s2) + 20dc: 0100 addi s0,sp,128 + 20de: 0200 addi s0,sp,256 + 20e0: 0f04 addi s1,sp,912 + 20e2: 08090003 lb zero,128(s2) + 20e6: 0100 addi s0,sp,128 + 20e8: 0200 addi s0,sp,256 + 20ea: 4204 lw s1,0(a2) + 20ec: 04090003 lb zero,64(s2) + 20f0: 0100 addi s0,sp,128 + 20f2: 0200 addi s0,sp,256 + 20f4: 4204 lw s1,0(a2) + 20f6: 04090003 lb zero,64(s2) + 20fa: 0100 addi s0,sp,128 + 20fc: 0200 addi s0,sp,256 + 20fe: 4204 lw s1,0(a2) + 2100: 00090003 lb zero,0(s2) + 2104: 0100 addi s0,sp,128 + 2106: 0200 addi s0,sp,256 + 2108: 4404 lw s1,8(s0) + 210a: 04090003 lb zero,64(s2) + 210e: 0100 addi s0,sp,128 + 2110: 0200 addi s0,sp,256 + 2112: 4704 lw s1,8(a4) + 2114: 04090003 lb zero,64(s2) + 2118: 0100 addi s0,sp,128 + 211a: 0200 addi s0,sp,256 + 211c: 4704 lw s1,8(a4) + 211e: 00090003 lb zero,0(s2) + 2122: 0100 addi s0,sp,128 + 2124: 0200 addi s0,sp,256 + 2126: 4704 lw s1,8(a4) + 2128: 04090003 lb zero,64(s2) + 212c: 0100 addi s0,sp,128 + 212e: 0200 addi s0,sp,256 + 2130: 5004 lw s1,32(s0) + 2132: 04090003 lb zero,64(s2) + 2136: 0100 addi s0,sp,128 + 2138: 0200 addi s0,sp,256 + 213a: 5004 lw s1,32(s0) + 213c: 04090003 lb zero,64(s2) + 2140: 0100 addi s0,sp,128 + 2142: 0200 addi s0,sp,256 + 2144: 5104 lw s1,32(a0) + 2146: 04090003 lb zero,64(s2) + 214a: 0100 addi s0,sp,128 + 214c: 0306 slli t1,t1,0x1 + 214e: 097f 0x97f + 2150: 0008 0x8 + 2152: 0001 nop + 2154: 0402 c.slli64 s0 + 2156: 0645 addi a2,a2,17 + 2158: 08090103 lb sp,128(s2) + 215c: 0100 addi s0,sp,128 + 215e: 0200 addi s0,sp,256 + 2160: 5f04 lw s1,56(a4) + 2162: 08090003 lb zero,128(s2) + 2166: 0100 addi s0,sp,128 + 2168: 0200 addi s0,sp,256 + 216a: 6804 flw fs1,16(s0) + 216c: 08090003 lb zero,128(s2) + 2170: 0100 addi s0,sp,128 + 2172: 0200 addi s0,sp,256 + 2174: 6904 flw fs1,16(a0) + 2176: 0c090003 lb zero,192(s2) + 217a: 0100 addi s0,sp,128 + 217c: 0200 addi s0,sp,256 + 217e: 7404 flw fs1,40(s0) + 2180: 18090003 lb zero,384(s2) + 2184: 0100 addi s0,sp,128 + 2186: 0200 addi s0,sp,256 + 2188: 4304 lw s1,0(a4) + 218a: 08090003 lb zero,128(s2) + 218e: 0100 addi s0,sp,128 + 2190: 0200 addi s0,sp,256 + 2192: 7604 flw fs1,40(a2) + 2194: 0c090003 lb zero,192(s2) + 2198: 0100 addi s0,sp,128 + 219a: 0200 addi s0,sp,256 + 219c: 7804 flw fs1,48(s0) + 219e: 04090003 lb zero,64(s2) + 21a2: 0100 addi s0,sp,128 + 21a4: 0200 addi s0,sp,256 + 21a6: 7804 flw fs1,48(s0) + 21a8: 00090003 lb zero,0(s2) + 21ac: 0100 addi s0,sp,128 + 21ae: 0200 addi s0,sp,256 + 21b0: 7b04 flw fs1,48(a4) + 21b2: 04090003 lb zero,64(s2) + 21b6: 0100 addi s0,sp,128 + 21b8: 0300 addi s0,sp,384 + 21ba: 8104 0x8104 + 21bc: 0301 addi t1,t1,0 + 21be: 0900 addi s0,sp,144 + 21c0: 0004 0x4 + 21c2: 0001 nop + 21c4: 01810403 lb s0,24(sp) + 21c8: 00090003 lb zero,0(s2) + 21cc: 0100 addi s0,sp,128 + 21ce: 0300 addi s0,sp,384 + 21d0: 8104 0x8104 + 21d2: 0301 addi t1,t1,0 + 21d4: 0900 addi s0,sp,144 + 21d6: 0004 0x4 + 21d8: 0001 nop + 21da: 01830403 lb s0,24(t1) + 21de: 08090003 lb zero,128(s2) + 21e2: 0100 addi s0,sp,128 + 21e4: 0300 addi s0,sp,384 + 21e6: 8304 0x8304 + 21e8: 0301 addi t1,t1,0 + 21ea: 0900 addi s0,sp,144 + 21ec: 000c 0xc + 21ee: 0001 nop + 21f0: 02fd0403 lb s0,47(s10) + 21f4: 04090003 lb zero,64(s2) + 21f8: 0100 addi s0,sp,128 + 21fa: 0300 addi s0,sp,384 + 21fc: fd04 fsw fs1,56(a0) + 21fe: 0302 c.slli64 t1 + 2200: 0900 addi s0,sp,144 + 2202: 0000 unimp + 2204: 0001 nop + 2206: 02fd0403 lb s0,47(s10) + 220a: 00090003 lb zero,0(s2) + 220e: 0100 addi s0,sp,128 + 2210: 0300 addi s0,sp,384 + 2212: fd04 fsw fs1,56(a0) + 2214: 0302 c.slli64 t1 + 2216: 0901 addi s2,s2,0 + 2218: 0000 unimp + 221a: 0001 nop + 221c: 02fd0403 lb s0,47(s10) + 2220: 00090003 lb zero,0(s2) + 2224: 0100 addi s0,sp,128 + 2226: 0300 addi s0,sp,384 + 2228: fd04 fsw fs1,56(a0) + 222a: 0302 c.slli64 t1 + 222c: 0900 addi s0,sp,144 + 222e: 0000 unimp + 2230: 0001 nop + 2232: 02fd0403 lb s0,47(s10) + 2236: 00090003 lb zero,0(s2) + 223a: 0100 addi s0,sp,128 + 223c: 0300 addi s0,sp,384 + 223e: fd04 fsw fs1,56(a0) + 2240: 0302 c.slli64 t1 + 2242: 0900 addi s0,sp,144 + 2244: 0000 unimp + 2246: 0001 nop + 2248: 0402 c.slli64 s0 + 224a: 0325 addi t1,t1,9 + 224c: 0900 addi s0,sp,144 + 224e: 0008 0x8 + 2250: 0001 nop + 2252: 0402 c.slli64 s0 + 2254: 0325 addi t1,t1,9 + 2256: 0900 addi s0,sp,144 + 2258: 0000 unimp + 225a: 0001 nop + 225c: 0402 c.slli64 s0 + 225e: 0325 addi t1,t1,9 + 2260: 0900 addi s0,sp,144 + 2262: 0000 unimp + 2264: 0001 nop + 2266: 0402 c.slli64 s0 + 2268: 0325 addi t1,t1,9 + 226a: 0900 addi s0,sp,144 + 226c: 0000 unimp + 226e: 0001 nop + 2270: 0402 c.slli64 s0 + 2272: 032c addi a1,sp,392 + 2274: 0900 addi s0,sp,144 + 2276: 000c 0xc + 2278: 0001 nop + 227a: 01940403 lb s0,25(s0) + 227e: 08097f03 0x8097f03 + 2282: 0100 addi s0,sp,128 + 2284: 0300 addi s0,sp,384 + 2286: 9404 0x9404 + 2288: 0301 addi t1,t1,0 + 228a: 0900 addi s0,sp,144 + 228c: 0000 unimp + 228e: 0001 nop + 2290: 01940403 lb s0,25(s0) + 2294: 00090003 lb zero,0(s2) + 2298: 0100 addi s0,sp,128 + 229a: 0300 addi s0,sp,384 + 229c: 9404 0x9404 + 229e: 0301 addi t1,t1,0 + 22a0: 0900 addi s0,sp,144 + 22a2: 0000 unimp + 22a4: 0001 nop + 22a6: 01940403 lb s0,25(s0) + 22aa: 00090003 lb zero,0(s2) + 22ae: 0100 addi s0,sp,128 + 22b0: 0300 addi s0,sp,384 + 22b2: 9404 0x9404 + 22b4: 0301 addi t1,t1,0 + 22b6: 0900 addi s0,sp,144 + 22b8: 0000 unimp + 22ba: 0001 nop + 22bc: 01940403 lb s0,25(s0) + 22c0: 00090003 lb zero,0(s2) + 22c4: 0100 addi s0,sp,128 + 22c6: 0300 addi s0,sp,384 + 22c8: 9404 0x9404 + 22ca: 0301 addi t1,t1,0 + 22cc: 0900 addi s0,sp,144 + 22ce: 0000 unimp + 22d0: 0001 nop + 22d2: 02ce0403 lb s0,44(t3) # 1a02c <_start-0x7ffe5fd4> + 22d6: 04090003 lb zero,64(s2) + 22da: 0100 addi s0,sp,128 + 22dc: 0200 addi s0,sp,256 + 22de: 7704 flw fs1,40(a4) + 22e0: 08090003 lb zero,128(s2) + 22e4: 0100 addi s0,sp,128 + 22e6: 0200 addi s0,sp,256 + 22e8: 7704 flw fs1,40(a4) + 22ea: 00090003 lb zero,0(s2) + 22ee: 0100 addi s0,sp,128 + 22f0: 0200 addi s0,sp,256 + 22f2: 7704 flw fs1,40(a4) + 22f4: 00090003 lb zero,0(s2) + 22f8: 0100 addi s0,sp,128 + 22fa: 0200 addi s0,sp,256 + 22fc: 7704 flw fs1,40(a4) + 22fe: 00090003 lb zero,0(s2) + 2302: 0100 addi s0,sp,128 + 2304: 0306 slli t1,t1,0x1 + 2306: 0900 addi s0,sp,144 + 2308: 0008 0x8 + 230a: 0001 nop + 230c: 0402 c.slli64 s0 + 230e: 060d addi a2,a2,3 + 2310: 10090003 lb zero,256(s2) + 2314: 0100 addi s0,sp,128 + 2316: 0200 addi s0,sp,256 + 2318: 0d04 addi s1,sp,656 + 231a: 00090003 lb zero,0(s2) + 231e: 0100 addi s0,sp,128 + 2320: 0300 addi s0,sp,384 + 2322: c204 sw s1,0(a2) + 2324: 0301 addi t1,t1,0 + 2326: 0900 addi s0,sp,144 + 2328: 0004 0x4 + 232a: 0001 nop + 232c: 01c20403 lb s0,28(tp) # 1a01c <_start-0x7ffe5fe4> + 2330: 00090003 lb zero,0(s2) + 2334: 0100 addi s0,sp,128 + 2336: 0300 addi s0,sp,384 + 2338: c204 sw s1,0(a2) + 233a: 0301 addi t1,t1,0 + 233c: 0900 addi s0,sp,144 + 233e: 0000 unimp + 2340: 0001 nop + 2342: 01c40403 lb s0,28(s0) + 2346: 04090003 lb zero,64(s2) + 234a: 0100 addi s0,sp,128 + 234c: 0300 addi s0,sp,384 + 234e: c404 sw s1,8(s0) + 2350: 0601 addi a2,a2,0 + 2352: 00097e03 0x97e03 + 2356: 0100 addi s0,sp,128 + 2358: 0300 addi s0,sp,384 + 235a: c404 sw s1,8(s0) + 235c: 0301 addi t1,t1,0 + 235e: 0902 c.slli64 s2 + 2360: 0004 0x4 + 2362: 0001 nop + 2364: 01c70403 lb s0,28(a4) + 2368: 0306 slli t1,t1,0x1 + 236a: 0900 addi s0,sp,144 + 236c: 0004 0x4 + 236e: 0001 nop + 2370: 01c70403 lb s0,28(a4) + 2374: 00090003 lb zero,0(s2) + 2378: 0100 addi s0,sp,128 + 237a: 0300 addi s0,sp,384 + 237c: c704 sw s1,8(a4) + 237e: 0301 addi t1,t1,0 + 2380: 0900 addi s0,sp,144 + 2382: 0004 0x4 + 2384: 0001 nop + 2386: 01d00403 lb s0,29(zero) # 1d <_start-0x7fffffe3> + 238a: 04090003 lb zero,64(s2) + 238e: 0100 addi s0,sp,128 + 2390: 0300 addi s0,sp,384 + 2392: d004 sw s1,32(s0) + 2394: 0301 addi t1,t1,0 + 2396: 0900 addi s0,sp,144 + 2398: 0004 0x4 + 239a: 0001 nop + 239c: 02a90403 lb s0,42(s2) + 23a0: 00090003 lb zero,0(s2) + 23a4: 0100 addi s0,sp,128 + 23a6: 0300 addi s0,sp,384 + 23a8: e404 fsw fs1,8(s0) + 23aa: 0302 c.slli64 t1 + 23ac: 0900 addi s0,sp,144 + 23ae: 0008 0x8 + 23b0: 0001 nop + 23b2: 02e40403 lb s0,46(s0) + 23b6: 00090003 lb zero,0(s2) + 23ba: 0100 addi s0,sp,128 + 23bc: 0300 addi s0,sp,384 + 23be: d104 sw s1,32(a0) + 23c0: 0301 addi t1,t1,0 + 23c2: 0900 addi s0,sp,144 + 23c4: 0014 0x14 + 23c6: 0001 nop + 23c8: 01e80403 lb s0,30(a6) + 23cc: 0c090003 lb zero,192(s2) + 23d0: 0100 addi s0,sp,128 + 23d2: 0300 addi s0,sp,384 + 23d4: e904 fsw fs1,16(a0) + 23d6: 0301 addi t1,t1,0 + 23d8: 0900 addi s0,sp,144 + 23da: 000c 0xc + 23dc: 0001 nop + 23de: 01f40403 lb s0,31(s0) + 23e2: 18090003 lb zero,384(s2) + 23e6: 0100 addi s0,sp,128 + 23e8: 0300 addi s0,sp,384 + 23ea: f404 fsw fs1,40(s0) + 23ec: 0601 addi a2,a2,0 + 23ee: 04097e03 0x4097e03 + 23f2: 0100 addi s0,sp,128 + 23f4: 0300 addi s0,sp,384 + 23f6: c504 sw s1,8(a0) + 23f8: 0601 addi a2,a2,0 + 23fa: 08090203 lb tp,128(s2) + 23fe: 0100 addi s0,sp,128 + 2400: 0300 addi s0,sp,384 + 2402: df04 sw s1,56(a4) + 2404: 0301 addi t1,t1,0 + 2406: 0900 addi s0,sp,144 + 2408: 000c 0xc + 240a: 0001 nop + 240c: 01c30403 lb s0,28(t1) + 2410: 0c090003 lb zero,192(s2) + 2414: 0100 addi s0,sp,128 + 2416: 0300 addi s0,sp,384 + 2418: f604 fsw fs1,40(a2) + 241a: 0301 addi t1,t1,0 + 241c: 0900 addi s0,sp,144 + 241e: 0004 0x4 + 2420: 0001 nop + 2422: 01f60403 lb s0,31(a2) # b01f <_start-0x7fff4fe1> + 2426: 04090003 lb zero,64(s2) + 242a: 0100 addi s0,sp,128 + 242c: 0300 addi s0,sp,384 + 242e: f604 fsw fs1,40(a2) + 2430: 0301 addi t1,t1,0 + 2432: 0900 addi s0,sp,144 + 2434: 0000 unimp + 2436: 0001 nop + 2438: 01f60403 lb s0,31(a2) + 243c: 00090003 lb zero,0(s2) + 2440: 0100 addi s0,sp,128 + 2442: 0300 addi s0,sp,384 + 2444: f804 fsw fs1,48(s0) + 2446: 0301 addi t1,t1,0 + 2448: 0900 addi s0,sp,144 + 244a: 0004 0x4 + 244c: 0001 nop + 244e: 01fb0403 lb s0,31(s6) + 2452: 04090003 lb zero,64(s2) + 2456: 0100 addi s0,sp,128 + 2458: 0300 addi s0,sp,384 + 245a: fb04 fsw fs1,48(a4) + 245c: 0301 addi t1,t1,0 + 245e: 0900 addi s0,sp,144 + 2460: 0000 unimp + 2462: 0001 nop + 2464: 01fb0403 lb s0,31(s6) + 2468: 04090003 lb zero,64(s2) + 246c: 0100 addi s0,sp,128 + 246e: 0300 addi s0,sp,384 + 2470: 8404 0x8404 + 2472: 0302 c.slli64 t1 + 2474: 0900 addi s0,sp,144 + 2476: 0004 0x4 + 2478: 0001 nop + 247a: 02840403 lb s0,40(s0) + 247e: 04090003 lb zero,64(s2) + 2482: 0100 addi s0,sp,128 + 2484: 0300 addi s0,sp,384 + 2486: 8504 0x8504 + 2488: 0302 c.slli64 t1 + 248a: 0900 addi s0,sp,144 + 248c: 0008 0x8 + 248e: 0601 addi a2,a2,0 + 2490: 08097f03 0x8097f03 + 2494: 0100 addi s0,sp,128 + 2496: 0300 addi s0,sp,384 + 2498: f904 fsw fs1,48(a0) + 249a: 0601 addi a2,a2,0 + 249c: 0c090103 lb sp,192(s2) + 24a0: 0100 addi s0,sp,128 + 24a2: 0300 addi s0,sp,384 + 24a4: 9304 0x9304 + 24a6: 0302 c.slli64 t1 + 24a8: 0900 addi s0,sp,144 + 24aa: 0008 0x8 + 24ac: 0001 nop + 24ae: 029c0403 lb s0,41(s8) + 24b2: 08090003 lb zero,128(s2) + 24b6: 0100 addi s0,sp,128 + 24b8: 0300 addi s0,sp,384 + 24ba: 9d04 0x9d04 + 24bc: 0302 c.slli64 t1 + 24be: 0900 addi s0,sp,144 + 24c0: 000c 0xc + 24c2: 0001 nop + 24c4: 02a80403 lb s0,42(a6) + 24c8: 18090003 lb zero,384(s2) + 24cc: 0100 addi s0,sp,128 + 24ce: 0300 addi s0,sp,384 + 24d0: f704 fsw fs1,40(a4) + 24d2: 0301 addi t1,t1,0 + 24d4: 0900 addi s0,sp,144 + 24d6: 0008 0x8 + 24d8: 0001 nop + 24da: 02aa0403 lb s0,42(s4) + 24de: 0c090003 lb zero,192(s2) + 24e2: 0100 addi s0,sp,128 + 24e4: 0300 addi s0,sp,384 + 24e6: ac04 fsd fs1,24(s0) + 24e8: 0302 c.slli64 t1 + 24ea: 0900 addi s0,sp,144 + 24ec: 0004 0x4 + 24ee: 0001 nop + 24f0: 02ac0403 lb s0,42(s8) + 24f4: 00090003 lb zero,0(s2) + 24f8: 0100 addi s0,sp,128 + 24fa: 0300 addi s0,sp,384 + 24fc: ae04 fsd fs1,24(a2) + 24fe: 0302 c.slli64 t1 + 2500: 0900 addi s0,sp,144 + 2502: 0004 0x4 + 2504: 0001 nop + 2506: 02ae0403 lb s0,42(t3) + 250a: 00090003 lb zero,0(s2) + 250e: 0100 addi s0,sp,128 + 2510: 0306 slli t1,t1,0x1 + 2512: 097f 0x97f + 2514: 0004 0x4 + 2516: 0001 nop + 2518: 02af0403 lb s0,42(t5) + 251c: 0306 slli t1,t1,0x1 + 251e: 0901 addi s2,s2,0 + 2520: 0008 0x8 + 2522: 0001 nop + 2524: 02b60403 lb s0,43(a2) + 2528: 04090003 lb zero,64(s2) + 252c: 0100 addi s0,sp,128 + 252e: 0300 addi s0,sp,384 + 2530: b604 fsd fs1,40(a2) + 2532: 0302 c.slli64 t1 + 2534: 0900 addi s0,sp,144 + 2536: 0000 unimp + 2538: 0001 nop + 253a: 02b60403 lb s0,43(a2) + 253e: 04090003 lb zero,64(s2) + 2542: 0100 addi s0,sp,128 + 2544: 0300 addi s0,sp,384 + 2546: b604 fsd fs1,40(a2) + 2548: 0302 c.slli64 t1 + 254a: 0900 addi s0,sp,144 + 254c: 0000 unimp + 254e: 0001 nop + 2550: 02b80403 lb s0,43(a6) + 2554: 08090003 lb zero,128(s2) + 2558: 0100 addi s0,sp,128 + 255a: 0300 addi s0,sp,384 + 255c: b804 fsd fs1,48(s0) + 255e: 0302 c.slli64 t1 + 2560: 0900 addi s0,sp,144 + 2562: 0004 0x4 + 2564: 0001 nop + 2566: 02b90403 lb s0,43(s2) + 256a: 08090003 lb zero,128(s2) + 256e: 0100 addi s0,sp,128 + 2570: 0306 slli t1,t1,0x1 + 2572: 0900 addi s0,sp,144 + 2574: 0004 0x4 + 2576: 0001 nop + 2578: 02cc0403 lb s0,44(s8) + 257c: 0306 slli t1,t1,0x1 + 257e: 0900 addi s0,sp,144 + 2580: 000c 0xc + 2582: 0001 nop + 2584: 02cc0403 lb s0,44(s8) + 2588: 00090003 lb zero,0(s2) + 258c: 0100 addi s0,sp,128 + 258e: 0300 addi s0,sp,384 + 2590: cc04 sw s1,24(s0) + 2592: 0302 c.slli64 t1 + 2594: 0900 addi s0,sp,144 + 2596: 0000 unimp + 2598: 0001 nop + 259a: 02cc0403 lb s0,44(s8) + 259e: 00090003 lb zero,0(s2) + 25a2: 0100 addi s0,sp,128 + 25a4: 0300 addi s0,sp,384 + 25a6: cc04 sw s1,24(s0) + 25a8: 0302 c.slli64 t1 + 25aa: 0900 addi s0,sp,144 + 25ac: 0000 unimp + 25ae: 0001 nop + 25b0: 02cc0403 lb s0,44(s8) + 25b4: 00090003 lb zero,0(s2) + 25b8: 0100 addi s0,sp,128 + 25ba: 0300 addi s0,sp,384 + 25bc: cc04 sw s1,24(s0) + 25be: 0302 c.slli64 t1 + 25c0: 0900 addi s0,sp,144 + 25c2: 0000 unimp + 25c4: 0001 nop + 25c6: 02cc0403 lb s0,44(s8) + 25ca: 00090003 lb zero,0(s2) + 25ce: 0100 addi s0,sp,128 + 25d0: 0300 addi s0,sp,384 + 25d2: cd04 sw s1,24(a0) + 25d4: 0302 c.slli64 t1 + 25d6: 0900 addi s0,sp,144 + 25d8: 0004 0x4 + 25da: 0601 addi a2,a2,0 + 25dc: 04090003 lb zero,64(s2) + 25e0: 0100 addi s0,sp,128 + 25e2: 0300 addi s0,sp,384 + 25e4: ab04 fsd fs1,16(a4) + 25e6: 0602 c.slli64 a2 + 25e8: 10090003 lb zero,256(s2) + 25ec: 0100 addi s0,sp,128 + 25ee: 0300 addi s0,sp,384 + 25f0: ab04 fsd fs1,16(a4) + 25f2: 0302 c.slli64 t1 + 25f4: 0900 addi s0,sp,144 + 25f6: 0000 unimp + 25f8: 0001 nop + 25fa: 02ab0403 lb s0,42(s6) + 25fe: 04090003 lb zero,64(s2) + 2602: 0100 addi s0,sp,128 + 2604: 0300 addi s0,sp,384 + 2606: ab04 fsd fs1,16(a4) + 2608: 0302 c.slli64 t1 + 260a: 0900 addi s0,sp,144 + 260c: 0000 unimp + 260e: 0001 nop + 2610: 02dd0403 lb s0,45(s10) + 2614: 08090003 lb zero,128(s2) + 2618: 0100 addi s0,sp,128 + 261a: 0300 addi s0,sp,384 + 261c: dd04 sw s1,56(a0) + 261e: 0302 c.slli64 t1 + 2620: 0900 addi s0,sp,144 + 2622: 0004 0x4 + 2624: 0001 nop + 2626: 02e70403 lb s0,46(a4) + 262a: 04090003 lb zero,64(s2) + 262e: 0100 addi s0,sp,128 + 2630: 0300 addi s0,sp,384 + 2632: e704 fsw fs1,8(a4) + 2634: 0302 c.slli64 t1 + 2636: 0900 addi s0,sp,144 + 2638: 0000 unimp + 263a: 0001 nop + 263c: 02e70403 lb s0,46(a4) + 2640: 00090003 lb zero,0(s2) + 2644: 0100 addi s0,sp,128 + 2646: 0300 addi s0,sp,384 + 2648: e704 fsw fs1,8(a4) + 264a: 0302 c.slli64 t1 + 264c: 0900 addi s0,sp,144 + 264e: 0000 unimp + 2650: 0001 nop + 2652: 02e70403 lb s0,46(a4) + 2656: 08090003 lb zero,128(s2) + 265a: 0100 addi s0,sp,128 + 265c: 0300 addi s0,sp,384 + 265e: e704 fsw fs1,8(a4) + 2660: 0302 c.slli64 t1 + 2662: 0900 addi s0,sp,144 + 2664: 0000 unimp + 2666: 0001 nop + 2668: 02e70403 lb s0,46(a4) + 266c: 04090003 lb zero,64(s2) + 2670: 0100 addi s0,sp,128 + 2672: 0300 addi s0,sp,384 + 2674: e704 fsw fs1,8(a4) + 2676: 0302 c.slli64 t1 + 2678: 0900 addi s0,sp,144 + 267a: 0000 unimp + 267c: 0001 nop + 267e: 02e70403 lb s0,46(a4) + 2682: 00090003 lb zero,0(s2) + 2686: 0100 addi s0,sp,128 + 2688: 0300 addi s0,sp,384 + 268a: e704 fsw fs1,8(a4) + 268c: 0302 c.slli64 t1 + 268e: 0900 addi s0,sp,144 + 2690: 0004 0x4 + 2692: 0001 nop + 2694: 02e70403 lb s0,46(a4) + 2698: 00090003 lb zero,0(s2) + 269c: 0100 addi s0,sp,128 + 269e: 0300 addi s0,sp,384 + 26a0: f404 fsw fs1,40(s0) + 26a2: 0302 c.slli64 t1 + 26a4: 0900 addi s0,sp,144 + 26a6: 0004 0x4 + 26a8: 0001 nop + 26aa: 02f40403 lb s0,47(s0) + 26ae: 08090003 lb zero,128(s2) + 26b2: 0100 addi s0,sp,128 + 26b4: 0300 addi s0,sp,384 + 26b6: f404 fsw fs1,40(s0) + 26b8: 0302 c.slli64 t1 + 26ba: 0900 addi s0,sp,144 + 26bc: 0018 0x18 + 26be: 0001 nop + 26c0: 02de0403 lb s0,45(t3) + 26c4: 08090003 lb zero,128(s2) + 26c8: 0100 addi s0,sp,128 + 26ca: 0306 slli t1,t1,0x1 + 26cc: 0900 addi s0,sp,144 + 26ce: 0004 0x4 + 26d0: 0001 nop + 26d2: 02f50403 lb s0,47(a0) + 26d6: 0306 slli t1,t1,0x1 + 26d8: 0900 addi s0,sp,144 + 26da: 000c 0xc + 26dc: 0001 nop + 26de: 02f50403 lb s0,47(a0) + 26e2: 0c090003 lb zero,192(s2) + 26e6: 0100 addi s0,sp,128 + 26e8: 0306 slli t1,t1,0x1 + 26ea: 097e slli s2,s2,0x1f + 26ec: 0008 0x8 + 26ee: 0301 addi t1,t1,0 + 26f0: 0901 addi s2,s2,0 + 26f2: 0008 0x8 + 26f4: 0001 nop + 26f6: 0402 c.slli64 s0 + 26f8: 0203062f 0x203062f + 26fc: 1009 c.nop -30 + 26fe: 0100 addi s0,sp,128 + 2700: 0200 addi s0,sp,256 + 2702: 2f04 fld fs1,24(a4) + 2704: 00090003 lb zero,0(s2) + 2708: 0100 addi s0,sp,128 + 270a: 0200 addi s0,sp,256 + 270c: 2f04 fld fs1,24(a4) + 270e: 00090003 lb zero,0(s2) + 2712: 0100 addi s0,sp,128 + 2714: 0200 addi s0,sp,256 + 2716: 3f04 fld fs1,56(a4) + 2718: 08090003 lb zero,128(s2) + 271c: 0100 addi s0,sp,128 + 271e: 0200 addi s0,sp,256 + 2720: 3f04 fld fs1,56(a4) + 2722: 00090003 lb zero,0(s2) + 2726: 0100 addi s0,sp,128 + 2728: 0200 addi s0,sp,256 + 272a: 3f04 fld fs1,56(a4) + 272c: 04090003 lb zero,64(s2) + 2730: 0100 addi s0,sp,128 + 2732: 0306 slli t1,t1,0x1 + 2734: 0900 addi s0,sp,144 + 2736: 0008 0x8 + 2738: 0001 nop + 273a: 0402 c.slli64 s0 + 273c: 0003064f fnmadd.s fa2,ft6,ft0,ft0,rne + 2740: 0c09 addi s8,s8,2 + 2742: 0100 addi s0,sp,128 + 2744: 0200 addi s0,sp,256 + 2746: 4f04 lw s1,24(a4) + 2748: 00090003 lb zero,0(s2) + 274c: 0100 addi s0,sp,128 + 274e: 0200 addi s0,sp,256 + 2750: 4f04 lw s1,24(a4) + 2752: 08090003 lb zero,128(s2) + 2756: 0100 addi s0,sp,128 + 2758: 0200 addi s0,sp,256 + 275a: 5004 lw s1,32(s0) + 275c: 0306 slli t1,t1,0x1 + 275e: 0900 addi s0,sp,144 + 2760: 0004 0x4 + 2762: 0301 addi t1,t1,0 + 2764: 0900 addi s0,sp,144 + 2766: 0004 0x4 + 2768: 0001 nop + 276a: 0402 c.slli64 s0 + 276c: 065a slli a2,a2,0x16 + 276e: 08090003 lb zero,128(s2) + 2772: 0100 addi s0,sp,128 + 2774: 0200 addi s0,sp,256 + 2776: 5a04 lw s1,48(a2) + 2778: 00090003 lb zero,0(s2) + 277c: 0100 addi s0,sp,128 + 277e: 0200 addi s0,sp,256 + 2780: 5a04 lw s1,48(a2) + 2782: 00090003 lb zero,0(s2) + 2786: 0100 addi s0,sp,128 + 2788: 0200 addi s0,sp,256 + 278a: 5a04 lw s1,48(a2) + 278c: 00090003 lb zero,0(s2) + 2790: 0100 addi s0,sp,128 + 2792: 0200 addi s0,sp,256 + 2794: 5a04 lw s1,48(a2) + 2796: 00090003 lb zero,0(s2) + 279a: 0100 addi s0,sp,128 + 279c: 0200 addi s0,sp,256 + 279e: 5a04 lw s1,48(a2) + 27a0: 00090003 lb zero,0(s2) + 27a4: 0100 addi s0,sp,128 + 27a6: 0200 addi s0,sp,256 + 27a8: 5a04 lw s1,48(a2) + 27aa: 00090003 lb zero,0(s2) + 27ae: 0100 addi s0,sp,128 + 27b0: 0105 addi sp,sp,1 + 27b2: 0200 addi s0,sp,256 + 27b4: 5a04 lw s1,48(a2) + 27b6: 0306 slli t1,t1,0x1 + 27b8: 0904 addi s1,sp,144 + 27ba: 0000 unimp + 27bc: 0501 addi a0,a0,0 + 27be: 04020003 lb zero,64(tp) # 40 <_start-0x7fffffc0> + 27c2: 035a slli t1,t1,0x16 + 27c4: 097c addi a5,sp,156 + 27c6: 0008 0x8 + 27c8: 0001 nop + 27ca: 0402 c.slli64 s0 + 27cc: 065a slli a2,a2,0x16 + 27ce: 1c090003 lb zero,448(s2) + 27d2: 0100 addi s0,sp,128 + 27d4: 0200 addi s0,sp,256 + 27d6: 5a04 lw s1,48(a2) + 27d8: 00090003 lb zero,0(s2) + 27dc: 0100 addi s0,sp,128 + 27de: 0200 addi s0,sp,256 + 27e0: 5a04 lw s1,48(a2) + 27e2: 00090003 lb zero,0(s2) + 27e6: 0100 addi s0,sp,128 + 27e8: 0200 addi s0,sp,256 + 27ea: 5a04 lw s1,48(a2) + 27ec: 00090103 lb sp,0(s2) + 27f0: 0100 addi s0,sp,128 + 27f2: 0200 addi s0,sp,256 + 27f4: 5a04 lw s1,48(a2) + 27f6: 00090003 lb zero,0(s2) + 27fa: 0100 addi s0,sp,128 + 27fc: 0200 addi s0,sp,256 + 27fe: 5a04 lw s1,48(a2) + 2800: 00090003 lb zero,0(s2) + 2804: 0100 addi s0,sp,128 + 2806: 0200 addi s0,sp,256 + 2808: 5a04 lw s1,48(a2) + 280a: 00090203 lb tp,0(s2) + 280e: 0100 addi s0,sp,128 + 2810: 0105 addi sp,sp,1 + 2812: 0200 addi s0,sp,256 + 2814: 5a04 lw s1,48(a2) + 2816: 0306 slli t1,t1,0x1 + 2818: 0901 addi s2,s2,0 + 281a: 0000 unimp + 281c: 0901 addi s2,s2,0 + 281e: 0024 addi s1,sp,8 + 2820: 0100 addi s0,sp,128 + 2822: c301 beqz a4,2822 <_start-0x7fffd7de> + 2824: 0001 nop + 2826: 0300 addi s0,sp,384 + 2828: a800 fsd fs0,16(s0) + 282a: 0000 unimp + 282c: 0100 addi s0,sp,128 + 282e: fb01 bnez a4,273e <_start-0x7fffd8c2> + 2830: 0d0e slli s10,s10,0x3 + 2832: 0100 addi s0,sp,128 + 2834: 0101 addi sp,sp,0 + 2836: 0001 nop + 2838: 0000 unimp + 283a: 0001 nop + 283c: 0100 addi s0,sp,128 + 283e: 2e2e fld ft8,200(sp) + 2840: 2f2e2e2f 0x2f2e2e2f + 2844: 2e2e fld ft8,200(sp) + 2846: 2f2e2e2f 0x2f2e2e2f + 284a: 6972 flw fs2,28(sp) + 284c: 2d766373 csrrsi t1,0x2d7,12 + 2850: 2f636367 0x2f636367 + 2854: 696c flw fa1,84(a0) + 2856: 6762 flw fa4,24(sp) + 2858: 732f6363 bltu t5,s2,2f7e <_start-0x7fffd082> + 285c: 2d74666f jal a2,49332 <_start-0x7ffb6cce> + 2860: 7066 flw ft0,120(sp) + 2862: 2e00 fld fs0,24(a2) + 2864: 2e00 fld fs0,24(a2) + 2866: 2f2e fld ft10,200(sp) + 2868: 2e2e fld ft8,200(sp) + 286a: 2f2e2e2f 0x2f2e2e2f + 286e: 2e2e fld ft8,200(sp) + 2870: 7369722f 0x7369722f + 2874: 672d7663 bgeu s10,s2,2ee0 <_start-0x7fffd120> + 2878: 6c2f6363 bltu t5,sp,2f3e <_start-0x7fffd0c2> + 287c: 6269 lui tp,0x1a + 287e: 2f636367 0x2f636367 + 2882: 2e2e fld ft8,200(sp) + 2884: 636e692f 0x636e692f + 2888: 756c flw fa1,108(a0) + 288a: 6564 flw fs1,76(a0) + 288c: 0000 unimp + 288e: 6e75 lui t3,0x1d + 2890: 7364726f jal tp,49fc6 <_start-0x7ffb603a> + 2894: 3266 fld ft4,120(sp) + 2896: 632e flw ft6,200(sp) + 2898: 0100 addi s0,sp,128 + 289a: 0000 unimp + 289c: 2d706673 csrrsi a2,0x2d7,0 + 28a0: 616d addi sp,sp,240 + 28a2: 6e696863 bltu s2,t1,2f92 <_start-0x7fffd06e> + 28a6: 2e65 jal 2c5e <_start-0x7fffd3a2> + 28a8: 0068 addi a0,sp,12 + 28aa: 0002 c.slli64 zero + 28ac: 7300 flw fs0,32(a4) + 28ae: 2d74666f jal a2,49384 <_start-0x7ffb6c7c> + 28b2: 7066 flw ft0,120(sp) + 28b4: 682e flw fa6,200(sp) + 28b6: 0100 addi s0,sp,128 + 28b8: 0000 unimp + 28ba: 676e6973 csrrsi s2,0x676,28 + 28be: 656c flw fa1,76(a0) + 28c0: 682e flw fa6,200(sp) + 28c2: 0100 addi s0,sp,128 + 28c4: 0000 unimp + 28c6: 6f6c flw fa1,92(a4) + 28c8: 676e flw fa4,216(sp) + 28ca: 6f6c flw fa1,92(a4) + 28cc: 676e flw fa4,216(sp) + 28ce: 682e flw fa6,200(sp) + 28d0: 0300 addi s0,sp,384 + 28d2: 0000 unimp + 28d4: 0500 addi s0,sp,640 + 28d6: 0001 nop + 28d8: 0205 addi tp,tp,1 + 28da: 1e38 addi a4,sp,824 + 28dc: 8000 0x8000 + 28de: 05012203 lw tp,80(sp) + 28e2: 09010303 lb t1,144(sp) + 28e6: 0000 unimp + 28e8: 0301 addi t1,t1,0 + 28ea: 0900 addi s0,sp,144 + 28ec: 0000 unimp + 28ee: 0501 addi a0,a0,0 + 28f0: 030d addi t1,t1,3 + 28f2: 0900 addi s0,sp,144 + 28f4: 0000 unimp + 28f6: 0501 addi a0,a0,0 + 28f8: 09010303 lb t1,144(sp) + 28fc: 0000 unimp + 28fe: 0301 addi t1,t1,0 + 2900: 0900 addi s0,sp,144 + 2902: 0000 unimp + 2904: 0301 addi t1,t1,0 + 2906: 0900 addi s0,sp,144 + 2908: 0000 unimp + 290a: 0301 addi t1,t1,0 + 290c: 0900 addi s0,sp,144 + 290e: 0000 unimp + 2910: 0301 addi t1,t1,0 + 2912: 0901 addi s2,s2,0 + 2914: 0000 unimp + 2916: 0301 addi t1,t1,0 + 2918: 0900 addi s0,sp,144 + 291a: 0000 unimp + 291c: 0301 addi t1,t1,0 + 291e: 0900 addi s0,sp,144 + 2920: 0000 unimp + 2922: 0301 addi t1,t1,0 + 2924: 0900 addi s0,sp,144 + 2926: 0000 unimp + 2928: 0301 addi t1,t1,0 + 292a: 0901 addi s2,s2,0 + 292c: 0000 unimp + 292e: 0301 addi t1,t1,0 + 2930: 0902 c.slli64 s2 + 2932: 0000 unimp + 2934: 0301 addi t1,t1,0 + 2936: 0901 addi s2,s2,0 + 2938: 0000 unimp + 293a: 0301 addi t1,t1,0 + 293c: 0900 addi s0,sp,144 + 293e: 0000 unimp + 2940: 0301 addi t1,t1,0 + 2942: 0900 addi s0,sp,144 + 2944: 0000 unimp + 2946: 0301 addi t1,t1,0 + 2948: 0900 addi s0,sp,144 + 294a: 0000 unimp + 294c: 0301 addi t1,t1,0 + 294e: 0900 addi s0,sp,144 + 2950: 000c 0xc + 2952: 0301 addi t1,t1,0 + 2954: 0900 addi s0,sp,144 + 2956: 0000 unimp + 2958: 0301 addi t1,t1,0 + 295a: 0900 addi s0,sp,144 + 295c: 0000 unimp + 295e: 0301 addi t1,t1,0 + 2960: 0901 addi s2,s2,0 + 2962: 0000 unimp + 2964: 0301 addi t1,t1,0 + 2966: 0900 addi s0,sp,144 + 2968: 0000 unimp + 296a: 0301 addi t1,t1,0 + 296c: 0900 addi s0,sp,144 + 296e: 0000 unimp + 2970: 0301 addi t1,t1,0 + 2972: 0900 addi s0,sp,144 + 2974: 0000 unimp + 2976: 0601 addi a2,a2,0 + 2978: 00090103 lb sp,0(s2) + 297c: 0100 addi s0,sp,128 + 297e: 04097f03 0x4097f03 + 2982: 0100 addi s0,sp,128 + 2984: 0306 slli t1,t1,0x1 + 2986: 0900 addi s0,sp,144 + 2988: 0004 0x4 + 298a: 0601 addi a2,a2,0 + 298c: 00090103 lb sp,0(s2) + 2990: 0100 addi s0,sp,128 + 2992: 0306 slli t1,t1,0x1 + 2994: 097f 0x97f + 2996: 0010 0x10 + 2998: 0301 addi t1,t1,0 + 299a: 0900 addi s0,sp,144 + 299c: 0000 unimp + 299e: 0301 addi t1,t1,0 + 29a0: 0901 addi s2,s2,0 + 29a2: 0000 unimp + 29a4: 0301 addi t1,t1,0 + 29a6: 0900 addi s0,sp,144 + 29a8: 0000 unimp + 29aa: 0301 addi t1,t1,0 + 29ac: 0900 addi s0,sp,144 + 29ae: 0000 unimp + 29b0: 0301 addi t1,t1,0 + 29b2: 0900 addi s0,sp,144 + 29b4: 0000 unimp + 29b6: 0301 addi t1,t1,0 + 29b8: 0900 addi s0,sp,144 + 29ba: 0000 unimp + 29bc: 0001 nop + 29be: 0402 c.slli64 s0 + 29c0: 0614 addi a3,sp,768 + 29c2: 08090003 lb zero,128(s2) + 29c6: 0100 addi s0,sp,128 + 29c8: 0200 addi s0,sp,256 + 29ca: 1704 addi s1,sp,928 + 29cc: 04090003 lb zero,64(s2) + 29d0: 0100 addi s0,sp,128 + 29d2: 0200 addi s0,sp,256 + 29d4: 1804 addi s1,sp,48 + 29d6: 0c090003 lb zero,192(s2) + 29da: 0100 addi s0,sp,128 + 29dc: 0105 addi sp,sp,1 + 29de: 04090403 lb s0,64(s2) + 29e2: 0100 addi s0,sp,128 + 29e4: 0409 addi s0,s0,2 + 29e6: 0000 unimp + 29e8: 0101 addi sp,sp,0 + 29ea: 02b0 addi a2,sp,328 + 29ec: 0000 unimp + 29ee: 021e0003 lb zero,33(t3) # 1d021 <_start-0x7ffe2fdf> + 29f2: 0000 unimp + 29f4: 0101 addi sp,sp,0 + 29f6: 000d0efb 0xd0efb + 29fa: 0101 addi sp,sp,0 + 29fc: 0101 addi sp,sp,0 + 29fe: 0000 unimp + 2a00: 0100 addi s0,sp,128 + 2a02: 0000 unimp + 2a04: 2e01 jal 2d14 <_start-0x7fffd2ec> + 2a06: 2f2e fld ft10,200(sp) + 2a08: 2e2e fld ft8,200(sp) + 2a0a: 2f2e2e2f 0x2f2e2e2f + 2a0e: 2e2e fld ft8,200(sp) + 2a10: 7369722f 0x7369722f + 2a14: 672d7663 bgeu s10,s2,3080 <_start-0x7fffcf80> + 2a18: 6c2f6363 bltu t5,sp,30de <_start-0x7fffcf22> + 2a1c: 6269 lui tp,0x1a + 2a1e: 00636367 0x636367 + 2a22: 6d6f682f 0x6d6f682f + 2a26: 2f65 jal 31de <_start-0x7fffce22> + 2a28: 6c62 flw fs8,24(sp) + 2a2a: 6961 lui s2,0x18 + 2a2c: 642f6573 csrrsi a0,0x642,30 + 2a30: 7665 lui a2,0xffff9 + 2a32: 7369722f 0x7369722f + 2a36: 672d7663 bgeu s10,s2,30a2 <_start-0x7fffcf5e> + 2a3a: 756e flw fa0,248(sp) + 2a3c: 742d lui s0,0xfffeb + 2a3e: 636c6f6f jal t5,c9074 <_start-0x7ff36f8c> + 2a42: 6168 flw fa0,68(a0) + 2a44: 6e69 lui t3,0x1a + 2a46: 2f32 fld ft10,264(sp) + 2a48: 7562 flw fa0,56(sp) + 2a4a: 6c69 lui s8,0x1a + 2a4c: 2f64 fld fs1,216(a4) + 2a4e: 7562 flw fa0,56(sp) + 2a50: 6c69 lui s8,0x1a + 2a52: 2d64 fld fs1,216(a0) + 2a54: 2d636367 0x2d636367 + 2a58: 656e flw fa0,216(sp) + 2a5a: 62696c77 0x62696c77 + 2a5e: 732d lui t1,0xfffeb + 2a60: 6174 flw fa3,68(a0) + 2a62: 2f326567 0x2f326567 + 2a66: 2f636367 0x2f636367 + 2a6a: 6e69 lui t3,0x1a + 2a6c: 64756c63 bltu a0,t2,30c4 <_start-0x7fffcf3c> + 2a70: 0065 c.nop 25 + 2a72: 6d6f682f 0x6d6f682f + 2a76: 2f65 jal 322e <_start-0x7fffcdd2> + 2a78: 6c62 flw fs8,24(sp) + 2a7a: 6961 lui s2,0x18 + 2a7c: 642f6573 csrrsi a0,0x642,30 + 2a80: 7665 lui a2,0xffff9 + 2a82: 7369722f 0x7369722f + 2a86: 672d7663 bgeu s10,s2,30f2 <_start-0x7fffcf0e> + 2a8a: 756e flw fa0,248(sp) + 2a8c: 742d lui s0,0xfffeb + 2a8e: 636c6f6f jal t5,c90c4 <_start-0x7ff36f3c> + 2a92: 6168 flw fa0,68(a0) + 2a94: 6e69 lui t3,0x1a + 2a96: 2f32 fld ft10,264(sp) + 2a98: 7264 flw fs1,100(a2) + 2a9a: 2f73706f j 3a590 <_start-0x7ffc5a70> + 2a9e: 6972 flw fs2,28(sp) + 2aa0: 33766373 csrrsi t1,mhpmevent23,12 + 2aa4: 2d32 fld fs10,264(sp) + 2aa6: 6e75 lui t3,0x1d + 2aa8: 776f6e6b 0x776f6e6b + 2aac: 2d6e fld fs10,216(sp) + 2aae: 6c65 lui s8,0x19 + 2ab0: 2f66 fld ft10,88(sp) + 2ab2: 6e69 lui t3,0x1a + 2ab4: 64756c63 bltu a0,t2,310c <_start-0x7fffcef4> + 2ab8: 2f65 jal 3270 <_start-0x7fffcd90> + 2aba: 00737973 csrrci s2,0x7,6 + 2abe: 6d6f682f 0x6d6f682f + 2ac2: 2f65 jal 327a <_start-0x7fffcd86> + 2ac4: 6c62 flw fs8,24(sp) + 2ac6: 6961 lui s2,0x18 + 2ac8: 642f6573 csrrsi a0,0x642,30 + 2acc: 7665 lui a2,0xffff9 + 2ace: 7369722f 0x7369722f + 2ad2: 672d7663 bgeu s10,s2,313e <_start-0x7fffcec2> + 2ad6: 756e flw fa0,248(sp) + 2ad8: 742d lui s0,0xfffeb + 2ada: 636c6f6f jal t5,c9110 <_start-0x7ff36ef0> + 2ade: 6168 flw fa0,68(a0) + 2ae0: 6e69 lui t3,0x1a + 2ae2: 2f32 fld ft10,264(sp) + 2ae4: 7264 flw fs1,100(a2) + 2ae6: 2f73706f j 3a5dc <_start-0x7ffc5a24> + 2aea: 6972 flw fs2,28(sp) + 2aec: 33766373 csrrsi t1,mhpmevent23,12 + 2af0: 2d32 fld fs10,264(sp) + 2af2: 6e75 lui t3,0x1d + 2af4: 776f6e6b 0x776f6e6b + 2af8: 2d6e fld fs10,216(sp) + 2afa: 6c65 lui s8,0x19 + 2afc: 2f66 fld ft10,88(sp) + 2afe: 6e69 lui t3,0x1a + 2b00: 64756c63 bltu a0,t2,3158 <_start-0x7fffcea8> + 2b04: 0065 c.nop 25 + 2b06: 2e2e fld ft8,200(sp) + 2b08: 2f2e2e2f 0x2f2e2e2f + 2b0c: 2e2e fld ft8,200(sp) + 2b0e: 2f2e2e2f 0x2f2e2e2f + 2b12: 6972 flw fs2,28(sp) + 2b14: 2d766373 csrrsi t1,0x2d7,12 + 2b18: 2f636367 0x2f636367 + 2b1c: 696c flw fa1,84(a0) + 2b1e: 6762 flw fa4,24(sp) + 2b20: 2e2f6363 bltu t5,sp,2e06 <_start-0x7fffd1fa> + 2b24: 2f2e fld ft10,200(sp) + 2b26: 6e69 lui t3,0x1a + 2b28: 64756c63 bltu a0,t2,3180 <_start-0x7fffce80> + 2b2c: 0065 c.nop 25 + 2b2e: 2e2e fld ft8,200(sp) + 2b30: 2f2e2e2f 0x2f2e2e2f + 2b34: 2e2e fld ft8,200(sp) + 2b36: 2f2e2e2f 0x2f2e2e2f + 2b3a: 6972 flw fs2,28(sp) + 2b3c: 2d766373 csrrsi t1,0x2d7,12 + 2b40: 2f636367 0x2f636367 + 2b44: 696c flw fa1,84(a0) + 2b46: 6762 flw fa4,24(sp) + 2b48: 2e2f6363 bltu t5,sp,2e2e <_start-0x7fffd1d2> + 2b4c: 2f2e fld ft10,200(sp) + 2b4e: 2f636367 0x2f636367 + 2b52: 666e6f63 bltu t3,t1,31d0 <_start-0x7fffce30> + 2b56: 6769 lui a4,0x1a + 2b58: 7369722f 0x7369722f + 2b5c: 2e007663 bgeu zero,zero,2e48 <_start-0x7fffd1b8> + 2b60: 2f2e fld ft10,200(sp) + 2b62: 2e2e fld ft8,200(sp) + 2b64: 672f2e2f amoand.w.aqrl t3,s2,(t5) + 2b68: 00006363 bltu zero,zero,2b6e <_start-0x7fffd492> + 2b6c: 696c flw fa1,84(a0) + 2b6e: 6762 flw fa4,24(sp) + 2b70: 2e326363 bltu tp,gp,2e56 <_start-0x7fffd1aa> + 2b74: 00010063 beqz sp,2b74 <_start-0x7fffd48c> + 2b78: 7300 flw fs0,32(a4) + 2b7a: 6474 flw fa3,76(s0) + 2b7c: 6564 flw fs1,76(a0) + 2b7e: 2e66 fld ft8,88(sp) + 2b80: 0068 addi a0,sp,12 + 2b82: 0002 c.slli64 zero + 2b84: 5f00 lw s0,56(a4) + 2b86: 7974 flw fa3,116(a0) + 2b88: 6570 flw fa2,76(a0) + 2b8a: 00682e73 csrrs t3,0x6,a6 + 2b8e: 72000003 lb zero,1824(zero) # 720 <_start-0x7ffff8e0> + 2b92: 6565 lui a0,0x19 + 2b94: 746e flw fs0,248(sp) + 2b96: 682e flw fa6,200(sp) + 2b98: 0300 addi s0,sp,384 + 2b9a: 0000 unimp + 2b9c: 6f6c flw fa1,92(a4) + 2b9e: 682e6b63 bltu t3,sp,3234 <_start-0x7fffcdcc> + 2ba2: 0300 addi s0,sp,384 + 2ba4: 0000 unimp + 2ba6: 7265 lui tp,0xffff9 + 2ba8: 6e72 flw ft8,28(sp) + 2baa: 00682e6f jal t3,84bb0 <_start-0x7ff7b450> + 2bae: 73000003 lb zero,1840(zero) # 730 <_start-0x7ffff8d0> + 2bb2: 6474 flw fa3,76(s0) + 2bb4: 696c flw fa1,84(a0) + 2bb6: 2e62 fld ft8,24(sp) + 2bb8: 0068 addi a0,sp,12 + 2bba: 0004 0x4 + 2bbc: 7500 flw fs0,40(a0) + 2bbe: 696e flw fs2,216(sp) + 2bc0: 2e647473 csrrci s0,0x2e6,8 + 2bc4: 0068 addi a0,sp,12 + 2bc6: 74000003 lb zero,1856(zero) # 740 <_start-0x7ffff8c0> + 2bca: 6d69 lui s10,0x1a + 2bcc: 2e65 jal 2f84 <_start-0x7fffd07c> + 2bce: 0068 addi a0,sp,12 + 2bd0: 0004 0x4 + 2bd2: 6800 flw fs0,16(s0) + 2bd4: 7361 lui t1,0xffff8 + 2bd6: 7468 flw fa0,108(s0) + 2bd8: 6261 lui tp,0x18 + 2bda: 682e flw fa6,200(sp) + 2bdc: 0500 addi s0,sp,640 + 2bde: 0000 unimp + 2be0: 6972 flw fs2,28(sp) + 2be2: 2d766373 csrrsi t1,0x2d7,12 + 2be6: 7374706f j 4ab1c <_start-0x7ffb54e4> + 2bea: 682e flw fa6,200(sp) + 2bec: 0600 addi s0,sp,768 + 2bee: 0000 unimp + 2bf0: 6e69 lui t3,0x1a + 2bf2: 632d6e73 csrrsi t3,0x632,26 + 2bf6: 74736e6f jal t3,39b3c <_start-0x7ffc64c4> + 2bfa: 6e61 lui t3,0x18 + 2bfc: 7374 flw fa3,100(a4) + 2bfe: 682e flw fa6,200(sp) + 2c00: 0700 addi s0,sp,896 + 2c02: 0000 unimp + 2c04: 696c flw fa1,84(a0) + 2c06: 6762 flw fa4,24(sp) + 2c08: 2e326363 bltu tp,gp,2eee <_start-0x7fffd112> + 2c0c: 0068 addi a0,sp,12 + 2c0e: 0001 nop + 2c10: 0000 unimp + 2c12: 0105 addi sp,sp,1 + 2c14: 0500 addi s0,sp,640 + 2c16: 7c02 flw fs8,32(sp) + 2c18: 001e c.slli zero,0x7 + 2c1a: 0380 addi s0,sp,448 + 2c1c: 05c2 slli a1,a1,0x10 + 2c1e: 0501 addi a0,a0,0 + 2c20: 09010303 lb t1,144(sp) + 2c24: 0000 unimp + 2c26: 0301 addi t1,t1,0 + 2c28: 0902 c.slli64 s2 + 2c2a: 0000 unimp + 2c2c: 0301 addi t1,t1,0 + 2c2e: 0900 addi s0,sp,144 + 2c30: 0000 unimp + 2c32: 0301 addi t1,t1,0 + 2c34: 0900 addi s0,sp,144 + 2c36: 0000 unimp + 2c38: 0301 addi t1,t1,0 + 2c3a: 0900 addi s0,sp,144 + 2c3c: 0000 unimp + 2c3e: 0301 addi t1,t1,0 + 2c40: 0900 addi s0,sp,144 + 2c42: 0000 unimp + 2c44: 0001 nop + 2c46: 0402 c.slli64 s0 + 2c48: 00030603 lb a2,0(t1) # ffff8000 <__global_pointer$+0x7fff4398> + 2c4c: 0809 addi a6,a6,2 + 2c4e: 0100 addi s0,sp,128 + 2c50: 0200 addi s0,sp,256 + 2c52: 0e04 addi s1,sp,784 + 2c54: 0306 slli t1,t1,0x1 + 2c56: 0900 addi s0,sp,144 + 2c58: 000c 0xc + 2c5a: 0001 nop + 2c5c: 0402 c.slli64 s0 + 2c5e: 030e slli t1,t1,0x3 + 2c60: 0900 addi s0,sp,144 + 2c62: 0000 unimp + 2c64: 0001 nop + 2c66: 0402 c.slli64 s0 + 2c68: 030e slli t1,t1,0x3 + 2c6a: 0902 c.slli64 s2 + 2c6c: 0000 unimp + 2c6e: 0001 nop + 2c70: 0402 c.slli64 s0 + 2c72: 060e slli a2,a2,0x3 + 2c74: 00097e03 0x97e03 + 2c78: 0100 addi s0,sp,128 + 2c7a: 0105 addi sp,sp,1 + 2c7c: 0200 addi s0,sp,256 + 2c7e: 0e04 addi s1,sp,784 + 2c80: 1c090303 lb t1,448(s2) # 181c0 <_start-0x7ffe7e40> + 2c84: 0100 addi s0,sp,128 + 2c86: 0305 addi t1,t1,1 + 2c88: 0200 addi s0,sp,256 + 2c8a: 0404 addi s1,sp,512 + 2c8c: 08097d03 0x8097d03 + 2c90: 0100 addi s0,sp,128 + 2c92: 0c090003 lb zero,192(s2) + 2c96: 0100 addi s0,sp,128 + 2c98: 0809 addi a6,a6,2 + 2c9a: 0000 unimp + 2c9c: 0101 addi sp,sp,0 + 2c9e: 0224 addi s1,sp,264 + 2ca0: 0000 unimp + 2ca2: 021e0003 lb zero,33(t3) # 18021 <_start-0x7ffe7fdf> + 2ca6: 0000 unimp + 2ca8: 0101 addi sp,sp,0 + 2caa: 000d0efb 0xd0efb + 2cae: 0101 addi sp,sp,0 + 2cb0: 0101 addi sp,sp,0 + 2cb2: 0000 unimp + 2cb4: 0100 addi s0,sp,128 + 2cb6: 0000 unimp + 2cb8: 2f01 jal 33c8 <_start-0x7fffcc38> + 2cba: 6f68 flw fa0,92(a4) + 2cbc: 656d lui a0,0x1b + 2cbe: 616c622f 0x616c622f + 2cc2: 7369 lui t1,0xffffa + 2cc4: 2f65 jal 347c <_start-0x7fffcb84> + 2cc6: 6564 flw fs1,76(a0) + 2cc8: 2f76 fld ft10,344(sp) + 2cca: 6972 flw fs2,28(sp) + 2ccc: 2d766373 csrrsi t1,0x2d7,12 + 2cd0: 2d756e67 0x2d756e67 + 2cd4: 6f74 flw fa3,92(a4) + 2cd6: 68636c6f jal s8,3935c <_start-0x7ffc6ca4> + 2cda: 6961 lui s2,0x18 + 2cdc: 326e fld ft4,248(sp) + 2cde: 6975622f 0x6975622f + 2ce2: 646c flw fa1,76(s0) + 2ce4: 6975622f 0x6975622f + 2ce8: 646c flw fa1,76(s0) + 2cea: 672d lui a4,0xb + 2cec: 6e2d6363 bltu s10,sp,33d2 <_start-0x7fffcc2e> + 2cf0: 7765 lui a4,0xffff9 + 2cf2: 696c flw fa1,84(a0) + 2cf4: 2d62 fld fs10,24(sp) + 2cf6: 67617473 csrrci s0,0x676,2 + 2cfa: 3265 jal 26a2 <_start-0x7fffd95e> + 2cfc: 6363672f 0x6363672f + 2d00: 636e692f 0x636e692f + 2d04: 756c flw fa1,108(a0) + 2d06: 6564 flw fs1,76(a0) + 2d08: 2f00 fld fs0,24(a4) + 2d0a: 6f68 flw fa0,92(a4) + 2d0c: 656d lui a0,0x1b + 2d0e: 616c622f 0x616c622f + 2d12: 7369 lui t1,0xffffa + 2d14: 2f65 jal 34cc <_start-0x7fffcb34> + 2d16: 6564 flw fs1,76(a0) + 2d18: 2f76 fld ft10,344(sp) + 2d1a: 6972 flw fs2,28(sp) + 2d1c: 2d766373 csrrsi t1,0x2d7,12 + 2d20: 2d756e67 0x2d756e67 + 2d24: 6f74 flw fa3,92(a4) + 2d26: 68636c6f jal s8,393ac <_start-0x7ffc6c54> + 2d2a: 6961 lui s2,0x18 + 2d2c: 326e fld ft4,248(sp) + 2d2e: 6f72642f 0x6f72642f + 2d32: 7370 flw fa2,100(a4) + 2d34: 7369722f 0x7369722f + 2d38: 32337663 bgeu t1,gp,3064 <_start-0x7fffcf9c> + 2d3c: 752d lui a0,0xfffeb + 2d3e: 6b6e flw fs6,216(sp) + 2d40: 6f6e flw ft10,216(sp) + 2d42: 652d6e77 0x652d6e77 + 2d46: 666c flw fa1,76(a2) + 2d48: 636e692f 0x636e692f + 2d4c: 756c flw fa1,108(a0) + 2d4e: 6564 flw fs1,76(a0) + 2d50: 7379732f 0x7379732f + 2d54: 2f00 fld fs0,24(a4) + 2d56: 6f68 flw fa0,92(a4) + 2d58: 656d lui a0,0x1b + 2d5a: 616c622f 0x616c622f + 2d5e: 7369 lui t1,0xffffa + 2d60: 2f65 jal 3518 <_start-0x7fffcae8> + 2d62: 6564 flw fs1,76(a0) + 2d64: 2f76 fld ft10,344(sp) + 2d66: 6972 flw fs2,28(sp) + 2d68: 2d766373 csrrsi t1,0x2d7,12 + 2d6c: 2d756e67 0x2d756e67 + 2d70: 6f74 flw fa3,92(a4) + 2d72: 68636c6f jal s8,393f8 <_start-0x7ffc6c08> + 2d76: 6961 lui s2,0x18 + 2d78: 326e fld ft4,248(sp) + 2d7a: 6f72642f 0x6f72642f + 2d7e: 7370 flw fa2,100(a4) + 2d80: 7369722f 0x7369722f + 2d84: 32337663 bgeu t1,gp,30b0 <_start-0x7fffcf50> + 2d88: 752d lui a0,0xfffeb + 2d8a: 6b6e flw fs6,216(sp) + 2d8c: 6f6e flw ft10,216(sp) + 2d8e: 652d6e77 0x652d6e77 + 2d92: 666c flw fa1,76(a2) + 2d94: 636e692f 0x636e692f + 2d98: 756c flw fa1,108(a0) + 2d9a: 6564 flw fs1,76(a0) + 2d9c: 2e00 fld fs0,24(a2) + 2d9e: 2f2e fld ft10,200(sp) + 2da0: 2e2e fld ft8,200(sp) + 2da2: 2f2e2e2f 0x2f2e2e2f + 2da6: 2e2e fld ft8,200(sp) + 2da8: 7369722f 0x7369722f + 2dac: 672d7663 bgeu s10,s2,3418 <_start-0x7fffcbe8> + 2db0: 6c2f6363 bltu t5,sp,3476 <_start-0x7fffcb8a> + 2db4: 6269 lui tp,0x1a + 2db6: 2f636367 0x2f636367 + 2dba: 2e2e fld ft8,200(sp) + 2dbc: 636e692f 0x636e692f + 2dc0: 756c flw fa1,108(a0) + 2dc2: 6564 flw fs1,76(a0) + 2dc4: 2e00 fld fs0,24(a2) + 2dc6: 2f2e fld ft10,200(sp) + 2dc8: 2e2e fld ft8,200(sp) + 2dca: 2f2e2e2f 0x2f2e2e2f + 2dce: 2e2e fld ft8,200(sp) + 2dd0: 7369722f 0x7369722f + 2dd4: 672d7663 bgeu s10,s2,3440 <_start-0x7fffcbc0> + 2dd8: 6c2f6363 bltu t5,sp,349e <_start-0x7fffcb62> + 2ddc: 6269 lui tp,0x1a + 2dde: 2f636367 0x2f636367 + 2de2: 2e2e fld ft8,200(sp) + 2de4: 6363672f 0x6363672f + 2de8: 6e6f632f 0x6e6f632f + 2dec: 6966 flw fs2,88(sp) + 2dee: 69722f67 0x69722f67 + 2df2: 00766373 csrrsi t1,0x7,12 + 2df6: 2e2e fld ft8,200(sp) + 2df8: 2f2e2e2f 0x2f2e2e2f + 2dfc: 2f2e fld ft10,200(sp) + 2dfe: 00636367 0x636367 + 2e02: 2e2e fld ft8,200(sp) + 2e04: 2f2e2e2f 0x2f2e2e2f + 2e08: 2e2e fld ft8,200(sp) + 2e0a: 2f2e2e2f 0x2f2e2e2f + 2e0e: 6972 flw fs2,28(sp) + 2e10: 2d766373 csrrsi t1,0x2d7,12 + 2e14: 2f636367 0x2f636367 + 2e18: 696c flw fa1,84(a0) + 2e1a: 6762 flw fa4,24(sp) + 2e1c: 00006363 bltu zero,zero,2e22 <_start-0x7fffd1de> + 2e20: 64647473 csrrci s0,0x646,8 + 2e24: 6665 lui a2,0x19 + 2e26: 682e flw fa6,200(sp) + 2e28: 0100 addi s0,sp,128 + 2e2a: 0000 unimp + 2e2c: 745f 7079 7365 0x73657079745f + 2e32: 682e flw fa6,200(sp) + 2e34: 0200 addi s0,sp,256 + 2e36: 0000 unimp + 2e38: 6572 flw fa0,28(sp) + 2e3a: 6e65 lui t3,0x19 + 2e3c: 2e74 fld fa3,216(a2) + 2e3e: 0068 addi a0,sp,12 + 2e40: 0002 c.slli64 zero + 2e42: 6c00 flw fs0,24(s0) + 2e44: 2e6b636f jal t1,b912a <_start-0x7ff46ed6> + 2e48: 0068 addi a0,sp,12 + 2e4a: 0002 c.slli64 zero + 2e4c: 6500 flw fs0,8(a0) + 2e4e: 7272 flw ft4,60(sp) + 2e50: 6f6e flw ft10,216(sp) + 2e52: 682e flw fa6,200(sp) + 2e54: 0200 addi s0,sp,256 + 2e56: 0000 unimp + 2e58: 6c647473 csrrci s0,0x6c6,8 + 2e5c: 6269 lui tp,0x1a + 2e5e: 682e flw fa6,200(sp) + 2e60: 0300 addi s0,sp,384 + 2e62: 0000 unimp + 2e64: 6e75 lui t3,0x1d + 2e66: 7369 lui t1,0xffffa + 2e68: 6474 flw fa3,76(s0) + 2e6a: 682e flw fa6,200(sp) + 2e6c: 0200 addi s0,sp,256 + 2e6e: 0000 unimp + 2e70: 6974 flw fa3,84(a0) + 2e72: 656d lui a0,0x1b + 2e74: 682e flw fa6,200(sp) + 2e76: 0300 addi s0,sp,384 + 2e78: 0000 unimp + 2e7a: 6168 flw fa0,68(a0) + 2e7c: 61746873 csrrsi a6,0x617,8 + 2e80: 2e62 fld ft8,24(sp) + 2e82: 0068 addi a0,sp,12 + 2e84: 0004 0x4 + 2e86: 7200 flw fs0,32(a2) + 2e88: 7369 lui t1,0xffffa + 2e8a: 6f2d7663 bgeu s10,s2,3576 <_start-0x7fffca8a> + 2e8e: 7470 flw fa2,108(s0) + 2e90: 00682e73 csrrs t3,0x6,a6 + 2e94: 0005 c.nop 1 + 2e96: 6900 flw fs0,16(a0) + 2e98: 736e flw ft6,248(sp) + 2e9a: 2d6e fld fs10,216(sp) + 2e9c: 736e6f63 bltu t3,s6,35da <_start-0x7fffca26> + 2ea0: 6174 flw fa3,68(a0) + 2ea2: 746e flw fs0,248(sp) + 2ea4: 00682e73 csrrs t3,0x6,a6 + 2ea8: 0006 c.slli zero,0x1 + 2eaa: 6c00 flw fs0,24(s0) + 2eac: 6269 lui tp,0x1a + 2eae: 32636367 0x32636367 + 2eb2: 682e flw fa6,200(sp) + 2eb4: 0700 addi s0,sp,896 + 2eb6: 0000 unimp + 2eb8: 696c flw fa1,84(a0) + 2eba: 6762 flw fa4,24(sp) + 2ebc: 2e326363 bltu tp,gp,31a2 <_start-0x7fffce5e> + 2ec0: 00070063 beqz a4,2ec0 <_start-0x7fffd140> + ... + +Disassembly of section .debug_frame: + +00000000 <.debug_frame>: + 0: 000c 0xc + 2: 0000 unimp + 4: ffff 0xffff + 6: ffff 0xffff + 8: 7c010003 lb zero,1984(sp) + c: 0d01 addi s10,s10,0 + e: 0002 c.slli64 zero + 10: 002c addi a1,sp,8 + 12: 0000 unimp + 14: 0000 unimp + 16: 0000 unimp + 18: 0ee8 addi a0,sp,860 + 1a: 8000 0x8000 + 1c: 042c addi a1,sp,520 + 1e: 0000 unimp + 20: 0e44 addi s1,sp,788 + 22: 5010 lw a2,32(s0) + 24: 0492 slli s1,s1,0x4 + 26: 8960 0x8960 + 28: 88018103 lb sp,-1920(gp) # 800034e8 + 2c: 0302 c.slli64 t1 + 2e: 03bc addi a5,sp,456 + 30: c10a sw sp,128(sp) + 32: c844 sw s1,20(s0) + 34: c960 sw s0,84(a0) + 36: d244 sw s1,36(a2) + 38: 0e48 addi a0,sp,788 + 3a: 4400 lw s0,8(s0) + 3c: 0000000b 0xb + 40: 000c 0xc + 42: 0000 unimp + 44: ffff 0xffff + 46: ffff 0xffff + 48: 7c010003 lb zero,1984(sp) + 4c: 0d01 addi s10,s10,0 + 4e: 0002 c.slli64 zero + 50: 0038 addi a4,sp,8 + 52: 0000 unimp + 54: 0040 addi s0,sp,4 + 56: 0000 unimp + 58: 1314 addi a3,sp,416 + 5a: 8000 0x8000 + 5c: 032c addi a1,sp,392 + 5e: 0000 unimp + 60: 0e44 addi s1,sp,788 + 62: 4420 lw s0,72(s0) + 64: 0389 addi t2,t2,2 + 66: 9250 0x9250 + 68: 9304 0x9304 + 6a: 9405 srai s0,s0,0x21 + 6c: 5006 0x5006 + 6e: 0181 addi gp,gp,0 + 70: 0288 addi a0,sp,320 + 72: 0795 addi a5,a5,5 + 74: 0a021c03 lh s8,160(tp) # 1a0a0 <_start-0x7ffe5f60> + 78: 48c1 li a7,16 + 7a: 44c8 lw a0,12(s1) + 7c: 44c9 li s1,18 + 7e: 44d2 lw s1,20(sp) + 80: 44d444d3 0x44d444d3 + 84: 44d5 li s1,21 + 86: 000e c.slli zero,0x3 + 88: 0b44 addi s1,sp,404 + 8a: 0000 unimp + 8c: 000c 0xc + 8e: 0000 unimp + 90: ffff 0xffff + 92: ffff 0xffff + 94: 7c010003 lb zero,1984(sp) + 98: 0d01 addi s10,s10,0 + 9a: 0002 c.slli64 zero + 9c: 000c 0xc + 9e: 0000 unimp + a0: 008c addi a1,sp,64 + a2: 0000 unimp + a4: 1640 addi s0,sp,804 + a6: 8000 0x8000 + a8: 00b4 addi a3,sp,72 + aa: 0000 unimp + ac: 000c 0xc + ae: 0000 unimp + b0: ffff 0xffff + b2: ffff 0xffff + b4: 7c010003 lb zero,1984(sp) + b8: 0d01 addi s10,s10,0 + ba: 0002 c.slli64 zero + bc: 0034 addi a3,sp,8 + be: 0000 unimp + c0: 00ac addi a1,sp,72 + c2: 0000 unimp + c4: 16f4 addi a3,sp,876 + c6: 8000 0x8000 + c8: 02f8 addi a4,sp,332 + ca: 0000 unimp + cc: 0e44 addi s1,sp,788 + ce: 4420 lw s0,72(s0) + d0: 0492 slli s1,s1,0x4 + d2: 8950 0x8950 + d4: 94059303 lh t1,-1728(a1) + d8: 5006 0x5006 + da: 0181 addi gp,gp,0 + dc: 0288 addi a0,sp,320 + de: 0795 addi a5,a5,5 + e0: c102ac03 lw s8,-1008(t0) # 1946fc <_start-0x7fe6b904> + e4: c848 sw a0,20(s0) + e6: c944 sw s1,20(a0) + e8: d244 sw s1,36(a2) + ea: d344 sw s1,36(a4) + ec: d444 sw s1,44(s0) + ee: d544 sw s1,44(a0) + f0: 0e44 addi s1,sp,788 + f2: 0000 unimp + f4: 000c 0xc + f6: 0000 unimp + f8: ffff 0xffff + fa: ffff 0xffff + fc: 7c010003 lb zero,1984(sp) + 100: 0d01 addi s10,s10,0 + 102: 0002 c.slli64 zero + 104: 002c addi a1,sp,8 + 106: 0000 unimp + 108: 00f4 addi a3,sp,76 + 10a: 0000 unimp + 10c: 19ec addi a1,sp,252 + 10e: 8000 0x8000 + 110: 044c addi a1,sp,516 + 112: 0000 unimp + 114: 0e48 addi a0,sp,788 + 116: 6010 flw fa2,0(s0) + 118: 0389 addi t2,t2,2 + 11a: 0492 slli s1,s1,0x4 + 11c: 8150 0x8150 + 11e: 8801 andi s0,s0,0 + 120: 0302 c.slli64 t1 + 122: 03d0 addi a2,sp,452 + 124: c10a sw sp,128(sp) + 126: c844 sw s1,20(s0) + 128: c960 sw s0,84(a0) + 12a: d244 sw s1,36(a2) + 12c: 0e48 addi a0,sp,788 + 12e: 4400 lw s0,8(s0) + 130: 0000000b 0xb + 134: 000c 0xc + 136: 0000 unimp + 138: ffff 0xffff + 13a: ffff 0xffff + 13c: 7c010003 lb zero,1984(sp) + 140: 0d01 addi s10,s10,0 + 142: 0002 c.slli64 zero + 144: 000c 0xc + 146: 0000 unimp + 148: 0134 addi a3,sp,136 + 14a: 0000 unimp + 14c: 1e38 addi a4,sp,824 + 14e: 8000 0x8000 + 150: 0044 addi s1,sp,4 + 152: 0000 unimp + 154: 000c 0xc + 156: 0000 unimp + 158: ffff 0xffff + 15a: ffff 0xffff + 15c: 7c010003 lb zero,1984(sp) + 160: 0d01 addi s10,s10,0 + 162: 0002 c.slli64 zero + 164: 000c 0xc + 166: 0000 unimp + 168: 0154 addi a3,sp,132 + 16a: 0000 unimp + 16c: 1e7c addi a5,sp,828 + 16e: 8000 0x8000 + 170: 004c addi a1,sp,4 + ... + +Disassembly of section .debug_str: + +00000000 <.debug_str>: + 0: 465f 5f50 4150 0x41505f50465f + 6: 525f4b43 fmadd.d fs6,ft10,ft5,fa0,rmm + a: 5741 li a4,-16 + c: 315f 665f 6f6c 0x6f6c665f315f + 12: 5f00 lw s0,56(a4) + 14: 5046 0x5046 + 16: 505f 4341 5f4b 0x5f4b4341505f + 1c: 494d4553 0x494d4553 + 20: 4152 lw sp,20(sp) + 22: 5f545f57 0x5f545f57 + 26: 665f0073 0x665f0073 + 2a: 7865 lui a6,0xffff9 + 2c: 5f00 lw s0,56(a4) + 2e: 5046 0x5046 + 30: 505f 4341 5f4b 0x5f4b4341505f + 36: 494d4553 0x494d4553 + 3a: 4152 lw sp,20(sp) + 3c: 5f545f57 0x5f545f57 + 40: 465f0063 beq t5,t0,4a0 <_start-0x7ffffb60> + 44: 5f50 lw a2,60(a4) + 46: 4150 lw a2,4(a0) + 48: 535f4b43 fmadd.d fs6,ft10,fs5,fa0,rmm + 4c: 4d45 li s10,17 + 4e: 5249 li tp,-14 + 50: 5741 li a4,-16 + 52: 545f 665f 6100 0x6100665f545f + 58: 6464 flw fs1,76(s0) + 5a: 645f 6e6f 0065 0x656e6f645f + 60: 6e75 lui t3,0x1d + 62: 6e676973 csrrsi s2,0x6e6,14 + 66: 6465 lui s0,0x19 + 68: 6320 flw fs0,64(a4) + 6a: 6168 flw fa0,68(a0) + 6c: 0072 c.slli zero,0x1c + 6e: 465f 5f50 4e55 0x4e555f50465f + 74: 4150 lw a2,4(a0) + 76: 525f4b43 fmadd.d fs6,ft10,ft5,fa0,rmm + 7a: 5741 li a4,-16 + 7c: 315f 665f 6f6c 0x6f6c665f315f + 82: 5f00 lw s0,56(a4) + 84: 615f 6464 6673 0x66736464615f + 8a: 68730033 0x68730033 + 8e: 2074726f jal tp,47a94 <_start-0x7ffb856c> + 92: 6e75 lui t3,0x1d + 94: 6e676973 csrrsi s2,0x6e6,14 + 98: 6465 lui s0,0x19 + 9a: 6920 flw fs0,80(a0) + 9c: 746e flw fs0,248(sp) + 9e: 7300 flw fs0,32(a4) + a0: 6275 lui tp,0x1d + a2: 0031 c.nop 12 + a4: 32627573 csrrci a0,mhpmevent6,4 + a8: 7300 flw fs0,32(a4) + aa: 6275 lui tp,0x1d + ac: 465f0033 0x465f0033 + b0: 5f50 lw a2,60(a4) + b2: 4150 lw a2,4(a0) + b4: 535f4b43 fmadd.d fs6,ft10,fs5,fa0,rmm + b8: 4d45 li s10,17 + ba: 5249 li tp,-14 + bc: 5741 li a4,-16 + be: 545f 655f 6e00 0x6e00655f545f + c4: 006d726f jal tp,d70ca <_start-0x7ff28f36> + c8: 5155 li sp,-11 + ca: 7449 lui s0,0xffff2 + cc: 7079 c.lui zero,0xffffe + ce: 0065 c.nop 25 + d0: 5f5f 6c63 5f7a 0x5f7a6c635f5f + d6: 6174 flw fa3,68(a0) + d8: 0062 c.slli zero,0x18 + da: 7266 flw ft4,120(sp) + dc: 6361 lui t1,0x18 + de: 6c00 flw fs0,24(s0) + e0: 20676e6f jal t3,762e6 <_start-0x7ff89d1a> + e4: 6f6c flw fa1,92(a4) + e6: 676e flw fa4,216(sp) + e8: 7520 flw fs0,104(a0) + ea: 736e flw ft6,248(sp) + ec: 6769 lui a4,0x1a + ee: 656e flw fa0,216(sp) + f0: 2064 fld fs1,192(s0) + f2: 6e69 lui t3,0x1a + f4: 0074 addi a3,sp,12 + f6: 6d6f682f 0x6d6f682f + fa: 2f65 jal 8b2 <_start-0x7ffff74e> + fc: 6c62 flw fs8,24(sp) + fe: 6961 lui s2,0x18 + 100: 642f6573 csrrsi a0,0x642,30 + 104: 7665 lui a2,0xffff9 + 106: 7369722f 0x7369722f + 10a: 672d7663 bgeu s10,s2,776 <_start-0x7ffff88a> + 10e: 756e flw fa0,248(sp) + 110: 742d lui s0,0xfffeb + 112: 636c6f6f jal t5,c6748 <_start-0x7ff398b8> + 116: 6168 flw fa0,68(a0) + 118: 6e69 lui t3,0x1a + 11a: 2f32 fld ft10,264(sp) + 11c: 7562 flw fa0,56(sp) + 11e: 6c69 lui s8,0x1a + 120: 2f64 fld fs1,216(a4) + 122: 7562 flw fa0,56(sp) + 124: 6c69 lui s8,0x1a + 126: 2d64 fld fs1,216(a0) + 128: 2d636367 0x2d636367 + 12c: 656e flw fa0,216(sp) + 12e: 62696c77 0x62696c77 + 132: 732d lui t1,0xfffeb + 134: 6174 flw fa3,68(a0) + 136: 2f326567 0x2f326567 + 13a: 6972 flw fs2,28(sp) + 13c: 33766373 csrrsi t1,mhpmevent23,12 + 140: 2d32 fld fs10,264(sp) + 142: 6e75 lui t3,0x1d + 144: 776f6e6b 0x776f6e6b + 148: 2d6e fld fs10,216(sp) + 14a: 6c65 lui s8,0x19 + 14c: 2f66 fld ft10,88(sp) + 14e: 696c flw fa1,84(a0) + 150: 6762 flw fa4,24(sp) + 152: 73006363 bltu zero,a6,878 <_start-0x7ffff788> + 156: 6275 lui tp,0x1d + 158: 645f 6e6f 0065 0x656e6f645f + 15e: 465f 5f50 4441 0x44415f50465f + 164: 5f44 lw s1,60(a4) + 166: 4e49 li t3,18 + 168: 4554 lw a3,12(a0) + 16a: 4e52 lw t3,20(sp) + 16c: 4c41 li s8,16 + 16e: 645f 6669 0066 0x666669645f + 174: 6f6c flw fa1,92(a4) + 176: 676e flw fa4,216(sp) + 178: 6c20 flw fs0,88(s0) + 17a: 20676e6f jal t3,76380 <_start-0x7ff89c80> + 17e: 6e69 lui t3,0x1a + 180: 0074 addi a3,sp,12 + 182: 20554e47 fmsub.s ft8,fa0,ft5,ft4,rmm + 186: 20373143 fmadd.s ft2,fa4,ft3,ft4,rup + 18a: 2e39 jal 4a8 <_start-0x7ffffb58> + 18c: 2e32 fld ft8,264(sp) + 18e: 2030 fld fa2,64(s0) + 190: 6d2d lui s10,0xb + 192: 646f6d63 bltu t5,t1,7ec <_start-0x7ffff814> + 196: 6c65 lui s8,0x19 + 198: 6d3d lui s10,0xf + 19a: 6465 lui s0,0x19 + 19c: 6f6c flw fa1,92(a4) + 19e: 6d2d2077 0x6d2d2077 + 1a2: 646f6d63 bltu t5,t1,7fc <_start-0x7ffff804> + 1a6: 6c65 lui s8,0x19 + 1a8: 6d3d lui s10,0xf + 1aa: 6465 lui s0,0x19 + 1ac: 6f6c flw fa1,92(a4) + 1ae: 6d2d2077 0x6d2d2077 + 1b2: 7574 flw fa3,108(a0) + 1b4: 656e flw fa0,216(sp) + 1b6: 723d lui tp,0xfffef + 1b8: 656b636f jal t1,b680e <_start-0x7ff497f2> + 1bc: 2074 fld fa3,192(s0) + 1be: 6d2d lui s10,0xb + 1c0: 7261 lui tp,0xffff8 + 1c2: 723d6863 bltu s10,gp,8f2 <_start-0x7ffff70e> + 1c6: 3376 fld ft6,376(sp) + 1c8: 6932 flw fs2,12(sp) + 1ca: 206d jal 274 <_start-0x7ffffd8c> + 1cc: 6d2d lui s10,0xb + 1ce: 6261 lui tp,0x18 + 1d0: 3d69 jal 6a <_start-0x7fffff96> + 1d2: 6c69 lui s8,0x1a + 1d4: 3370 fld fa2,224(a4) + 1d6: 2032 fld ft0,264(sp) + 1d8: 672d lui a4,0xb + 1da: 2d20 fld fs0,88(a0) + 1dc: 2d20734f 0x2d20734f + 1e0: 2d20324f 0x2d20324f + 1e4: 2d20734f 0x2d20734f + 1e8: 6266 flw ft4,88(sp) + 1ea: 6975 lui s2,0x1d + 1ec: 646c flw fa1,76(s0) + 1ee: 6e69 lui t3,0x1a + 1f0: 696c2d67 0x696c2d67 + 1f4: 6762 flw fa4,24(sp) + 1f6: 2d206363 bltu zero,s2,4bc <_start-0x7ffffb44> + 1fa: 6e66 flw ft8,88(sp) + 1fc: 74732d6f jal s10,33142 <_start-0x7ffccebe> + 200: 6361 lui t1,0x18 + 202: 72702d6b 0x72702d6b + 206: 6365746f jal s0,5783c <_start-0x7ffa87c4> + 20a: 6f74 flw fa3,92(a4) + 20c: 2072 fld ft0,280(sp) + 20e: 662d lui a2,0xb + 210: 6976 flw fs2,92(sp) + 212: 69626973 csrrsi s2,0x696,4 + 216: 696c flw fa1,84(a0) + 218: 7974 flw fa3,116(a0) + 21a: 683d lui a6,0xf + 21c: 6469 lui s0,0x1a + 21e: 6564 flw fs1,76(a0) + 220: 006e c.slli zero,0x1b + 222: 465f 5f50 4441 0x44415f50465f + 228: 5f44 lw s1,60(a4) + 22a: 4e49 li t3,18 + 22c: 4554 lw a3,12(a0) + 22e: 4e52 lw t3,20(sp) + 230: 4c41 li s8,16 + 232: 655f 6964 6666 0x66666964655f + 238: 6200 flw fs0,0(a2) + 23a: 7469 lui s0,0xffffa + 23c: 2e2e0073 0x2e2e0073 + 240: 2f2e2e2f 0x2f2e2e2f + 244: 2e2e fld ft8,200(sp) + 246: 2f2e2e2f 0x2f2e2e2f + 24a: 6972 flw fs2,28(sp) + 24c: 2d766373 csrrsi t1,0x2d7,12 + 250: 2f636367 0x2f636367 + 254: 696c flw fa1,84(a0) + 256: 6762 flw fa4,24(sp) + 258: 732f6363 bltu t5,s2,97e <_start-0x7ffff682> + 25c: 2d74666f jal a2,46d32 <_start-0x7ffb92ce> + 260: 7066 flw ft0,120(sp) + 262: 6464612f 0x6464612f + 266: 2e336673 csrrsi a2,0x2e3,6 + 26a: 64610063 beq sp,t1,8aa <_start-0x7ffff756> + 26e: 3164 fld fs1,224(a0) + 270: 6100 flw fs0,0(a0) + 272: 6464 flw fs1,76(s0) + 274: 0032 c.slli zero,0xc + 276: 6461 lui s0,0x18 + 278: 3364 fld fs1,224(a4) + 27a: 5f00 lw s0,56(a4) + 27c: 5046 0x5046 + 27e: 555f 494e 4e4f 0x4e4f494e555f + 284: 535f 5300 7446 0x74465300535f + 28a: 7079 c.lui zero,0xffffe + 28c: 0065 c.nop 25 + 28e: 465f 5f50 4150 0x41505f50465f + 294: 535f4b43 fmadd.d fs6,ft10,fs5,fa0,rmm + 298: 4d45 li s10,17 + 29a: 5249 li tp,-14 + 29c: 5741 li a4,-16 + 29e: 695f 5f73 6974 0x69745f73695f + 2a4: 796e flw fs2,248(sp) + 2a6: 5f00 lw s0,56(a4) + 2a8: 7266 flw ft4,120(sp) + 2aa: 006d c.nop 27 + 2ac: 5f5f 3072 5f00 0x5f0030725f5f + 2b2: 715f 0030 5f5f 0x5f5f0030715f + 2b8: 3171 jal ffffff44 <__global_pointer$+0x7fffc2dc> + 2ba: 5f00 lw s0,56(a4) + 2bc: 725f 0031 465f 0x465f0031725f + 2c2: 5f50 lw a2,60(a4) + 2c4: 4150 lw a2,4(a0) + 2c6: 435f4b43 fmadd.d fs6,ft10,fs5,fs0,rmm + 2ca: 4e41 li t3,16 + 2cc: 43494e4f fnmadd.d ft8,fs2,fs4,fs0,rmm + 2d0: 4c41 li s8,16 + 2d2: 695f 5f73 6974 0x69745f73695f + 2d8: 796e flw fs2,248(sp) + 2da: 2e00 fld fs0,24(a2) + 2dc: 2f2e fld ft10,200(sp) + 2de: 2e2e fld ft8,200(sp) + 2e0: 2f2e2e2f 0x2f2e2e2f + 2e4: 2e2e fld ft8,200(sp) + 2e6: 7369722f 0x7369722f + 2ea: 672d7663 bgeu s10,s2,956 <_start-0x7ffff6aa> + 2ee: 6c2f6363 bltu t5,sp,9b4 <_start-0x7ffff64c> + 2f2: 6269 lui tp,0x1a + 2f4: 2f636367 0x2f636367 + 2f8: 74666f73 csrrsi t5,0x746,12 + 2fc: 662d lui a2,0xb + 2fe: 2f70 fld fa2,216(a4) + 300: 6964 flw fs1,84(a0) + 302: 7376 flw ft6,124(sp) + 304: 3366 fld ft6,120(sp) + 306: 632e flw ft6,200(sp) + 308: 5f00 lw s0,56(a4) + 30a: 5046 0x5046 + 30c: 505f 4341 5f4b 0x5f4b4341505f + 312: 4f4e4143 fmadd.q ft2,ft8,fs4,fs1,rmm + 316: 494e lw s2,208(sp) + 318: 5f4c4143 fmadd.q ft2,fs8,fs4,fa1,rmm + 31c: 5f54 lw a3,60(a4) + 31e: 0066 c.slli zero,0x19 + 320: 5f5f 3164 5f00 0x5f0031645f5f + 326: 645f 7669 6673 0x66737669645f + 32c: 465f0033 0x465f0033 + 330: 5f50 lw a2,60(a4) + 332: 4150 lw a2,4(a0) + 334: 435f4b43 fmadd.d fs6,ft10,fs5,fs0,rmm + 338: 4e41 li t3,16 + 33a: 43494e4f fnmadd.d ft8,fs2,fs4,fs0,rmm + 33e: 4c41 li s8,16 + 340: 545f 655f 5f00 0x5f00655f545f + 346: 5046 0x5046 + 348: 445f 5649 4d5f 0x4d5f5649445f + 34e: 4145 li sp,17 + 350: 5f54 lw a3,60(a4) + 352: 5f31 li t5,-20 + 354: 6475 lui s0,0x1d + 356: 7669 lui a2,0xffffa + 358: 6e5f 726f 5f6d 0x5f6d726f6e5f + 35e: 686e flw fa6,216(sp) + 360: 5f00 lw s0,56(a4) + 362: 5046 0x5046 + 364: 445f 5649 4d5f 0x4d5f5649445f + 36a: 4145 li sp,17 + 36c: 5f54 lw a3,60(a4) + 36e: 5f31 li t5,-20 + 370: 6475 lui s0,0x1d + 372: 7669 lui a2,0xffffa + 374: 6e5f 726f 5f6d 0x5f6d726f6e5f + 37a: 0072 c.slli zero,0x1c + 37c: 465f 5f50 4150 0x41505f50465f + 382: 435f4b43 fmadd.d fs6,ft10,fs5,fs0,rmm + 386: 4e41 li t3,16 + 388: 43494e4f fnmadd.d ft8,fs2,fs4,fs0,rmm + 38c: 4c41 li s8,16 + 38e: 545f 635f 5f00 0x5f00635f545f + 394: 5046 0x5046 + 396: 505f 4341 5f4b 0x5f4b4341505f + 39c: 4f4e4143 fmadd.q ft2,ft8,fs4,fs1,rmm + 3a0: 494e lw s2,208(sp) + 3a2: 5f4c4143 fmadd.q ft2,fs8,fs4,fa1,rmm + 3a6: 5f54 lw a3,60(a4) + 3a8: 5f5f0073 0x5f5f0073 + 3ac: 3064 fld fs1,224(s0) + 3ae: 5f00 lw s0,56(a4) + 3b0: 5046 0x5046 + 3b2: 445f 5649 4d5f 0x4d5f5649445f + 3b8: 4145 li sp,17 + 3ba: 5f54 lw a3,60(a4) + 3bc: 5f31 li t5,-20 + 3be: 6475 lui s0,0x1d + 3c0: 7669 lui a2,0xffffa + 3c2: 6e5f 726f 5f6d 0x5f6d726f6e5f + 3c8: 0071 c.nop 28 + 3ca: 465f 5f50 4944 0x49445f50465f + 3d0: 5f56 lw t5,116(sp) + 3d2: 454d li a0,19 + 3d4: 5441 li s0,-16 + 3d6: 315f 755f 6964 0x6964755f315f + 3dc: 5f76 lw t5,124(sp) + 3de: 6f6e flw ft10,216(sp) + 3e0: 6d72 flw fs10,28(sp) + 3e2: 795f 5f00 5046 0x50465f00795f + 3e8: 445f 5649 4d5f 0x4d5f5649445f + 3ee: 4145 li sp,17 + 3f0: 5f54 lw a3,60(a4) + 3f2: 5f31 li t5,-20 + 3f4: 6475 lui s0,0x1d + 3f6: 7669 lui a2,0xffffa + 3f8: 6e5f 726f 5f6d 0x5f6d726f6e5f + 3fe: 6c6e flw fs8,216(sp) + 400: 5f00 lw s0,56(a4) + 402: 5046 0x5046 + 404: 555f 504e 4341 0x4341504e555f + 40a: 41435f4b fnmsub.s ft10,ft6,fs4,fs0,unknown + 40e: 4f4e lw t5,208(sp) + 410: 494e lw s2,208(sp) + 412: 5f4c4143 fmadd.q ft2,fs8,fs4,fa1,rmm + 416: 66696873 csrrsi a6,0x666,18 + 41a: 0074 addi a3,sp,12 + 41c: 5f5f 6367 5f63 0x5f6363675f5f + 422: 74504d43 0x74504d43 + 426: 7079 c.lui zero,0xffffe + 428: 0065 c.nop 25 + 42a: 465f 5f50 5349 0x53495f50465f + 430: 4e474953 0x4e474953 + 434: 4e41 li t3,16 + 436: 725f 7465 5f00 0x5f007465725f + 43c: 6c5f 7365 3266 0x326673656c5f + 442: 2e00 fld fs0,24(a2) + 444: 2f2e fld ft10,200(sp) + 446: 2e2e fld ft8,200(sp) + 448: 2f2e2e2f 0x2f2e2e2f + 44c: 2e2e fld ft8,200(sp) + 44e: 7369722f 0x7369722f + 452: 672d7663 bgeu s10,s2,abe <_start-0x7ffff542> + 456: 6c2f6363 bltu t5,sp,b1c <_start-0x7ffff4e4> + 45a: 6269 lui tp,0x1a + 45c: 2f636367 0x2f636367 + 460: 74666f73 csrrsi t5,0x746,12 + 464: 662d lui a2,0xb + 466: 2f70 fld fa2,216(a4) + 468: 656c flw fa1,76(a0) + 46a: 2e326673 csrrsi a2,0x2e3,4 + 46e: 465f0063 beq t5,t0,8ce <_start-0x7ffff732> + 472: 5f50 lw a2,60(a4) + 474: 5f504d43 fmadd.q fs10,ft0,fs5,fa1,rmm + 478: 7369 lui t1,0xffffa + 47a: 7a5f 7265 5f6f 0x5f6f72657a5f + 480: 0078 addi a4,sp,12 + 482: 465f 5f50 4d43 0x4d435f50465f + 488: 5f50 lw a2,60(a4) + 48a: 7369 lui t1,0xffffa + 48c: 7a5f 7265 5f6f 0x5f6f72657a5f + 492: 0079 c.nop 30 + 494: 465f 5f50 554d 0x554d5f50465f + 49a: 5f4c lw a1,60(a4) + 49c: 454d li a0,19 + 49e: 5441 li s0,-16 + 4a0: 315f 775f 6469 0x6469775f315f + 4a6: 5f65 li t5,-7 + 4a8: 5f5a lw t5,180(sp) + 4aa: 3066 fld ft0,120(sp) + 4ac: 5f00 lw s0,56(a4) + 4ae: 5046 0x5046 + 4b0: 4d5f 4c55 4d5f 0x4d5f4c554d5f + 4b6: 4145 li sp,17 + 4b8: 5f54 lw a3,60(a4) + 4ba: 5f31 li t5,-20 + 4bc: 65646977 0x65646977 + 4c0: 5a5f 665f 0031 0x31665f5a5f + 4c6: 5f5f 6875 5f00 0x5f0068755f5f + 4cc: 755f 006c 4855 0x4855006c755f + 4d2: 70797457 0x70797457 + 4d6: 0065 c.nop 25 + 4d8: 5f5f 3078 2e00 0x2e0030785f5f + 4de: 2f2e fld ft10,200(sp) + 4e0: 2e2e fld ft8,200(sp) + 4e2: 2f2e2e2f 0x2f2e2e2f + 4e6: 2e2e fld ft8,200(sp) + 4e8: 7369722f 0x7369722f + 4ec: 672d7663 bgeu s10,s2,b58 <_start-0x7ffff4a8> + 4f0: 6c2f6363 bltu t5,sp,bb6 <_start-0x7ffff44a> + 4f4: 6269 lui tp,0x1a + 4f6: 2f636367 0x2f636367 + 4fa: 74666f73 csrrsi t5,0x746,12 + 4fe: 662d lui a2,0xb + 500: 2f70 fld fa2,216(a4) + 502: 756d lui a0,0xffffb + 504: 736c flw fa1,100(a4) + 506: 3366 fld ft6,120(sp) + 508: 632e flw ft6,200(sp) + 50a: 5f00 lw s0,56(a4) + 50c: 785f 0031 5f5f 0x5f5f0031785f + 512: 3278 fld fa4,224(a2) + 514: 5f00 lw s0,56(a4) + 516: 785f 0033 5f5f 0x5f5f0033785f + 51c: 6876 flw fa6,92(sp) + 51e: 5f00 lw s0,56(a4) + 520: 765f 006c 5f5f 0x5f5f006c765f + 526: 756d lui a0,0xffffb + 528: 736c flw fa1,100(a4) + 52a: 3366 fld ft6,120(sp) + 52c: 2e00 fld fs0,24(a2) + 52e: 2f2e fld ft10,200(sp) + 530: 2e2e fld ft8,200(sp) + 532: 2f2e2e2f 0x2f2e2e2f + 536: 2e2e fld ft8,200(sp) + 538: 7369722f 0x7369722f + 53c: 672d7663 bgeu s10,s2,ba8 <_start-0x7ffff458> + 540: 6c2f6363 bltu t5,sp,c06 <_start-0x7ffff3fa> + 544: 6269 lui tp,0x1a + 546: 2f636367 0x2f636367 + 54a: 74666f73 csrrsi t5,0x746,12 + 54e: 662d lui a2,0xb + 550: 2f70 fld fa2,216(a4) + 552: 73627573 csrrci a0,0x736,4 + 556: 3366 fld ft6,120(sp) + 558: 632e flw ft6,200(sp) + 55a: 5f00 lw s0,56(a4) + 55c: 735f 6275 6673 0x66736275735f + 562: 2e2e0033 0x2e2e0033 + 566: 2f2e2e2f 0x2f2e2e2f + 56a: 2e2e fld ft8,200(sp) + 56c: 2f2e2e2f 0x2f2e2e2f + 570: 6972 flw fs2,28(sp) + 572: 2d766373 csrrsi t1,0x2d7,12 + 576: 2f636367 0x2f636367 + 57a: 696c flw fa1,84(a0) + 57c: 6762 flw fa4,24(sp) + 57e: 732f6363 bltu t5,s2,ca4 <_start-0x7ffff35c> + 582: 2d74666f jal a2,47058 <_start-0x7ffb8fa8> + 586: 7066 flw ft0,120(sp) + 588: 6f6e752f 0x6f6e752f + 58c: 6472 flw fs0,28(sp) + 58e: 2e326673 csrrsi a2,0x2e3,4 + 592: 5f5f0063 beq t5,s5,b72 <_start-0x7ffff48e> + 596: 6e75 lui t3,0x1d + 598: 7364726f jal tp,47cce <_start-0x7ffb8332> + 59c: 3266 fld ft4,120(sp) + 59e: 7300 flw fs0,32(a4) + 5a0: 6f68 flw fa0,92(a4) + 5a2: 7472 flw fs0,60(sp) + 5a4: 6920 flw fs0,80(a0) + 5a6: 746e flw fs0,248(sp) + 5a8: 6800 flw fs0,16(s0) + 5aa: 6174 flw fa3,68(a0) + 5ac: 5f62 lw t5,56(sp) + 5ae: 6168 flw fa0,68(a0) + 5b0: 705f6873 csrrsi a6,0x705,30 + 5b4: 746e696f jal s2,e6cfa <_start-0x7ff19306> + 5b8: 7265 lui tp,0xffff9 + 5ba: 5f00 lw s0,56(a4) + 5bc: 657a6973 csrrsi s2,0x657,20 + 5c0: 5f00 lw s0,56(a4) + 5c2: 6172 flw ft2,28(sp) + 5c4: 646e flw fs0,216(sp) + 5c6: 3834 fld fa3,112(s0) + 5c8: 5f00 lw s0,56(a4) + 5ca: 6d65 lui s10,0x19 + 5cc: 7265 lui tp,0xffff9 + 5ce: 636e6567 0x636e6567 + 5d2: 0079 c.nop 30 + 5d4: 645f 7961 696c 0x696c7961645f + 5da: 00746867 0x746867 + 5de: 706d6f63 bltu s10,t1,cfc <_start-0x7ffff304> + 5e2: 656c flw fa1,76(a0) + 5e4: 2078 fld fa4,192(s0) + 5e6: 6f64 flw fs1,92(a4) + 5e8: 6275 lui tp,0x1d + 5ea: 656c flw fa1,76(a0) + 5ec: 5f00 lw s0,56(a4) + 5ee: 64746567 0x64746567 + 5f2: 7461 lui s0,0xffff8 + 5f4: 5f65 li t5,-7 + 5f6: 7265 lui tp,0xffff9 + 5f8: 0072 c.slli zero,0x1c + 5fa: 645f 7461 0061 0x617461645f + 600: 775f 7263 6f74 0x6f747263775f + 606: 626d lui tp,0x1b + 608: 735f 6174 6574 0x65746174735f + 60e: 7200 flw fs0,32(a2) + 610: 7369 lui t1,0xffffa + 612: 6d5f7663 bgeu t5,s5,cde <_start-0x7ffff322> + 616: 6369 lui t1,0x1a + 618: 6f72 flw ft10,28(sp) + 61a: 7261 lui tp,0xffff8 + 61c: 74696863 bltu s2,t1,d6c <_start-0x7ffff294> + 620: 6365 lui t1,0x19 + 622: 7574 flw fa3,108(a0) + 624: 6572 flw fa0,28(sp) + 626: 745f 7079 0065 0x657079745f + 62c: 775f 7363 7472 0x74727363775f + 632: 73626d6f jal s10,26d68 <_start-0x7ffd9298> + 636: 735f 6174 6574 0x65746174735f + 63c: 5f00 lw s0,56(a4) + 63e: 626c flw fa1,68(a2) + 640: 7366 flw ft6,120(sp) + 642: 7a69 lui s4,0xffffa + 644: 0065 c.nop 25 + 646: 706d6f63 bltu s10,t1,d64 <_start-0x7ffff29c> + 64a: 656c flw fa1,76(a0) + 64c: 2078 fld fa4,192(s0) + 64e: 6f6c flw fa1,92(a4) + 650: 676e flw fa4,216(sp) + 652: 6420 flw fs0,72(s0) + 654: 6c62756f jal a0,27d1a <_start-0x7ffd82e6> + 658: 0065 c.nop 25 + 65a: 6972 flw fs2,28(sp) + 65c: 5f766373 csrrsi t1,0x5f7,12 + 660: 6261 lui tp,0x18 + 662: 0069 c.nop 26 + 664: 5f5f 6f6c 6163 0x61636f6c5f5f + 66a: 656c flw fa1,76(a0) + 66c: 745f 5f00 626d 0x626d5f00745f + 672: 7472 flw fs0,60(sp) + 674: 5f63776f jal a4,37c6a <_start-0x7ffc8396> + 678: 74617473 csrrci s0,0x746,2 + 67c: 0065 c.nop 25 + 67e: 745f 6e7a 6d61 0x6d616e7a745f + 684: 0065 c.nop 25 + 686: 775f 7463 6d6f 0x6d6f7463775f + 68c: 5f62 lw t5,56(sp) + 68e: 74617473 csrrci s0,0x746,2 + 692: 0065 c.nop 25 + 694: 5f5f 6d74 735f 0x735f6d745f5f + 69a: 6365 lui t1,0x19 + 69c: 5f00 lw s0,56(a4) + 69e: 736f6c63 bltu t5,s6,dd6 <_start-0x7ffff22a> + 6a2: 0065 c.nop 25 + 6a4: 755f 7562 0066 0x667562755f + 6aa: 625f 7361 0065 0x657361625f + 6b0: 5f5f 6d74 685f 0x685f6d745f5f + 6b6: 0072756f jal a0,27ebc <_start-0x7ffd8144> + 6ba: 6e75 lui t3,0x1d + 6bc: 63657073 csrci 0x636,10 + 6c0: 5f76 lw t5,124(sp) + 6c2: 69727473 csrrci s0,0x697,4 + 6c6: 676e flw fa4,216(sp) + 6c8: 5f5f0073 0x5f5f0073 + 6cc: 5f006673 csrrsi a2,0x5f0,0 + 6d0: 655f6e6f jal t3,f7524 <_start-0x7ff08adc> + 6d4: 6978 flw fa4,84(a0) + 6d6: 5f74 lw a3,124(a4) + 6d8: 7261 lui tp,0xffff8 + 6da: 5f007367 0x5f007367 + 6de: 6b6f6f63 bltu t5,s6,d9c <_start-0x7ffff264> + 6e2: 6569 lui a0,0x1a + 6e4: 5f00 lw s0,56(a4) + 6e6: 735f 6c67 6575 0x65756c67735f + 6ec: 5f00 lw s0,56(a4) + 6ee: 6c66 flw fs8,88(sp) + 6f0: 6761 lui a4,0x18 + 6f2: 695f0073 0x695f0073 + 6f6: 78635f73 csrrwi t5,0x786,6 + 6fa: 0061 c.nop 24 + 6fc: 775f 7364 5f00 0x5f007364775f + 702: 465f 4c49 0045 0x454c49465f + 708: 725f 7365 6c75 0x6c757365725f + 70e: 5f74 lw a3,124(a4) + 710: 5355006b 0x5355006b + 714: 7449 lui s0,0xffff2 + 716: 7079 c.lui zero,0xffffe + 718: 0065 c.nop 25 + 71a: 6972 flw fs2,28(sp) + 71c: 5f766373 csrrsi t1,0x5f7,12 + 720: 696d lui s2,0x1b + 722: 616f7263 bgeu t5,s6,d26 <_start-0x7ffff2da> + 726: 6372 flw ft6,28(sp) + 728: 6968 flw fa0,84(a0) + 72a: 6574 flw fa3,76(a0) + 72c: 72757463 bgeu a0,t2,e54 <_start-0x7ffff1ac> + 730: 0065 c.nop 25 + 732: 735f 7379 655f 0x655f7379735f + 738: 7272 flw ft4,60(sp) + 73a: 696c flw fa1,84(a0) + 73c: 5f007473 csrrci s0,0x5f0,0 + 740: 62747663 bgeu s0,t2,d6c <_start-0x7ffff294> + 744: 6675 lui a2,0x1d + 746: 5f00 lw s0,56(a4) + 748: 626d lui tp,0x1b + 74a: 6f747273 csrrci tp,0x6f7,8 + 74e: 5f736377 0x5f736377 + 752: 74617473 csrrci s0,0x746,2 + 756: 0065 c.nop 25 + 758: 6d5f 7262 656c 0x656c72626d5f + 75e: 5f6e lw t5,248(sp) + 760: 74617473 csrrci s0,0x746,2 + 764: 0065 c.nop 25 + 766: 6972 flw fs2,28(sp) + 768: 5f766373 csrrsi t1,0x5f7,12 + 76c: 646f6d63 bltu t5,t1,dc6 <_start-0x7ffff23a> + 770: 6c65 lui s8,0x19 + 772: 5f00 lw s0,56(a4) + 774: 6e66 flw ft8,88(sp) + 776: 7261 lui tp,0xffff8 + 778: 5f007367 0x5f007367 + 77c: 6e66 flw ft8,88(sp) + 77e: 735f0073 0x735f0073 + 782: 6769 lui a4,0x1a + 784: 006e c.slli zero,0x1b + 786: 735f 6474 7265 0x72656474735f + 78c: 0072 c.slli zero,0x1c + 78e: 425f 6769 6e69 0x6e696769425f + 794: 0074 addi a3,sp,12 + 796: 675f 6d61 616d 0x616d6d61675f + 79c: 735f 6769 676e 0x676e6769735f + 7a2: 6d61 lui s10,0x18 + 7a4: 5f00 lw s0,56(a4) + 7a6: 6d6e flw fs10,216(sp) + 7a8: 6c61 lui s8,0x18 + 7aa: 6f6c flw fa1,92(a4) + 7ac: 5f5f0063 beq t5,s5,d8c <_start-0x7ffff274> + 7b0: 6d74 flw fa3,92(a0) + 7b2: 7200 flw fs0,32(a2) + 7b4: 7369 lui t1,0xffffa + 7b6: 615f7663 bgeu t5,s5,dc2 <_start-0x7ffff23e> + 7ba: 6962 flw fs2,24(sp) + 7bc: 745f 7079 0065 0x657079745f + 7c2: 6d5f 7362 6174 0x617473626d5f + 7c8: 6574 flw fa3,76(a0) + 7ca: 5f00 lw s0,56(a4) + 7cc: 775f 6863 0062 0x626863775f + 7d2: 635f 7476 656c 0x656c7476635f + 7d8: 006e c.slli zero,0x1b + 7da: 665f 6c69 0065 0x656c69665f + 7e0: 6168 flw fa0,68(a0) + 7e2: 61766873 csrrsi a6,0x617,12 + 7e6: 5f6c lw a1,124(a4) + 7e8: 0074 addi a3,sp,12 + 7ea: 6e5f 6f69 7362 0x73626f696e5f + 7f0: 5f00 lw s0,56(a4) + 7f2: 635f 7a6c 6973 0x69737a6c635f + 7f8: 0032 c.slli zero,0xc + 7fa: 615f 6574 6978 0x69786574615f + 800: 3074 fld fa3,224(s0) + 802: 5f00 lw s0,56(a4) + 804: 6e676973 csrrsi s2,0x6e6,14 + 808: 6c61 lui s8,0x18 + 80a: 625f 6675 5f00 0x5f006675625f + 810: 7361 lui t1,0xffff8 + 812: 6d697463 bgeu s2,s6,eda <_start-0x7ffff126> + 816: 5f65 li t5,-7 + 818: 7562 flw fa0,56(sp) + 81a: 0066 c.slli zero,0x19 + 81c: 725f 7365 6c75 0x6c757365725f + 822: 0074 addi a3,sp,12 + 824: 5f5f 6377 0068 0x6863775f5f + 82a: 6e65 lui t3,0x19 + 82c: 6976 flw fs2,92(sp) + 82e: 6f72 flw ft10,28(sp) + 830: 006e c.slli zero,0x1b + 832: 746e6977 0x746e6977 + 836: 745f 5f00 6f6c 0x6f6c5f00745f + 83c: 41006b63 bltu zero,a6,c52 <_start-0x7ffff3ae> + 840: 4942 lw s2,16(sp) + 842: 495f 504c 3233 0x3233504c495f + 848: 0044 addi s1,sp,4 + 84a: 4241 li tp,16 + 84c: 5f49 li t5,-14 + 84e: 4c49 li s8,18 + 850: 3350 fld fa2,160(a4) + 852: 4532 lw a0,12(sp) + 854: 5f00 lw s0,56(a4) + 856: 756d lui a0,0xffffb + 858: 746c flw fa1,108(s0) + 85a: 7500 flw fs0,40(a0) + 85c: 736e flw ft6,248(sp) + 85e: 6570 flw fa2,76(a0) + 860: 74735f63 bge t1,t2,fbe <_start-0x7ffff042> + 864: 6972 flw fs2,28(sp) + 866: 676e flw fa4,216(sp) + 868: 706f0073 0x706f0073 + 86c: 7274 flw fa3,100(a2) + 86e: 7365 lui t1,0xffff9 + 870: 7465 lui s0,0xffff9 + 872: 5f00 lw s0,56(a4) + 874: 74697277 0x74697277 + 878: 0065 c.nop 25 + 87a: 5f5f 6d74 795f 0x795f6d745f5f + 880: 6165 addi sp,sp,112 + 882: 0072 c.slli zero,0x1c + 884: 4241 li tp,16 + 886: 5f49 li t5,-14 + 888: 4c49 li s8,18 + 88a: 3350 fld fa2,160(a4) + 88c: 4632 lw a2,12(sp) + 88e: 5f00 lw s0,56(a4) + 890: 6e75 lui t3,0x1d + 892: 7375 lui t1,0xffffd + 894: 6465 lui s0,0x19 + 896: 725f 6e61 0064 0x646e61725f + 89c: 6972 flw fs2,28(sp) + 89e: 5f766373 csrrsi t1,0x5f7,12 + 8a2: 65646f63 bltu s0,s6,f00 <_start-0x7ffff100> + 8a6: 6d5f 646f 6c65 0x6c65646f6d5f + 8ac: 5f00 lw s0,56(a4) + 8ae: 7366666f jal a2,66fe4 <_start-0x7ff9901c> + 8b2: 7465 lui s0,0xffff9 + 8b4: 6f00 flw fs0,24(a4) + 8b6: 7470 flw fa2,108(s0) + 8b8: 6e69 lui t3,0x1a + 8ba: 0064 addi s1,sp,12 + 8bc: 6e5f 7865 6674 0x667478656e5f + 8c2: 6300 flw fs0,0(a4) + 8c4: 6c706d6f jal s10,778a <_start-0x7fff8876> + 8c8: 7865 lui a6,0xffff9 + 8ca: 6620 flw fs0,72(a2) + 8cc: 6f6c flw fa1,92(a4) + 8ce: 7461 lui s0,0xffff8 + 8d0: 5f00 lw s0,56(a4) + 8d2: 745f 5f6d 6f6d 0x6f6d5f6d745f + 8d8: 006e c.slli zero,0x1b + 8da: 615f 6574 6978 0x69786574615f + 8e0: 0074 addi a3,sp,12 + 8e2: 6f627573 csrrci a0,0x6f6,4 + 8e6: 7470 flw fa2,108(s0) + 8e8: 7261 lui tp,0xffff8 + 8ea: 5f5f0067 jr 1525(t5) + 8ee: 64696473 csrrsi s0,0x646,18 + 8f2: 6e69 lui t3,0x1a + 8f4: 7469 lui s0,0xffffa + 8f6: 5f00 lw s0,56(a4) + 8f8: 5f66666f jal a2,66eee <_start-0x7ff99112> + 8fc: 0074 addi a3,sp,12 + 8fe: 665f 6572 6c65 0x6c656572665f + 904: 7369 lui t1,0xffffa + 906: 0074 addi a3,sp,12 + 908: 745f 6d69 7a65 0x7a656d69745f + 90e: 00656e6f jal t3,56914 <_start-0x7ffa96ec> + 912: 6d5f 7362 6174 0x617473626d5f + 918: 6574 flw fa3,76(a0) + 91a: 745f 5f00 4f4c 0x4f4c5f00745f + 920: 525f4b43 fmadd.d fs6,ft10,ft5,fa0,rmm + 924: 4345 li t1,17 + 926: 5255 li tp,-11 + 928: 45564953 0x45564953 + 92c: 545f 5f00 6572 0x65725f00545f + 932: 6461 lui s0,0x18 + 934: 2e00 fld fs0,24(a2) + 936: 2f2e fld ft10,200(sp) + 938: 2e2e fld ft8,200(sp) + 93a: 2f2e2e2f 0x2f2e2e2f + 93e: 2e2e fld ft8,200(sp) + 940: 7369722f 0x7369722f + 944: 672d7663 bgeu s10,s2,fb0 <_start-0x7ffff050> + 948: 6c2f6363 bltu t5,sp,100e <_start-0x7fffeff2> + 94c: 6269 lui tp,0x1a + 94e: 2f636367 0x2f636367 + 952: 696c flw fa1,84(a0) + 954: 6762 flw fa4,24(sp) + 956: 2e326363 bltu tp,gp,c3c <_start-0x7ffff3c4> + 95a: 42410063 beq sp,tp,d7a <_start-0x7ffff286> + 95e: 5f49 li t5,-14 + 960: 504c lw a1,36(s0) + 962: 3436 fld fs0,360(sp) + 964: 4100 lw s0,0(a0) + 966: 4942 lw s2,16(sp) + 968: 495f 504c 3233 0x3233504c495f + 96e: 5f00 lw s0,56(a4) + 970: 7364 flw fs1,100(a4) + 972: 61685f6f jal t5,85f88 <_start-0x7ff7a078> + 976: 646e flw fs0,216(sp) + 978: 656c flw fa1,76(a0) + 97a: 4300 lw s0,0(a4) + 97c: 5f4d li t5,-13 + 97e: 454d li a0,19 + 980: 4144 lw s1,4(a0) + 982: 594e lw s2,240(sp) + 984: 5f00 lw s0,56(a4) + 986: 656e flw fa0,216(sp) + 988: 685f0077 0x685f0077 + 98c: 655f 7272 6f6e 0x6f6e7272655f + 992: 5f00 lw s0,56(a4) + 994: 6c66 flw fs8,88(sp) + 996: 5f6b636f jal t1,b6f8c <_start-0x7ff49074> + 99a: 0074 addi a3,sp,12 + 99c: 5f5f 6d74 795f 0x795f6d745f5f + 9a2: 6164 flw fs1,68(a0) + 9a4: 0079 c.nop 30 + 9a6: 5f5f 6273 6675 0x667562735f5f + 9ac: 5f00 lw s0,56(a4) + 9ae: 6c66 flw fs8,88(sp) + 9b0: 6761 lui a4,0x18 + 9b2: 5f003273 csrrc tp,0x5f0,zero + 9b6: 6f69 lui t5,0x1a + 9b8: 7362 flw ft6,56(sp) + 9ba: 4300 lw s0,0(a4) + 9bc: 5f4d li t5,-13 + 9be: 454d li a0,19 + 9c0: 4c44 lw s1,28(s0) + 9c2: 6800574f fnmadd.s fa4,ft0,ft0,fa3,unknown + 9c6: 6174 flw fa3,68(a0) + 9c8: 5f62 lw t5,56(sp) + 9ca: 6168 flw fa0,68(a0) + 9cc: 5f006873 csrrsi a6,0x5f0,0 + 9d0: 735f 4946 454c 0x454c4946735f + 9d6: 5f00 lw s0,56(a4) + 9d8: 5f737973 csrrci s2,0x5f7,6 + 9dc: 656e flw fa0,216(sp) + 9de: 7272 flw ft4,60(sp) + 9e0: 5f00 lw s0,56(a4) + 9e2: 6172 flw ft2,28(sp) + 9e4: 646e flw fs0,216(sp) + 9e6: 6e5f 7865 0074 0x7478656e5f + 9ec: 6d5f 6c62 6e65 0x6e656c626d5f + 9f2: 735f 6174 6574 0x65746174735f + 9f8: 5f00 lw s0,56(a4) + 9fa: 6e69 lui t3,0x1a + 9fc: 695f0063 beq t5,s5,107c <_start-0x7fffef84> + a00: 646e flw fs0,216(sp) + a02: 5f00 lw s0,56(a4) + a04: 6f6c flw fa1,92(a4) + a06: 656c6163 bltu s8,s6,1048 <_start-0x7fffefb8> + a0a: 5f00 lw s0,56(a4) + a0c: 635f 656c 6e61 0x6e61656c635f + a12: 7075 c.lui zero,0xffffd + a14: 5f00 lw s0,56(a4) + a16: 6e75 lui t3,0x1d + a18: 63657073 csrci 0x636,10 + a1c: 6669 lui a2,0x1a + a1e: 6569 lui a0,0x1a + a20: 5f64 lw s1,124(a4) + a22: 6f6c flw fa1,92(a4) + a24: 656c6163 bltu s8,s6,1066 <_start-0x7fffef9a> + a28: 695f 666e 006f 0x6f666e695f + a2e: 6d5f 7861 6477 0x647778616d5f + a34: 725f0073 0x725f0073 + a38: 6565 lui a0,0x19 + a3a: 746e flw fs0,248(sp) + a3c: 5f00 lw s0,56(a4) + a3e: 64656573 csrrsi a0,0x646,10 + a42: 5f00 lw s0,56(a4) + a44: 635f 756f 746e 0x746e756f635f + a4a: 5f00 lw s0,56(a4) + a4c: 765f 6c61 6575 0x65756c61765f + a52: 5f00 lw s0,56(a4) + a54: 6b656573 csrrsi a0,0x6b6,10 + a58: 5f00 lw s0,56(a4) + a5a: 7066 flw ft0,120(sp) + a5c: 745f736f jal t1,f89a0 <_start-0x7ff07660> + a60: 7300 flw fs0,32(a4) + a62: 6669 lui a2,0x1a + a64: 7669 lui a2,0xffffa + a66: 5f65 li t5,-7 + a68: 625f0037 lui zero,0x625f0 + a6c: 6b6c flw fa1,84(a4) + a6e: 657a6973 csrrsi s2,0x657,20 + a72: 6700 flw fs0,8(a4) + a74: 6e65 lui t3,0x19 + a76: 7265 lui tp,0xffff9 + a78: 6369 lui t1,0x1a + a7a: 6f00 flw fs0,24(a4) + a7c: 7470 flw fa2,108(s0) + a7e: 7265 lui tp,0xffff9 + a80: 0072 c.slli zero,0x1c + a82: 735f 7274 6f74 0x6f747274735f + a88: 616c5f6b 0x616c5f6b + a8c: 43007473 csrrci s0,0x430,0 + a90: 5f4d li t5,-13 + a92: 4950 lw a2,20(a0) + a94: 665f0043 fmadd.q ft0,ft10,ft5,fa2,rne + a98: 746e flw fs0,248(sp) + a9a: 7079 c.lui zero,0xffffe + a9c: 7365 lui t1,0xffff9 + a9e: 5f00 lw s0,56(a4) + aa0: 6461 lui s0,0x18 + aa2: 0064 addi s1,sp,12 + aa4: 5f5f 4c55 6e6f 0x6e6f4c555f5f + aaa: 74680067 jr 1862(a6) # ffff9746 <__global_pointer$+0x7fff5ade> + aae: 6261 lui tp,0x18 + ab0: 655f 5f71 6f70 0x6f705f71655f + ab6: 6e69 lui t3,0x1a + ab8: 6574 flw fa3,76(a0) + aba: 0072 c.slli zero,0x1c + abc: 5f5f 7278 5f00 0x5f0072785f5f + ac2: 626f6c67 0x626f6c67 + ac6: 6c61 lui s8,0x18 + ac8: 695f 706d 7275 0x7275706d695f + ace: 5f65 li t5,-7 + ad0: 7470 flw fa2,108(s0) + ad2: 0072 c.slli zero,0x1c + ad4: 735f 6474 756f 0x756f6474735f + ada: 0074 addi a3,sp,12 + adc: 5f5f 6d74 775f 0x775f6d745f5f + ae2: 6164 flw fs1,68(a0) + ae4: 0079 c.nop 30 + ae6: 675f 756c 0065 0x65756c675f + aec: 735f 6474 6e69 0x6e696474735f + af2: 5f00 lw s0,56(a4) + af4: 7a697373 csrrci t1,0x7a6,18 + af8: 5f65 li t5,-7 + afa: 0074 addi a3,sp,12 + afc: 6c5f 3436 5f61 0x5f6134366c5f + b02: 7562 flw fa0,56(sp) + b04: 0066 c.slli zero,0x19 + b06: 735f 6769 665f 0x665f6769735f + b0c: 6e75 lui t3,0x1d + b0e: 5f5f0063 beq t5,s5,10ee <_start-0x7fffef12> + b12: 6f70 flw fa2,92(a4) + b14: 6370 flw fa2,68(a4) + b16: 746e756f jal a0,e825c <_start-0x7ff17da4> + b1a: 745f 6261 5f00 0x5f006261745f + b20: 626e flw ft4,216(sp) + b22: 6675 lui a2,0x1d + b24: 5f00 lw s0,56(a4) + b26: 6e75 lui t3,0x1d + b28: 7375 lui t1,0xffffd + b2a: 6465 lui s0,0x19 + b2c: 5f00 lw s0,56(a4) + b2e: 745f 5f6d 7369 0x73695f6d745f + b34: 7364 flw fs1,100(a4) + b36: 0074 addi a3,sp,12 + b38: 6c5f 636f 6c61 0x6c61636f6c5f + b3e: 6974 flw fa3,84(a0) + b40: 656d lui a0,0x1b + b42: 625f 6675 5f00 0x5f006675625f + b48: 745f 5f6d 696d 0x696d5f6d745f + b4e: 006e c.slli zero,0x1b + b50: 725f 3834 4100 0x41003834725f + b56: 4942 lw s2,16(sp) + b58: 4c5f 3650 4434 0x443436504c5f + b5e: 6f00 flw fs0,24(a4) + b60: 7470 flw fa2,108(s0) + b62: 0074706f j 48368 <_start-0x7ffb7c98> + b66: 4241 li tp,16 + b68: 5f49 li t5,-14 + b6a: 504c lw a1,36(s0) + b6c: 3436 fld fs0,360(sp) + b6e: 0046 c.slli zero,0x11 + b70: 6d5f 7462 776f 0x776f74626d5f + b76: 74735f63 bge t1,t2,12d4 <_start-0x7fffed2c> + b7a: 7461 lui s0,0xffff8 + b7c: 0065 c.nop 25 + b7e: 705f 7335 5f00 0x5f007335705f + b84: 745f 5f6d 646d 0x646d5f6d745f + b8a: 7961 lui s2,0xffff8 + b8c: 6800 flw fs0,16(s0) + b8e: 6174 flw fa3,68(a0) + b90: 5f62 lw t5,56(sp) + b92: 7165 addi sp,sp,-400 + ... + +Disassembly of section .debug_loc: + +00000000 <.debug_loc>: + 0: 0000 unimp + 2: 0000 unimp + 4: 0068 addi a0,sp,12 + 6: 0000 unimp + 8: 0001 nop + a: 685a flw fa6,148(sp) + c: 0000 unimp + e: 9800 0x9800 + 10: 0000 unimp + 12: 0600 addi s0,sp,768 + 14: f300 fsw fs0,32(a4) + 16: 250af503 0x250af503 + 1a: 989f 0000 2800 0x28000000989f + 20: 0001 nop + 22: 0100 addi s0,sp,128 + 24: 5a00 lw s0,48(a2) + 26: 0128 addi a0,sp,136 + 28: 0000 unimp + 2a: 0150 addi a2,sp,132 + 2c: 0000 unimp + 2e: 0006 c.slli zero,0x1 + 30: 0af503f3 0xaf503f3 + 34: 9f25 0x9f25 + 36: 0150 addi a2,sp,132 + 38: 0000 unimp + 3a: 0184 addi s1,sp,192 + 3c: 0000 unimp + 3e: 0001 nop + 40: 845a mv s0,s6 + 42: 0001 nop + 44: a000 fsd fs0,0(s0) + 46: 0001 nop + 48: 0600 addi s0,sp,768 + 4a: f300 fsw fs0,32(a4) + 4c: 250af503 0x250af503 + 50: a09f 0001 ec00 0xec000001a09f + 56: 0001 nop + 58: 0100 addi s0,sp,128 + 5a: 5a00 lw s0,48(a2) + 5c: 01ec addi a1,sp,204 + 5e: 0000 unimp + 60: 0208 addi a0,sp,256 + 62: 0000 unimp + 64: 0006 c.slli zero,0x1 + 66: 0af503f3 0xaf503f3 + 6a: 9f25 0x9f25 + 6c: 0208 addi a0,sp,256 + 6e: 0000 unimp + 70: 0264 addi s1,sp,268 + 72: 0000 unimp + 74: 0001 nop + 76: 645a flw fs0,148(sp) + 78: 0002 c.slli64 zero + 7a: d000 sw s0,32(s0) + 7c: 0002 c.slli64 zero + 7e: 0600 addi s0,sp,768 + 80: f300 fsw fs0,32(a4) + 82: 250af503 0x250af503 + 86: d09f 0002 e800 0xe8000002d09f + 8c: 0002 c.slli64 zero + 8e: 0100 addi s0,sp,128 + 90: 5a00 lw s0,48(a2) + 92: 02e8 addi a0,sp,332 + 94: 0000 unimp + 96: 02f4 addi a3,sp,332 + 98: 0000 unimp + 9a: 0006 c.slli zero,0x1 + 9c: 0af503f3 0xaf503f3 + a0: 9f25 0x9f25 + a2: 02f4 addi a3,sp,332 + a4: 0000 unimp + a6: 0300 addi s0,sp,384 + a8: 0000 unimp + aa: 0001 nop + ac: 005a c.slli zero,0x16 + ae: 14000003 lb zero,320(zero) # 140 <_start-0x7ffffec0> + b2: 06000003 lb zero,96(zero) # 60 <_start-0x7fffffa0> + b6: f300 fsw fs0,32(a4) + b8: 250af503 0x250af503 + bc: 149f 0003 3c00 0x3c000003149f + c2: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> + c6: 5a00 lw s0,48(a2) + c8: 033c addi a5,sp,392 + ca: 0000 unimp + cc: 0378 addi a4,sp,396 + ce: 0000 unimp + d0: 0006 c.slli zero,0x1 + d2: 0af503f3 0xaf503f3 + d6: 9f25 0x9f25 + d8: 0378 addi a4,sp,396 + da: 0000 unimp + dc: 0388 addi a0,sp,448 + de: 0000 unimp + e0: 0001 nop + e2: 885a mv a6,s6 + e4: 9c000003 lb zero,-1600(zero) # fffff9c0 <__global_pointer$+0x7fffbd58> + e8: 06000003 lb zero,96(zero) # 60 <_start-0x7fffffa0> + ec: f300 fsw fs0,32(a4) + ee: 250af503 0x250af503 + f2: 9c9f 0003 b000 0xb00000039c9f + f8: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> + fc: 5a00 lw s0,48(a2) + fe: 03b0 addi a2,sp,456 + 100: 0000 unimp + 102: 042c addi a1,sp,520 + 104: 0000 unimp + 106: 0006 c.slli zero,0x1 + 108: 0af503f3 0xaf503f3 + 10c: 9f25 0x9f25 + ... + 11a: 003c addi a5,sp,8 + 11c: 0000 unimp + 11e: 0001 nop + 120: 00003c5b 0x3c5b + 124: 2c00 fld fs0,24(s0) + 126: 0004 0x4 + 128: 0600 addi s0,sp,768 + 12a: f300 fsw fs0,32(a4) + 12c: 250bf503 0x250bf503 + 130: 009f 0000 0000 0x9f + 136: 0000 unimp + 138: 0000 unimp + 13a: 0000 unimp + 13c: a000 fsd fs0,0(s0) + 13e: 0000 unimp + 140: 0200 addi s0,sp,256 + 142: 3000 fld fs0,32(s0) + 144: a89f 0000 8400 0x84000000a89f + 14a: 0001 nop + 14c: 0200 addi s0,sp,256 + 14e: 3000 fld fs0,32(s0) + 150: b89f 0001 1400 0x14000001b89f + 156: 02000003 lb zero,32(zero) # 20 <_start-0x7fffffe0> + 15a: 3000 fld fs0,32(s0) + 15c: 289f 0003 a400 0xa4000003289f + 162: 02000003 lb zero,32(zero) # 20 <_start-0x7fffffe0> + 166: 3000 fld fs0,32(s0) + 168: ac9f 0003 b400 0xb4000003ac9f + 16e: 02000003 lb zero,32(zero) # 20 <_start-0x7fffffe0> + 172: 3000 fld fs0,32(s0) + 174: 009f 0000 0000 0x9f + 17a: 0000 unimp + 17c: 3800 fld fs0,48(s0) + 17e: 0000 unimp + 180: a000 fsd fs0,0(s0) + 182: 0000 unimp + 184: 0100 addi s0,sp,128 + 186: 5900 lw s0,48(a0) + 188: 00a0 addi s0,sp,72 + 18a: 0000 unimp + 18c: 00a8 addi a0,sp,72 + 18e: 0000 unimp + 190: 0005 c.nop 1 + 192: 007a c.slli zero,0x1e + 194: a89f254f fnmadd.s fa0,ft10,fs1,fs5,rdn + 198: 0000 unimp + 19a: 8400 0x8400 + 19c: 0001 nop + 19e: 0100 addi s0,sp,128 + 1a0: 5900 lw s0,48(a0) + 1a2: 01a0 addi s0,sp,200 + 1a4: 0000 unimp + 1a6: 01ac addi a1,sp,200 + 1a8: 0000 unimp + 1aa: 0001 nop + 1ac: ac59 j 442 <_start-0x7ffffbbe> + 1ae: 0001 nop + 1b0: b800 fsd fs0,48(s0) + 1b2: 0001 nop + 1b4: 0500 addi s0,sp,640 + 1b6: 7a00 flw fs0,48(a2) + 1b8: 4f00 lw s0,24(a4) + 1ba: 9f25 0x9f25 + 1bc: 01b8 addi a4,sp,200 + 1be: 0000 unimp + 1c0: 01ec addi a1,sp,204 + 1c2: 0000 unimp + 1c4: 0001 nop + 1c6: 0859 addi a6,a6,22 + 1c8: 0002 c.slli64 zero + 1ca: 7c00 flw fs0,56(s0) + 1cc: 0002 c.slli64 zero + 1ce: 0100 addi s0,sp,128 + 1d0: 5900 lw s0,48(a0) + 1d2: 0280 addi s0,sp,320 + 1d4: 0000 unimp + 1d6: 0290 addi a2,sp,320 + 1d8: 0000 unimp + 1da: 0001 nop + 1dc: 9459 srai s0,s0,0x36 + 1de: 0002 c.slli64 zero + 1e0: f000 fsw fs0,32(s0) + 1e2: 0002 c.slli64 zero + 1e4: 0100 addi s0,sp,128 + 1e6: 5900 lw s0,48(a0) + 1e8: 02f4 addi a3,sp,332 + 1ea: 0000 unimp + 1ec: 0324 addi s1,sp,392 + 1ee: 0000 unimp + 1f0: 0001 nop + 1f2: 2459 jal 478 <_start-0x7ffffb88> + 1f4: 28000003 lb zero,640(zero) # 280 <_start-0x7ffffd80> + 1f8: 05000003 lb zero,80(zero) # 50 <_start-0x7fffffb0> + 1fc: 7a00 flw fs0,48(a2) + 1fe: 4f00 lw s0,24(a4) + 200: 9f25 0x9f25 + 202: 0328 addi a0,sp,392 + 204: 0000 unimp + 206: 033c addi a5,sp,392 + 208: 0000 unimp + 20a: 0001 nop + 20c: 7859 lui a6,0xffff6 + 20e: 88000003 lb zero,-1920(zero) # fffff880 <__global_pointer$+0x7fffbc18> + 212: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> + 216: 5900 lw s0,48(a0) + 218: 039c addi a5,sp,448 + 21a: 0000 unimp + 21c: 03b4 addi a3,sp,456 + 21e: 0000 unimp + 220: 0001 nop + 222: 0059 c.nop 22 + 224: 0000 unimp + 226: 0000 unimp + 228: 0000 unimp + 22a: 2000 fld fs0,0(s0) + 22c: 0000 unimp + 22e: 8400 0x8400 + 230: 0001 nop + 232: 0100 addi s0,sp,128 + 234: 6200 flw fs0,0(a2) + 236: 01a0 addi s0,sp,200 + 238: 0000 unimp + 23a: 01e0 addi s0,sp,204 + 23c: 0000 unimp + 23e: 0001 nop + 240: e062 fsw fs8,0(sp) + 242: 0001 nop + 244: ec00 fsw fs0,24(s0) + 246: 0001 nop + 248: 0100 addi s0,sp,128 + 24a: 5e00 lw s0,56(a2) + 24c: 01ec addi a1,sp,204 + 24e: 0000 unimp + 250: 0204 addi s1,sp,256 + 252: 0000 unimp + 254: 0001 nop + 256: 0862 slli a6,a6,0x18 + 258: 0002 c.slli64 zero + 25a: 1000 addi s0,sp,32 + 25c: 0002 c.slli64 zero + 25e: 0100 addi s0,sp,128 + 260: 5e00 lw s0,56(a2) + 262: 0210 addi a2,sp,256 + 264: 0000 unimp + 266: 033c addi a5,sp,392 + 268: 0000 unimp + 26a: 0001 nop + 26c: 7862 flw fa6,56(sp) + 26e: 88000003 lb zero,-1920(zero) # fffff880 <__global_pointer$+0x7fffbc18> + 272: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> + 276: 6200 flw fs0,0(a2) + 278: 039c addi a5,sp,448 + 27a: 0000 unimp + 27c: 03b4 addi a3,sp,456 + 27e: 0000 unimp + 280: 0001 nop + 282: 0062 c.slli zero,0x18 + 284: 0000 unimp + 286: 0000 unimp + 288: 0000 unimp + 28a: 2000 fld fs0,0(s0) + 28c: 0000 unimp + 28e: 6400 flw fs0,8(s0) + 290: 0000 unimp + 292: 0100 addi s0,sp,128 + 294: 5f00 lw s0,56(a4) + 296: 0064 addi s1,sp,12 + 298: 0000 unimp + 29a: 0068 addi a0,sp,12 + 29c: 0000 unimp + 29e: 007a000b 0x7a000b + 2a2: ff0c fsw fa1,56(a4) + 2a4: 7fff 0x7fff + 2a6: 1a00 addi s0,sp,304 + 2a8: 989f2433 0x989f2433 + 2ac: 0000 unimp + 2ae: a000 fsd fs0,0(s0) + 2b0: 0000 unimp + 2b2: 0100 addi s0,sp,128 + 2b4: 5f00 lw s0,56(a4) + 2b6: 00a0 addi s0,sp,72 + 2b8: 0000 unimp + 2ba: 00a8 addi a0,sp,72 + 2bc: 0000 unimp + 2be: 007a000b 0x7a000b + 2c2: ff0c fsw fa1,56(a4) + 2c4: 7fff 0x7fff + 2c6: 1a00 addi s0,sp,304 + 2c8: a89f2433 0xa89f2433 + 2cc: 0000 unimp + 2ce: e000 fsw fs0,0(s0) + 2d0: 0000 unimp + 2d2: 0100 addi s0,sp,128 + 2d4: 5f00 lw s0,56(a4) + 2d6: 00e0 addi s0,sp,76 + 2d8: 0000 unimp + 2da: 00e4 addi s1,sp,76 + 2dc: 0000 unimp + 2de: 007a000b 0x7a000b + 2e2: ff0c fsw fa1,56(a4) + 2e4: 7fff 0x7fff + 2e6: 1a00 addi s0,sp,304 + 2e8: e49f2433 0xe49f2433 + 2ec: 0000 unimp + 2ee: 0000 unimp + 2f0: 0001 nop + 2f2: 0100 addi s0,sp,128 + 2f4: 5f00 lw s0,56(a4) + 2f6: 0100 addi s0,sp,128 + 2f8: 0000 unimp + 2fa: 0104 addi s1,sp,128 + 2fc: 0000 unimp + 2fe: 007a000b 0x7a000b + 302: ff0c fsw fa1,56(a4) + 304: 7fff 0x7fff + 306: 1a00 addi s0,sp,304 + 308: 049f2433 0x49f2433 + 30c: 0001 nop + 30e: 1000 addi s0,sp,32 + 310: 0001 nop + 312: 0100 addi s0,sp,128 + 314: 5f00 lw s0,56(a4) + 316: 0110 addi a2,sp,128 + 318: 0000 unimp + 31a: 0114 addi a3,sp,128 + 31c: 0000 unimp + 31e: 007a000b 0x7a000b + 322: ff0c fsw fa1,56(a4) + 324: 7fff 0x7fff + 326: 1a00 addi s0,sp,304 + 328: 149f2433 0x149f2433 + 32c: 0001 nop + 32e: 4000 lw s0,0(s0) + 330: 0001 nop + 332: 0100 addi s0,sp,128 + 334: 5f00 lw s0,56(a4) + 336: 0148 addi a0,sp,132 + 338: 0000 unimp + 33a: 0150 addi a2,sp,132 + 33c: 0000 unimp + 33e: 0001 nop + 340: 505d c.li zero,-9 + 342: 0001 nop + 344: 6c00 flw fs0,24(s0) + 346: 0001 nop + 348: 0100 addi s0,sp,128 + 34a: 5f00 lw s0,56(a4) + 34c: 016c addi a1,sp,140 + 34e: 0000 unimp + 350: 0184 addi s1,sp,192 + 352: 0000 unimp + 354: 007a000b 0x7a000b + 358: ff0c fsw fa1,56(a4) + 35a: 7fff 0x7fff + 35c: 1a00 addi s0,sp,304 + 35e: a09f2433 0xa09f2433 + 362: 0001 nop + 364: b000 fsd fs0,32(s0) + 366: 0001 nop + 368: 0100 addi s0,sp,128 + 36a: 5f00 lw s0,56(a4) + 36c: 01b0 addi a2,sp,200 + 36e: 0000 unimp + 370: 01b8 addi a4,sp,200 + 372: 0000 unimp + 374: 007a000b 0x7a000b + 378: ff0c fsw fa1,56(a4) + 37a: 7fff 0x7fff + 37c: 1a00 addi s0,sp,304 + 37e: b89f2433 0xb89f2433 + 382: 0001 nop + 384: c400 sw s0,8(s0) + 386: 0001 nop + 388: 0100 addi s0,sp,128 + 38a: 5f00 lw s0,56(a4) + 38c: 01c4 addi s1,sp,196 + 38e: 0000 unimp + 390: 01d0 addi a2,sp,196 + 392: 0000 unimp + 394: 007a000b 0x7a000b + 398: ff0c fsw fa1,56(a4) + 39a: 7fff 0x7fff + 39c: 1a00 addi s0,sp,304 + 39e: d09f2433 0xd09f2433 + 3a2: 0001 nop + 3a4: ec00 fsw fs0,24(s0) + 3a6: 0001 nop + 3a8: 0100 addi s0,sp,128 + 3aa: 5f00 lw s0,56(a4) + 3ac: 0208 addi a0,sp,256 + 3ae: 0000 unimp + 3b0: 023c addi a5,sp,264 + 3b2: 0000 unimp + 3b4: 0001 nop + 3b6: 3c5f 0002 4400 0x440000023c5f + 3bc: 0002 c.slli64 zero + 3be: 0b00 addi s0,sp,400 + 3c0: 7a00 flw fs0,48(a2) + 3c2: 0c00 addi s0,sp,528 + 3c4: ffff 0xffff + 3c6: 007f 0x7f + 3c8: 331a fld ft6,416(sp) + 3ca: 9f24 0x9f24 + 3cc: 0244 addi s1,sp,260 + 3ce: 0000 unimp + 3d0: 0278 addi a4,sp,268 + 3d2: 0000 unimp + 3d4: 0001 nop + 3d6: 805f 0002 8c00 0x8c000002805f + 3dc: 0002 c.slli64 zero + 3de: 0100 addi s0,sp,128 + 3e0: 5f00 lw s0,56(a4) + 3e2: 0294 addi a3,sp,320 + 3e4: 0000 unimp + 3e6: 02c0 addi s0,sp,324 + 3e8: 0000 unimp + 3ea: 0001 nop + 3ec: c85f 0002 d000 0xd0000002c85f + 3f2: 0002 c.slli64 zero + 3f4: 0100 addi s0,sp,128 + 3f6: 5d00 lw s0,56(a0) + 3f8: 02d0 addi a2,sp,324 + 3fa: 0000 unimp + 3fc: 02e8 addi a0,sp,332 + 3fe: 0000 unimp + 400: 0001 nop + 402: f45f 0002 0400 0x4000002f45f + 408: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> + 40c: 5f00 lw s0,56(a4) + 40e: 0314 addi a3,sp,384 + 410: 0000 unimp + 412: 0320 addi s0,sp,392 + 414: 0000 unimp + 416: 0001 nop + 418: 205f 0003 2800 0x28000003205f + 41e: 0b000003 lb zero,176(zero) # b0 <_start-0x7fffff50> + 422: 7a00 flw fs0,48(a2) + 424: 0c00 addi s0,sp,528 + 426: ffff 0xffff + 428: 007f 0x7f + 42a: 331a fld ft6,416(sp) + 42c: 9f24 0x9f24 + 42e: 0328 addi a0,sp,392 + 430: 0000 unimp + 432: 033c addi a5,sp,392 + 434: 0000 unimp + 436: 0001 nop + 438: 785f 0003 8000 0x80000003785f + 43e: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> + 442: 5f00 lw s0,56(a4) + 444: 0380 addi s0,sp,448 + 446: 0000 unimp + 448: 0388 addi a0,sp,448 + 44a: 0000 unimp + 44c: 007a000b 0x7a000b + 450: ff0c fsw fa1,56(a4) + 452: 7fff 0x7fff + 454: 1a00 addi s0,sp,304 + 456: 9c9f2433 0x9c9f2433 + 45a: a8000003 lb zero,-1408(zero) # fffffa80 <__global_pointer$+0x7fffbe18> + 45e: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> + 462: 5f00 lw s0,56(a4) + 464: 03a8 addi a0,sp,456 + 466: 0000 unimp + 468: 03ac addi a1,sp,456 + 46a: 0000 unimp + 46c: 007a000b 0x7a000b + 470: ff0c fsw fa1,56(a4) + 472: 7fff 0x7fff + 474: 1a00 addi s0,sp,304 + 476: ac9f2433 0xac9f2433 + 47a: b0000003 lb zero,-1280(zero) # fffffb00 <__global_pointer$+0x7fffbe98> + 47e: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> + 482: 5f00 lw s0,56(a4) + ... + 48c: 0040 addi s0,sp,4 + 48e: 0000 unimp + 490: 0064 addi s1,sp,12 + 492: 0000 unimp + 494: 0001 nop + 496: 0000985b 0x985b + 49a: a000 fsd fs0,0(s0) + 49c: 0000 unimp + 49e: 0100 addi s0,sp,128 + 4a0: 5b00 lw s0,48(a4) + 4a2: 00a8 addi a0,sp,72 + 4a4: 0000 unimp + 4a6: 00bc addi a5,sp,72 + 4a8: 0000 unimp + 4aa: 0001 nop + 4ac: 0000e45b 0xe45b + 4b0: ec00 fsw fs0,24(s0) + 4b2: 0000 unimp + 4b4: 0100 addi s0,sp,128 + 4b6: 5b00 lw s0,48(a4) + 4b8: 0150 addi a2,sp,132 + 4ba: 0000 unimp + 4bc: 0154 addi a3,sp,132 + 4be: 0000 unimp + 4c0: 0001 nop + 4c2: 0001d05b 0x1d05b + 4c6: ec00 fsw fs0,24(s0) + 4c8: 0001 nop + 4ca: 0100 addi s0,sp,128 + 4cc: 5b00 lw s0,48(a4) + 4ce: 0208 addi a0,sp,256 + 4d0: 0000 unimp + 4d2: 020c addi a1,sp,256 + 4d4: 0000 unimp + 4d6: 0001 nop + 4d8: 0002445b 0x2445b + 4dc: 4800 lw s0,16(s0) + 4de: 0002 c.slli64 zero + 4e0: 0100 addi s0,sp,128 + 4e2: 5b00 lw s0,48(a4) + 4e4: 025c addi a5,sp,260 + 4e6: 0000 unimp + 4e8: 033c addi a5,sp,392 + 4ea: 0000 unimp + 4ec: 0001 nop + 4ee: 0003785b 0x3785b + 4f2: 8800 0x8800 + 4f4: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> + 4f8: 5b00 lw s0,48(a4) + 4fa: 039c addi a5,sp,448 + 4fc: 0000 unimp + 4fe: 03a4 addi s1,sp,456 + 500: 0000 unimp + 502: 0001 nop + 504: 0000005b 0x5b + 508: 0000 unimp + 50a: 0000 unimp + 50c: 4000 lw s0,0(s0) + 50e: 0000 unimp + 510: 6400 flw fs0,8(s0) + 512: 0000 unimp + 514: 0100 addi s0,sp,128 + 516: 5e00 lw s0,56(a2) + 518: 0098 addi a4,sp,64 + 51a: 0000 unimp + 51c: 009c addi a5,sp,64 + 51e: 0000 unimp + 520: 0001 nop + 522: a85e fsd fs7,16(sp) + 524: 0000 unimp + 526: ac00 fsd fs0,24(s0) + 528: 0000 unimp + 52a: 0100 addi s0,sp,128 + 52c: 5e00 lw s0,56(a2) + 52e: 00e4 addi s1,sp,76 + 530: 0000 unimp + 532: 010c addi a1,sp,128 + 534: 0000 unimp + 536: 0001 nop + 538: 145e slli s0,s0,0x37 + 53a: 0001 nop + 53c: 5800 lw s0,48(s0) + 53e: 0001 nop + 540: 0100 addi s0,sp,128 + 542: 5e00 lw s0,56(a2) + 544: 01d0 addi a2,sp,196 + 546: 0000 unimp + 548: 01dc addi a5,sp,196 + 54a: 0000 unimp + 54c: 0001 nop + 54e: 445e lw s0,212(sp) + 550: 0002 c.slli64 zero + 552: 4c00 lw s0,24(s0) + 554: 0002 c.slli64 zero + 556: 0100 addi s0,sp,128 + 558: 5e00 lw s0,56(a2) + 55a: 025c addi a5,sp,260 + 55c: 0000 unimp + 55e: 0288 addi a0,sp,320 + 560: 0000 unimp + 562: 0001 nop + 564: 945e add s0,s0,s7 + 566: 0002 c.slli64 zero + 568: d400 sw s0,40(s0) + 56a: 0002 c.slli64 zero + 56c: 0100 addi s0,sp,128 + 56e: 5e00 lw s0,56(a2) + 570: 039c addi a5,sp,448 + 572: 0000 unimp + 574: 03a0 addi s0,sp,456 + 576: 0000 unimp + 578: 0001 nop + 57a: 005e c.slli zero,0x17 + 57c: 0000 unimp + 57e: 0000 unimp + 580: 0000 unimp + 582: 4000 lw s0,0(s0) + 584: 0000 unimp + 586: 6400 flw fs0,8(s0) + 588: 0000 unimp + 58a: 0100 addi s0,sp,128 + 58c: 5c00 lw s0,56(s0) + 58e: 0098 addi a4,sp,64 + 590: 0000 unimp + 592: 00d4 addi a3,sp,68 + 594: 0000 unimp + 596: 0001 nop + 598: dc5c sw a5,60(s0) + 59a: 0000 unimp + 59c: e400 fsw fs0,8(s0) + 59e: 0000 unimp + 5a0: 0100 addi s0,sp,128 + 5a2: 5e00 lw s0,56(a2) + 5a4: 00e4 addi s1,sp,76 + 5a6: 0000 unimp + 5a8: 0184 addi s1,sp,192 + 5aa: 0000 unimp + 5ac: 0001 nop + 5ae: a05c fsd fa5,128(s0) + 5b0: 0001 nop + 5b2: ec00 fsw fs0,24(s0) + 5b4: 0001 nop + 5b6: 0100 addi s0,sp,128 + 5b8: 5c00 lw s0,56(s0) + 5ba: 0208 addi a0,sp,256 + 5bc: 0000 unimp + 5be: 0230 addi a2,sp,264 + 5c0: 0000 unimp + 5c2: 0001 nop + 5c4: 385c fld fa5,176(s0) + 5c6: 0002 c.slli64 zero + 5c8: 4000 lw s0,0(s0) + 5ca: 0002 c.slli64 zero + 5cc: 0100 addi s0,sp,128 + 5ce: 5e00 lw s0,56(a2) + 5d0: 0244 addi s1,sp,260 + 5d2: 0000 unimp + 5d4: 033c addi a5,sp,392 + 5d6: 0000 unimp + 5d8: 0001 nop + 5da: 785c flw fa5,52(s0) + 5dc: 88000003 lb zero,-1920(zero) # fffff880 <__global_pointer$+0x7fffbc18> + 5e0: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> + 5e4: 5c00 lw s0,56(s0) + 5e6: 039c addi a5,sp,448 + 5e8: 0000 unimp + 5ea: 03b0 addi a2,sp,456 + 5ec: 0000 unimp + 5ee: 0001 nop + 5f0: 005c addi a5,sp,4 + 5f2: 0000 unimp + 5f4: 0000 unimp + 5f6: 0000 unimp + 5f8: 4c00 lw s0,24(s0) + 5fa: 0000 unimp + 5fc: a000 fsd fs0,0(s0) + 5fe: 0000 unimp + 600: 0100 addi s0,sp,128 + 602: 5900 lw s0,48(a0) + 604: 00a8 addi a0,sp,72 + 606: 0000 unimp + 608: 01a4 addi s1,sp,200 + 60a: 0000 unimp + 60c: 0001 nop + 60e: b859 j fffffea4 <__global_pointer$+0x7fffc23c> + 610: 0001 nop + 612: d000 sw s0,32(s0) + 614: 0001 nop + 616: 0100 addi s0,sp,128 + 618: 5900 lw s0,48(a0) + 61a: 01d4 addi a3,sp,196 + 61c: 0000 unimp + 61e: 025c addi a5,sp,260 + 620: 0000 unimp + 622: 0001 nop + 624: 6459 lui s0,0x16 + 626: 0002 c.slli64 zero + 628: 8800 0x8800 + 62a: 0002 c.slli64 zero + 62c: 0100 addi s0,sp,128 + 62e: 5b00 lw s0,48(a4) + 630: 0294 addi a3,sp,320 + 632: 0000 unimp + 634: 02d0 addi a2,sp,324 + 636: 0000 unimp + 638: 0001 nop + 63a: 0002fc5b 0x2fc5b + 63e: 1400 addi s0,sp,544 + 640: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> + 644: 5900 lw s0,48(a0) + 646: 032c addi a1,sp,392 + 648: 0000 unimp + 64a: 0338 addi a4,sp,392 + 64c: 0000 unimp + 64e: 0001 nop + 650: 3859 jal fffffee6 <__global_pointer$+0x7fffc27e> + 652: 3c000003 lb zero,960(zero) # 3c0 <_start-0x7ffffc40> + 656: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> + 65a: 5b00 lw s0,48(a4) + 65c: 033c addi a5,sp,392 + 65e: 0000 unimp + 660: 03b4 addi a3,sp,456 + 662: 0000 unimp + 664: 0001 nop + 666: ec59 bnez s0,704 <_start-0x7ffff8fc> + 668: 14000003 lb zero,320(zero) # 140 <_start-0x7ffffec0> + 66c: 0004 0x4 + 66e: 0100 addi s0,sp,128 + 670: 5900 lw s0,48(a0) + ... + 67a: 0050 addi a2,sp,4 + 67c: 0000 unimp + 67e: 0068 addi a0,sp,12 + 680: 0000 unimp + 682: 0001 nop + 684: 6862 flw fa6,24(sp) + 686: 0000 unimp + 688: 9800 0x9800 + 68a: 0000 unimp + 68c: 0100 addi s0,sp,128 + 68e: 5e00 lw s0,56(a2) + 690: 0098 addi a4,sp,64 + 692: 0000 unimp + 694: 00a0 addi s0,sp,72 + 696: 0000 unimp + 698: 0001 nop + 69a: a862 fsd fs8,16(sp) + 69c: 0000 unimp + 69e: e400 fsw fs0,8(s0) + 6a0: 0000 unimp + 6a2: 0100 addi s0,sp,128 + 6a4: 6200 flw fs0,0(a2) + 6a6: 00ec addi a1,sp,76 + 6a8: 0000 unimp + 6aa: 010c addi a1,sp,128 + 6ac: 0000 unimp + 6ae: 0001 nop + 6b0: 145e slli s0,s0,0x37 + 6b2: 0001 nop + 6b4: 5000 lw s0,32(s0) + 6b6: 0001 nop + 6b8: 0100 addi s0,sp,128 + 6ba: 5e00 lw s0,56(a2) + 6bc: 0160 addi s0,sp,140 + 6be: 0000 unimp + 6c0: 0180 addi s0,sp,192 + 6c2: 0000 unimp + 6c4: 0002 c.slli64 zero + 6c6: 9f30 0x9f30 + 6c8: 0180 addi s0,sp,192 + 6ca: 0000 unimp + 6cc: 0184 addi s1,sp,192 + 6ce: 0000 unimp + 6d0: 0002 c.slli64 zero + 6d2: 9f31 0x9f31 + 6d4: 0184 addi s1,sp,192 + 6d6: 0000 unimp + 6d8: 01a0 addi s0,sp,200 + 6da: 0000 unimp + 6dc: 0001 nop + 6de: a05e fsd fs7,0(sp) + 6e0: 0001 nop + 6e2: b800 fsd fs0,48(s0) + 6e4: 0001 nop + 6e6: 0300 addi s0,sp,384 + 6e8: 0800 addi s0,sp,16 + 6ea: 9fff 0x9fff + 6ec: 01b8 addi a4,sp,200 + 6ee: 0000 unimp + 6f0: 01d0 addi a2,sp,196 + 6f2: 0000 unimp + 6f4: 0001 nop + 6f6: 0001d45b 0x1d45b + 6fa: e000 fsw fs0,0(s0) + 6fc: 0001 nop + 6fe: 0100 addi s0,sp,128 + 700: 6200 flw fs0,0(a2) + 702: 01e0 addi s0,sp,204 + 704: 0000 unimp + 706: 0210 addi a2,sp,256 + 708: 0000 unimp + 70a: 0001 nop + 70c: 105e c.slli zero,0x37 + 70e: 0002 c.slli64 zero + 710: 5c00 lw s0,56(s0) + 712: 0002 c.slli64 zero + 714: 0100 addi s0,sp,128 + 716: 6200 flw fs0,0(a2) + 718: 0264 addi s1,sp,268 + 71a: 0000 unimp + 71c: 0288 addi a0,sp,320 + 71e: 0000 unimp + 720: 0001 nop + 722: 945e add s0,s0,s7 + 724: 0002 c.slli64 zero + 726: d000 sw s0,32(s0) + 728: 0002 c.slli64 zero + 72a: 0100 addi s0,sp,128 + 72c: 5e00 lw s0,56(a2) + 72e: 02e0 addi s0,sp,332 + 730: 0000 unimp + 732: 02ec addi a1,sp,332 + 734: 0000 unimp + 736: 0002 c.slli64 zero + 738: 9f30 0x9f30 + 73a: 02f4 addi a3,sp,332 + 73c: 0000 unimp + 73e: 0314 addi a3,sp,384 + 740: 0000 unimp + 742: 0002 c.slli64 zero + 744: 9f30 0x9f30 + 746: 0314 addi a3,sp,384 + 748: 0000 unimp + 74a: 0328 addi a0,sp,392 + 74c: 0000 unimp + 74e: ff080003 lb zero,-16(a6) # ffff5ff0 <__global_pointer$+0x7fff2388> + 752: 289f 0003 7000 0x70000003289f + 758: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> + 75c: 6200 flw fs0,0(a2) + 75e: 0370 addi a2,sp,396 + 760: 0000 unimp + 762: 0378 addi a4,sp,396 + 764: 0000 unimp + 766: 0002 c.slli64 zero + 768: 9f30 0x9f30 + 76a: 0378 addi a4,sp,396 + 76c: 0000 unimp + 76e: 0394 addi a3,sp,448 + 770: 0000 unimp + 772: 0001 nop + 774: 9462 add s0,s0,s8 + 776: 9c000003 lb zero,-1600(zero) # fffff9c0 <__global_pointer$+0x7fffbd58> + 77a: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> + 77e: 5e00 lw s0,56(a2) + 780: 039c addi a5,sp,448 + 782: 0000 unimp + 784: 03a4 addi s1,sp,456 + 786: 0000 unimp + 788: 0001 nop + 78a: a462 fsd fs8,8(sp) + 78c: ac000003 lb zero,-1344(zero) # fffffac0 <__global_pointer$+0x7fffbe58> + 790: 03000003 lb zero,48(zero) # 30 <_start-0x7fffffd0> + 794: 0800 addi s0,sp,16 + 796: 9fff 0x9fff + 798: 03ac addi a1,sp,456 + 79a: 0000 unimp + 79c: 03b0 addi a2,sp,456 + 79e: 0000 unimp + 7a0: 0001 nop + 7a2: 0003c05b 0x3c05b + 7a6: e000 fsw fs0,0(s0) + 7a8: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> + 7ac: 5e00 lw s0,56(a2) + 7ae: 03e0 addi s0,sp,460 + 7b0: 0000 unimp + 7b2: 03ec addi a1,sp,460 + 7b4: 0000 unimp + 7b6: ff080003 lb zero,-16(a6) + 7ba: 249f 0004 2c00 0x2c000004249f + 7c0: 0004 0x4 + 7c2: 0100 addi s0,sp,128 + 7c4: 5e00 lw s0,56(a2) + ... + 7ce: 0064 addi s1,sp,12 + 7d0: 0000 unimp + 7d2: 0070 addi a2,sp,12 + 7d4: 0000 unimp + 7d6: 0001 nop + 7d8: 705f 0000 7400 0x74000000705f + 7de: 0000 unimp + 7e0: 0900 addi s0,sp,144 + 7e2: 7f00 flw fs0,56(a4) + 7e4: 1100 addi s0,sp,160 + 7e6: ffff 0xffff + 7e8: 5fff 0x5fff + 7ea: 9f1a add t5,t5,t1 + 7ec: 0074 addi a3,sp,12 + 7ee: 0000 unimp + 7f0: 0084 addi s1,sp,64 + 7f2: 0000 unimp + 7f4: 0010 0x10 + 7f6: 007f 0x7f + 7f8: 2531 jal e04 <_start-0x7ffff1fc> + 7fa: ff0c fsw fa1,56(a4) + 7fc: ffff 0xffff + 7fe: 1a7d addi s4,s4,-1 + 800: 007f 0x7f + 802: 1a31 addi s4,s4,-20 + 804: 9f21 0x9f21 + 806: 0084 addi s1,sp,64 + 808: 0000 unimp + 80a: 008c addi a1,sp,64 + 80c: 0000 unimp + 80e: 000e c.slli zero,0x3 + 810: 007f 0x7f + 812: 2531 jal e1e <_start-0x7ffff1e2> + 814: ff0c fsw fa1,56(a4) + 816: ffff 0xffff + 818: 1a7d addi s4,s4,-1 + 81a: 007c addi a5,sp,12 + 81c: 9f21 0x9f21 + 81e: 008c addi a1,sp,64 + 820: 0000 unimp + 822: 0090 addi a2,sp,64 + 824: 0000 unimp + 826: 000c 0xc + 828: 007f 0x7f + 82a: ff0c fsw fa1,56(a4) + 82c: ffff 0xffff + 82e: 1a7d addi s4,s4,-1 + 830: 007c addi a5,sp,12 + 832: 9f21 0x9f21 + 834: 0100 addi s0,sp,128 + 836: 0000 unimp + 838: 0104 addi s1,sp,128 + 83a: 0000 unimp + 83c: 0001 nop + 83e: 4c5f 0001 5000 0x500000014c5f + 844: 0001 nop + 846: 0100 addi s0,sp,128 + 848: 5f00 lw s0,56(a4) + 84a: 016c addi a1,sp,140 + 84c: 0000 unimp + 84e: 01a0 addi s0,sp,200 + 850: 0000 unimp + 852: 0001 nop + 854: b85f 0001 c400 0xc4000001b85f + 85a: 0001 nop + 85c: 0800 addi s0,sp,16 + 85e: 7f00 flw fs0,56(a4) + 860: 7c00 flw fs0,56(s0) + 862: 2200 fld fs0,0(a2) + 864: 2531 jal e70 <_start-0x7ffff190> + 866: c49f 0001 c800 0xc8000001c49f + 86c: 0001 nop + 86e: 0500 addi s0,sp,640 + 870: 7f00 flw fs0,56(a4) + 872: 3100 fld fs0,32(a0) + 874: 9f25 0x9f25 + 876: 01c8 addi a0,sp,196 + 878: 0000 unimp + 87a: 01d0 addi a2,sp,196 + 87c: 0000 unimp + 87e: 0010 0x10 + 880: 007a c.slli zero,0x1e + 882: ff0c fsw fa1,56(a4) + 884: 7fff 0x7fff + 886: 1a00 addi s0,sp,304 + 888: 007c2433 slt s0,s8,t2 + 88c: 3122 fld ft2,40(sp) + 88e: 9f25 0x9f25 + 890: 01ec addi a1,sp,204 + 892: 0000 unimp + 894: 0200 addi s0,sp,256 + 896: 0000 unimp + 898: 0001 nop + 89a: 005f 0002 0800 0x8000002005f + 8a0: 0002 c.slli64 zero + 8a2: 0100 addi s0,sp,128 + 8a4: 5800 lw s0,48(s0) + 8a6: 023c addi a5,sp,264 + 8a8: 0000 unimp + 8aa: 0244 addi s1,sp,260 + 8ac: 0000 unimp + 8ae: 0001 nop + 8b0: 785f 0002 8000 0x80000002785f + 8b6: 0002 c.slli64 zero + 8b8: 0100 addi s0,sp,128 + 8ba: 5f00 lw s0,56(a4) + 8bc: 02e4 addi s1,sp,332 + 8be: 0000 unimp + 8c0: 02e8 addi a0,sp,332 + 8c2: 0000 unimp + 8c4: 0001 nop + 8c6: fc5c fsw fa5,60(s0) + 8c8: 0002 c.slli64 zero + 8ca: 1400 addi s0,sp,544 + 8cc: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> + 8d0: 5d00 lw s0,56(a0) + 8d2: 032c addi a1,sp,392 + 8d4: 0000 unimp + 8d6: 0368 addi a0,sp,396 + 8d8: 0000 unimp + 8da: 0001 nop + 8dc: 7058 flw fa4,36(s0) + 8de: 78000003 lb zero,1920(zero) # 780 <_start-0x7ffff880> + 8e2: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> + 8e6: 5f00 lw s0,56(a4) + 8e8: 0378 addi a4,sp,396 + 8ea: 0000 unimp + 8ec: 0398 addi a4,sp,448 + 8ee: 0000 unimp + 8f0: 0001 nop + 8f2: 9858 0x9858 + 8f4: 9c000003 lb zero,-1600(zero) # fffff9c0 <__global_pointer$+0x7fffbd58> + 8f8: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> + 8fc: 5f00 lw s0,56(a4) + 8fe: 03ac addi a1,sp,456 + 900: 0000 unimp + 902: 03b0 addi a2,sp,456 + 904: 0000 unimp + 906: 0008 0x8 + 908: 007f 0x7f + 90a: 007c addi a5,sp,12 + 90c: 3122 fld ft2,40(sp) + 90e: 9f25 0x9f25 + 910: 03b4 addi a3,sp,456 + 912: 0000 unimp + 914: 03bc addi a5,sp,456 + 916: 0000 unimp + 918: 0001 nop + 91a: bc5f 0003 d400 0xd4000003bc5f + 920: 09000003 lb zero,144(zero) # 90 <_start-0x7fffff70> + 924: 7f00 flw fs0,56(a4) + 926: 1100 addi s0,sp,160 + 928: ffff 0xffff + 92a: 5fff 0x5fff + 92c: 9f1a add t5,t5,t1 + 92e: 03d4 addi a3,sp,452 + 930: 0000 unimp + 932: 03e8 addi a0,sp,460 + 934: 0000 unimp + 936: 0001 nop + 938: ec5f 0003 0000 0x3ec5f + 93e: 0004 0x4 + 940: 0100 addi s0,sp,128 + 942: 5f00 lw s0,56(a4) + 944: 0424 addi s1,sp,520 + 946: 0000 unimp + 948: 0428 addi a0,sp,520 + 94a: 0000 unimp + 94c: 0009 c.nop 2 + 94e: 007f 0x7f + 950: ff11 bnez a4,86c <_start-0x7ffff794> + 952: ffff 0xffff + 954: 1a5f 009f 0000 0x9f1a5f + 95a: 0000 unimp + 95c: 0000 unimp + 95e: 1000 addi s0,sp,32 + 960: 0004 0x4 + 962: 1c00 addi s0,sp,560 + 964: 0004 0x4 + 966: 0800 addi s0,sp,16 + 968: 7f00 flw fs0,56(a4) + 96a: 7a00 flw fs0,48(a2) + 96c: 2100 fld fs0,0(a0) + 96e: 25f9 jal 103c <_start-0x7fffefc4> + 970: 1c9f 0004 2400 0x240000041c9f + 976: 0004 0x4 + 978: 0100 addi s0,sp,128 + 97a: 5a00 lw s0,48(a2) + ... + 984: 004c addi a1,sp,4 + 986: 0000 unimp + 988: 0064 addi s1,sp,12 + 98a: 0000 unimp + 98c: 0001 nop + 98e: 985d andi s0,s0,-9 + 990: 0000 unimp + 992: a000 fsd fs0,0(s0) + 994: 0000 unimp + 996: 0100 addi s0,sp,128 + 998: 5d00 lw s0,56(a0) + 99a: 00a8 addi a0,sp,72 + 99c: 0000 unimp + 99e: 00d0 addi a2,sp,68 + 9a0: 0000 unimp + 9a2: 0001 nop + 9a4: e45d bnez s0,a52 <_start-0x7ffff5ae> + 9a6: 0000 unimp + 9a8: ec00 fsw fs0,24(s0) + 9aa: 0000 unimp + 9ac: 0100 addi s0,sp,128 + 9ae: 5d00 lw s0,56(a0) + 9b0: 00ec addi a1,sp,76 + 9b2: 0000 unimp + 9b4: 010c addi a1,sp,128 + 9b6: 0000 unimp + 9b8: 0001 nop + 9ba: 0001145b 0x1145b + 9be: 5000 lw s0,32(s0) + 9c0: 0001 nop + 9c2: 0100 addi s0,sp,128 + 9c4: 5b00 lw s0,48(a4) + 9c6: 0150 addi a2,sp,132 + 9c8: 0000 unimp + 9ca: 0170 addi a2,sp,140 + 9cc: 0000 unimp + 9ce: 0001 nop + 9d0: a05d j a76 <_start-0x7ffff58a> + 9d2: 0001 nop + 9d4: a400 fsd fs0,8(s0) + 9d6: 0001 nop + 9d8: 0100 addi s0,sp,128 + 9da: 5d00 lw s0,56(a0) + 9dc: 01b8 addi a4,sp,200 + 9de: 0000 unimp + 9e0: 01d0 addi a2,sp,196 + 9e2: 0000 unimp + 9e4: 0001 nop + 9e6: 9c5d 0x9c5d + 9e8: b0000003 lb zero,-1280(zero) # fffffb00 <__global_pointer$+0x7fffbe98> + 9ec: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> + 9f0: 5d00 lw s0,56(a0) + ... + 9fa: 01d0 addi a2,sp,196 + 9fc: 0000 unimp + 9fe: 01dc addi a5,sp,196 + a00: 0000 unimp + a02: 0006 c.slli zero,0x1 + a04: 0082 c.slli64 ra + a06: 007e c.slli zero,0x1f + a08: 9f1c 0x9f1c + a0a: 01e4 addi s1,sp,204 + a0c: 0000 unimp + a0e: 01ec addi a1,sp,204 + a10: 0000 unimp + a12: 0001 nop + a14: 085d addi a6,a6,23 + a16: 0002 c.slli64 zero + a18: 2c00 fld fs0,24(s0) + a1a: 0002 c.slli64 zero + a1c: 0100 addi s0,sp,128 + a1e: 5d00 lw s0,56(a0) + a20: 0244 addi s1,sp,260 + a22: 0000 unimp + a24: 024c addi a1,sp,260 + a26: 0000 unimp + a28: 0006 c.slli zero,0x1 + a2a: 0082 c.slli64 ra + a2c: 007e c.slli zero,0x1f + a2e: 9f1c 0x9f1c + a30: 025c addi a5,sp,260 + a32: 0000 unimp + a34: 0264 addi s1,sp,268 + a36: 0000 unimp + a38: 0006 c.slli zero,0x1 + a3a: 0082 c.slli64 ra + a3c: 007e c.slli zero,0x1f + a3e: 9f1c 0x9f1c + a40: 0264 addi s1,sp,268 + a42: 0000 unimp + a44: 0288 addi a0,sp,320 + a46: 0000 unimp + a48: 0001 nop + a4a: 945a add s0,s0,s6 + a4c: 0002 c.slli64 zero + a4e: d000 sw s0,32(s0) + a50: 0002 c.slli64 zero + a52: 0100 addi s0,sp,128 + a54: 5a00 lw s0,48(a2) + a56: 02d0 addi a2,sp,324 + a58: 0000 unimp + a5a: 02d4 addi a3,sp,324 + a5c: 0000 unimp + a5e: 0006 c.slli zero,0x1 + a60: 0082 c.slli64 ra + a62: 007e c.slli zero,0x1f + a64: 9f1c 0x9f1c + ... + a6e: 0344 addi s1,sp,388 + a70: 0000 unimp + a72: 0348 addi a0,sp,388 + a74: 0000 unimp + a76: 0001 nop + a78: 485a lw a6,148(sp) + a7a: 54000003 lb zero,1344(zero) # 540 <_start-0x7ffffac0> + a7e: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> + a82: 5e00 lw s0,56(a2) + a84: 0354 addi a3,sp,388 + a86: 0000 unimp + a88: 0358 addi a4,sp,388 + a8a: 0000 unimp + a8c: 7b7a0003 lb zero,1975(s4) # ffffa7b7 <__global_pointer$+0x7fff6b4f> + a90: 589f 0003 6400 0x64000003589f + a96: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> + a9a: 5e00 lw s0,56(a2) + a9c: 0364 addi s1,sp,396 + a9e: 0000 unimp + aa0: 0378 addi a4,sp,396 + aa2: 0000 unimp + aa4: 0008 0x8 + aa6: 007a c.slli zero,0x1e + aa8: 0082 c.slli64 ra + aaa: 341c fld fa5,40(s0) + aac: 9f1c 0x9f1c + aae: 0388 addi a0,sp,448 + ab0: 0000 unimp + ab2: 0394 addi a3,sp,448 + ab4: 0000 unimp + ab6: 0001 nop + ab8: 945e add s0,s0,s7 + aba: 9c000003 lb zero,-1600(zero) # fffff9c0 <__global_pointer$+0x7fffbd58> + abe: 03000003 lb zero,48(zero) # 30 <_start-0x7fffffd0> + ac2: 7a00 flw fs0,48(a2) + ac4: 00009f7b 0x9f7b + ... + ad0: 0000 unimp + ad2: 0054 addi a3,sp,4 + ad4: 0000 unimp + ad6: 0001 nop + ad8: 545a lw s0,180(sp) + ada: 0000 unimp + adc: c000 sw s0,0(s0) + ade: 0000 unimp + ae0: 0600 addi s0,sp,768 + ae2: f300 fsw fs0,32(a4) + ae4: 250af503 0x250af503 + ae8: c09f 0000 c800 0xc8000000c09f + aee: 0000 unimp + af0: 0100 addi s0,sp,128 + af2: 5a00 lw s0,48(a2) + af4: 00c8 addi a0,sp,68 + af6: 0000 unimp + af8: 00e0 addi s0,sp,76 + afa: 0000 unimp + afc: 0006 c.slli zero,0x1 + afe: 0af503f3 0xaf503f3 + b02: 9f25 0x9f25 + b04: 00e0 addi s0,sp,76 + b06: 0000 unimp + b08: 0100 addi s0,sp,128 + b0a: 0000 unimp + b0c: 0001 nop + b0e: 005a c.slli zero,0x16 + b10: 0001 nop + b12: 2c00 fld fs0,24(s0) + b14: 06000003 lb zero,96(zero) # 60 <_start-0x7fffffa0> + b18: f300 fsw fs0,32(a4) + b1a: 250af503 0x250af503 + b1e: 009f 0000 0000 0x9f + b24: 0000 unimp + b26: 0000 unimp + b28: 0000 unimp + b2a: 5400 lw s0,40(s0) + b2c: 0000 unimp + b2e: 0100 addi s0,sp,128 + b30: 5b00 lw s0,48(a4) + b32: 0054 addi a3,sp,4 + b34: 0000 unimp + b36: 006c addi a1,sp,12 + b38: 0000 unimp + b3a: 0001 nop + b3c: 6c64 flw fs1,92(s0) + b3e: 0000 unimp + b40: c000 sw s0,0(s0) + b42: 0000 unimp + b44: 0600 addi s0,sp,768 + b46: f300 fsw fs0,32(a4) + b48: 250bf503 0x250bf503 + b4c: c09f 0000 cb00 0xcb000000c09f + b52: 0000 unimp + b54: 0100 addi s0,sp,128 + b56: 5b00 lw s0,48(a4) + b58: 000000cb fnmsub.s ft1,ft0,ft0,ft0,rne + b5c: 00e0 addi s0,sp,76 + b5e: 0000 unimp + b60: 0001 nop + b62: e064 fsw fs1,68(s0) + b64: 0000 unimp + b66: 0000 unimp + b68: 0001 nop + b6a: 0100 addi s0,sp,128 + b6c: 5b00 lw s0,48(a4) + b6e: 0100 addi s0,sp,128 + b70: 0000 unimp + b72: 032c addi a1,sp,392 + b74: 0000 unimp + b76: 0006 c.slli zero,0x1 + b78: 0bf503f3 0xbf503f3 + b7c: 9f25 0x9f25 + ... + b8a: 0058 addi a4,sp,4 + b8c: 0000 unimp + b8e: 0002 c.slli64 zero + b90: 9f30 0x9f30 + b92: 00c0 addi s0,sp,68 + b94: 0000 unimp + b96: 0100 addi s0,sp,128 + b98: 0000 unimp + b9a: 0002 c.slli64 zero + b9c: 9f30 0x9f30 + ... + ba6: 0054 addi a3,sp,4 + ba8: 0000 unimp + baa: 0058 addi a4,sp,4 + bac: 0000 unimp + bae: 0002 c.slli64 zero + bb0: 9f30 0x9f30 + bb2: 0058 addi a4,sp,4 + bb4: 0000 unimp + bb6: 00c0 addi s0,sp,68 + bb8: 0000 unimp + bba: 0001 nop + bbc: 0065 c.nop 25 + bbe: 0001 nop + bc0: 6000 flw fs0,0(s0) + bc2: 0002 c.slli64 zero + bc4: 0100 addi s0,sp,128 + bc6: 6500 flw fs0,8(a0) + bc8: 0268 addi a0,sp,268 + bca: 0000 unimp + bcc: 032c addi a1,sp,392 + bce: 0000 unimp + bd0: 0001 nop + bd2: 0065 c.nop 25 + bd4: 0000 unimp + bd6: 0000 unimp + bd8: 0000 unimp + bda: 3800 fld fs0,48(s0) + bdc: 0000 unimp + bde: 5400 lw s0,40(s0) + be0: 0002 c.slli64 zero + be2: 0600 addi s0,sp,768 + be4: 8200 0x8200 + be6: 0800 addi s0,sp,16 + be8: 1aff 0x1aff + bea: 689f 0002 2c00 0x2c000002689f + bf0: 06000003 lb zero,96(zero) # 60 <_start-0x7fffffa0> + bf4: 8200 0x8200 + bf6: 0800 addi s0,sp,16 + bf8: 1aff 0x1aff + bfa: 009f 0000 0000 0x9f + c00: 0000 unimp + c02: 3400 fld fs0,40(s0) + c04: 0000 unimp + c06: 5400 lw s0,40(s0) + c08: 0000 unimp + c0a: 0600 addi s0,sp,768 + c0c: 7900 flw fs0,48(a0) + c0e: 0800 addi s0,sp,16 + c10: 1aff 0x1aff + c12: 549f 0000 9800 0x98000000549f + c18: 0000 unimp + c1a: 0100 addi s0,sp,128 + c1c: 5900 lw s0,48(a0) + c1e: 00c0 addi s0,sp,68 + c20: 0000 unimp + c22: 00d4 addi a3,sp,68 + c24: 0000 unimp + c26: 0006 c.slli zero,0x1 + c28: 0079 c.nop 30 + c2a: ff08 fsw fa0,56(a4) + c2c: 9f1a add t5,t5,t1 + c2e: 00e0 addi s0,sp,76 + c30: 0000 unimp + c32: 00e4 addi s1,sp,76 + c34: 0000 unimp + c36: 0006 c.slli zero,0x1 + c38: 0079 c.nop 30 + c3a: ff08 fsw fa0,56(a4) + c3c: 9f1a add t5,t5,t1 + c3e: 00e4 addi s1,sp,76 + c40: 0000 unimp + c42: 00f4 addi a3,sp,76 + c44: 0000 unimp + c46: 0008 0x8 + c48: 007a c.slli zero,0x1e + c4a: ff082547 fmsub.q fa0,fa6,fa6,ft11,rdn + c4e: 9f1a add t5,t5,t1 + c50: 00f4 addi a3,sp,76 + c52: 0000 unimp + c54: 00f8 addi a4,sp,76 + c56: 0000 unimp + c58: 0006 c.slli zero,0x1 + c5a: 0079 c.nop 30 + c5c: ff08 fsw fa0,56(a4) + c5e: 9f1a add t5,t5,t1 + c60: 00f8 addi a4,sp,76 + c62: 0000 unimp + c64: 0100 addi s0,sp,128 + c66: 0000 unimp + c68: 0008 0x8 + c6a: 007a c.slli zero,0x1e + c6c: ff082547 fmsub.q fa0,fa6,fa6,ft11,rdn + c70: 9f1a add t5,t5,t1 + c72: 0100 addi s0,sp,128 + c74: 0000 unimp + c76: 0140 addi s0,sp,132 + c78: 0000 unimp + c7a: 0001 nop + c7c: 0059 c.nop 22 + c7e: 0000 unimp + c80: 0000 unimp + c82: 0000 unimp + c84: 3400 fld fs0,40(s0) + c86: 0000 unimp + c88: 4400 lw s0,8(s0) + c8a: 0000 unimp + c8c: 0100 addi s0,sp,128 + c8e: 6300 flw fs0,0(a4) + c90: 0044 addi s1,sp,4 + c92: 0000 unimp + c94: 0048 addi a0,sp,4 + c96: 0000 unimp + c98: 00830007 0x830007 + c9c: 4340 lw s0,4(a4) + c9e: 2124 fld fs1,64(a0) + ca0: 489f 0000 5000 0x50000000489f + ca6: 0000 unimp + ca8: 0b00 addi s0,sp,400 + caa: 7a00 flw fs0,48(a2) + cac: 3900 fld fs0,48(a0) + cae: 3924 fld fs1,112(a0) + cb0: 4025 c.li zero,9 + cb2: 9f212443 fmadd.q fs0,ft2,fs2,fs3,rdn + cb6: 0050 addi a2,sp,4 + cb8: 0000 unimp + cba: 0150 addi a2,sp,132 + cbc: 0000 unimp + cbe: 0001 nop + cc0: 00026863 bltu tp,zero,cd0 <_start-0x7ffff330> + cc4: 7000 flw fs0,32(s0) + cc6: 0002 c.slli64 zero + cc8: 0100 addi s0,sp,128 + cca: 6300 flw fs0,0(a4) + ccc: 0274 addi a3,sp,268 + cce: 0000 unimp + cd0: 0298 addi a4,sp,320 + cd2: 0000 unimp + cd4: 0001 nop + cd6: 0002a463 0x2a463 + cda: bc00 fsd fs0,56(s0) + cdc: 0002 c.slli64 zero + cde: 0100 addi s0,sp,128 + ce0: 6300 flw fs0,0(a4) + ce2: 0310 addi a2,sp,384 + ce4: 0000 unimp + ce6: 0320 addi s0,sp,392 + ce8: 0000 unimp + cea: 0001 nop + cec: 00000063 beqz zero,cec <_start-0x7ffff314> + cf0: 0000 unimp + cf2: 0000 unimp + cf4: 8800 0x8800 + cf6: 0000 unimp + cf8: 8c00 0x8c00 + cfa: 0000 unimp + cfc: 0200 addi s0,sp,256 + cfe: 3000 fld fs0,32(s0) + d00: 8c9f 0000 c000 0xc00000008c9f + d06: 0000 unimp + d08: 0100 addi s0,sp,128 + d0a: 5d00 lw s0,56(a0) + d0c: 0140 addi s0,sp,132 + d0e: 0000 unimp + d10: 0150 addi a2,sp,132 + d12: 0000 unimp + d14: 0001 nop + d16: 685d lui a6,0x17 + d18: 0002 c.slli64 zero + d1a: 6c00 flw fs0,24(s0) + d1c: 0002 c.slli64 zero + d1e: 0100 addi s0,sp,128 + d20: 5d00 lw s0,56(a0) + d22: 0274 addi a3,sp,268 + d24: 0000 unimp + d26: 0280 addi s0,sp,320 + d28: 0000 unimp + d2a: 0001 nop + d2c: a45d j fd2 <_start-0x7ffff02e> + d2e: 0002 c.slli64 zero + d30: b800 fsd fs0,48(s0) + d32: 0002 c.slli64 zero + d34: 0100 addi s0,sp,128 + d36: 5d00 lw s0,56(a0) + ... + d40: 006c addi a1,sp,12 + d42: 0000 unimp + d44: 00c0 addi s0,sp,68 + d46: 0000 unimp + d48: 0006 c.slli zero,0x1 + d4a: 0084 addi s1,sp,64 + d4c: ff08 fsw fa0,56(a4) + d4e: 9f1a add t5,t5,t1 + d50: 0100 addi s0,sp,128 + d52: 0000 unimp + d54: 025c addi a5,sp,260 + d56: 0000 unimp + d58: 0006 c.slli zero,0x1 + d5a: 0084 addi s1,sp,64 + d5c: ff08 fsw fa0,56(a4) + d5e: 9f1a add t5,t5,t1 + d60: 0268 addi a0,sp,268 + d62: 0000 unimp + d64: 032c addi a1,sp,392 + d66: 0000 unimp + d68: 0006 c.slli zero,0x1 + d6a: 0084 addi s1,sp,64 + d6c: ff08 fsw fa0,56(a4) + d6e: 9f1a add t5,t5,t1 + ... + d78: 0068 addi a0,sp,12 + d7a: 0000 unimp + d7c: 0088 addi a0,sp,64 + d7e: 0000 unimp + d80: 0006 c.slli zero,0x1 + d82: 007f 0x7f + d84: ff08 fsw fa0,56(a4) + d86: 9f1a add t5,t5,t1 + d88: 0088 addi a0,sp,64 + d8a: 0000 unimp + d8c: 00a0 addi s0,sp,72 + d8e: 0000 unimp + d90: 0001 nop + d92: 005f 0001 0b00 0xb000001005f + d98: 0001 nop + d9a: 0600 addi s0,sp,768 + d9c: 7f00 flw fs0,56(a4) + d9e: 0800 addi s0,sp,16 + da0: 1aff 0x1aff + da2: 209f 0001 2400 0x24000001209f + da8: 0001 nop + daa: 0600 addi s0,sp,768 + dac: 7f00 flw fs0,56(a4) + dae: 0800 addi s0,sp,16 + db0: 1aff 0x1aff + db2: 349f 0001 3800 0x38000001349f + db8: 0001 nop + dba: 0600 addi s0,sp,768 + dbc: 7f00 flw fs0,56(a4) + dbe: 0800 addi s0,sp,16 + dc0: 1aff 0x1aff + dc2: 009f 0000 0000 0x9f + dc8: 0000 unimp + dca: 6800 flw fs0,16(s0) + dcc: 0000 unimp + dce: 7800 flw fs0,48(s0) + dd0: 0000 unimp + dd2: 0100 addi s0,sp,128 + dd4: 5800 lw s0,48(s0) + dd6: 0078 addi a4,sp,12 + dd8: 0000 unimp + dda: 007c addi a5,sp,12 + ddc: 0000 unimp + dde: 00780007 0x780007 + de2: 4340 lw s0,4(a4) + de4: 2124 fld fs1,64(a0) + de6: 849f 0000 c000 0xc0000000849f + dec: 0000 unimp + dee: 0100 addi s0,sp,128 + df0: 5800 lw s0,48(s0) + df2: 0100 addi s0,sp,128 + df4: 0000 unimp + df6: 0154 addi a3,sp,132 + df8: 0000 unimp + dfa: 0001 nop + dfc: 6858 flw fa4,20(s0) + dfe: 0002 c.slli64 zero + e00: 7c00 flw fs0,56(s0) + e02: 0002 c.slli64 zero + e04: 0100 addi s0,sp,128 + e06: 5800 lw s0,48(s0) + e08: 02a4 addi s1,sp,328 + e0a: 0000 unimp + e0c: 02b0 addi a2,sp,328 + e0e: 0000 unimp + e10: 0001 nop + e12: 0058 addi a4,sp,4 + e14: 0000 unimp + e16: 0000 unimp + e18: 0000 unimp + e1a: 4000 lw s0,0(s0) + e1c: 0001 nop + e1e: e000 fsw fs0,0(s0) + e20: 0001 nop + e22: 0200 addi s0,sp,256 + e24: 3000 fld fs0,32(s0) + e26: 689f 0002 7400 0x74000002689f + e2c: 0002 c.slli64 zero + e2e: 0200 addi s0,sp,256 + e30: 3000 fld fs0,32(s0) + e32: 789f 0002 8000 0x80000002789f + e38: 0002 c.slli64 zero + e3a: 0100 addi s0,sp,128 + e3c: 6500 flw fs0,8(a0) + e3e: 0280 addi s0,sp,320 + e40: 0000 unimp + e42: 0298 addi a4,sp,320 + e44: 0000 unimp + e46: 0001 nop + e48: a85d j efe <_start-0x7ffff102> + e4a: 0002 c.slli64 zero + e4c: ac00 fsd fs0,24(s0) + e4e: 0002 c.slli64 zero + e50: 0100 addi s0,sp,128 + e52: 5d00 lw s0,56(a0) + ... + e5c: 00a4 addi s1,sp,72 + e5e: 0000 unimp + e60: 00c0 addi s0,sp,68 + e62: 0000 unimp + e64: 0001 nop + e66: 405a 0x405a + e68: 0001 nop + e6a: 4000 lw s0,0(s0) + e6c: 0002 c.slli64 zero + e6e: 0100 addi s0,sp,128 + e70: 5a00 lw s0,48(a2) + e72: 0268 addi a0,sp,268 + e74: 0000 unimp + e76: 0278 addi a4,sp,268 + e78: 0000 unimp + e7a: 0001 nop + e7c: 785a flw fa6,180(sp) + e7e: 0002 c.slli64 zero + e80: 8000 0x8000 + e82: 0002 c.slli64 zero + e84: 0600 addi s0,sp,768 + e86: 8200 0x8200 + e88: 0800 addi s0,sp,16 + e8a: 1aff 0x1aff + e8c: 809f 0002 a800 0xa8000002809f + e92: 0002 c.slli64 zero + e94: 0100 addi s0,sp,128 + e96: 5a00 lw s0,48(a2) + e98: 02a8 addi a0,sp,328 + e9a: 0000 unimp + e9c: 02ac addi a1,sp,328 + e9e: 0000 unimp + ea0: 0006 c.slli zero,0x1 + ea2: 0084 addi s1,sp,64 + ea4: ff08 fsw fa0,56(a4) + ea6: 9f1a add t5,t5,t1 + ea8: 02ac addi a1,sp,328 + eaa: 0000 unimp + eac: 02b4 addi a3,sp,328 + eae: 0000 unimp + eb0: 0001 nop + eb2: b45a fsd fs6,40(sp) + eb4: 0002 c.slli64 zero + eb6: bc00 fsd fs0,56(s0) + eb8: 0002 c.slli64 zero + eba: 0600 addi s0,sp,768 + ebc: 8200 0x8200 + ebe: 8400 0x8400 + ec0: 2700 fld fs0,8(a4) + ec2: bc9f 0002 1c00 0x1c000002bc9f + ec8: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> + ecc: 5a00 lw s0,48(a2) + ece: 0320 addi s0,sp,392 + ed0: 0000 unimp + ed2: 032c addi a1,sp,392 + ed4: 0000 unimp + ed6: 0001 nop + ed8: 005a c.slli zero,0x16 + eda: 0000 unimp + edc: 0000 unimp + ede: 0000 unimp + ee0: a400 fsd fs0,8(s0) + ee2: 0000 unimp + ee4: c000 sw s0,0(s0) + ee6: 0000 unimp + ee8: 0100 addi s0,sp,128 + eea: 5900 lw s0,48(a0) + eec: 0140 addi s0,sp,132 + eee: 0000 unimp + ef0: 01e4 addi s1,sp,204 + ef2: 0000 unimp + ef4: 0001 nop + ef6: e459 bnez s0,f84 <_start-0x7ffff07c> + ef8: 0001 nop + efa: 2800 fld fs0,16(s0) + efc: 0002 c.slli64 zero + efe: 0100 addi s0,sp,128 + f00: 5e00 lw s0,56(a2) + f02: 0268 addi a0,sp,268 + f04: 0000 unimp + f06: 0298 addi a4,sp,320 + f08: 0000 unimp + f0a: 0001 nop + f0c: a459 j 1192 <_start-0x7fffee6e> + f0e: 0002 c.slli64 zero + f10: bc00 fsd fs0,56(s0) + f12: 0002 c.slli64 zero + f14: 0100 addi s0,sp,128 + f16: 5900 lw s0,48(a0) + f18: 02bc addi a5,sp,328 + f1a: 0000 unimp + f1c: 02c4 addi s1,sp,324 + f1e: 0000 unimp + f20: 0001 nop + f22: c45e sw s7,8(sp) + f24: 0002 c.slli64 zero + f26: d400 sw s0,40(s0) + f28: 0002 c.slli64 zero + f2a: 0100 addi s0,sp,128 + f2c: 5f00 lw s0,56(a4) + f2e: 02d4 addi a3,sp,324 + f30: 0000 unimp + f32: 030c addi a1,sp,384 + f34: 0000 unimp + f36: 0006 c.slli zero,0x1 + f38: 2008 fld fa0,0(s0) + f3a: 0079 c.nop 30 + f3c: 9f1c 0x9f1c + f3e: 030c addi a1,sp,384 + f40: 0000 unimp + f42: 0310 addi a2,sp,384 + f44: 0000 unimp + f46: 0008 0x8 + f48: 007e c.slli zero,0x1f + f4a: 0079 c.nop 30 + f4c: 231c fld fa5,0(a4) + f4e: 9f1f 0310 0000 0x3109f1f + f54: 0320 addi s0,sp,392 + f56: 0000 unimp + f58: 0001 nop + f5a: 0059 c.nop 22 + f5c: 0000 unimp + f5e: 0000 unimp + f60: 0000 unimp + f62: e000 fsw fs0,0(s0) + f64: 0001 nop + f66: 1800 addi s0,sp,48 + f68: 0002 c.slli64 zero + f6a: 0100 addi s0,sp,128 + f6c: 5800 lw s0,48(s0) + f6e: 0218 addi a4,sp,256 + f70: 0000 unimp + f72: 0220 addi s0,sp,264 + f74: 0000 unimp + f76: 0005 c.nop 1 + f78: 0078 addi a4,sp,12 + f7a: 209f2533 0x209f2533 + f7e: 0002 c.slli64 zero + f80: 3000 fld fs0,32(s0) + f82: 0002 c.slli64 zero + f84: 0100 addi s0,sp,128 + f86: 5800 lw s0,48(s0) + f88: 0278 addi a4,sp,268 + f8a: 0000 unimp + f8c: 0280 addi s0,sp,320 + f8e: 0000 unimp + f90: 0001 nop + f92: 00028063 beqz t0,f92 <_start-0x7ffff06e> + f96: 9800 0x9800 + f98: 0002 c.slli64 zero + f9a: 0100 addi s0,sp,128 + f9c: 5800 lw s0,48(s0) + f9e: 02a8 addi a0,sp,328 + fa0: 0000 unimp + fa2: 02ac addi a1,sp,328 + fa4: 0000 unimp + fa6: 0001 nop + fa8: bc58 fsd fa4,184(s0) + faa: 0002 c.slli64 zero + fac: d800 sw s0,48(s0) + fae: 0002 c.slli64 zero + fb0: 0100 addi s0,sp,128 + fb2: 5800 lw s0,48(s0) + fb4: 02e0 addi s0,sp,332 + fb6: 0000 unimp + fb8: 0300 addi s0,sp,384 + fba: 0000 unimp + fbc: 0001 nop + fbe: 0058 addi a4,sp,4 + fc0: 0000 unimp + fc2: 0000 unimp + fc4: 0000 unimp + fc6: 4000 lw s0,0(s0) + fc8: 0002 c.slli64 zero + fca: 4800 lw s0,16(s0) + fcc: 0002 c.slli64 zero + fce: 0800 addi s0,sp,16 + fd0: 7800 flw fs0,48(s0) + fd2: 7a00 flw fs0,48(a2) + fd4: 2100 fld fs0,0(a0) + fd6: 25f9 jal 16a4 <_start-0x7fffe95c> + fd8: 489f 0002 6800 0x68000002489f + fde: 0002 c.slli64 zero + fe0: 0100 addi s0,sp,128 + fe2: 5a00 lw s0,48(a2) + ... + fec: 00cc addi a1,sp,68 + fee: 0000 unimp + ff0: 00e0 addi s0,sp,76 + ff2: 0000 unimp + ff4: 787a0003 lb zero,1927(s4) + ff8: 009f 0000 0000 0x9f + ffe: 0000 unimp + 1000: 0c00 addi s0,sp,528 + 1002: 0001 nop + 1004: 2000 fld fs0,0(s0) + 1006: 0001 nop + 1008: 0300 addi s0,sp,384 + 100a: 7a00 flw fs0,48(a2) + 100c: 9f78 0x9f78 + ... + 1016: 014c addi a1,sp,132 + 1018: 0000 unimp + 101a: 01e0 addi s0,sp,204 + 101c: 0000 unimp + 101e: 0001 nop + 1020: 00027063 bgeu tp,zero,1020 <_start-0x7fffefe0> + 1024: 7400 flw fs0,40(s0) + 1026: 0002 c.slli64 zero + 1028: 0100 addi s0,sp,128 + 102a: 6300 flw fs0,0(a4) + ... + 1034: 014c addi a1,sp,132 + 1036: 0000 unimp + 1038: 0150 addi a2,sp,132 + 103a: 0000 unimp + 103c: 0002 c.slli64 zero + 103e: 9f30 0x9f30 + 1040: 0150 addi a2,sp,132 + 1042: 0000 unimp + 1044: 0168 addi a0,sp,140 + 1046: 0000 unimp + 1048: 0001 nop + 104a: 6c5d lui s8,0x17 + 104c: 0002 c.slli64 zero + 104e: 7400 flw fs0,40(s0) + 1050: 0002 c.slli64 zero + 1052: 0100 addi s0,sp,128 + 1054: 5d00 lw s0,56(a0) + ... + 105e: 01cc addi a1,sp,196 + 1060: 0000 unimp + 1062: 01d8 addi a4,sp,196 + 1064: 0000 unimp + 1066: 0008 0x8 + 1068: 007c addi a5,sp,12 + 106a: 2440 fld fs0,136(s0) + 106c: 007e c.slli zero,0x1f + 106e: 9f21 0x9f21 + 1070: 01d8 addi a4,sp,196 + 1072: 0000 unimp + 1074: 01e0 addi s0,sp,204 + 1076: 0000 unimp + 1078: 0001 nop + 107a: 0058 addi a4,sp,4 + 107c: 0000 unimp + 107e: 0000 unimp + 1080: 0000 unimp + 1082: cc00 sw s0,24(s0) + 1084: 0001 nop + 1086: d400 sw s0,40(s0) + 1088: 0001 nop + 108a: 0600 addi s0,sp,768 + 108c: 7f00 flw fs0,56(a4) + 108e: 7d00 flw fs0,56(a0) + 1090: 1c00 addi s0,sp,560 + 1092: d49f 0001 dc00 0xdc000001d49f + 1098: 0001 nop + 109a: 0100 addi s0,sp,128 + 109c: 5f00 lw s0,56(a4) + ... + 10a6: 0144 addi s1,sp,132 + 10a8: 0000 unimp + 10aa: 01e0 addi s0,sp,204 + 10ac: 0000 unimp + 10ae: 0001 nop + 10b0: 0002685b 0x2685b + 10b4: 7400 flw fs0,40(s0) + 10b6: 0002 c.slli64 zero + 10b8: 0100 addi s0,sp,128 + 10ba: 5b00 lw s0,48(a4) + ... + 10c4: 0154 addi a3,sp,132 + 10c6: 0000 unimp + 10c8: 01d0 addi a2,sp,196 + 10ca: 0000 unimp + 10cc: 0001 nop + 10ce: d058 sw a4,36(s0) + 10d0: 0001 nop + 10d2: e000 fsw fs0,0(s0) + 10d4: 0001 nop + 10d6: 0500 addi s0,sp,640 + 10d8: 7b00 flw fs0,48(a4) + 10da: 4000 lw s0,0(s0) + 10dc: 9f25 0x9f25 + ... + 10e6: 0164 addi s1,sp,140 + 10e8: 0000 unimp + 10ea: 01ac addi a1,sp,200 + 10ec: 0000 unimp + 10ee: 0001 nop + 10f0: ac5f 0001 e000 0xe0000001ac5f + 10f6: 0001 nop + 10f8: 0700 addi s0,sp,896 + 10fa: 7b00 flw fs0,48(a4) + 10fc: 0a00 addi s0,sp,272 + 10fe: ffff 0xffff + 1100: 9f1a add t5,t5,t1 + ... + 110a: 0164 addi s1,sp,140 + 110c: 0000 unimp + 110e: 0188 addi a0,sp,192 + 1110: 0000 unimp + 1112: 0001 nop + 1114: 8861 andi s0,s0,24 + 1116: 0001 nop + 1118: e000 fsw fs0,0(s0) + 111a: 0001 nop + 111c: 0100 addi s0,sp,128 + 111e: 5c00 lw s0,56(s0) + ... + 1128: 01a0 addi s0,sp,200 + 112a: 0000 unimp + 112c: 01bc addi a5,sp,200 + 112e: 0000 unimp + 1130: 0001 nop + 1132: bc60 fsd fs0,248(s0) + 1134: 0001 nop + 1136: e000 fsw fs0,0(s0) + 1138: 0001 nop + 113a: 0100 addi s0,sp,128 + 113c: 5e00 lw s0,56(a2) + ... + 1146: 0164 addi s1,sp,140 + 1148: 0000 unimp + 114a: 016c addi a1,sp,140 + 114c: 0000 unimp + 114e: 0006 c.slli zero,0x1 + 1150: 00780083 lb ra,7(a6) # 17007 <_start-0x7ffe8ff9> + 1154: 9f1d 0x9f1d + 1156: 016c addi a1,sp,140 + 1158: 0000 unimp + 115a: 0178 addi a4,sp,140 + 115c: 0000 unimp + 115e: 0001 nop + 1160: 785e flw fa6,244(sp) + 1162: 0001 nop + 1164: 7c00 flw fs0,56(s0) + 1166: 0001 nop + 1168: 0600 addi s0,sp,768 + 116a: 8300 0x8300 + 116c: 7800 flw fs0,48(s0) + 116e: 1d00 addi s0,sp,688 + 1170: 7c9f 0001 8400 0x840000017c9f + 1176: 0001 nop + 1178: 0100 addi s0,sp,128 + 117a: 5e00 lw s0,56(a2) + 117c: 0184 addi s1,sp,192 + 117e: 0000 unimp + 1180: 0188 addi a0,sp,192 + 1182: 0000 unimp + 1184: 0083000b 0x83000b + 1188: 0078 addi a4,sp,12 + 118a: 401d c.li zero,7 + 118c: 7d24 flw fs1,120(a0) + 118e: 2100 fld fs0,0(a0) + 1190: 889f 0001 a400 0xa4000001889f + 1196: 0001 nop + 1198: 0100 addi s0,sp,128 + 119a: 5e00 lw s0,56(a2) + ... + 11a4: 019c addi a5,sp,192 + 11a6: 0000 unimp + 11a8: 01a4 addi s1,sp,200 + 11aa: 0000 unimp + 11ac: 0006 c.slli zero,0x1 + 11ae: 007e c.slli zero,0x1f + 11b0: 0078 addi a4,sp,12 + 11b2: 9f1d 0x9f1d + 11b4: 01a4 addi s1,sp,200 + 11b6: 0000 unimp + 11b8: 01ac addi a1,sp,200 + 11ba: 0000 unimp + 11bc: 0001 nop + 11be: ac5e fsd fs7,24(sp) + 11c0: 0001 nop + 11c2: b800 fsd fs0,48(s0) + 11c4: 0001 nop + 11c6: 0100 addi s0,sp,128 + 11c8: 5f00 lw s0,56(a4) + 11ca: 01bc addi a5,sp,200 + 11cc: 0000 unimp + 11ce: 01cc addi a1,sp,196 + 11d0: 0000 unimp + 11d2: 0001 nop + 11d4: cc5f 0001 d400 0xd4000001cc5f + 11da: 0001 nop + 11dc: 0600 addi s0,sp,768 + 11de: 7f00 flw fs0,56(a4) + 11e0: 7d00 flw fs0,56(a0) + 11e2: 1c00 addi s0,sp,560 + 11e4: d49f 0001 dc00 0xdc000001d49f + 11ea: 0001 nop + 11ec: 0100 addi s0,sp,128 + 11ee: 5f00 lw s0,56(a4) + ... + 11f8: 0174 addi a3,sp,140 + 11fa: 0000 unimp + 11fc: 01a0 addi s0,sp,200 + 11fe: 0000 unimp + 1200: 0001 nop + 1202: a060 fsd fs0,192(s0) + 1204: 0001 nop + 1206: a800 fsd fs0,16(s0) + 1208: 0001 nop + 120a: 0600 addi s0,sp,768 + 120c: 7f00 flw fs0,56(a4) + 120e: 8100 0x8100 + 1210: 1e00 addi s0,sp,816 + 1212: a89f 0001 e000 0xe0000001a89f + 1218: 0001 nop + 121a: 0100 addi s0,sp,128 + 121c: 5d00 lw s0,56(a0) + ... + 122a: 0028 addi a0,sp,8 + 122c: 0000 unimp + 122e: 0001 nop + 1230: 285a fld fa6,400(sp) + 1232: 0000 unimp + 1234: b400 fsd fs0,40(s0) + 1236: 0000 unimp + 1238: 0600 addi s0,sp,768 + 123a: f300 fsw fs0,32(a4) + 123c: 250af503 0x250af503 + 1240: 009f 0000 0000 0x9f + 1246: 0000 unimp + 1248: 0000 unimp + 124a: 0000 unimp + 124c: 2c00 fld fs0,24(s0) + 124e: 0000 unimp + 1250: 0100 addi s0,sp,128 + 1252: 5b00 lw s0,48(a4) + 1254: 002c addi a1,sp,8 + 1256: 0000 unimp + 1258: 00b4 addi a3,sp,72 + 125a: 0000 unimp + 125c: 0006 c.slli zero,0x1 + 125e: 0bf503f3 0xbf503f3 + 1262: 9f25 0x9f25 + ... + 1270: 0090 addi a2,sp,64 + 1272: 0000 unimp + 1274: 0002 c.slli64 zero + 1276: 9f30 0x9f30 + 1278: 0094 addi a3,sp,64 + 127a: 0000 unimp + 127c: 00b4 addi a3,sp,72 + 127e: 0000 unimp + 1280: 0002 c.slli64 zero + 1282: 9f30 0x9f30 + ... + 128c: 0028 addi a0,sp,8 + 128e: 0000 unimp + 1290: 0038 addi a4,sp,8 + 1292: 0000 unimp + 1294: 0001 nop + 1296: 3c5a fld fs8,432(sp) + 1298: 0000 unimp + 129a: 6400 flw fs0,8(s0) + 129c: 0000 unimp + 129e: 0100 addi s0,sp,128 + 12a0: 5a00 lw s0,48(a2) + 12a2: 0068 addi a0,sp,12 + 12a4: 0000 unimp + 12a6: 006c addi a1,sp,12 + 12a8: 0000 unimp + 12aa: 0001 nop + 12ac: 785a flw fa6,180(sp) + 12ae: 0000 unimp + 12b0: 8000 0x8000 + 12b2: 0000 unimp + 12b4: 0100 addi s0,sp,128 + 12b6: 5a00 lw s0,48(a2) + 12b8: 0084 addi s1,sp,64 + 12ba: 0000 unimp + 12bc: 0090 addi a2,sp,64 + 12be: 0000 unimp + 12c0: 0001 nop + 12c2: 945a add s0,s0,s6 + 12c4: 0000 unimp + 12c6: 9800 0x9800 + 12c8: 0000 unimp + 12ca: 0100 addi s0,sp,128 + 12cc: 5a00 lw s0,48(a2) + 12ce: 009c addi a5,sp,64 + 12d0: 0000 unimp + 12d2: 00b4 addi a3,sp,72 + 12d4: 0000 unimp + 12d6: 0001 nop + 12d8: 005a c.slli zero,0x16 + 12da: 0000 unimp + 12dc: 0000 unimp + 12de: 0000 unimp + 12e0: 9000 0x9000 + 12e2: 0000 unimp + 12e4: 9400 0x9400 + 12e6: 0000 unimp + 12e8: 0200 addi s0,sp,256 + 12ea: 3000 fld fs0,32(s0) + 12ec: 009f 0000 0000 0x9f + 12f2: 0000 unimp + 12f4: 4800 lw s0,16(s0) + 12f6: 0000 unimp + 12f8: 5400 lw s0,40(s0) + 12fa: 0000 unimp + 12fc: 0800 addi s0,sp,16 + 12fe: 7c00 flw fs0,56(s0) + 1300: 3000 fld fs0,32(s0) + 1302: 0829 addi a6,a6,10 + 1304: 1aff 0x1aff + 1306: 689f 0000 7800 0x78000000689f + 130c: 0000 unimp + 130e: 0800 addi s0,sp,16 + 1310: 7c00 flw fs0,56(s0) + 1312: 3000 fld fs0,32(s0) + 1314: 0829 addi a6,a6,10 + 1316: 1aff 0x1aff + 1318: 9c9f 0000 a400 0xa40000009c9f + 131e: 0000 unimp + 1320: 0800 addi s0,sp,16 + 1322: 7c00 flw fs0,56(s0) + 1324: 3000 fld fs0,32(s0) + 1326: 0829 addi a6,a6,10 + 1328: 1aff 0x1aff + 132a: a89f 0000 b400 0xb4000000a89f + 1330: 0000 unimp + 1332: 0200 addi s0,sp,256 + 1334: 3000 fld fs0,32(s0) + 1336: 009f 0000 0000 0x9f + 133c: 0000 unimp + 133e: 5000 lw s0,32(s0) + 1340: 0000 unimp + 1342: 5c00 lw s0,56(s0) + 1344: 0000 unimp + 1346: 0200 addi s0,sp,256 + 1348: 3000 fld fs0,32(s0) + 134a: 689f 0000 8c00 0x8c000000689f + 1350: 0000 unimp + 1352: 0200 addi s0,sp,256 + 1354: 3000 fld fs0,32(s0) + 1356: 9c9f 0000 a400 0xa40000009c9f + 135c: 0000 unimp + 135e: 0200 addi s0,sp,256 + 1360: 3100 fld fs0,32(a0) + 1362: 009f 0000 0000 0x9f + 1368: 0000 unimp + 136a: 0000 unimp + 136c: 0000 unimp + 136e: 5400 lw s0,40(s0) + 1370: 0000 unimp + 1372: 0100 addi s0,sp,128 + 1374: 5a00 lw s0,48(a2) + 1376: 0054 addi a3,sp,4 + 1378: 0000 unimp + 137a: 00c4 addi s1,sp,68 + 137c: 0000 unimp + 137e: 0006 c.slli zero,0x1 + 1380: 0af503f3 0xaf503f3 + 1384: 9f25 0x9f25 + 1386: 00c4 addi s1,sp,68 + 1388: 0000 unimp + 138a: 00cc addi a1,sp,68 + 138c: 0000 unimp + 138e: 0001 nop + 1390: cc5a sw s6,24(sp) + 1392: 0000 unimp + 1394: e400 fsw fs0,8(s0) + 1396: 0000 unimp + 1398: 0600 addi s0,sp,768 + 139a: f300 fsw fs0,32(a4) + 139c: 250af503 0x250af503 + 13a0: e49f 0000 0400 0x4000000e49f + 13a6: 0001 nop + 13a8: 0100 addi s0,sp,128 + 13aa: 5a00 lw s0,48(a2) + 13ac: 0104 addi s1,sp,128 + 13ae: 0000 unimp + 13b0: 02f8 addi a4,sp,332 + 13b2: 0000 unimp + 13b4: 0006 c.slli zero,0x1 + 13b6: 0af503f3 0xaf503f3 + 13ba: 9f25 0x9f25 + ... + 13c8: 0054 addi a3,sp,4 + 13ca: 0000 unimp + 13cc: 0001 nop + 13ce: 0000545b 0x545b + 13d2: 6c00 flw fs0,24(s0) + 13d4: 0000 unimp + 13d6: 0100 addi s0,sp,128 + 13d8: 6400 flw fs0,8(s0) + 13da: 006c addi a1,sp,12 + 13dc: 0000 unimp + 13de: 00c4 addi s1,sp,68 + 13e0: 0000 unimp + 13e2: 0006 c.slli zero,0x1 + 13e4: 0bf503f3 0xbf503f3 + 13e8: 9f25 0x9f25 + 13ea: 00c4 addi s1,sp,68 + 13ec: 0000 unimp + 13ee: 000000cf fnmadd.s ft1,ft0,ft0,ft0,rne + 13f2: 0001 nop + 13f4: 0000cf5b 0xcf5b + 13f8: e400 fsw fs0,8(s0) + 13fa: 0000 unimp + 13fc: 0100 addi s0,sp,128 + 13fe: 6400 flw fs0,8(s0) + 1400: 00e4 addi s1,sp,76 + 1402: 0000 unimp + 1404: 0104 addi s1,sp,128 + 1406: 0000 unimp + 1408: 0001 nop + 140a: 0001045b 0x1045b + 140e: f800 fsw fs0,48(s0) + 1410: 0002 c.slli64 zero + 1412: 0600 addi s0,sp,768 + 1414: f300 fsw fs0,32(a4) + 1416: 250bf503 0x250bf503 + 141a: 009f 0000 0000 0x9f + 1420: 0000 unimp + 1422: 0000 unimp + 1424: 0000 unimp + 1426: 5800 lw s0,48(s0) + 1428: 0000 unimp + 142a: 0200 addi s0,sp,256 + 142c: 3000 fld fs0,32(s0) + 142e: c49f 0000 0400 0x4000000c49f + 1434: 0001 nop + 1436: 0200 addi s0,sp,256 + 1438: 3000 fld fs0,32(s0) + 143a: 009f 0000 0000 0x9f + 1440: 0000 unimp + 1442: 5400 lw s0,40(s0) + 1444: 0000 unimp + 1446: 5800 lw s0,48(s0) + 1448: 0000 unimp + 144a: 0200 addi s0,sp,256 + 144c: 3000 fld fs0,32(s0) + 144e: 589f 0000 c400 0xc4000000589f + 1454: 0000 unimp + 1456: 0100 addi s0,sp,128 + 1458: 6500 flw fs0,8(a0) + 145a: 0104 addi s1,sp,128 + 145c: 0000 unimp + 145e: 02f0 addi a2,sp,332 + 1460: 0000 unimp + 1462: 0001 nop + 1464: 0065 c.nop 25 + 1466: 0000 unimp + 1468: 0000 unimp + 146a: 0000 unimp + 146c: 3800 fld fs0,48(s0) + 146e: 0000 unimp + 1470: e800 fsw fs0,16(s0) + 1472: 0002 c.slli64 zero + 1474: 0600 addi s0,sp,768 + 1476: 8300 0x8300 + 1478: 0800 addi s0,sp,16 + 147a: 1aff 0x1aff + 147c: 009f 0000 0000 0x9f + 1482: 0000 unimp + 1484: 3400 fld fs0,40(s0) + 1486: 0000 unimp + 1488: 5400 lw s0,40(s0) + 148a: 0000 unimp + 148c: 0600 addi s0,sp,768 + 148e: 8200 0x8200 + 1490: 0800 addi s0,sp,16 + 1492: 1aff 0x1aff + 1494: 549f 0000 c400 0xc4000000549f + 149a: 0000 unimp + 149c: 0100 addi s0,sp,128 + 149e: 6200 flw fs0,0(a2) + 14a0: 00c4 addi s1,sp,68 + 14a2: 0000 unimp + 14a4: 00d8 addi a4,sp,68 + 14a6: 0000 unimp + 14a8: 0006 c.slli zero,0x1 + 14aa: 0082 c.slli64 ra + 14ac: ff08 fsw fa0,56(a4) + 14ae: 9f1a add t5,t5,t1 + 14b0: 00e4 addi s1,sp,76 + 14b2: 0000 unimp + 14b4: 00e8 addi a0,sp,76 + 14b6: 0000 unimp + 14b8: 0006 c.slli zero,0x1 + 14ba: 0082 c.slli64 ra + 14bc: ff08 fsw fa0,56(a4) + 14be: 9f1a add t5,t5,t1 + 14c0: 00e8 addi a0,sp,76 + 14c2: 0000 unimp + 14c4: 00f8 addi a4,sp,76 + 14c6: 0000 unimp + 14c8: 0008 0x8 + 14ca: 007a c.slli zero,0x1e + 14cc: ff082547 fmsub.q fa0,fa6,fa6,ft11,rdn + 14d0: 9f1a add t5,t5,t1 + 14d2: 00f8 addi a4,sp,76 + 14d4: 0000 unimp + 14d6: 00fc addi a5,sp,76 + 14d8: 0000 unimp + 14da: 0006 c.slli zero,0x1 + 14dc: 0082 c.slli64 ra + 14de: ff08 fsw fa0,56(a4) + 14e0: 9f1a add t5,t5,t1 + 14e2: 00fc addi a5,sp,76 + 14e4: 0000 unimp + 14e6: 0104 addi s1,sp,128 + 14e8: 0000 unimp + 14ea: 0008 0x8 + 14ec: 007a c.slli zero,0x1e + 14ee: ff082547 fmsub.q fa0,fa6,fa6,ft11,rdn + 14f2: 9f1a add t5,t5,t1 + 14f4: 0104 addi s1,sp,128 + 14f6: 0000 unimp + 14f8: 02e4 addi s1,sp,332 + 14fa: 0000 unimp + 14fc: 0001 nop + 14fe: 0062 c.slli zero,0x18 + 1500: 0000 unimp + 1502: 0000 unimp + 1504: 0000 unimp + 1506: 3400 fld fs0,40(s0) + 1508: 0000 unimp + 150a: 4400 lw s0,8(s0) + 150c: 0000 unimp + 150e: 0100 addi s0,sp,128 + 1510: 5900 lw s0,48(a0) + 1512: 0044 addi s1,sp,4 + 1514: 0000 unimp + 1516: 0048 addi a0,sp,4 + 1518: 0000 unimp + 151a: 00790007 0x790007 + 151e: 4340 lw s0,4(a4) + 1520: 2124 fld fs1,64(a0) + 1522: 489f 0000 5000 0x50000000489f + 1528: 0000 unimp + 152a: 0b00 addi s0,sp,400 + 152c: 7a00 flw fs0,48(a2) + 152e: 3900 fld fs0,48(a0) + 1530: 3924 fld fs1,112(a0) + 1532: 4025 c.li zero,9 + 1534: 9f212443 fmadd.q fs0,ft2,fs2,fs3,rdn + 1538: 0050 addi a2,sp,4 + 153a: 0000 unimp + 153c: 0158 addi a4,sp,132 + 153e: 0000 unimp + 1540: 0001 nop + 1542: 1459 addi s0,s0,-10 + 1544: 0002 c.slli64 zero + 1546: 3800 fld fs0,48(s0) + 1548: 0002 c.slli64 zero + 154a: 0100 addi s0,sp,128 + 154c: 5900 lw s0,48(a0) + 154e: 0244 addi s1,sp,260 + 1550: 0000 unimp + 1552: 024c addi a1,sp,260 + 1554: 0000 unimp + 1556: 0001 nop + 1558: a859 j 15ee <_start-0x7fffea12> + 155a: 0002 c.slli64 zero + 155c: b400 fsd fs0,40(s0) + 155e: 0002 c.slli64 zero + 1560: 0100 addi s0,sp,128 + 1562: 5900 lw s0,48(a0) + ... + 156c: 0088 addi a0,sp,64 + 156e: 0000 unimp + 1570: 008c addi a1,sp,64 + 1572: 0000 unimp + 1574: 0002 c.slli64 zero + 1576: 9f30 0x9f30 + 1578: 008c addi a1,sp,64 + 157a: 0000 unimp + 157c: 00c4 addi s1,sp,68 + 157e: 0000 unimp + 1580: 0001 nop + 1582: 445e lw s0,212(sp) + 1584: 0001 nop + 1586: 4800 lw s0,16(s0) + 1588: 0001 nop + 158a: 0100 addi s0,sp,128 + 158c: 5e00 lw s0,56(a2) + 158e: 0214 addi a3,sp,256 + 1590: 0000 unimp + 1592: 0220 addi s0,sp,264 + 1594: 0000 unimp + 1596: 0001 nop + 1598: 445e lw s0,212(sp) + 159a: 0002 c.slli64 zero + 159c: 4c00 lw s0,24(s0) + 159e: 0002 c.slli64 zero + 15a0: 0100 addi s0,sp,128 + 15a2: 5e00 lw s0,56(a2) + ... + 15ac: 006c addi a1,sp,12 + 15ae: 0000 unimp + 15b0: 00c4 addi s1,sp,68 + 15b2: 0000 unimp + 15b4: 0006 c.slli zero,0x1 + 15b6: 0084 addi s1,sp,64 + 15b8: ff08 fsw fa0,56(a4) + 15ba: 9f1a add t5,t5,t1 + 15bc: 0104 addi s1,sp,128 + 15be: 0000 unimp + 15c0: 02ec addi a1,sp,332 + 15c2: 0000 unimp + 15c4: 0006 c.slli zero,0x1 + 15c6: 0084 addi s1,sp,64 + 15c8: ff08 fsw fa0,56(a4) + 15ca: 9f1a add t5,t5,t1 + ... + 15d4: 0068 addi a0,sp,12 + 15d6: 0000 unimp + 15d8: 0088 addi a0,sp,64 + 15da: 0000 unimp + 15dc: 0006 c.slli zero,0x1 + 15de: 007f 0x7f + 15e0: ff08 fsw fa0,56(a4) + 15e2: 9f1a add t5,t5,t1 + 15e4: 0088 addi a0,sp,64 + 15e6: 0000 unimp + 15e8: 0098 addi a4,sp,64 + 15ea: 0000 unimp + 15ec: 0001 nop + 15ee: 045f 0001 0f00 0xf000001045f + 15f4: 0001 nop + 15f6: 0600 addi s0,sp,768 + 15f8: 7f00 flw fs0,56(a4) + 15fa: 0800 addi s0,sp,16 + 15fc: 1aff 0x1aff + 15fe: 249f 0001 2800 0x28000001249f + 1604: 0001 nop + 1606: 0600 addi s0,sp,768 + 1608: 7f00 flw fs0,56(a4) + 160a: 0800 addi s0,sp,16 + 160c: 1aff 0x1aff + 160e: 389f 0001 3c00 0x3c000001389f + 1614: 0001 nop + 1616: 0600 addi s0,sp,768 + 1618: 7f00 flw fs0,56(a4) + 161a: 0800 addi s0,sp,16 + 161c: 1aff 0x1aff + 161e: 009f 0000 0000 0x9f + 1624: 0000 unimp + 1626: 6800 flw fs0,16(s0) + 1628: 0000 unimp + 162a: 7800 flw fs0,48(s0) + 162c: 0000 unimp + 162e: 0100 addi s0,sp,128 + 1630: 5800 lw s0,48(s0) + 1632: 0078 addi a4,sp,12 + 1634: 0000 unimp + 1636: 007c addi a5,sp,12 + 1638: 0000 unimp + 163a: 00780007 0x780007 + 163e: 4340 lw s0,4(a4) + 1640: 2124 fld fs1,64(a0) + 1642: 849f 0000 c400 0xc4000000849f + 1648: 0000 unimp + 164a: 0100 addi s0,sp,128 + 164c: 5800 lw s0,48(s0) + 164e: 0104 addi s1,sp,128 + 1650: 0000 unimp + 1652: 015c addi a5,sp,132 + 1654: 0000 unimp + 1656: 0001 nop + 1658: 1458 addi a4,sp,548 + 165a: 0002 c.slli64 zero + 165c: 1c00 addi s0,sp,560 + 165e: 0002 c.slli64 zero + 1660: 0100 addi s0,sp,128 + 1662: 5800 lw s0,48(s0) + 1664: 0244 addi s1,sp,260 + 1666: 0000 unimp + 1668: 024c addi a1,sp,260 + 166a: 0000 unimp + 166c: 0001 nop + 166e: 0058 addi a4,sp,4 + 1670: 0000 unimp + 1672: 0000 unimp + 1674: 0000 unimp + 1676: 4400 lw s0,8(s0) + 1678: 0001 nop + 167a: c400 sw s0,8(s0) + 167c: 0001 nop + 167e: 0200 addi s0,sp,256 + 1680: 3000 fld fs0,32(s0) + 1682: 209f 0002 3800 0x38000002209f + 1688: 0002 c.slli64 zero + 168a: 0100 addi s0,sp,128 + 168c: 5e00 lw s0,56(a2) + 168e: 024c addi a1,sp,260 + 1690: 0000 unimp + 1692: 0254 addi a3,sp,260 + 1694: 0000 unimp + 1696: 0002 c.slli64 zero + 1698: 9f30 0x9f30 + ... + 16a2: 00a4 addi s1,sp,72 + 16a4: 0000 unimp + 16a6: 00c4 addi s1,sp,68 + 16a8: 0000 unimp + 16aa: 0001 nop + 16ac: 445a lw s0,148(sp) + 16ae: 0001 nop + 16b0: 1800 addi s0,sp,48 + 16b2: 0002 c.slli64 zero + 16b4: 0100 addi s0,sp,128 + 16b6: 5a00 lw s0,48(a2) + 16b8: 0218 addi a4,sp,256 + 16ba: 0000 unimp + 16bc: 0220 addi s0,sp,264 + 16be: 0000 unimp + 16c0: 0006 c.slli zero,0x1 + 16c2: ff080083 lb ra,-16(a6) + 16c6: 9f1a add t5,t5,t1 + 16c8: 0220 addi s0,sp,264 + 16ca: 0000 unimp + 16cc: 0248 addi a0,sp,260 + 16ce: 0000 unimp + 16d0: 0001 nop + 16d2: 485a lw a6,148(sp) + 16d4: 0002 c.slli64 zero + 16d6: 4c00 lw s0,24(s0) + 16d8: 0002 c.slli64 zero + 16da: 0600 addi s0,sp,768 + 16dc: 8400 0x8400 + 16de: 0800 addi s0,sp,16 + 16e0: 1aff 0x1aff + 16e2: 4c9f 0002 d000 0xd00000024c9f + 16e8: 0002 c.slli64 zero + 16ea: 0100 addi s0,sp,128 + 16ec: 5a00 lw s0,48(a2) + ... + 16f6: 00a8 addi a0,sp,72 + 16f8: 0000 unimp + 16fa: 00c4 addi s1,sp,68 + 16fc: 0000 unimp + 16fe: 0001 nop + 1700: 445c lw a5,12(s0) + 1702: 0001 nop + 1704: c800 sw s0,16(s0) + 1706: 0001 nop + 1708: 0100 addi s0,sp,128 + 170a: 5c00 lw s0,56(s0) + 170c: 01c8 addi a0,sp,196 + 170e: 0000 unimp + 1710: 0208 addi a0,sp,256 + 1712: 0000 unimp + 1714: 0001 nop + 1716: 145e slli s0,s0,0x37 + 1718: 0002 c.slli64 zero + 171a: 3800 fld fs0,48(s0) + 171c: 0002 c.slli64 zero + 171e: 0100 addi s0,sp,128 + 1720: 5c00 lw s0,56(s0) + 1722: 0244 addi s1,sp,260 + 1724: 0000 unimp + 1726: 0250 addi a2,sp,260 + 1728: 0000 unimp + 172a: 0001 nop + 172c: 505c lw a5,36(s0) + 172e: 0002 c.slli64 zero + 1730: 5400 lw s0,40(s0) + 1732: 0002 c.slli64 zero + 1734: 0300 addi s0,sp,384 + 1736: 7f00 flw fs0,56(a4) + 1738: 9f01 0x9f01 + 173a: 0254 addi a3,sp,260 + 173c: 0000 unimp + 173e: 025c addi a5,sp,260 + 1740: 0000 unimp + 1742: 0001 nop + 1744: 5c5e lw s8,244(sp) + 1746: 0002 c.slli64 zero + 1748: 6c00 flw fs0,24(s0) + 174a: 0002 c.slli64 zero + 174c: 0100 addi s0,sp,128 + 174e: 5f00 lw s0,56(a4) + 1750: 026c addi a1,sp,268 + 1752: 0000 unimp + 1754: 02a4 addi s1,sp,328 + 1756: 0000 unimp + 1758: 0006 c.slli zero,0x1 + 175a: 2008 fld fa0,0(s0) + 175c: 007c addi a5,sp,12 + 175e: 9f1c 0x9f1c + 1760: 02a4 addi s1,sp,328 + 1762: 0000 unimp + 1764: 02a8 addi a0,sp,328 + 1766: 0000 unimp + 1768: 0008 0x8 + 176a: 007e c.slli zero,0x1f + 176c: 007c addi a5,sp,12 + 176e: 231c fld fa5,0(a4) + 1770: 9f1f 02a8 0000 0x2a89f1f + 1776: 02b4 addi a3,sp,328 + 1778: 0000 unimp + 177a: 0001 nop + 177c: b45c fsd fa5,168(s0) + 177e: 0002 c.slli64 zero + 1780: b800 fsd fs0,48(s0) + 1782: 0002 c.slli64 zero + 1784: 0100 addi s0,sp,128 + 1786: 5e00 lw s0,56(a2) + ... + 1790: 01b0 addi a2,sp,200 + 1792: 0000 unimp + 1794: 01c0 addi s0,sp,196 + 1796: 0000 unimp + 1798: 0001 nop + 179a: c458 sw a4,12(s0) + 179c: 0001 nop + 179e: fc00 fsw fs0,56(s0) + 17a0: 0001 nop + 17a2: 0100 addi s0,sp,128 + 17a4: 5800 lw s0,48(s0) + 17a6: 01fc addi a5,sp,204 + 17a8: 0000 unimp + 17aa: 0204 addi s1,sp,256 + 17ac: 0000 unimp + 17ae: 0005 c.nop 1 + 17b0: 0078 addi a4,sp,12 + 17b2: 049f2533 0x49f2533 + 17b6: 0002 c.slli64 zero + 17b8: 0c00 addi s0,sp,528 + 17ba: 0002 c.slli64 zero + 17bc: 0100 addi s0,sp,128 + 17be: 5800 lw s0,48(s0) + 17c0: 0220 addi s0,sp,264 + 17c2: 0000 unimp + 17c4: 023c addi a5,sp,264 + 17c6: 0000 unimp + 17c8: 0001 nop + 17ca: 4c58 lw a4,28(s0) + 17cc: 0002 c.slli64 zero + 17ce: 7000 flw fs0,32(s0) + 17d0: 0002 c.slli64 zero + 17d2: 0100 addi s0,sp,128 + 17d4: 5800 lw s0,48(s0) + 17d6: 0278 addi a4,sp,268 + 17d8: 0000 unimp + 17da: 0298 addi a4,sp,320 + 17dc: 0000 unimp + 17de: 0001 nop + 17e0: b458 fsd fa4,168(s0) + 17e2: 0002 c.slli64 zero + 17e4: c000 sw s0,0(s0) + 17e6: 0002 c.slli64 zero + 17e8: 0100 addi s0,sp,128 + 17ea: 5800 lw s0,48(s0) + ... + 17f4: 02d0 addi a2,sp,324 + 17f6: 0000 unimp + 17f8: 02d8 addi a4,sp,324 + 17fa: 0000 unimp + 17fc: 0008 0x8 + 17fe: 0078 addi a4,sp,12 + 1800: 007a c.slli zero,0x1e + 1802: f921 bnez a0,1752 <_start-0x7fffe8ae> + 1804: 9f25 0x9f25 + 1806: 02d8 addi a4,sp,324 + 1808: 0000 unimp + 180a: 02f8 addi a4,sp,332 + 180c: 0000 unimp + 180e: 0001 nop + 1810: 005a c.slli zero,0x16 + 1812: 0000 unimp + 1814: 0000 unimp + 1816: 0000 unimp + 1818: d000 sw s0,32(s0) + 181a: 0000 unimp + 181c: e400 fsw fs0,8(s0) + 181e: 0000 unimp + 1820: 0300 addi s0,sp,384 + 1822: 7a00 flw fs0,48(a2) + 1824: 9f78 0x9f78 + ... + 182e: 0110 addi a2,sp,128 + 1830: 0000 unimp + 1832: 0124 addi s1,sp,136 + 1834: 0000 unimp + 1836: 787a0003 lb zero,1927(s4) + 183a: 009f 0000 0000 0x9f + 1840: 0000 unimp + 1842: 9000 0x9000 + 1844: 0001 nop + 1846: a000 fsd fs0,0(s0) + 1848: 0001 nop + 184a: 0100 addi s0,sp,128 + 184c: 5e00 lw s0,56(a2) + 184e: 01b0 addi a2,sp,200 + 1850: 0000 unimp + 1852: 01c0 addi s0,sp,196 + 1854: 0000 unimp + 1856: 0001 nop + 1858: 4c58 lw a4,28(s0) + 185a: 0002 c.slli64 zero + 185c: 5400 lw s0,40(s0) + 185e: 0002 c.slli64 zero + 1860: 0100 addi s0,sp,128 + 1862: 5800 lw s0,48(s0) + ... + 186c: 0180 addi s0,sp,192 + 186e: 0000 unimp + 1870: 0198 addi a4,sp,192 + 1872: 0000 unimp + 1874: 0008 0x8 + 1876: 0079 c.nop 30 + 1878: 2540 fld fs0,136(a0) + 187a: 007d c.nop 31 + 187c: 9f22 add t5,t5,s0 + 187e: 01a4 addi s1,sp,200 + 1880: 0000 unimp + 1882: 01ac addi a1,sp,200 + 1884: 0000 unimp + 1886: 0001 nop + 1888: 0059 c.nop 22 + 188a: 0000 unimp + 188c: 0000 unimp + 188e: 0000 unimp + 1890: 6000 flw fs0,0(s0) + 1892: 0001 nop + 1894: 8c00 0x8c00 + 1896: 0001 nop + 1898: 0100 addi s0,sp,128 + 189a: 6000 flw fs0,0(s0) + ... + 18a4: 0160 addi s0,sp,140 + 18a6: 0000 unimp + 18a8: 016c addi a1,sp,140 + 18aa: 0000 unimp + 18ac: 0006 c.slli zero,0x1 + 18ae: 0079007b 0x79007b + 18b2: 9f1e add t5,t5,t2 + 18b4: 016c addi a1,sp,140 + 18b6: 0000 unimp + 18b8: 0174 addi a3,sp,140 + 18ba: 0000 unimp + 18bc: 0001 nop + 18be: 0001785b 0x1785b + 18c2: 9800 0x9800 + 18c4: 0001 nop + 18c6: 0100 addi s0,sp,128 + 18c8: 5900 lw s0,48(a0) + ... + 18d2: 0164 addi s1,sp,140 + 18d4: 0000 unimp + 18d6: 0194 addi a3,sp,192 + 18d8: 0000 unimp + 18da: 0001 nop + 18dc: 0058 addi a4,sp,4 + 18de: 0000 unimp + 18e0: 0000 unimp + 18e2: 0000 unimp + 18e4: 6800 flw fs0,16(s0) + 18e6: 0001 nop + 18e8: c400 sw s0,8(s0) + 18ea: 0001 nop + 18ec: 0100 addi s0,sp,128 + 18ee: 5d00 lw s0,56(a0) + 18f0: 024c addi a1,sp,260 + 18f2: 0000 unimp + 18f4: 0254 addi a3,sp,260 + 18f6: 0000 unimp + 18f8: 0001 nop + 18fa: 005d c.nop 23 + 18fc: 0000 unimp + 18fe: 0000 unimp + 1900: 0000 unimp + 1902: 4400 lw s0,8(s0) + 1904: 0001 nop + 1906: 5800 lw s0,48(s0) + 1908: 0001 nop + 190a: 0100 addi s0,sp,128 + 190c: 5900 lw s0,48(a0) + ... + 1916: 0150 addi a2,sp,132 + 1918: 0000 unimp + 191a: 015c addi a5,sp,132 + 191c: 0000 unimp + 191e: 0001 nop + 1920: 0058 addi a4,sp,4 + 1922: 0000 unimp + 1924: 0000 unimp + 1926: 0000 unimp + 1928: 5000 lw s0,32(s0) + 192a: 0001 nop + 192c: 6800 flw fs0,16(s0) + 192e: 0001 nop + 1930: 0100 addi s0,sp,128 + 1932: 5d00 lw s0,56(a0) + ... + 193c: 0154 addi a3,sp,132 + 193e: 0000 unimp + 1940: 016c addi a1,sp,140 + 1942: 0000 unimp + 1944: 0001 nop + 1946: 0000005b 0x5b + ... + 1952: 3c00 fld fs0,56(s0) + 1954: 0000 unimp + 1956: 0100 addi s0,sp,128 + 1958: 5a00 lw s0,48(a2) + 195a: 003c addi a5,sp,8 + 195c: 0000 unimp + 195e: 044c addi a1,sp,516 + 1960: 0000 unimp + 1962: 0006 c.slli zero,0x1 + 1964: 0af503f3 0xaf503f3 + 1968: 9f25 0x9f25 + ... + 1976: 004c addi a1,sp,4 + 1978: 0000 unimp + 197a: 0001 nop + 197c: 00004c5b 0x4c5b + 1980: 4c00 lw s0,24(s0) + 1982: 0004 0x4 + 1984: 0600 addi s0,sp,768 + 1986: f300 fsw fs0,32(a4) + 1988: 250bf503 0x250bf503 + 198c: 009f 0000 0000 0x9f + 1992: 0000 unimp + 1994: 0000 unimp + 1996: 0000 unimp + 1998: b800 fsd fs0,48(s0) + 199a: 0000 unimp + 199c: 0200 addi s0,sp,256 + 199e: 3000 fld fs0,32(s0) + 19a0: c09f 0000 2400 0x24000000c09f + 19a6: 0001 nop + 19a8: 0200 addi s0,sp,256 + 19aa: 3000 fld fs0,32(s0) + 19ac: 2c9f 0001 9c00 0x9c0000012c9f + 19b2: 0001 nop + 19b4: 0200 addi s0,sp,256 + 19b6: 3000 fld fs0,32(s0) + 19b8: c49f 0001 9400 0x94000001c49f + 19be: 0002 c.slli64 zero + 19c0: 0200 addi s0,sp,256 + 19c2: 3000 fld fs0,32(s0) + 19c4: a09f 0002 2800 0x28000002a09f + 19ca: 02000003 lb zero,32(zero) # 20 <_start-0x7fffffe0> + 19ce: 3000 fld fs0,32(s0) + 19d0: 409f 0003 cc00 0xcc000003409f + 19d6: 02000003 lb zero,32(zero) # 20 <_start-0x7fffffe0> + 19da: 3000 fld fs0,32(s0) + 19dc: 3c9f 0004 4400 0x440000043c9f + 19e2: 0004 0x4 + 19e4: 0200 addi s0,sp,256 + 19e6: 3000 fld fs0,32(s0) + 19e8: 009f 0000 0000 0x9f + 19ee: 0000 unimp + 19f0: 4000 lw s0,0(s0) + 19f2: 0000 unimp + 19f4: b800 fsd fs0,48(s0) + 19f6: 0000 unimp + 19f8: 0100 addi s0,sp,128 + 19fa: 5900 lw s0,48(a0) + 19fc: 00c0 addi s0,sp,68 + 19fe: 0000 unimp + 1a00: 019c addi a5,sp,192 + 1a02: 0000 unimp + 1a04: 0001 nop + 1a06: b859 j 129c <_start-0x7fffed64> + 1a08: 0001 nop + 1a0a: f800 fsw fs0,48(s0) + 1a0c: 0001 nop + 1a0e: 0100 addi s0,sp,128 + 1a10: 5900 lw s0,48(a0) + 1a12: 0214 addi a3,sp,256 + 1a14: 0000 unimp + 1a16: 0288 addi a0,sp,320 + 1a18: 0000 unimp + 1a1a: 0001 nop + 1a1c: 8c59 or s0,s0,a4 + 1a1e: 0002 c.slli64 zero + 1a20: 9c00 0x9c00 + 1a22: 0002 c.slli64 zero + 1a24: 0100 addi s0,sp,128 + 1a26: 5900 lw s0,48(a0) + 1a28: 02a0 addi s0,sp,328 + 1a2a: 0000 unimp + 1a2c: 0314 addi a3,sp,384 + 1a2e: 0000 unimp + 1a30: 0001 nop + 1a32: 1859 addi a6,a6,-10 + 1a34: 24000003 lb zero,576(zero) # 240 <_start-0x7ffffdc0> + 1a38: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> + 1a3c: 5900 lw s0,48(a0) + 1a3e: 0328 addi a0,sp,392 + 1a40: 0000 unimp + 1a42: 0334 addi a3,sp,392 + 1a44: 0000 unimp + 1a46: 0001 nop + 1a48: 4059 c.li zero,22 + 1a4a: 54000003 lb zero,1344(zero) # 540 <_start-0x7ffffac0> + 1a4e: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> + 1a52: 5900 lw s0,48(a0) + 1a54: 0390 addi a2,sp,448 + 1a56: 0000 unimp + 1a58: 03a0 addi s0,sp,456 + 1a5a: 0000 unimp + 1a5c: 0001 nop + 1a5e: b459 j 14e4 <_start-0x7fffeb1c> + 1a60: cc000003 lb zero,-832(zero) # fffffcc0 <__global_pointer$+0x7fffc058> + 1a64: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> + 1a68: 5900 lw s0,48(a0) + 1a6a: 043c addi a5,sp,520 + 1a6c: 0000 unimp + 1a6e: 0444 addi s1,sp,516 + 1a70: 0000 unimp + 1a72: 0001 nop + 1a74: 0059 c.nop 22 + 1a76: 0000 unimp + 1a78: 0000 unimp + 1a7a: 0000 unimp + 1a7c: 4000 lw s0,0(s0) + 1a7e: 0000 unimp + 1a80: 8000 0x8000 + 1a82: 0000 unimp + 1a84: 0100 addi s0,sp,128 + 1a86: 5c00 lw s0,56(s0) + 1a88: 0080 addi s0,sp,64 + 1a8a: 0000 unimp + 1a8c: 00b0 addi a2,sp,72 + 1a8e: 0000 unimp + 1a90: 0001 nop + 1a92: b062 fsd fs8,32(sp) + 1a94: 0000 unimp + 1a96: b800 fsd fs0,48(s0) + 1a98: 0000 unimp + 1a9a: 0100 addi s0,sp,128 + 1a9c: 5c00 lw s0,56(s0) + 1a9e: 00b8 addi a4,sp,72 + 1aa0: 0000 unimp + 1aa2: 00c0 addi s0,sp,68 + 1aa4: 0000 unimp + 1aa6: 0001 nop + 1aa8: c062 sw s8,0(sp) + 1aaa: 0000 unimp + 1aac: 2000 fld fs0,0(s0) + 1aae: 0001 nop + 1ab0: 0100 addi s0,sp,128 + 1ab2: 5c00 lw s0,56(s0) + 1ab4: 0120 addi s0,sp,136 + 1ab6: 0000 unimp + 1ab8: 012c addi a1,sp,136 + 1aba: 0000 unimp + 1abc: 0001 nop + 1abe: 2c62 fld fs8,24(sp) + 1ac0: 0001 nop + 1ac2: 3000 fld fs0,32(s0) + 1ac4: 0001 nop + 1ac6: 0100 addi s0,sp,128 + 1ac8: 5c00 lw s0,56(s0) + 1aca: 0130 addi a2,sp,136 + 1acc: 0000 unimp + 1ace: 0168 addi a0,sp,140 + 1ad0: 0000 unimp + 1ad2: 0001 nop + 1ad4: 6862 flw fa6,24(sp) + 1ad6: 0001 nop + 1ad8: 9c00 0x9c00 + 1ada: 0001 nop + 1adc: 0100 addi s0,sp,128 + 1ade: 5c00 lw s0,56(s0) + 1ae0: 01b8 addi a4,sp,200 + 1ae2: 0000 unimp + 1ae4: 01f8 addi a4,sp,204 + 1ae6: 0000 unimp + 1ae8: 0001 nop + 1aea: f85c fsw fa5,52(s0) + 1aec: 0001 nop + 1aee: 1000 addi s0,sp,32 + 1af0: 0002 c.slli64 zero + 1af2: 0100 addi s0,sp,128 + 1af4: 6200 flw fs0,0(a2) + 1af6: 0214 addi a3,sp,256 + 1af8: 0000 unimp + 1afa: 0284 addi s1,sp,320 + 1afc: 0000 unimp + 1afe: 0001 nop + 1b00: 845c 0x845c + 1b02: 0002 c.slli64 zero + 1b04: 8c00 0x8c00 + 1b06: 0002 c.slli64 zero + 1b08: 0100 addi s0,sp,128 + 1b0a: 6200 flw fs0,0(a2) + 1b0c: 028c addi a1,sp,320 + 1b0e: 0000 unimp + 1b10: 0290 addi a2,sp,320 + 1b12: 0000 unimp + 1b14: 0001 nop + 1b16: 905c 0x905c + 1b18: 0002 c.slli64 zero + 1b1a: a000 fsd fs0,0(s0) + 1b1c: 0002 c.slli64 zero + 1b1e: 0100 addi s0,sp,128 + 1b20: 6200 flw fs0,0(a2) + 1b22: 02a0 addi s0,sp,328 + 1b24: 0000 unimp + 1b26: 02a4 addi s1,sp,328 + 1b28: 0000 unimp + 1b2a: 0001 nop + 1b2c: a45c fsd fa5,136(s0) + 1b2e: 0002 c.slli64 zero + 1b30: dc00 sw s0,56(s0) + 1b32: 0002 c.slli64 zero + 1b34: 0100 addi s0,sp,128 + 1b36: 6200 flw fs0,0(a2) + 1b38: 02dc addi a5,sp,324 + 1b3a: 0000 unimp + 1b3c: 0304 addi s1,sp,384 + 1b3e: 0000 unimp + 1b40: 0001 nop + 1b42: 045c addi a5,sp,516 + 1b44: 28000003 lb zero,640(zero) # 280 <_start-0x7ffffd80> + 1b48: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> + 1b4c: 6200 flw fs0,0(a2) + 1b4e: 0328 addi a0,sp,392 + 1b50: 0000 unimp + 1b52: 0354 addi a3,sp,388 + 1b54: 0000 unimp + 1b56: 0001 nop + 1b58: 905c 0x905c + 1b5a: a0000003 lb zero,-1536(zero) # fffffa00 <__global_pointer$+0x7fffbd98> + 1b5e: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> + 1b62: 5c00 lw s0,56(s0) + 1b64: 03b4 addi a3,sp,456 + 1b66: 0000 unimp + 1b68: 03c8 addi a0,sp,452 + 1b6a: 0000 unimp + 1b6c: 0001 nop + 1b6e: c85c sw a5,20(s0) + 1b70: cc000003 lb zero,-832(zero) # fffffcc0 <__global_pointer$+0x7fffc058> + 1b74: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> + 1b78: 6200 flw fs0,0(a2) + 1b7a: 043c addi a5,sp,520 + 1b7c: 0000 unimp + 1b7e: 0444 addi s1,sp,516 + 1b80: 0000 unimp + 1b82: 0001 nop + 1b84: 0062 c.slli zero,0x18 + 1b86: 0000 unimp + 1b88: 0000 unimp + 1b8a: 0000 unimp + 1b8c: 1800 addi s0,sp,48 + 1b8e: 0000 unimp + 1b90: 7c00 flw fs0,56(s0) + 1b92: 0000 unimp + 1b94: 0100 addi s0,sp,128 + 1b96: 5f00 lw s0,56(a4) + 1b98: 00b0 addi a2,sp,72 + 1b9a: 0000 unimp + 1b9c: 00b8 addi a4,sp,72 + 1b9e: 0000 unimp + 1ba0: 0001 nop + 1ba2: c05f 0000 f800 0xf8000000c05f + 1ba8: 0000 unimp + 1baa: 0100 addi s0,sp,128 + 1bac: 5f00 lw s0,56(a4) + 1bae: 00fc addi a5,sp,76 + 1bb0: 0000 unimp + 1bb2: 0118 addi a4,sp,128 + 1bb4: 0000 unimp + 1bb6: 0001 nop + 1bb8: 1c5f 0001 2800 0x280000011c5f + 1bbe: 0001 nop + 1bc0: 0100 addi s0,sp,128 + 1bc2: 5f00 lw s0,56(a4) + 1bc4: 012c addi a1,sp,136 + 1bc6: 0000 unimp + 1bc8: 0158 addi a4,sp,132 + 1bca: 0000 unimp + 1bcc: 0001 nop + 1bce: 605f 0001 6800 0x68000001605f + 1bd4: 0001 nop + 1bd6: 0100 addi s0,sp,128 + 1bd8: 5c00 lw s0,56(s0) + 1bda: 0168 addi a0,sp,140 + 1bdc: 0000 unimp + 1bde: 0184 addi s1,sp,192 + 1be0: 0000 unimp + 1be2: 0001 nop + 1be4: b85f 0001 d000 0xd0000001b85f + 1bea: 0001 nop + 1bec: 0100 addi s0,sp,128 + 1bee: 5f00 lw s0,56(a4) + 1bf0: 01dc addi a5,sp,196 + 1bf2: 0000 unimp + 1bf4: 01f8 addi a4,sp,204 + 1bf6: 0000 unimp + 1bf8: 0001 nop + 1bfa: 145f 0002 4800 0x48000002145f + 1c00: 0002 c.slli64 zero + 1c02: 0100 addi s0,sp,128 + 1c04: 5f00 lw s0,56(a4) + 1c06: 0250 addi a2,sp,260 + 1c08: 0000 unimp + 1c0a: 0284 addi s1,sp,320 + 1c0c: 0000 unimp + 1c0e: 0001 nop + 1c10: 8c5f 0002 9800 0x980000028c5f + 1c16: 0002 c.slli64 zero + 1c18: 0100 addi s0,sp,128 + 1c1a: 5f00 lw s0,56(a4) + 1c1c: 02a0 addi s0,sp,328 + 1c1e: 0000 unimp + 1c20: 02cc addi a1,sp,324 + 1c22: 0000 unimp + 1c24: 0001 nop + 1c26: d45f 0002 dc00 0xdc000002d45f + 1c2c: 0002 c.slli64 zero + 1c2e: 0100 addi s0,sp,128 + 1c30: 5c00 lw s0,56(s0) + 1c32: 02dc addi a5,sp,324 + 1c34: 0000 unimp + 1c36: 02f8 addi a4,sp,332 + 1c38: 0000 unimp + 1c3a: 0001 nop + 1c3c: fc5f 0002 1000 0x10000002fc5f + 1c42: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> + 1c46: 5f00 lw s0,56(a4) + 1c48: 0318 addi a4,sp,384 + 1c4a: 0000 unimp + 1c4c: 0320 addi s0,sp,392 + 1c4e: 0000 unimp + 1c50: 0001 nop + 1c52: 285f 0003 3800 0x38000003285f + 1c58: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> + 1c5c: 5f00 lw s0,56(a4) + 1c5e: 0340 addi s0,sp,388 + 1c60: 0000 unimp + 1c62: 0354 addi a3,sp,388 + 1c64: 0000 unimp + 1c66: 0001 nop + 1c68: 905f 0003 9800 0x98000003905f + 1c6e: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> + 1c72: 5f00 lw s0,56(a4) + 1c74: 03b4 addi a3,sp,456 + 1c76: 0000 unimp + 1c78: 03c0 addi s0,sp,452 + 1c7a: 0000 unimp + 1c7c: 0001 nop + 1c7e: c45f 0003 c800 0xc8000003c45f + 1c84: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> + 1c88: 5f00 lw s0,56(a4) + 1c8a: 043c addi a5,sp,520 + 1c8c: 0000 unimp + 1c8e: 0440 addi s0,sp,516 + 1c90: 0000 unimp + 1c92: 0001 nop + 1c94: 005f 0000 0000 0x5f + 1c9a: 0000 unimp + 1c9c: 4c00 lw s0,24(s0) + 1c9e: 0000 unimp + 1ca0: 5c00 lw s0,56(s0) + 1ca2: 0000 unimp + 1ca4: 0600 addi s0,sp,768 + 1ca6: 7b00 flw fs0,48(a4) + 1ca8: 0800 addi s0,sp,16 + 1caa: 1aff 0x1aff + 1cac: 5c9f 0000 7c00 0x7c0000005c9f + 1cb2: 0000 unimp + 1cb4: 0100 addi s0,sp,128 + 1cb6: 5b00 lw s0,48(a4) + 1cb8: 00b0 addi a2,sp,72 + 1cba: 0000 unimp + 1cbc: 00b8 addi a4,sp,72 + 1cbe: 0000 unimp + 1cc0: 0001 nop + 1cc2: 0000c05b 0xc05b + 1cc6: d400 sw s0,40(s0) + 1cc8: 0000 unimp + 1cca: 0100 addi s0,sp,128 + 1ccc: 5b00 lw s0,48(a4) + 1cce: 00fc addi a5,sp,76 + 1cd0: 0000 unimp + 1cd2: 0104 addi s1,sp,128 + 1cd4: 0000 unimp + 1cd6: 0001 nop + 1cd8: 0001685b 0x1685b + 1cdc: 6c00 flw fs0,24(s0) + 1cde: 0001 nop + 1ce0: 0100 addi s0,sp,128 + 1ce2: 5b00 lw s0,48(a4) + 1ce4: 01dc addi a5,sp,196 + 1ce6: 0000 unimp + 1ce8: 01f8 addi a4,sp,204 + 1cea: 0000 unimp + 1cec: 0001 nop + 1cee: 0002145b 0x2145b + 1cf2: 1800 addi s0,sp,48 + 1cf4: 0002 c.slli64 zero + 1cf6: 0100 addi s0,sp,128 + 1cf8: 5b00 lw s0,48(a4) + 1cfa: 0250 addi a2,sp,260 + 1cfc: 0000 unimp + 1cfe: 0254 addi a3,sp,260 + 1d00: 0000 unimp + 1d02: 0001 nop + 1d04: 0002685b 0x2685b + 1d08: 3000 fld fs0,32(s0) + 1d0a: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> + 1d0e: 5b00 lw s0,48(a4) + 1d10: 0340 addi s0,sp,388 + 1d12: 0000 unimp + 1d14: 0354 addi a3,sp,388 + 1d16: 0000 unimp + 1d18: 0001 nop + 1d1a: 0003905b 0x3905b + 1d1e: a000 fsd fs0,0(s0) + 1d20: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> + 1d24: 5b00 lw s0,48(a4) + 1d26: 03b4 addi a3,sp,456 + 1d28: 0000 unimp + 1d2a: 03bc addi a5,sp,456 + 1d2c: 0000 unimp + 1d2e: 0001 nop + 1d30: 00043c5b 0x43c5b + 1d34: 4400 lw s0,8(s0) + 1d36: 0004 0x4 + 1d38: 0100 addi s0,sp,128 + 1d3a: 5b00 lw s0,48(a4) + ... + 1d44: 0048 addi a0,sp,4 + 1d46: 0000 unimp + 1d48: 007c addi a5,sp,12 + 1d4a: 0000 unimp + 1d4c: 0001 nop + 1d4e: 7c5e flw fs8,244(sp) + 1d50: 0000 unimp + 1d52: b000 fsd fs0,32(s0) + 1d54: 0000 unimp + 1d56: 0100 addi s0,sp,128 + 1d58: 6100 flw fs0,0(a0) + 1d5a: 00b0 addi a2,sp,72 + 1d5c: 0000 unimp + 1d5e: 00b4 addi a3,sp,72 + 1d60: 0000 unimp + 1d62: 0001 nop + 1d64: b45e fsd fs7,40(sp) + 1d66: 0000 unimp + 1d68: c000 sw s0,0(s0) + 1d6a: 0000 unimp + 1d6c: 0100 addi s0,sp,128 + 1d6e: 6100 flw fs0,0(a0) + 1d70: 00c0 addi s0,sp,68 + 1d72: 0000 unimp + 1d74: 00c4 addi s1,sp,68 + 1d76: 0000 unimp + 1d78: 0001 nop + 1d7a: c45e sw s7,8(sp) + 1d7c: 0000 unimp + 1d7e: fc00 fsw fs0,56(s0) + 1d80: 0000 unimp + 1d82: 0100 addi s0,sp,128 + 1d84: 6100 flw fs0,0(a0) + 1d86: 00fc addi a5,sp,76 + 1d88: 0000 unimp + 1d8a: 0124 addi s1,sp,136 + 1d8c: 0000 unimp + 1d8e: 0001 nop + 1d90: 245e fld fs0,464(sp) + 1d92: 0001 nop + 1d94: 2c00 fld fs0,24(s0) + 1d96: 0001 nop + 1d98: 0100 addi s0,sp,128 + 1d9a: 6100 flw fs0,0(a0) + 1d9c: 012c addi a1,sp,136 + 1d9e: 0000 unimp + 1da0: 0170 addi a2,sp,140 + 1da2: 0000 unimp + 1da4: 0001 nop + 1da6: 705e flw ft0,244(sp) + 1da8: 0001 nop + 1daa: 9c00 0x9c00 + 1dac: 0001 nop + 1dae: 0100 addi s0,sp,128 + 1db0: 6100 flw fs0,0(a0) + 1db2: 01b8 addi a4,sp,200 + 1db4: 0000 unimp + 1db6: 01dc addi a5,sp,196 + 1db8: 0000 unimp + 1dba: 0001 nop + 1dbc: dc61 beqz s0,1d94 <_start-0x7fffe26c> + 1dbe: 0001 nop + 1dc0: e800 fsw fs0,16(s0) + 1dc2: 0001 nop + 1dc4: 0100 addi s0,sp,128 + 1dc6: 5e00 lw s0,56(a2) + 1dc8: 01e8 addi a0,sp,204 + 1dca: 0000 unimp + 1dcc: 0250 addi a2,sp,260 + 1dce: 0000 unimp + 1dd0: 0001 nop + 1dd2: 5061 c.li zero,-8 + 1dd4: 0002 c.slli64 zero + 1dd6: 5800 lw s0,48(s0) + 1dd8: 0002 c.slli64 zero + 1dda: 0100 addi s0,sp,128 + 1ddc: 5e00 lw s0,56(a2) + 1dde: 0258 addi a4,sp,260 + 1de0: 0000 unimp + 1de2: 0268 addi a0,sp,268 + 1de4: 0000 unimp + 1de6: 0001 nop + 1de8: 6861 lui a6,0x18 + 1dea: 0002 c.slli64 zero + 1dec: 9400 0x9400 + 1dee: 0002 c.slli64 zero + 1df0: 0100 addi s0,sp,128 + 1df2: 5e00 lw s0,56(a2) + 1df4: 0294 addi a3,sp,320 + 1df6: 0000 unimp + 1df8: 02a0 addi s0,sp,328 + 1dfa: 0000 unimp + 1dfc: 0001 nop + 1dfe: a061 j 1e86 <_start-0x7fffe17a> + 1e00: 0002 c.slli64 zero + 1e02: e000 fsw fs0,0(s0) + 1e04: 0002 c.slli64 zero + 1e06: 0100 addi s0,sp,128 + 1e08: 5e00 lw s0,56(a2) + 1e0a: 02e0 addi s0,sp,332 + 1e0c: 0000 unimp + 1e0e: 0000035b 0x35b + 1e12: 0001 nop + 1e14: 9061 srli s0,s0,0x38 + 1e16: a0000003 lb zero,-1536(zero) # fffffa00 <__global_pointer$+0x7fffbd98> + 1e1a: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> + 1e1e: 6100 flw fs0,0(a0) + 1e20: 03b4 addi a3,sp,456 + 1e22: 0000 unimp + 1e24: 03b8 addi a4,sp,456 + 1e26: 0000 unimp + 1e28: 0001 nop + 1e2a: b85e fsd fs7,48(sp) + 1e2c: cc000003 lb zero,-832(zero) # fffffcc0 <__global_pointer$+0x7fffc058> + 1e30: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> + 1e34: 6100 flw fs0,0(a0) + 1e36: 043c addi a5,sp,520 + 1e38: 0000 unimp + 1e3a: 0444 addi s1,sp,516 + 1e3c: 0000 unimp + 1e3e: 0001 nop + 1e40: 0061 c.nop 24 + 1e42: 0000 unimp + 1e44: 0000 unimp + 1e46: 0000 unimp + 1e48: 4400 lw s0,8(s0) + 1e4a: 0000 unimp + 1e4c: 7c00 flw fs0,56(s0) + 1e4e: 0000 unimp + 1e50: 0100 addi s0,sp,128 + 1e52: 5d00 lw s0,56(a0) + 1e54: 00b0 addi a2,sp,72 + 1e56: 0000 unimp + 1e58: 00ec addi a1,sp,76 + 1e5a: 0000 unimp + 1e5c: 0001 nop + 1e5e: f45d bnez s0,1e0c <_start-0x7fffe1f4> + 1e60: 0000 unimp + 1e62: fc00 fsw fs0,56(s0) + 1e64: 0000 unimp + 1e66: 0100 addi s0,sp,128 + 1e68: 5e00 lw s0,56(a2) + 1e6a: 00fc addi a5,sp,76 + 1e6c: 0000 unimp + 1e6e: 0188 addi a0,sp,192 + 1e70: 0000 unimp + 1e72: 0001 nop + 1e74: b85d j 172a <_start-0x7fffe8d6> + 1e76: 0001 nop + 1e78: f800 fsw fs0,48(s0) + 1e7a: 0001 nop + 1e7c: 0100 addi s0,sp,128 + 1e7e: 5d00 lw s0,56(a0) + 1e80: 0214 addi a3,sp,256 + 1e82: 0000 unimp + 1e84: 023c addi a5,sp,264 + 1e86: 0000 unimp + 1e88: 0001 nop + 1e8a: 445d li s0,23 + 1e8c: 0002 c.slli64 zero + 1e8e: 4c00 lw s0,24(s0) + 1e90: 0002 c.slli64 zero + 1e92: 0100 addi s0,sp,128 + 1e94: 5e00 lw s0,56(a2) + 1e96: 0250 addi a2,sp,260 + 1e98: 0000 unimp + 1e9a: 0354 addi a3,sp,388 + 1e9c: 0000 unimp + 1e9e: 0001 nop + 1ea0: 905d srli s0,s0,0x37 + 1ea2: a0000003 lb zero,-1536(zero) # fffffa00 <__global_pointer$+0x7fffbd98> + 1ea6: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> + 1eaa: 5d00 lw s0,56(a0) + 1eac: 03b4 addi a3,sp,456 + 1eae: 0000 unimp + 1eb0: 03c8 addi a0,sp,452 + 1eb2: 0000 unimp + 1eb4: 0001 nop + 1eb6: 3c5d jal 196c <_start-0x7fffe694> + 1eb8: 0004 0x4 + 1eba: 4400 lw s0,8(s0) + 1ebc: 0004 0x4 + 1ebe: 0100 addi s0,sp,128 + 1ec0: 5d00 lw s0,56(a0) + ... + 1eca: 0064 addi s1,sp,12 + 1ecc: 0000 unimp + 1ece: 00b8 addi a4,sp,72 + 1ed0: 0000 unimp + 1ed2: 0001 nop + 1ed4: c059 beqz s0,1f5a <_start-0x7fffe0a6> + 1ed6: 0000 unimp + 1ed8: bc00 fsd fs0,56(s0) + 1eda: 0001 nop + 1edc: 0100 addi s0,sp,128 + 1ede: 5900 lw s0,48(a0) + 1ee0: 01c4 addi s1,sp,196 + 1ee2: 0000 unimp + 1ee4: 01dc addi a5,sp,196 + 1ee6: 0000 unimp + 1ee8: 0001 nop + 1eea: e059 bnez s0,1f70 <_start-0x7fffe090> + 1eec: 0001 nop + 1eee: 6800 flw fs0,16(s0) + 1ef0: 0002 c.slli64 zero + 1ef2: 0100 addi s0,sp,128 + 1ef4: 5900 lw s0,48(a0) + 1ef6: 0270 addi a2,sp,268 + 1ef8: 0000 unimp + 1efa: 0294 addi a3,sp,320 + 1efc: 0000 unimp + 1efe: 0001 nop + 1f00: 0002a05b 0x2a05b + 1f04: dc00 sw s0,56(s0) + 1f06: 0002 c.slli64 zero + 1f08: 0100 addi s0,sp,128 + 1f0a: 5b00 lw s0,48(a4) + 1f0c: 0304 addi s1,sp,384 + 1f0e: 0000 unimp + 1f10: 0310 addi a2,sp,384 + 1f12: 0000 unimp + 1f14: 0001 nop + 1f16: 1059 c.nop -10 + 1f18: 18000003 lb zero,384(zero) # 180 <_start-0x7ffffe80> + 1f1c: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> + 1f20: 5b00 lw s0,48(a4) + 1f22: 0318 addi a4,sp,384 + 1f24: 0000 unimp + 1f26: 031c addi a5,sp,384 + 1f28: 0000 unimp + 1f2a: 0001 nop + 1f2c: 4459 li s0,22 + 1f2e: 50000003 lb zero,1280(zero) # 500 <_start-0x7ffffb00> + 1f32: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> + 1f36: 5900 lw s0,48(a0) + 1f38: 0350 addi a2,sp,388 + 1f3a: 0000 unimp + 1f3c: 0354 addi a3,sp,388 + 1f3e: 0000 unimp + 1f40: 0001 nop + 1f42: 0003545b 0x3545b + 1f46: cc00 sw s0,24(s0) + 1f48: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> + 1f4c: 5900 lw s0,48(a0) + 1f4e: 0404 addi s1,sp,512 + 1f50: 0000 unimp + 1f52: 042c addi a1,sp,520 + 1f54: 0000 unimp + 1f56: 0001 nop + 1f58: 3c59 jal 19ee <_start-0x7fffe612> + 1f5a: 0004 0x4 + 1f5c: 4400 lw s0,8(s0) + 1f5e: 0004 0x4 + 1f60: 0100 addi s0,sp,128 + 1f62: 5900 lw s0,48(a0) + ... + 1f6c: 0068 addi a0,sp,12 + 1f6e: 0000 unimp + 1f70: 0080 addi s0,sp,64 + 1f72: 0000 unimp + 1f74: 0001 nop + 1f76: 805c 0x805c + 1f78: 0000 unimp + 1f7a: b000 fsd fs0,32(s0) + 1f7c: 0000 unimp + 1f7e: 0100 addi s0,sp,128 + 1f80: 5e00 lw s0,56(a2) + 1f82: 00b0 addi a2,sp,72 + 1f84: 0000 unimp + 1f86: 00b8 addi a4,sp,72 + 1f88: 0000 unimp + 1f8a: 0001 nop + 1f8c: c05c sw a5,4(s0) + 1f8e: 0000 unimp + 1f90: fc00 fsw fs0,56(s0) + 1f92: 0000 unimp + 1f94: 0100 addi s0,sp,128 + 1f96: 5c00 lw s0,56(s0) + 1f98: 0104 addi s1,sp,128 + 1f9a: 0000 unimp + 1f9c: 0124 addi s1,sp,136 + 1f9e: 0000 unimp + 1fa0: 0001 nop + 1fa2: 2c5e fld fs8,464(sp) + 1fa4: 0001 nop + 1fa6: 6800 flw fs0,16(s0) + 1fa8: 0001 nop + 1faa: 0100 addi s0,sp,128 + 1fac: 5e00 lw s0,56(a2) + 1fae: 0178 addi a4,sp,140 + 1fb0: 0000 unimp + 1fb2: 0198 addi a4,sp,192 + 1fb4: 0000 unimp + 1fb6: 0002 c.slli64 zero + 1fb8: 9f30 0x9f30 + 1fba: 0198 addi a4,sp,192 + 1fbc: 0000 unimp + 1fbe: 019c addi a5,sp,192 + 1fc0: 0000 unimp + 1fc2: 0002 c.slli64 zero + 1fc4: 9f31 0x9f31 + 1fc6: 019c addi a5,sp,192 + 1fc8: 0000 unimp + 1fca: 01b8 addi a4,sp,200 + 1fcc: 0000 unimp + 1fce: 0001 nop + 1fd0: b85e fsd fs7,48(sp) + 1fd2: 0001 nop + 1fd4: c400 sw s0,8(s0) + 1fd6: 0001 nop + 1fd8: 0300 addi s0,sp,384 + 1fda: 0800 addi s0,sp,16 + 1fdc: 9fff 0x9fff + 1fde: 01c4 addi s1,sp,196 + 1fe0: 0000 unimp + 1fe2: 01dc addi a5,sp,196 + 1fe4: 0000 unimp + 1fe6: 0001 nop + 1fe8: 0001e05b 0x1e05b + 1fec: f800 fsw fs0,48(s0) + 1fee: 0001 nop + 1ff0: 0100 addi s0,sp,128 + 1ff2: 5c00 lw s0,56(s0) + 1ff4: 01f8 addi a4,sp,204 + 1ff6: 0000 unimp + 1ff8: 0214 addi a3,sp,256 + 1ffa: 0000 unimp + 1ffc: 0001 nop + 1ffe: 145e slli s0,s0,0x37 + 2000: 0002 c.slli64 zero + 2002: 6800 flw fs0,16(s0) + 2004: 0002 c.slli64 zero + 2006: 0100 addi s0,sp,128 + 2008: 5c00 lw s0,56(s0) + 200a: 0270 addi a2,sp,268 + 200c: 0000 unimp + 200e: 0294 addi a3,sp,320 + 2010: 0000 unimp + 2012: 0001 nop + 2014: a05e fsd fs7,0(sp) + 2016: 0002 c.slli64 zero + 2018: dc00 sw s0,56(s0) + 201a: 0002 c.slli64 zero + 201c: 0100 addi s0,sp,128 + 201e: 5e00 lw s0,56(a2) + 2020: 02ec addi a1,sp,332 + 2022: 0000 unimp + 2024: 02f4 addi a3,sp,332 + 2026: 0000 unimp + 2028: 0002 c.slli64 zero + 202a: 9f30 0x9f30 + 202c: 02fc addi a5,sp,332 + 202e: 0000 unimp + 2030: 0310 addi a2,sp,384 + 2032: 0000 unimp + 2034: 0002 c.slli64 zero + 2036: 9f30 0x9f30 + 2038: 0318 addi a4,sp,384 + 203a: 0000 unimp + 203c: 0320 addi s0,sp,392 + 203e: 0000 unimp + 2040: 0002 c.slli64 zero + 2042: 9f30 0x9f30 + 2044: 0328 addi a0,sp,392 + 2046: 0000 unimp + 2048: 0340 addi s0,sp,388 + 204a: 0000 unimp + 204c: ff080003 lb zero,-16(a6) # 17ff0 <_start-0x7ffe8010> + 2050: 409f 0003 5400 0x54000003409f + 2056: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> + 205a: 5c00 lw s0,56(s0) + 205c: 0354 addi a3,sp,388 + 205e: 0000 unimp + 2060: 0388 addi a0,sp,448 + 2062: 0000 unimp + 2064: 0001 nop + 2066: 8862 mv a6,s8 + 2068: 90000003 lb zero,-1792(zero) # fffff900 <__global_pointer$+0x7fffbc98> + 206c: 02000003 lb zero,32(zero) # 20 <_start-0x7fffffe0> + 2070: 3000 fld fs0,32(s0) + 2072: 909f 0003 a000 0xa0000003909f + 2078: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> + 207c: 5c00 lw s0,56(s0) + 207e: 03a0 addi s0,sp,456 + 2080: 0000 unimp + 2082: 03ac addi a1,sp,456 + 2084: 0000 unimp + 2086: 0001 nop + 2088: ac62 fsd fs8,24(sp) + 208a: b4000003 lb zero,-1216(zero) # fffffb40 <__global_pointer$+0x7fffbed8> + 208e: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> + 2092: 5e00 lw s0,56(a2) + 2094: 03b4 addi a3,sp,456 + 2096: 0000 unimp + 2098: 03bc addi a5,sp,456 + 209a: 0000 unimp + 209c: 0001 nop + 209e: c45c sw a5,12(s0) + 20a0: c8000003 lb zero,-896(zero) # fffffc80 <__global_pointer$+0x7fffc018> + 20a4: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> + 20a8: 5b00 lw s0,48(a4) + 20aa: 03d8 addi a4,sp,452 + 20ac: 0000 unimp + 20ae: 03f8 addi a4,sp,460 + 20b0: 0000 unimp + 20b2: 0001 nop + 20b4: f85e fsw fs7,48(sp) + 20b6: 04000003 lb zero,64(zero) # 40 <_start-0x7fffffc0> + 20ba: 0004 0x4 + 20bc: 0300 addi s0,sp,384 + 20be: 0800 addi s0,sp,16 + 20c0: 9fff 0x9fff + 20c2: 043c addi a5,sp,520 + 20c4: 0000 unimp + 20c6: 0444 addi s1,sp,516 + 20c8: 0000 unimp + 20ca: 0002 c.slli64 zero + 20cc: 9f30 0x9f30 + 20ce: 0444 addi s1,sp,516 + 20d0: 0000 unimp + 20d2: 044c addi a1,sp,516 + 20d4: 0000 unimp + 20d6: 0001 nop + 20d8: 005e c.slli zero,0x17 + 20da: 0000 unimp + 20dc: 0000 unimp + 20de: 0000 unimp + 20e0: 7c00 flw fs0,56(s0) + 20e2: 0000 unimp + 20e4: 8800 0x8800 + 20e6: 0000 unimp + 20e8: 0100 addi s0,sp,128 + 20ea: 5f00 lw s0,56(a4) + 20ec: 0088 addi a0,sp,64 + 20ee: 0000 unimp + 20f0: 008c addi a1,sp,64 + 20f2: 0000 unimp + 20f4: 0009 c.nop 2 + 20f6: 007f 0x7f + 20f8: ff11 bnez a4,2014 <_start-0x7fffdfec> + 20fa: ffff 0xffff + 20fc: 1a5f 8c9f 0000 0x8c9f1a5f + 2102: 9c00 0x9c00 + 2104: 0000 unimp + 2106: 1000 addi s0,sp,32 + 2108: 7f00 flw fs0,56(a4) + 210a: 3100 fld fs0,32(a0) + 210c: 0c25 addi s8,s8,9 + 210e: ffff 0xffff + 2110: 7dff 0x7dff + 2112: 7f1a flw ft10,164(sp) + 2114: 3100 fld fs0,32(a0) + 2116: 211a fld ft2,384(sp) + 2118: 9c9f 0000 a400 0xa40000009c9f + 211e: 0000 unimp + 2120: 0e00 addi s0,sp,784 + 2122: 7f00 flw fs0,56(a4) + 2124: 3100 fld fs0,32(a0) + 2126: 0c25 addi s8,s8,9 + 2128: ffff 0xffff + 212a: 7dff 0x7dff + 212c: 7c1a flw fs8,164(sp) + 212e: 2100 fld fs0,0(a0) + 2130: a49f 0000 a800 0xa8000000a49f + 2136: 0000 unimp + 2138: 0c00 addi s0,sp,528 + 213a: 7f00 flw fs0,56(a4) + 213c: 0c00 addi s0,sp,528 + 213e: ffff 0xffff + 2140: 7dff 0x7dff + 2142: 7c1a flw fs8,164(sp) + 2144: 2100 fld fs0,0(a0) + 2146: 189f 0001 1c00 0x1c000001189f + 214c: 0001 nop + 214e: 0100 addi s0,sp,128 + 2150: 5f00 lw s0,56(a4) + 2152: 0164 addi s1,sp,140 + 2154: 0000 unimp + 2156: 0168 addi a0,sp,140 + 2158: 0000 unimp + 215a: 0001 nop + 215c: 845f 0001 b800 0xb8000001845f + 2162: 0001 nop + 2164: 0100 addi s0,sp,128 + 2166: 5f00 lw s0,56(a4) + 2168: 01c4 addi s1,sp,196 + 216a: 0000 unimp + 216c: 01d0 addi a2,sp,196 + 216e: 0000 unimp + 2170: 0008 0x8 + 2172: 007f 0x7f + 2174: 007d c.nop 31 + 2176: 3122 fld ft2,40(sp) + 2178: 9f25 0x9f25 + 217a: 01d0 addi a2,sp,196 + 217c: 0000 unimp + 217e: 01d4 addi a3,sp,196 + 2180: 0000 unimp + 2182: 0005 c.nop 1 + 2184: 007f 0x7f + 2186: 2531 jal 2792 <_start-0x7fffd86e> + 2188: f89f 0001 0c00 0xc000001f89f + 218e: 0002 c.slli64 zero + 2190: 0100 addi s0,sp,128 + 2192: 5f00 lw s0,56(a4) + 2194: 020c addi a1,sp,256 + 2196: 0000 unimp + 2198: 0214 addi a3,sp,256 + 219a: 0000 unimp + 219c: 0001 nop + 219e: 4858 lw a4,20(s0) + 21a0: 0002 c.slli64 zero + 21a2: 5000 lw s0,32(s0) + 21a4: 0002 c.slli64 zero + 21a6: 0100 addi s0,sp,128 + 21a8: 5f00 lw s0,56(a4) + 21aa: 0284 addi s1,sp,320 + 21ac: 0000 unimp + 21ae: 028c addi a1,sp,320 + 21b0: 0000 unimp + 21b2: 0001 nop + 21b4: f05f 0002 f400 0xf4000002f05f + 21ba: 0002 c.slli64 zero + 21bc: 0100 addi s0,sp,128 + 21be: 5d00 lw s0,56(a0) + 21c0: 0304 addi s1,sp,384 + 21c2: 0000 unimp + 21c4: 0310 addi a2,sp,384 + 21c6: 0000 unimp + 21c8: 0001 nop + 21ca: 105c addi a5,sp,36 + 21cc: 18000003 lb zero,384(zero) # 180 <_start-0x7ffffe80> + 21d0: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> + 21d4: 5f00 lw s0,56(a4) + 21d6: 0318 addi a4,sp,384 + 21d8: 0000 unimp + 21da: 031c addi a5,sp,384 + 21dc: 0000 unimp + 21de: 0001 nop + 21e0: 445c lw a5,12(s0) + 21e2: 80000003 lb zero,-2048(zero) # fffff800 <__global_pointer$+0x7fffbb98> + 21e6: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> + 21ea: 5800 lw s0,48(s0) + 21ec: 0388 addi a0,sp,448 + 21ee: 0000 unimp + 21f0: 0390 addi a2,sp,448 + 21f2: 0000 unimp + 21f4: 0001 nop + 21f6: 905f 0003 b000 0xb0000003905f + 21fc: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> + 2200: 5800 lw s0,48(s0) + 2202: 03b0 addi a2,sp,456 + 2204: 0000 unimp + 2206: 03b4 addi a3,sp,456 + 2208: 0000 unimp + 220a: 0001 nop + 220c: c45f 0003 c800 0xc8000003c45f + 2212: 08000003 lb zero,128(zero) # 80 <_start-0x7fffff80> + 2216: 7f00 flw fs0,56(a4) + 2218: 7d00 flw fs0,56(a0) + 221a: 2200 fld fs0,0(a2) + 221c: 2531 jal 2828 <_start-0x7fffd7d8> + 221e: cc9f 0003 d400 0xd4000003cc9f + 2224: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> + 2228: 5f00 lw s0,56(a4) + 222a: 03d4 addi a3,sp,452 + 222c: 0000 unimp + 222e: 03ec addi a1,sp,460 + 2230: 0000 unimp + 2232: 0009 c.nop 2 + 2234: 007f 0x7f + 2236: ff11 bnez a4,2152 <_start-0x7fffdeae> + 2238: ffff 0xffff + 223a: 1a5f ec9f 0003 0x3ec9f1a5f + 2240: 0000 unimp + 2242: 0004 0x4 + 2244: 0100 addi s0,sp,128 + 2246: 5f00 lw s0,56(a4) + 2248: 0404 addi s1,sp,512 + 224a: 0000 unimp + 224c: 0418 addi a4,sp,512 + 224e: 0000 unimp + 2250: 0001 nop + 2252: 3c5f 0004 4400 0x440000043c5f + 2258: 0004 0x4 + 225a: 0100 addi s0,sp,128 + 225c: 5c00 lw s0,56(s0) + 225e: 0444 addi s1,sp,516 + 2260: 0000 unimp + 2262: 0448 addi a0,sp,516 + 2264: 0000 unimp + 2266: 0009 c.nop 2 + 2268: 007f 0x7f + 226a: ff11 bnez a4,2186 <_start-0x7fffde7a> + 226c: ffff 0xffff + 226e: 1a5f 009f 0000 0x9f1a5f + 2274: 0000 unimp + 2276: 0000 unimp + 2278: 2800 fld fs0,16(s0) + 227a: 0004 0x4 + 227c: 3400 fld fs0,40(s0) + 227e: 0004 0x4 + 2280: 0800 addi s0,sp,16 + 2282: 7f00 flw fs0,56(a4) + 2284: 7a00 flw fs0,48(a2) + 2286: 2100 fld fs0,0(a0) + 2288: 25f9 jal 2956 <_start-0x7fffd6aa> + 228a: 349f 0004 3c00 0x3c000004349f + 2290: 0004 0x4 + 2292: 0100 addi s0,sp,128 + 2294: 5a00 lw s0,48(a2) + ... + 229e: 0064 addi s1,sp,12 + 22a0: 0000 unimp + 22a2: 0074 addi a3,sp,12 + 22a4: 0000 unimp + 22a6: 0006 c.slli zero,0x1 + 22a8: 007c addi a5,sp,12 + 22aa: 007e c.slli zero,0x1f + 22ac: 9f1c 0x9f1c + 22ae: 0074 addi a3,sp,12 + 22b0: 0000 unimp + 22b2: 007c addi a5,sp,12 + 22b4: 0000 unimp + 22b6: 0001 nop + 22b8: b060 fsd fs0,224(s0) + 22ba: 0000 unimp + 22bc: b800 fsd fs0,48(s0) + 22be: 0000 unimp + 22c0: 0100 addi s0,sp,128 + 22c2: 6000 flw fs0,0(s0) + 22c4: 00c0 addi s0,sp,68 + 22c6: 0000 unimp + 22c8: 00c4 addi s1,sp,68 + 22ca: 0000 unimp + 22cc: 0006 c.slli zero,0x1 + 22ce: 007c addi a5,sp,12 + 22d0: 007e c.slli zero,0x1f + 22d2: 9f1c 0x9f1c + 22d4: 00c4 addi s1,sp,68 + 22d6: 0000 unimp + 22d8: 00d0 addi a2,sp,68 + 22da: 0000 unimp + 22dc: 0006 c.slli zero,0x1 + 22de: 007c addi a5,sp,12 + 22e0: 0081 addi ra,ra,0 + 22e2: 9f1c 0x9f1c + 22e4: 00d0 addi a2,sp,68 + 22e6: 0000 unimp + 22e8: 00e8 addi a0,sp,76 + 22ea: 0000 unimp + 22ec: 0001 nop + 22ee: fc60 fsw fs0,124(s0) + 22f0: 0000 unimp + 22f2: 0400 addi s0,sp,512 + 22f4: 0001 nop + 22f6: 0600 addi s0,sp,768 + 22f8: 7c00 flw fs0,56(s0) + 22fa: 7e00 flw fs0,56(a2) + 22fc: 1c00 addi s0,sp,560 + 22fe: 049f 0001 2400 0x24000001049f + 2304: 0001 nop + 2306: 0100 addi s0,sp,128 + 2308: 5b00 lw s0,48(a4) + 230a: 012c addi a1,sp,136 + 230c: 0000 unimp + 230e: 0168 addi a0,sp,140 + 2310: 0000 unimp + 2312: 0001 nop + 2314: 0001685b 0x1685b + 2318: 7000 flw fs0,32(s0) + 231a: 0001 nop + 231c: 0600 addi s0,sp,768 + 231e: 7c00 flw fs0,56(s0) + 2320: 7e00 flw fs0,56(a2) + 2322: 1c00 addi s0,sp,560 + 2324: 709f 0001 9c00 0x9c000001709f + 232a: 0001 nop + 232c: 0600 addi s0,sp,768 + 232e: 7c00 flw fs0,56(s0) + 2330: 8100 0x8100 + 2332: 1c00 addi s0,sp,560 + 2334: b89f 0001 bc00 0xbc000001b89f + 233a: 0001 nop + 233c: 0600 addi s0,sp,768 + 233e: 7c00 flw fs0,56(s0) + 2340: 8100 0x8100 + 2342: 1c00 addi s0,sp,560 + 2344: c49f 0001 dc00 0xdc000001c49f + 234a: 0001 nop + 234c: 0600 addi s0,sp,768 + 234e: 7c00 flw fs0,56(s0) + 2350: 8100 0x8100 + 2352: 1c00 addi s0,sp,560 + 2354: b49f 0003 b800 0xb8000003b49f + 235a: 06000003 lb zero,96(zero) # 60 <_start-0x7fffffa0> + 235e: 7c00 flw fs0,56(s0) + 2360: 7e00 flw fs0,56(a2) + 2362: 1c00 addi s0,sp,560 + 2364: b89f 0003 bc00 0xbc000003b89f + 236a: 06000003 lb zero,96(zero) # 60 <_start-0x7fffffa0> + 236e: 7c00 flw fs0,56(s0) + 2370: 8100 0x8100 + 2372: 1c00 addi s0,sp,560 + 2374: c49f 0003 c800 0xc8000003c49f + 237a: 06000003 lb zero,96(zero) # 60 <_start-0x7fffffa0> + 237e: 7c00 flw fs0,56(s0) + 2380: 8100 0x8100 + 2382: 1c00 addi s0,sp,560 + 2384: 009f 0000 0000 0x9f + 238a: 0000 unimp + 238c: dc00 sw s0,56(s0) + 238e: 0001 nop + 2390: e800 fsw fs0,16(s0) + 2392: 0001 nop + 2394: 0600 addi s0,sp,768 + 2396: 7c00 flw fs0,56(s0) + 2398: 7e00 flw fs0,56(a2) + 239a: 1c00 addi s0,sp,560 + 239c: e89f 0001 f000 0xf0000001e89f + 23a2: 0001 nop + 23a4: 0600 addi s0,sp,768 + 23a6: 7c00 flw fs0,56(s0) + 23a8: 8100 0x8100 + 23aa: 1c00 addi s0,sp,560 + 23ac: f09f 0001 f800 0xf8000001f09f + 23b2: 0001 nop + 23b4: 0100 addi s0,sp,128 + 23b6: 6000 flw fs0,0(s0) + 23b8: 0214 addi a3,sp,256 + 23ba: 0000 unimp + 23bc: 0238 addi a4,sp,264 + 23be: 0000 unimp + 23c0: 0001 nop + 23c2: 5060 lw s0,100(s0) + 23c4: 0002 c.slli64 zero + 23c6: 5800 lw s0,48(s0) + 23c8: 0002 c.slli64 zero + 23ca: 0600 addi s0,sp,768 + 23cc: 7c00 flw fs0,56(s0) + 23ce: 7e00 flw fs0,56(a2) + 23d0: 1c00 addi s0,sp,560 + 23d2: 589f 0002 6800 0x68000002589f + 23d8: 0002 c.slli64 zero + 23da: 0600 addi s0,sp,768 + 23dc: 7c00 flw fs0,56(s0) + 23de: 8100 0x8100 + 23e0: 1c00 addi s0,sp,560 + 23e2: 689f 0002 7000 0x70000002689f + 23e8: 0002 c.slli64 zero + 23ea: 0600 addi s0,sp,768 + 23ec: 7c00 flw fs0,56(s0) + 23ee: 7e00 flw fs0,56(a2) + 23f0: 1c00 addi s0,sp,560 + 23f2: 709f 0002 9400 0x94000002709f + 23f8: 0002 c.slli64 zero + 23fa: 0100 addi s0,sp,128 + 23fc: 5a00 lw s0,48(a2) + 23fe: 02a0 addi s0,sp,328 + 2400: 0000 unimp + 2402: 02dc addi a5,sp,324 + 2404: 0000 unimp + 2406: 0001 nop + 2408: dc5a sw s6,56(sp) + 240a: 0002 c.slli64 zero + 240c: e000 fsw fs0,0(s0) + 240e: 0002 c.slli64 zero + 2410: 0600 addi s0,sp,768 + 2412: 7c00 flw fs0,56(s0) + 2414: 7e00 flw fs0,56(a2) + 2416: 1c00 addi s0,sp,560 + 2418: e09f 0002 f400 0xf4000002e09f + 241e: 0002 c.slli64 zero + 2420: 0600 addi s0,sp,768 + 2422: 7c00 flw fs0,56(s0) + 2424: 8100 0x8100 + 2426: 1c00 addi s0,sp,560 + 2428: fc9f 0002 0400 0x4000002fc9f + 242e: 06000003 lb zero,96(zero) # 60 <_start-0x7fffffa0> + 2432: 7c00 flw fs0,56(s0) + 2434: 8100 0x8100 + 2436: 1c00 addi s0,sp,560 + 2438: 049f 0003 1000 0x10000003049f + 243e: 06000003 lb zero,96(zero) # 60 <_start-0x7fffffa0> + 2442: 8200 0x8200 + 2444: 8100 0x8100 + 2446: 1c00 addi s0,sp,560 + 2448: 189f 0003 2800 0x28000003189f + 244e: 06000003 lb zero,96(zero) # 60 <_start-0x7fffffa0> + 2452: 8200 0x8200 + 2454: 8100 0x8100 + 2456: 1c00 addi s0,sp,560 + 2458: 289f 0003 3000 0x30000003289f + 245e: 06000003 lb zero,96(zero) # 60 <_start-0x7fffffa0> + 2462: 7c00 flw fs0,56(s0) + 2464: 8100 0x8100 + 2466: 1c00 addi s0,sp,560 + 2468: 409f 0003 5400 0x54000003409f + 246e: 06000003 lb zero,96(zero) # 60 <_start-0x7fffffa0> + 2472: 7c00 flw fs0,56(s0) + 2474: 8100 0x8100 + 2476: 1c00 addi s0,sp,560 + 2478: 909f 0003 a000 0xa0000003909f + 247e: 06000003 lb zero,96(zero) # 60 <_start-0x7fffffa0> + 2482: 7c00 flw fs0,56(s0) + 2484: 8100 0x8100 + 2486: 1c00 addi s0,sp,560 + 2488: 3c9f 0004 4400 0x440000043c9f + 248e: 0004 0x4 + 2490: 0600 addi s0,sp,768 + 2492: 8200 0x8200 + 2494: 8100 0x8100 + 2496: 1c00 addi s0,sp,560 + 2498: 009f 0000 0000 0x9f + 249e: 0000 unimp + 24a0: 5c00 lw s0,56(s0) + 24a2: 60000003 lb zero,1536(zero) # 600 <_start-0x7ffffa00> + 24a6: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> + 24aa: 5a00 lw s0,48(a2) + 24ac: 0360 addi s0,sp,396 + 24ae: 0000 unimp + 24b0: 036c addi a1,sp,396 + 24b2: 0000 unimp + 24b4: 0001 nop + 24b6: 6c5e flw fs8,212(sp) + 24b8: 70000003 lb zero,1792(zero) # 700 <_start-0x7ffff900> + 24bc: 03000003 lb zero,48(zero) # 30 <_start-0x7fffffd0> + 24c0: 7a00 flw fs0,48(a2) + 24c2: 03709f7b 0x3709f7b + 24c6: 0000 unimp + 24c8: 037c addi a5,sp,396 + 24ca: 0000 unimp + 24cc: 0001 nop + 24ce: 7c5e flw fs8,244(sp) + 24d0: 90000003 lb zero,-1792(zero) # fffff900 <__global_pointer$+0x7fffbc98> + 24d4: 08000003 lb zero,128(zero) # 80 <_start-0x7fffff80> + 24d8: 7a00 flw fs0,48(a2) + 24da: 8200 0x8200 + 24dc: 1c00 addi s0,sp,560 + 24de: 1c34 addi a3,sp,568 + 24e0: a09f 0003 ac00 0xac000003a09f + 24e6: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> + 24ea: 5e00 lw s0,56(a2) + 24ec: 03ac addi a1,sp,456 + 24ee: 0000 unimp + 24f0: 03b4 addi a3,sp,456 + 24f2: 0000 unimp + 24f4: 7b7a0003 lb zero,1975(s4) + 24f8: 009f 0000 0000 0x9f + 24fe: 0000 unimp + 2500: 0000 unimp + 2502: 0000 unimp + 2504: 1000 addi s0,sp,32 + 2506: 0000 unimp + 2508: 0100 addi s0,sp,128 + 250a: 5a00 lw s0,48(a2) + 250c: 0010 0x10 + 250e: 0000 unimp + 2510: 0044 addi s1,sp,4 + 2512: 0000 unimp + 2514: 0006 c.slli zero,0x1 + 2516: 0af503f3 0xaf503f3 + 251a: 9f25 0x9f25 + ... + 2528: 001c 0x1c + 252a: 0000 unimp + 252c: 0001 nop + 252e: 00001c5b 0x1c5b + 2532: 4400 lw s0,8(s0) + 2534: 0000 unimp + 2536: 0600 addi s0,sp,768 + 2538: f300 fsw fs0,32(a4) + 253a: 250bf503 0x250bf503 + 253e: 009f 0000 0000 0x9f + 2544: 0000 unimp + 2546: 0c00 addi s0,sp,528 + 2548: 0000 unimp + 254a: 3400 fld fs0,40(s0) + 254c: 0000 unimp + 254e: 0100 addi s0,sp,128 + 2550: 5e00 lw s0,56(a2) + ... + 255e: 0024 addi s1,sp,8 + 2560: 0000 unimp + 2562: 0001 nop + 2564: 245a fld fs0,400(sp) + 2566: 0000 unimp + 2568: 3800 fld fs0,48(s0) + 256a: 0000 unimp + 256c: 0400 addi s0,sp,512 + 256e: f300 fsw fs0,32(a4) + 2570: 5a01 li s4,-32 + 2572: 389f 0000 4c00 0x4c000000389f + 2578: 0000 unimp + 257a: 0100 addi s0,sp,128 + 257c: 5a00 lw s0,48(a2) + ... + 258a: 0024 addi s1,sp,8 + 258c: 0000 unimp + 258e: 0001 nop + 2590: 245a fld fs0,400(sp) + 2592: 0000 unimp + 2594: 3800 fld fs0,48(s0) + 2596: 0000 unimp + 2598: 0400 addi s0,sp,512 + 259a: f300 fsw fs0,32(a4) + 259c: 5a01 li s4,-32 + 259e: 389f 0000 4c00 0x4c000000389f + 25a4: 0000 unimp + 25a6: 0100 addi s0,sp,128 + 25a8: 5a00 lw s0,48(a2) + ... + 25b2: 0014 0x14 + 25b4: 0000 unimp + 25b6: 0028 addi a0,sp,8 + 25b8: 0000 unimp + 25ba: 0001 nop + 25bc: 005f 0000 0000 0x5f + 25c2: 0000 unimp + ... + +Disassembly of section .debug_ranges: + +00000000 <.debug_ranges>: + ... + 8: 0008 0x8 + a: 0000 unimp + c: 0010 0x10 + e: 0000 unimp + 10: 001c 0x1c + 12: 0000 unimp + 14: 0020 addi s0,sp,8 + 16: 0000 unimp + 18: 0034 addi a3,sp,8 + 1a: 0000 unimp + 1c: 0038 addi a4,sp,8 + 1e: 0000 unimp + 20: 0064 addi s1,sp,12 + 22: 0000 unimp + 24: 0068 addi a0,sp,12 + 26: 0000 unimp + 28: 01d8 addi a4,sp,196 + 2a: 0000 unimp + 2c: 01dc addi a5,sp,196 + 2e: 0000 unimp + 30: 023c addi a5,sp,264 + 32: 0000 unimp + 34: 0240 addi s0,sp,260 + 36: 0000 unimp + 38: 039c addi a5,sp,448 + 3a: 0000 unimp + 3c: 03a4 addi s1,sp,456 + ... + 46: 0000 unimp + 48: 0024 addi s1,sp,8 + 4a: 0000 unimp + 4c: 002c addi a1,sp,8 + 4e: 0000 unimp + 50: 0038 addi a4,sp,8 + 52: 0000 unimp + 54: 003c addi a5,sp,8 + 56: 0000 unimp + 58: 0040 addi s0,sp,4 + 5a: 0000 unimp + 5c: 0040 addi s0,sp,4 + ... + 66: 0000 unimp + 68: 004c addi a1,sp,4 + 6a: 0000 unimp + 6c: 0064 addi s1,sp,12 + 6e: 0000 unimp + 70: 0068 addi a0,sp,12 + 72: 0000 unimp + 74: 00a0 addi s0,sp,72 + 76: 0000 unimp + 78: 00a8 addi a0,sp,72 + 7a: 0000 unimp + 7c: 010c addi a1,sp,128 + 7e: 0000 unimp + 80: 0114 addi a3,sp,128 + 82: 0000 unimp + 84: 0184 addi s1,sp,192 + 86: 0000 unimp + 88: 01a0 addi s0,sp,200 + 8a: 0000 unimp + 8c: 01a4 addi s1,sp,200 + 8e: 0000 unimp + 90: 01b8 addi a4,sp,200 + 92: 0000 unimp + 94: 01d0 addi a2,sp,196 + 96: 0000 unimp + 98: 03ac addi a1,sp,456 + 9a: 0000 unimp + 9c: 03b4 addi a3,sp,456 + ... + a6: 0000 unimp + a8: 00a0 addi s0,sp,72 + aa: 0000 unimp + ac: 00a8 addi a0,sp,72 + ae: 0000 unimp + b0: 0184 addi s1,sp,192 + b2: 0000 unimp + b4: 0184 addi s1,sp,192 + b6: 0000 unimp + b8: 01a4 addi s1,sp,200 + ba: 0000 unimp + bc: 01b8 addi a4,sp,200 + be: 0000 unimp + c0: 01d0 addi a2,sp,196 + c2: 0000 unimp + c4: 01d8 addi a4,sp,196 + c6: 0000 unimp + c8: 01dc addi a5,sp,196 + ca: 0000 unimp + cc: 023c addi a5,sp,264 + ce: 0000 unimp + d0: 0240 addi s0,sp,260 + d2: 0000 unimp + d4: 0288 addi a0,sp,320 + d6: 0000 unimp + d8: 028c addi a1,sp,320 + da: 0000 unimp + dc: 039c addi a5,sp,448 + ... + e6: 0000 unimp + e8: 01f4 addi a3,sp,204 + ea: 0000 unimp + ec: 0208 addi a0,sp,256 + ee: 0000 unimp + f0: 033c addi a5,sp,392 + f2: 0000 unimp + f4: 0378 addi a4,sp,396 + f6: 0000 unimp + f8: 0388 addi a0,sp,448 + fa: 0000 unimp + fc: 039c addi a5,sp,448 + ... + 106: 0000 unimp + 108: 0184 addi s1,sp,192 + 10a: 0000 unimp + 10c: 01a0 addi s0,sp,200 + 10e: 0000 unimp + 110: 03b4 addi a3,sp,456 + 112: 0000 unimp + 114: 03ec addi a1,sp,460 + 116: 0000 unimp + 118: 0424 addi s1,sp,520 + 11a: 0000 unimp + 11c: 042c addi a1,sp,520 + ... + 126: 0000 unimp + 128: 03ec addi a1,sp,460 + 12a: 0000 unimp + 12c: 03ec addi a1,sp,460 + 12e: 0000 unimp + 130: 03f4 addi a3,sp,460 + 132: 0000 unimp + 134: 0410 addi a2,sp,512 + ... + 146: 0000 unimp + 148: 0018 0x18 + 14a: 0000 unimp + 14c: 001c 0x1c + 14e: 0000 unimp + 150: 0030 addi a2,sp,8 + 152: 0000 unimp + 154: 0038 addi a4,sp,8 + 156: 0000 unimp + 158: 0274 addi a3,sp,268 + 15a: 0000 unimp + 15c: 0278 addi a4,sp,268 + ... + 166: 0000 unimp + 168: 0054 addi a3,sp,4 + 16a: 0000 unimp + 16c: 0058 addi a4,sp,4 + 16e: 0000 unimp + 170: 00c4 addi s1,sp,68 + 172: 0000 unimp + 174: 00e0 addi s0,sp,76 + ... + 17e: 0000 unimp + 180: 0058 addi a4,sp,4 + 182: 0000 unimp + 184: 006c addi a1,sp,12 + 186: 0000 unimp + 188: 02a4 addi s1,sp,328 + 18a: 0000 unimp + 18c: 02a8 addi a0,sp,328 + ... + 196: 0000 unimp + 198: 0088 addi a0,sp,64 + 19a: 0000 unimp + 19c: 008c addi a1,sp,64 + 19e: 0000 unimp + 1a0: 0104 addi s1,sp,128 + 1a2: 0000 unimp + 1a4: 0120 addi s0,sp,136 + ... + 1ae: 0000 unimp + 1b0: 0140 addi s0,sp,132 + 1b2: 0000 unimp + 1b4: 01e0 addi s0,sp,204 + 1b6: 0000 unimp + 1b8: 0268 addi a0,sp,268 + 1ba: 0000 unimp + 1bc: 0274 addi a3,sp,268 + ... + 1c6: 0000 unimp + 1c8: 0150 addi a2,sp,132 + 1ca: 0000 unimp + 1cc: 01cc addi a1,sp,196 + 1ce: 0000 unimp + 1d0: 01cc addi a1,sp,196 + 1d2: 0000 unimp + 1d4: 01d0 addi a2,sp,196 + 1d6: 0000 unimp + 1d8: 01d4 addi a3,sp,196 + 1da: 0000 unimp + 1dc: 01d8 addi a4,sp,196 + ... + 1e6: 0000 unimp + 1e8: 02bc addi a5,sp,328 + 1ea: 0000 unimp + 1ec: 0310 addi a2,sp,384 + 1ee: 0000 unimp + 1f0: 0320 addi s0,sp,392 + 1f2: 0000 unimp + 1f4: 032c addi a1,sp,392 + ... + 202: 0000 unimp + 204: 0014 0x14 + 206: 0000 unimp + 208: 0018 0x18 + 20a: 0000 unimp + 20c: 0020 addi s0,sp,8 + 20e: 0000 unimp + 210: 0024 addi s1,sp,8 + 212: 0000 unimp + 214: 0028 addi a0,sp,8 + ... + 21e: 0000 unimp + 220: 0020 addi s0,sp,8 + 222: 0000 unimp + 224: 0024 addi s1,sp,8 + 226: 0000 unimp + 228: 0028 addi a0,sp,8 + 22a: 0000 unimp + 22c: 002c addi a1,sp,8 + ... + 236: 0000 unimp + 238: 0044 addi s1,sp,4 + 23a: 0000 unimp + 23c: 0080 addi s0,sp,64 + 23e: 0000 unimp + 240: 0084 addi s1,sp,64 + 242: 0000 unimp + 244: 0090 addi a2,sp,64 + 246: 0000 unimp + 248: 0094 addi a3,sp,64 + 24a: 0000 unimp + 24c: 00a4 addi s1,sp,72 + 24e: 0000 unimp + 250: 00a8 addi a0,sp,72 + 252: 0000 unimp + 254: 00b4 addi a3,sp,72 + ... + 266: 0000 unimp + 268: 0018 0x18 + 26a: 0000 unimp + 26c: 001c 0x1c + 26e: 0000 unimp + 270: 0030 addi a2,sp,8 + 272: 0000 unimp + 274: 0038 addi a4,sp,8 + 276: 0000 unimp + 278: 0214 addi a3,sp,256 + 27a: 0000 unimp + 27c: 0218 addi a4,sp,256 + ... + 286: 0000 unimp + 288: 0054 addi a3,sp,4 + 28a: 0000 unimp + 28c: 0058 addi a4,sp,4 + 28e: 0000 unimp + 290: 00c8 addi a0,sp,68 + 292: 0000 unimp + 294: 00e4 addi s1,sp,76 + ... + 29e: 0000 unimp + 2a0: 0058 addi a4,sp,4 + 2a2: 0000 unimp + 2a4: 006c addi a1,sp,12 + 2a6: 0000 unimp + 2a8: 0244 addi s1,sp,260 + 2aa: 0000 unimp + 2ac: 0248 addi a0,sp,260 + ... + 2b6: 0000 unimp + 2b8: 0088 addi a0,sp,64 + 2ba: 0000 unimp + 2bc: 008c addi a1,sp,64 + 2be: 0000 unimp + 2c0: 0108 addi a0,sp,128 + 2c2: 0000 unimp + 2c4: 0124 addi s1,sp,136 + ... + 2ce: 0000 unimp + 2d0: 0144 addi s1,sp,132 + 2d2: 0000 unimp + 2d4: 0190 addi a2,sp,192 + 2d6: 0000 unimp + 2d8: 0194 addi a3,sp,192 + 2da: 0000 unimp + 2dc: 0198 addi a4,sp,192 + 2de: 0000 unimp + 2e0: 01a0 addi s0,sp,200 + 2e2: 0000 unimp + 2e4: 01a8 addi a0,sp,200 + ... + 2ee: 0000 unimp + 2f0: 0238 addi a4,sp,264 + 2f2: 0000 unimp + 2f4: 0244 addi s1,sp,260 + 2f6: 0000 unimp + 2f8: 0254 addi a3,sp,260 + 2fa: 0000 unimp + 2fc: 02a8 addi a0,sp,328 + ... + 30a: 0000 unimp + 30c: 0004 0x4 + 30e: 0000 unimp + 310: 0008 0x8 + 312: 0000 unimp + 314: 0018 0x18 + 316: 0000 unimp + 318: 0028 addi a0,sp,8 + 31a: 0000 unimp + 31c: 0030 addi a2,sp,8 + 31e: 0000 unimp + 320: 003c addi a5,sp,8 + 322: 0000 unimp + 324: 0040 addi s0,sp,4 + 326: 0000 unimp + 328: 007c addi a5,sp,12 + 32a: 0000 unimp + 32c: 0080 addi s0,sp,64 + 32e: 0000 unimp + 330: 01e4 addi s1,sp,204 + 332: 0000 unimp + 334: 01e8 addi a0,sp,204 + 336: 0000 unimp + 338: 0248 addi a0,sp,260 + 33a: 0000 unimp + 33c: 024c addi a1,sp,260 + 33e: 0000 unimp + 340: 03b4 addi a3,sp,456 + 342: 0000 unimp + 344: 03bc addi a5,sp,456 + ... + 34e: 0000 unimp + 350: 001c 0x1c + 352: 0000 unimp + 354: 0020 addi s0,sp,8 + 356: 0000 unimp + 358: 0044 addi s1,sp,4 + 35a: 0000 unimp + 35c: 004c addi a1,sp,4 + ... + 366: 0000 unimp + 368: 0064 addi s1,sp,12 + 36a: 0000 unimp + 36c: 007c addi a5,sp,12 + 36e: 0000 unimp + 370: 0080 addi s0,sp,64 + 372: 0000 unimp + 374: 00b8 addi a4,sp,72 + 376: 0000 unimp + 378: 00c0 addi s0,sp,68 + 37a: 0000 unimp + 37c: 0124 addi s1,sp,136 + 37e: 0000 unimp + 380: 012c addi a1,sp,136 + 382: 0000 unimp + 384: 019c addi a5,sp,192 + 386: 0000 unimp + 388: 01b8 addi a4,sp,200 + 38a: 0000 unimp + 38c: 01bc addi a5,sp,200 + 38e: 0000 unimp + 390: 01c4 addi s1,sp,196 + 392: 0000 unimp + 394: 01dc addi a5,sp,196 + 396: 0000 unimp + 398: 03c4 addi s1,sp,452 + 39a: 0000 unimp + 39c: 03cc addi a1,sp,452 + ... + 3a6: 0000 unimp + 3a8: 00b8 addi a4,sp,72 + 3aa: 0000 unimp + 3ac: 00c0 addi s0,sp,68 + 3ae: 0000 unimp + 3b0: 019c addi a5,sp,192 + 3b2: 0000 unimp + 3b4: 019c addi a5,sp,192 + 3b6: 0000 unimp + 3b8: 01bc addi a5,sp,200 + 3ba: 0000 unimp + 3bc: 01c4 addi s1,sp,196 + 3be: 0000 unimp + 3c0: 01dc addi a5,sp,196 + 3c2: 0000 unimp + 3c4: 01e4 addi s1,sp,204 + 3c6: 0000 unimp + 3c8: 01e8 addi a0,sp,204 + 3ca: 0000 unimp + 3cc: 0248 addi a0,sp,260 + 3ce: 0000 unimp + 3d0: 024c addi a1,sp,260 + 3d2: 0000 unimp + 3d4: 0294 addi a3,sp,320 + 3d6: 0000 unimp + 3d8: 0298 addi a4,sp,320 + 3da: 0000 unimp + 3dc: 02f4 addi a3,sp,332 + 3de: 0000 unimp + 3e0: 02fc addi a5,sp,332 + 3e2: 0000 unimp + 3e4: 03b4 addi a3,sp,456 + 3e6: 0000 unimp + 3e8: 043c addi a5,sp,520 + 3ea: 0000 unimp + 3ec: 0444 addi s1,sp,516 + ... + 3f6: 0000 unimp + 3f8: 0200 addi s0,sp,256 + 3fa: 0000 unimp + 3fc: 0214 addi a3,sp,256 + 3fe: 0000 unimp + 400: 0354 addi a3,sp,388 + 402: 0000 unimp + 404: 0390 addi a2,sp,448 + 406: 0000 unimp + 408: 03a0 addi s0,sp,456 + 40a: 0000 unimp + 40c: 03b4 addi a3,sp,456 + ... + 416: 0000 unimp + 418: 019c addi a5,sp,192 + 41a: 0000 unimp + 41c: 01b8 addi a4,sp,200 + 41e: 0000 unimp + 420: 03cc addi a1,sp,452 + 422: 0000 unimp + 424: 0404 addi s1,sp,512 + 426: 0000 unimp + 428: 0444 addi s1,sp,516 + 42a: 0000 unimp + 42c: 044c addi a1,sp,516 + ... + 436: 0000 unimp + 438: 0404 addi s1,sp,512 + 43a: 0000 unimp + 43c: 0404 addi s1,sp,512 + 43e: 0000 unimp + 440: 040c addi a1,sp,512 + 442: 0000 unimp + 444: 0428 addi a0,sp,520 + ... + 44e: 0000 unimp + 450: 000c 0xc + 452: 0000 unimp + 454: 000c 0xc + 456: 0000 unimp + 458: 0010 0x10 + 45a: 0000 unimp + 45c: 0014 0x14 + 45e: 0000 unimp + 460: 0024 addi s1,sp,8 + 462: 0000 unimp + 464: 0024 addi s1,sp,8 + ... + 472: 0000 unimp + 474: 0014 0x14 + 476: 0000 unimp + 478: 0014 0x14 + 47a: 0000 unimp + 47c: 0030 addi a2,sp,8 + 47e: 0000 unimp + 480: 0038 addi a4,sp,8 + 482: 0000 unimp + 484: 004c addi a1,sp,4 + ... diff --git a/driver/tests/dogfood/kernel.elf b/driver/tests/dogfood/kernel.elf new file mode 100755 index 00000000..d6a4d862 Binary files /dev/null and b/driver/tests/dogfood/kernel.elf differ diff --git a/driver/tests/dogfood/testcases.h b/driver/tests/dogfood/testcases.h new file mode 100644 index 00000000..7e015b18 --- /dev/null +++ b/driver/tests/dogfood/testcases.h @@ -0,0 +1,581 @@ +#pragma once + +#include +#include +#include + +union Float_t { + float f; + int i; + struct { + uint32_t man : 23; + uint32_t exp : 8; + uint32_t sign : 1; + } parts; +}; + +inline bool almost_equal_eps(float a, float b, float eps = std::numeric_limits::epsilon()) { + auto tolerance = std::max(fabs(a), fabs(b)) * eps; + return fabs(a - b) <= tolerance; +} + +inline bool almost_equal_ulp(float a, float b, int32_t ulp = 4) { + Float_t fa{a}, fb{b}; + return std::abs(fa.i - fb.i) <= ulp; +} + +inline bool almost_equal(float a, float b) { + return almost_equal_ulp(a, b); +} + +class ITestCase { +public: + ITestCase() {} + virtual ~ITestCase() {} + + virtual void setup(int n, void* src1, void* src2) = 0; + virtual int verify(int n, void* dst, const void* src1, const void* src2) = 0; +}; + +class Test_IADD : public ITestCase { +public: + + void setup(int n, void* src1, void* src2) override { + auto a = (int32_t*)src1; + auto b = (int32_t*)src2; + for (int i = 0; i < n; ++i) { + a[i] = n/2 - i; + b[i] = n/2 + i; + } + } + + int verify(int n, void* dst, const void* src1, const void* src2) override { + int errors = 0; + auto a = (int32_t*)src1; + auto b = (int32_t*)src2; + auto c = (int32_t*)dst; + for (int i = 0; i < n; ++i) { + auto ref = a[i] + b[i]; + if (c[i] != ref) { + std::cout << "error at result #" << i << ": expected " << ref << ", actual " << c[i] << ", a=" << a[i] << ", b=" << b[i] << std::endl; + ++errors; + } + } + return errors; + } +}; + +class Test_IMUL : public ITestCase { +public: + + void setup(int n, void* src1, void* src2) override { + auto a = (int32_t*)src1; + auto b = (int32_t*)src2; + for (int i = 0; i < n; ++i) { + a[i] = n/2 - i; + b[i] = n/2 + i; + } + } + + int verify(int n, void* dst, const void* src1, const void* src2) override { + int errors = 0; + auto a = (int32_t*)src1; + auto b = (int32_t*)src2; + auto c = (int32_t*)dst; + for (int i = 0; i < n; ++i) { + auto ref = a[i] * b[i]; + if (c[i] != ref) { + std::cout << "error at result #" << i << ": expected " << ref << ", actual " << c[i] << ", a=" << a[i] << ", b=" << b[i] << std::endl; + ++errors; + } + } + return errors; + } +}; + +class Test_IDIV : public ITestCase { +public: + + void setup(int n, void* src1, void* src2) override { + auto a = (int32_t*)src1; + auto b = (int32_t*)src2; + for (int i = 0; i < n; ++i) { + a[i] = n/2 - i; + b[i] = n/2 + i; + } + } + + int verify(int n, void* dst, const void* src1, const void* src2) override { + int errors = 0; + auto a = (int32_t*)src1; + auto b = (int32_t*)src2; + auto c = (int32_t*)dst; + for (int i = 0; i < n; ++i) { + auto ref = a[i] / b[i]; + if (c[i] != ref) { + std::cout << "error at result #" << i << ": expected " << ref << ", actual " << c[i] << ", a=" << a[i] << ", b=" << b[i] << std::endl; + ++errors; + } + } + return errors; + } +}; + +class Test_IDIV_MUL : public ITestCase { +public: + + void setup(int n, void* src1, void* src2) override { + auto a = (int32_t*)src1; + auto b = (int32_t*)src2; + for (int i = 0; i < n; ++i) { + a[i] = n/2 - i; + b[i] = n/2 + i; + } + } + + int verify(int n, void* dst, const void* src1, const void* src2) override { + int errors = 0; + auto a = (int32_t*)src1; + auto b = (int32_t*)src2; + auto c = (int32_t*)dst; + for (int i = 0; i < n; ++i) { + auto x = a[i] / b[i]; + auto y = a[i] * b[i]; + auto ref = x + y; + if (c[i] != ref) { + std::cout << "error at result #" << i << ": expected " << ref << ", actual " << c[i] << ", a=" << a[i] << ", b=" << b[i] << std::endl; + ++errors; + } + } + return errors; + } +}; + +class Test_FADD : public ITestCase { +public: + + void setup(int n, void* src1, void* src2) override { + auto a = (float*)src1; + auto b = (float*)src2; + for (int i = 0; i < n; ++i) { + a[i] = (n - i) * (1.0f/n); + b[i] = (n + i) * (1.0f/n); + } + } + + int verify(int n, void* dst, const void* src1, const void* src2) override { + int errors = 0; + auto a = (float*)src1; + auto b = (float*)src2; + auto c = (float*)dst; + for (int i = 0; i < n; ++i) { + auto ref = a[i] + b[i]; + if (!almost_equal(c[i], ref)) { + std::cout << "error at result #" << i << ": expected " << ref << ", actual " << c[i] << ", a=" << a[i] << ", b=" << b[i] << std::endl; + ++errors; + } + } + return errors; + } +}; + +class Test_FSUB : public ITestCase { +public: + + void setup(int n, void* src1, void* src2) override { + auto a = (float*)src1; + auto b = (float*)src2; + for (int i = 0; i < n; ++i) { + a[i] = (n - i) * (1.0f/n); + b[i] = (n + i) * (1.0f/n); + } + } + + int verify(int n, void* dst, const void* src1, const void* src2) override { + int errors = 0; + auto a = (float*)src1; + auto b = (float*)src2; + auto c = (float*)dst; + for (int i = 0; i < n; ++i) { + auto ref = a[i] - b[i]; + if (!almost_equal(c[i], ref)) { + std::cout << "error at result #" << i << ": expected " << ref << ", actual " << c[i] << ", a=" << a[i] << ", b=" << b[i] << std::endl; + ++errors; + } + } + return errors; + } +}; + +class Test_FMUL : public ITestCase { +public: + + void setup(int n, void* src1, void* src2) override { + auto a = (float*)src1; + auto b = (float*)src2; + for (int i = 0; i < n; ++i) { + a[i] = (n - i) * (1.0f/n); + b[i] = (n + i) * (1.0f/n); + } + } + + int verify(int n, void* dst, const void* src1, const void* src2) override { + int errors = 0; + auto a = (float*)src1; + auto b = (float*)src2; + auto c = (float*)dst; + for (int i = 0; i < n; ++i) { + auto ref = a[i] * b[i]; + if (!almost_equal(c[i], ref)) { + std::cout << "error at result #" << i << ": expected " << ref << ", actual " << c[i] << ", a=" << a[i] << ", b=" << b[i] << std::endl; + ++errors; + } + } + return errors; + } +}; + +class Test_FMADD : public ITestCase { +public: + + void setup(int n, void* src1, void* src2) override { + auto a = (float*)src1; + auto b = (float*)src2; + for (int i = 0; i < n; ++i) { + a[i] = (n - i) * (1.0f/n); + b[i] = (n + i) * (1.0f/n); + } + } + + int verify(int n, void* dst, const void* src1, const void* src2) override { + int errors = 0; + auto a = (float*)src1; + auto b = (float*)src2; + auto c = (float*)dst; + for (int i = 0; i < n; ++i) { + auto ref = a[i] * b[i] + 0.5f; + if (!almost_equal(c[i], ref)) { + std::cout << "error at result #" << i << ": expected " << ref << ", actual " << c[i] << ", a=" << a[i] << ", b=" << b[i] << std::endl; + ++errors; + } + } + return errors; + } +}; + +class Test_FMSUB : public ITestCase { +public: + + void setup(int n, void* src1, void* src2) override { + auto a = (float*)src1; + auto b = (float*)src2; + for (int i = 0; i < n; ++i) { + a[i] = (n - i) * (1.0f/n); + b[i] = (n + i) * (1.0f/n); + } + } + + int verify(int n, void* dst, const void* src1, const void* src2) override { + int errors = 0; + auto a = (float*)src1; + auto b = (float*)src2; + auto c = (float*)dst; + for (int i = 0; i < n; ++i) { + auto ref = a[i] * b[i] - 0.5f; + if (!almost_equal(c[i], ref)) { + std::cout << "error at result #" << i << ": expected " << ref << ", actual " << c[i] << ", a=" << a[i] << ", b=" << b[i] << std::endl; + ++errors; + } + } + return errors; + } +}; + +class Test_FNMADD : public ITestCase { +public: + + void setup(int n, void* src1, void* src2) override { + auto a = (float*)src1; + auto b = (float*)src2; + for (int i = 0; i < n; ++i) { + a[i] = (n - i) * (1.0f/n); + b[i] = (n + i) * (1.0f/n); + } + } + + int verify(int n, void* dst, const void* src1, const void* src2) override { + int errors = 0; + auto a = (float*)src1; + auto b = (float*)src2; + auto c = (float*)dst; + for (int i = 0; i < n; ++i) { + auto ref = -a[i] * b[i] - 0.5f; + if (!almost_equal(c[i], ref)) { + std::cout << "error at result #" << i << ": expected " << ref << ", actual " << c[i] << ", a=" << a[i] << ", b=" << b[i] << std::endl; + ++errors; + } + } + return errors; + } +}; + +class Test_FNMSUB : public ITestCase { +public: + + void setup(int n, void* src1, void* src2) override { + auto a = (float*)src1; + auto b = (float*)src2; + for (int i = 0; i < n; ++i) { + a[i] = (n - i) * (1.0f/n); + b[i] = (n + i) * (1.0f/n); + } + } + + int verify(int n, void* dst, const void* src1, const void* src2) override { + int errors = 0; + auto a = (float*)src1; + auto b = (float*)src2; + auto c = (float*)dst; + for (int i = 0; i < n; ++i) { + auto ref = -a[i] * b[i] + 0.5f; + if (!almost_equal(c[i], ref)) { + std::cout << "error at result #" << i << ": expected " << ref << ", actual " << c[i] << ", a=" << a[i] << ", b=" << b[i] << std::endl; + ++errors; + } + } + return errors; + } +}; + +class Test_FNMADD_MADD : public ITestCase { +public: + + void setup(int n, void* src1, void* src2) override { + auto a = (float*)src1; + auto b = (float*)src2; + for (int i = 0; i < n; ++i) { + a[i] = (n - i) * (1.0f/n); + b[i] = (n + i) * (1.0f/n); + } + } + + int verify(int n, void* dst, const void* src1, const void* src2) override { + int errors = 0; + auto a = (float*)src1; + auto b = (float*)src2; + auto c = (float*)dst; + for (int i = 0; i < n; ++i) { + auto x = -a[i] * b[i] - 0.5f; + auto y = a[i] * b[i] + 0.5f; + auto ref = x + y; + if (!almost_equal(c[i], ref)) { + std::cout << "error at result #" << i << ": expected " << ref << ", actual " << c[i] << ", a=" << a[i] << ", b=" << b[i] << std::endl; + ++errors; + } + } + return errors; + } +}; + +class Test_FDIV : public ITestCase { +public: + + void setup(int n, void* src1, void* src2) override { + auto a = (float*)src1; + auto b = (float*)src2; + for (int i = 0; i < n; ++i) { + a[i] = (n - i) * (1.0f/n); + b[i] = (n + i) * (1.0f/n); + } + } + + int verify(int n, void* dst, const void* src1, const void* src2) override { + int errors = 0; + auto a = (float*)src1; + auto b = (float*)src2; + auto c = (float*)dst; + for (int i = 0; i < n; ++i) { + auto ref = a[i] / b[i]; + if (!almost_equal(c[i], ref)) { + std::cout << "error at result #" << i << ": expected " << ref << ", actual " << c[i] << ", a=" << a[i] << ", b=" << b[i] << std::endl; + ++errors; + } + } + return errors; + } +}; + +class Test_FDIV2 : public ITestCase { +public: + + void setup(int n, void* src1, void* src2) override { + auto a = (float*)src1; + auto b = (float*)src2; + for (int i = 0; i < n; ++i) { + a[i] = (n - i) * (1.0f/n); + b[i] = (n + i) * (1.0f/n); + } + } + + int verify(int n, void* dst, const void* src1, const void* src2) override { + int errors = 0; + auto a = (float*)src1; + auto b = (float*)src2; + auto c = (float*)dst; + for (int i = 0; i < n; ++i) { + auto x = a[i] / b[i]; + auto y = b[i] / a[i]; + auto ref = x + y; + if (!almost_equal(c[i], ref)) { + std::cout << "error at result #" << i << ": expected " << ref << ", actual " << c[i] << ", a=" << a[i] << ", b=" << b[i] << std::endl; + ++errors; + } + } + return errors; + } +}; + +class Test_FSQRT : public ITestCase { +public: + + void setup(int n, void* src1, void* src2) override { + auto a = (float*)src1; + auto b = (float*)src2; + for (int i = 0; i < n; ++i) { + int q = 1.0f + (i % 64); + a[i] = q; + b[i] = q; + } + } + + int verify(int n, void* dst, const void* src1, const void* src2) override { + int errors = 0; + auto a = (float*)src1; + auto b = (float*)src2; + auto c = (float*)dst; + for (int i = 0; i < n; ++i) { + auto ref = sqrt(a[i] * b[i]); + if (!almost_equal(c[i], ref)) { + std::cout << "error at result #" << i << ": expected " << ref << ", actual " << c[i] << ", a=" << a[i] << ", b=" << b[i] << std::endl; + ++errors; + } + } + return errors; + } +}; + +class Test_FTOI : public ITestCase { +public: + + void setup(int n, void* src1, void* src2) override { + auto a = (float*)src1; + auto b = (float*)src2; + for (int i = 0; i < n; ++i) { + a[i] = (n/2 - i) * (1.0f/n); + b[i] = (n/2 - i) * (1.0f/n); + } + } + + int verify(int n, void* dst, const void* src1, const void* src2) override { + int errors = 0; + auto a = (float*)src1; + auto b = (float*)src2; + auto c = (int32_t*)dst; + for (int i = 0; i < n; ++i) { + auto x = a[i] + b[i]; + auto ref = (int32_t)x; + if (c[i] != ref) { + std::cout << "error at result #" << i << ": expected " << ref << ", actual " << c[i] << ", a=" << a[i] << ", b=" << b[i] << std::endl; + ++errors; + } + } + return errors; + } +}; + +class Test_FTOU : public ITestCase { +public: + + void setup(int n, void* src1, void* src2) override { + auto a = (float*)src1; + auto b = (float*)src2; + for (int i = 0; i < n; ++i) { + a[i] = i * (1.0f/n); + b[i] = i * (1.0f/n); + } + } + + int verify(int n, void* dst, const void* src1, const void* src2) override { + int errors = 0; + auto a = (float*)src1; + auto b = (float*)src2; + auto c = (uint32_t*)dst; + for (int i = 0; i < n; ++i) { + auto x = a[i] + b[i]; + auto ref = (uint32_t)x; + if (c[i] != ref) { + std::cout << "error at result #" << i << ": expected " << ref << ", actual " << c[i] << ", a=" << a[i] << ", b=" << b[i] << std::endl; + ++errors; + } + } + return errors; + } +}; + +class Test_ITOF : public ITestCase { +public: + + void setup(int n, void* src1, void* src2) override { + auto a = (int32_t*)src1; + auto b = (int32_t*)src2; + for (int i = 0; i < n; ++i) { + a[i] = n/2 - i; + b[i] = n/2 - i; + } + } + + int verify(int n, void* dst, const void* src1, const void* src2) override { + int errors = 0; + auto a = (int32_t*)src1; + auto b = (int32_t*)src2; + auto c = (float*)dst; + for (int i = 0; i < n; ++i) { + auto x = a[i] + b[i]; + auto ref = (float)x; + if (!almost_equal(c[i], ref)) { + std::cout << "error at result #" << i << ": expected " << ref << ", actual " << c[i] << ", a=" << a[i] << ", b=" << b[i] << std::endl; + ++errors; + } + } + return errors; + } +}; + +class Test_UTOF : public ITestCase { +public: + + void setup(int n, void* src1, void* src2) override { + auto a = (uint32_t*)src1; + auto b = (uint32_t*)src2; + for (int i = 0; i < n; ++i) { + a[i] = i; + b[i] = i; + } + } + + int verify(int n, void* dst, const void* src1, const void* src2) override { + int errors = 0; + auto a = (uint32_t*)src1; + auto b = (uint32_t*)src2; + auto c = (float*)dst; + for (int i = 0; i < n; ++i) { + auto x = a[i] + b[i]; + auto ref = (float)x; + if (!almost_equal(c[i], ref)) { + std::cout << "error at result #" << i << ": expected " << ref << ", actual " << c[i] << ", a=" << a[i] << ", b=" << b[i] << std::endl; + ++errors; + } + } + return errors; + } +}; \ No newline at end of file diff --git a/hw/Makefile b/hw/Makefile index 4c5575a4..d615dfc0 100644 --- a/hw/Makefile +++ b/hw/Makefile @@ -1,4 +1,7 @@ .PHONY: build_config build_config: - ./scripts/gen_config.py --outv ./rtl/VX_user_config.vh --outc ./VX_config.h \ No newline at end of file + ./scripts/gen_config.py --outv ./rtl/VX_user_config.vh --outc ./VX_config.h + +clean: + rm ./rtl/VX_user_config.vh ./VX_config.h \ No newline at end of file diff --git a/hw/opae/Makefile b/hw/opae/Makefile index eddd6849..6c57a567 100644 --- a/hw/opae/Makefile +++ b/hw/opae/Makefile @@ -4,14 +4,22 @@ FPGA_BUILD_DIR=build_fpga all: ase-1c -ase-1c: setup-ase-1c +sources.txt: + ./gen_sources.sh > sources.txt + +gen_sources: sources.txt + +ase-1c: gen_sources setup-ase-1c make -C $(ASE_BUILD_DIR)_1c + cp ../rtl/fp_cores/altera/*.hex $(ASE_BUILD_DIR)_1c/work -ase-2c: setup-ase-2c +ase-2c: gen_sources setup-ase-2c make -C $(ASE_BUILD_DIR)_2c + cp ../rtl/fp_cores/altera/*.hex $(ASE_BUILD_DIR)_2c/work -ase-4c: setup-ase-4c +ase-4c: gen_sources setup-ase-4c make -C $(ASE_BUILD_DIR)_4c + cp ../rtl/fp_cores/altera/*.hex $(ASE_BUILD_DIR)_3c/work setup-ase-1c: $(ASE_BUILD_DIR)_1c/Makefile @@ -19,23 +27,26 @@ setup-ase-2c: $(ASE_BUILD_DIR)_2c/Makefile setup-ase-4c: $(ASE_BUILD_DIR)_4c/Makefile -$(ASE_BUILD_DIR)_1c/Makefile: +$(ASE_BUILD_DIR)_1c/Makefile: sources.txt afu_sim_setup -s sources_1c.txt $(ASE_BUILD_DIR)_1c -$(ASE_BUILD_DIR)_2c/Makefile: +$(ASE_BUILD_DIR)_2c/Makefile: sources.txt afu_sim_setup -s sources_2c.txt $(ASE_BUILD_DIR)_2c -$(ASE_BUILD_DIR)_4c/Makefile: +$(ASE_BUILD_DIR)_4c/Makefile: sources.txt afu_sim_setup -s sources_4c.txt $(ASE_BUILD_DIR)_4c -fpga-1c: setup-fpga-1c +fpga-1c: gen_sources setup-fpga-1c cd $(FPGA_BUILD_DIR)_1c && qsub-synth + cp ../rtl/fp_cores/altera/*.hex $(FPGA_BUILD_DIR)_1c -fpga-2c: setup-fpga-2c +fpga-2c: gen_sources setup-fpga-2c cd $(FPGA_BUILD_DIR)_2c && qsub-synth + cp ../rtl/fp_cores/altera/*.hex $(FPGA_BUILD_DIR)_2c -fpga-4c: setup-fpga-4c +fpga-4c: gen_sources setup-fpga-4c cd $(FPGA_BUILD_DIR)_4c && qsub-synth + cp ../rtl/fp_cores/altera/*.hex $(FPGA_BUILD_DIR)_4c setup-fpga-1c: $(FPGA_BUILD_DIR)_1c/build/dcp.qpf @@ -62,20 +73,20 @@ run-ase-4c: cd $(ASE_BUILD_DIR)_4c && make sim clean-ase-1c: - rm -rf $(ASE_BUILD_DIR)_1c + rm -rf $(ASE_BUILD_DIR)_1c sources.txt clean-ase-2c: - rm -rf $(ASE_BUILD_DIR)_2c + rm -rf $(ASE_BUILD_DIR)_2c sources.txt clean-ase-4c: - rm -rf $(ASE_BUILD_DIR)_4c + rm -rf $(ASE_BUILD_DIR)_4c sources.txt clean-fpga-1c: - rm -rf $(FPGA_BUILD_DIR)_1c + rm -rf $(FPGA_BUILD_DIR)_1c sources.txt clean-fpga-2c: - rm -rf $(FPGA_BUILD_DIR)_2c + rm -rf $(FPGA_BUILD_DIR)_2c sources.txt clean-fpga-4c: - rm -rf $(FPGA_BUILD_DIR)_4c + rm -rf $(FPGA_BUILD_DIR)_4c sources.txt diff --git a/hw/opae/README b/hw/opae/README index 86e6f862..611adec4 100644 --- a/hw/opae/README +++ b/hw/opae/README @@ -60,8 +60,9 @@ qsub-sim make ase # tests -./run_ase.sh build_ase_1c ../../driver/tests/basic/basic -./run_ase.sh build_ase_1c ../../driver/tests/demo/demo +./run_ase.sh build_ase_1c ../../driver/tests/basic/basic -n 256 +./run_ase.sh build_ase_1c ../../driver/tests/demo/demo -n 16 +./run_ase.sh build_ase_1c ../../driver/tests/dogfood/dogfood -n1 -s4 -e4 ./run_ase.sh build_ase_1c ../../benchmarks/opencl/vecadd/vecadd # modify "vsim_run.tcl" to dump VCD trace @@ -74,6 +75,10 @@ tar -zcvf output_files_1c.tar.gz `find ./build_fpga_1c -type f \( -iname \*.rpt # compress VCD trace tar -zcvf vortex.vcd.tar.gz ./build_ase_1c/work/vortex.vcd +tar -zcvf trace.vcd.tar.gz obj_dir/trace.vcd +tar -zcvf trace.vcd.tar.gz trace.vcd +tar -zcvf run.log.tar.gz run.log +tar -cvjf vortex.vcd.tar.bz2 build_ase_1c/work/vortex.vcd # decompress VCD trace tar -zxvf /mnt/c/Users/Blaise/Downloads/vortex.vcd.tar.gz @@ -89,8 +94,16 @@ kill -9 lsof +D build_ase_1c # quick off cache synthesis -make -C pipeline > pipeline/build.log 2>&1 & -make -C cache > cache/build.log 2>&1 & -make -C core > core/build.log 2>&1 & -make -C vortex > vortex/build.log 2>&1 & -make -C top > top/build.log 2>&1 & +make -C pipeline clean && make -C pipeline > pipeline/build.log 2>&1 & +make -C cache clean && make -C cache > cache/build.log 2>&1 & +make -C core clean && make -C core > core/build.log 2>&1 & +make -C vortex clean && make -C vortex > vortex/build.log 2>&1 & +make -C top clean && make -C top > top/build.log 2>&1 & + +# How to calculate the maximum operating frequency? +200 Mhz -> period = 1/200x10^6 = 5ns +if slack = +1.664 -> minimal period = 5-1.664 = 3.336 -> fmax = 1/3.336 = 300 Mhz + + +# build rtlsim from driver tests +make -C ../../rtlsim clean && reset && make -C ../../rtlsim \ No newline at end of file diff --git a/hw/opae/gen_sources.sh b/hw/opae/gen_sources.sh new file mode 100755 index 00000000..0120d34f --- /dev/null +++ b/hw/opae/gen_sources.sh @@ -0,0 +1,20 @@ +#!/bin/bash + +dir_list='../rtl/libs ../rtl/cache ../rtl/interfaces ../rtl ../rtl/fp_cores/fpnew/src/common_cells/include ../rtl/fp_cores ../rtl/fp_cores/altera' +exclude_list='VX_fpnew.v' + +# read design sources +for dir in $dir_list; do + echo "+incdir+$dir" + for file in $(find $dir -maxdepth 1 -name '*.v' -o -name '*.sv' -type f); do + exclude=0 + for fe in $exclude_list; do + if [[ $file =~ $fe ]]; then + exclude=1 + fi + done + if [[ $exclude == 0 ]]; then + echo $file + fi + done +done \ No newline at end of file diff --git a/hw/opae/sources.txt b/hw/opae/sources.txt deleted file mode 100644 index 0b448e88..00000000 --- a/hw/opae/sources.txt +++ /dev/null @@ -1,112 +0,0 @@ -vortex_afu.json - -QI:vortex_afu.qsf - -#+define+SCOPE - -#+define+DBG_PRINT_CORE_ICACHE -#+define+DBG_PRINT_CORE_DCACHE -#+define+DBG_PRINT_CACHE_BANK -#+define+DBG_PRINT_CACHE_SNP -#+define+DBG_PRINT_CACHE_MSRQ -#+define+DBG_PRINT_DRAM -#+define+DBG_PRINT_PIPELINE -#+define+DBG_PRINT_OPAE -#+define+DBG_PRINT_SCOPE - -+incdir+. -+incdir+../rtl -+incdir+../rtl/interfaces -+incdir+../rtl/pipe_regs -+incdir+../rtl/cache -+incdir+../rtl/libs - -../rtl/VX_user_config.vh -../rtl/VX_config.vh -../rtl/VX_define.vh - -../rtl/cache/VX_cache_config.vh -../rtl/cache/VX_cache.v -../rtl/cache/VX_cache_core_rsp_merge.v -../rtl/cache/VX_cache_core_req_bank_sel.v -../rtl/cache/VX_cache_dram_req_arb.v -../rtl/cache/VX_cache_dram_fill_arb.v -../rtl/cache/VX_cache_miss_resrv.v -../rtl/cache/VX_bank.v -../rtl/cache/VX_bank_core_req_arb.v -../rtl/cache/VX_snp_rsp_arb.v -../rtl/cache/VX_tag_data_access.v -../rtl/cache/VX_tag_data_structure.v -../rtl/cache/VX_snp_forwarder.v -../rtl/cache/VX_prefetcher.v - -../rtl/interfaces/VX_branch_rsp_if.v -../rtl/interfaces/VX_cache_core_req_if.v -../rtl/interfaces/VX_cache_core_rsp_if.v -../rtl/interfaces/VX_cache_dram_req_if.v -../rtl/interfaces/VX_cache_dram_rsp_if.v -../rtl/interfaces/VX_cache_snp_req_if.v -../rtl/interfaces/VX_cache_snp_rsp_if.v -../rtl/interfaces/VX_csr_req_if.v -../rtl/interfaces/VX_csr_io_req_if.v -../rtl/interfaces/VX_csr_io_rsp_if.v -../rtl/interfaces/VX_exec_unit_req_if.v -../rtl/interfaces/VX_backend_req_if.v -../rtl/interfaces/VX_gpr_read_if.v -../rtl/interfaces/VX_gpu_inst_req_if.v -../rtl/interfaces/VX_inst_meta_if.v -../rtl/interfaces/VX_jal_rsp_if.v -../rtl/interfaces/VX_join_if.v -../rtl/interfaces/VX_lsu_req_if.v -../rtl/interfaces/VX_warp_ctl_if.v -../rtl/interfaces/VX_wb_if.v -../rtl/interfaces/VX_wstall_if.v - -../rtl/libs/VX_generic_register.v -../rtl/libs/VX_mult.v -../rtl/libs/VX_divide.v -../rtl/libs/VX_generic_stack.v -../rtl/libs/VX_priority_encoder.v -../rtl/libs/VX_generic_queue.v -../rtl/libs/VX_indexable_queue.v -../rtl/libs/VX_fair_arbiter.v -../rtl/libs/VX_fixed_arbiter.v -../rtl/libs/VX_rr_arbiter.v -../rtl/libs/VX_countones.v -../rtl/libs/VX_scope.v - -../rtl/Vortex.v -../rtl/VX_cluster.v -../rtl/VX_core.v -../rtl/VX_mem_unit.v -../rtl/VX_pipeline.v -../rtl/VX_front_end.v -../rtl/VX_back_end.v -../rtl/VX_fetch.v -../rtl/VX_scheduler.v -../rtl/VX_exec_unit.v -../rtl/VX_warp.v -../rtl/VX_icache_stage.v -../rtl/VX_gpr_wrapper.v -../rtl/VX_gpu_inst.v -../rtl/VX_writeback.v -../rtl/VX_csr_pipe.v -../rtl/VX_csr_data.v -../rtl/VX_csr_arb.v -../rtl/VX_csr_io_arb.v -../rtl/VX_warp_sched.v -../rtl/VX_gpr_ram.v -../rtl/VX_gpr_stage.v -../rtl/VX_alu_unit.v -../rtl/VX_lsu_unit.v -../rtl/VX_decode.v -../rtl/VX_inst_multiplex.v -../rtl/VX_dcache_arb.v -../rtl/VX_mem_arb.v -../rtl/VX_f_d_reg.v -../rtl/VX_i_d_reg.v -../rtl/VX_d_e_reg.v - -ccip_interface_reg.sv -ccip_std_afu.sv -vortex_afu.sv \ No newline at end of file diff --git a/hw/opae/sources_1c.txt b/hw/opae/sources_1c.txt index 8cbd9b8f..897468c2 100644 --- a/hw/opae/sources_1c.txt +++ b/hw/opae/sources_1c.txt @@ -1,3 +1,25 @@ +define+NUM_CORES=1 ++define+SYNTHESIS ++define+QUARTUS ++define+FPU_FAST +#+define+SCOPE + +#+define+DBG_PRINT_CORE_ICACHE +#+define+DBG_PRINT_CORE_DCACHE +#+define+DBG_PRINT_CACHE_BANK +#+define+DBG_PRINT_CACHE_SNP +#+define+DBG_PRINT_CACHE_MSRQ +#+define+DBG_PRINT_DRAM +#+define+DBG_PRINT_PIPELINE +#+define+DBG_PRINT_OPAE +#+define+DBG_CORE_REQ_INFO +#+define+DBG_PRINT_SCOPE + +vortex_afu.json +QI:vortex_afu.qsf +ccip_interface_reg.sv +ccip_std_afu.sv +vortex_afu.sv + C:sources.txt \ No newline at end of file diff --git a/hw/opae/sources_2c.txt b/hw/opae/sources_2c.txt index d32f448f..34a20a0b 100644 --- a/hw/opae/sources_2c.txt +++ b/hw/opae/sources_2c.txt @@ -1,4 +1,13 @@ +define+NUM_CORES=2 +define+L2_ENABLE=0 ++define+SYNTHESIS ++define+QUARTUS ++define+FPU_FAST + +vortex_afu.json +QI:vortex_afu.qsf +ccip_interface_reg.sv +ccip_std_afu.sv +vortex_afu.sv C:sources.txt \ No newline at end of file diff --git a/hw/opae/sources_4c.txt b/hw/opae/sources_4c.txt index 03959c74..4772d476 100644 --- a/hw/opae/sources_4c.txt +++ b/hw/opae/sources_4c.txt @@ -1,4 +1,13 @@ +define+NUM_CORES=4 +define+L2_ENABLE=0 ++define+SYNTHESIS ++define+QUARTUS ++define+FPU_FAST + +vortex_afu.json +QI:vortex_afu.qsf +ccip_interface_reg.sv +ccip_std_afu.sv +vortex_afu.sv C:sources.txt \ No newline at end of file diff --git a/hw/opae/vortex_afu.qsf b/hw/opae/vortex_afu.qsf index 75c1bda1..96b1c98b 100644 --- a/hw/opae/vortex_afu.qsf +++ b/hw/opae/vortex_afu.qsf @@ -1,7 +1,9 @@ # Analysis & Synthesis Assignments set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2009 -set_global_assignment -name ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS ON +# set_global_assignment -name ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS ON set_global_assignment -name VERILOG_MACRO QUARTUS set_global_assignment -name VERILOG_MACRO SYNTHESIS -set_global_assignment -name VERILOG_MACRO NDEBUG \ No newline at end of file +set_global_assignment -name VERILOG_MACRO NDEBUG +set_global_assignment -name MESSAGE_DISABLE 16818 +set_global_assignment -name VERILOG_MACRO FPU_FAST \ No newline at end of file diff --git a/hw/opae/vortex_afu.sv b/hw/opae/vortex_afu.sv index 5f13fd77..63ae563c 100644 --- a/hw/opae/vortex_afu.sv +++ b/hw/opae/vortex_afu.sv @@ -913,10 +913,9 @@ assign cmd_run_done = !vx_busy; Vortex #() vortex ( `SCOPE_SIGNALS_ISTAGE_BIND `SCOPE_SIGNALS_LSU_BIND - `SCOPE_SIGNALS_CORE_BIND `SCOPE_SIGNALS_CACHE_BIND - `SCOPE_SIGNALS_PIPELINE_BIND - `SCOPE_SIGNALS_BE_BIND + `SCOPE_SIGNALS_ISSUE_BIND + `SCOPE_SIGNALS_EXECUTE_BIND .clk (clk), .reset (SoftReset | vx_reset), @@ -988,32 +987,36 @@ Vortex #() vortex ( localparam SCOPE_DATAW = $bits({`SCOPE_SIGNALS_DATA_LIST `SCOPE_SIGNALS_UPD_LIST}); localparam SCOPE_SR_DEPTH = 2; -`SCOPE_ASSIGN(scope_dram_req_valid, vx_dram_req_valid); -`SCOPE_ASSIGN(scope_dram_req_addr, {vx_dram_req_addr, 4'b0}); -`SCOPE_ASSIGN(scope_dram_req_rw, vx_dram_req_rw); -`SCOPE_ASSIGN(scope_dram_req_byteen,vx_dram_req_byteen); -`SCOPE_ASSIGN(scope_dram_req_data, vx_dram_req_data); -`SCOPE_ASSIGN(scope_dram_req_tag, vx_dram_req_tag); -`SCOPE_ASSIGN(scope_dram_req_ready, vx_dram_req_ready); +`STATIC_ASSERT(SCOPE_DATAW == 1766, "invalid size") -`SCOPE_ASSIGN(scope_dram_rsp_valid, vx_dram_rsp_valid); -`SCOPE_ASSIGN(scope_dram_rsp_data, vx_dram_rsp_data); -`SCOPE_ASSIGN(scope_dram_rsp_tag, vx_dram_rsp_tag); -`SCOPE_ASSIGN(scope_dram_rsp_ready, vx_dram_rsp_ready); +`SCOPE_ASSIGN (scope_dram_req_valid, vx_dram_req_valid); +`SCOPE_ASSIGN (scope_dram_req_addr, {vx_dram_req_addr, 4'b0}); +`SCOPE_ASSIGN (scope_dram_req_rw, vx_dram_req_rw); +`SCOPE_ASSIGN (scope_dram_req_byteen,vx_dram_req_byteen); +`SCOPE_ASSIGN (scope_dram_req_data, vx_dram_req_data); +`SCOPE_ASSIGN (scope_dram_req_tag, vx_dram_req_tag); +`SCOPE_ASSIGN (scope_dram_req_ready, vx_dram_req_ready); -`SCOPE_ASSIGN(scope_snp_req_valid, vx_snp_req_valid); -`SCOPE_ASSIGN(scope_snp_req_addr, {vx_snp_req_addr, 4'b0}); -`SCOPE_ASSIGN(scope_snp_req_invalidate, vx_snp_req_invalidate); -`SCOPE_ASSIGN(scope_snp_req_tag, vx_snp_req_tag); -`SCOPE_ASSIGN(scope_snp_req_ready, vx_snp_req_ready); +`SCOPE_ASSIGN (scope_dram_rsp_valid, vx_dram_rsp_valid); +`SCOPE_ASSIGN (scope_dram_rsp_data, vx_dram_rsp_data); +`SCOPE_ASSIGN (scope_dram_rsp_tag, vx_dram_rsp_tag); +`SCOPE_ASSIGN (scope_dram_rsp_ready, vx_dram_rsp_ready); -`SCOPE_ASSIGN(scope_snp_rsp_valid, vx_snp_rsp_valid); -`SCOPE_ASSIGN(scope_snp_rsp_tag, vx_snp_rsp_tag); -`SCOPE_ASSIGN(scope_snp_rsp_ready, vx_snp_rsp_ready); +`SCOPE_ASSIGN (scope_snp_req_valid, vx_snp_req_valid); +`SCOPE_ASSIGN (scope_snp_req_addr, {vx_snp_req_addr, 4'b0}); +`SCOPE_ASSIGN (scope_snp_req_invalidate, vx_snp_req_invalidate); +`SCOPE_ASSIGN (scope_snp_req_tag, vx_snp_req_tag); +`SCOPE_ASSIGN (scope_snp_req_ready, vx_snp_req_ready); -`SCOPE_ASSIGN(scope_snp_rsp_valid, vx_snp_rsp_valid); -`SCOPE_ASSIGN(scope_snp_rsp_tag, vx_snp_rsp_tag); -`SCOPE_ASSIGN(scope_snp_rsp_ready, vx_snp_rsp_ready); +`SCOPE_ASSIGN (scope_snp_rsp_valid, vx_snp_rsp_valid); +`SCOPE_ASSIGN (scope_snp_rsp_tag, vx_snp_rsp_tag); +`SCOPE_ASSIGN (scope_snp_rsp_ready, vx_snp_rsp_ready); + +`SCOPE_ASSIGN (scope_snp_rsp_valid, vx_snp_rsp_valid); +`SCOPE_ASSIGN (scope_snp_rsp_tag, vx_snp_rsp_tag); +`SCOPE_ASSIGN (scope_snp_rsp_ready, vx_snp_rsp_ready); + +`SCOPE_ASSIGN (scope_busy, vx_busy); wire scope_changed = (scope_icache_req_valid && scope_icache_req_ready) || (scope_icache_rsp_valid && scope_icache_rsp_ready) @@ -1023,10 +1026,16 @@ wire scope_changed = (scope_icache_req_valid && scope_icache_req_ready) || (scope_dram_rsp_valid && scope_dram_rsp_ready) || (scope_snp_req_valid && scope_snp_req_ready) || (scope_snp_rsp_valid && scope_snp_rsp_ready) + || (scope_issue_valid && scope_issue_ready) + || scope_gpr_rsp_valid || scope_bank_valid_st0 || scope_bank_valid_st1 || scope_bank_valid_st2 - || scope_bank_stall_pipe; + || scope_bank_stall_pipe + || scope_scoreboard_delay + || scope_gpr_delay + || scope_execute_delay + || scope_busy; wire scope_start = vx_reset; @@ -1035,8 +1044,7 @@ wire [SCOPE_DATAW+1:0] scope_data_in_ste; assign scope_data_in_st[0] = {`SCOPE_SIGNALS_DATA_LIST `SCOPE_SIGNALS_UPD_LIST, scope_changed, scope_start}; assign scope_data_in_ste = scope_data_in_st[SCOPE_SR_DEPTH-1]; -genvar i; -for (i = 1; i < SCOPE_SR_DEPTH; i++) begin +for (genvar i = 1; i < SCOPE_SR_DEPTH; i++) begin VX_generic_register #( .N (SCOPE_DATAW+2) ) scope_sr ( diff --git a/hw/rtl/VX_alu_unit.v b/hw/rtl/VX_alu_unit.v index d1b30016..a2257e15 100644 --- a/hw/rtl/VX_alu_unit.v +++ b/hw/rtl/VX_alu_unit.v @@ -1,132 +1,125 @@ `include "VX_define.vh" -module VX_alu_unit ( - input wire clk, - input wire reset, - input wire [31:0] src_a, - input wire [31:0] src_b, - input wire src_rs2, - input wire [31:0] itype_immed, - input wire [19:0] upper_immed, - input wire [4:0] alu_op, - input wire [31:0] curr_PC, - output reg [31:0] alu_result, - output reg alu_stall -); - wire[31:0] div_result_unsigned; - wire[31:0] div_result_signed; - - wire[31:0] rem_result_unsigned; - wire[31:0] rem_result_signed; - - wire[63:0] mul_result; - - wire[31:0] alu_in1 = src_a; - wire[31:0] alu_in2 = (src_rs2 == `RS2_IMMED) ? itype_immed : src_b; - - wire[31:0] upper_immed_s = {upper_immed, {12{1'b0}}}; +module VX_alu_unit #( + parameter CORE_ID = 0 +) ( + input wire clk, + input wire reset, - reg [7:0] inst_delay; - reg [7:0] curr_inst_delay; - - always @(*) begin - case (alu_op) - `ALU_DIV, - `ALU_DIVU, - `ALU_REM, - `ALU_REMU: inst_delay = `DIV_LATENCY; - `ALU_MUL, - `ALU_MULH, - `ALU_MULHSU, - `ALU_MULHU: inst_delay = `MUL_LATENCY; - default: inst_delay = 0; - endcase + // Inputs + VX_alu_req_if alu_req_if, + + // Outputs + VX_branch_ctl_if branch_ctl_if, + VX_exu_to_cmt_if alu_commit_if +); + reg [`NUM_THREADS-1:0][31:0] alu_result; + reg [`NUM_THREADS-1:0][31:0] add_result; + reg [`NUM_THREADS-1:0][32:0] sub_result; + reg [`NUM_THREADS-1:0][31:0] shr_result; + reg [`NUM_THREADS-1:0][31:0] msc_result; + + wire is_br_op = alu_req_if.is_br_op; + wire [`ALU_BITS-1:0] alu_op = `ALU_OP(alu_req_if.op_type); + wire [`BR_BITS-1:0] br_op = `BR_OP(alu_req_if.op_type); + wire alu_signed = `ALU_SIGNED(alu_op); + wire [1:0] alu_op_class = `ALU_OP_CLASS(alu_op); + wire is_sub = (alu_op == `ALU_SUB); + + wire [`NUM_THREADS-1:0][31:0] alu_in1 = alu_req_if.rs1_data; + wire [`NUM_THREADS-1:0][31:0] alu_in2 = alu_req_if.rs2_data; + + wire [`NUM_THREADS-1:0][31:0] alu_in1_PC = alu_req_if.rs1_is_PC ? {`NUM_THREADS{alu_req_if.PC}} : alu_in1; + wire [`NUM_THREADS-1:0][31:0] alu_in2_imm = alu_req_if.rs2_is_imm ? {`NUM_THREADS{alu_req_if.imm}} : alu_in2; + wire [`NUM_THREADS-1:0][31:0] alu_in2_less = (alu_req_if.rs2_is_imm && ~is_br_op) ? {`NUM_THREADS{alu_req_if.imm}} : alu_in2; + + for (genvar i = 0; i < `NUM_THREADS; i++) begin + always @(*) begin + add_result[i] = alu_in1_PC[i] + alu_in2_imm[i]; + end end - wire inst_stalled = (curr_inst_delay != inst_delay); - - always @(posedge clk) begin - if (reset) begin - curr_inst_delay <= 0; - end else begin - curr_inst_delay <= inst_stalled ? (curr_inst_delay + 1) : 0; - end + for (genvar i = 0; i < `NUM_THREADS; i++) begin + wire [32:0] sub_in1 = {alu_signed & alu_in1[i][31], alu_in1[i]}; + wire [32:0] sub_in2 = {alu_signed & alu_in2_less[i][31], alu_in2_less[i]}; + always @(*) begin + sub_result[i] = $signed(sub_in1) - $signed(sub_in2); + end end - assign alu_stall = inst_stalled; + for (genvar i = 0; i < `NUM_THREADS; i++) begin + wire [32:0] shr_in1 = {alu_signed & alu_in1[i][31], alu_in1[i]}; + `IGNORE_WARNINGS_BEGIN + wire [32:0] shr_value = $signed(shr_in1) >>> alu_in2_imm[i][4:0]; + `IGNORE_WARNINGS_END + always @(*) begin + shr_result[i] = shr_value[31:0]; + end + end - always @(*) begin - case (alu_op) - `ALU_ADD: alu_result = $signed(alu_in1) + $signed(alu_in2); - `ALU_SUB: alu_result = $signed(alu_in1) - $signed(alu_in2); - `ALU_SLLA: alu_result = alu_in1 << alu_in2[4:0]; - `ALU_SLT: alu_result = ($signed(alu_in1) < $signed(alu_in2)) ? 32'h1 : 32'h0; - `ALU_SLTU: alu_result = alu_in1 < alu_in2 ? 32'h1 : 32'h0; - `ALU_XOR: alu_result = alu_in1 ^ alu_in2; - `ALU_SRL: alu_result = alu_in1 >> alu_in2[4:0]; - `ALU_SRA: alu_result = $signed(alu_in1) >>> alu_in2[4:0]; - `ALU_OR: alu_result = alu_in1 | alu_in2; - `ALU_AND: alu_result = alu_in2 & alu_in1; - `ALU_SUBU: alu_result = (alu_in1 >= alu_in2) ? 32'h0 : 32'hffffffff; - `ALU_LUI: alu_result = upper_immed_s; - `ALU_AUIPC: alu_result = $signed(curr_PC) + $signed(upper_immed_s); - `ALU_MUL: alu_result = mul_result[31:0]; - `ALU_MULH: alu_result = mul_result[63:32]; - `ALU_MULHSU: alu_result = mul_result[63:32]; - `ALU_MULHU: alu_result = mul_result[63:32]; - `ALU_DIV: alu_result = (alu_in2 == 0) ? 32'hffffffff : div_result_signed; - `ALU_DIVU: alu_result = (alu_in2 == 0) ? 32'hffffffff : div_result_unsigned; - `ALU_REM: alu_result = (alu_in2 == 0) ? alu_in1 : rem_result_signed; - `ALU_REMU: alu_result = (alu_in2 == 0) ? alu_in1 : rem_result_unsigned; - default: alu_result = 32'h0; - endcase + for (genvar i = 0; i < `NUM_THREADS; i++) begin + always @(*) begin + case (alu_op) + `ALU_AND: msc_result[i] = alu_in1[i] & alu_in2_imm[i]; + `ALU_OR: msc_result[i] = alu_in1[i] | alu_in2_imm[i]; + `ALU_XOR: msc_result[i] = alu_in1[i] ^ alu_in2_imm[i]; + //`ALU_SLL, + default: msc_result[i] = alu_in1[i] << alu_in2_imm[i][4:0]; + endcase + end end + + for (genvar i = 0; i < `NUM_THREADS; i++) begin + always @(*) begin + case (alu_op_class) + 0: alu_result[i] = add_result[i]; + 1: alu_result[i] = {31'b0, sub_result[i][32]}; + 2: alu_result[i] = is_sub ? sub_result[i][31:0] : shr_result[i]; + default: alu_result[i] = msc_result[i]; + endcase + end + end + + wire is_jal = is_br_op && (br_op == `BR_JAL || br_op == `BR_JALR); + wire [`NUM_THREADS-1:0][31:0] alu_jal_result = is_jal ? {`NUM_THREADS{alu_req_if.next_PC}} : alu_result; - VX_divide #( - .WIDTHN(32), - .WIDTHD(32), - .NSIGNED(0), - .DSIGNED(0), - .PIPELINE(`DIV_LATENCY) - ) udiv ( - .clk(clk), - .reset(reset), - .numer(alu_in1), - .denom(alu_in2), - .quotient(div_result_unsigned), - .remainder(rem_result_unsigned) + wire [31:0] br_dest = add_result[alu_req_if.tid]; + wire [32:0] cmp_result = sub_result[alu_req_if.tid]; + + wire [32:0] cmp_result_r; + wire is_br_op_r; +`IGNORE_WARNINGS_BEGIN + wire [`BR_BITS-1:0] br_op_r; +`IGNORE_WARNINGS_END + + // output + + wire stall_out = ~alu_commit_if.ready && alu_commit_if.valid; + + VX_generic_register #( + .N(1 + `NW_BITS + `NUM_THREADS + 32 + `NR_BITS + 1 + (`NUM_THREADS * 32) + 1 + `BR_BITS + 32 + 33) + ) alu_reg ( + .clk (clk), + .reset (reset), + .stall (stall_out), + .flush (1'b0), + .in ({alu_req_if.valid, alu_req_if.wid, alu_req_if.tmask, alu_req_if.PC, alu_req_if.rd, alu_req_if.wb, alu_jal_result, is_br_op, br_op, br_dest, cmp_result}), + .out ({alu_commit_if.valid, alu_commit_if.wid, alu_commit_if.tmask, alu_commit_if.PC, alu_commit_if.rd, alu_commit_if.wb, alu_commit_if.data, is_br_op_r, br_op_r, branch_ctl_if.dest, cmp_result_r}) ); + + wire is_less = cmp_result_r[32]; + wire is_equal = ~(| cmp_result_r[31:0]); - VX_divide #( - .WIDTHN(32), - .WIDTHD(32), - .NSIGNED(1), - .DSIGNED(1), - .PIPELINE(`DIV_LATENCY) - ) sdiv ( - .clk(clk), - .reset(reset), - .numer(alu_in1), - .denom(alu_in2), - .quotient(div_result_signed), - .remainder(rem_result_signed) - ); + wire br_neg = `BR_NEG(br_op_r); + wire br_less = `BR_LESS(br_op_r); + wire br_static = `BR_STATIC(br_op_r); + wire br_taken = ((br_less ? is_less : is_equal) ^ br_neg) | br_static; - wire [32:0] mul_dataa = {(alu_op == `ALU_MULHU) ? 1'b0 : alu_in1[31], alu_in1}; - wire [32:0] mul_datab = {(alu_op == `ALU_MULHU || alu_op == `ALU_MULHSU) ? 1'b0 : alu_in2[31], alu_in2}; + assign branch_ctl_if.valid = alu_commit_if.valid && alu_commit_if.ready && is_br_op_r; + assign branch_ctl_if.wid = alu_commit_if.wid; + assign branch_ctl_if.taken = br_taken; - VX_mult #( - .WIDTHA(33), - .WIDTHB(33), - .WIDTHP(64), - .SIGNED(1), - .PIPELINE(`MUL_LATENCY) - ) multiplier ( - .clk(clk), - .reset(reset), - .dataa(mul_dataa), - .datab(mul_datab), - .result(mul_result) - ); + // can accept new request? + assign alu_req_if.ready = ~stall_out; endmodule \ No newline at end of file diff --git a/hw/rtl/VX_back_end.v b/hw/rtl/VX_back_end.v deleted file mode 100644 index 3da014ce..00000000 --- a/hw/rtl/VX_back_end.v +++ /dev/null @@ -1,171 +0,0 @@ -`include "VX_define.vh" - -module VX_back_end #( - parameter CORE_ID = 0 -) ( - `SCOPE_SIGNALS_LSU_IO - `SCOPE_SIGNALS_BE_IO - - input wire clk, - input wire reset, - - VX_csr_io_req_if csr_io_req_if, - VX_csr_io_rsp_if csr_io_rsp_if, - - input wire schedule_delay, - - VX_cache_core_req_if dcache_req_if, - VX_cache_core_rsp_if dcache_rsp_if, - VX_jal_rsp_if jal_rsp_if, - VX_branch_rsp_if branch_rsp_if, - - VX_backend_req_if bckE_req_if, - VX_wb_if writeback_if, - - VX_warp_ctl_if warp_ctl_if, - - output wire mem_delay, - output wire exec_delay, - output wire gpr_stage_delay, - - output wire ebreak -); - - wire no_slot_mem; - wire no_slot_exec; - - - // LSU input + output - VX_lsu_req_if lsu_req_if(); - VX_wb_if mem_wb_if(); - - // Exec unit input + output - VX_exec_unit_req_if exec_unit_req_if(); - VX_wb_if inst_exec_wb_if(); - - // GPU unit input - VX_gpu_inst_req_if gpu_inst_req_if(); - - // CSR unit inputs - VX_csr_req_if csr_req_if(); - VX_wb_if csr_wb_if(); - wire no_slot_csr; - wire stall_gpr_csr; - - VX_gpr_stage gpr_stage ( - .clk (clk), - .reset (reset), - .schedule_delay (schedule_delay), - .writeback_if (writeback_if), - .bckE_req_if (bckE_req_if), - // New - .exec_unit_req_if (exec_unit_req_if), - .lsu_req_if (lsu_req_if), - .gpu_inst_req_if (gpu_inst_req_if), - .csr_req_if (csr_req_if), - .stall_gpr_csr (stall_gpr_csr), - // End new - .memory_delay (mem_delay), - .exec_delay (exec_delay), - .delay (gpr_stage_delay) - ); - - assign ebreak = exec_unit_req_if.is_etype && (| exec_unit_req_if.valid); - - VX_lsu_unit #( - .CORE_ID(CORE_ID) - ) lsu_unit ( - `SCOPE_SIGNALS_LSU_BIND - - .clk (clk), - .reset (reset), - .lsu_req_if (lsu_req_if), - .mem_wb_if (mem_wb_if), - .dcache_req_if (dcache_req_if), - .dcache_rsp_if (dcache_rsp_if), - .delay (mem_delay), - .no_slot_mem (no_slot_mem) - ); - - VX_exec_unit exec_unit ( - .clk (clk), - .reset (reset), - .exec_unit_req_if(exec_unit_req_if), - .inst_exec_wb_if(inst_exec_wb_if), - .jal_rsp_if (jal_rsp_if), - .branch_rsp_if (branch_rsp_if), - .delay (exec_delay), - .no_slot_exec (no_slot_exec) - ); - - VX_gpu_inst gpu_inst ( - .gpu_inst_req_if(gpu_inst_req_if), - .warp_ctl_if (warp_ctl_if) - ); - - VX_csr_req_if issued_csr_req_if(); - - VX_wb_if csr_pipe_rsp_if(); - - VX_csr_arb csr_arb ( - .clk (clk), - .reset (reset), - - .csr_pipe_stall (stall_gpr_csr), - - .csr_core_req_if (csr_req_if), - .csr_io_req_if (csr_io_req_if), - .issued_csr_req_if(issued_csr_req_if), - - .csr_pipe_rsp_if (csr_pipe_rsp_if), - .csr_wb_if (csr_wb_if), - .csr_io_rsp_if (csr_io_rsp_if) - ); - - VX_csr_pipe #( - .CORE_ID(CORE_ID) - ) csr_pipe ( - .clk (clk), - .reset (reset), - .no_slot_csr (no_slot_csr), - .csr_req_if (issued_csr_req_if), - .writeback_if (writeback_if), - .csr_wb_if (csr_pipe_rsp_if), - .stall_gpr_csr (stall_gpr_csr) - ); - - VX_writeback writeback ( - .clk (clk), - .reset (reset), - .mem_wb_if (mem_wb_if), - .inst_exec_wb_if(inst_exec_wb_if), - .csr_wb_if (csr_wb_if), - - .writeback_if (writeback_if), - .no_slot_mem (no_slot_mem), - .no_slot_exec (no_slot_exec), - .no_slot_csr (no_slot_csr) - ); - - `SCOPE_ASSIGN(scope_decode_valid, bckE_req_if.valid); - `SCOPE_ASSIGN(scope_decode_warp_num, bckE_req_if.warp_num); - `SCOPE_ASSIGN(scope_decode_curr_PC, bckE_req_if.curr_PC); - `SCOPE_ASSIGN(scope_decode_is_jal, bckE_req_if.is_jal); - `SCOPE_ASSIGN(scope_decode_rs1, bckE_req_if.rs1); - `SCOPE_ASSIGN(scope_decode_rs2, bckE_req_if.rs2); - - `SCOPE_ASSIGN(scope_execute_valid, exec_unit_req_if.valid); - `SCOPE_ASSIGN(scope_execute_warp_num, exec_unit_req_if.warp_num); - `SCOPE_ASSIGN(scope_execute_curr_PC, exec_unit_req_if.curr_PC); - `SCOPE_ASSIGN(scope_execute_rd, exec_unit_req_if.rd); - `SCOPE_ASSIGN(scope_execute_a, exec_unit_req_if.a_reg_data); - `SCOPE_ASSIGN(scope_execute_b, exec_unit_req_if.b_reg_data); - - `SCOPE_ASSIGN(scope_writeback_valid, writeback_if.valid); - `SCOPE_ASSIGN(scope_writeback_warp_num, writeback_if.warp_num); - `SCOPE_ASSIGN(scope_writeback_curr_PC, writeback_if.curr_PC); - `SCOPE_ASSIGN(scope_writeback_wb, writeback_if.wb); - `SCOPE_ASSIGN(scope_writeback_rd, writeback_if.rd); - `SCOPE_ASSIGN(scope_writeback_data, writeback_if.data); - -endmodule diff --git a/hw/rtl/VX_cluster.v b/hw/rtl/VX_cluster.v index 2633bf7d..2d767cd7 100644 --- a/hw/rtl/VX_cluster.v +++ b/hw/rtl/VX_cluster.v @@ -5,10 +5,9 @@ module VX_cluster #( ) ( `SCOPE_SIGNALS_ISTAGE_IO `SCOPE_SIGNALS_LSU_IO - `SCOPE_SIGNALS_CORE_IO `SCOPE_SIGNALS_CACHE_IO - `SCOPE_SIGNALS_PIPELINE_IO - `SCOPE_SIGNALS_BE_IO + `SCOPE_SIGNALS_ISSUE_IO + `SCOPE_SIGNALS_EXECUTE_IO // Clock input wire clk, @@ -135,18 +134,15 @@ module VX_cluster #( wire [`NUM_CORES-1:0] per_core_busy; wire [`NUM_CORES-1:0] per_core_ebreak; - genvar i; - - for (i = 0; i < `NUM_CORES; i++) begin + for (genvar i = 0; i < `NUM_CORES; i++) begin VX_core #( .CORE_ID(i + (CLUSTER_ID * `NUM_CORES)) ) core ( `SCOPE_SIGNALS_ISTAGE_BIND `SCOPE_SIGNALS_LSU_BIND - `SCOPE_SIGNALS_CORE_BIND `SCOPE_SIGNALS_CACHE_BIND - `SCOPE_SIGNALS_PIPELINE_BIND - `SCOPE_SIGNALS_BE_BIND + `SCOPE_SIGNALS_ISSUE_BIND + `SCOPE_SIGNALS_EXECUTE_BIND .clk (clk), .reset (reset), @@ -316,7 +312,7 @@ module VX_cluster #( wire[`NUM_CORES-1:0][`DSNP_TAG_WIDTH-1:0] l2_snp_fwdin_tag; wire[`NUM_CORES-1:0] l2_snp_fwdin_ready; - for (i = 0; i < `L2NUM_REQUESTS; i = i + 2) begin + for (genvar i = 0; i < `L2NUM_REQUESTS; i = i + 2) begin assign l2_core_req_valid [i] = per_core_D_dram_req_valid[(i/2)]; assign l2_core_req_valid [i+1] = per_core_I_dram_req_valid[(i/2)]; @@ -367,7 +363,6 @@ module VX_cluster #( .NUM_BANKS (`L2NUM_BANKS), .WORD_SIZE (`L2WORD_SIZE), .NUM_REQUESTS (`L2NUM_REQUESTS), - .STAGE_1_CYCLES (`L2STAGE_1_CYCLES), .CREQ_SIZE (`L2CREQ_SIZE), .MRVQ_SIZE (`L2MRVQ_SIZE), .DFPQ_SIZE (`L2DFPQ_SIZE), @@ -472,7 +467,7 @@ module VX_cluster #( wire[`NUM_CORES-1:0][`DSNP_TAG_WIDTH-1:0] arb_snp_fwdin_tag; wire[`NUM_CORES-1:0] arb_snp_fwdin_ready; - for (i = 0; i < `L2NUM_REQUESTS; i = i + 2) begin + for (genvar i = 0; i < `L2NUM_REQUESTS; i = i + 2) begin assign arb_dram_req_valid [i] = per_core_D_dram_req_valid[(i/2)]; assign arb_dram_req_valid [i+1] = per_core_I_dram_req_valid[(i/2)]; diff --git a/hw/rtl/VX_commit.v b/hw/rtl/VX_commit.v new file mode 100644 index 00000000..6735c694 --- /dev/null +++ b/hw/rtl/VX_commit.v @@ -0,0 +1,124 @@ +`include "VX_define.vh" + +module VX_commit #( + parameter CORE_ID = 0 +) ( + input wire clk, + input wire reset, + + // inputs + VX_exu_to_cmt_if alu_commit_if, + VX_exu_to_cmt_if lsu_commit_if, + VX_exu_to_cmt_if mul_commit_if, + VX_exu_to_cmt_if csr_commit_if, + VX_fpu_to_cmt_if fpu_commit_if, + VX_exu_to_cmt_if gpu_commit_if, + + // outputs + VX_writeback_if writeback_if, + VX_cmt_to_csr_if cmt_to_csr_if +); + // CSRs update + + wire [`NUM_EXS-1:0] commited_mask; + assign commited_mask = {alu_commit_if.valid, + lsu_commit_if.valid, + csr_commit_if.valid, + mul_commit_if.valid, + fpu_commit_if.valid, + gpu_commit_if.valid}; + + wire [$clog2(`NUM_EXS+1)-1:0] num_commits; + + VX_countones #( + .N(`NUM_EXS) + ) valids_counter ( + .valids(commited_mask), + .count (num_commits) + ); + + fflags_t fflags; + always @(*) begin + fflags = 0; + for (integer i = 0; i < `NUM_THREADS; i++) begin + if (fpu_commit_if.tmask[i]) begin + fflags.NX |= fpu_commit_if.fflags[i].NX; + fflags.UF |= fpu_commit_if.fflags[i].UF; + fflags.OF |= fpu_commit_if.fflags[i].OF; + fflags.DZ |= fpu_commit_if.fflags[i].DZ; + fflags.NV |= fpu_commit_if.fflags[i].NV; + end + end + end + + fflags_t fflags_r; + reg has_fflags_r; + reg [`NW_BITS-1:0] wid_r; + reg [$clog2(`NUM_EXS+1)-1:0] num_commits_r; + reg csr_update_r; + + always @(posedge clk) begin + csr_update_r <= (| commited_mask); + fflags_r <= fflags; + has_fflags_r <= fpu_commit_if.valid && fpu_commit_if.has_fflags; + wid_r <= fpu_commit_if.wid; + num_commits_r <= (num_commits << $clog2(`NUM_THREADS)); + end + + assign cmt_to_csr_if.valid = csr_update_r; + assign cmt_to_csr_if.wid = wid_r; + assign cmt_to_csr_if.num_commits = num_commits_r; + assign cmt_to_csr_if.has_fflags = has_fflags_r; + assign cmt_to_csr_if.fflags = fflags_r; + + // Writeback + + VX_writeback #( + .CORE_ID(CORE_ID) + ) writeback ( + .clk (clk), + .reset (reset), + + .alu_commit_if (alu_commit_if), + .lsu_commit_if (lsu_commit_if), + .csr_commit_if (csr_commit_if), + .mul_commit_if (mul_commit_if), + .fpu_commit_if (fpu_commit_if), + .gpu_commit_if (gpu_commit_if), + + .writeback_if (writeback_if) + ); + +`ifdef DBG_PRINT_PIPELINE + always @(posedge clk) begin + if (alu_commit_if.valid && alu_commit_if.ready) begin + $display("%t: core%0d-commit: wid=%0d, PC=%0h, ex=ALU, tmask=%b, wb=%0d, rd=%0d, data=%0h", $time, CORE_ID, alu_commit_if.wid, alu_commit_if.PC, alu_commit_if.tmask, alu_commit_if.wb, alu_commit_if.rd, alu_commit_if.data); + end + if (lsu_commit_if.valid && lsu_commit_if.ready) begin + $display("%t: core%0d-commit: wid=%0d, PC=%0h, ex=LSU, tmask=%b, wb=%0d, rd=%0d, data=%0h", $time, CORE_ID, lsu_commit_if.wid, lsu_commit_if.PC, lsu_commit_if.tmask, lsu_commit_if.wb, lsu_commit_if.rd, lsu_commit_if.data); + end + if (csr_commit_if.valid && csr_commit_if.ready) begin + $display("%t: core%0d-commit: wid=%0d, PC=%0h, ex=CSR, tmask=%b, wb=%0d, rd=%0d, data=%0h", $time, CORE_ID, csr_commit_if.wid, csr_commit_if.PC, csr_commit_if.tmask, csr_commit_if.wb, csr_commit_if.rd, csr_commit_if.data); + end + if (mul_commit_if.valid && mul_commit_if.ready) begin + $display("%t: core%0d-commit: wid=%0d, PC=%0h, ex=MUL, tmask=%b, wb=%0d, rd=%0d, data=%0h", $time, CORE_ID, mul_commit_if.wid, mul_commit_if.PC, mul_commit_if.tmask, mul_commit_if.wb, mul_commit_if.rd, mul_commit_if.data); + end + if (fpu_commit_if.valid && fpu_commit_if.ready) begin + $display("%t: core%0d-commit: wid=%0d, PC=%0h, ex=FPU, tmask=%b, wb=%0d, rd=%0d, data=%0h", $time, CORE_ID, fpu_commit_if.wid, fpu_commit_if.PC, fpu_commit_if.tmask, fpu_commit_if.wb, fpu_commit_if.rd, fpu_commit_if.data); + end + if (gpu_commit_if.valid && gpu_commit_if.ready) begin + $display("%t: core%0d-commit: wid=%0d, PC=%0h, ex=GPU, tmask=%b, wb=%0d, rd=%0d, data=%0h", $time, CORE_ID, gpu_commit_if.wid, gpu_commit_if.PC, gpu_commit_if.tmask, gpu_commit_if.wb, gpu_commit_if.rd, gpu_commit_if.data); + end + end +`else + `UNUSED_VAR(fpu_commit_if.PC) +`endif + +endmodule + + + + + + + diff --git a/hw/rtl/VX_config.vh b/hw/rtl/VX_config.vh index 6a5f7386..7e01fe70 100644 --- a/hw/rtl/VX_config.vh +++ b/hw/rtl/VX_config.vh @@ -27,10 +27,6 @@ `define GLOBAL_BLOCK_SIZE 16 `endif -`ifndef NUM_CSRS -`define NUM_CSRS 1024 -`endif - `ifndef STARTUP_ADDR `define STARTUP_ADDR 32'h80000000 `endif @@ -39,10 +35,6 @@ `define SHARED_MEM_BASE_ADDR 32'h6FFFF000 `endif -`ifndef STACK_BASE_ADDR -`define STACK_BASE_ADDR 20'h6FFFF -`endif - `ifndef IO_BUS_BASE_ADDR `define IO_BUS_BASE_ADDR 32'hFFFFFF00 `endif @@ -59,31 +51,121 @@ `define L3_ENABLE (`NUM_CLUSTERS > 1) `endif -// Configuration Values ======================================================= +`ifndef EXT_M_DISABLE +`define EXT_M_ENABLE +`endif +`ifndef EXT_F_DISABLE +`define EXT_F_ENABLE +`endif + +// Device identification `define VENDOR_ID 0 `define ARCHITECTURE_ID 0 `define IMPLEMENTATION_ID 0 -// CSR Addresses ============================================================== +/////////////////////////////////////////////////////////////////////////////// -`define CSR_VEND_ID 12'hF11 -`define CSR_ARCH_ID 12'hF12 -`define CSR_IMPL_ID 12'hF13 -`define CSR_GTID 12'hF14 +`ifndef LATENCY_IMUL +`define LATENCY_IMUL 3 +`endif + +`ifndef LATENCY_FNONCOMP +`define LATENCY_FNONCOMP 1 +`endif + +`ifndef LATENCY_FADDMUL +`define LATENCY_FADDMUL 3 +`endif + +`ifndef LATENCY_FMADD +`define LATENCY_FMADD 4 +`endif + +`ifndef LATENCY_FDIV +`define LATENCY_FDIV 15 +`endif + +`ifndef LATENCY_FSQRT +`define LATENCY_FSQRT 10 +`endif + +`ifndef LATENCY_ITOF +`define LATENCY_ITOF 7 +`endif + +`ifndef LATENCY_FTOI +`define LATENCY_FTOI 3 +`endif + +`ifndef LATENCY_FDIVSQRT +`define LATENCY_FDIVSQRT 10 +`endif + +`ifndef LATENCY_FCONV +`define LATENCY_FCONV 3 +`endif + +// CSR Addresses ////////////////////////////////////////////////////////////// + +`define CSR_FFLAGS 12'h001 +`define CSR_FRM 12'h002 +`define CSR_FCSR 12'h003 `define CSR_LTID 12'h020 `define CSR_LWID 12'h021 +`define CSR_GTID 12'h022 `define CSR_GWID 12'h023 `define CSR_GCID 12'h024 `define CSR_NT 12'h025 `define CSR_NW 12'h026 `define CSR_NC 12'h027 -`define CSR_CYCLE_L 12'hC00 +`define CSR_SATP 12'h180 + +`define CSR_PMPCFG0 12'h3A0 +`define CSR_PMPADDR0 12'h3B0 + +`define CSR_MSTATUS 12'h300 +`define CSR_MISA 12'h301 +`define CSR_MEDELEG 12'h302 +`define CSR_MIDELEG 12'h303 +`define CSR_MIE 12'h304 +`define CSR_MTVEC 12'h305 + +`define CSR_MEPC 12'h341 + +`define CSR_CYCLE 12'hC00 `define CSR_CYCLE_H 12'hC80 -`define CSR_INSTR_L 12'hC02 -`define CSR_INSTR_H 12'hC82 +`define CSR_INSTRET 12'hC02 +`define CSR_INSTRET_H 12'hC82 + +`define CSR_MVENDORID 12'hF11 +`define CSR_MARCHID 12'hF12 +`define CSR_MIMPID 12'hF13 +`define CSR_MHARTID 12'hF14 + +// Pipeline Queues ============================================================ + +// Size of instruction queue +`ifndef IBUF_SIZE +`define IBUF_SIZE 8 +`endif + +// Size of LSU Request Queue +`ifndef LSUQ_SIZE +`define LSUQ_SIZE 8 +`endif + +// Size of MUL Request Queue +`ifndef MULQ_SIZE +`define MULQ_SIZE 8 +`endif + +// Size of FPU Request Queue +`ifndef FPUQ_SIZE +`define FPUQ_SIZE 8 +`endif // Dcache Configurable Knobs ================================================== @@ -107,11 +189,6 @@ `define DWORD_SIZE 4 `endif -// Number of cycles to complete stage 1 (read from memory) -`ifndef DSTAGE_1_CYCLES -`define DSTAGE_1_CYCLES 1 -`endif - // Core Request Queue Size `ifndef DCREQ_SIZE `define DCREQ_SIZE `NUM_WARPS @@ -124,12 +201,12 @@ // Dram Fill Rsp Queue Size `ifndef DDFPQ_SIZE -`define DDFPQ_SIZE 16 +`define DDFPQ_SIZE 8 `endif // Snoop Req Queue Size `ifndef DSNRQ_SIZE -`define DSNRQ_SIZE 16 +`define DSNRQ_SIZE 8 `endif // Core Writeback Queue Size @@ -149,7 +226,7 @@ // Prefetcher `ifndef DPRFQ_SIZE -`define DPRFQ_SIZE 16 +`define DPRFQ_SIZE 8 `endif `ifndef DPRFQ_STRIDE @@ -178,11 +255,6 @@ `define IWORD_SIZE 4 `endif -// Number of cycles to complete stage 1 (read from memory) -`ifndef ISTAGE_1_CYCLES -`define ISTAGE_1_CYCLES 1 -`endif - // Core Request Queue Size `ifndef ICREQ_SIZE `define ICREQ_SIZE `NUM_WARPS @@ -195,7 +267,7 @@ // Dram Fill Rsp Queue Size `ifndef IDFPQ_SIZE -`define IDFPQ_SIZE 16 +`define IDFPQ_SIZE 8 `endif // Core Writeback Queue Size @@ -205,7 +277,7 @@ // Dram Writeback Queue Size `ifndef IDWBQ_SIZE -`define IDWBQ_SIZE 16 +`define IDWBQ_SIZE 8 `endif // Dram Fill Req Queue Size @@ -215,7 +287,7 @@ // Prefetcher `ifndef IPRFQ_SIZE -`define IPRFQ_SIZE 16 +`define IPRFQ_SIZE 8 `endif `ifndef IPRFQ_STRIDE @@ -244,11 +316,6 @@ `define SWORD_SIZE 4 `endif -// Number of cycles to complete stage 1 (read from memory) -`ifndef SSTAGE_1_CYCLES -`define SSTAGE_1_CYCLES 1 -`endif - // Core Request Queue Size `ifndef SCREQ_SIZE `define SCREQ_SIZE `NUM_WARPS @@ -281,14 +348,9 @@ `define L2WORD_SIZE `L2BANK_LINE_SIZE `endif -// Number of cycles to complete stage 1 (read from memory) -`ifndef L2STAGE_1_CYCLES -`define L2STAGE_1_CYCLES 1 -`endif - // Core Request Queue Size `ifndef L2CREQ_SIZE -`define L2CREQ_SIZE 16 +`define L2CREQ_SIZE 8 `endif // Miss Reserv Queue Knob @@ -298,12 +360,12 @@ // Dram Fill Rsp Queue Size `ifndef L2DFPQ_SIZE -`define L2DFPQ_SIZE 16 +`define L2DFPQ_SIZE 8 `endif // Snoop Req Queue Size `ifndef L2SNRQ_SIZE -`define L2SNRQ_SIZE 16 +`define L2SNRQ_SIZE 8 `endif // Core Writeback Queue Size @@ -313,7 +375,7 @@ // Dram Writeback Queue Size `ifndef L2DWBQ_SIZE -`define L2DWBQ_SIZE 16 +`define L2DWBQ_SIZE 8 `endif // Dram Fill Req Queue Size @@ -323,7 +385,7 @@ // Prefetcher `ifndef L2PRFQ_SIZE -`define L2PRFQ_SIZE 16 +`define L2PRFQ_SIZE 8 `endif `ifndef L2PRFQ_STRIDE @@ -352,14 +414,9 @@ `define L3WORD_SIZE `L3BANK_LINE_SIZE `endif -// Number of cycles to complete stage 1 (read from memory) -`ifndef L3STAGE_1_CYCLES -`define L3STAGE_1_CYCLES 1 -`endif - // Core Request Queue Size `ifndef L3CREQ_SIZE -`define L3CREQ_SIZE 16 +`define L3CREQ_SIZE 8 `endif // Miss Reserv Queue Knob @@ -369,12 +426,12 @@ // Dram Fill Rsp Queue Size `ifndef L3DFPQ_SIZE -`define L3DFPQ_SIZE 16 +`define L3DFPQ_SIZE 8 `endif // Snoop Req Queue Size `ifndef L3SNRQ_SIZE -`define L3SNRQ_SIZE 16 +`define L3SNRQ_SIZE 8 `endif // Core Writeback Queue Size @@ -384,7 +441,7 @@ // Dram Writeback Queue Size `ifndef L3DWBQ_SIZE -`define L3DWBQ_SIZE 16 +`define L3DWBQ_SIZE 8 `endif // Dram Fill Req Queue Size @@ -394,12 +451,11 @@ // Prefetcher `ifndef L3PRFQ_SIZE -`define L3PRFQ_SIZE 16 +`define L3PRFQ_SIZE 8 `endif `ifndef L3PRFQ_STRIDE `define L3PRFQ_STRIDE 0 `endif - // VX_CONFIG `endif diff --git a/hw/rtl/VX_core.v b/hw/rtl/VX_core.v index c437c398..a72833f2 100644 --- a/hw/rtl/VX_core.v +++ b/hw/rtl/VX_core.v @@ -5,10 +5,9 @@ module VX_core #( ) ( `SCOPE_SIGNALS_ISTAGE_IO `SCOPE_SIGNALS_LSU_IO - `SCOPE_SIGNALS_CORE_IO `SCOPE_SIGNALS_CACHE_IO - `SCOPE_SIGNALS_PIPELINE_IO - `SCOPE_SIGNALS_BE_IO + `SCOPE_SIGNALS_ISSUE_IO + `SCOPE_SIGNALS_EXECUTE_IO // Clock input wire clk, @@ -166,15 +165,15 @@ module VX_core #( VX_cache_core_req_if #( .NUM_REQUESTS(`INUM_REQUESTS), .WORD_SIZE(`IWORD_SIZE), - .CORE_TAG_WIDTH(`DCORE_TAG_WIDTH), - .CORE_TAG_ID_BITS(`DCORE_TAG_ID_BITS) + .CORE_TAG_WIDTH(`ICORE_TAG_WIDTH), + .CORE_TAG_ID_BITS(`ICORE_TAG_ID_BITS) ) core_icache_req_if(); VX_cache_core_rsp_if #( .NUM_REQUESTS(`INUM_REQUESTS), .WORD_SIZE(`IWORD_SIZE), - .CORE_TAG_WIDTH(`DCORE_TAG_WIDTH), - .CORE_TAG_ID_BITS(`DCORE_TAG_ID_BITS) + .CORE_TAG_WIDTH(`ICORE_TAG_WIDTH), + .CORE_TAG_ID_BITS(`ICORE_TAG_ID_BITS) ) core_icache_rsp_if(); VX_pipeline #( @@ -182,8 +181,8 @@ module VX_core #( ) pipeline ( `SCOPE_SIGNALS_ISTAGE_BIND `SCOPE_SIGNALS_LSU_BIND - `SCOPE_SIGNALS_PIPELINE_BIND - `SCOPE_SIGNALS_BE_BIND + `SCOPE_SIGNALS_ISSUE_BIND + `SCOPE_SIGNALS_EXECUTE_BIND .clk(clk), .reset(reset), @@ -250,7 +249,7 @@ module VX_core #( assign dcache_snp_req_if.addr = snp_req_addr; assign dcache_snp_req_if.invalidate = snp_req_invalidate; assign dcache_snp_req_if.tag = snp_req_tag; - assign snp_req_ready = dcache_snp_req_if.ready; + assign snp_req_ready = dcache_snp_req_if.ready; assign snp_rsp_valid = dcache_snp_rsp_if.valid; assign snp_rsp_tag = dcache_snp_rsp_if.tag; @@ -283,18 +282,20 @@ module VX_core #( .icache_dram_rsp_if (icache_dram_rsp_if) ); - // select io address + // select io bus wire is_io_addr = ({core_dcache_req_if.addr[0], 2'b0} >= `IO_BUS_BASE_ADDR); - wire io_select = (| core_dcache_req_if.valid) ? is_io_addr : 0; + wire io_req_select = (| core_dcache_req_if.valid) ? is_io_addr : 0; + wire io_rsp_select = (| arb_io_rsp_if.valid); - VX_dcache_arb dcache_io_arb ( - .req_select (io_select), - .in_core_req_if (core_dcache_req_if), - .out0_core_req_if (arb_dcache_req_if), - .out1_core_req_if (arb_io_req_if), - .in0_core_rsp_if (arb_dcache_rsp_if), - .in1_core_rsp_if (arb_io_rsp_if), - .out_core_rsp_if (core_dcache_rsp_if) + VX_dcache_arb dcache_io_arb ( + .core_req_in_if (core_dcache_req_if), + .core_req_out0_if (arb_dcache_req_if), + .core_req_out1_if (arb_io_req_if), + .core_rsp_in0_if (arb_dcache_rsp_if), + .core_rsp_in1_if (arb_io_rsp_if), + .core_rsp_out_if (core_dcache_rsp_if), + .select_req (io_req_select), + .select_rsp (io_rsp_select) ); endmodule diff --git a/hw/rtl/VX_csr_arb.v b/hw/rtl/VX_csr_arb.v index 58327ee3..c059113e 100644 --- a/hw/rtl/VX_csr_arb.v +++ b/hw/rtl/VX_csr_arb.v @@ -1,51 +1,50 @@ `include "VX_define.vh" -module VX_csr_arb ( - input wire clk, - input wire reset, - - input wire csr_pipe_stall, - +module VX_csr_arb ( + // inputs VX_csr_req_if csr_core_req_if, VX_csr_io_req_if csr_io_req_if, - VX_csr_req_if issued_csr_req_if, - VX_wb_if csr_pipe_rsp_if, - VX_wb_if csr_wb_if, - VX_csr_io_rsp_if csr_io_rsp_if + // output + VX_csr_req_if csr_req_if, + + // input + VX_exu_to_cmt_if csr_rsp_if, + + // outputs + VX_exu_to_cmt_if csr_commit_if, + VX_csr_io_rsp_if csr_io_rsp_if, + + input wire select_io_req, + input wire select_io_rsp ); + // requests + assign csr_req_if.valid = (~select_io_req) ? csr_core_req_if.valid : csr_io_req_if.valid; + assign csr_req_if.wid = (~select_io_req) ? csr_core_req_if.wid : 0; + assign csr_req_if.tmask = (~select_io_req) ? csr_core_req_if.tmask : 0; + assign csr_req_if.PC = (~select_io_req) ? csr_core_req_if.PC : 0; + assign csr_req_if.op_type = (~select_io_req) ? csr_core_req_if.op_type : (csr_io_req_if.rw ? `CSR_RW : `CSR_RS); + assign csr_req_if.csr_addr = (~select_io_req) ? csr_core_req_if.csr_addr : csr_io_req_if.addr; + assign csr_req_if.csr_mask = (~select_io_req) ? csr_core_req_if.csr_mask : (csr_io_req_if.rw ? csr_io_req_if.data : 32'b0); + assign csr_req_if.rd = (~select_io_req) ? csr_core_req_if.rd : 0; + assign csr_req_if.wb = (~select_io_req) ? csr_core_req_if.wb : 0; + assign csr_req_if.is_io = select_io_req; - `UNUSED_VAR (clk) - `UNUSED_VAR (reset) - - wire pick_core = (| csr_core_req_if.valid); - - // Mux between core and io - assign issued_csr_req_if.valid = pick_core ? csr_core_req_if.valid : {`NUM_THREADS{csr_io_req_if.valid}}; - assign issued_csr_req_if.is_csr = pick_core ? csr_core_req_if.is_csr : 1'b1; - assign issued_csr_req_if.alu_op = pick_core ? csr_core_req_if.alu_op : (csr_io_req_if.rw ? `ALU_CSR_RW : `ALU_CSR_RS); - assign issued_csr_req_if.csr_addr = pick_core ? csr_core_req_if.csr_addr : csr_io_req_if.addr; - assign issued_csr_req_if.csr_immed = pick_core ? csr_core_req_if.csr_immed : 0; - assign issued_csr_req_if.csr_mask = pick_core ? csr_core_req_if.csr_mask : (csr_io_req_if.rw ? csr_io_req_if.data : 32'b0); - assign issued_csr_req_if.is_io = !pick_core; - assign issued_csr_req_if.warp_num = csr_core_req_if.warp_num; - assign issued_csr_req_if.rd = csr_core_req_if.rd; - assign issued_csr_req_if.wb = csr_core_req_if.wb; - - assign csr_io_req_if.ready = !(csr_pipe_stall || pick_core); - - // Core Writeback - assign csr_wb_if.valid = csr_pipe_rsp_if.valid & {`NUM_THREADS{~csr_pipe_rsp_if.is_io}}; - assign csr_wb_if.data = csr_pipe_rsp_if.data; - assign csr_wb_if.warp_num = csr_pipe_rsp_if.warp_num; - assign csr_wb_if.rd = csr_pipe_rsp_if.rd; - assign csr_wb_if.wb = csr_pipe_rsp_if.wb; - assign csr_wb_if.curr_PC = csr_pipe_rsp_if.curr_PC; + assign csr_core_req_if.ready = csr_req_if.ready && (~select_io_req); + assign csr_io_req_if.ready = csr_req_if.ready && select_io_req; - // CSR I/O response - assign csr_io_rsp_if.valid = csr_pipe_rsp_if.valid[0] & csr_pipe_rsp_if.is_io; - assign csr_io_rsp_if.data = csr_pipe_rsp_if.data[0]; - wire x = csr_io_rsp_if.ready; - `UNUSED_VAR(x) + // responses + assign csr_io_rsp_if.valid = csr_rsp_if.valid & select_io_rsp; + assign csr_io_rsp_if.data = csr_rsp_if.data[0]; + + assign csr_commit_if.valid = csr_rsp_if.valid & ~select_io_rsp; + assign csr_commit_if.wid = csr_rsp_if.wid; + assign csr_commit_if.tmask = csr_rsp_if.tmask; + assign csr_commit_if.PC = csr_rsp_if.PC; + assign csr_commit_if.rd = csr_rsp_if.rd; + assign csr_commit_if.wb = csr_rsp_if.wb; + assign csr_commit_if.data = csr_rsp_if.data; + + assign csr_rsp_if.ready = select_io_rsp ? csr_io_rsp_if.ready : csr_commit_if.ready; endmodule diff --git a/hw/rtl/VX_csr_data.v b/hw/rtl/VX_csr_data.v index 7488129e..5ee0831e 100644 --- a/hw/rtl/VX_csr_data.v +++ b/hw/rtl/VX_csr_data.v @@ -3,62 +3,143 @@ module VX_csr_data #( parameter CORE_ID = 0 ) ( - input wire clk, // Clock + input wire clk, input wire reset, - input wire[`CSR_ADDR_SIZE-1:0] read_addr, - output reg[31:0] read_data, - input wire write_enable, -`IGNORE_WARNINGS_BEGIN - // We use a smaller storage for CSRs than the standard 4KB in RISC-V - input wire[`CSR_ADDR_SIZE-1:0] write_addr, -`IGNORE_WARNINGS_END - input wire[`CSR_WIDTH-1:0] write_data, - input wire[`NW_BITS-1:0] warp_num, - input wire wb_valid + VX_cmt_to_csr_if cmt_to_csr_if, + VX_csr_to_issue_if csr_to_issue_if, + + input wire read_enable, + input wire[`CSR_ADDR_BITS-1:0] read_addr, + input wire[`NW_BITS-1:0] read_wid, + output wire[31:0] read_data, + + input wire write_enable, + input wire[`CSR_ADDR_BITS-1:0] write_addr, + input wire[`NW_BITS-1:0] write_wid, + input wire[`CSR_WIDTH-1:0] write_data ); - reg [`CSR_WIDTH-1:0] csr_table[`NUM_CSRS-1:0]; + reg [`CSR_WIDTH-1:0] csr_satp; + reg [`CSR_WIDTH-1:0] csr_mstatus; + reg [`CSR_WIDTH-1:0] csr_medeleg; + reg [`CSR_WIDTH-1:0] csr_mideleg; + reg [`CSR_WIDTH-1:0] csr_mie; + reg [`CSR_WIDTH-1:0] csr_mtvec; + reg [`CSR_WIDTH-1:0] csr_mepc; + reg [`CSR_WIDTH-1:0] csr_pmpcfg [0:0]; + reg [`CSR_WIDTH-1:0] csr_pmpaddr [0:0]; + reg [63:0] csr_cycle; + reg [63:0] csr_instret; + + reg [`FFG_BITS-1:0] csr_fflags [`NUM_WARPS-1:0]; + reg [`FRM_BITS-1:0] csr_frm [`NUM_WARPS-1:0]; + reg [`FRM_BITS+`FFG_BITS-1:0] csr_fcsr [`NUM_WARPS-1:0]; // fflags + frm - reg [63:0] num_cycles, num_instrs; + reg [31:0] read_data_r; - // cast address to physical CSR range - wire [$clog2(`NUM_CSRS)-1:0] rd_addr, wr_addr; - assign rd_addr = $size(rd_addr)'(read_addr); - assign wr_addr = $size(wr_addr)'(write_addr); + always @(posedge clk) begin + if (cmt_to_csr_if.has_fflags) begin + csr_fflags[cmt_to_csr_if.wid] <= cmt_to_csr_if.fflags; + csr_fcsr[cmt_to_csr_if.wid][`FFG_BITS-1:0] <= cmt_to_csr_if.fflags; + end + + if (write_enable) begin + case (write_addr) + `CSR_FFLAGS: begin + csr_fcsr[write_wid][`FFG_BITS-1:0] <= write_data[`FFG_BITS-1:0]; + csr_fflags[write_wid] <= write_data[`FFG_BITS-1:0]; + end + + `CSR_FRM: begin + csr_fcsr[write_wid][`FFG_BITS+`FRM_BITS-1:`FFG_BITS] <= write_data[`FRM_BITS-1:0]; + csr_frm[write_wid] <= write_data[`FRM_BITS-1:0]; + end + + `CSR_FCSR: begin + csr_fcsr[write_wid] <= write_data[`FFG_BITS+`FRM_BITS-1:0]; + csr_frm[write_wid] <= write_data[`FFG_BITS+`FRM_BITS-1:`FFG_BITS]; + csr_fflags[write_wid] <= write_data[`FFG_BITS-1:0]; + end + + `CSR_SATP: csr_satp <= write_data; + + `CSR_MSTATUS: csr_mstatus <= write_data; + `CSR_MEDELEG: csr_medeleg <= write_data; + `CSR_MIDELEG: csr_mideleg <= write_data; + `CSR_MIE: csr_mie <= write_data; + `CSR_MTVEC: csr_mtvec <= write_data; + + `CSR_MEPC: csr_mepc <= write_data; + + `CSR_PMPCFG0: csr_pmpcfg[0] <= write_data; + `CSR_PMPADDR0: csr_pmpaddr[0] <= write_data; + + default: begin + assert(~write_enable) else $error("%t: invalid CSR write address: %0h", $time, write_addr); + end + endcase + end + end always @(posedge clk) begin if (reset) begin - num_cycles <= 0; - num_instrs <= 0; + csr_cycle <= 0; + csr_instret <= 0; end else begin - if (write_enable) begin - csr_table[wr_addr] <= write_data; - end - num_cycles <= num_cycles + 1; - if (wb_valid) begin - num_instrs <= num_instrs + 1; + csr_cycle <= csr_cycle + 1; + if (cmt_to_csr_if.valid) begin + csr_instret <= csr_instret + 64'(cmt_to_csr_if.num_commits); end end end always @(*) begin + read_data_r = 'x; case (read_addr) - `CSR_LWID : read_data = 32'(warp_num); - `CSR_GTID , - `CSR_GWID : read_data = CORE_ID * `NUM_WARPS + 32'(warp_num); - `CSR_GCID : read_data = CORE_ID; - `CSR_NT : read_data = `NUM_THREADS; - `CSR_NW : read_data = `NUM_WARPS; - `CSR_NC : read_data = `NUM_CORES * `NUM_CLUSTERS; - `CSR_CYCLE_L : read_data = num_cycles[31:0]; - `CSR_CYCLE_H : read_data = num_cycles[63:32]; - `CSR_INSTR_L : read_data = num_instrs[31:0]; - `CSR_INSTR_H : read_data = num_instrs[63:32]; - `CSR_VEND_ID : read_data = `VENDOR_ID; - `CSR_ARCH_ID : read_data = `ARCHITECTURE_ID; - `CSR_IMPL_ID : read_data = `IMPLEMENTATION_ID; - default : read_data = 32'(csr_table[rd_addr]); - endcase - end + `CSR_FFLAGS : read_data_r = 32'(csr_fflags[read_wid]); + `CSR_FRM : read_data_r = 32'(csr_frm[read_wid]); + `CSR_FCSR : read_data_r = 32'(csr_fcsr[read_wid]); -endmodule + `CSR_LWID : read_data_r = 32'(read_wid); + `CSR_LTID , + `CSR_GTID , + `CSR_MHARTID , + `CSR_GWID : read_data_r = CORE_ID * `NUM_WARPS + 32'(read_wid); + `CSR_GCID : read_data_r = CORE_ID; + `CSR_NT : read_data_r = `NUM_THREADS; + `CSR_NW : read_data_r = `NUM_WARPS; + `CSR_NC : read_data_r = `NUM_CORES * `NUM_CLUSTERS; + + `CSR_SATP : read_data_r = 32'(csr_satp); + + `CSR_MSTATUS : read_data_r = 32'(csr_mstatus); + `CSR_MISA : read_data_r = `ISA_CODE; + `CSR_MEDELEG : read_data_r = 32'(csr_medeleg); + `CSR_MIDELEG : read_data_r = 32'(csr_mideleg); + `CSR_MIE : read_data_r = 32'(csr_mie); + `CSR_MTVEC : read_data_r = 32'(csr_mtvec); + + `CSR_MEPC : read_data_r = 32'(csr_mepc); + + `CSR_PMPCFG0 : read_data_r = 32'(csr_pmpcfg[0]); + `CSR_PMPADDR0: read_data_r = 32'(csr_pmpaddr[0]); + + `CSR_CYCLE : read_data_r = csr_cycle[31:0]; + `CSR_CYCLE_H : read_data_r = csr_cycle[63:32]; + `CSR_INSTRET : read_data_r = csr_instret[31:0]; + `CSR_INSTRET_H:read_data_r = csr_instret[63:32]; + + `CSR_MVENDORID:read_data_r = `VENDOR_ID; + `CSR_MARCHID : read_data_r = `ARCHITECTURE_ID; + `CSR_MIMPID : read_data_r = `IMPLEMENTATION_ID; + + default: begin + assert(~read_enable) else $error("%t: invalid CSR read address: %0h", $time, read_addr); + end + endcase + end + + assign read_data = read_data_r; + assign csr_to_issue_if.frm = csr_frm[csr_to_issue_if.wid]; + +endmodule \ No newline at end of file diff --git a/hw/rtl/VX_csr_io_arb.v b/hw/rtl/VX_csr_io_arb.v index bf0d7041..04097c55 100644 --- a/hw/rtl/VX_csr_io_arb.v +++ b/hw/rtl/VX_csr_io_arb.v @@ -2,7 +2,7 @@ module VX_csr_io_arb #( parameter NUM_REQUESTS = 1, - parameter REQS_BITS = `CLOG2(NUM_REQUESTS) + parameter REQS_BITS = `LOG2UP(NUM_REQUESTS) ) ( input wire clk, input wire reset, @@ -37,6 +37,7 @@ module VX_csr_io_arb #( `UNUSED_VAR (clk) `UNUSED_VAR (reset) + `UNUSED_VAR (request_id) assign out_csr_io_req_valid = in_csr_io_req_valid; assign out_csr_io_req_rw = in_csr_io_req_rw; @@ -50,9 +51,7 @@ module VX_csr_io_arb #( end else begin - genvar i; - - for (i = 0; i < NUM_REQUESTS; i++) begin + for (genvar i = 0; i < NUM_REQUESTS; i++) begin assign out_csr_io_req_valid[i] = in_csr_io_req_valid && (request_id == `REQS_BITS'(i)); assign out_csr_io_req_rw[i] = in_csr_io_req_rw; assign out_csr_io_req_addr[i] = in_csr_io_req_addr; @@ -77,7 +76,7 @@ module VX_csr_io_arb #( assign out_csr_io_rsp_valid = in_csr_io_rsp_valid [bus_rsp_sel]; assign out_csr_io_rsp_data = in_csr_io_rsp_data [bus_rsp_sel]; - for (i = 0; i < NUM_REQUESTS; i++) begin + for (genvar i = 0; i < NUM_REQUESTS; i++) begin assign in_csr_io_rsp_ready[i] = out_csr_io_rsp_ready && (bus_rsp_sel == `REQS_BITS'(i)); end diff --git a/hw/rtl/VX_csr_pipe.v b/hw/rtl/VX_csr_pipe.v deleted file mode 100644 index aa6980ab..00000000 --- a/hw/rtl/VX_csr_pipe.v +++ /dev/null @@ -1,81 +0,0 @@ -`include "VX_define.vh" - -module VX_csr_pipe #( - parameter CORE_ID = 0 -) ( - input wire clk, - input wire reset, - input wire no_slot_csr, - VX_csr_req_if csr_req_if, - VX_wb_if writeback_if, - VX_wb_if csr_wb_if, - output wire stall_gpr_csr -); - - wire[`NUM_THREADS-1:0] valid_s2; - wire[`NW_BITS-1:0] warp_num_s2; - wire[4:0] rd_s2; - wire[1:0] wb_s2; - wire is_csr_s2; - wire[`CSR_ADDR_SIZE-1:0] csr_addr_s2; - wire[31:0] csr_read_data_s2; - wire[31:0] csr_updated_data_s2; - - wire[31:0] csr_read_data_unqual; - wire[31:0] csr_read_data; - - VX_csr_data #( - .CORE_ID(CORE_ID) - ) csr_data ( - .clk (clk), - .reset (reset), - .read_addr (csr_req_if.csr_addr), - .read_data (csr_read_data_unqual), - .write_enable (is_csr_s2), - .write_data (csr_updated_data_s2[`CSR_WIDTH-1:0]), - .write_addr (csr_addr_s2), - .warp_num (csr_req_if.warp_num), - .wb_valid (| writeback_if.valid) - ); - - wire car_hazard = (csr_addr_s2 == csr_req_if.csr_addr) & (warp_num_s2 == csr_req_if.warp_num) & |(valid_s2) & is_csr_s2; - - assign csr_read_data = car_hazard ? csr_updated_data_s2 : csr_read_data_unqual; - - reg [31:0] csr_updated_data; - - always @(*) begin - case (csr_req_if.alu_op) - `ALU_CSR_RW: csr_updated_data = csr_req_if.csr_mask; - `ALU_CSR_RS: csr_updated_data = csr_read_data | csr_req_if.csr_mask; - `ALU_CSR_RC: csr_updated_data = csr_read_data & (32'hFFFFFFFF - csr_req_if.csr_mask); - default: csr_updated_data = 32'hdeadbeef; - endcase - end - - VX_generic_register #( - .N(32 + 32 + 12 + 1 + 1 + 2 + 5 + (`NW_BITS-1+1) + `NUM_THREADS) - ) csr_reg_s2 ( - .clk (clk), - .reset(reset), - .stall(no_slot_csr), - .flush(1'b0), - .in ({csr_req_if.valid, csr_req_if.warp_num, csr_req_if.rd, csr_req_if.wb, csr_req_if.is_csr, csr_req_if.csr_addr, csr_req_if.is_io, csr_read_data , csr_updated_data }), - .out ({valid_s2 , warp_num_s2 , rd_s2 , wb_s2 , is_csr_s2 , csr_addr_s2 , csr_wb_if.is_io , csr_read_data_s2, csr_updated_data_s2}) - ); - - assign csr_wb_if.valid = valid_s2; - assign csr_wb_if.warp_num = warp_num_s2; - assign csr_wb_if.rd = rd_s2; - assign csr_wb_if.wb = wb_s2; - - genvar i; - for (i = 0; i < `NUM_THREADS; i++) begin - assign csr_wb_if.data[i] = (csr_addr_s2 == `CSR_LTID) ? i : - (csr_addr_s2 == `CSR_GTID) ? (csr_read_data_s2 * `NUM_THREADS + i) : - csr_read_data_s2; - end - - assign stall_gpr_csr = no_slot_csr && csr_req_if.is_csr && (| csr_req_if.valid); - -endmodule diff --git a/hw/rtl/VX_csr_unit.v b/hw/rtl/VX_csr_unit.v new file mode 100644 index 00000000..f299bb0c --- /dev/null +++ b/hw/rtl/VX_csr_unit.v @@ -0,0 +1,112 @@ +`include "VX_define.vh" + +module VX_csr_unit #( + parameter CORE_ID = 0 +) ( + input wire clk, + input wire reset, + + VX_cmt_to_csr_if cmt_to_csr_if, + VX_csr_to_issue_if csr_to_issue_if, + + VX_csr_io_req_if csr_io_req_if, + VX_csr_io_rsp_if csr_io_rsp_if, + + VX_csr_req_if csr_req_if, + VX_exu_to_cmt_if csr_commit_if +); + VX_csr_req_if csr_pipe_req_if(); + VX_exu_to_cmt_if csr_pipe_rsp_if(); + + wire select_io_req = csr_io_req_if.valid; + wire select_io_rsp; + + VX_csr_arb csr_arb ( + .csr_core_req_if (csr_req_if), + .csr_io_req_if (csr_io_req_if), + .csr_req_if (csr_pipe_req_if), + + .csr_rsp_if (csr_pipe_rsp_if), + .csr_io_rsp_if (csr_io_rsp_if), + .csr_commit_if (csr_commit_if), + + .select_io_req (select_io_req), + .select_io_rsp (select_io_rsp) + ); + + wire csr_we_s1; + wire [`CSR_ADDR_BITS-1:0] csr_addr_s1; + wire [31:0] csr_read_data, csr_read_data_s1; + wire [31:0] csr_updated_data_s1; + + VX_csr_data #( + .CORE_ID(CORE_ID) + ) csr_data ( + .clk (clk), + .reset (reset), + .cmt_to_csr_if (cmt_to_csr_if), + .csr_to_issue_if(csr_to_issue_if), + .read_enable (csr_pipe_req_if.valid), + .read_addr (csr_pipe_req_if.csr_addr), + .read_wid (csr_pipe_req_if.wid), + .read_data (csr_read_data), + .write_enable (csr_we_s1), + .write_addr (csr_addr_s1), + .write_wid (csr_pipe_rsp_if.wid), + .write_data (csr_updated_data_s1[`CSR_WIDTH-1:0]) + ); + + wire csr_hazard = (csr_addr_s1 == csr_pipe_req_if.csr_addr) + && (csr_pipe_rsp_if.wid == csr_pipe_req_if.wid) + && csr_pipe_rsp_if.valid; + + wire [31:0] csr_read_data_qual = csr_hazard ? csr_updated_data_s1 : csr_read_data; + + reg [31:0] csr_updated_data; + + reg csr_we_s0_unqual; + + always @(*) begin + csr_we_s0_unqual = 0; + case (csr_pipe_req_if.op_type) + `CSR_RW: begin + csr_updated_data = csr_pipe_req_if.csr_mask; + csr_we_s0_unqual = 1; + end + `CSR_RS: begin + csr_updated_data = csr_read_data_qual | csr_pipe_req_if.csr_mask; + csr_we_s0_unqual = (csr_pipe_req_if.csr_mask != 0); + end + `CSR_RC: begin + csr_updated_data = csr_read_data_qual & (32'hFFFFFFFF - csr_pipe_req_if.csr_mask); + csr_we_s0_unqual = (csr_pipe_req_if.csr_mask != 0); + end + default: csr_updated_data = 32'hdeadbeef; + endcase + end + + wire csr_we_s0 = csr_we_s0_unqual && csr_pipe_req_if.valid; + + wire stall = ~csr_pipe_rsp_if.ready && csr_pipe_rsp_if.valid; + + VX_generic_register #( + .N(1 + `NW_BITS + `NUM_THREADS + 32 + `NR_BITS + 1 + 1 + `CSR_ADDR_BITS + 1 + 32 + 32) + ) csr_reg ( + .clk (clk), + .reset (reset), + .stall (stall), + .flush (1'b0), + .in ({csr_pipe_req_if.valid, csr_pipe_req_if.wid, csr_pipe_req_if.tmask, csr_pipe_req_if.PC, csr_pipe_req_if.rd, csr_pipe_req_if.wb, csr_we_s0, csr_pipe_req_if.csr_addr, csr_pipe_req_if.is_io, csr_read_data_qual, csr_updated_data}), + .out ({csr_pipe_rsp_if.valid, csr_pipe_rsp_if.wid, csr_pipe_rsp_if.tmask, csr_pipe_rsp_if.PC, csr_pipe_rsp_if.rd, csr_pipe_rsp_if.wb, csr_we_s1, csr_addr_s1, select_io_rsp, csr_read_data_s1, csr_updated_data_s1}) + ); + + for (genvar i = 0; i < `NUM_THREADS; i++) begin + assign csr_pipe_rsp_if.data[i] = (csr_addr_s1 == `CSR_LTID) ? i : + (csr_addr_s1 == `CSR_GTID) ? (csr_read_data_s1 * `NUM_THREADS + i) : + csr_read_data_s1; + end + + // can accept new request? + assign csr_pipe_req_if.ready = ~stall; + +endmodule diff --git a/hw/rtl/VX_dcache_arb.v b/hw/rtl/VX_dcache_arb.v index 1431be60..4d493c60 100644 --- a/hw/rtl/VX_dcache_arb.v +++ b/hw/rtl/VX_dcache_arb.v @@ -1,48 +1,50 @@ `include "VX_define.vh" module VX_dcache_arb ( - input wire req_select, - // input request - VX_cache_core_req_if in_core_req_if, + VX_cache_core_req_if core_req_in_if, // output 0 request - VX_cache_core_req_if out0_core_req_if, + VX_cache_core_req_if core_req_out0_if, // output 1 request - VX_cache_core_req_if out1_core_req_if, + VX_cache_core_req_if core_req_out1_if, // input 0 response - VX_cache_core_rsp_if in0_core_rsp_if, + VX_cache_core_rsp_if core_rsp_in0_if, // input 1 response - VX_cache_core_rsp_if in1_core_rsp_if, + VX_cache_core_rsp_if core_rsp_in1_if, // output response - VX_cache_core_rsp_if out_core_rsp_if + VX_cache_core_rsp_if core_rsp_out_if, + + // bus select + input wire select_req, + input wire select_rsp ); - assign out0_core_req_if.valid = in_core_req_if.valid & {`NUM_THREADS{~req_select}}; - assign out0_core_req_if.rw = in_core_req_if.rw; - assign out0_core_req_if.byteen = in_core_req_if.byteen; - assign out0_core_req_if.addr = in_core_req_if.addr; - assign out0_core_req_if.data = in_core_req_if.data; - assign out0_core_req_if.tag = in_core_req_if.tag; + // select request + assign core_req_out0_if.valid = core_req_in_if.valid & {`NUM_THREADS{~select_req}}; + assign core_req_out0_if.rw = core_req_in_if.rw; + assign core_req_out0_if.byteen = core_req_in_if.byteen; + assign core_req_out0_if.addr = core_req_in_if.addr; + assign core_req_out0_if.data = core_req_in_if.data; + assign core_req_out0_if.tag = core_req_in_if.tag; - assign out1_core_req_if.valid = in_core_req_if.valid & {`NUM_THREADS{req_select}}; - assign out1_core_req_if.rw = in_core_req_if.rw; - assign out1_core_req_if.byteen = in_core_req_if.byteen; - assign out1_core_req_if.addr = in_core_req_if.addr; - assign out1_core_req_if.data = in_core_req_if.data; - assign out1_core_req_if.tag = in_core_req_if.tag; + assign core_req_out1_if.valid = core_req_in_if.valid & {`NUM_THREADS{select_req}}; + assign core_req_out1_if.rw = core_req_in_if.rw; + assign core_req_out1_if.byteen = core_req_in_if.byteen; + assign core_req_out1_if.addr = core_req_in_if.addr; + assign core_req_out1_if.data = core_req_in_if.data; + assign core_req_out1_if.tag = core_req_in_if.tag; - assign in_core_req_if.ready = req_select ? out1_core_req_if.ready : out0_core_req_if.ready; + assign core_req_in_if.ready = select_req ? core_req_out1_if.ready : core_req_out0_if.ready; - wire rsp_select0 = (| in0_core_rsp_if.valid); - - assign out_core_rsp_if.valid = rsp_select0 ? in0_core_rsp_if.valid : in1_core_rsp_if.valid; - assign out_core_rsp_if.data = rsp_select0 ? in0_core_rsp_if.data : in1_core_rsp_if.data; - assign out_core_rsp_if.tag = rsp_select0 ? in0_core_rsp_if.tag : in1_core_rsp_if.tag; - assign in0_core_rsp_if.ready = out_core_rsp_if.ready && rsp_select0; - assign in1_core_rsp_if.ready = out_core_rsp_if.ready && !rsp_select0; + // select response + assign core_rsp_out_if.valid = select_rsp ? core_rsp_in1_if.valid : core_rsp_in0_if.valid; + assign core_rsp_out_if.data = select_rsp ? core_rsp_in1_if.data : core_rsp_in0_if.data; + assign core_rsp_out_if.tag = select_rsp ? core_rsp_in1_if.tag : core_rsp_in0_if.tag; + assign core_rsp_in0_if.ready = core_rsp_out_if.ready && ~select_rsp; + assign core_rsp_in1_if.ready = core_rsp_out_if.ready && select_rsp; endmodule \ No newline at end of file diff --git a/hw/rtl/VX_decode.v b/hw/rtl/VX_decode.v index deb3f44b..17c3d7dd 100644 --- a/hw/rtl/VX_decode.v +++ b/hw/rtl/VX_decode.v @@ -1,321 +1,401 @@ - `include "VX_define.vh" +`include "VX_print_instr.vh" -module VX_decode( - // Fetch Inputs - VX_inst_meta_if fd_inst_meta_de, +module VX_decode #( + parameter CORE_ID = 0 +) ( + input wire clk, + input wire reset, - // Outputs - VX_backend_req_if frE_to_bckE_req_if, - VX_wstall_if wstall_if, - VX_join_if join_if + // inputs + VX_ifetch_rsp_if ifetch_rsp_if, + + // outputs + VX_decode_if decode_if, + VX_wstall_if wstall_if, + VX_join_if join_if ); - wire in_valid = (| fd_inst_meta_de.valid); - wire[31:0] in_instruction = fd_inst_meta_de.instruction; - wire[31:0] in_curr_PC = fd_inst_meta_de.curr_PC; - wire[`NW_BITS-1:0] in_warp_num = fd_inst_meta_de.warp_num; + `UNUSED_VAR (clk) + `UNUSED_VAR (reset) - assign frE_to_bckE_req_if.curr_PC = in_curr_PC; + wire [31:0] instr = ifetch_rsp_if.instr; - wire[6:0] curr_opcode; + reg [`ALU_BITS-1:0] alu_op; + reg [`BR_BITS-1:0] br_op; + reg [`LSU_BITS-1:0] lsu_op; + reg [`CSR_BITS-1:0] csr_op; + reg [`MUL_BITS-1:0] mul_op; + reg [`FPU_BITS-1:0] fpu_op; + reg [`GPU_BITS-1:0] gpu_op; - wire is_itype; - wire is_rtype; - wire is_stype; - wire is_btype; - wire is_linst; - wire is_jal; - wire is_jalr; - wire is_lui; - wire is_auipc; - wire is_csr; - wire is_csr_immed; - wire is_etype; + reg [19:0] upper_imm; + reg [31:0] jalx_offset; + reg [31:0] src2_imm; - wire is_gpgpu; - wire is_wspawn; - wire is_tmc; - wire is_split; - wire is_join; - wire is_barrier; + wire [6:0] opcode = instr[6:0]; + wire [2:0] func3 = instr[14:12]; + wire [6:0] func7 = instr[31:25]; + wire [11:0] u_12 = instr[31:20]; - wire[2:0] func3; - wire[6:0] func7; - wire[11:0] u_12; + wire [4:0] rd = instr[11:7]; + wire [4:0] rs1 = instr[19:15]; + wire [4:0] rs2 = instr[24:20]; + wire [4:0] rs3 = instr[31:27]; - wire[7:0] jal_b_19_to_12; - wire jal_b_11; - wire[9:0] jal_b_10_to_1; - wire jal_b_20; - wire jal_b_0; - wire[20:0] jal_unsigned_offset; - wire[31:0] jal_1_offset; + // opcode types + wire is_rtype = (opcode == `INST_R); + wire is_ltype = (opcode == `INST_L); + wire is_itype = (opcode == `INST_I); + wire is_stype = (opcode == `INST_S); + wire is_btype = (opcode == `INST_B); + wire is_jal = (opcode == `INST_JAL); + wire is_jalr = (opcode == `INST_JALR); + wire is_lui = (opcode == `INST_LUI); + wire is_auipc = (opcode == `INST_AUIPC); + wire is_jals = (opcode == `INST_SYS) && (func3 == 0); + wire is_csr = (opcode == `INST_SYS) && (func3 != 0); + wire is_gpu = (opcode == `INST_GPU); + + // upper immediate - wire[11:0] jalr_immed; - wire[31:0] jal_2_offset; - - wire jal_sys_cond1; - wire jal_sys_cond2; - wire jal_sys_jal; - wire[31:0] jal_sys_off; - - wire csr_cond1; - wire csr_cond2; - - wire[11:0] alu_tempp; - wire alu_shift_i; - wire[11:0] alu_shift_i_immed; - - wire[1:0] csr_type; - - reg[4:0] csr_alu; - reg[4:0] alu_op; - reg[4:0] mul_alu; - reg[19:0] temp_upper_immed; - reg temp_jal; - reg[31:0] temp_jal_offset; - reg[31:0] temp_itype_immed; - reg[2:0] temp_branch_type; - reg temp_branch_stall; - - assign frE_to_bckE_req_if.valid = fd_inst_meta_de.valid; - - assign frE_to_bckE_req_if.warp_num = in_warp_num; - - assign curr_opcode = in_instruction[6:0]; - - assign frE_to_bckE_req_if.rd = in_instruction[11:7]; - assign frE_to_bckE_req_if.rs1 = in_instruction[19:15]; - assign frE_to_bckE_req_if.rs2 = in_instruction[24:20]; - assign func3 = in_instruction[14:12]; - assign func7 = in_instruction[31:25]; - assign u_12 = in_instruction[31:20]; - - assign frE_to_bckE_req_if.next_PC = in_curr_PC + 32'h4; - - // Write Back sigal - assign is_rtype = (curr_opcode == `INST_R); - assign is_linst = (curr_opcode == `INST_L); - assign is_itype = (curr_opcode == `INST_ALU) || is_linst; - assign is_stype = (curr_opcode == `INST_S); - assign is_btype = (curr_opcode == `INST_B); - assign is_jal = (curr_opcode == `INST_JAL); - assign is_jalr = (curr_opcode == `INST_JALR); - assign is_lui = (curr_opcode == `INST_LUI); - assign is_auipc = (curr_opcode == `INST_AUIPC); - assign is_csr = (curr_opcode == `INST_SYS) && (func3 != 0); - assign is_csr_immed = is_csr && (func3[2] == 1); - - assign is_gpgpu = (curr_opcode == `INST_GPGPU); - - assign is_tmc = is_gpgpu && (func3 == 0); // Goes to BE - assign is_wspawn = is_gpgpu && (func3 == 1); // Goes to BE - assign is_barrier = is_gpgpu && (func3 == 4); // Goes to BE - assign is_split = is_gpgpu && (func3 == 2); // Goes to BE - assign is_join = is_gpgpu && (func3 == 3); // Doesn't go to BE - - assign join_if.is_join = is_join && in_valid; - assign join_if.warp_num = in_warp_num; - - assign frE_to_bckE_req_if.is_wspawn = is_wspawn; - assign frE_to_bckE_req_if.is_tmc = is_tmc; - assign frE_to_bckE_req_if.is_split = is_split; - assign frE_to_bckE_req_if.is_barrier = is_barrier; - - assign frE_to_bckE_req_if.csr_immed = is_csr_immed; - assign frE_to_bckE_req_if.is_csr = is_csr; - - assign frE_to_bckE_req_if.wb = (is_jal || is_jalr || is_etype) ? `WB_JAL : - is_linst ? `WB_MEM : - (is_itype || is_rtype || is_lui || is_auipc || is_csr) ? `WB_ALU : - `WB_NO; - - assign frE_to_bckE_req_if.rs2_src = (is_itype || is_stype) ? `RS2_IMMED : `RS2_REG; - - // MEM signals - assign frE_to_bckE_req_if.mem_read = (is_linst) ? func3 : `BYTE_EN_NO; - assign frE_to_bckE_req_if.mem_write = (is_stype) ? func3 : `BYTE_EN_NO; - - // UPPER IMMEDIATE always @(*) begin - case (curr_opcode) - `INST_LUI: temp_upper_immed = {func7, frE_to_bckE_req_if.rs2, frE_to_bckE_req_if.rs1, func3}; - `INST_AUIPC: temp_upper_immed = {func7, frE_to_bckE_req_if.rs2, frE_to_bckE_req_if.rs1, func3}; - default: temp_upper_immed = 20'h0; - endcase // curr_opcode - end - - assign frE_to_bckE_req_if.upper_immed = temp_upper_immed; - - assign jal_b_19_to_12 = in_instruction[19:12]; - assign jal_b_11 = in_instruction[20]; - assign jal_b_10_to_1 = in_instruction[30:21]; - assign jal_b_20 = in_instruction[31]; - assign jal_b_0 = 1'b0; - assign jal_unsigned_offset = {jal_b_20, jal_b_19_to_12, jal_b_11, jal_b_10_to_1, jal_b_0}; - assign jal_1_offset = {{11{jal_b_20}}, jal_unsigned_offset}; - - assign jalr_immed = {func7, frE_to_bckE_req_if.rs2}; - assign jal_2_offset = {{20{jalr_immed[11]}}, jalr_immed}; - - assign jal_sys_cond1 = (func3 == 3'h0); - assign jal_sys_cond2 = (u_12 < 12'h2); - - assign jal_sys_jal = (jal_sys_cond1 && jal_sys_cond2) ? 1'b1 : 1'b0; - assign jal_sys_off = (jal_sys_cond1 && jal_sys_cond2) ? 32'hb0000000 : 32'hdeadbeef; - - // JAL - always @(*) begin - case (curr_opcode) - `INST_JAL: - begin - temp_jal = in_valid; - temp_jal_offset = jal_1_offset; - end - `INST_JALR: - begin - temp_jal = in_valid; - temp_jal_offset = jal_2_offset; - end - `INST_SYS: - begin - // $display("SYS EBREAK %h", (jal_sys_jal && in_valid)); - temp_jal = jal_sys_jal && in_valid; - temp_jal_offset = jal_sys_off; - end - default: - begin - temp_jal = 1'b0; - temp_jal_offset = 32'hdeadbeef; - end + case (opcode) + `INST_LUI: upper_imm = {func7, rs2, rs1, func3}; + `INST_AUIPC: upper_imm = {func7, rs2, rs1, func3}; + default: upper_imm = 20'h0; endcase - end + end - assign frE_to_bckE_req_if.is_jal = is_jal; - assign frE_to_bckE_req_if.jal = temp_jal; - assign frE_to_bckE_req_if.jal_offset = temp_jal_offset; - - // ecall/ebreak - assign is_etype = (curr_opcode == `INST_SYS) && jal_sys_jal; - assign frE_to_bckE_req_if.is_etype = is_etype; - - // CSR - - assign csr_cond1 = func3 != 3'h0; - assign csr_cond2 = u_12 >= 12'h2; - - assign frE_to_bckE_req_if.csr_addr = (csr_cond1 && csr_cond2) ? u_12 : 12'h55; - - // ITYPE IMEED - assign alu_shift_i = (func3 == 3'h1) || (func3 == 3'h5); - assign alu_shift_i_immed = {{7{1'b0}}, frE_to_bckE_req_if.rs2}; - assign alu_tempp = alu_shift_i ? alu_shift_i_immed : u_12; + // I-type immediate + wire alu_shift_i = (func3 == 3'h1) || (func3 == 3'h5); + wire [11:0] alu_shift_imm = {{7{1'b0}}, rs2}; + wire [11:0] alu_imm = alu_shift_i ? alu_shift_imm : u_12; always @(*) begin - case (curr_opcode) - `INST_ALU: temp_itype_immed = {{20{alu_tempp[11]}}, alu_tempp}; - `INST_S: temp_itype_immed = {{20{func7[6]}}, func7, frE_to_bckE_req_if.rd}; - `INST_L: temp_itype_immed = {{20{u_12[11]}}, u_12}; - `INST_B: temp_itype_immed = {{20{in_instruction[31]}}, in_instruction[31], in_instruction[7], in_instruction[30:25], in_instruction[11:8]}; - default: temp_itype_immed = 32'hdeadbeef; + case (opcode) + `INST_I: src2_imm = {{20{alu_imm[11]}}, alu_imm}; + `INST_S, + `INST_FS: src2_imm = {{20{func7[6]}}, func7, rd}; + `INST_L, + `INST_FL: src2_imm = {{20{u_12[11]}}, u_12}; + `INST_B: src2_imm = {{20{instr[31]}}, instr[7], instr[30:25], instr[11:8], 1'b0}; + default: src2_imm = 32'hdeadbeef; endcase - end + end - assign frE_to_bckE_req_if.itype_immed = temp_itype_immed; + // JAL + + wire [20:0] jal_imm = {instr[31], instr[19:12], instr[20], instr[30:21], 1'b0}; + wire [31:0] jal_offset = {{11{jal_imm[20]}}, jal_imm}; + wire [11:0] jalr_imm = {func7, rs2}; + wire [31:0] jalr_offset = {{20{jalr_imm[11]}}, jalr_imm}; + always @(*) begin + case (opcode) + `INST_JAL: jalx_offset = jal_offset; + `INST_JALR: jalx_offset = jalr_offset; + default: jalx_offset = 32'd4; + endcase + end + + // BRANCH + + wire is_br = (is_btype || is_jal || is_jalr || is_jals); always @(*) begin - case (curr_opcode) + br_op = `BR_OTHER; + case (opcode) `INST_B: begin - // $display("BRANCH IN DECODE"); - temp_branch_stall = in_valid; case (func3) - 3'h0: temp_branch_type = `BR_EQ; - 3'h1: temp_branch_type = `BR_NE; - 3'h4: temp_branch_type = `BR_LT; - 3'h5: temp_branch_type = `BR_GT; - 3'h6: temp_branch_type = `BR_LTU; - 3'h7: temp_branch_type = `BR_GTU; - default: temp_branch_type = `BR_NO; + 3'h0: br_op = `BR_EQ; + 3'h1: br_op = `BR_NE; + 3'h4: br_op = `BR_LT; + 3'h5: br_op = `BR_GE; + 3'h6: br_op = `BR_LTU; + 3'h7: br_op = `BR_GEU; + default:; endcase end - `INST_JAL: begin - temp_branch_type = `BR_NO; - temp_branch_stall = in_valid; - end - `INST_JALR: begin - temp_branch_type = `BR_NO; - temp_branch_stall = in_valid; - end - default: begin - temp_branch_type = `BR_NO; - temp_branch_stall = 1'b0; + `INST_JAL: br_op = `BR_JAL; + `INST_JALR: br_op = `BR_JALR; + `INST_SYS: begin + if (is_jals && u_12 == 12'h000) br_op = `BR_ECALL; + if (is_jals && u_12 == 12'h001) br_op = `BR_EBREAK; + if (is_jals && u_12 == 12'h302) br_op = `BR_MRET; + if (is_jals && u_12 == 12'h102) br_op = `BR_SRET; + if (is_jals && u_12 == 12'h7B2) br_op = `BR_DRET; end + default:; + endcase + end + + // ALU + + always @(*) begin + alu_op = `ALU_OTHER; + if (is_lui) begin + alu_op = `ALU_LUI; + end else if (is_auipc) begin + alu_op = `ALU_AUIPC; + end else if (is_itype || is_rtype) begin + case (func3) + 3'h0: alu_op = (is_rtype && func7 == 7'h20) ? `ALU_SUB : `ALU_ADD; + 3'h1: alu_op = `ALU_SLL; + 3'h2: alu_op = `ALU_SLT; + 3'h3: alu_op = `ALU_SLTU; + 3'h4: alu_op = `ALU_XOR; + 3'h5: alu_op = (func7 == 7'h0) ? `ALU_SRL : `ALU_SRA; + 3'h6: alu_op = `ALU_OR; + 3'h7: alu_op = `ALU_AND; + default:; + endcase + end + end + + // CSR + + wire is_csr_imm = is_csr && (func3[2] == 1); + + always @(*) begin + csr_op = `CSR_OTHER; + case (func3[1:0]) + 2'h1: csr_op = `CSR_RW; + 2'h2: csr_op = `CSR_RS; + 2'h3: csr_op = `CSR_RC; + default:; endcase end - assign frE_to_bckE_req_if.branch_type = temp_branch_type; - - assign wstall_if.wstall = (temp_branch_stall || is_tmc || is_split || is_barrier) && in_valid; - assign wstall_if.warp_num = in_warp_num; - + // MUL +`ifdef EXT_M_ENABLE + wire is_mul = is_rtype && (func7 == 7'h1); always @(*) begin - // ALU OP + mul_op = `MUL_MUL; case (func3) - 3'h0: alu_op = (curr_opcode == `INST_ALU) ? `ALU_ADD : (func7 == 7'h0 ? `ALU_ADD : `ALU_SUB); - 3'h1: alu_op = `ALU_SLLA; - 3'h2: alu_op = `ALU_SLT; - 3'h3: alu_op = `ALU_SLTU; - 3'h4: alu_op = `ALU_XOR; - 3'h5: alu_op = (func7 == 7'h0) ? `ALU_SRL : `ALU_SRA; - 3'h6: alu_op = `ALU_OR; - 3'h7: alu_op = `ALU_AND; - default: alu_op = `ALU_NO; + 3'h0: mul_op = `MUL_MUL; + 3'h1: mul_op = `MUL_MULH; + 3'h2: mul_op = `MUL_MULHSU; + 3'h3: mul_op = `MUL_MULHU; + 3'h4: mul_op = `MUL_DIV; + 3'h5: mul_op = `MUL_DIVU; + 3'h6: mul_op = `MUL_REM; + 3'h7: mul_op = `MUL_REMU; + default:; endcase end +`else + wire is_mul = 0; + always @(*) begin + mul_op = `MUL_MUL; + end +`endif + + // FPU +`ifdef EXT_F_ENABLE + wire is_fl = (opcode == `INST_FL) && ((func3 == 2)); + wire is_fs = (opcode == `INST_FS) && ((func3 == 2)); + wire is_fci = (opcode == `INST_FCI); + wire is_fmadd = (opcode == `INST_FMADD); + wire is_fmsub = (opcode == `INST_FMSUB); + wire is_fnmsub = (opcode == `INST_FNMSUB); + wire is_fnmadd = (opcode == `INST_FNMADD); + + wire is_fcmp = is_fci && (func7 == 7'h50); // compare + wire is_fcvti = is_fci && (func7 == 7'h60); // convert to int + wire is_fcvtf = is_fci && (func7 == 7'h68); // convert to float + wire is_fmvw_clss = is_fci && (func7 == 7'h70); // move to int + class + wire is_fmvx = is_fci && (func7 == 7'h78); // move to float + wire is_fr4 = is_fmadd || is_fmsub || is_fnmsub || is_fnmadd; + wire is_fpu = (is_fl || is_fs || is_fci || is_fr4); + + reg [2:0] frm; + + always @(*) begin + fpu_op = `FPU_MISC; + frm = func3; + if (is_fr4) begin + case ({is_fmadd, is_fmsub, is_fnmsub, is_fnmadd}) + 4'b1000: fpu_op = `FPU_MADD; + 4'b0100: fpu_op = `FPU_MSUB; + 4'b0010: fpu_op = `FPU_NMSUB; + 4'b0001: fpu_op = `FPU_NMADD; + default:; + endcase + end + else begin + case (func7) + 7'h00: fpu_op = `FPU_ADD; + 7'h04: fpu_op = `FPU_SUB; + 7'h08: fpu_op = `FPU_MUL; + 7'h0C: fpu_op = `FPU_DIV; + 7'h10: begin + fpu_op = `FPU_MISC; + frm = (func3[1]) ? 2 : ((func3[0]) ? 1 : 0); + end + 7'h14: begin + fpu_op = `FPU_MISC; + frm = (func3 == 3'h0) ? 3 : 4; + end + 7'h2C: fpu_op = `FPU_SQRT; + 7'h50: fpu_op = `FPU_CMP; // wb to intReg + 7'h60: fpu_op = (instr[20]) ? `FPU_CVTWUS : `FPU_CVTWS; // doesn't need rs2, and read rs1 from fpReg, WB to intReg + 7'h68: fpu_op = (instr[20]) ? `FPU_CVTSWU : `FPU_CVTSW; // doesn't need rs2, and read rs1 from intReg + 7'h70: begin + fpu_op = (func3 == 3'h0) ? `FPU_MISC : `FPU_CLASS; + frm = (func3 == 3'h0) ? 5 : func3; + end + 7'h78: begin fpu_op = `FPU_MISC; frm = 6; end + default:; + endcase + end + end +`else + wire is_fl = 0; + wire is_fs = 0; + wire is_fci = 0; + wire is_fcvti = 0; + wire is_fcvtf = 0; + wire is_fmvw_clss = 0; + wire is_fmvx = 0; + wire is_fr4 = 0; + wire is_fpu = 0; + wire [2:0] frm = 0; always @(*) begin - // ALU OP + fpu_op = `FPU_MISC; + end +`endif + + // LSU + + wire is_lsu = (is_ltype || is_stype || is_fl || is_fs); + always @(*) begin + lsu_op = {is_stype, func3}; + if (is_fl) lsu_op = `LSU_LW; + if (is_fs) lsu_op = `LSU_SW; + end + + // GPU + + always @(*) begin + gpu_op = `GPU_OTHER; case (func3) - 3'h0: mul_alu = `ALU_MUL; - 3'h1: mul_alu = `ALU_MULH; - 3'h2: mul_alu = `ALU_MULHSU; - 3'h3: mul_alu = `ALU_MULHU; - 3'h4: mul_alu = `ALU_DIV; - 3'h5: mul_alu = `ALU_DIVU; - 3'h6: mul_alu = `ALU_REM; - 3'h7: mul_alu = `ALU_REMU; - default: mul_alu = `ALU_NO; + 3'h0: gpu_op = `GPU_TMC; + 3'h1: gpu_op = `GPU_WSPAWN; + 3'h2: gpu_op = `GPU_SPLIT; + 3'h3: gpu_op = `GPU_JOIN; + 3'h4: gpu_op = `GPU_BAR; + default:; endcase end - assign csr_type = func3[1:0]; + /////////////////////////////////////////////////////////////////////////// - always @(*) begin - case (csr_type) - 2'h1: csr_alu = `ALU_CSR_RW; - 2'h2: csr_alu = `ALU_CSR_RS; - 2'h3: csr_alu = `ALU_CSR_RC; - default: csr_alu = `ALU_NO; - endcase + wire use_rd = (is_fl || is_fci || is_fr4) + || ((rd != 0) && (is_itype || is_rtype || is_lui || is_auipc || is_csr || is_jal || is_jalr || is_jals || is_ltype)); + + wire use_rs1 = is_fpu + || is_gpu + || ((is_jalr || is_btype || is_ltype || is_stype || is_itype || is_rtype || ~is_csr_imm || is_gpu) && (rs1 != 0)); + + wire use_rs2 = (is_fpu && ~(is_fl || (fpu_op == `FPU_SQRT) || is_fcvti || is_fcvtf || is_fmvw_clss || is_fmvx)) + || (is_gpu && (gpu_op == `GPU_BAR || gpu_op == `GPU_WSPAWN)) + || ((is_btype || is_stype || is_rtype) && (rs2 != 0)); + + wire use_rs3 = is_fr4; + + wire [4:0] rs1_qual = is_lui ? 5'h0 : rs1; + + /////////////////////////////////////////////////////////////////////////// + + assign decode_if.valid = ifetch_rsp_if.valid + && (decode_if.ex_type != `EX_NOP); // skip noop + + assign decode_if.wid = ifetch_rsp_if.wid; + assign decode_if.tmask = ifetch_rsp_if.tmask; + assign decode_if.PC = ifetch_rsp_if.PC; + + assign decode_if.ex_type = is_lsu ? `EX_LSU : + is_csr ? `EX_CSR : + is_mul ? `EX_MUL : + is_fpu ? `EX_FPU : + is_gpu ? `EX_GPU : + is_br ? `EX_ALU : + (is_rtype || is_itype || is_lui || is_auipc) ? `EX_ALU : + `EX_NOP; + + assign decode_if.op_type = is_lsu ? `OP_BITS'(lsu_op) : + is_csr ? `OP_BITS'(csr_op) : + is_mul ? `OP_BITS'(mul_op) : + is_fpu ? `OP_BITS'(fpu_op) : + is_gpu ? `OP_BITS'(gpu_op) : + is_br ? `OP_BITS'(br_op) : + (is_rtype || is_itype || is_lui || is_auipc) ? `OP_BITS'(alu_op) : + 0; + + assign decode_if.wb = use_rd; + + `ifdef EXT_F_ENABLE + wire rd_is_fp = is_fpu && ~(is_fcmp || is_fcvti || is_fmvw_clss); + wire rs1_is_fp = is_fr4 || (is_fci && ~(is_fcvtf || is_fmvx)); + wire rs2_is_fp = is_fs || is_fr4 || is_fci; + + assign decode_if.rd = {rd_is_fp, rd}; + assign decode_if.rs1 = {rs1_is_fp, rs1_qual}; + assign decode_if.rs2 = {rs2_is_fp, rs2}; + assign decode_if.rs3 = {1'b1, rs3}; + `else + assign decode_if.rd = rd; + assign decode_if.rs1 = rs1_qual; + assign decode_if.rs2 = rs2; + assign decode_if.rs3 = rs3; + `endif + + assign decode_if.use_rs3 = use_rs3; + + assign decode_if.used_regs = ((`NUM_REGS)'(use_rd) << decode_if.rd) + | ((`NUM_REGS)'(use_rs1) << decode_if.rs1) + | ((`NUM_REGS)'(use_rs2) << decode_if.rs2) + | ((`NUM_REGS)'(use_rs3) << decode_if.rs3); + + assign decode_if.imm = (is_lui || is_auipc) ? {upper_imm, 12'(0)} : + (is_jal || is_jalr || is_jals) ? jalx_offset : + is_csr ? 32'(u_12) : + src2_imm; + + assign decode_if.rs1_is_PC = is_auipc || is_btype || is_jal || is_jals; + assign decode_if.rs2_is_imm = is_itype || is_lui || is_auipc || is_csr_imm || is_br; + + assign decode_if.op_mod = is_fpu ? frm : (is_br ? 1 : 0); + + /////////////////////////////////////////////////////////////////////////// + + wire decode_fire = decode_if.valid && decode_if.ready; + + assign join_if.valid = decode_fire && is_gpu && (gpu_op == `GPU_JOIN); + assign join_if.wid = ifetch_rsp_if.wid; + + assign wstall_if.valid = decode_fire && (is_btype + || is_jal + || is_jalr + || (is_gpu && (gpu_op == `GPU_TMC + || gpu_op == `GPU_SPLIT + || gpu_op == `GPU_BAR))); + assign wstall_if.wid = ifetch_rsp_if.wid; + + /////////////////////////////////////////////////////////////////////////// + + assign ifetch_rsp_if.ready = decode_if.ready; + +`ifdef DBG_PRINT_PIPELINE + always @(posedge clk) begin + if (decode_if.valid && decode_if.ready) begin + $write("%t: core%0d-decode: wid=%0d, PC=%0h, ex=", $time, CORE_ID, decode_if.wid, decode_if.PC); + print_ex_type(decode_if.ex_type); + $write(", op="); + print_ex_op(decode_if.ex_type, decode_if.op_type, decode_if.op_mod); + $write(", mod=%0d, tmask=%b, wb=%b, rd=%0d, rs1=%0d, rs2=%0d, rs3=%0d, imm=%0h, use_pc=%b, use_imm=%b\n", decode_if.op_mod, decode_if.tmask, decode_if.wb, decode_if.rd, decode_if.rs1, decode_if.rs2, decode_if.rs3, decode_if.imm, decode_if.rs1_is_PC, decode_if.rs2_is_imm); + end end +`endif - wire[4:0] temp_final_alu; - - assign temp_final_alu = is_btype ? ((frE_to_bckE_req_if.branch_type < `BR_LTU) ? `ALU_SUB : `ALU_SUBU) : - is_lui ? `ALU_LUI : - is_auipc ? `ALU_AUIPC : - is_csr ? csr_alu : - (is_stype || is_linst) ? `ALU_ADD : - alu_op; - - assign frE_to_bckE_req_if.alu_op = ((func7[0] == 1'b1) && is_rtype) ? mul_alu : temp_final_alu; - -endmodule - - - - - - - - +endmodule \ No newline at end of file diff --git a/hw/rtl/VX_define.vh b/hw/rtl/VX_define.vh index 21da158e..dcb7e8b7 100644 --- a/hw/rtl/VX_define.vh +++ b/hw/rtl/VX_define.vh @@ -1,60 +1,13 @@ `ifndef VX_DEFINE `define VX_DEFINE +`include "VX_platform.vh" `include "VX_config.vh" -`include "VX_scope.vh" - -`define QUEUE_FORCE_MLAB 1 - -// `define SYNTHESIS 1 -// `define ASIC 1 /////////////////////////////////////////////////////////////////////////////// -`ifndef NDEBUG - `define DEBUG_BLOCK(x) /* verilator lint_off UNUSED */ \ - x \ - /* verilator lint_on UNUSED */ -`else - `define DEBUG_BLOCK(x) -`endif - -`define DEBUG_BEGIN /* verilator lint_off UNUSED */ - -`define DEBUG_END /* verilator lint_on UNUSED */ - -`define IGNORE_WARNINGS_BEGIN /* verilator lint_off UNUSED */ \ - /* verilator lint_off PINCONNECTEMPTY */ \ - /* verilator lint_off DECLFILENAME */ - -`define IGNORE_WARNINGS_END /* verilator lint_on UNUSED */ \ - /* verilator lint_on PINCONNECTEMPTY */ \ - /* verilator lint_on DECLFILENAME */ - -`define UNUSED_VAR(x) /* verilator lint_off UNUSED */ \ - wire [$bits(x)-1:0] __``x``__ = x; \ - /* verilator lint_on UNUSED */ - -`define UNUSED_PIN(x) /* verilator lint_off PINCONNECTEMPTY */ \ - . x () \ - /* verilator lint_on PINCONNECTEMPTY */ - -`define STRINGIFY(x) `"x`" - -`define STATIC_ASSERT(cond, msg) \ - generate \ - if (!(cond)) $error(msg); \ - endgenerate - -`define CLOG2(x) $clog2(x) -`define FLOG2(x) ($clog2(x) - (((1 << $clog2(x)) > (x)) ? 1 : 0)) -`define LOG2UP(x) (((x) > 1) ? $clog2(x) : 1) -`define ISPOW2(x) (((x) != 0) && (0 == ((x) & ((x) - 1)))) - -`define MIN(x, y) ((x < y) ? (x) : (y)) -`define MAX(x, y) ((x > y) ? (x) : (y)) - -`define UP(x) (((x) > 0) ? x : 1) +// `define SYNTHESIS 1 +// `define ASIC 1 /////////////////////////////////////////////////////////////////////////////// @@ -64,90 +17,232 @@ `define NC_BITS `LOG2UP(`NUM_CORES) +`define NB_BITS `LOG2UP(`NUM_BARRIERS) + `define REQS_BITS `LOG2UP(NUM_REQUESTS) -`define NUM_GPRS 32 +`ifdef EXT_F_ENABLE +`define NUM_REGS 64 +`else +`define NUM_REGS 32 +`endif -`define CSR_ADDR_SIZE 12 +`define NR_BITS `LOG2UP(`NUM_REGS) + +`define CSR_ADDR_BITS 12 `define CSR_WIDTH 12 -`define DIV_LATENCY 22 +/////////////////////////////////////////////////////////////////////////////// -`define MUL_LATENCY 2 +`define INST_LUI 7'b0110111 +`define INST_AUIPC 7'b0010111 +`define INST_JAL 7'b1101111 +`define INST_JALR 7'b1100111 +`define INST_B 7'b1100011 // branch instructions +`define INST_L 7'b0000011 // load instructions +`define INST_S 7'b0100011 // store instructions +`define INST_I 7'b0010011 // immediate instructions +`define INST_R 7'b0110011 // register instructions +`define INST_F 7'b0001111 // Fence instructions +`define INST_SYS 7'b1110011 // system instructions + +`define INST_FL 7'b0000111 // float load instruction +`define INST_FS 7'b0100111 // float store instruction +`define INST_FMADD 7'b1000011 +`define INST_FMSUB 7'b1000111 +`define INST_FNMSUB 7'b1001011 +`define INST_FNMADD 7'b1001111 +`define INST_FCI 7'b1010011 // float common instructions + +`define INST_GPU 7'b1101011 /////////////////////////////////////////////////////////////////////////////// -`define BYTE_EN_NO 3'h7 -`define BYTE_EN_SB 3'h0 -`define BYTE_EN_SH 3'h1 -`define BYTE_EN_SW 3'h2 -`define BYTE_EN_UB 3'h4 -`define BYTE_EN_UH 3'h5 -`define BYTE_EN_BITS 3 +`define BYTEEN_SB 3'h0 +`define BYTEEN_SH 3'h1 +`define BYTEEN_SW 3'h2 +`define BYTEEN_UB 3'h4 +`define BYTEEN_UH 3'h5 +`define BYTEEN_BITS 3 +`define BYTEEN_TYPE(x) x[1:0] + +`define FRM_RNE 3'b000 // round to nearest even +`define FRM_RTZ 3'b001 // round to zero +`define FRM_RDN 3'b010 // round to -inf +`define FRM_RUP 3'b011 // round to +inf +`define FRM_RMM 3'b100 // round to nearest max magnitude +`define FRM_DYN 3'b111 // dynamic mode +`define FRM_BITS 3 /////////////////////////////////////////////////////////////////////////////// -`define INST_R 7'd051 -`define INST_L 7'd003 -`define INST_ALU 7'd019 -`define INST_S 7'd035 -`define INST_B 7'd099 -`define INST_LUI 7'd055 -`define INST_AUIPC 7'd023 -`define INST_JAL 7'd111 -`define INST_JALR 7'd103 -`define INST_SYS 7'd115 -`define INST_GPGPU 7'd107 +`define EX_NOP 3'h0 +`define EX_ALU 3'h1 +`define EX_LSU 3'h2 +`define EX_CSR 3'h3 +`define EX_MUL 3'h4 +`define EX_FPU 3'h5 +`define EX_GPU 3'h6 +`define EX_BITS 3 -`define RS2_IMMED 1 -`define RS2_REG 0 - -`define BR_NO 3'h0 -`define BR_EQ 3'h1 -`define BR_NE 3'h2 -`define BR_LT 3'h3 -`define BR_GT 3'h4 -`define BR_LTU 3'h5 -`define BR_GTU 3'h6 - -`define ALU_NO 5'd15 -`define ALU_ADD 5'd00 -`define ALU_SUB 5'd01 -`define ALU_SLLA 5'd02 -`define ALU_SLT 5'd03 -`define ALU_SLTU 5'd04 -`define ALU_XOR 5'd05 -`define ALU_SRL 5'd06 -`define ALU_SRA 5'd07 -`define ALU_OR 5'd08 -`define ALU_AND 5'd09 -`define ALU_SUBU 5'd10 -`define ALU_LUI 5'd11 -`define ALU_AUIPC 5'd12 -`define ALU_CSR_RW 5'd13 -`define ALU_CSR_RS 5'd14 -`define ALU_CSR_RC 5'd15 -`define ALU_MUL 5'd16 -`define ALU_MULH 5'd17 -`define ALU_MULHSU 5'd18 -`define ALU_MULHU 5'd19 -`define ALU_DIV 5'd20 -`define ALU_DIVU 5'd21 -`define ALU_REM 5'd22 -`define ALU_REMU 5'd23 - -`define WB_NO 2'h0 -`define WB_ALU 2'h1 -`define WB_MEM 2'h2 -`define WB_JAL 2'h3 +`define NUM_EXS 6 +`define NE_BITS `LOG2UP(`NUM_EXS) /////////////////////////////////////////////////////////////////////////////// -`ifdef DBG_CORE_REQ_INFO // pc, wb, rd, warp_num -`define DEBUG_CORE_REQ_MDATA_WIDTH (32 + 2 + 5 + `NW_BITS) +`define OP_BITS 4 +`define MOD_BITS 3 + +`define ALU_ADD 4'b0000 +`define ALU_LUI 4'b0010 +`define ALU_AUIPC 4'b0011 +`define ALU_SLTU 4'b0100 +`define ALU_SLT 4'b0101 +`define ALU_SRL 4'b1000 +`define ALU_SRA 4'b1001 +`define ALU_SUB 4'b1011 +`define ALU_AND 4'b1100 +`define ALU_OR 4'b1101 +`define ALU_XOR 4'b1110 +`define ALU_SLL 4'b1111 +`define ALU_OTHER 4'b0111 +`define ALU_BITS 4 +`define ALU_OP(x) x[`ALU_BITS-1:0] +`define ALU_OP_CLASS(x) x[3:2] +`define ALU_SIGNED(x) x[0] + +`define BR_EQ 4'b0000 +`define BR_NE 4'b0010 +`define BR_LTU 4'b0100 +`define BR_GEU 4'b0110 +`define BR_LT 4'b0101 +`define BR_GE 4'b0111 +`define BR_JAL 4'b1000 +`define BR_JALR 4'b1001 +`define BR_ECALL 4'b1010 +`define BR_EBREAK 4'b1011 +`define BR_MRET 4'b1100 +`define BR_SRET 4'b1101 +`define BR_DRET 4'b1110 +`define BR_OTHER 4'b1111 +`define BR_BITS 4 +`define BR_OP(x) x[`BR_BITS-1:0] +`define BR_NEG(x) x[1] +`define BR_LESS(x) x[2] +`define BR_STATIC(x) x[3] +`define ALU_BR_BITS 4 +`define ALU_BR_OP(x) x[`ALU_BR_BITS-1:0] +`define IS_BR_MOD(x) x[0] + +`define LSU_LB {1'b0, `BYTEEN_SB} +`define LSU_LH {1'b0, `BYTEEN_SH} +`define LSU_LW {1'b0, `BYTEEN_SW} +`define LSU_LBU {1'b0, `BYTEEN_UB} +`define LSU_LHU {1'b0, `BYTEEN_UH} +`define LSU_SB {1'b1, `BYTEEN_SB} +`define LSU_SH {1'b1, `BYTEEN_SH} +`define LSU_SW {1'b1, `BYTEEN_SW} +`define LSU_SBU {1'b1, `BYTEEN_UB} +`define LSU_SHU {1'b1, `BYTEEN_UH} +`define LSU_BITS 4 +`define LSU_RW(x) x[3] +`define LSU_BE(x) x[2:0] + +`define CSR_RW 2'h0 +`define CSR_RS 2'h1 +`define CSR_RC 2'h2 +`define CSR_OTHER 2'h3 +`define CSR_BITS 2 +`define CSR_OP(x) x[`CSR_BITS-1:0] + +`define MUL_MUL 3'h0 +`define MUL_MULH 3'h1 +`define MUL_MULHSU 3'h2 +`define MUL_MULHU 3'h3 +`define MUL_DIV 3'h4 +`define MUL_DIVU 3'h5 +`define MUL_REM 3'h6 +`define MUL_REMU 3'h7 +`define MUL_BITS 3 +`define MUL_OP(x) x[`MUL_BITS-1:0] +`define IS_DIV_OP(x) x[2] + +`define FPU_ADD 4'h0 +`define FPU_SUB 4'h1 +`define FPU_MUL 4'h2 +`define FPU_DIV 4'h3 +`define FPU_SQRT 4'h4 +`define FPU_MADD 4'h5 +`define FPU_MSUB 4'h6 +`define FPU_NMSUB 4'h7 +`define FPU_NMADD 4'h8 +`define FPU_CVTWS 4'h9 // FCVT.W.S +`define FPU_CVTWUS 4'hA // FCVT.WU.S +`define FPU_CVTSW 4'hB // FCVT.S.W +`define FPU_CVTSWU 4'hC // FCVT.S.WU +`define FPU_CLASS 4'hD +`define FPU_CMP 4'hE +`define FPU_MISC 4'hF // SGNJ, SGNJN, SGNJX, FMIN, FMAX, MVXW, MVWX +`define FPU_BITS 4 +`define FPU_OP(x) x[`FPU_BITS-1:0] + +`define GPU_TMC 3'h0 +`define GPU_WSPAWN 3'h1 +`define GPU_SPLIT 3'h2 +`define GPU_JOIN 3'h3 +`define GPU_BAR 3'h4 +`define GPU_OTHER 3'h7 +`define GPU_BITS 3 +`define GPU_OP(x) x[`GPU_BITS-1:0] + +/////////////////////////////////////////////////////////////////////////////// + +`ifdef EXT_M_ENABLE + `define ISA_EXT_M (1 << 12) `else -`define DEBUG_CORE_REQ_MDATA_WIDTH 0 + `define ISA_EXT_M 0 +`endif + +`ifdef EXT_F_ENABLE + `define ISA_EXT_F (1 << 5) +`else + `define ISA_EXT_F 0 +`endif + +`define ISA_CODE (0 << 0) // A - Atomic Instructions extension \ + | (0 << 1) // B - Tentatively reserved for Bit operations extension \ + | (0 << 2) // C - Compressed extension \ + | (0 << 3) // D - Double precsision floating-point extension \ + | (0 << 4) // E - RV32E base ISA \ + |`ISA_EXT_F // F - Single precsision floating-point extension \ + | (0 << 6) // G - Additional standard extensions present \ + | (0 << 7) // H - Hypervisor mode implemented \ + | (1 << 8) // I - RV32I/64I/128I base ISA \ + | (0 << 9) // J - Reserved \ + | (0 << 10) // K - Reserved \ + | (0 << 11) // L - Tentatively reserved for Bit operations extension \ + |`ISA_EXT_M // M - Integer Multiply/Divide extension \ + | (0 << 13) // N - User level interrupts supported \ + | (0 << 14) // O - Reserved \ + | (0 << 15) // P - Tentatively reserved for Packed-SIMD extension \ + | (0 << 16) // Q - Quad-precision floating-point extension \ + | (0 << 17) // R - Reserved \ + | (0 << 18) // S - Supervisor mode implemented \ + | (0 << 19) // T - Tentatively reserved for Transactional Memory extension \ + | (1 << 20) // U - User mode implemented \ + | (0 << 21) // V - Tentatively reserved for Vector extension \ + | (0 << 22) // W - Reserved \ + | (1 << 23) // X - Non-standard extensions present \ + | (0 << 24) // Y - Reserved \ + | (0 << 25) // Z - Reserved + +/////////////////////////////////////////////////////////////////////////////// + +`ifdef DBG_CORE_REQ_INFO // pc, rd, wid +`define DBG_CORE_REQ_MDATAW (32 + `NR_BITS + `NW_BITS) +`else +`define DBG_CORE_REQ_MDATAW 0 `endif ////////////////////////// Dcache Configurable Knobs ////////////////////////// @@ -156,10 +251,10 @@ `define DCACHE_ID (((`L3_ENABLE && `L2_ENABLE) ? 2 : `L2_ENABLE ? 1 : 0) + (CORE_ID * 3) + 0) // TAG sharing enable -`define DCORE_TAG_ID_BITS `LOG2UP(`DCREQ_SIZE) +`define DCORE_TAG_ID_BITS `LOG2UP(`LSUQ_SIZE) // Core request tag bits -`define DCORE_TAG_WIDTH (`DEBUG_CORE_REQ_MDATA_WIDTH + `DCORE_TAG_ID_BITS) +`define DCORE_TAG_WIDTH (`DBG_CORE_REQ_MDATAW + `DCORE_TAG_ID_BITS) // DRAM request data bits `define DDRAM_LINE_WIDTH (`DBANK_LINE_SIZE * 8) @@ -191,10 +286,10 @@ `define ICORE_BYTEEN_WIDTH `DWORD_SIZE // TAG sharing enable -`define ICORE_TAG_ID_BITS `LOG2UP(`ICREQ_SIZE) +`define ICORE_TAG_ID_BITS `NW_BITS // Core request tag bits -`define ICORE_TAG_WIDTH (`DEBUG_CORE_REQ_MDATA_WIDTH + `ICORE_TAG_ID_BITS) +`define ICORE_TAG_WIDTH (`DBG_CORE_REQ_MDATAW + `ICORE_TAG_ID_BITS) // DRAM request data bits `define IDRAM_LINE_WIDTH (`IBANK_LINE_SIZE * 8) @@ -288,9 +383,10 @@ `define VX_DRAM_TAG_WIDTH `L3DRAM_TAG_WIDTH `define VX_SNP_TAG_WIDTH `L3SNP_TAG_WIDTH `define VX_CORE_TAG_WIDTH `L3CORE_TAG_WIDTH -`define VX_CSR_ID_WIDTH `CLOG2(`NUM_CLUSTERS * `NUM_CORES) +`define VX_CSR_ID_WIDTH `LOG2UP(`NUM_CLUSTERS * `NUM_CORES) -`define DRAM_TO_BYTE_ADDR(x) {x, (32-$bits(x))'(0)} +`define DRAM_TO_BYTE_ADDR(x) {x, (32-$bits(x))'(0)} + +`include "VX_types.vh" - // VX_DEFINE `endif diff --git a/hw/rtl/VX_exec_unit.v b/hw/rtl/VX_exec_unit.v deleted file mode 100644 index 0b4259b5..00000000 --- a/hw/rtl/VX_exec_unit.v +++ /dev/null @@ -1,147 +0,0 @@ -`include "VX_define.vh" - -module VX_exec_unit ( - input wire clk, - input wire reset, - // Request - VX_exec_unit_req_if exec_unit_req_if, - - // Output - VX_wb_if inst_exec_wb_if, - VX_jal_rsp_if jal_rsp_if, - VX_branch_rsp_if branch_rsp_if, - - input wire no_slot_exec, - output wire delay -); - - wire [`NUM_THREADS-1:0][31:0] in_a_reg_data; - wire [`NUM_THREADS-1:0][31:0] in_b_reg_data; - wire [4:0] in_alu_op; - wire in_rs2_src; - wire [31:0] in_itype_immed; -`DEBUG_BEGIN - wire [2:0] in_branch_type; -`DEBUG_END - wire [19:0] in_upper_immed; - wire in_jal; - wire [31:0] in_jal_offset; - wire [31:0] in_curr_PC; - - assign in_a_reg_data = exec_unit_req_if.a_reg_data; - assign in_b_reg_data = exec_unit_req_if.b_reg_data; - assign in_alu_op = exec_unit_req_if.alu_op; - assign in_rs2_src = exec_unit_req_if.rs2_src; - assign in_itype_immed = exec_unit_req_if.itype_immed; - assign in_branch_type = exec_unit_req_if.branch_type; - assign in_upper_immed = exec_unit_req_if.upper_immed; - assign in_jal = exec_unit_req_if.jal; - assign in_jal_offset = exec_unit_req_if.jal_offset; - assign in_curr_PC = exec_unit_req_if.curr_PC; - - wire [`NUM_THREADS-1:0][31:0] alu_result; - wire [`NUM_THREADS-1:0] alu_stall; - - genvar i; - generate - for (i = 0; i < `NUM_THREADS; i++) begin - VX_alu_unit alu_unit ( - .clk (clk), - .reset (reset), - .src_a (in_a_reg_data[i]), - .src_b (in_b_reg_data[i]), - .src_rs2 (in_rs2_src), - .itype_immed (in_itype_immed), - .upper_immed (in_upper_immed), - .alu_op (in_alu_op), - .curr_PC (in_curr_PC), - .alu_result (alu_result[i]), - .alu_stall (alu_stall[i]) - ); - end - endgenerate - - wire internal_stall = (| alu_stall); - - assign delay = no_slot_exec || internal_stall; - - wire [$clog2(`NUM_THREADS)-1:0] jal_branch_use_index; - - VX_priority_encoder #( - .N(`NUM_THREADS) - ) choose_alu_result ( - .data_in (exec_unit_req_if.valid), - .data_out (jal_branch_use_index), - `UNUSED_PIN (valid_out) - ); - - wire [31:0] branch_use_alu_result = alu_result[jal_branch_use_index]; - - reg temp_branch_dir; - always @(*) - begin - case (exec_unit_req_if.branch_type) - `BR_EQ: temp_branch_dir = (branch_use_alu_result == 0); - `BR_NE: temp_branch_dir = (branch_use_alu_result != 0); - `BR_LT: temp_branch_dir = (branch_use_alu_result[31] != 0); - `BR_GT: temp_branch_dir = (branch_use_alu_result[31] == 0); - `BR_LTU: temp_branch_dir = (branch_use_alu_result[31] != 0); - `BR_GTU: temp_branch_dir = (branch_use_alu_result[31] == 0); - `BR_NO: temp_branch_dir = 0; - default: temp_branch_dir = 0; - endcase // in_branch_type - end - - wire [`NUM_THREADS-1:0][31:0] duplicate_PC_data; - - generate - for (i = 0; i < `NUM_THREADS; i++) begin - assign duplicate_PC_data[i] = exec_unit_req_if.next_PC; - end - endgenerate - - VX_jal_rsp_if jal_rsp_temp_if(); - VX_branch_rsp_if branch_rsp_temp_if(); - - // Actual Writeback - assign inst_exec_wb_if.rd = exec_unit_req_if.rd; - assign inst_exec_wb_if.wb = exec_unit_req_if.wb; - assign inst_exec_wb_if.valid = exec_unit_req_if.valid & {`NUM_THREADS{!internal_stall}}; - assign inst_exec_wb_if.warp_num = exec_unit_req_if.warp_num; - assign inst_exec_wb_if.data = exec_unit_req_if.jal ? duplicate_PC_data : alu_result; - assign inst_exec_wb_if.curr_PC = in_curr_PC; - - // Jal rsp - assign jal_rsp_temp_if.valid = in_jal; - assign jal_rsp_temp_if.dest = $signed(in_a_reg_data[jal_branch_use_index]) + $signed(in_jal_offset); - assign jal_rsp_temp_if.warp_num = exec_unit_req_if.warp_num; - - // Branch rsp - assign branch_rsp_temp_if.valid = (exec_unit_req_if.branch_type != `BR_NO) && (| exec_unit_req_if.valid); - assign branch_rsp_temp_if.dir = temp_branch_dir; - assign branch_rsp_temp_if.warp_num = exec_unit_req_if.warp_num; - assign branch_rsp_temp_if.dest = $signed(exec_unit_req_if.curr_PC) + ($signed(exec_unit_req_if.itype_immed) << 1); // itype_immed = branch_offset - - VX_generic_register #( - .N(33 + `NW_BITS-1 + 1) - ) jal_reg ( - .clk (clk), - .reset (reset), - .stall (1'b0), - .flush (1'b0), - .in ({jal_rsp_temp_if.valid, jal_rsp_temp_if.dest, jal_rsp_temp_if.warp_num}), - .out ({jal_rsp_if.valid , jal_rsp_if.dest , jal_rsp_if.warp_num}) - ); - - VX_generic_register #( - .N(34 + `NW_BITS-1 + 1) - ) branch_reg ( - .clk (clk), - .reset (reset), - .stall (1'b0), - .flush (1'b0), - .in ({branch_rsp_temp_if.valid, branch_rsp_temp_if.dir, branch_rsp_temp_if.warp_num, branch_rsp_temp_if.dest}), - .out ({branch_rsp_if.valid , branch_rsp_if.dir , branch_rsp_if.warp_num , branch_rsp_if.dest }) - ); - -endmodule : VX_exec_unit \ No newline at end of file diff --git a/hw/rtl/VX_execute.v b/hw/rtl/VX_execute.v new file mode 100644 index 00000000..f542d3ce --- /dev/null +++ b/hw/rtl/VX_execute.v @@ -0,0 +1,137 @@ +`include "VX_define.vh" + +module VX_execute #( + parameter CORE_ID = 0 +) ( + `SCOPE_SIGNALS_LSU_IO + `SCOPE_SIGNALS_EXECUTE_IO + + input wire clk, + input wire reset, + + // CSR io interface + VX_csr_io_req_if csr_io_req_if, + VX_csr_io_rsp_if csr_io_rsp_if, + + // Dcache interface + VX_cache_core_req_if dcache_req_if, + VX_cache_core_rsp_if dcache_rsp_if, + + // perf + VX_cmt_to_csr_if cmt_to_csr_if, + + // inputs + VX_alu_req_if alu_req_if, + VX_lsu_req_if lsu_req_if, + VX_csr_req_if csr_req_if, + VX_mul_req_if mul_req_if, + VX_fpu_req_if fpu_req_if, + VX_gpu_req_if gpu_req_if, + + // outputs + VX_csr_to_issue_if csr_to_issue_if, + VX_branch_ctl_if branch_ctl_if, + VX_warp_ctl_if warp_ctl_if, + VX_exu_to_cmt_if alu_commit_if, + VX_exu_to_cmt_if lsu_commit_if, + VX_exu_to_cmt_if csr_commit_if, + VX_exu_to_cmt_if mul_commit_if, + VX_fpu_to_cmt_if fpu_commit_if, + VX_exu_to_cmt_if gpu_commit_if, + + output wire ebreak +); + + VX_alu_unit #( + .CORE_ID(CORE_ID) + ) alu_unit ( + .clk (clk), + .reset (reset), + .alu_req_if (alu_req_if), + .branch_ctl_if (branch_ctl_if), + .alu_commit_if (alu_commit_if) + ); + + VX_lsu_unit #( + .CORE_ID(CORE_ID) + ) lsu_unit ( + `SCOPE_SIGNALS_LSU_BIND + .clk (clk), + .reset (reset), + .dcache_req_if (dcache_req_if), + .dcache_rsp_if (dcache_rsp_if), + .lsu_req_if (lsu_req_if), + .lsu_commit_if (lsu_commit_if) + ); + + VX_csr_unit #( + .CORE_ID(CORE_ID) + ) csr_unit ( + .clk (clk), + .reset (reset), + .cmt_to_csr_if (cmt_to_csr_if), + .csr_to_issue_if (csr_to_issue_if), + .csr_io_req_if (csr_io_req_if), + .csr_io_rsp_if (csr_io_rsp_if), + .csr_req_if (csr_req_if), + .csr_commit_if (csr_commit_if) + ); + +`ifdef EXT_M_ENABLE + VX_mul_unit #( + .CORE_ID(CORE_ID) + ) mul_unit ( + .clk (clk), + .reset (reset), + .mul_req_if (mul_req_if), + .mul_commit_if (mul_commit_if) + ); +`else + assign mul_req_if.ready = 0; + assign mul_commit_if.valid = 0; + assign mul_commit_if.wid = 0; + assign mul_commit_if.PC = 0; + assign mul_commit_if.tmask = 0; + assign mul_commit_if.wb = 0; + assign mul_commit_if.rd = 0; + assign mul_commit_if.data = 0; +`endif + +`ifdef EXT_F_ENABLE + VX_fpu_unit #( + .CORE_ID(CORE_ID) + ) fpu_unit ( + .clk (clk), + .reset (reset), + .fpu_req_if (fpu_req_if), + .fpu_commit_if (fpu_commit_if) + ); +`else + assign fpu_req_if.ready = 0; + assign fpu_commit_if.valid = 0; + assign fpu_commit_if.wid = 0; + assign fpu_commit_if.PC = 0; + assign fpu_commit_if.tmask = 0; + assign fpu_commit_if.wb = 0; + assign fpu_commit_if.rd = 0; + assign fpu_commit_if.data = 0; + assign fpu_commit_if.has_fflags = 0; + assign fpu_commit_if.fflags = 0; +`endif + + VX_gpu_unit #( + .CORE_ID(CORE_ID) + ) gpu_unit ( + .clk (clk), + .reset (reset), + .gpu_req_if (gpu_req_if), + .warp_ctl_if (warp_ctl_if), + .gpu_commit_if (gpu_commit_if) + ); + + assign ebreak = alu_req_if.valid + && alu_req_if.is_br_op + && (`BR_OP(alu_req_if.op_type) == `BR_EBREAK + || `BR_OP(alu_req_if.op_type) == `BR_ECALL); + +endmodule diff --git a/hw/rtl/VX_fetch.v b/hw/rtl/VX_fetch.v index 810f0317..cf0c2e45 100644 --- a/hw/rtl/VX_fetch.v +++ b/hw/rtl/VX_fetch.v @@ -1,99 +1,58 @@ `include "VX_define.vh" -module VX_fetch ( - input wire clk, - input wire reset, - VX_wstall_if wstall_if, - VX_join_if join_if, - input wire schedule_delay, - input wire icache_stage_delay, - input wire[`NW_BITS-1:0] icache_stage_wid, - input wire icache_stage_response, - output wire busy, - VX_jal_rsp_if jal_rsp_if, - VX_branch_rsp_if branch_rsp_if, - VX_inst_meta_if fe_inst_meta_fi, - VX_warp_ctl_if warp_ctl_if +module VX_fetch #( + parameter CORE_ID = 0 +) ( + `SCOPE_SIGNALS_ISTAGE_IO + + input wire clk, + input wire reset, + + // Icache interface + VX_cache_core_req_if icache_req_if, + VX_cache_core_rsp_if icache_rsp_if, + + // inputs + VX_wstall_if wstall_if, + VX_join_if join_if, + VX_branch_ctl_if branch_ctl_if, + VX_warp_ctl_if warp_ctl_if, + + // outputs + VX_ifetch_rsp_if ifetch_rsp_if, + + output wire busy ); - wire[`NUM_THREADS-1:0] thread_mask; - wire[`NW_BITS-1:0] warp_num; - wire[31:0] warp_pc; - wire scheduled_warp; + VX_ifetch_req_if ifetch_req_if(); - wire pipe_stall = schedule_delay || icache_stage_delay; - - VX_warp_sched warp_sched ( + VX_warp_sched #( + .CORE_ID(CORE_ID) + ) warp_sched ( .clk (clk), - .reset (reset), - .stall (pipe_stall), + .reset (reset), + .warp_ctl_if (warp_ctl_if), + .wstall_if (wstall_if), + .join_if (join_if), + .branch_ctl_if (branch_ctl_if), + .ifetch_req_if (ifetch_req_if), + .ifetch_rsp_if (ifetch_rsp_if), + .busy (busy) + ); - .is_barrier (warp_ctl_if.is_barrier), - .barrier_id (warp_ctl_if.barrier_id), - .num_warps (warp_ctl_if.num_warps), - .barrier_warp_num (warp_ctl_if.warp_num), + VX_icache_stage #( + .CORE_ID(CORE_ID) + ) icache_stage ( + `SCOPE_SIGNALS_ISTAGE_BIND - // Wspawn - .wspawn (warp_ctl_if.wspawn), - .wsapwn_pc (warp_ctl_if.wspawn_pc), - .wspawn_new_active(warp_ctl_if.wspawn_new_active), + .clk (clk), + .reset (reset), - // CTM - .ctm (warp_ctl_if.change_mask), - .ctm_mask (warp_ctl_if.thread_mask), - .ctm_warp_num (warp_ctl_if.warp_num), + .icache_rsp_if (icache_rsp_if), + .icache_req_if (icache_req_if), - // WHALT - .whalt (warp_ctl_if.whalt), - .whalt_warp_num (warp_ctl_if.warp_num), - - // Wstall - .wstall (wstall_if.wstall), - .wstall_warp_num (wstall_if.warp_num), - - // Lock/release Stuff - .icache_stage_response(icache_stage_response), - .icache_stage_wid (icache_stage_wid), - - // Join - .is_join (join_if.is_join), - .join_warp_num (join_if.warp_num), - - // Split - .is_split (warp_ctl_if.is_split), - .dont_split (warp_ctl_if.dont_split), - .split_new_mask (warp_ctl_if.split_new_mask), - .split_later_mask (warp_ctl_if.split_later_mask), - .split_save_pc (warp_ctl_if.split_save_pc), - .split_warp_num (warp_ctl_if.warp_num), - - // JAL - .jal (jal_rsp_if.valid), - .dest (jal_rsp_if.dest), - .jal_warp_num (jal_rsp_if.warp_num), - - // Branch - .branch_valid (branch_rsp_if.valid), - .branch_dir (branch_rsp_if.dir), - .branch_dest (branch_rsp_if.dest), - .branch_warp_num (branch_rsp_if.warp_num), - - // Outputs - .thread_mask (thread_mask), - .warp_num (warp_num), - .warp_pc (warp_pc), - .busy (busy), - .scheduled_warp (scheduled_warp) + .ifetch_req_if (ifetch_req_if), + .ifetch_rsp_if (ifetch_rsp_if) ); - assign fe_inst_meta_fi.warp_num = warp_num; - assign fe_inst_meta_fi.valid = thread_mask; - assign fe_inst_meta_fi.instruction = 32'h0; - assign fe_inst_meta_fi.curr_PC = warp_pc; - -`DEBUG_BEGIN - wire start_mat_add = scheduled_warp && (warp_pc == 32'h80000ed8) && (warp_num == 0); - wire end_mat_add = scheduled_warp && (warp_pc == 32'h80000fbc) && (warp_num == 0); -`DEBUG_END - endmodule \ No newline at end of file diff --git a/hw/rtl/VX_fpu_unit.v b/hw/rtl/VX_fpu_unit.v new file mode 100644 index 00000000..6e84c5e1 --- /dev/null +++ b/hw/rtl/VX_fpu_unit.v @@ -0,0 +1,140 @@ +`include "VX_define.vh" + +module VX_fpu_unit #( + parameter CORE_ID = 0 +) ( + // inputs + input wire clk, + input wire reset, + + // inputs + VX_fpu_req_if fpu_req_if, + + // outputs + VX_fpu_to_cmt_if fpu_commit_if +); + localparam FPUQ_BITS = `LOG2UP(`FPUQ_SIZE); + + wire ready_in; + wire valid_out; + wire ready_out; + + wire [`NW_BITS-1:0] rsp_wid; + wire [`NUM_THREADS-1:0] rsp_tmask; + wire [31:0] rsp_PC; + wire [`NR_BITS-1:0] rsp_rd; + wire rsp_wb; + + wire has_fflags; + fflags_t [`NUM_THREADS-1:0] fflags; + wire [`NUM_THREADS-1:0][31:0] result; + + wire [FPUQ_BITS-1:0] tag_in, tag_out; + wire fpuq_full; + + wire fpuq_push = fpu_req_if.valid && fpu_req_if.ready; + wire fpuq_pop = valid_out && ready_out; + + VX_cam_buffer #( + .DATAW (`NW_BITS + `NUM_THREADS + 32 + `NR_BITS + 1), + .SIZE (`FPUQ_SIZE) + ) fpu_cam ( + .clk (clk), + .reset (reset), + .acquire_slot (fpuq_push), + .write_addr (tag_in), + .read_addr (tag_out), + .release_addr (tag_out), + .write_data ({fpu_req_if.wid, fpu_req_if.tmask, fpu_req_if.PC, fpu_req_if.rd, fpu_req_if.wb}), + .read_data ({rsp_wid, rsp_tmask, rsp_PC, rsp_rd, rsp_wb}), + .release_slot (fpuq_pop), + .full (fpuq_full) + ); + + wire valid_in = fpu_req_if.valid && ~fpuq_full; + + // can accept new request? + assign fpu_req_if.ready = ready_in && ~fpuq_full; + +`ifdef FPU_FAST + + VX_fp_fpga #( + .TAGW (FPUQ_BITS) + ) fp_core ( + .clk (clk), + .reset (reset), + + .valid_in (valid_in), + .ready_in (ready_in), + + .tag_in (tag_in), + + .op_type (fpu_req_if.op_type), + .frm (fpu_req_if.frm), + + .dataa (fpu_req_if.rs1_data), + .datab (fpu_req_if.rs2_data), + .datac (fpu_req_if.rs3_data), + .result (result), + + .has_fflags (has_fflags), + .fflags (fflags), + + .tag_out (tag_out), + + .ready_out (ready_out), + .valid_out (valid_out) + ); + +`else + + VX_fpnew #( + .FMULADD (1), + .FDIVSQRT (1), + .FNONCOMP (1), + .FCONV (1), + .TAGW (FPUQ_BITS) + ) fp_core ( + .clk (clk), + .reset (reset), + + .valid_in (valid_in), + .ready_in (ready_in), + + .tag_in (tag_in), + + .op_type (fpu_req_if.op_type), + .frm (fpu_req_if.frm), + + .dataa (fpu_req_if.rs1_data), + .datab (fpu_req_if.rs2_data), + .datac (fpu_req_if.rs3_data), + .result (result), + + .has_fflags (has_fflags), + .fflags (fflags), + + .tag_out (tag_out), + + .ready_out (ready_out), + .valid_out (valid_out) + ); + +`endif + + wire stall_out = ~fpu_commit_if.ready && fpu_commit_if.valid; + + VX_generic_register #( + .N(1 + `NW_BITS + `NUM_THREADS + 32 + `NR_BITS + 1 + (`NUM_THREADS * 32) + 1 + (`NUM_THREADS * `FFG_BITS)) + ) fpu_reg ( + .clk (clk), + .reset (reset), + .stall (stall_out), + .flush (1'b0), + .in ({valid_out, rsp_wid, rsp_tmask, rsp_PC, rsp_rd, rsp_wb, result, has_fflags, fflags}), + .out ({fpu_commit_if.valid, fpu_commit_if.wid, fpu_commit_if.tmask, fpu_commit_if.PC, fpu_commit_if.rd, fpu_commit_if.wb, fpu_commit_if.data, fpu_commit_if.has_fflags, fpu_commit_if.fflags}) + ); + + assign ready_out = ~stall_out; + +endmodule \ No newline at end of file diff --git a/hw/rtl/VX_front_end.v b/hw/rtl/VX_front_end.v deleted file mode 100644 index 8ceba8df..00000000 --- a/hw/rtl/VX_front_end.v +++ /dev/null @@ -1,116 +0,0 @@ -`include "VX_define.vh" - -module VX_front_end #( - parameter CORE_ID = 0 -) ( - `SCOPE_SIGNALS_ISTAGE_IO - - input wire clk, - input wire reset, - - input wire schedule_delay, - - VX_warp_ctl_if warp_ctl_if, - - VX_cache_core_rsp_if icache_rsp_if, - VX_cache_core_req_if icache_req_if, - - VX_jal_rsp_if jal_rsp_if, - VX_branch_rsp_if branch_rsp_if, - - VX_backend_req_if bckE_req_if, - output wire busy -); - - VX_inst_meta_if fe_inst_meta_fi(); - VX_inst_meta_if fe_inst_meta_fi2(); - VX_inst_meta_if fe_inst_meta_id(); - - VX_backend_req_if frE_to_bckE_req_if(); - VX_inst_meta_if fd_inst_meta_de(); - - wire total_freeze = schedule_delay; - wire icache_stage_delay; - - wire[`NW_BITS-1:0] icache_stage_wid; - wire icache_stage_response; - - VX_wstall_if wstall_if(); - VX_join_if join_if(); - - VX_fetch fetch ( - .clk (clk), - .reset (reset), - .icache_stage_wid (icache_stage_wid), - .icache_stage_response(icache_stage_response), - .wstall_if (wstall_if), - .join_if (join_if), - .schedule_delay (schedule_delay), - .jal_rsp_if (jal_rsp_if), - .warp_ctl_if (warp_ctl_if), - .icache_stage_delay (icache_stage_delay), - .branch_rsp_if (branch_rsp_if), - .busy (busy), - .fe_inst_meta_fi (fe_inst_meta_fi) - ); - - VX_generic_register #( - .N(64+`NW_BITS-1+1+`NUM_THREADS) - ) f_d_reg ( - .clk (clk), - .reset (reset), - .stall (icache_stage_delay), - .flush (1'b0), - .in ({fe_inst_meta_fi.instruction, fe_inst_meta_fi.curr_PC, fe_inst_meta_fi.warp_num, fe_inst_meta_fi.valid}), - .out ({fe_inst_meta_fi2.instruction, fe_inst_meta_fi2.curr_PC, fe_inst_meta_fi2.warp_num, fe_inst_meta_fi2.valid}) - ); - - VX_icache_stage #( - .CORE_ID(CORE_ID) - ) icache_stage ( - `SCOPE_SIGNALS_ISTAGE_BIND - - .clk (clk), - .reset (reset), - .total_freeze (total_freeze), - .icache_stage_delay (icache_stage_delay), - .icache_stage_response(icache_stage_response), - .icache_stage_wid (icache_stage_wid), - .fe_inst_meta_fi (fe_inst_meta_fi2), - .fe_inst_meta_id (fe_inst_meta_id), - .icache_rsp_if (icache_rsp_if), - .icache_req_if (icache_req_if) - ); - - VX_generic_register #( - .N(64 + `NW_BITS-1 + 1 + `NUM_THREADS) - ) i_d_reg ( - .clk (clk), - .reset (reset), - .stall (total_freeze), - .flush (1'b0), - .in ({fe_inst_meta_id.instruction, fe_inst_meta_id.curr_PC, fe_inst_meta_id.warp_num, fe_inst_meta_id.valid}), - .out ({fd_inst_meta_de.instruction, fd_inst_meta_de.curr_PC, fd_inst_meta_de.warp_num, fd_inst_meta_de.valid}) - ); - - VX_decode decode ( - .fd_inst_meta_de (fd_inst_meta_de), - .frE_to_bckE_req_if (frE_to_bckE_req_if), - .wstall_if (wstall_if), - .join_if (join_if) - ); - - VX_generic_register #( - .N(233 + `NW_BITS-1 + 1 + `NUM_THREADS) - ) d_e_reg ( - .clk (clk), - .reset (reset), - .stall (total_freeze), - .flush (1'b0), - .in ({frE_to_bckE_req_if.csr_addr, frE_to_bckE_req_if.is_jal, frE_to_bckE_req_if.is_etype, frE_to_bckE_req_if.is_csr, frE_to_bckE_req_if.csr_immed, frE_to_bckE_req_if.csr_mask, frE_to_bckE_req_if.rd, frE_to_bckE_req_if.rs1, frE_to_bckE_req_if.rs2, frE_to_bckE_req_if.alu_op, frE_to_bckE_req_if.wb, frE_to_bckE_req_if.rs2_src, frE_to_bckE_req_if.itype_immed, frE_to_bckE_req_if.mem_read, frE_to_bckE_req_if.mem_write, frE_to_bckE_req_if.branch_type, frE_to_bckE_req_if.upper_immed, frE_to_bckE_req_if.curr_PC, frE_to_bckE_req_if.jal, frE_to_bckE_req_if.jal_offset, frE_to_bckE_req_if.next_PC, frE_to_bckE_req_if.valid, frE_to_bckE_req_if.warp_num, frE_to_bckE_req_if.is_wspawn, frE_to_bckE_req_if.is_tmc, frE_to_bckE_req_if.is_split, frE_to_bckE_req_if.is_barrier}), - .out ({bckE_req_if.csr_addr , bckE_req_if.is_jal , bckE_req_if.is_etype ,bckE_req_if.is_csr , bckE_req_if.csr_immed , bckE_req_if.csr_mask , bckE_req_if.rd , bckE_req_if.rs1 , bckE_req_if.rs2 , bckE_req_if.alu_op , bckE_req_if.wb , bckE_req_if.rs2_src , bckE_req_if.itype_immed , bckE_req_if.mem_read , bckE_req_if.mem_write , bckE_req_if.branch_type , bckE_req_if.upper_immed , bckE_req_if.curr_PC , bckE_req_if.jal , bckE_req_if.jal_offset , bckE_req_if.next_PC , bckE_req_if.valid , bckE_req_if.warp_num , bckE_req_if.is_wspawn , bckE_req_if.is_tmc , bckE_req_if.is_split , bckE_req_if.is_barrier }) - ); - -endmodule - - diff --git a/hw/rtl/VX_gpr_bypass.v b/hw/rtl/VX_gpr_bypass.v new file mode 100644 index 00000000..65d13339 --- /dev/null +++ b/hw/rtl/VX_gpr_bypass.v @@ -0,0 +1,72 @@ +`include "VX_platform.vh" + +module VX_gpr_bypass #( + parameter DATAW = 1, + parameter PASSTHRU = 0 +) ( + input wire clk, + input wire reset, + input wire push, + input wire pop, + input wire [DATAW-1:0] data_in, + output wire [DATAW-1:0] data_out +); + if (PASSTHRU) begin + reg delayed_push; + + always @(posedge clk) begin + if (reset) begin + delayed_push <= 0; + end else begin + delayed_push <= push; + assert(!delayed_push || pop); + end + end + + assign data_out = data_in; + + end else begin + + reg [DATAW-1:0] buffer, buffer2; + reg use_buffer, use_buffer2; + reg delayed_push; + + always @(posedge clk) begin + if (reset) begin + delayed_push <= 0; + use_buffer <= 0; + use_buffer2 <= 0; + buffer <= 0; + buffer2 <= 0; + end else begin + delayed_push <= push; + assert(!use_buffer2 || use_buffer); + if (pop) begin + if (use_buffer) begin + buffer <= buffer2; + use_buffer <= use_buffer2; + use_buffer2 <= 0; + end + end + if (delayed_push) begin + if (use_buffer) begin + assert(!use_buffer2); // queue full! + if (pop) begin + buffer <= data_in; + end else begin + buffer2 <= data_in; + use_buffer2 <= 1; + end + use_buffer <= 1; + end else if (!pop) begin + buffer <= data_in; + use_buffer <= 1; + end + end + end + end + + assign data_out = use_buffer ? buffer : data_in; + end + +endmodule \ No newline at end of file diff --git a/hw/rtl/VX_gpr_fp_ctrl.v b/hw/rtl/VX_gpr_fp_ctrl.v new file mode 100644 index 00000000..1d7224ab --- /dev/null +++ b/hw/rtl/VX_gpr_fp_ctrl.v @@ -0,0 +1,74 @@ +`include "VX_define.vh" + +// control module to support multi-cycle read for fp register + +module VX_gpr_fp_ctrl ( + input wire clk, + input wire reset, + + input wire [`NUM_THREADS-1:0][31:0] rs1_data, + input wire [`NUM_THREADS-1:0][31:0] rs2_data, + VX_gpr_req_if gpr_req_if, + + // outputs + output wire [`NW_BITS+`NR_BITS-1:0] raddr1, + VX_gpr_rsp_if gpr_rsp_if +); + + reg [`NUM_THREADS-1:0][31:0] rsp_rs1_data, rsp_rs2_data, rsp_rs3_data; + reg rsp_valid; + reg [31:0] rsp_pc; + reg [`NW_BITS-1:0] rsp_wid; + reg read_rs1; + + wire rs3_delay = gpr_req_if.valid && gpr_req_if.use_rs3 && read_rs1; + wire read_fire = gpr_req_if.valid && gpr_rsp_if.ready; + + always @(posedge clk) begin + if (reset) begin + rsp_valid <= 0; + rsp_pc <= 0; + rsp_rs1_data <= 0; + rsp_rs2_data <= 0; + rsp_rs3_data <= 0; + rsp_wid <= 0; + read_rs1 <= 1; + end else begin + if (rs3_delay) begin + read_rs1 <= 0; + rsp_wid <= gpr_req_if.wid; + end else if (read_fire) begin + read_rs1 <= 1; + end + + rsp_valid <= gpr_req_if.valid; + rsp_wid <= gpr_req_if.wid; + rsp_pc <= gpr_req_if.PC; + + if (read_rs1) begin + rsp_rs1_data <= rs1_data; + end + rsp_rs2_data <= rs2_data; + rsp_rs3_data <= rs1_data; + + assert(read_rs1 || rsp_wid == gpr_req_if.wid); + end + end + + always @(posedge clk) begin + + end + + // outputs + wire [`NR_BITS-1:0] rs1 = read_rs1 ? gpr_req_if.rs1 : gpr_req_if.rs3; + assign raddr1 = {gpr_req_if.wid, rs1}; + assign gpr_req_if.ready = ~rs3_delay; + + assign gpr_rsp_if.valid = rsp_valid; + assign gpr_rsp_if.wid = rsp_wid; + assign gpr_rsp_if.PC = rsp_pc; + assign gpr_rsp_if.rs1_data = rsp_rs1_data; + assign gpr_rsp_if.rs2_data = rsp_rs2_data; + assign gpr_rsp_if.rs3_data = rsp_rs3_data; + +endmodule \ No newline at end of file diff --git a/hw/rtl/VX_gpr_ram.v b/hw/rtl/VX_gpr_ram.v index d30b6a91..8f1b4483 100644 --- a/hw/rtl/VX_gpr_ram.v +++ b/hw/rtl/VX_gpr_ram.v @@ -1,35 +1,30 @@ `include "VX_define.vh" module VX_gpr_ram ( - input wire clk, - input wire reset, - input wire write_ce, - VX_gpr_read_if gpr_read_if, - VX_wb_if writeback_if, + input wire clk, + input wire [`NUM_THREADS-1:0] we, + input wire [`NW_BITS+`NR_BITS-1:0] waddr, + input wire [`NUM_THREADS-1:0][31:0] wdata, + input wire [`NW_BITS+`NR_BITS-1:0] rs1, + input wire [`NW_BITS+`NR_BITS-1:0] rs2, + output wire [`NUM_THREADS-1:0][31:0] rs1_data, + output wire [`NUM_THREADS-1:0][31:0] rs2_data +); + `ifndef ASIC - output wire [`NUM_THREADS-1:0][`NUM_GPRS-1:0] a_reg_data, - output wire [`NUM_THREADS-1:0][`NUM_GPRS-1:0] b_reg_data -); - wire [`NUM_THREADS-1:0][`NUM_GPRS-1:0] a_reg_data_unqual; - wire [`NUM_THREADS-1:0][`NUM_GPRS-1:0] b_reg_data_unqual; + reg [`NUM_THREADS-1:0][3:0][7:0] ram [(`NUM_WARPS * `NUM_REGS)-1:0]; - assign a_reg_data = (gpr_read_if.rs1 != 0) ? a_reg_data_unqual : 0; - assign b_reg_data = (gpr_read_if.rs2 != 0) ? b_reg_data_unqual : 0; - - wire [`NUM_THREADS-1:0] write_enable = writeback_if.valid & {`NUM_THREADS{write_ce && (writeback_if.wb != 0)}}; - - `ifndef ASIC - `UNUSED_VAR(reset) - - reg [`NUM_THREADS-1:0][3:0][7:0] ram[31:0]; - - wire [4:0] waddr = writeback_if.rd; - wire [`NUM_THREADS-1:0][31:0] wdata = writeback_if.data; + initial begin // initialize ram: set r0 = 0 + for (integer j = 0; j < `NUM_WARPS; j++) begin + for (integer i = 0; i < `NUM_REGS; i++) begin + ram[j * `NUM_REGS + i] = (i == 0) ? {`NUM_THREADS{32'h0}} : {`NUM_THREADS{32'hx}}; + end + end + end - genvar i; - for (i = 0; i < `NUM_THREADS; i++) begin - always @(posedge clk) begin - if (write_enable[i]) begin + always @(posedge clk) begin + for (integer i = 0; i < `NUM_THREADS; i++) begin + if (we[i]) begin ram[waddr][i][0] <= wdata[i][07:00]; ram[waddr][i][1] <= wdata[i][15:08]; ram[waddr][i][2] <= wdata[i][23:16]; @@ -38,44 +33,36 @@ module VX_gpr_ram ( end end - assign a_reg_data_unqual = ram[gpr_read_if.rs1]; - assign b_reg_data_unqual = ram[gpr_read_if.rs2]; + assign rs1_data = ram[rs1]; + assign rs2_data = ram[rs2]; `else - wire going_to_write = write_enable & (| writeback_if.wb_valid); - wire [`NUM_THREADS-1:0][`NUM_GPRS-1:0] write_bit_mask; + wire [`NUM_THREADS-1:0][31:0] write_bit_mask; - genvar i; - for (i = 0; i < `NUM_THREADS; i++) begin - wire local_write = write_enable & writeback_if.wb_valid[i]; - assign write_bit_mask[i] = {`NUM_GPRS{~local_write}}; + for (integer i = 0; i < `NUM_THREADS; i++) begin + assign write_bit_mask[i] = {32{~we[i]}}; end wire cenb = 0; wire cena_1 = 0; wire cena_2 = 0; - wire [`NUM_THREADS-1:0][`NUM_GPRS-1:0] tmp_a; - wire [`NUM_THREADS-1:0][`NUM_GPRS-1:0] tmp_b; + wire [`NUM_THREADS-1:0][31:0] tmp_a; + wire [`NUM_THREADS-1:0][31:0] tmp_b; `ifndef SYNTHESIS - genvar j; - for (i = 0; i < `NUM_THREADS; i++) begin - for (j = 0; j < `NUM_GPRS; j++) begin - assign a_reg_data_unqual[i][j] = ((tmp_a[i][j] === 1'dx) || cena_1) ? 1'b0 : tmp_a[i][j]; - assign b_reg_data_unqual[i][j] = ((tmp_b[i][j] === 1'dx) || cena_2) ? 1'b0 : tmp_b[i][j]; + for (integer i = 0; i < `NUM_THREADS; i++) begin + for (integer j = 0; j < 32; j++) begin + assign rs1_data[i][j] = ((tmp_a[i][j] === 1'dx) || cena_1) ? 1'b0 : tmp_a[i][j]; + assign rs2_data[i][j] = ((tmp_b[i][j] === 1'dx) || cena_2) ? 1'b0 : tmp_b[i][j]; end end `else - assign a_reg_data_unqual = tmp_a; - assign b_reg_data_unqual = tmp_b; + assign rs1_data = tmp_a; + assign rs2_data = tmp_b; `endif - - wire [`NUM_THREADS-1:0][`NUM_GPRS-1:0] to_write = writeback_if.write_data; - - for (i = 0; i < 'NT; i=i+4) - begin + for (integer i = 0; i < 'NT; i=i+4) begin `IGNORE_WARNINGS_BEGIN rf2_32x128_wm1 first_ram ( .CENYA(), @@ -88,12 +75,12 @@ module VX_gpr_ram ( .SOB(), .CLKA(clk), .CENA(cena_1), - .AA(gpr_read_if.rs1[(i+3):(i)]), + .AA(rs1[(i+3):(i)]), .CLKB(clk), .CENB(cenb), .WENB(write_bit_mask[(i+3):(i)]), - .AB(writeback_if.rd[(i+3):(i)]), - .DB(to_write[(i+3):(i)]), + .AB(waddr[(i+3):(i)]), + .DB(wdata[(i+3):(i)]), .EMAA(3'b011), .EMASA(1'b0), .EMAB(3'b011), @@ -125,12 +112,12 @@ module VX_gpr_ram ( .SOB(), .CLKA(clk), .CENA(cena_2), - .AA(gpr_read_if.rs2[(i+3):(i)]), + .AA(rs2[(i+3):(i)]), .CLKB(clk), .CENB(cenb), .WENB(write_bit_mask[(i+3):(i)]), - .AB(writeback_if.rd[(i+3):(i)]), - .DB(to_write[(i+3):(i)]), + .AB(waddr[(i+3):(i)]), + .DB(wdata[(i+3):(i)]), .EMAA(3'b011), .EMASA(1'b0), .EMAB(3'b011), diff --git a/hw/rtl/VX_gpr_stage.v b/hw/rtl/VX_gpr_stage.v index e0f5f865..129da4c0 100644 --- a/hw/rtl/VX_gpr_stage.v +++ b/hw/rtl/VX_gpr_stage.v @@ -1,226 +1,84 @@ `include "VX_define.vh" -module VX_gpr_stage ( - input wire clk, - input wire reset, - input wire schedule_delay, +module VX_gpr_stage #( + parameter CORE_ID = 0 +) ( + input wire clk, + input wire reset, - input wire memory_delay, - input wire exec_delay, - input wire stall_gpr_csr, - output wire delay, + // inputs + VX_writeback_if writeback_if, + VX_gpr_req_if gpr_req_if, - // decodee inputs - VX_backend_req_if bckE_req_if, - - // WriteBack inputs - VX_wb_if writeback_if, - - // Outputs - VX_exec_unit_req_if exec_unit_req_if, - VX_lsu_req_if lsu_req_if, - VX_gpu_inst_req_if gpu_inst_req_if, - VX_csr_req_if csr_req_if + // outputs + VX_gpr_rsp_if gpr_rsp_if ); -`DEBUG_BEGIN - wire[31:0] curr_PC = bckE_req_if.curr_PC; - wire[2:0] branchType = bckE_req_if.branch_type; - wire is_store = (bckE_req_if.mem_write != `BYTE_EN_NO); - wire is_load = (bckE_req_if.mem_read != `BYTE_EN_NO); - wire is_jal = bckE_req_if.is_jal; -`DEBUG_END + `UNUSED_VAR (reset) - assign csr_req_if.is_io = 1'b0; // GPR only issues csr requests coming from core + wire [`NUM_THREADS-1:0][31:0] rs1_data; + wire [`NUM_THREADS-1:0][31:0] rs2_data; + wire [`NW_BITS+`NR_BITS-1:0] raddr1; - VX_gpr_read_if gpr_read_if(); - assign gpr_read_if.rs1 = bckE_req_if.rs1; - assign gpr_read_if.rs2 = bckE_req_if.rs2; - assign gpr_read_if.warp_num = bckE_req_if.warp_num; + VX_gpr_ram gpr_ram ( + .clk (clk), + .we ({`NUM_THREADS{writeback_if.valid}} & writeback_if.tmask), + .waddr ({writeback_if.wid, writeback_if.rd}), + .wdata (writeback_if.data), + .rs1 (raddr1), + .rs2 ({gpr_req_if.wid, gpr_req_if.rs2}), + .rs1_data (rs1_data), + .rs2_data (rs2_data) + ); -`ifndef ASIC - assign gpr_read_if.is_jal = bckE_req_if.is_jal; - assign gpr_read_if.curr_PC = bckE_req_if.curr_PC; -`else - assign gpr_read_if.is_jal = exec_unit_req_if.is_jal; - assign gpr_read_if.curr_PC = exec_unit_req_if.curr_PC; +`ifdef EXT_F_ENABLE + VX_gpr_fp_ctrl VX_gpr_fp_ctrl ( + .clk (clk), + .reset (reset), + .rs1_data (rs1_data), + .rs2_data (rs2_data), + .raddr1 (raddr1), + .gpr_req_if (gpr_req_if), + .gpr_rsp_if (gpr_rsp_if) + ); +`else + reg [`NUM_THREADS-1:0][31:0] rsp_rs1_data, rsp_rs2_data; + reg rsp_valid; + reg [`NW_BITS-1:0] rsp_wid; + reg [31:0] rsp_pc; + + always @(posedge clk) begin + if (reset) begin + rsp_valid <= 0; + rsp_wid <= 0; + rsp_pc <= 0; + rsp_rs1_data <= 0; + rsp_rs2_data <= 0; + end else begin + rsp_valid <= gpr_req_if.valid; + rsp_wid <= gpr_req_if.wid; + rsp_pc <= gpr_req_if.PC; + rsp_rs1_data <= rs1_data; + rsp_rs2_data <= rs2_data; + end + end + + assign raddr1 = {gpr_req_if.wid, gpr_req_if.rs1}; + + assign gpr_req_if.ready = 1; + + assign gpr_rsp_if.valid = rsp_valid; + assign gpr_rsp_if.wid = rsp_wid; + assign gpr_rsp_if.PC = rsp_pc; + assign gpr_rsp_if.rs1_data = rsp_rs1_data; + assign gpr_rsp_if.rs2_data = rsp_rs2_data; + assign gpr_rsp_if.rs3_data = 0; + + `UNUSED_VAR (gpr_req_if.valid); + `UNUSED_VAR (gpr_req_if.rs3); + `UNUSED_VAR (gpr_req_if.use_rs3); + `UNUSED_VAR (gpr_rsp_if.ready); `endif - VX_gpr_wrapper grp_wrapper ( - .clk (clk), - .reset (reset), - .writeback_if (writeback_if), - .gpr_read_if (gpr_read_if) - ); + assign writeback_if.ready = 1'b1; - // Outputs - VX_exec_unit_req_if exec_unit_req_temp_if(); - VX_lsu_req_if lsu_req_temp_if(); - VX_gpu_inst_req_if gpu_inst_req_temp_if(); - VX_csr_req_if csr_req_temp_if(); - - VX_inst_multiplex inst_mult( - .bckE_req_if (bckE_req_if), - .gpr_read_if (gpr_read_if), - .exec_unit_req_if (exec_unit_req_temp_if), - .lsu_req_if (lsu_req_temp_if), - .gpu_inst_req_if (gpu_inst_req_temp_if), - .csr_req_if (csr_req_temp_if) - ); - -`DEBUG_BEGIN - wire is_lsu = (| lsu_req_temp_if.valid); -`DEBUG_END - wire stall_rest = 0; - wire flush_rest = schedule_delay; - - wire stall_lsu = memory_delay; - wire flush_lsu = schedule_delay && !stall_lsu; - - wire stall_exec = exec_delay; - wire flush_exec = schedule_delay && !stall_exec; - - wire stall_csr = stall_gpr_csr && bckE_req_if.is_csr && (| bckE_req_if.valid); - - assign delay = stall_lsu || stall_exec || stall_csr; - -`ifdef ASIC - wire delayed_lsu_last_cycle; - - VX_generic_register #( - .N(1) - ) delayed_reg ( - .clk (clk), - .reset (reset), - .stall (stall_rest), - .flush (stall_rest), - .in (stall_lsu), - .out (delayed_lsu_last_cycle), - `UNUSED_PIN (size) - ); - - wire [`NUM_THREADS-1:0][31:0] temp_store_data; - wire [`NUM_THREADS-1:0][31:0] temp_base_addr; // A reg data - - wire [`NUM_THREADS-1:0][31:0] real_store_data; - wire [`NUM_THREADS-1:0][31:0] real_base_addr; // A reg data - - wire store_curr_real = !delayed_lsu_last_cycle && stall_lsu; - - VX_generic_register #( - .N(`NUM_THREADS*32*2) - ) lsu_data ( - .clk (clk), - .reset (reset), - .stall (!store_curr_real), - .flush (stall_rest), - .in ({real_store_data, real_base_addr}), - .out ({temp_store_data, temp_base_addr}) - ); - - assign real_store_data = lsu_req_temp_if.store_data; - assign real_base_addr = lsu_req_temp_if.base_addr; - - assign lsu_req_if.store_data = (delayed_lsu_last_cycle) ? temp_store_data : real_store_data; - assign lsu_req_if.base_addr = (delayed_lsu_last_cycle) ? temp_base_addr : real_base_addr; - - VX_generic_register #( - .N(77 + `NW_BITS-1 + 1 + (`NUM_THREADS)) - ) lsu_reg ( - .clk (clk), - .reset (reset), - .stall (stall_lsu), - .flush (flush_lsu), - .in ({lsu_req_temp_if.valid, lsu_req_temp_if.curr_PC, lsu_req_temp_if.warp_num, lsu_req_temp_if.offset, lsu_req_temp_if.mem_read, lsu_req_temp_if.mem_write, lsu_req_temp_if.rd, lsu_req_temp_if.wb}), - .out ({lsu_req_if.valid , lsu_req_if.curr_PC ,lsu_req_if.warp_num , lsu_req_if.offset , lsu_req_if.mem_read , lsu_req_if.mem_write , lsu_req_if.rd , lsu_req_if.wb }) - ); - - VX_generic_register #( - .N(224 + `NW_BITS-1 + 1 + (`NUM_THREADS)) - ) exec_unit_reg ( - .clk (clk), - .reset (reset), - .stall (stall_exec), - .flush (flush_exec), - .in ({exec_unit_req_temp_if.valid, exec_unit_req_temp_if.warp_num, exec_unit_req_temp_if.curr_PC, exec_unit_req_temp_if.next_PC, exec_unit_req_temp_if.rd, exec_unit_req_temp_if.wb, exec_unit_req_temp_if.alu_op, exec_unit_req_temp_if.rs1, exec_unit_req_temp_if.rs2, exec_unit_req_temp_if.rs2_src, exec_unit_req_temp_if.itype_immed, exec_unit_req_temp_if.upper_immed, exec_unit_req_temp_if.branch_type, exec_unit_req_temp_if.is_jal, exec_unit_req_temp_if.jal, exec_unit_req_temp_if.jal_offset, exec_unit_req_temp_if.is_etype, exec_unit_req_temp_if.wspawn, exec_unit_req_temp_if.is_csr, exec_unit_req_temp_if.csr_addr, exec_unit_req_temp_if.csr_immed, exec_unit_req_temp_if.csr_mask}), - .out ({exec_unit_req_if.valid , exec_unit_req_if.warp_num , exec_unit_req_if.curr_PC , exec_unit_req_if.next_PC , exec_unit_req_if.rd , exec_unit_req_if.wb , exec_unit_req_if.alu_op , exec_unit_req_if.rs1 , exec_unit_req_if.rs2 , exec_unit_req_if.rs2_src , exec_unit_req_if.itype_immed , exec_unit_req_if.upper_immed , exec_unit_req_if.branch_type , exec_unit_req_if.is_jal , exec_unit_req_if.jal , exec_unit_req_if.jal_offset , exec_unit_req_if.is_etype , exec_unit_req_if.wspawn , exec_unit_req_if.is_csr , exec_unit_req_if.csr_addr , exec_unit_req_if.csr_immed , exec_unit_req_if.csr_mask }) - ); - - assign exec_unit_req_if.a_reg_data = real_base_addr; - assign exec_unit_req_if.b_reg_data = real_store_data; - - VX_generic_register #( - .N(36 + `NW_BITS-1 + 1 + (`NUM_THREADS)) - ) gpu_inst_reg ( - .clk (clk), - .reset (reset), - .stall (stall_rest), - .flush (flush_rest), - .in ({gpu_inst_req_temp_if.valid, gpu_inst_req_temp_if.warp_num, gpu_inst_req_temp_if.is_wspawn, gpu_inst_req_temp_if.is_tmc, gpu_inst_req_temp_if.is_split, gpu_inst_req_temp_if.is_barrier, gpu_inst_req_temp_if.next_PC}), - .out ({gpu_inst_req_if.valid , gpu_inst_req_if.warp_num , gpu_inst_req_if.is_wspawn , gpu_inst_req_if.is_tmc , gpu_inst_req_if.is_split , gpu_inst_req_if.is_barrier , gpu_inst_req_if.next_PC }) - ); - - assign gpu_inst_req_if.a_reg_data = real_base_addr; - assign gpu_inst_req_if.rd2 = real_store_data; - - VX_generic_register #( - .N(`NW_BITS-1 + 1 + `NUM_THREADS + 58) - ) csr_reg ( - .clk (clk), - .reset (reset), - .stall (stall_gpr_csr), - .flush (flush_rest), - .in ({csr_req_temp_if.valid, csr_req_temp_if.warp_num, csr_req_temp_if.rd, csr_req_temp_if.wb, csr_req_temp_if.alu_op, csr_req_temp_if.is_csr, csr_req_temp_if.csr_addr, csr_req_temp_if.csr_immed, csr_req_temp_if.csr_mask}), - .out ({csr_req_if.valid , csr_req_if.warp_num , csr_req_if.rd , csr_req_if.wb , csr_req_if.alu_op , csr_req_if.is_csr , csr_req_if.csr_addr , csr_req_if.csr_immed , csr_req_if.csr_mask }) - ); - - -`else - - // 341 - VX_generic_register #( - .N(77 + `NW_BITS-1 + 1 + 65*(`NUM_THREADS)) - ) lsu_reg ( - .clk (clk), - .reset (reset), - .stall (stall_lsu), - .flush (flush_lsu), - .in ({lsu_req_temp_if.valid, lsu_req_temp_if.curr_PC, lsu_req_temp_if.warp_num, lsu_req_temp_if.store_data, lsu_req_temp_if.base_addr, lsu_req_temp_if.offset, lsu_req_temp_if.mem_read, lsu_req_temp_if.mem_write, lsu_req_temp_if.rd, lsu_req_temp_if.wb}), - .out ({lsu_req_if.valid , lsu_req_if.curr_PC , lsu_req_if.warp_num , lsu_req_if.store_data , lsu_req_if.base_addr , lsu_req_if.offset , lsu_req_if.mem_read , lsu_req_if.mem_write , lsu_req_if.rd , lsu_req_if.wb }) - ); - - VX_generic_register #( - .N(224 + `NW_BITS-1 + 1 + 65*(`NUM_THREADS)) - ) exec_unit_reg ( - .clk (clk), - .reset (reset), - .stall (stall_exec), - .flush (flush_exec), - .in ({exec_unit_req_temp_if.valid, exec_unit_req_temp_if.warp_num, exec_unit_req_temp_if.curr_PC, exec_unit_req_temp_if.next_PC, exec_unit_req_temp_if.rd, exec_unit_req_temp_if.wb, exec_unit_req_temp_if.a_reg_data, exec_unit_req_temp_if.b_reg_data, exec_unit_req_temp_if.alu_op, exec_unit_req_temp_if.rs1, exec_unit_req_temp_if.rs2, exec_unit_req_temp_if.rs2_src, exec_unit_req_temp_if.itype_immed, exec_unit_req_temp_if.upper_immed, exec_unit_req_temp_if.branch_type, exec_unit_req_temp_if.is_jal, exec_unit_req_temp_if.jal, exec_unit_req_temp_if.jal_offset, exec_unit_req_temp_if.is_etype, exec_unit_req_temp_if.wspawn, exec_unit_req_temp_if.is_csr, exec_unit_req_temp_if.csr_addr, exec_unit_req_temp_if.csr_immed, exec_unit_req_temp_if.csr_mask}), - .out ({exec_unit_req_if.valid , exec_unit_req_if.warp_num , exec_unit_req_if.curr_PC , exec_unit_req_if.next_PC , exec_unit_req_if.rd , exec_unit_req_if.wb , exec_unit_req_if.a_reg_data , exec_unit_req_if.b_reg_data , exec_unit_req_if.alu_op , exec_unit_req_if.rs1 , exec_unit_req_if.rs2 , exec_unit_req_if.rs2_src , exec_unit_req_if.itype_immed , exec_unit_req_if.upper_immed , exec_unit_req_if.branch_type , exec_unit_req_if.is_jal , exec_unit_req_if.jal , exec_unit_req_if.jal_offset , exec_unit_req_if.is_etype , exec_unit_req_if.wspawn , exec_unit_req_if.is_csr , exec_unit_req_if.csr_addr , exec_unit_req_if.csr_immed , exec_unit_req_if.csr_mask }) - ); - - VX_generic_register #( - .N(68 + `NW_BITS-1 + 1 + 33*(`NUM_THREADS)) - ) gpu_inst_reg ( - .clk (clk), - .reset (reset), - .stall (stall_rest), - .flush (flush_rest), - .in ({gpu_inst_req_temp_if.valid, gpu_inst_req_temp_if.warp_num, gpu_inst_req_temp_if.is_wspawn, gpu_inst_req_temp_if.is_tmc, gpu_inst_req_temp_if.is_split, gpu_inst_req_temp_if.is_barrier, gpu_inst_req_temp_if.next_PC, gpu_inst_req_temp_if.a_reg_data, gpu_inst_req_temp_if.rd2}), - .out ({gpu_inst_req_if.valid , gpu_inst_req_if.warp_num , gpu_inst_req_if.is_wspawn , gpu_inst_req_if.is_tmc , gpu_inst_req_if.is_split , gpu_inst_req_if.is_barrier , gpu_inst_req_if.next_PC , gpu_inst_req_if.a_reg_data , gpu_inst_req_if.rd2 }) - ); - - VX_generic_register #( - .N(`NW_BITS-1 + 1 + `NUM_THREADS + 58) - ) csr_reg ( - .clk (clk), - .reset (reset), - .stall (stall_gpr_csr), - .flush (flush_rest), - .in ({csr_req_temp_if.valid, csr_req_temp_if.warp_num, csr_req_temp_if.rd, csr_req_temp_if.wb, csr_req_temp_if.alu_op, csr_req_temp_if.is_csr, csr_req_temp_if.csr_addr, csr_req_temp_if.csr_immed, csr_req_temp_if.csr_mask}), - .out ({csr_req_if.valid , csr_req_if.warp_num , csr_req_if.rd , csr_req_if.wb , csr_req_if.alu_op , csr_req_if.is_csr , csr_req_if.csr_addr , csr_req_if.csr_immed , csr_req_if.csr_mask }) - ); - -`endif - -endmodule : VX_gpr_stage +endmodule diff --git a/hw/rtl/VX_gpr_wrapper.v b/hw/rtl/VX_gpr_wrapper.v deleted file mode 100644 index fe71f064..00000000 --- a/hw/rtl/VX_gpr_wrapper.v +++ /dev/null @@ -1,60 +0,0 @@ -`include "VX_define.vh" - -module VX_gpr_wrapper ( - input wire clk, - input wire reset, - VX_wb_if writeback_if, - VX_gpr_read_if gpr_read_if -); - wire [`NUM_WARPS-1:0][`NUM_THREADS-1:0][31:0] tmp_a_reg_data; - wire [`NUM_WARPS-1:0][`NUM_THREADS-1:0][31:0] tmp_b_reg_data; - wire [`NUM_THREADS-1:0][31:0] jal_data; - - genvar i; - generate - for (i = 0; i < `NUM_THREADS; i++) begin : jal_data_assign - assign jal_data[i] = gpr_read_if.curr_PC; - end - endgenerate - - `ifndef ASIC - assign gpr_read_if.a_reg_data = gpr_read_if.is_jal ? jal_data : tmp_a_reg_data[gpr_read_if.warp_num]; - assign gpr_read_if.b_reg_data = tmp_b_reg_data[gpr_read_if.warp_num]; - `else - - wire [`NW_BITS-1:0] old_warp_num; - - VX_generic_register #( - .N(`NW_BITS-1+1) - ) store_wn ( - .clk (clk), - .reset (reset), - .stall (1'b0), - .flush (1'b0), - .in (gpr_read_if.warp_num), - .out (old_warp_num) - ); - - assign gpr_read_if.a_reg_data = gpr_jal_if.is_jal ? jal_data : tmp_a_reg_data[old_warp_num]; - assign gpr_read_if.b_reg_data = tmp_b_reg_data[old_warp_num]; - - `endif - - generate - for (i = 0; i < `NUM_WARPS; i++) begin : warp_gprs - wire write_ce = (i == writeback_if.warp_num); - VX_gpr_ram gpr_ram( - .clk (clk), - .reset (reset), - .write_ce (write_ce), - .gpr_read_if (gpr_read_if), - .writeback_if (writeback_if), - .a_reg_data (tmp_a_reg_data[i]), - .b_reg_data (tmp_b_reg_data[i]) - ); - end - endgenerate - -endmodule - - diff --git a/hw/rtl/VX_gpu_inst.v b/hw/rtl/VX_gpu_inst.v deleted file mode 100644 index 5dbf3e57..00000000 --- a/hw/rtl/VX_gpu_inst.v +++ /dev/null @@ -1,88 +0,0 @@ -`include "VX_define.vh" - -module VX_gpu_inst ( - // Input - VX_gpu_inst_req_if gpu_inst_req_if, - - // Output - VX_warp_ctl_if warp_ctl_if -); - wire[`NUM_THREADS-1:0] curr_valids = gpu_inst_req_if.valid; - wire is_split = gpu_inst_req_if.is_split; - - wire[`NUM_THREADS-1:0] tmc_new_mask; - wire all_threads = `NUM_THREADS < gpu_inst_req_if.a_reg_data[0]; - - genvar i; - generate - for (i = 0; i < `NUM_THREADS; i++) begin : tmc_new_mask_init - assign tmc_new_mask[i] = all_threads ? 1 : i < gpu_inst_req_if.a_reg_data[0]; - end - endgenerate - - wire valid_inst = (| curr_valids); - - assign warp_ctl_if.warp_num = gpu_inst_req_if.warp_num; - assign warp_ctl_if.change_mask = gpu_inst_req_if.is_tmc && valid_inst; - assign warp_ctl_if.thread_mask = gpu_inst_req_if.is_tmc ? tmc_new_mask : 0; - - assign warp_ctl_if.whalt = warp_ctl_if.change_mask && (0 == warp_ctl_if.thread_mask); - - wire wspawn = gpu_inst_req_if.is_wspawn && valid_inst; - wire[31:0] wspawn_pc = gpu_inst_req_if.rd2; - wire all_active = `NUM_WARPS < gpu_inst_req_if.a_reg_data[0]; - wire[`NUM_WARPS-1:0] wspawn_new_active; - - generate - for (i = 0; i < `NUM_WARPS; i++) begin : wspawn_new_active_init - assign wspawn_new_active[i] = all_active ? 1 : i < gpu_inst_req_if.a_reg_data[0]; - end - endgenerate - - assign warp_ctl_if.is_barrier = gpu_inst_req_if.is_barrier && valid_inst; - assign warp_ctl_if.barrier_id = gpu_inst_req_if.a_reg_data[0]; - -`DEBUG_BEGIN - wire[31:0] num_warps_m1 = gpu_inst_req_if.rd2 - 1; -`DEBUG_END - - assign warp_ctl_if.num_warps = num_warps_m1[$clog2(`NUM_WARPS):0]; - - assign warp_ctl_if.wspawn = wspawn; - assign warp_ctl_if.wspawn_pc = wspawn_pc; - assign warp_ctl_if.wspawn_new_active = wspawn_new_active; - - wire[`NUM_THREADS-1:0] split_new_use_mask; - wire[`NUM_THREADS-1:0] split_new_later_mask; - - generate - for (i = 0; i < `NUM_THREADS; i++) begin : masks_init - wire curr_bool = (gpu_inst_req_if.a_reg_data[i] == 32'b1); - assign split_new_use_mask[i] = curr_valids[i] & (curr_bool); - assign split_new_later_mask[i] = curr_valids[i] & (!curr_bool); - end - endgenerate - - wire[$clog2(`NUM_THREADS):0] num_valids; - - VX_countones #( - .N(`NUM_THREADS) - ) valids_counter ( - .valids(curr_valids), - .count (num_valids) - ); - - // wire[`NW_BITS-1:0] num_valids = $countones(curr_valids); - - assign warp_ctl_if.is_split = is_split && (num_valids > 1); - assign warp_ctl_if.dont_split = warp_ctl_if.is_split && ((split_new_use_mask == 0) || (split_new_use_mask == {`NUM_THREADS{1'b1}})); - assign warp_ctl_if.split_new_mask = split_new_use_mask; - assign warp_ctl_if.split_later_mask = split_new_later_mask; - assign warp_ctl_if.split_save_pc = gpu_inst_req_if.next_PC; - assign warp_ctl_if.split_warp_num = gpu_inst_req_if.warp_num; - - // gpu_inst_req_if.is_wspawn - // gpu_inst_req_if.is_split - // gpu_inst_req_if.is_barrier - -endmodule \ No newline at end of file diff --git a/hw/rtl/VX_gpu_unit.v b/hw/rtl/VX_gpu_unit.v new file mode 100644 index 00000000..ac6550a3 --- /dev/null +++ b/hw/rtl/VX_gpu_unit.v @@ -0,0 +1,91 @@ +`include "VX_define.vh" + +module VX_gpu_unit #( + parameter CORE_ID = 0 +) ( + input wire clk, + input wire reset, + + // Input + VX_gpu_req_if gpu_req_if, + + // Output + VX_warp_ctl_if warp_ctl_if, + VX_exu_to_cmt_if gpu_commit_if +); + `UNUSED_VAR (clk) + `UNUSED_VAR (reset) + + gpu_tmc_t tmc; + gpu_wspawn_t wspawn; + gpu_barrier_t barrier; + gpu_split_t split; + + wire is_wspawn = (gpu_req_if.op_type == `GPU_WSPAWN); + wire is_tmc = (gpu_req_if.op_type == `GPU_TMC); + wire is_split = (gpu_req_if.op_type == `GPU_SPLIT); + wire is_bar = (gpu_req_if.op_type == `GPU_BAR); + + // tmc + + wire [`NUM_THREADS-1:0] tmc_new_mask; + for (genvar i = 0; i < `NUM_THREADS; i++) begin + assign tmc_new_mask[i] = (i < gpu_req_if.rs1_data[0]); + end + assign tmc.valid = is_tmc; + assign tmc.tmask = tmc_new_mask; + + // wspawn + + wire [31:0] wspawn_pc = gpu_req_if.rs2_data; + wire [`NUM_WARPS-1:0] wspawn_wmask; + for (genvar i = 0; i < `NUM_WARPS; i++) begin + assign wspawn_wmask[i] = (i < gpu_req_if.rs1_data[0]); + end + assign wspawn.valid = is_wspawn; + assign wspawn.wmask = wspawn_wmask; + assign wspawn.pc = wspawn_pc; + + // split + + wire [`NUM_THREADS-1:0] split_then_mask; + wire [`NUM_THREADS-1:0] split_else_mask; + + for (genvar i = 0; i < `NUM_THREADS; i++) begin + wire taken = gpu_req_if.rs1_data[i][0]; + assign split_then_mask[i] = gpu_req_if.tmask[i] & taken; + assign split_else_mask[i] = gpu_req_if.tmask[i] & ~taken; + end + + assign split.valid = is_split; + assign split.diverged = (| split_then_mask) && (| split_else_mask); + assign split.then_mask = split_then_mask; + assign split.else_mask = split_else_mask; + assign split.pc = gpu_req_if.next_PC; + + // barrier + + assign barrier.valid = is_bar; + assign barrier.id = gpu_req_if.rs1_data[0][`NB_BITS-1:0]; + assign barrier.size_m1 = (`NW_BITS)'(gpu_req_if.rs2_data - 1); + + // output + + assign warp_ctl_if.valid = gpu_req_if.valid && gpu_commit_if.ready; + assign warp_ctl_if.wid = gpu_commit_if.wid; + assign warp_ctl_if.tmc = tmc; + assign warp_ctl_if.wspawn = wspawn; + assign warp_ctl_if.split = split; + assign warp_ctl_if.barrier = barrier; + + assign gpu_commit_if.valid = gpu_req_if.valid; + assign gpu_commit_if.wid = gpu_req_if.wid; + assign gpu_commit_if.tmask = gpu_req_if.tmask; + assign gpu_commit_if.PC = gpu_req_if.PC; + assign gpu_commit_if.rd = gpu_req_if.rd; + assign gpu_commit_if.wb = gpu_req_if.wb; + + // can accept new request? + assign gpu_req_if.ready = gpu_commit_if.ready; + +endmodule \ No newline at end of file diff --git a/hw/rtl/VX_ibuffer.v b/hw/rtl/VX_ibuffer.v new file mode 100644 index 00000000..2d7d9db2 --- /dev/null +++ b/hw/rtl/VX_ibuffer.v @@ -0,0 +1,212 @@ +`include "VX_define.vh" + +module VX_ibuffer #( + parameter CORE_ID = 0 +) ( + input wire clk, + input wire reset, + + // inputs + input wire freeze, // keep current warp + VX_decode_if ibuf_enq_if, + + // outputs + output wire [`NW_BITS-1:0] deq_wid_next, + VX_decode_if ibuf_deq_if +); + localparam DATAW = `NUM_THREADS + 32 + `EX_BITS + `OP_BITS + `FRM_BITS + 1 + (`NR_BITS * 4) + 32 + 1 + 1 + 1 + `NUM_REGS; + localparam SIZE = `IBUF_SIZE; + localparam SIZEW = $clog2(SIZE+1); + localparam ADDRW = $clog2(SIZE); + localparam NWARPSW = $clog2(`NUM_WARPS+1); + + `USE_FAST_BRAM reg [DATAW-1:0] entries [`NUM_WARPS-1:0][SIZE-1:0]; + reg [SIZEW-1:0] size_r [`NUM_WARPS-1:0]; + reg [ADDRW:0] rd_ptr_r [`NUM_WARPS-1:0]; + reg [ADDRW:0] wr_ptr_r [`NUM_WARPS-1:0]; + + wire [`NUM_WARPS-1:0] q_full; + wire [`NUM_WARPS-1:0][SIZEW-1:0] q_size; + wire [DATAW-1:0] q_data_in; + wire [`NUM_WARPS-1:0][DATAW-1:0] q_data_prev; + reg [`NUM_WARPS-1:0][DATAW-1:0] q_data_out; + + wire enq_fire = ibuf_enq_if.valid && ibuf_enq_if.ready; + wire deq_fire = ibuf_deq_if.valid && ibuf_deq_if.ready; + + for (genvar i = 0; i < `NUM_WARPS; ++i) begin + + wire writing = enq_fire && (i == ibuf_enq_if.wid); + wire reading = deq_fire && (i == ibuf_deq_if.wid); + + wire [ADDRW-1:0] rd_ptr_a = rd_ptr_r[i][ADDRW-1:0]; + wire [ADDRW-1:0] wr_ptr_a = wr_ptr_r[i][ADDRW-1:0]; + + always @(posedge clk) begin + if (reset) begin + rd_ptr_r[i] <= 0; + wr_ptr_r[i] <= 0; + size_r[i] <= 0; + end else begin + if (writing) begin + if ((0 == size_r[i]) || ((1 == size_r[i]) && reading)) begin + q_data_out[i] <= q_data_in; + end else begin + entries[i][wr_ptr_a] <= q_data_in; + wr_ptr_r[i] <= wr_ptr_r[i] + ADDRW'(1); + end + if (!reading) begin + size_r[i] <= size_r[i] + SIZEW'(1); + end + end + if (reading) begin + if (size_r[i] != 1) begin + q_data_out[i] <= q_data_prev[i]; + rd_ptr_r[i] <= rd_ptr_r[i] + ADDRW'(1); + end + if (!writing) begin + size_r[i] <= size_r[i] - SIZEW'(1); + end + end + end + end + + assign q_data_prev[i] = entries[i][rd_ptr_a]; + assign q_full[i] = (size_r[i] == SIZE); + assign q_size[i] = size_r[i]; + end + + /////////////////////////////////////////////////////////////////////////// + + reg [`NUM_WARPS-1:0] valid_table, valid_table_n; + reg [`NUM_WARPS-1:0] schedule_table, schedule_table_n; + reg [NWARPSW-1:0] num_warps; + reg [`NW_BITS-1:0] deq_wid, deq_wid_n; + reg deq_valid, deq_valid_n; + reg [DATAW-1:0] deq_instr, deq_instr_n; + + always @(*) begin + valid_table_n = valid_table; + if (deq_fire) begin + valid_table_n[deq_wid] = (q_size[deq_wid] != SIZEW'(1)); + end + if (enq_fire) begin + valid_table_n[ibuf_enq_if.wid] = 1; + end + end + + // schedule the next instruction to issue + // does round-robin scheduling when multiple warps are present + always @(*) begin + deq_valid_n = 0; + deq_wid_n = 'x; + deq_instr_n = 'x; + + schedule_table_n = schedule_table; + + if (0 == num_warps) begin + deq_valid_n = enq_fire; + deq_wid_n = ibuf_enq_if.wid; + deq_instr_n = q_data_in; + end else if ((1 == num_warps) || freeze) begin + deq_valid_n = (!deq_fire || (q_size[deq_wid] != SIZEW'(1))) || enq_fire; + deq_wid_n = (!deq_fire || (q_size[deq_wid] != SIZEW'(1))) ? deq_wid : ibuf_enq_if.wid; + deq_instr_n = deq_fire ? ((q_size[deq_wid] != SIZEW'(1)) ? q_data_prev[deq_wid] : q_data_in) : q_data_out[deq_wid]; + end else begin + for (integer i = 0; i < `NUM_WARPS; i++) begin + if (schedule_table_n[i]) begin + deq_valid_n = 1; + deq_wid_n = `NW_BITS'(i); + deq_instr_n = q_data_out[i]; + schedule_table_n[i] = 0; + break; + end + end + end + end + + wire warp_added = enq_fire && (0 == q_size[ibuf_enq_if.wid]); + wire warp_removed = deq_fire && ~(enq_fire && ibuf_enq_if.wid == deq_wid) && ~(q_size[deq_wid] != SIZEW'(1)); + + always @(posedge clk) begin + if (reset) begin + valid_table <= 0; + schedule_table <= 0; + deq_valid <= 0; + num_warps <= 0; + end else begin + valid_table <= valid_table_n; + + if ((| schedule_table_n)) begin + schedule_table <= schedule_table_n; + end else begin + schedule_table <= valid_table_n; + schedule_table[deq_wid_n] <= 0; + end + + deq_valid <= deq_valid_n; + deq_wid <= deq_wid_n; + deq_instr <= deq_instr_n; + + if (warp_added && !warp_removed) begin + num_warps <= num_warps + NWARPSW'(1); + end else if (warp_removed && !warp_added) begin + num_warps <= num_warps - NWARPSW'(1); + end + + `ifdef VERILATOR + /*if (enq_fire || deq_fire || deq_valid) begin + $display("*** %t: cur=%b(%0d), nxt=%b(%0d), enq=%b(%0d), deq=%b(%0d), nw=%0d(%0d,%0d,%0d,%0d), sched=%b, sched_n=%b", + $time, deq_valid, deq_wid, deq_valid_n, deq_wid_n, enq_fire, ibuf_enq_if.wid, deq_fire, ibuf_deq_if.wid, num_warps, size_r[0], size_r[1], size_r[2], size_r[3], schedule_table, schedule_table_n); + end*/ + begin // verify 'num_warps' + integer nw = 0; + for (integer i = 0; i < `NUM_WARPS; i++) begin + nw += 32'(q_size[i] != 0); + end + assert(nw == 32'(num_warps)) else $display("%t: error: invalid num_warps: nw=%0d, ref=%0d", $time, num_warps, nw); + assert(~deq_valid || (q_size[deq_wid] != 0)) else $display("%t: error: invalid schedule: wid=%0d", $time, deq_wid); + assert(~deq_fire || (q_size[deq_wid] != 0)) else $display("%t: error: invalid dequeu: wid=%0d", $time, deq_wid); + end + `endif + end + end + + assign deq_wid_next = deq_wid_n; + + assign ibuf_enq_if.ready = ~q_full[ibuf_enq_if.wid]; + assign q_data_in = {ibuf_enq_if.tmask, + ibuf_enq_if.PC, + ibuf_enq_if.ex_type, + ibuf_enq_if.op_type, + ibuf_enq_if.op_mod, + ibuf_enq_if.wb, + ibuf_enq_if.rd, + ibuf_enq_if.rs1, + ibuf_enq_if.rs2, + ibuf_enq_if.rs3, + ibuf_enq_if.imm, + ibuf_enq_if.rs1_is_PC, + ibuf_enq_if.rs2_is_imm, + ibuf_enq_if.use_rs3, + ibuf_enq_if.used_regs}; + + assign ibuf_deq_if.valid = deq_valid; + assign ibuf_deq_if.wid = deq_wid; + assign {ibuf_deq_if.tmask, + ibuf_deq_if.PC, + ibuf_deq_if.ex_type, + ibuf_deq_if.op_type, + ibuf_deq_if.op_mod, + ibuf_deq_if.wb, + ibuf_deq_if.rd, + ibuf_deq_if.rs1, + ibuf_deq_if.rs2, + ibuf_deq_if.rs3, + ibuf_deq_if.imm, + ibuf_deq_if.rs1_is_PC, + ibuf_deq_if.rs2_is_imm, + ibuf_deq_if.use_rs3, + ibuf_deq_if.used_regs} = deq_instr; + +endmodule \ No newline at end of file diff --git a/hw/rtl/VX_icache_stage.v b/hw/rtl/VX_icache_stage.v index 5232f943..1bb61f92 100644 --- a/hw/rtl/VX_icache_stage.v +++ b/hw/rtl/VX_icache_stage.v @@ -7,97 +7,77 @@ module VX_icache_stage #( input wire clk, input wire reset, - input wire total_freeze, - output wire icache_stage_delay, - output wire[`NW_BITS-1:0] icache_stage_wid, - output wire icache_stage_response, - VX_inst_meta_if fe_inst_meta_fi, - VX_inst_meta_if fe_inst_meta_id, + // Icache interface VX_cache_core_req_if icache_req_if, - VX_cache_core_rsp_if icache_rsp_if + VX_cache_core_rsp_if icache_rsp_if, + + // request + VX_ifetch_req_if ifetch_req_if, + + // reponse + VX_ifetch_rsp_if ifetch_rsp_if ); + `UNUSED_VAR (reset) - reg [`NUM_THREADS-1:0] valid_threads [`NUM_WARPS-1:0]; + reg [31:0] rsp_PC_buf [`NUM_WARPS-1:0]; + reg [`NUM_THREADS-1:0] rsp_tmask_buf [`NUM_WARPS-1:0]; - wire valid_inst = (| fe_inst_meta_fi.valid); - - wire [`LOG2UP(`ICREQ_SIZE)-1:0] mrq_write_addr, mrq_read_addr, dbg_mrq_write_addr; - wire mrq_full; - - wire mrq_push = icache_req_if.valid && icache_req_if.ready; - wire mrq_pop = icache_rsp_if.valid && icache_rsp_if.ready; - - assign mrq_read_addr = icache_rsp_if.tag[0][`LOG2UP(`ICREQ_SIZE)-1:0]; - - VX_indexable_queue #( - .DATAW (`LOG2UP(`ICREQ_SIZE) + 32 + `NW_BITS), - .SIZE (`ICREQ_SIZE) - ) mem_req_queue ( - .clk (clk), - .reset (reset), - .write_data ({mrq_write_addr, fe_inst_meta_fi.curr_PC, fe_inst_meta_fi.warp_num}), - .write_addr (mrq_write_addr), - .push (mrq_push), - .full (mrq_full), - .pop (mrq_pop), - .read_addr (mrq_read_addr), - .read_data ({dbg_mrq_write_addr, fe_inst_meta_id.curr_PC, fe_inst_meta_id.warp_num}), - `UNUSED_PIN (empty) - ); + wire icache_req_fire = icache_req_if.valid && icache_req_if.ready; + + wire [`NW_BITS-1:0] req_tag = ifetch_req_if.wid; + wire [`NW_BITS-1:0] rsp_tag = icache_rsp_if.tag[0][`NW_BITS-1:0]; always @(posedge clk) begin - if (mrq_push) begin - valid_threads[fe_inst_meta_fi.warp_num] <= fe_inst_meta_fi.valid; - end - if (mrq_pop) begin - assert(mrq_read_addr == dbg_mrq_write_addr); - end - end + if (icache_req_fire) begin + rsp_PC_buf[req_tag] <= ifetch_req_if.PC; + rsp_tmask_buf[req_tag] <= ifetch_req_if.tmask; + end + end // Icache Request - assign icache_req_if.valid = valid_inst && !mrq_full; + assign icache_req_if.valid = ifetch_req_if.valid; assign icache_req_if.rw = 0; assign icache_req_if.byteen = 4'b1111; - assign icache_req_if.addr = fe_inst_meta_fi.curr_PC[31:2]; + assign icache_req_if.addr = ifetch_req_if.PC[31:2]; assign icache_req_if.data = 0; - // Can't accept new request - assign icache_stage_delay = mrq_full || !icache_req_if.ready; + // Can accept new request? + assign ifetch_req_if.ready = icache_req_if.ready; `ifdef DBG_CORE_REQ_INFO - assign icache_req_if.tag = {fe_inst_meta_fi.curr_PC, 2'b1, 5'b0, fe_inst_meta_fi.warp_num, mrq_write_addr}; + assign icache_req_if.tag = {ifetch_req_if.PC, `NR_BITS'(0), ifetch_req_if.wid, req_tag}; `else - assign icache_req_if.tag = mrq_write_addr; + assign icache_req_if.tag = req_tag; `endif - assign fe_inst_meta_id.instruction = icache_rsp_if.valid ? icache_rsp_if.data[0] : 0; - assign fe_inst_meta_id.valid = icache_rsp_if.valid ? valid_threads[fe_inst_meta_id.warp_num] : 0; - - assign icache_stage_response = mrq_pop; - assign icache_stage_wid = fe_inst_meta_id.warp_num; + assign ifetch_rsp_if.valid = icache_rsp_if.valid; + assign ifetch_rsp_if.wid = rsp_tag; + assign ifetch_rsp_if.tmask = rsp_tmask_buf[rsp_tag]; + assign ifetch_rsp_if.PC = rsp_PC_buf[rsp_tag]; + assign ifetch_rsp_if.instr = icache_rsp_if.data[0]; - // Can't accept new response - assign icache_rsp_if.ready = !total_freeze; + // Can accept new response? + assign icache_rsp_if.ready = ifetch_rsp_if.ready; - `SCOPE_ASSIGN(scope_icache_req_valid, icache_req_if.valid); - `SCOPE_ASSIGN(scope_icache_req_warp_num, fe_inst_meta_fi.warp_num); - `SCOPE_ASSIGN(scope_icache_req_addr, {icache_req_if.addr, 2'b0}); - `SCOPE_ASSIGN(scope_icache_req_tag, icache_req_if.tag); - `SCOPE_ASSIGN(scope_icache_req_ready, icache_req_if.ready); + `SCOPE_ASSIGN (scope_icache_req_valid, icache_req_if.valid); + `SCOPE_ASSIGN (scope_icache_req_wid, ifetch_req_if.wid); + `SCOPE_ASSIGN (scope_icache_req_addr, {icache_req_if.addr, 2'b0}); + `SCOPE_ASSIGN (scope_icache_req_tag, req_tag); + `SCOPE_ASSIGN (scope_icache_req_ready, icache_req_if.ready); - `SCOPE_ASSIGN(scope_icache_rsp_valid, icache_rsp_if.valid); - `SCOPE_ASSIGN(scope_icache_rsp_data, icache_rsp_if.data); - `SCOPE_ASSIGN(scope_icache_rsp_tag, icache_rsp_if.tag); - `SCOPE_ASSIGN(scope_icache_rsp_ready, icache_rsp_if.ready); + `SCOPE_ASSIGN (scope_icache_rsp_valid, icache_rsp_if.valid); + `SCOPE_ASSIGN (scope_icache_rsp_data, icache_rsp_if.data); + `SCOPE_ASSIGN (scope_icache_rsp_tag, rsp_tag); + `SCOPE_ASSIGN (scope_icache_rsp_ready, icache_rsp_if.ready); `ifdef DBG_PRINT_CORE_ICACHE always @(posedge clk) begin if (icache_req_if.valid && icache_req_if.ready) begin - $display("%t: I%0d$ req: tag=%0h, pc=%0h, warp=%0d", $time, CORE_ID, mrq_write_addr, fe_inst_meta_fi.curr_PC, fe_inst_meta_fi.warp_num); + $display("%t: I$%0d req: wid=%0d, PC=%0h", $time, CORE_ID, ifetch_req_if.wid, ifetch_req_if.PC); end if (icache_rsp_if.valid && icache_rsp_if.ready) begin - $display("%t: I%0d$ rsp: tag=%0h, pc=%0h, warp=%0d, instr=%0h", $time, CORE_ID, mrq_read_addr, fe_inst_meta_id.curr_PC, fe_inst_meta_id.warp_num, fe_inst_meta_id.instruction); + $display("%t: I$%0d rsp: wid=%0d, PC=%0h, instr=%0h", $time, CORE_ID, ifetch_rsp_if.wid, ifetch_rsp_if.PC, ifetch_rsp_if.instr); end end `endif diff --git a/hw/rtl/VX_inst_multiplex.v b/hw/rtl/VX_inst_multiplex.v deleted file mode 100644 index 73225085..00000000 --- a/hw/rtl/VX_inst_multiplex.v +++ /dev/null @@ -1,90 +0,0 @@ -`include "VX_define.vh" - -module VX_inst_multiplex ( - // Inputs - VX_backend_req_if bckE_req_if, - VX_gpr_read_if gpr_read_if, - - // Outputs - VX_exec_unit_req_if exec_unit_req_if, - VX_lsu_req_if lsu_req_if, - VX_gpu_inst_req_if gpu_inst_req_if, - VX_csr_req_if csr_req_if -); - - wire[`NUM_THREADS-1:0] is_mem_mask; - wire[`NUM_THREADS-1:0] is_gpu_mask; - wire[`NUM_THREADS-1:0] is_csr_mask; - - wire is_mem = (bckE_req_if.mem_write != `BYTE_EN_NO) || (bckE_req_if.mem_read != `BYTE_EN_NO); - wire is_gpu = (bckE_req_if.is_wspawn || bckE_req_if.is_tmc || bckE_req_if.is_barrier || bckE_req_if.is_split); - wire is_csr = bckE_req_if.is_csr; - // wire is_gpu = 0; - - genvar i; - generate - for (i = 0; i < `NUM_THREADS; i++) begin : mask_init - assign is_mem_mask[i] = is_mem; - assign is_gpu_mask[i] = is_gpu; - assign is_csr_mask[i] = is_csr; - end - endgenerate - - // LSU Unit - assign lsu_req_if.valid = bckE_req_if.valid & is_mem_mask; - assign lsu_req_if.warp_num = bckE_req_if.warp_num; - assign lsu_req_if.base_addr = gpr_read_if.a_reg_data; - assign lsu_req_if.store_data = gpr_read_if.b_reg_data; - - assign lsu_req_if.offset = bckE_req_if.itype_immed; - - assign lsu_req_if.mem_read = bckE_req_if.mem_read; - assign lsu_req_if.mem_write = bckE_req_if.mem_write; - assign lsu_req_if.rd = bckE_req_if.rd; - assign lsu_req_if.wb = bckE_req_if.wb; - assign lsu_req_if.curr_PC = bckE_req_if.curr_PC; - - // Execute Unit - assign exec_unit_req_if.valid = bckE_req_if.valid & (~is_mem_mask & ~is_gpu_mask & ~is_csr_mask); - assign exec_unit_req_if.warp_num = bckE_req_if.warp_num; - assign exec_unit_req_if.curr_PC = bckE_req_if.curr_PC; - assign exec_unit_req_if.next_PC = bckE_req_if.next_PC; - assign exec_unit_req_if.rd = bckE_req_if.rd; - assign exec_unit_req_if.wb = bckE_req_if.wb; - assign exec_unit_req_if.a_reg_data = gpr_read_if.a_reg_data; - assign exec_unit_req_if.b_reg_data = gpr_read_if.b_reg_data; - assign exec_unit_req_if.alu_op = bckE_req_if.alu_op; - assign exec_unit_req_if.rs1 = bckE_req_if.rs1; - assign exec_unit_req_if.rs2 = bckE_req_if.rs2; - assign exec_unit_req_if.rs2_src = bckE_req_if.rs2_src; - assign exec_unit_req_if.itype_immed = bckE_req_if.itype_immed; - assign exec_unit_req_if.upper_immed = bckE_req_if.upper_immed; - assign exec_unit_req_if.branch_type = bckE_req_if.branch_type; - assign exec_unit_req_if.is_jal = bckE_req_if.is_jal; - assign exec_unit_req_if.jal = bckE_req_if.jal; - assign exec_unit_req_if.jal_offset = bckE_req_if.jal_offset; - assign exec_unit_req_if.is_etype = bckE_req_if.is_etype; - - // GPR Req - assign gpu_inst_req_if.valid = bckE_req_if.valid & is_gpu_mask; - assign gpu_inst_req_if.warp_num = bckE_req_if.warp_num; - assign gpu_inst_req_if.is_wspawn = bckE_req_if.is_wspawn; - assign gpu_inst_req_if.is_tmc = bckE_req_if.is_tmc; - assign gpu_inst_req_if.is_split = bckE_req_if.is_split; - assign gpu_inst_req_if.is_barrier = bckE_req_if.is_barrier; - assign gpu_inst_req_if.a_reg_data = gpr_read_if.a_reg_data; - assign gpu_inst_req_if.rd2 = gpr_read_if.b_reg_data[0]; - assign gpu_inst_req_if.next_PC = bckE_req_if.next_PC; - - // CSR Req - assign csr_req_if.valid = bckE_req_if.valid & is_csr_mask; - assign csr_req_if.warp_num = bckE_req_if.warp_num; - assign csr_req_if.rd = bckE_req_if.rd; - assign csr_req_if.wb = bckE_req_if.wb; - assign csr_req_if.alu_op = bckE_req_if.alu_op; - assign csr_req_if.is_csr = bckE_req_if.is_csr; - assign csr_req_if.csr_addr = bckE_req_if.csr_addr; - assign csr_req_if.csr_immed = bckE_req_if.csr_immed; - assign csr_req_if.csr_mask = bckE_req_if.csr_mask; - -endmodule \ No newline at end of file diff --git a/hw/rtl/VX_instr_demux.v b/hw/rtl/VX_instr_demux.v new file mode 100644 index 00000000..e7a280d7 --- /dev/null +++ b/hw/rtl/VX_instr_demux.v @@ -0,0 +1,237 @@ +`include "VX_define.vh" + +module VX_instr_demux ( + input wire clk, + input wire reset, + + // inputs + VX_decode_if execute_if, + VX_gpr_rsp_if gpr_rsp_if, + VX_csr_to_issue_if csr_to_issue_if, + + // outputs + VX_alu_req_if alu_req_if, + VX_lsu_req_if lsu_req_if, + VX_csr_req_if csr_req_if, + VX_mul_req_if mul_req_if, + VX_fpu_req_if fpu_req_if, + VX_gpu_req_if gpu_req_if +); + wire [`NT_BITS-1:0] tid; + VX_priority_encoder #( + .N(`NUM_THREADS) + ) tid_select ( + .data_in (execute_if.tmask), + .data_out (tid), + `UNUSED_PIN (valid_out) + ); + + wire [31:0] next_PC = execute_if.PC + 4; + + // ALU unit + + wire alu_req_valid = execute_if.valid && (execute_if.ex_type == `EX_ALU); + wire alu_req_ready; + wire is_br_op = `IS_BR_MOD(execute_if.op_mod); + + VX_skid_buffer #( + .DATAW (`NW_BITS + `NUM_THREADS + 32 + 32 + `ALU_BR_BITS + 1 + 32 + 1 + 1 + `NR_BITS + 1 + `NT_BITS) + ) alu_reg ( + .clk (clk), + .reset (reset), + .ready_in (alu_req_ready), + .valid_in (alu_req_valid), + .data_in ({execute_if.wid, execute_if.tmask, execute_if.PC, next_PC, `ALU_BR_OP(execute_if.op_type), is_br_op, execute_if.imm, execute_if.rs1_is_PC, execute_if.rs2_is_imm, execute_if.rd, execute_if.wb, tid}), + .data_out ({alu_req_if.wid, alu_req_if.tmask, alu_req_if.PC, alu_req_if.next_PC, alu_req_if.op_type, alu_req_if.is_br_op, alu_req_if.imm, alu_req_if.rs1_is_PC, alu_req_if.rs2_is_imm, alu_req_if.rd, alu_req_if.wb, alu_req_if.tid}), + .ready_out (alu_req_if.ready), + .valid_out (alu_req_if.valid) + ); + + VX_gpr_bypass #( + .DATAW (2 * `NUM_THREADS * 32), + .PASSTHRU (1) // ALU has no back-pressure, bypass not needed + ) alu_bypass ( + .clk (clk), + .reset (reset), + .push (alu_req_valid && alu_req_ready), + .data_in ({gpr_rsp_if.rs1_data, gpr_rsp_if.rs2_data}), + .data_out ({alu_req_if.rs1_data, alu_req_if.rs2_data}), + .pop (alu_req_if.valid && alu_req_if.ready) + ); + + // lsu unit + + wire lsu_req_valid = execute_if.valid && (execute_if.ex_type == `EX_LSU); + wire lsu_req_ready; + + VX_skid_buffer #( + .DATAW (`NW_BITS + `NUM_THREADS + 32 + 1 + `BYTEEN_BITS + 32 + `NR_BITS + 1) + ) lsu_reg ( + .clk (clk), + .reset (reset), + .ready_in (lsu_req_ready), + .valid_in (lsu_req_valid), + .data_in ({execute_if.wid, execute_if.tmask, execute_if.PC, `LSU_RW(execute_if.op_type), `LSU_BE(execute_if.op_type), execute_if.imm, execute_if.rd, execute_if.wb}), + .data_out ({lsu_req_if.wid, lsu_req_if.tmask, lsu_req_if.PC, lsu_req_if.rw, lsu_req_if.byteen, lsu_req_if.offset, lsu_req_if.rd, lsu_req_if.wb}), + .ready_out (lsu_req_if.ready), + .valid_out (lsu_req_if.valid) + ); + + VX_gpr_bypass #( + .DATAW ((2 * `NUM_THREADS * 32)) + ) lsu_bypass ( + .clk (clk), + .reset (reset), + .push (lsu_req_valid && lsu_req_ready), + .data_in ({gpr_rsp_if.rs1_data, gpr_rsp_if.rs2_data}), + .data_out ({lsu_req_if.base_addr, lsu_req_if.store_data}), + .pop (lsu_req_if.valid && lsu_req_if.ready) + ); + + // csr unit + + wire csr_req_valid = execute_if.valid && (execute_if.ex_type == `EX_CSR); + wire csr_req_ready; + + VX_skid_buffer #( + .DATAW (`NW_BITS + `NUM_THREADS + 32 + `CSR_BITS + `CSR_ADDR_BITS + `NR_BITS + 1 + 1) + ) csr_reg ( + .clk (clk), + .reset (reset), + .ready_in (csr_req_ready), + .valid_in (csr_req_valid), + .data_in ({execute_if.wid, execute_if.tmask, execute_if.PC, `CSR_OP(execute_if.op_type), execute_if.imm[`CSR_ADDR_BITS-1:0], execute_if.rd, execute_if.wb, 1'b0}), + .data_out ({csr_req_if.wid, csr_req_if.tmask, csr_req_if.PC, csr_req_if.op_type, csr_req_if.csr_addr, csr_req_if.rd, csr_req_if.wb, csr_req_if.is_io}), + .ready_out (csr_req_if.ready), + .valid_out (csr_req_if.valid) + ); + + reg tmp_rs2_is_imm; + reg [`NR_BITS-1:0] tmp_rs1; + + always @(posedge clk) begin + tmp_rs2_is_imm <= execute_if.rs2_is_imm; + tmp_rs1 <= execute_if.rs1; + end + + wire [31:0] csr_req_mask = tmp_rs2_is_imm ? 32'(tmp_rs1) : gpr_rsp_if.rs1_data[0]; + + VX_gpr_bypass #( + .DATAW (32) + ) csr_bypass ( + .clk (clk), + .reset (reset), + .push (csr_req_valid && csr_req_ready), + .data_in (csr_req_mask), + .data_out (csr_req_if.csr_mask), + .pop (csr_req_if.valid && csr_req_if.ready) + ); + + // mul unit + +`ifdef EXT_M_ENABLE + wire mul_req_valid = execute_if.valid && (execute_if.ex_type == `EX_MUL); + wire mul_req_ready; + + VX_skid_buffer #( + .DATAW (`NW_BITS + `NUM_THREADS + 32 + `MUL_BITS + `NR_BITS + 1) + ) mul_reg ( + .clk (clk), + .reset (reset), + .ready_in (mul_req_ready), + .valid_in (mul_req_valid), + .data_in ({execute_if.wid, execute_if.tmask, execute_if.PC, `MUL_OP(execute_if.op_type), execute_if.rd, execute_if.wb}), + .data_out ({mul_req_if.wid, mul_req_if.tmask, mul_req_if.PC, mul_req_if.op_type, mul_req_if.rd, mul_req_if.wb}), + .ready_out (mul_req_if.ready), + .valid_out (mul_req_if.valid) + ); + + VX_gpr_bypass #( + .DATAW ((2 * `NUM_THREADS * 32)) + ) mul_bypass ( + .clk (clk), + .reset (reset), + .push (mul_req_valid && mul_req_ready), + .data_in ({gpr_rsp_if.rs1_data, gpr_rsp_if.rs2_data}), + .data_out ({mul_req_if.rs1_data, mul_req_if.rs2_data}), + .pop (mul_req_if.valid && mul_req_if.ready) + ); +`endif + + // fpu unit + +`ifdef EXT_F_ENABLE + wire fpu_req_valid = execute_if.valid && (execute_if.ex_type == `EX_FPU); + wire fpu_req_ready; + + // resolve dynamic FRM + assign csr_to_issue_if.wid = execute_if.wid; + wire [`FRM_BITS-1:0] fpu_frm = (execute_if.op_mod == `FRM_DYN) ? csr_to_issue_if.frm : execute_if.op_mod; + + VX_skid_buffer #( + .DATAW (`NW_BITS + `NUM_THREADS + 32 + `FPU_BITS + `FRM_BITS + `NR_BITS + 1) + ) fpu_reg ( + .clk (clk), + .reset (reset), + .ready_in (fpu_req_ready), + .valid_in (fpu_req_valid), + .data_in ({execute_if.wid, execute_if.tmask, execute_if.PC, `FPU_OP(execute_if.op_type), fpu_frm, execute_if.rd, execute_if.wb}), + .data_out ({fpu_req_if.wid, fpu_req_if.tmask, fpu_req_if.PC, fpu_req_if.op_type, fpu_req_if.frm, fpu_req_if.rd, fpu_req_if.wb}), + .ready_out (fpu_req_if.ready), + .valid_out (fpu_req_if.valid) + ); + + VX_gpr_bypass #( + .DATAW ((3 * `NUM_THREADS * 32)) + ) fpu_bypass ( + .clk (clk), + .reset (reset), + .push (fpu_req_valid && fpu_req_ready), + .data_in ({gpr_rsp_if.rs1_data, gpr_rsp_if.rs2_data, gpr_rsp_if.rs3_data}), + .data_out ({fpu_req_if.rs1_data, fpu_req_if.rs2_data, fpu_req_if.rs3_data}), + .pop (fpu_req_if.valid && fpu_req_if.ready) + ); +`endif + + // gpu unit + + wire gpu_req_valid = execute_if.valid && (execute_if.ex_type == `EX_GPU); + wire gpu_req_ready; + + VX_skid_buffer #( + .DATAW (`NW_BITS + `NUM_THREADS + 32 + 32 + `GPU_BITS + `NR_BITS + 1) + ) gpu_reg ( + .clk (clk), + .reset (reset), + .ready_in (gpu_req_ready), + .valid_in (gpu_req_valid), + .data_in ({execute_if.wid, execute_if.tmask, execute_if.PC, next_PC, `GPU_OP(execute_if.op_type), execute_if.rd, execute_if.wb}), + .data_out ({gpu_req_if.wid, gpu_req_if.tmask, gpu_req_if.PC, gpu_req_if.next_PC, gpu_req_if.op_type, gpu_req_if.rd, gpu_req_if.wb}), + .ready_out (gpu_req_if.ready), + .valid_out (gpu_req_if.valid) + ); + + VX_gpr_bypass #( + .DATAW ((`NUM_THREADS * 32) + 32) + ) gpu_bypass ( + .clk (clk), + .reset (reset), + .push (gpu_req_valid && gpu_req_ready), + .data_in ({gpr_rsp_if.rs1_data, gpr_rsp_if.rs2_data[0]}), + .data_out ({gpu_req_if.rs1_data, gpu_req_if.rs2_data}), + .pop (gpu_req_if.valid && gpu_req_if.ready) + ); + + // can take next request? + assign execute_if.ready = (alu_req_ready && (execute_if.ex_type == `EX_ALU)) + || (lsu_req_ready && (execute_if.ex_type == `EX_LSU)) + || (csr_req_ready && (execute_if.ex_type == `EX_CSR)) + `ifdef EXT_M_ENABLE + || (mul_req_ready && (execute_if.ex_type == `EX_MUL)) + `endif + `ifdef EXT_F_ENABLE + || (fpu_req_ready && (execute_if.ex_type == `EX_FPU)) + `endif + || (gpu_req_ready && (execute_if.ex_type == `EX_GPU)); + +endmodule \ No newline at end of file diff --git a/hw/rtl/VX_ipdom_stack.v b/hw/rtl/VX_ipdom_stack.v new file mode 100644 index 00000000..f388d3d0 --- /dev/null +++ b/hw/rtl/VX_ipdom_stack.v @@ -0,0 +1,49 @@ + +`include "VX_platform.vh" + +module VX_ipdom_stack #( + parameter WIDTH = 1, + parameter DEPTH = 1 +) ( + input wire clk, + input wire reset, + input wire [WIDTH - 1:0] q1, + input wire [WIDTH - 1:0] q2, + output wire [WIDTH - 1:0] d, + input wire push, + input wire pop, + output wire empty, + output wire full +); + localparam STACK_SIZE = 2 ** DEPTH; + + `USE_FAST_BRAM reg [WIDTH-1:0] stack_1 [0:STACK_SIZE-1]; + `USE_FAST_BRAM reg [WIDTH-1:0] stack_2 [0:STACK_SIZE-1]; + `USE_FAST_BRAM reg is_part [0:STACK_SIZE-1]; + + reg [DEPTH-1:0] rd_ptr, wr_ptr; + + always @(posedge clk) begin + if (reset) begin + wr_ptr <= 0; + end else begin + if (push) begin + stack_1[wr_ptr] <= q1; + stack_2[wr_ptr] <= q2; + is_part[wr_ptr] <= 0; + rd_ptr <= wr_ptr; + wr_ptr <= wr_ptr + DEPTH'(1); + end else if (pop) begin + wr_ptr <= wr_ptr - DEPTH'(is_part[rd_ptr]); + rd_ptr <= rd_ptr - DEPTH'(is_part[rd_ptr]); + is_part[rd_ptr] <= 1; + end + end + end + + assign d = is_part[rd_ptr] ? stack_1[rd_ptr] : stack_2[rd_ptr]; + + assign empty = (0 == wr_ptr); + assign full = ((STACK_SIZE-1) == wr_ptr); + +endmodule \ No newline at end of file diff --git a/hw/rtl/VX_issue.v b/hw/rtl/VX_issue.v new file mode 100644 index 00000000..1c1e4f8a --- /dev/null +++ b/hw/rtl/VX_issue.v @@ -0,0 +1,159 @@ +`include "VX_define.vh" + +module VX_issue #( + parameter CORE_ID = 0 +) ( + `SCOPE_SIGNALS_ISSUE_IO + + input wire clk, + input wire reset, + + VX_decode_if decode_if, + VX_writeback_if writeback_if, + VX_csr_to_issue_if csr_to_issue_if, + + VX_alu_req_if alu_req_if, + VX_lsu_req_if lsu_req_if, + VX_csr_req_if csr_req_if, + VX_mul_req_if mul_req_if, + VX_fpu_req_if fpu_req_if, + VX_gpu_req_if gpu_req_if +); + VX_decode_if ibuf_deq_if(); + VX_decode_if execute_if(); + VX_gpr_req_if gpr_req_if(); + VX_gpr_rsp_if gpr_rsp_if(); + + wire scoreboard_delay; + wire [`NW_BITS-1:0] deq_wid_next; + + VX_ibuffer #( + .CORE_ID(CORE_ID) + ) ibuffer ( + .clk (clk), + .reset (reset), + .freeze (~gpr_req_if.ready), + .ibuf_enq_if (decode_if), + .deq_wid_next (deq_wid_next), + .ibuf_deq_if (ibuf_deq_if) + ); + + VX_scoreboard #( + .CORE_ID(CORE_ID) + ) scoreboard ( + .clk (clk), + .reset (reset), + .ibuf_deq_if (ibuf_deq_if), + .writeback_if (writeback_if), + .deq_wid_next (deq_wid_next), + .exe_delay (~execute_if.ready), + .gpr_delay (~gpr_req_if.ready), + .delay (scoreboard_delay) + ); + + assign gpr_req_if.valid = ibuf_deq_if.valid && ~scoreboard_delay; + assign gpr_req_if.wid = ibuf_deq_if.wid; + assign gpr_req_if.PC = ibuf_deq_if.PC; + assign gpr_req_if.rs1 = ibuf_deq_if.rs1; + assign gpr_req_if.rs2 = ibuf_deq_if.rs2; + assign gpr_req_if.rs3 = ibuf_deq_if.rs3; + assign gpr_req_if.use_rs3 = ibuf_deq_if.use_rs3; + assign gpr_rsp_if.ready = execute_if.ready; + + VX_gpr_stage #( + .CORE_ID(CORE_ID) + ) gpr_stage ( + .clk (clk), + .reset (reset), + .writeback_if (writeback_if), + .gpr_req_if (gpr_req_if), + .gpr_rsp_if (gpr_rsp_if) + ); + + `UNUSED_VAR (gpr_rsp_if.valid); + + assign execute_if.valid = ibuf_deq_if.valid && gpr_req_if.ready && ~scoreboard_delay; + assign execute_if.wid = ibuf_deq_if.wid; + assign execute_if.tmask = ibuf_deq_if.tmask; + assign execute_if.PC = ibuf_deq_if.PC; + assign execute_if.ex_type = ibuf_deq_if.ex_type; + assign execute_if.op_type = ibuf_deq_if.op_type; + assign execute_if.op_mod = ibuf_deq_if.op_mod; + assign execute_if.wb = ibuf_deq_if.wb; + assign execute_if.rd = ibuf_deq_if.rd; + assign execute_if.rs1 = ibuf_deq_if.rs1; + assign execute_if.imm = ibuf_deq_if.imm; + assign execute_if.rs1_is_PC = ibuf_deq_if.rs1_is_PC; + assign execute_if.rs2_is_imm = ibuf_deq_if.rs2_is_imm; + + VX_instr_demux instr_demux ( + .clk (clk), + .reset (reset), + .execute_if (execute_if), + .gpr_rsp_if (gpr_rsp_if), + .csr_to_issue_if(csr_to_issue_if), + .alu_req_if (alu_req_if), + .lsu_req_if (lsu_req_if), + .csr_req_if (csr_req_if), + .mul_req_if (mul_req_if), + .fpu_req_if (fpu_req_if), + .gpu_req_if (gpu_req_if) + ); + + `SCOPE_ASSIGN (scope_issue_valid, ibuf_deq_if.valid); + `SCOPE_ASSIGN (scope_issue_wid, ibuf_deq_if.wid); + `SCOPE_ASSIGN (scope_issue_tmask, ibuf_deq_if.tmask); + `SCOPE_ASSIGN (scope_issue_pc, ibuf_deq_if.PC); + `SCOPE_ASSIGN (scope_issue_ex_type, ibuf_deq_if.ex_type); + `SCOPE_ASSIGN (scope_issue_op_type, ibuf_deq_if.op_type); + `SCOPE_ASSIGN (scope_issue_op_mod, ibuf_deq_if.op_mod); + `SCOPE_ASSIGN (scope_issue_wb, ibuf_deq_if.wb); + `SCOPE_ASSIGN (scope_issue_rd, ibuf_deq_if.rd); + `SCOPE_ASSIGN (scope_issue_rs1, ibuf_deq_if.rs1); + `SCOPE_ASSIGN (scope_issue_rs2, ibuf_deq_if.rs2); + `SCOPE_ASSIGN (scope_issue_rs3, ibuf_deq_if.rs3); + `SCOPE_ASSIGN (scope_issue_imm, ibuf_deq_if.imm); + `SCOPE_ASSIGN (scope_issue_rs1_is_pc, ibuf_deq_if.rs1_is_PC); + `SCOPE_ASSIGN (scope_issue_rs2_is_imm, ibuf_deq_if.rs2_is_imm); + `SCOPE_ASSIGN (scope_issue_ready, ibuf_deq_if.ready); + `SCOPE_ASSIGN (scope_scoreboard_delay, scoreboard_delay); + `SCOPE_ASSIGN (scope_gpr_delay, ~gpr_req_if.ready); + `SCOPE_ASSIGN (scope_execute_delay, ~execute_if.ready); + + `SCOPE_ASSIGN (scope_gpr_rsp_valid, gpr_rsp_if.valid); + `SCOPE_ASSIGN (scope_gpr_rsp_wid, gpr_rsp_if.wid); + `SCOPE_ASSIGN (scope_gpr_rsp_pc, gpr_rsp_if.PC); + `SCOPE_ASSIGN (scope_gpr_rsp_a, gpr_rsp_if.rs1_data); + `SCOPE_ASSIGN (scope_gpr_rsp_b, gpr_rsp_if.rs2_data); + `SCOPE_ASSIGN (scope_gpr_rsp_c, gpr_rsp_if.rs3_data); + + `SCOPE_ASSIGN (scope_writeback_valid, writeback_if.valid); + `SCOPE_ASSIGN (scope_writeback_wid, writeback_if.wid); + `SCOPE_ASSIGN (scope_writeback_pc, writeback_if.PC); + `SCOPE_ASSIGN (scope_writeback_rd, writeback_if.rd); + `SCOPE_ASSIGN (scope_writeback_data, writeback_if.data); + +`ifdef DBG_PRINT_PIPELINE + always @(posedge clk) begin + if (alu_req_if.valid && alu_req_if.ready) begin + $display("%t: core%0d-issue: wid=%0d, PC=%0h, ex=ALU, tmask=%b, rs1_data=%0h, rs2_data=%0h", $time, CORE_ID, alu_req_if.wid, alu_req_if.PC, alu_req_if.tmask, alu_req_if.rs1_data, alu_req_if.rs2_data); + end + if (lsu_req_if.valid && lsu_req_if.ready) begin + $display("%t: core%0d-issue: wid=%0d, PC=%0h, ex=LSU, tmask=%b, rw=%b, byteen=%b, baddr=%0h, offset=%0h, data=%0h", $time, CORE_ID, lsu_req_if.wid, lsu_req_if.PC, lsu_req_if.tmask, lsu_req_if.rw, lsu_req_if.byteen, lsu_req_if.base_addr, lsu_req_if.offset, lsu_req_if.store_data); + end + if (csr_req_if.valid && csr_req_if.ready) begin + $display("%t: core%0d-issue: wid=%0d, PC=%0h, ex=CSR, tmask=%b, addr=%0h, mask=%0h", $time, CORE_ID, csr_req_if.wid, csr_req_if.PC, csr_req_if.tmask, csr_req_if.csr_addr, csr_req_if.csr_mask); + end + if (mul_req_if.valid && mul_req_if.ready) begin + $display("%t: core%0d-issue: wid=%0d, PC=%0h, ex=MUL, tmask=%b, rs1_data=%0h, rs2_data=%0h", $time, CORE_ID, mul_req_if.wid, mul_req_if.PC, mul_req_if.tmask, mul_req_if.rs1_data, mul_req_if.rs2_data); + end + if (fpu_req_if.valid && fpu_req_if.ready) begin + $display("%t: core%0d-issue: wid=%0d, PC=%0h, ex=FPU, tmask=%b, rs1_data=%0h, rs2_data=%0h, rs3_data=%0h", $time, CORE_ID, fpu_req_if.wid, fpu_req_if.PC, fpu_req_if.tmask, fpu_req_if.rs1_data, fpu_req_if.rs2_data, fpu_req_if.rs3_data); + end + if (gpu_req_if.valid && gpu_req_if.ready) begin + $display("%t: core%0d-issue: wid=%0d, PC=%0h, ex=GPU, tmask=%b, rs1_data=%0h, rs2_data=%0h", $time, CORE_ID, gpu_req_if.wid, gpu_req_if.PC, gpu_req_if.tmask, gpu_req_if.rs1_data, gpu_req_if.rs2_data); + end + end +`endif + +endmodule \ No newline at end of file diff --git a/hw/rtl/VX_lsu_unit.v b/hw/rtl/VX_lsu_unit.v index d1296680..86ebcd3b 100644 --- a/hw/rtl/VX_lsu_unit.v +++ b/hw/rtl/VX_lsu_unit.v @@ -5,203 +5,217 @@ module VX_lsu_unit #( ) ( `SCOPE_SIGNALS_LSU_IO - input wire clk, - input wire reset, - - input wire no_slot_mem, - VX_lsu_req_if lsu_req_if, - - // Write back to GPR - VX_wb_if mem_wb_if, + input wire clk, + input wire reset, // Dcache interface - VX_cache_core_req_if dcache_req_if, - VX_cache_core_rsp_if dcache_rsp_if, + VX_cache_core_req_if dcache_req_if, + VX_cache_core_rsp_if dcache_rsp_if, - output wire delay + // inputs + VX_lsu_req_if lsu_req_if, + + // outputs + VX_exu_to_cmt_if lsu_commit_if ); + wire [`NUM_THREADS-1:0] req_tmask; + wire req_rw; + wire [`NUM_THREADS-1:0][29:0] req_addr; + wire [`NUM_THREADS-1:0][1:0] req_offset; + wire [`NUM_THREADS-1:0][3:0] req_byteen; + wire [`NUM_THREADS-1:0][31:0] req_data; + wire [1:0] req_sext; + wire [`NR_BITS-1:0] req_rd; + wire req_wb; + wire [`NW_BITS-1:0] req_wid; + wire [31:0] req_pc; - VX_wb_if mem_wb_unqual_if(); - - wire [`NUM_THREADS-1:0] use_valid; - wire use_req_rw; - wire [`NUM_THREADS-1:0][29:0] use_req_addr; - wire [`NUM_THREADS-1:0][1:0] use_req_offset; - wire [`NUM_THREADS-1:0][3:0] use_req_byteen; - wire [`NUM_THREADS-1:0][31:0] use_req_data; - wire [`BYTE_EN_BITS-1:0] use_mem_read; - wire [4:0] use_rd; - wire [`NW_BITS-1:0] use_warp_num; - wire [1:0] use_wb; - wire [31:0] use_pc; - - genvar i; - - // Generate Full Addresses - wire[`NUM_THREADS-1:0][31:0] full_address; - for (i = 0; i < `NUM_THREADS; i++) begin + wire [`NUM_THREADS-1:0][31:0] full_address; + for (genvar i = 0; i < `NUM_THREADS; i++) begin assign full_address[i] = lsu_req_if.base_addr[i] + lsu_req_if.offset; end - wire mem_req_rw = (lsu_req_if.mem_write != `BYTE_EN_NO); - - reg [3:0] wmask; + reg [1:0] mem_req_sext; always @(*) begin - case ((mem_req_rw ? lsu_req_if.mem_write[1:0] : lsu_req_if.mem_read[1:0])) - 0: wmask = 4'b0001; - 1: wmask = 4'b0011; - default : wmask = 4'b1111; + case (lsu_req_if.byteen) + `BYTEEN_SB: mem_req_sext = 2'h1; + `BYTEEN_SH: mem_req_sext = 2'h2; + default: mem_req_sext = 2'h0; endcase end wire [`NUM_THREADS-1:0][29:0] mem_req_addr; wire [`NUM_THREADS-1:0][1:0] mem_req_offset; - wire [`NUM_THREADS-1:0][3:0] mem_req_byteen; + wire [`NUM_THREADS-1:0][3:0] mem_req_byteen; wire [`NUM_THREADS-1:0][31:0] mem_req_data; - for (i = 0; i < `NUM_THREADS; i++) begin + reg [3:0] wmask; + always @(*) begin + case (`BYTEEN_TYPE(lsu_req_if.byteen)) + 0: wmask = 4'b0001; + 1: wmask = 4'b0011; + default: wmask = 4'b1111; + endcase + end + + for (genvar i = 0; i < `NUM_THREADS; i++) begin assign mem_req_addr[i] = full_address[i][31:2]; assign mem_req_offset[i] = full_address[i][1:0]; assign mem_req_byteen[i] = wmask << full_address[i][1:0]; assign mem_req_data[i] = lsu_req_if.store_data[i] << {mem_req_offset[i], 3'b0}; - end + end `IGNORE_WARNINGS_BEGIN - wire[`NUM_THREADS-1:0][31:0] use_address; + wire [`NUM_THREADS-1:0][31:0] req_address; `IGNORE_WARNINGS_END + wire valid_in; + wire stall_in; + VX_generic_register #( - .N((`NUM_THREADS * 1) + (`NUM_THREADS * 32) + `BYTE_EN_BITS + 1 + (`NUM_THREADS * (30 + 2 + 4 + 32)) + 5 + `NW_BITS + 2 + 32) - ) lsu_buffer ( + .N(1 + `NW_BITS + `NUM_THREADS + 32 + 1 + `NR_BITS + 1 + (`NUM_THREADS * 32) + 2 + (`NUM_THREADS * (30 + 2 + 4 + 32))) + ) lsu_req_reg ( .clk (clk), .reset (reset), - .stall (delay), + .stall (stall_in), .flush (1'b0), - .in ({lsu_req_if.valid, full_address, lsu_req_if.mem_read, mem_req_rw, mem_req_addr, mem_req_offset, mem_req_byteen, mem_req_data, lsu_req_if.rd, lsu_req_if.warp_num, lsu_req_if.wb, lsu_req_if.curr_PC}), - .out ({use_valid , use_address, use_mem_read , use_req_rw, use_req_addr, use_req_offset, use_req_byteen, use_req_data, use_rd , use_warp_num , use_wb , use_pc}) + .in ({lsu_req_if.valid, lsu_req_if.wid, lsu_req_if.tmask, lsu_req_if.PC, lsu_req_if.rw, lsu_req_if.rd, lsu_req_if.wb, full_address, mem_req_sext, mem_req_addr, mem_req_offset, mem_req_byteen, mem_req_data}), + .out ({valid_in, req_wid, req_tmask, req_pc, req_rw, req_rd, req_wb, req_address, req_sext, req_addr, req_offset, req_byteen, req_data}) ); - wire [`NUM_THREADS-1:0][1:0] mem_rsp_offset; - wire [`BYTE_EN_BITS-1:0] core_rsp_mem_read; + wire [`NW_BITS-1:0] rsp_wid; + wire [31:0] rsp_pc; + wire [`NR_BITS-1:0] rsp_rd; + wire rsp_wb; + wire [`NUM_THREADS-1:0][1:0] rsp_offset; + wire [1:0] rsp_sext; + reg [`NUM_THREADS-1:0][31:0] rsp_data; - reg [`NUM_THREADS-1:0] mem_rsp_mask[`DCREQ_SIZE-1:0]; + reg [`LSUQ_SIZE-1:0][`NUM_THREADS-1:0] mem_rsp_mask; - wire [`LOG2UP(`DCREQ_SIZE)-1:0] mrq_write_addr, mrq_read_addr, dbg_mrq_write_addr; - wire mrq_full; + wire [`DCORE_TAG_ID_BITS-1:0] req_tag, rsp_tag; + wire lsuq_full; - wire mrq_push = (| dcache_req_if.valid) && dcache_req_if.ready - && (0 == use_req_rw); // only push read requests + wire lsuq_push = (| dcache_req_if.valid) && dcache_req_if.ready + && (0 == req_rw); // loads only - wire mrq_pop_part = (| dcache_rsp_if.valid) && dcache_rsp_if.ready; + wire lsuq_pop_part = (| dcache_rsp_if.valid) && dcache_rsp_if.ready; - assign mrq_read_addr = dcache_rsp_if.tag[0][`LOG2UP(`DCREQ_SIZE)-1:0]; + assign rsp_tag = dcache_rsp_if.tag[0][`DCORE_TAG_ID_BITS-1:0]; - wire [`NUM_THREADS-1:0] mem_rsp_mask_upd = mem_rsp_mask[mrq_read_addr] & ~dcache_rsp_if.valid; + wire [`NUM_THREADS-1:0] mem_rsp_mask_n = mem_rsp_mask[rsp_tag] & ~dcache_rsp_if.valid; - wire mrq_pop = mrq_pop_part && (0 == mem_rsp_mask_upd); + wire lsuq_pop = lsuq_pop_part && (0 == mem_rsp_mask_n); - VX_indexable_queue #( - .DATAW (`LOG2UP(`DCREQ_SIZE) + 32 + 2 + (`NUM_THREADS * 2) + `BYTE_EN_BITS + 5 + `NW_BITS), - .SIZE (`DCREQ_SIZE) - ) mem_req_queue ( - .clk (clk), - .reset (reset), - .write_data ({mrq_write_addr, use_pc, use_wb, use_req_offset, use_mem_read, use_rd, use_warp_num}), - .write_addr (mrq_write_addr), - .push (mrq_push), - .full (mrq_full), - .pop (mrq_pop), - .read_addr (mrq_read_addr), - .read_data ({dbg_mrq_write_addr, mem_wb_unqual_if.curr_PC, mem_wb_unqual_if.wb, mem_rsp_offset, core_rsp_mem_read, mem_wb_unqual_if.rd, mem_wb_unqual_if.warp_num}), - `UNUSED_PIN (empty) + VX_cam_buffer #( + .DATAW (`NW_BITS + 32 + `NR_BITS + 1 + (`NUM_THREADS * 2) + 2), + .SIZE (`LSUQ_SIZE) + ) lsu_cam ( + .clk (clk), + .reset (reset), + .write_addr (req_tag), + .acquire_slot (lsuq_push), + .read_addr (rsp_tag), + .write_data ({req_wid, req_pc, req_rd, req_wb, req_offset, req_sext}), + .read_data ({rsp_wid, rsp_pc, rsp_rd, rsp_wb, rsp_offset, rsp_sext}), + .release_addr (rsp_tag), + .release_slot (lsuq_pop), + .full (lsuq_full) ); always @(posedge clk) begin - if (mrq_push) begin - mem_rsp_mask[mrq_write_addr] <= use_valid; + if (lsuq_push) begin + mem_rsp_mask[req_tag] <= req_tmask; end - if (mrq_pop_part) begin - mem_rsp_mask[mrq_read_addr] <= mem_rsp_mask_upd; - assert(($time < 2) || mrq_read_addr == dbg_mrq_write_addr); + if (lsuq_pop_part) begin + mem_rsp_mask[rsp_tag] <= mem_rsp_mask_n; end end - // Core Request + wire stall_out = ~lsu_commit_if.ready && lsu_commit_if.valid; + wire store_stall = valid_in && req_rw && stall_out; - assign dcache_req_if.valid = use_valid & {`NUM_THREADS{~mrq_full}}; - assign dcache_req_if.rw = {`NUM_THREADS{use_req_rw}}; - assign dcache_req_if.byteen = use_req_byteen; - assign dcache_req_if.addr = use_req_addr; - assign dcache_req_if.data = use_req_data; + // Core Request + assign dcache_req_if.valid = {`NUM_THREADS{valid_in && ~lsuq_full && ~store_stall}} & req_tmask; + assign dcache_req_if.rw = {`NUM_THREADS{req_rw}}; + assign dcache_req_if.byteen = req_byteen; + assign dcache_req_if.addr = req_addr; + assign dcache_req_if.data = req_data; `ifdef DBG_CORE_REQ_INFO - assign dcache_req_if.tag = {use_pc, use_wb, use_rd, use_warp_num, mrq_write_addr}; + assign dcache_req_if.tag = {req_pc, req_rd, req_wid, req_tag}; `else - assign dcache_req_if.tag = mrq_write_addr; + assign dcache_req_if.tag = req_tag; `endif - // Can't accept new request - assign delay = mrq_full || !dcache_req_if.ready; + assign stall_in = ~dcache_req_if.ready || lsuq_full || store_stall; - // Core Response + // Can accept new request? + assign lsu_req_if.ready = ~stall_in; - reg [`NUM_THREADS-1:0][31:0] core_rsp_data; - wire [`NUM_THREADS-1:0][31:0] rsp_data_shifted; - - for (i = 0; i < `NUM_THREADS; i++) begin - assign rsp_data_shifted[i] = dcache_rsp_if.data[i] >> {mem_rsp_offset[i], 3'b0}; + // Core Response + for (genvar i = 0; i < `NUM_THREADS; i++) begin + wire [31:0] rsp_data_shifted = dcache_rsp_if.data[i] >> {rsp_offset[i], 3'b0}; always @(*) begin - case (core_rsp_mem_read) - `BYTE_EN_SB: core_rsp_data[i] = {{24{rsp_data_shifted[i][7]}}, rsp_data_shifted[i][7:0]}; - `BYTE_EN_SH: core_rsp_data[i] = {{16{rsp_data_shifted[i][15]}}, rsp_data_shifted[i][15:0]}; - `BYTE_EN_UB: core_rsp_data[i] = 32'(rsp_data_shifted[i][7:0]); - `BYTE_EN_UH: core_rsp_data[i] = 32'(rsp_data_shifted[i][15:0]); - default : core_rsp_data[i] = rsp_data_shifted[i]; + case (rsp_sext) + 1: rsp_data[i] = {{24{rsp_data_shifted[7]}}, rsp_data_shifted[7:0]}; + 2: rsp_data[i] = {{16{rsp_data_shifted[15]}}, rsp_data_shifted[15:0]}; + default: rsp_data[i] = rsp_data_shifted; endcase - end + end end - assign mem_wb_unqual_if.valid = dcache_rsp_if.valid; - assign mem_wb_unqual_if.data = core_rsp_data; + wire is_store_req = valid_in && ~lsuq_full && req_rw && dcache_req_if.ready; + wire is_load_rsp = (| dcache_rsp_if.valid); - // Can't accept new response - assign dcache_rsp_if.ready = !(no_slot_mem & (|mem_wb_if.valid)); + wire mem_rsp_stall = is_load_rsp && is_store_req; // arbitration prioritizes stores - // From LSU to WB - localparam WB_REQ_SIZE = (`NUM_THREADS) + (`NUM_THREADS * 32) + (`NW_BITS) + (5) + (2) + 32; - VX_generic_register #(.N(WB_REQ_SIZE)) lsu_to_wb ( + wire arb_valid = is_store_req || is_load_rsp; + wire [`NW_BITS-1:0] arb_wid = is_store_req ? req_wid : rsp_wid; + wire [`NUM_THREADS-1:0] arb_tmask = is_store_req ? req_tmask : dcache_rsp_if.valid; + wire [31:0] arb_PC = is_store_req ? req_pc : rsp_pc; + wire [`NR_BITS-1:0] arb_rd = is_store_req ? 0 : rsp_rd; + wire arb_wb = is_store_req ? 0 : rsp_wb; + + VX_generic_register #( + .N(1 + `NW_BITS + `NUM_THREADS + 32 + `NR_BITS + 1 + (`NUM_THREADS * 32)) + ) lsu_rsp_reg ( .clk (clk), .reset (reset), - .stall (no_slot_mem), + .stall (stall_out), .flush (1'b0), - .in ({mem_wb_unqual_if.valid, mem_wb_unqual_if.data, mem_wb_unqual_if.warp_num, mem_wb_unqual_if.rd, mem_wb_unqual_if.wb, mem_wb_unqual_if.curr_PC}), - .out ({mem_wb_if.valid, mem_wb_if.data, mem_wb_if.warp_num, mem_wb_if.rd, mem_wb_if.wb, mem_wb_if.curr_PC}) + .in ({arb_valid, arb_wid, arb_tmask, arb_PC, arb_rd, arb_wb, rsp_data}), + .out ({lsu_commit_if.valid, lsu_commit_if.wid, lsu_commit_if.tmask, lsu_commit_if.PC, lsu_commit_if.rd, lsu_commit_if.wb, lsu_commit_if.data}) ); - `SCOPE_ASSIGN(scope_dcache_req_valid, dcache_req_if.valid); - `SCOPE_ASSIGN(scope_dcache_req_warp_num, use_warp_num); - `SCOPE_ASSIGN(scope_dcache_req_curr_PC, use_pc); - `SCOPE_ASSIGN(scope_dcache_req_addr, use_address); - `SCOPE_ASSIGN(scope_dcache_req_rw, core_req_rw); - `SCOPE_ASSIGN(scope_dcache_req_byteen,dcache_req_if.byteen); - `SCOPE_ASSIGN(scope_dcache_req_data, dcache_req_if.data); - `SCOPE_ASSIGN(scope_dcache_req_tag, dcache_req_if.tag); - `SCOPE_ASSIGN(scope_dcache_req_ready, dcache_req_if.ready); + // Can accept new cache response? + assign dcache_rsp_if.ready = ~(stall_out || mem_rsp_stall); - `SCOPE_ASSIGN(scope_dcache_rsp_valid, dcache_rsp_if.valid); - `SCOPE_ASSIGN(scope_dcache_rsp_data, dcache_rsp_if.data); - `SCOPE_ASSIGN(scope_dcache_rsp_tag, dcache_rsp_if.tag); - `SCOPE_ASSIGN(scope_dcache_rsp_ready, dcache_rsp_if.ready); + // scope registration + `SCOPE_ASSIGN (scope_dcache_req_valid, dcache_req_if.valid); + `SCOPE_ASSIGN (scope_dcache_req_addr, req_address); + `SCOPE_ASSIGN (scope_dcache_req_rw, req_rw); + `SCOPE_ASSIGN (scope_dcache_req_byteen,dcache_req_if.byteen); + `SCOPE_ASSIGN (scope_dcache_req_data, dcache_req_if.data); + `SCOPE_ASSIGN (scope_dcache_req_tag, req_tag); + `SCOPE_ASSIGN (scope_dcache_req_ready, dcache_req_if.ready); + `SCOPE_ASSIGN (scope_dcache_req_wid, req_wid); + `SCOPE_ASSIGN (scope_dcache_req_pc, req_pc); + + `SCOPE_ASSIGN (scope_dcache_rsp_valid, dcache_rsp_if.valid); + `SCOPE_ASSIGN (scope_dcache_rsp_data, dcache_rsp_if.data); + `SCOPE_ASSIGN (scope_dcache_rsp_tag, rsp_tag); + `SCOPE_ASSIGN (scope_dcache_rsp_ready, dcache_rsp_if.ready); `ifdef DBG_PRINT_CORE_DCACHE always @(posedge clk) begin if ((| dcache_req_if.valid) && dcache_req_if.ready) begin - $display("%t: D%0d$ req: valid=%b, addr=%0h, tag=%0h, rw=%0b, pc=%0h, rd=%0d, warp=%0d, byteen=%0h, data=%0h", - $time, CORE_ID, use_valid, use_address, mrq_write_addr, use_req_rw, use_pc, use_rd, use_warp_num, use_req_byteen, use_req_data); + $display("%t: D$%0d req: wid=%0d, PC=%0h, tmask=%b, addr=%0h, tag=%0h, rd=%0d, rw=%0b, byteen=%0h, data=%0h", + $time, CORE_ID, req_wid, req_pc, dcache_req_if.valid, req_address, dcache_req_if.tag, req_rd, dcache_req_if.rw, dcache_req_if.byteen, dcache_req_if.data); end if ((| dcache_rsp_if.valid) && dcache_rsp_if.ready) begin - $display("%t: D%0d$ rsp: valid=%b, tag=%0h, pc=%0h, rd=%0d, warp=%0d, data=%0h", - $time, CORE_ID, mem_wb_unqual_if.valid, mrq_read_addr, mem_wb_unqual_if.curr_PC, mem_wb_unqual_if.rd, mem_wb_unqual_if.warp_num, mem_wb_unqual_if.data); + $display("%t: D$%0d rsp: valid=%b, wid=%0d, PC=%0h, tag=%0h, rd=%0d, data=%0h", + $time, CORE_ID, dcache_rsp_if.valid, rsp_wid, rsp_pc, dcache_rsp_if.tag, rsp_rd, dcache_rsp_if.data); end end `endif diff --git a/hw/rtl/VX_mem_arb.v b/hw/rtl/VX_mem_arb.v index edf6741c..f8c5ac37 100644 --- a/hw/rtl/VX_mem_arb.v +++ b/hw/rtl/VX_mem_arb.v @@ -83,15 +83,13 @@ module VX_mem_arb #( assign out_mem_req_data = in_mem_req_data [bus_req_sel]; assign out_mem_req_tag = {in_mem_req_tag [bus_req_sel], REQS_BITS'(bus_req_sel)}; - genvar i; - - for (i = 0; i < NUM_REQUESTS; i++) begin + for (genvar i = 0; i < NUM_REQUESTS; i++) begin assign in_mem_req_ready[i] = out_mem_req_ready && (bus_req_sel == REQS_BITS'(i)); end wire [REQS_BITS-1:0] bus_rsp_sel = out_mem_rsp_tag[REQS_BITS-1:0]; - for (i = 0; i < NUM_REQUESTS; i++) begin + for (genvar i = 0; i < NUM_REQUESTS; i++) begin assign in_mem_rsp_valid[i] = out_mem_rsp_valid && (bus_rsp_sel == REQS_BITS'(i)); assign in_mem_rsp_data[i] = out_mem_rsp_data; assign in_mem_rsp_tag[i] = out_mem_rsp_tag[REQS_BITS +: TAG_IN_WIDTH]; diff --git a/hw/rtl/VX_mem_unit.v b/hw/rtl/VX_mem_unit.v index af626723..fbcee41f 100644 --- a/hw/rtl/VX_mem_unit.v +++ b/hw/rtl/VX_mem_unit.v @@ -40,18 +40,20 @@ module VX_mem_unit # ( .CORE_TAG_ID_BITS (`DCORE_TAG_ID_BITS) ) core_dcache_rsp_qual_if(), core_smem_rsp_if(); - // select shared memory address - wire is_smem_addr = (({core_dcache_req_if.addr[0], 2'b0} - `SHARED_MEM_BASE_ADDR) <= `SCACHE_SIZE); - wire smem_select = (| core_dcache_req_if.valid) ? is_smem_addr : 0; + // select shared memory bus + wire is_smem_addr = (({core_dcache_req_if.addr[0], 2'b0} - `SHARED_MEM_BASE_ADDR) <= `SCACHE_SIZE); + wire smem_req_select = (| core_dcache_req_if.valid) ? is_smem_addr : 0; + wire smem_rsp_select = (| core_smem_rsp_if.valid); - VX_dcache_arb dcache_smem_arb ( - .req_select (smem_select), - .in_core_req_if (core_dcache_req_if), - .out0_core_req_if (core_dcache_req_qual_if), - .out1_core_req_if (core_smem_req_if), - .in0_core_rsp_if (core_dcache_rsp_qual_if), - .in1_core_rsp_if (core_smem_rsp_if), - .out_core_rsp_if (core_dcache_rsp_if) + VX_dcache_arb dcache_smem_arb ( + .core_req_in_if (core_dcache_req_if), + .core_req_out0_if (core_dcache_req_qual_if), + .core_req_out1_if (core_smem_req_if), + .core_rsp_in0_if (core_dcache_rsp_qual_if), + .core_rsp_in1_if (core_smem_rsp_if), + .core_rsp_out_if (core_dcache_rsp_if), + .select_req (smem_req_select), + .select_rsp (smem_rsp_select) ); VX_cache #( @@ -61,7 +63,6 @@ module VX_mem_unit # ( .NUM_BANKS (`SNUM_BANKS), .WORD_SIZE (`SWORD_SIZE), .NUM_REQUESTS (`SNUM_REQUESTS), - .STAGE_1_CYCLES (`SSTAGE_1_CYCLES), .CREQ_SIZE (`SCREQ_SIZE), .MRVQ_SIZE (8), .DFPQ_SIZE (1), @@ -145,7 +146,6 @@ module VX_mem_unit # ( .NUM_BANKS (`DNUM_BANKS), .WORD_SIZE (`DWORD_SIZE), .NUM_REQUESTS (`DNUM_REQUESTS), - .STAGE_1_CYCLES (`DSTAGE_1_CYCLES), .CREQ_SIZE (`DCREQ_SIZE), .MRVQ_SIZE (`DMRVQ_SIZE), .DFPQ_SIZE (`DDFPQ_SIZE), @@ -230,7 +230,6 @@ module VX_mem_unit # ( .NUM_BANKS (`INUM_BANKS), .WORD_SIZE (`IWORD_SIZE), .NUM_REQUESTS (`INUM_REQUESTS), - .STAGE_1_CYCLES (`ISTAGE_1_CYCLES), .CREQ_SIZE (`ICREQ_SIZE), .MRVQ_SIZE (`IMRVQ_SIZE), .DFPQ_SIZE (`IDFPQ_SIZE), @@ -243,8 +242,8 @@ module VX_mem_unit # ( .SNOOP_FORWARDING (0), .DRAM_ENABLE (1), .WRITE_ENABLE (0), - .CORE_TAG_WIDTH (`DCORE_TAG_WIDTH), - .CORE_TAG_ID_BITS (`DCORE_TAG_ID_BITS), + .CORE_TAG_WIDTH (`ICORE_TAG_WIDTH), + .CORE_TAG_ID_BITS (`ICORE_TAG_ID_BITS), .DRAM_TAG_WIDTH (`IDRAM_TAG_WIDTH) ) icache ( `SCOPE_SIGNALS_CACHE_UNBIND diff --git a/hw/rtl/VX_mul_unit.v b/hw/rtl/VX_mul_unit.v new file mode 100644 index 00000000..fb679451 --- /dev/null +++ b/hw/rtl/VX_mul_unit.v @@ -0,0 +1,165 @@ +`include "VX_define.vh" + +module VX_mul_unit #( + parameter CORE_ID = 0 +) ( + input wire clk, + input wire reset, + + // Inputs + VX_mul_req_if mul_req_if, + + // Outputs + VX_exu_to_cmt_if mul_commit_if +); + localparam MULQ_BITS = `LOG2UP(`MULQ_SIZE); + + wire [`MUL_BITS-1:0] alu_op = mul_req_if.op_type; + wire is_div_op = `IS_DIV_OP(alu_op); + wire [`NUM_THREADS-1:0][31:0] alu_in1 = mul_req_if.rs1_data; + wire [`NUM_THREADS-1:0][31:0] alu_in2 = mul_req_if.rs2_data; + + wire [`NW_BITS-1:0] rsp_wid; + wire [`NUM_THREADS-1:0] rsp_tmask; + wire [31:0] rsp_PC; + wire [`NR_BITS-1:0] rsp_rd; + wire rsp_wb; + wire [MULQ_BITS-1:0] tag_in, tag_out; + wire valid_out; + wire stall_out; + wire mulq_full; + + wire mulq_push = mul_req_if.valid && mul_req_if.ready; + wire mulq_pop = valid_out && ~stall_out; + + VX_cam_buffer #( + .DATAW (`NW_BITS + `NUM_THREADS + 32 + `NR_BITS + 1), + .SIZE (`MULQ_SIZE) + ) mul_cam ( + .clk (clk), + .reset (reset), + .acquire_slot (mulq_push), + .write_addr (tag_in), + .read_addr (tag_out), + .release_addr (tag_out), + .write_data ({mul_req_if.wid, mul_req_if.tmask, mul_req_if.PC, mul_req_if.rd, mul_req_if.wb}), + .read_data ({rsp_wid, rsp_tmask, rsp_PC, rsp_rd, rsp_wb}), + .release_slot (mulq_pop), + .full (mulq_full) + ); + + /////////////////////////////////////////////////////////////////////////// + + wire [`NUM_THREADS-1:0][31:0] mul_result; + wire is_mul_in = (alu_op == `MUL_MUL); + wire is_mul_out; + wire stall_mul; + + for (genvar i = 0; i < `NUM_THREADS; i++) begin + + wire [32:0] mul_in1 = {(alu_op != `MUL_MULHU) & alu_in1[i][31], alu_in1[i]}; + wire [32:0] mul_in2 = {(alu_op != `MUL_MULHU && alu_op != `MUL_MULHSU) & alu_in2[i][31], alu_in2[i]}; + `IGNORE_WARNINGS_BEGIN + wire [65:0] mul_result_tmp; + `IGNORE_WARNINGS_END + + VX_multiplier #( + .WIDTHA(33), + .WIDTHB(33), + .WIDTHP(66), + .SIGNED(1), + .LATENCY(`LATENCY_IMUL) + ) multiplier ( + .clk(clk), + .enable(~stall_mul), + .dataa(mul_in1), + .datab(mul_in2), + .result(mul_result_tmp) + ); + + assign mul_result[i] = is_mul_out ? mul_result_tmp[31:0] : mul_result_tmp[63:32]; + end + + wire [MULQ_BITS-1:0] mul_tag; + wire mul_valid_out; + + wire mul_fire = mul_req_if.valid && mul_req_if.ready && !is_div_op; + + VX_shift_register #( + .DATAW(1 + MULQ_BITS + 1), + .DEPTH(`LATENCY_IMUL) + ) mul_shift_reg ( + .clk(clk), + .reset(reset), + .enable(~stall_mul), + .in({mul_fire, tag_in, is_mul_in}), + .out({mul_valid_out, mul_tag, is_mul_out}) + ); + + /////////////////////////////////////////////////////////////////////////// + + wire [`NUM_THREADS-1:0][31:0] div_result_tmp, rem_result_tmp; + + wire is_div_only = (alu_op == `MUL_DIV) || (alu_op == `MUL_DIVU); + wire is_signed_div = (alu_op == `MUL_DIV) || (alu_op == `MUL_REM); + wire div_valid_in = mul_req_if.valid && is_div_op; + wire div_ready_in; + wire div_ready_out; + wire div_valid_out; + wire is_div_out; + wire [MULQ_BITS-1:0] div_tag; + + VX_serial_div #( + .WIDTHN(32), + .WIDTHD(32), + .WIDTHQ(32), + .WIDTHR(32), + .LANES(`NUM_THREADS), + .TAGW(MULQ_BITS + 1) + ) divide ( + .clk(clk), + .reset(reset), + .ready_in(div_ready_in), + .valid_in(div_valid_in), + .signed_mode(is_signed_div), + .tag_in({tag_in, is_div_only}), + .numer(alu_in1), + .denom(alu_in2), + .quotient(div_result_tmp), + .remainder(rem_result_tmp), + .ready_out(div_ready_out), + .valid_out(div_valid_out), + .tag_out({div_tag, is_div_out}) + ); + + wire [`NUM_THREADS-1:0][31:0] div_result = is_div_out ? div_result_tmp : rem_result_tmp; + + /////////////////////////////////////////////////////////////////////////// + + wire arbiter_hazard = mul_valid_out && div_valid_out; + + assign stall_out = ~mul_commit_if.ready && mul_commit_if.valid; + assign stall_mul = (stall_out && !is_div_op) || mulq_full; + assign div_ready_out = ~stall_out && ~arbiter_hazard; // arbitration prioritizes MUL + wire stall_in = stall_mul || ~div_ready_in; + + assign valid_out = mul_valid_out || div_valid_out; + assign tag_out = mul_valid_out ? mul_tag : div_tag; + + wire [`NUM_THREADS-1:0][31:0] result = mul_valid_out ? mul_result : div_result; + + VX_generic_register #( + .N(1 + `NW_BITS + `NUM_THREADS + 32 + `NR_BITS + 1 + (`NUM_THREADS * 32)) + ) mul_reg ( + .clk (clk), + .reset (reset), + .stall (stall_out), + .flush (1'b0), + .in ({valid_out, rsp_wid, rsp_tmask, rsp_PC, rsp_rd, rsp_wb, result}), + .out ({mul_commit_if.valid, mul_commit_if.wid, mul_commit_if.tmask, mul_commit_if.PC, mul_commit_if.rd, mul_commit_if.wb, mul_commit_if.data}) + ); + + // can accept new request? + assign mul_req_if.ready = ~stall_in; + +endmodule \ No newline at end of file diff --git a/hw/rtl/VX_pipeline.v b/hw/rtl/VX_pipeline.v index 72c6ee2d..df290d5d 100644 --- a/hw/rtl/VX_pipeline.v +++ b/hw/rtl/VX_pipeline.v @@ -5,8 +5,8 @@ module VX_pipeline #( ) ( `SCOPE_SIGNALS_ISTAGE_IO `SCOPE_SIGNALS_LSU_IO - `SCOPE_SIGNALS_PIPELINE_IO - `SCOPE_SIGNALS_BE_IO + `SCOPE_SIGNALS_ISSUE_IO + `SCOPE_SIGNALS_EXECUTE_IO // Clock input wire clk, @@ -58,16 +58,6 @@ module VX_pipeline #( output wire busy, output wire ebreak ); - -`DEBUG_BEGIN - wire scheduler_empty; -`DEBUG_END - - wire memory_delay; - wire exec_delay; - wire gpr_stage_delay; - wire schedule_delay; - // Dcache VX_cache_core_req_if #( .NUM_REQUESTS(`NUM_THREADS), @@ -98,7 +88,6 @@ module VX_pipeline #( .CORE_TAG_ID_BITS(`ICORE_TAG_ID_BITS) ) core_icache_rsp_if(); - // CSR I/O VX_csr_io_req_if csr_io_req_if(); assign csr_io_req_if.valid = csr_io_req_valid; @@ -112,69 +101,127 @@ module VX_pipeline #( assign csr_io_rsp_data = csr_io_rsp_if.data; assign csr_io_rsp_if.ready = csr_io_rsp_ready; - // Front-end to Back-end - VX_backend_req_if bckE_req_if(); - - // Back-end to Front-end - VX_wb_if writeback_if(); - VX_branch_rsp_if branch_rsp_if(); - VX_jal_rsp_if jal_rsp_if(); - - // Warp controls + VX_csr_to_issue_if csr_to_issue_if(); + VX_cmt_to_csr_if cmt_to_csr_if(); + VX_decode_if decode_if(); + VX_branch_ctl_if branch_ctl_if(); VX_warp_ctl_if warp_ctl_if(); + VX_ifetch_rsp_if ifetch_rsp_if(); + VX_alu_req_if alu_req_if(); + VX_lsu_req_if lsu_req_if(); + VX_csr_req_if csr_req_if(); + VX_mul_req_if mul_req_if(); + VX_fpu_req_if fpu_req_if(); + VX_gpu_req_if gpu_req_if(); + VX_writeback_if writeback_if(); + VX_wstall_if wstall_if(); + VX_join_if join_if(); + VX_exu_to_cmt_if alu_commit_if(); + VX_exu_to_cmt_if lsu_commit_if(); + VX_exu_to_cmt_if csr_commit_if(); + VX_exu_to_cmt_if mul_commit_if(); + VX_fpu_to_cmt_if fpu_commit_if(); + VX_exu_to_cmt_if gpu_commit_if(); - VX_front_end #( + VX_fetch #( .CORE_ID(CORE_ID) - ) front_end ( + ) fetch ( `SCOPE_SIGNALS_ISTAGE_BIND - .clk (clk), .reset (reset), - .warp_ctl_if (warp_ctl_if), - .bckE_req_if (bckE_req_if), - .schedule_delay (schedule_delay), - .icache_rsp_if (core_icache_rsp_if), .icache_req_if (core_icache_req_if), - .jal_rsp_if (jal_rsp_if), - .branch_rsp_if (branch_rsp_if), + .icache_rsp_if (core_icache_rsp_if), + .wstall_if (wstall_if), + .join_if (join_if), + .warp_ctl_if (warp_ctl_if), + .branch_ctl_if (branch_ctl_if), + .ifetch_rsp_if (ifetch_rsp_if), .busy (busy) ); - VX_scheduler scheduler ( + VX_decode #( + .CORE_ID(CORE_ID) + ) decode ( + .clk (clk), + .reset (reset), + .ifetch_rsp_if (ifetch_rsp_if), + .decode_if (decode_if), + .wstall_if (wstall_if), + .join_if (join_if) + ); + + VX_issue #( + .CORE_ID(CORE_ID) + ) issue ( + `SCOPE_SIGNALS_ISSUE_BIND + + .clk (clk), + .reset (reset), + + .decode_if (decode_if), + .writeback_if (writeback_if), + .csr_to_issue_if(csr_to_issue_if), + + .alu_req_if (alu_req_if), + .lsu_req_if (lsu_req_if), + .csr_req_if (csr_req_if), + .mul_req_if (mul_req_if), + .fpu_req_if (fpu_req_if), + .gpu_req_if (gpu_req_if) + ); + + VX_execute #( + .CORE_ID(CORE_ID) + ) execute ( + `SCOPE_SIGNALS_LSU_BIND + `SCOPE_SIGNALS_EXECUTE_BIND + .clk (clk), + .reset (reset), + + .dcache_req_if (core_dcache_req_if), + .dcache_rsp_if (core_dcache_rsp_if), + + .csr_io_req_if (csr_io_req_if), + .csr_io_rsp_if (csr_io_rsp_if), + + .csr_to_issue_if(csr_to_issue_if), + .cmt_to_csr_if (cmt_to_csr_if), + + .alu_req_if (alu_req_if), + .lsu_req_if (lsu_req_if), + .csr_req_if (csr_req_if), + .mul_req_if (mul_req_if), + .fpu_req_if (fpu_req_if), + .gpu_req_if (gpu_req_if), + + .warp_ctl_if (warp_ctl_if), + .branch_ctl_if (branch_ctl_if), + .alu_commit_if (alu_commit_if), + .lsu_commit_if (lsu_commit_if), + .csr_commit_if (csr_commit_if), + .mul_commit_if (mul_commit_if), + .fpu_commit_if (fpu_commit_if), + .gpu_commit_if (gpu_commit_if), + + .ebreak (ebreak) + ); + + VX_commit #( + .CORE_ID(CORE_ID) + ) commit ( .clk (clk), .reset (reset), - .memory_delay (memory_delay), - .exec_delay (exec_delay), - .gpr_stage_delay(gpr_stage_delay), - .bckE_req_if (bckE_req_if), + + .alu_commit_if (alu_commit_if), + .lsu_commit_if (lsu_commit_if), + .csr_commit_if (csr_commit_if), + .mul_commit_if (mul_commit_if), + .fpu_commit_if (fpu_commit_if), + .gpu_commit_if (gpu_commit_if), + .writeback_if (writeback_if), - .schedule_delay (schedule_delay), - .is_empty (scheduler_empty) - ); - - VX_back_end #( - .CORE_ID(CORE_ID) - ) back_end ( - `SCOPE_SIGNALS_LSU_BIND - `SCOPE_SIGNALS_BE_BIND - - .clk (clk), - .reset (reset), - .csr_io_req_if (csr_io_req_if), - .csr_io_rsp_if (csr_io_rsp_if), - .schedule_delay (schedule_delay), - .warp_ctl_if (warp_ctl_if), - .bckE_req_if (bckE_req_if), - .jal_rsp_if (jal_rsp_if), - .branch_rsp_if (branch_rsp_if), - .dcache_req_if (core_dcache_req_if), - .dcache_rsp_if (core_dcache_rsp_if), - .writeback_if (writeback_if), - .mem_delay (memory_delay), - .exec_delay (exec_delay), - .gpr_stage_delay (gpr_stage_delay), - .ebreak (ebreak) - ); + .cmt_to_csr_if (cmt_to_csr_if) + ); assign dcache_req_valid = core_dcache_req_if.valid; assign dcache_req_rw = core_dcache_req_if.rw; @@ -202,21 +249,4 @@ module VX_pipeline #( assign core_icache_rsp_if.tag = icache_rsp_tag; assign icache_rsp_ready = core_icache_rsp_if.ready; - `SCOPE_ASSIGN(scope_busy, busy); - `SCOPE_ASSIGN(scope_schedule_delay, schedule_delay); - `SCOPE_ASSIGN(scope_memory_delay, memory_delay); - `SCOPE_ASSIGN(scope_exec_delay, exec_delay); - `SCOPE_ASSIGN(scope_gpr_stage_delay, gpr_stage_delay); - -`ifdef DBG_PRINT_PIPELINE - always @(posedge clk) begin - if ((| writeback_if.valid) && (writeback_if.wb != 0)) begin - $display("%t: Core%0d-WB: warp=%0d, rd=%0d, data=%0h", $time, CORE_ID, writeback_if.warp_num, writeback_if.rd, writeback_if.data); - end - if (schedule_delay || memory_delay || exec_delay || gpr_stage_delay) begin - $display("%t: Core%0d-Delay: sched=%b, mem=%b, exec=%b, gpr=%b ", $time, CORE_ID, schedule_delay, memory_delay, exec_delay, gpr_stage_delay); - end - end -`endif - endmodule diff --git a/hw/rtl/VX_platform.vh b/hw/rtl/VX_platform.vh new file mode 100644 index 00000000..3f158408 --- /dev/null +++ b/hw/rtl/VX_platform.vh @@ -0,0 +1,67 @@ +`ifndef VX_PLATFORM +`define VX_PLATFORM + +`include "VX_scope.vh" + +/////////////////////////////////////////////////////////////////////////////// + +`ifndef NDEBUG + `define DEBUG_BLOCK(x) /* verilator lint_off UNUSED */ \ + x \ + /* verilator lint_on UNUSED */ +`else + `define DEBUG_BLOCK(x) +`endif + +`define DEBUG_BEGIN /* verilator lint_off UNUSED */ + +`define DEBUG_END /* verilator lint_on UNUSED */ + +`define IGNORE_WARNINGS_BEGIN /* verilator lint_off UNUSED */ \ + /* verilator lint_off PINCONNECTEMPTY */ \ + /* verilator lint_off WIDTH */ \ + /* verilator lint_off UNOPTFLAT */ \ + /* verilator lint_off UNDRIVEN */ \ + /* verilator lint_off DECLFILENAME */ + +`define IGNORE_WARNINGS_END /* verilator lint_on UNUSED */ \ + /* verilator lint_on PINCONNECTEMPTY */ \ + /* verilator lint_on WIDTH */ \ + /* verilator lint_on UNOPTFLAT */ \ + /* verilator lint_on UNDRIVEN */ \ + /* verilator lint_on DECLFILENAME */ + +`define UNUSED_VAR(x) always @(x) begin end + +`define UNUSED_PIN(x) /* verilator lint_off PINCONNECTEMPTY */ \ + . x () \ + /* verilator lint_on PINCONNECTEMPTY */ + +`define STRINGIFY(x) `"x`" + +`define STATIC_ASSERT(cond, msg) \ + generate \ + if (!(cond)) $error(msg); \ + endgenerate + +`define ENABLE_TRACING /* verilator tracing_on */ +`define DISABLE_TRACING /* verilator tracing_off */ + +/////////////////////////////////////////////////////////////////////////////// + +`define USE_FAST_BRAM (* syn_ramstyle = "mlab" *) +`define RELAX_BRAM_RW (* syn_ramstyle = "no_rw_check" *) + +/////////////////////////////////////////////////////////////////////////////// + +`define CLOG2(x) $clog2(x) +`define FLOG2(x) ($clog2(x) - (((1 << $clog2(x)) > (x)) ? 1 : 0)) +`define LOG2UP(x) (((x) > 1) ? $clog2(x) : 1) +`define ISPOW2(x) (((x) != 0) && (0 == ((x) & ((x) - 1)))) + +`define MIN(x, y) ((x < y) ? (x) : (y)) +`define MAX(x, y) ((x > y) ? (x) : (y)) + +`define UP(x) (((x) > 0) ? x : 1) + +`endif \ No newline at end of file diff --git a/hw/rtl/VX_print_instr.vh b/hw/rtl/VX_print_instr.vh new file mode 100644 index 00000000..68fd8756 --- /dev/null +++ b/hw/rtl/VX_print_instr.vh @@ -0,0 +1,144 @@ +`ifndef VX_PRINT_INSTR +`define VX_PRINT_INSTR + +`include "VX_define.vh" + +task print_ex_type; + input [`EX_BITS-1:0] ex; + begin + case (ex) + `EX_ALU: $write("ALU"); + `EX_LSU: $write("LSU"); + `EX_CSR: $write("CSR"); + `EX_MUL: $write("MUL"); + `EX_FPU: $write("FPU"); + `EX_GPU: $write("GPU"); + default: $write("NOP"); + endcase + end +endtask + +task print_ex_op; + input [`EX_BITS-1:0] ex_type; + input [`OP_BITS-1:0] op_type; + input [`MOD_BITS-1:0] op_mod; + begin + case (ex_type) + `EX_ALU: begin + if (`IS_BR_MOD(op_mod)) begin + case (`BR_BITS'(op_type)) + `BR_EQ: $write("BEQ"); + `BR_NE: $write("BNE"); + `BR_LT: $write("BLT"); + `BR_GE: $write("BGE"); + `BR_LTU: $write("BLTU"); + `BR_GEU: $write("BGEU"); + `BR_JAL: $write("JAL"); + `BR_JALR: $write("JALR"); + `BR_ECALL: $write("ECALL"); + `BR_EBREAK:$write("EBREAK"); + `BR_MRET: $write("MRET"); + `BR_SRET: $write("SRET"); + `BR_DRET: $write("DRET"); + default: $write("?"); + endcase + end else begin + case (`ALU_BITS'(op_type)) + `ALU_ADD: $write("ADD"); + `ALU_SUB: $write("SUB"); + `ALU_SLL: $write("SLL"); + `ALU_SRL: $write("SRL"); + `ALU_SRA: $write("SRA"); + `ALU_SLT: $write("SLT"); + `ALU_SLTU: $write("SLTU"); + `ALU_XOR: $write("XOR"); + `ALU_OR: $write("OR"); + `ALU_AND: $write("AND"); + `ALU_LUI: $write("LUI"); + `ALU_AUIPC: $write("AUIPC"); + default: $write("?"); + endcase + end + end + `EX_LSU: begin + case (`LSU_BITS'(op_type)) + `LSU_LB: $write("LB"); + `LSU_LH: $write("LH"); + `LSU_LW: $write("LW"); + `LSU_LBU: $write("LBU"); + `LSU_LHU: $write("LHU"); + `LSU_SB: $write("SB"); + `LSU_SH: $write("SH"); + `LSU_SW: $write("SW"); + `LSU_SBU: $write("SBU"); + `LSU_SHU: $write("SHU"); + default: $write("?"); + endcase + end + `EX_CSR: begin + case (`CSR_BITS'(op_type)) + `CSR_RW: $write("CSRW"); + `CSR_RS: $write("CSRS"); + `CSR_RC: $write("CSRC"); + default: $write("?"); + endcase + end + `EX_MUL: begin + case (`MUL_BITS'(op_type)) + `MUL_MUL: $write("MUL"); + `MUL_MULH: $write("MULH"); + `MUL_MULHSU:$write("MULHSU"); + `MUL_MULHU: $write("MULHU"); + `MUL_DIV: $write("DIV"); + `MUL_DIVU: $write("DIVU"); + `MUL_REM: $write("REM"); + `MUL_REMU: $write("REMU"); + default: $write("?"); + endcase + end + `EX_FPU: begin + case (`FPU_BITS'(op_type)) + `FPU_ADD: $write("ADD"); + `FPU_SUB: $write("SUB"); + `FPU_MUL: $write("MUL"); + `FPU_DIV: $write("DIV"); + `FPU_SQRT: $write("SQRT"); + `FPU_MADD: $write("MADD"); + `FPU_NMSUB: $write("NMSUB"); + `FPU_NMADD: $write("NMADD"); + `FPU_CVTWS: $write("CVTWS"); + `FPU_CVTWUS:$write("CVTWUS"); + `FPU_CVTSW: $write("CVTSW"); + `FPU_CVTSWU:$write("CVTSWU"); + `FPU_CLASS: $write("CLASS"); + `FPU_CMP: $write("CMP"); + `FPU_MISC: begin + case (op_mod) + 0: $write("SGNJ"); + 1: $write("SGNJN"); + 2: $write("SGNJX"); + 3: $write("MIN"); + 4: $write("MAX"); + 5: $write("MVXW"); + 6: $write("MVWX"); + endcase + end + default: $write("?"); + endcase + end + `EX_GPU: begin + case (`GPU_BITS'(op_type)) + `GPU_TMC: $write("TMC"); + `GPU_WSPAWN:$write("WSPAWN"); + `GPU_SPLIT: $write("SPLIT"); + `GPU_JOIN: $write("JOIN"); + `GPU_BAR: $write("BAR"); + default: $write("?"); + endcase + end + default:; + endcase + end +endtask + +`endif diff --git a/hw/rtl/VX_scheduler.v b/hw/rtl/VX_scheduler.v deleted file mode 100644 index 52810bcc..00000000 --- a/hw/rtl/VX_scheduler.v +++ /dev/null @@ -1,83 +0,0 @@ -`include "VX_define.vh" - -module VX_scheduler ( - input wire clk, - input wire reset, - input wire memory_delay, - input wire exec_delay, - input wire gpr_stage_delay, - - VX_backend_req_if bckE_req_if, - VX_wb_if writeback_if, - - output wire schedule_delay, - output wire is_empty -); - localparam CTVW = `CLOG2(`NUM_WARPS * 32 + 1); - - reg [31:0][`NUM_THREADS-1:0] rename_table[`NUM_WARPS-1:0]; - reg [CTVW-1:0] count_valid; - - wire is_store = (bckE_req_if.mem_write != `BYTE_EN_NO); - wire is_load = (bckE_req_if.mem_read != `BYTE_EN_NO); - wire is_mem = (is_store || is_load); - wire is_gpu = (bckE_req_if.is_wspawn || bckE_req_if.is_tmc || bckE_req_if.is_barrier || bckE_req_if.is_split); - wire is_csr = bckE_req_if.is_csr; - wire is_exec = !is_mem && !is_gpu && !is_csr; - - wire using_rs2 = is_store - || (bckE_req_if.rs2_src == `RS2_REG) - || bckE_req_if.is_barrier - || bckE_req_if.is_wspawn; - - wire rs1_rename = (rename_table[bckE_req_if.warp_num][bckE_req_if.rs1] != 0); - wire rs2_rename = (rename_table[bckE_req_if.warp_num][bckE_req_if.rs2] != 0); - wire rd_rename = (rename_table[bckE_req_if.warp_num][bckE_req_if.rd ] != 0); - - wire rs1_rename_qual = (rs1_rename) && (bckE_req_if.rs1 != 0); - wire rs2_rename_qual = (rs2_rename) && (bckE_req_if.rs2 != 0 && using_rs2); - wire rd_rename_qual = (rd_rename) && (bckE_req_if.rd != 0); - - wire rename_valid = rs1_rename_qual || rs2_rename_qual || rd_rename_qual; - - assign schedule_delay = (| bckE_req_if.valid) - && ((rename_valid) - || (memory_delay && is_mem) - || (gpr_stage_delay && (is_mem || is_exec)) - || (exec_delay && is_exec)); - - assign is_empty = (count_valid == 0); - - integer i, w; - - wire acquire_rd = (| bckE_req_if.valid) && (bckE_req_if.wb != 0) && (bckE_req_if.rd != 0) && !schedule_delay; - - wire release_rd = (| writeback_if.valid) && (writeback_if.wb != 0) && (writeback_if.rd != 0); - - wire [`NUM_THREADS-1:0] valid_wb_new_mask = rename_table[writeback_if.warp_num][writeback_if.rd] & ~writeback_if.valid; - - reg [CTVW-1:0] count_valid_next = (acquire_rd && !(release_rd && (0 == valid_wb_new_mask))) ? (count_valid + 1) : - (~acquire_rd && (release_rd && (0 == valid_wb_new_mask))) ? (count_valid - 1) : - count_valid; - - always @(posedge clk) begin - if (reset) begin - for (w = 0; w < `NUM_WARPS; w++) begin - for (i = 0; i < 32; i++) begin - rename_table[w][i] <= 0; - end - end - count_valid <= 0; - end else begin - if (acquire_rd) begin - rename_table[bckE_req_if.warp_num][bckE_req_if.rd] <= bckE_req_if.valid; - end - if (release_rd) begin - assert(rename_table[writeback_if.warp_num][writeback_if.rd] != 0); - rename_table[writeback_if.warp_num][writeback_if.rd] <= valid_wb_new_mask; - end - count_valid <= count_valid_next; - end - end - -endmodule \ No newline at end of file diff --git a/hw/rtl/VX_scope.vh b/hw/rtl/VX_scope.vh index 972286ae..fa595c56 100644 --- a/hw/rtl/VX_scope.vh +++ b/hw/rtl/VX_scope.vh @@ -15,13 +15,13 @@ scope_snp_req_invalidate, \ scope_snp_req_tag, \ scope_snp_rsp_tag, \ - scope_icache_req_warp_num, \ + scope_icache_req_wid, \ scope_icache_req_addr, \ scope_icache_req_tag, \ scope_icache_rsp_data, \ scope_icache_rsp_tag, \ - scope_dcache_req_warp_num, \ - scope_dcache_req_curr_PC, \ + scope_dcache_req_wid, \ + scope_dcache_req_pc, \ scope_dcache_req_addr, \ scope_dcache_req_rw, \ scope_dcache_req_byteen, \ @@ -29,19 +29,27 @@ scope_dcache_req_tag, \ scope_dcache_rsp_data, \ scope_dcache_rsp_tag, \ - scope_decode_warp_num, \ - scope_decode_curr_PC, \ - scope_decode_is_jal, \ - scope_decode_rs1, \ - scope_decode_rs2, \ - scope_execute_warp_num, \ - scope_execute_curr_PC, \ - scope_execute_rd, \ - scope_execute_a, \ - scope_execute_b, \ - scope_writeback_warp_num, \ - scope_writeback_curr_PC, \ - scope_writeback_wb, \ + scope_issue_wid, \ + scope_issue_tmask, \ + scope_issue_pc, \ + scope_issue_ex_type, \ + scope_issue_op_type, \ + scope_issue_op_mod, \ + scope_issue_wb, \ + scope_issue_rd, \ + scope_issue_rs1, \ + scope_issue_rs2, \ + scope_issue_rs3, \ + scope_issue_imm, \ + scope_issue_rs1_is_pc, \ + scope_issue_rs2_is_imm, \ + scope_gpr_rsp_wid, \ + scope_gpr_rsp_pc, \ + scope_gpr_rsp_a, \ + scope_gpr_rsp_b, \ + scope_gpr_rsp_c, \ + scope_writeback_wid, \ + scope_writeback_pc, \ scope_writeback_rd, \ scope_writeback_data, \ scope_bank_addr_st0, \ @@ -51,7 +59,6 @@ scope_bank_miss_st1, \ scope_bank_dirty_st1, \ scope_bank_force_miss_st1, - `define SCOPE_SIGNALS_UPD_LIST \ scope_dram_req_valid, \ @@ -70,18 +77,18 @@ scope_dcache_req_ready, \ scope_dcache_rsp_valid, \ scope_dcache_rsp_ready, \ - scope_decode_valid, \ - scope_execute_valid, \ - scope_writeback_valid, \ - scope_schedule_delay, \ - scope_memory_delay, \ - scope_exec_delay, \ - scope_gpr_stage_delay, \ - scope_busy, \ scope_bank_valid_st0, \ scope_bank_valid_st1, \ scope_bank_valid_st2, \ - scope_bank_stall_pipe + scope_bank_stall_pipe, \ + scope_issue_valid, \ + scope_issue_ready, \ + scope_gpr_rsp_valid, \ + scope_writeback_valid, \ + scope_scoreboard_delay, \ + scope_gpr_delay, \ + scope_execute_delay, \ + scope_busy `define SCOPE_SIGNALS_DECL \ wire scope_dram_req_valid; \ @@ -103,51 +110,53 @@ wire scope_snp_rsp_valid; \ wire [`VX_SNP_TAG_WIDTH-1:0] scope_snp_rsp_tag; \ wire scope_icache_req_valid; \ - wire [`NW_BITS-1:0] scope_icache_req_warp_num; \ + wire [`NW_BITS-1:0] scope_icache_req_wid; \ wire [31:0] scope_icache_req_addr; \ - wire [`ICORE_TAG_WIDTH-1:0] scope_icache_req_tag; \ + wire [`ICORE_TAG_ID_BITS-1:0] scope_icache_req_tag; \ wire scope_icache_req_ready; \ wire scope_icache_rsp_valid; \ wire [31:0] scope_icache_rsp_data; \ - wire [`ICORE_TAG_WIDTH-1:0] scope_icache_rsp_tag; \ + wire [`ICORE_TAG_ID_BITS-1:0] scope_icache_rsp_tag; \ wire scope_icache_rsp_ready; \ wire [`NUM_THREADS-1:0] scope_dcache_req_valid; \ - wire [`NW_BITS-1:0] scope_dcache_req_warp_num; \ - wire [31:0] scope_dcache_req_curr_PC; \ - wire [63:0] scope_dcache_req_addr; \ + wire [`NW_BITS-1:0] scope_dcache_req_wid; \ + wire [31:0] scope_dcache_req_pc; \ + wire [`NUM_THREADS-1:0][31:0] scope_dcache_req_addr; \ wire scope_dcache_req_rw; \ - wire [7:0] scope_dcache_req_byteen; \ - wire [63:0] scope_dcache_req_data; \ - wire [`DCORE_TAG_WIDTH-1:0] scope_dcache_req_tag; \ + wire [`NUM_THREADS-1:0][3:0] scope_dcache_req_byteen; \ + wire [`NUM_THREADS-1:0][31:0] scope_dcache_req_data; \ + wire [`DCORE_TAG_ID_BITS-1:0] scope_dcache_req_tag; \ wire scope_dcache_req_ready; \ wire [`NUM_THREADS-1:0] scope_dcache_rsp_valid; \ - wire [63:0] scope_dcache_rsp_data; \ - wire [`DCORE_TAG_WIDTH-1:0] scope_dcache_rsp_tag; \ + wire [`NUM_THREADS-1:0][31:0] scope_dcache_rsp_data; \ + wire [`DCORE_TAG_ID_BITS-1:0] scope_dcache_rsp_tag; \ wire scope_dcache_rsp_ready; \ - wire scope_busy; \ wire scope_snp_rsp_ready; \ - wire scope_schedule_delay; \ - wire scope_memory_delay; \ - wire scope_exec_delay; \ - wire scope_gpr_stage_delay; \ - wire [`NUM_THREADS-1:0] scope_decode_valid; \ - wire [`NW_BITS-1:0] scope_decode_warp_num; \ - wire [31:0] scope_decode_curr_PC; \ - wire scope_decode_is_jal; \ - wire [4:0] scope_decode_rs1; \ - wire [4:0] scope_decode_rs2; \ - wire [`NUM_THREADS-1:0] scope_execute_valid; \ - wire [`NW_BITS-1:0] scope_execute_warp_num; \ - wire [31:0] scope_execute_curr_PC; \ - wire [4:0] scope_execute_rd; \ - wire [63:0] scope_execute_a; \ - wire [63:0] scope_execute_b; \ - wire [`NUM_THREADS-1:0] scope_writeback_valid; \ - wire [`NW_BITS-1:0] scope_writeback_warp_num; \ - wire [31:0] scope_writeback_curr_PC; \ - wire [1:0] scope_writeback_wb; \ - wire [4:0] scope_writeback_rd; \ - wire [63:0] scope_writeback_data; \ + wire [`NW_BITS-1:0] scope_issue_wid; \ + wire [`NUM_THREADS-1:0] scope_issue_tmask; \ + wire [31:0] scope_issue_pc; \ + wire [`EX_BITS-1:0] scope_issue_ex_type; \ + wire [`OP_BITS-1:0] scope_issue_op_type; \ + wire [`MOD_BITS-1:0] scope_issue_op_mod; \ + wire scope_issue_wb; \ + wire [`NR_BITS-1:0] scope_issue_rd; \ + wire [`NR_BITS-1:0] scope_issue_rs1; \ + wire [`NR_BITS-1:0] scope_issue_rs2; \ + wire [`NR_BITS-1:0] scope_issue_rs3; \ + wire [31:0] scope_issue_imm; \ + wire scope_issue_rs1_is_pc; \ + wire scope_issue_rs2_is_imm; \ + wire scope_gpr_rsp_valid; \ + wire [`NW_BITS-1:0] scope_gpr_rsp_wid; \ + wire [31:0] scope_gpr_rsp_pc; \ + wire [`NUM_THREADS-1:0][31:0] scope_gpr_rsp_a; \ + wire [`NUM_THREADS-1:0][31:0] scope_gpr_rsp_b; \ + wire [`NUM_THREADS-1:0][31:0] scope_gpr_rsp_c; \ + wire scope_writeback_valid; \ + wire [`NW_BITS-1:0] scope_writeback_wid; \ + wire [31:0] scope_writeback_pc; \ + wire [`NR_BITS-1:0] scope_writeback_rd; \ + wire [`NUM_THREADS-1:0][31:0] scope_writeback_data; \ wire scope_bank_valid_st0; \ wire scope_bank_valid_st1; \ wire scope_bank_valid_st2; \ @@ -158,35 +167,39 @@ wire scope_bank_miss_st1; \ wire scope_bank_dirty_st1; \ wire scope_bank_force_miss_st1; \ - wire scope_bank_stall_pipe; + wire scope_bank_stall_pipe; \ + wire scope_issue_valid; \ + wire scope_issue_ready; \ + wire scope_scoreboard_delay; \ + wire scope_gpr_delay; \ + wire scope_execute_delay; \ + wire scope_busy; `define SCOPE_SIGNALS_ISTAGE_IO \ output wire scope_icache_req_valid, \ - output wire [`NW_BITS-1:0] scope_icache_req_warp_num, \ + output wire [`NW_BITS-1:0] scope_icache_req_wid, \ output wire [31:0] scope_icache_req_addr, \ - output wire [`ICORE_TAG_WIDTH-1:0] scope_icache_req_tag, \ + output wire [`ICORE_TAG_ID_BITS-1:0] scope_icache_req_tag, \ output wire scope_icache_req_ready, \ output wire scope_icache_rsp_valid, \ output wire [31:0] scope_icache_rsp_data, \ - output wire [`ICORE_TAG_WIDTH-1:0] scope_icache_rsp_tag, \ + output wire [`ICORE_TAG_ID_BITS-1:0] scope_icache_rsp_tag, \ output wire scope_icache_rsp_ready, `define SCOPE_SIGNALS_LSU_IO \ output wire [`NUM_THREADS-1:0] scope_dcache_req_valid, \ - output wire [`NW_BITS-1:0] scope_dcache_req_warp_num, \ - output wire [31:0] scope_dcache_req_curr_PC, \ - output wire [63:0] scope_dcache_req_addr, \ + output wire [`NW_BITS-1:0] scope_dcache_req_wid, \ + output wire [31:0] scope_dcache_req_pc, \ + output wire [`NUM_THREADS-1:0][31:0] scope_dcache_req_addr, \ output wire scope_dcache_req_rw, \ - output wire [7:0] scope_dcache_req_byteen, \ - output wire [63:0] scope_dcache_req_data, \ - output wire [`DCORE_TAG_WIDTH-1:0] scope_dcache_req_tag, \ + output wire [`NUM_THREADS-1:0][3:0] scope_dcache_req_byteen, \ + output wire [`NUM_THREADS-1:0][31:0] scope_dcache_req_data, \ + output wire [`DCORE_TAG_ID_BITS-1:0] scope_dcache_req_tag, \ output wire scope_dcache_req_ready, \ output wire [`NUM_THREADS-1:0] scope_dcache_rsp_valid, \ - output wire [63:0] scope_dcache_rsp_data, \ - output wire [`DCORE_TAG_WIDTH-1:0] scope_dcache_rsp_tag, \ + output wire [`NUM_THREADS-1:0][31:0] scope_dcache_rsp_data, \ + output wire [`DCORE_TAG_ID_BITS-1:0] scope_dcache_rsp_tag, \ output wire scope_dcache_rsp_ready, - - `define SCOPE_SIGNALS_CORE_IO \ `define SCOPE_SIGNALS_CACHE_IO \ output wire scope_bank_valid_st0, \ @@ -201,36 +214,43 @@ output wire scope_bank_force_miss_st1, \ output wire scope_bank_stall_pipe, - `define SCOPE_SIGNALS_PIPELINE_IO \ - output wire scope_busy, \ - output wire scope_schedule_delay, \ - output wire scope_memory_delay, \ - output wire scope_exec_delay, \ - output wire scope_gpr_stage_delay, - - `define SCOPE_SIGNALS_BE_IO \ - output wire [`NUM_THREADS-1:0] scope_decode_valid, \ - output wire [`NW_BITS-1:0] scope_decode_warp_num, \ - output wire [31:0] scope_decode_curr_PC, \ - output wire scope_decode_is_jal, \ - output wire [4:0] scope_decode_rs1, \ - output wire [4:0] scope_decode_rs2, \ - output wire [`NUM_THREADS-1:0] scope_execute_valid, \ - output wire [`NW_BITS-1:0] scope_execute_warp_num, \ - output wire [31:0] scope_execute_curr_PC, \ - output wire [4:0] scope_execute_rd, \ - output wire [63:0] scope_execute_a, \ - output wire [63:0] scope_execute_b, \ - output wire [`NUM_THREADS-1:0] scope_writeback_valid, \ - output wire [`NW_BITS-1:0] scope_writeback_warp_num, \ - output wire [31:0] scope_writeback_curr_PC, \ - output wire [1:0] scope_writeback_wb, \ - output wire [4:0] scope_writeback_rd, \ - output wire [63:0] scope_writeback_data, + `define SCOPE_SIGNALS_ISSUE_IO \ + output wire scope_issue_valid, \ + output wire [`NW_BITS-1:0] scope_issue_wid, \ + output wire [`NUM_THREADS-1:0] scope_issue_tmask, \ + output wire [31:0] scope_issue_pc, \ + output wire [`EX_BITS-1:0] scope_issue_ex_type, \ + output wire [`OP_BITS-1:0] scope_issue_op_type, \ + output wire [`MOD_BITS-1:0] scope_issue_op_mod, \ + output wire scope_issue_wb, \ + output wire [`NR_BITS-1:0] scope_issue_rd, \ + output wire [`NR_BITS-1:0] scope_issue_rs1, \ + output wire [`NR_BITS-1:0] scope_issue_rs2, \ + output wire [`NR_BITS-1:0] scope_issue_rs3, \ + output wire [31:0] scope_issue_imm, \ + output wire scope_issue_rs1_is_pc, \ + output wire scope_issue_rs2_is_imm, \ + output wire scope_writeback_valid, \ + output wire scope_gpr_rsp_valid, \ + output wire [`NW_BITS-1:0] scope_gpr_rsp_wid, \ + output wire [31:0] scope_gpr_rsp_pc, \ + output wire [`NUM_THREADS-1:0][31:0] scope_gpr_rsp_a, \ + output wire [`NUM_THREADS-1:0][31:0] scope_gpr_rsp_b, \ + output wire [`NUM_THREADS-1:0][31:0] scope_gpr_rsp_c, \ + output wire [`NW_BITS-1:0] scope_writeback_wid, \ + output wire [31:0] scope_writeback_pc, \ + output wire [`NR_BITS-1:0] scope_writeback_rd, \ + output wire [`NUM_THREADS-1:0][31:0] scope_writeback_data, \ + output wire scope_issue_ready, \ + output wire scope_scoreboard_delay, \ + output wire scope_gpr_delay, \ + output wire scope_execute_delay, + `define SCOPE_SIGNALS_EXECUTE_IO + `define SCOPE_SIGNALS_ISTAGE_BIND \ .scope_icache_req_valid (scope_icache_req_valid), \ - .scope_icache_req_warp_num (scope_icache_req_warp_num), \ + .scope_icache_req_wid (scope_icache_req_wid), \ .scope_icache_req_addr (scope_icache_req_addr), \ .scope_icache_req_tag (scope_icache_req_tag), \ .scope_icache_req_ready (scope_icache_req_ready), \ @@ -241,8 +261,8 @@ `define SCOPE_SIGNALS_LSU_BIND \ .scope_dcache_req_valid (scope_dcache_req_valid), \ - .scope_dcache_req_warp_num (scope_dcache_req_warp_num), \ - .scope_dcache_req_curr_PC (scope_dcache_req_curr_PC), \ + .scope_dcache_req_wid (scope_dcache_req_wid), \ + .scope_dcache_req_pc (scope_dcache_req_pc), \ .scope_dcache_req_addr (scope_dcache_req_addr), \ .scope_dcache_req_rw (scope_dcache_req_rw), \ .scope_dcache_req_byteen(scope_dcache_req_byteen), \ @@ -254,8 +274,6 @@ .scope_dcache_rsp_tag (scope_dcache_rsp_tag), \ .scope_dcache_rsp_ready (scope_dcache_rsp_ready), - `define SCOPE_SIGNALS_CORE_BIND \ - `define SCOPE_SIGNALS_CACHE_BIND \ .scope_bank_valid_st0 (scope_bank_valid_st0), \ .scope_bank_valid_st1 (scope_bank_valid_st1), \ @@ -266,7 +284,7 @@ .scope_bank_is_mrvq_st1 (scope_bank_is_mrvq_st1), \ .scope_bank_miss_st1 (scope_bank_miss_st1), \ .scope_bank_dirty_st1 (scope_bank_dirty_st1), \ - .scope_bank_force_miss_st1 (scope_bank_force_miss_st1), \ + .scope_bank_force_miss_st1(scope_bank_force_miss_st1), \ .scope_bank_stall_pipe (scope_bank_stall_pipe), `define SCOPE_SIGNALS_CACHE_UNBIND \ @@ -311,60 +329,65 @@ assign scope_bank_stall_pipe = scope_per_bank_stall_pipe[0]; `define SCOPE_SIGNALS_CACHE_BANK_BIND \ - .scope_bank_valid_st0 (scope_per_bank_valid_st0[i]), \ - .scope_bank_valid_st1 (scope_per_bank_valid_st1[i]), \ - .scope_bank_valid_st2 (scope_per_bank_valid_st2[i]), \ - .scope_bank_addr_st0 (scope_per_bank_addr_st0[i]), \ - .scope_bank_addr_st1 (scope_per_bank_addr_st1[i]), \ - .scope_bank_addr_st2 (scope_per_bank_addr_st2[i]), \ + .scope_bank_valid_st0 (scope_per_bank_valid_st0[i]), \ + .scope_bank_valid_st1 (scope_per_bank_valid_st1[i]), \ + .scope_bank_valid_st2 (scope_per_bank_valid_st2[i]), \ + .scope_bank_addr_st0 (scope_per_bank_addr_st0[i]), \ + .scope_bank_addr_st1 (scope_per_bank_addr_st1[i]), \ + .scope_bank_addr_st2 (scope_per_bank_addr_st2[i]), \ .scope_bank_is_mrvq_st1 (scope_per_bank_is_mrvq_st1[i]), \ - .scope_bank_miss_st1 (scope_per_bank_miss_st1[i]), \ - .scope_bank_dirty_st1 (scope_per_bank_dirty_st1[i]), \ + .scope_bank_miss_st1 (scope_per_bank_miss_st1[i]), \ + .scope_bank_dirty_st1 (scope_per_bank_dirty_st1[i]), \ .scope_bank_force_miss_st1 (scope_per_bank_force_miss_st1[i]), \ - .scope_bank_stall_pipe (scope_per_bank_stall_pipe[i]), + .scope_bank_stall_pipe (scope_per_bank_stall_pipe[i]), - `define SCOPE_SIGNALS_PIPELINE_BIND \ - .scope_busy (scope_busy), \ - .scope_schedule_delay (scope_schedule_delay), \ - .scope_memory_delay (scope_memory_delay), \ - .scope_exec_delay (scope_exec_delay), \ - .scope_gpr_stage_delay (scope_gpr_stage_delay), - - `define SCOPE_SIGNALS_BE_BIND \ - .scope_decode_valid (scope_decode_valid), \ - .scope_decode_warp_num (scope_decode_warp_num), \ - .scope_decode_curr_PC (scope_decode_curr_PC), \ - .scope_decode_is_jal (scope_decode_is_jal), \ - .scope_decode_rs1 (scope_decode_rs1), \ - .scope_decode_rs2 (scope_decode_rs2), \ - .scope_execute_valid (scope_execute_valid), \ - .scope_execute_warp_num (scope_execute_warp_num), \ - .scope_execute_curr_PC (scope_execute_curr_PC), \ - .scope_execute_rd (scope_execute_rd), \ - .scope_execute_a (scope_execute_a), \ - .scope_execute_b (scope_execute_b), \ + `define SCOPE_SIGNALS_ISSUE_BIND \ + .scope_issue_valid (scope_issue_valid), \ + .scope_issue_wid (scope_issue_wid), \ + .scope_issue_tmask (scope_issue_tmask), \ + .scope_issue_pc (scope_issue_pc), \ + .scope_issue_ex_type (scope_issue_ex_type), \ + .scope_issue_op_type (scope_issue_op_type), \ + .scope_issue_op_mod (scope_issue_op_mod), \ + .scope_issue_wb (scope_issue_wb), \ + .scope_issue_rd (scope_issue_rd), \ + .scope_issue_rs1 (scope_issue_rs1), \ + .scope_issue_rs2 (scope_issue_rs2), \ + .scope_issue_rs3 (scope_issue_rs3), \ + .scope_issue_imm (scope_issue_imm), \ + .scope_issue_rs1_is_pc (scope_issue_rs1_is_pc), \ + .scope_issue_rs2_is_imm (scope_issue_rs2_is_imm), \ .scope_writeback_valid (scope_writeback_valid), \ - .scope_writeback_warp_num (scope_writeback_warp_num), \ - .scope_writeback_curr_PC(scope_writeback_curr_PC), \ - .scope_writeback_wb (scope_writeback_wb), \ + .scope_writeback_wid (scope_writeback_wid), \ + .scope_writeback_pc (scope_writeback_pc), \ .scope_writeback_rd (scope_writeback_rd), \ - .scope_writeback_data (scope_writeback_data), + .scope_writeback_data (scope_writeback_data), \ + .scope_issue_ready (scope_issue_ready), \ + .scope_gpr_rsp_valid (scope_gpr_rsp_valid), \ + .scope_gpr_rsp_wid (scope_gpr_rsp_wid), \ + .scope_gpr_rsp_pc (scope_gpr_rsp_pc), \ + .scope_gpr_rsp_a (scope_gpr_rsp_a), \ + .scope_gpr_rsp_b (scope_gpr_rsp_b), \ + .scope_gpr_rsp_c (scope_gpr_rsp_c), \ + .scope_scoreboard_delay (scope_scoreboard_delay), \ + .scope_gpr_delay (scope_gpr_delay), \ + .scope_execute_delay (scope_execute_delay), \ + + `define SCOPE_SIGNALS_EXECUTE_BIND `define SCOPE_ASSIGN(d,s) assign d = s `else `define SCOPE_SIGNALS_ISTAGE_IO `define SCOPE_SIGNALS_LSU_IO - `define SCOPE_SIGNALS_CORE_IO `define SCOPE_SIGNALS_CACHE_IO - `define SCOPE_SIGNALS_PIPELINE_IO - `define SCOPE_SIGNALS_BE_IO + `define SCOPE_SIGNALS_ISSUE_IO + `define SCOPE_SIGNALS_EXECUTE_IO `define SCOPE_SIGNALS_ISTAGE_BIND `define SCOPE_SIGNALS_LSU_BIND - `define SCOPE_SIGNALS_CORE_BIND `define SCOPE_SIGNALS_CACHE_BIND - `define SCOPE_SIGNALS_PIPELINE_BIND - `define SCOPE_SIGNALS_BE_BIND + `define SCOPE_SIGNALS_ISSUE_BIND + `define SCOPE_SIGNALS_EXECUTE_BIND `define SCOPE_SIGNALS_CACHE_UNBIND `define SCOPE_SIGNALS_CACHE_BANK_SELECT diff --git a/hw/rtl/VX_scoreboard.v b/hw/rtl/VX_scoreboard.v new file mode 100644 index 00000000..2370745c --- /dev/null +++ b/hw/rtl/VX_scoreboard.v @@ -0,0 +1,76 @@ +`include "VX_define.vh" + +module VX_scoreboard #( + parameter CORE_ID = 0 +) ( + input wire clk, + input wire reset, + + VX_decode_if ibuf_deq_if, + VX_writeback_if writeback_if, + input wire [`NW_BITS-1:0] deq_wid_next, + input wire exe_delay, + input wire gpr_delay, + + output wire delay +); + reg [`NUM_THREADS-1:0] inuse_registers [(`NUM_WARPS * `NUM_REGS)-1:0]; + reg [`NUM_WARPS-1:0][`NUM_REGS-1:0] inuse_reg_mask, inuse_reg_mask_n; + reg [`NUM_REGS-1:0] deq_used_regs; + + wire [`NUM_REGS-1:0] inuse_regs = deq_used_regs & ibuf_deq_if.used_regs; + + assign delay = (| inuse_regs); + + wire reserve_reg = ibuf_deq_if.valid && ibuf_deq_if.ready && (ibuf_deq_if.wb != 0); + + wire release_reg = writeback_if.valid && writeback_if.ready; + + wire [`NUM_THREADS-1:0] inuse_registers_n = inuse_registers[{writeback_if.wid, writeback_if.rd}] & ~writeback_if.tmask; + + always @(*) begin + inuse_reg_mask_n = inuse_reg_mask; + if (reserve_reg) begin + inuse_reg_mask_n[ibuf_deq_if.wid][ibuf_deq_if.rd] = 1; + end + if (release_reg) begin + inuse_reg_mask_n[writeback_if.wid][writeback_if.rd] = (| inuse_registers_n); + end + end + + always @(posedge clk) begin + if (reset) begin + for (integer w = 0; w < `NUM_WARPS; w++) begin + for (integer i = 0; i < `NUM_REGS; i++) begin + inuse_registers[w * `NUM_REGS + i] <= 0; + end + inuse_reg_mask[w] <= `NUM_REGS'(0); + end + end else begin + if (reserve_reg) begin + inuse_registers[{ibuf_deq_if.wid, ibuf_deq_if.rd}] <= ibuf_deq_if.tmask; + end + if (release_reg) begin + assert(inuse_reg_mask[writeback_if.wid][writeback_if.rd] != 0); + inuse_registers[{writeback_if.wid, writeback_if.rd}] <= inuse_registers_n; + end + inuse_reg_mask <= inuse_reg_mask_n; + end + + deq_used_regs <= inuse_reg_mask_n[deq_wid_next]; + end + + // issue the instruction + assign ibuf_deq_if.ready = ~(delay || exe_delay || gpr_delay); + +`ifdef DBG_PRINT_PIPELINE + always @(posedge clk) begin + if (ibuf_deq_if.valid && ~ibuf_deq_if.ready) begin + $display("%t: core%0d-stall: wid=%0d, PC=%0h, rd=%0d, wb=%0d, inuse=%b%b%b%b, exe=%b, gpr=%b", + $time, CORE_ID, ibuf_deq_if.wid, ibuf_deq_if.PC, ibuf_deq_if.rd, ibuf_deq_if.wb, + inuse_regs[ibuf_deq_if.rd], inuse_regs[ibuf_deq_if.rs1], inuse_regs[ibuf_deq_if.rs2], inuse_regs[ibuf_deq_if.rs3], exe_delay, gpr_delay); + end + end +`endif + +endmodule \ No newline at end of file diff --git a/hw/rtl/VX_types.vh b/hw/rtl/VX_types.vh new file mode 100644 index 00000000..dd7d22b5 --- /dev/null +++ b/hw/rtl/VX_types.vh @@ -0,0 +1,51 @@ +`ifndef VX_TYPES +`define VX_TYPES + +`include "VX_define.vh" + +typedef struct packed { + logic is_normal; + logic is_zero; + logic is_subnormal; + logic is_inf; + logic is_nan; + logic is_signaling; + logic is_quiet; +} fp_type_t; + +typedef struct packed { + logic NV; // Invalid + logic DZ; // Divide by zero + logic OF; // Overflow + logic UF; // Underflow + logic NX; // Inexact +} fflags_t; + +`define FFG_BITS $bits(fflags_t) + +typedef struct packed { + logic valid; + logic [`NUM_THREADS-1:0] tmask; +} gpu_tmc_t; + +typedef struct packed { + logic valid; + logic [`NUM_WARPS-1:0] wmask; + logic [31:0] pc; +} gpu_wspawn_t; + +typedef struct packed { + logic valid; + logic diverged; + logic [`NUM_THREADS-1:0] then_mask; + logic [`NUM_THREADS-1:0] else_mask; + logic [31:0] pc; +} gpu_split_t; + +typedef struct packed { + logic valid; + logic [`NB_BITS-1:0] id; + logic [`NW_BITS-1:0] size_m1; +} gpu_barrier_t; + +`endif \ No newline at end of file diff --git a/hw/rtl/VX_warp.v b/hw/rtl/VX_warp.v deleted file mode 100644 index b780d760..00000000 --- a/hw/rtl/VX_warp.v +++ /dev/null @@ -1,69 +0,0 @@ -`include "VX_define.vh" - - -module VX_warp ( - input wire clk, - input wire reset, - input wire stall, - input wire remove, - input wire[`NUM_THREADS-1:0] thread_mask, - input wire change_mask, - input wire jal, - input wire[31:0] dest, - input wire branch_dir, - input wire[31:0] branch_dest, - input wire wspawn, - input wire[31:0] wspawn_pc, - - output wire[31:0] PC, - output wire[`NUM_THREADS-1:0] valid -); - - reg [`NUM_THREADS-1:0] valid_t; - reg [31:0] real_PC; - reg [31:0] temp_PC; - reg [31:0] use_PC; - - always @(posedge clk) begin - if (reset) begin - valid_t <= {{(`NUM_THREADS-1){1'b0}},1'b1}; // Thread 1 active - end else if (remove) begin - valid_t <= 0; - end else if (change_mask) begin - valid_t <= thread_mask; - end - end - - genvar i; - generate - for (i = 0; i < `NUM_THREADS; i++) begin : valid_assign - assign valid[i] = change_mask ? thread_mask[i] : stall ? 1'b0 : valid_t[i]; - end - endgenerate - - always @(*) begin - if (jal == 1'b1) begin - temp_PC = dest; - end else if (branch_dir) begin - temp_PC = branch_dest; - end else begin - temp_PC = real_PC; - end - end - - assign use_PC = temp_PC; - assign PC = temp_PC; - - always @(posedge clk) begin - if (reset) begin - real_PC <= 0; - end else if (wspawn) begin - real_PC <= wspawn_pc; - end else if (!stall) begin - real_PC <= use_PC + 32'h4; - end else begin - real_PC <= use_PC; - end - end - -endmodule \ No newline at end of file diff --git a/hw/rtl/VX_warp_sched.v b/hw/rtl/VX_warp_sched.v index 9621d47b..5234f74a 100644 --- a/hw/rtl/VX_warp_sched.v +++ b/hw/rtl/VX_warp_sched.v @@ -1,327 +1,245 @@ `include "VX_define.vh" -module VX_warp_sched ( - input wire clk, - input wire reset, - input wire stall, +module VX_warp_sched #( + parameter CORE_ID = 0 +) ( + input wire clk, + input wire reset, - // Wspawn - input wire wspawn, - input wire[31:0] wsapwn_pc, - input wire[`NUM_WARPS-1:0] wspawn_new_active, + VX_warp_ctl_if warp_ctl_if, + VX_wstall_if wstall_if, + VX_join_if join_if, + VX_branch_ctl_if branch_ctl_if, - // CTM - input wire ctm, - input wire[`NUM_THREADS-1:0] ctm_mask, - input wire[`NW_BITS-1:0] ctm_warp_num, + VX_ifetch_rsp_if ifetch_rsp_if, + VX_ifetch_req_if ifetch_req_if, - // WHALT - input wire whalt, - input wire[`NW_BITS-1:0] whalt_warp_num, - - input wire is_barrier, -`DEBUG_BEGIN - input wire[31:0] barrier_id, -`DEBUG_END - input wire[$clog2(`NUM_WARPS):0] num_warps, - input wire[`NW_BITS-1:0] barrier_warp_num, - - // WSTALL - input wire wstall, - input wire [`NW_BITS-1:0] wstall_warp_num, - - // Split - input wire is_split, - input wire dont_split, - input wire [`NUM_THREADS-1:0] split_new_mask, - input wire [`NUM_THREADS-1:0] split_later_mask, - input wire [31:0] split_save_pc, - input wire [`NW_BITS-1:0] split_warp_num, - - // Join - input wire is_join, - input wire [`NW_BITS-1:0] join_warp_num, - - // JAL - input wire jal, - input wire [31:0] dest, - input wire [`NW_BITS-1:0] jal_warp_num, - - // Branch - input wire branch_valid, - input wire branch_dir, - input wire [31:0] branch_dest, - input wire [`NW_BITS-1:0] branch_warp_num, - - output wire [`NUM_THREADS-1:0] thread_mask, - output wire [`NW_BITS-1:0] warp_num, - output wire [31:0] warp_pc, - output wire busy, - output wire scheduled_warp, - - input wire [`NW_BITS-1:0] icache_stage_wid, - input wire icache_stage_response + output wire busy ); - wire update_use_wspawn; - wire update_visible_active; + wire join_fall; + wire [31:0] join_pc; + wire [`NUM_THREADS-1:0] join_tm; - wire[(1+32+`NUM_THREADS-1):0] d[`NUM_WARPS-1:0]; - - wire join_fall; - wire[31:0] join_pc; - wire[`NUM_THREADS-1:0] join_tm; - -`DEBUG_BEGIN - wire in_wspawn = wspawn; - wire in_ctm = ctm; - wire in_whalt = whalt; - wire in_wstall = wstall; -`DEBUG_END - - reg[`NUM_WARPS-1:0] warp_active; - reg[`NUM_WARPS-1:0] warp_stalled; - - reg [`NUM_WARPS-1:0] visible_active; - wire[`NUM_WARPS-1:0] use_active; - - reg [`NUM_WARPS-1:0] warp_lock; - - wire wstall_this_cycle; + reg [`NUM_WARPS-1:0] active_warps; // real active warps (updated when a warp is activated or disabled) + reg [`NUM_WARPS-1:0] stalled_warps; // asserted when a branch/gpgpu instructions are issued + reg [`NUM_WARPS-1:0] schedule_table, schedule_table_n; // enforces round-robin, barrier, and non-speculating branches + + // Lock warp until instruction decode to resolve branches + reg [`NUM_WARPS-1:0] fetch_lock; reg [`NUM_THREADS-1:0] thread_masks[`NUM_WARPS-1:0]; reg [31:0] warp_pcs[`NUM_WARPS-1:0]; // barriers - reg [`NUM_WARPS-1:0] barrier_stall_mask[(`NUM_BARRIERS-1):0]; - wire reached_barrier_limit; - wire [`NUM_WARPS-1:0] b_mask; - wire [$clog2(`NUM_WARPS):0] b_count; - - // wsapwn - reg [31:0] use_wsapwn_pc; - reg [`NUM_WARPS-1:0] use_wsapwn; - - wire [`NW_BITS-1:0] warp_to_schedule; - wire schedule; - - wire hazard; - wire global_stall; - - wire real_schedule; - - wire [31:0] new_pc; - - reg [`NUM_WARPS-1:0] total_barrier_stall; - - reg didnt_split; - - integer w, b; + reg [`NUM_WARPS-1:0] barrier_stall_mask[`NUM_BARRIERS-1:0]; // warps waiting on barrier + wire reached_barrier_limit; // the expected number of warps reached the barrier + // wspawn + reg [31:0] use_wspawn_pc; + reg [`NUM_WARPS-1:0] use_wspawn; + + reg [31:0] warp_pc; + reg [`NW_BITS-1:0] warp_to_schedule; + wire scheduled_warp; + + reg didnt_split; + + wire ifetch_rsp_fire = ifetch_rsp_if.valid && ifetch_rsp_if.ready; + + always @(*) begin + schedule_table_n = schedule_table; + if (warp_ctl_if.valid + && warp_ctl_if.tmc.valid + && (0 == warp_ctl_if.tmc.tmask)) begin + schedule_table_n[warp_ctl_if.wid] = 0; + end + if (scheduled_warp) begin // remove scheduled warp (round-robin) + schedule_table_n[warp_to_schedule] = 0; + end + end + always @(posedge clk) begin if (reset) begin - for (b = 0; b < `NUM_BARRIERS; b=b+1) begin - barrier_stall_mask[b] <= 0; - end - use_wsapwn_pc <= 0; - use_wsapwn <= 0; - warp_pcs[0] <= `STARTUP_ADDR; - warp_active[0] <= 1; // Activating first warp - visible_active[0] <= 1; // Activating first warp - thread_masks[0] <= 1; // Activating first thread in first warp - warp_stalled <= 0; - didnt_split <= 0; - warp_lock <= 0; - // total_barrier_stall = 0; - for (w = 1; w < `NUM_WARPS; w=w+1) begin - warp_pcs[w] <= 0; - warp_active[w] <= 0; // Activating first warp - visible_active[w] <= 0; // Activating first warp - thread_masks[w] <= 1; // Activating first thread in first warp + for (integer i = 0; i < `NUM_BARRIERS; i++) begin + barrier_stall_mask[i] <= 0; end - end else begin - // Wsapwning warps - if (wspawn) begin - warp_active <= wspawn_new_active; - use_wsapwn_pc <= wsapwn_pc; - use_wsapwn <= wspawn_new_active & (~`NUM_WARPS'b1); - end - - if (is_barrier) begin - warp_stalled[barrier_warp_num] <= 0; - if (reached_barrier_limit) begin - barrier_stall_mask[barrier_id] <= 0; - end else begin - barrier_stall_mask[barrier_id][barrier_warp_num] <= 1; - end - end else if (ctm) begin - thread_masks[ctm_warp_num] <= ctm_mask; - warp_stalled[ctm_warp_num] <= 0; - end else if (is_join && !didnt_split) begin - if (!join_fall) begin - warp_pcs[join_warp_num] <= join_pc; - end - thread_masks[join_warp_num] <= join_tm; - didnt_split <= 0; - end else if (is_split) begin - warp_stalled[split_warp_num] <= 0; - if (!dont_split) begin - thread_masks[split_warp_num] <= split_new_mask; - didnt_split <= 0; - end else begin - didnt_split <= 1; - end - end + use_wspawn_pc <= 0; + use_wspawn <= 0; + warp_pcs[0] <= `STARTUP_ADDR; + active_warps[0] <= 1; // Activating first warp + schedule_table[0] <= 1; // set first warp as ready + thread_masks[0] <= 1; // Activating first thread in first warp + stalled_warps <= 0; + didnt_split <= 0; + fetch_lock <= 0; - if (whalt) begin - warp_active[whalt_warp_num] <= 0; - visible_active[whalt_warp_num] <= 0; + for (integer i = 1; i < `NUM_WARPS; i++) begin + warp_pcs[i] <= 0; + active_warps[i] <= 0; + schedule_table[i] <= 0; + thread_masks[i] <= 0; + end + end else begin + if (warp_ctl_if.valid && warp_ctl_if.wspawn.valid) begin + active_warps <= warp_ctl_if.wspawn.wmask; + use_wspawn <= warp_ctl_if.wspawn.wmask & (~`NUM_WARPS'(1)); + use_wspawn_pc <= warp_ctl_if.wspawn.pc; end - if (update_use_wspawn) begin - use_wsapwn[warp_to_schedule] <= 0; + if (warp_ctl_if.valid && warp_ctl_if.barrier.valid) begin + stalled_warps[warp_ctl_if.wid] <= 0; + if (reached_barrier_limit) begin + barrier_stall_mask[warp_ctl_if.barrier.id] <= 0; + end else begin + barrier_stall_mask[warp_ctl_if.barrier.id][warp_ctl_if.wid] <= 1; + end + end else if (warp_ctl_if.valid && warp_ctl_if.tmc.valid) begin + thread_masks[warp_ctl_if.wid] <= warp_ctl_if.tmc.tmask; + stalled_warps[warp_ctl_if.wid] <= 0; + if (0 == warp_ctl_if.tmc.tmask) begin + active_warps[warp_ctl_if.wid] <= 0; + end + end else if (join_if.valid && !didnt_split) begin + if (!join_fall) begin + warp_pcs[join_if.wid] <= join_pc; + end + thread_masks[join_if.wid] <= join_tm; + didnt_split <= 0; + end else if (warp_ctl_if.valid && warp_ctl_if.split.valid) begin + stalled_warps[warp_ctl_if.wid] <= 0; + if (warp_ctl_if.split.diverged) begin + thread_masks[warp_ctl_if.wid] <= warp_ctl_if.split.then_mask; + didnt_split <= 0; + end else begin + didnt_split <= 1; + end + end + + if (use_wspawn[warp_to_schedule] && scheduled_warp) begin + use_wspawn[warp_to_schedule] <= 0; thread_masks[warp_to_schedule] <= 1; end - // Stalling the scheduling of warps - if (wstall) begin - warp_stalled[wstall_warp_num] <= 1; - visible_active[wstall_warp_num] <= 0; - end - - // Refilling active warps - if (update_visible_active) begin - visible_active <= warp_active & (~warp_stalled) & (~total_barrier_stall) & ~warp_lock; - end - - // Don't change state if stall - if (!global_stall && real_schedule && (thread_mask != 0)) begin - visible_active[warp_to_schedule] <= 0; - warp_pcs[warp_to_schedule] <= new_pc; - end - - // Jal - if (jal) begin - warp_pcs[jal_warp_num] <= dest; - warp_stalled[jal_warp_num] <= 0; + if (wstall_if.valid) begin + stalled_warps[wstall_if.wid] <= 1; end // Branch - if (branch_valid) begin - if (branch_dir) begin - warp_pcs[branch_warp_num] <= branch_dest; + if (branch_ctl_if.valid) begin + if (branch_ctl_if.taken) begin + warp_pcs[branch_ctl_if.wid] <= branch_ctl_if.dest; end - warp_stalled[branch_warp_num] <= 0; + stalled_warps[branch_ctl_if.wid] <= 0; end - // Lock/Release - if (scheduled_warp && !stall) begin - warp_lock[warp_num] <= 1'b1; + // Lock warp until instruction decode to resolve branches + if (scheduled_warp) begin + fetch_lock[warp_to_schedule] <= 1; end - if (icache_stage_response) begin - warp_lock[icache_stage_wid] <= 1'b0; + if (ifetch_rsp_fire) begin + fetch_lock[ifetch_rsp_if.wid] <= 0; + warp_pcs[ifetch_rsp_if.wid] <= ifetch_rsp_if.PC + 4; end + // reset 'schedule_table' when it goes to zero + schedule_table <= (| schedule_table_n) ? schedule_table_n : active_warps; end end + // calculate active barrier status + +`IGNORE_WARNINGS_BEGIN + wire [`NW_BITS:0] active_barrier_count; +`IGNORE_WARNINGS_END VX_countones #( .N(`NUM_WARPS) ) barrier_count ( - .valids(b_mask), - .count (b_count) - ); + .valids(barrier_stall_mask[warp_ctl_if.barrier.id]), + .count (active_barrier_count) + ); - wire [$clog2(`NUM_WARPS):0] count_visible_active; + assign reached_barrier_limit = (active_barrier_count[`NW_BITS-1:0] == warp_ctl_if.barrier.size_m1); - VX_countones #( - .N(`NUM_WARPS) - ) num_visible ( - .valids(visible_active), - .count (count_visible_active) - ); + reg [`NUM_WARPS-1:0] total_barrier_stall; + always @(*) begin + total_barrier_stall = barrier_stall_mask[0]; + for (integer i = 1; i < `NUM_BARRIERS; ++i) begin + total_barrier_stall |= barrier_stall_mask[i]; + end + end - // assign b_count = $countones(b_mask); + // split/join stack management - assign b_mask = barrier_stall_mask[barrier_id][`NUM_WARPS-1:0]; - assign reached_barrier_limit = b_count == (num_warps); + wire [(1+32+`NUM_THREADS-1):0] ipdom[`NUM_WARPS-1:0]; + wire [(1+32+`NUM_THREADS-1):0] q1 = {1'b1, 32'b0, thread_masks[warp_ctl_if.wid]}; + wire [(1+32+`NUM_THREADS-1):0] q2 = {1'b0, warp_ctl_if.split.pc, warp_ctl_if.split.else_mask}; - assign wstall_this_cycle = wstall && (wstall_warp_num == warp_to_schedule); // Maybe bug + assign {join_fall, join_pc, join_tm} = ipdom[join_if.wid]; - assign total_barrier_stall = barrier_stall_mask[0] | barrier_stall_mask[1] | barrier_stall_mask[2] | barrier_stall_mask[3]; + for (genvar i = 0; i < `NUM_WARPS; i++) begin + wire push = warp_ctl_if.valid + && warp_ctl_if.split.valid + && warp_ctl_if.split.diverged + && (i == warp_ctl_if.wid); - assign update_visible_active = (0 == count_visible_active) && !(stall || wstall_this_cycle || hazard || is_join); + wire pop = join_if.valid && (i == join_if.wid); - wire [(1+32+`NUM_THREADS-1):0] q1 = {1'b1, 32'b0, thread_masks[split_warp_num]}; - wire [(1+32+`NUM_THREADS-1):0] q2 = {1'b0, split_save_pc, split_later_mask}; - - assign {join_fall, join_pc, join_tm} = d[join_warp_num]; - - genvar i; - generate - for (i = 0; i < `NUM_WARPS; i++) begin : stacks - wire correct_warp_s = (i == split_warp_num); - wire correct_warp_j = (i == join_warp_num); - - wire push = (is_split && !dont_split) && correct_warp_s; - wire pop = is_join && correct_warp_j; - - VX_generic_stack #( + VX_ipdom_stack #( .WIDTH(1+32+`NUM_THREADS), - .DEPTH($clog2(`NUM_THREADS)+1) - ) ipdom_stack( + .DEPTH(`NT_BITS+1) + ) ipdom_stack ( .clk (clk), .reset(reset), .push (push), .pop (pop), - .d (d[i]), .q1 (q1), - .q2 (q2) + .q2 (q2), + .d (ipdom[i]), + `UNUSED_PIN (empty), + `UNUSED_PIN (full) ); end - endgenerate - wire should_jal = (jal && (warp_to_schedule == jal_warp_num)); - wire should_bra = (branch_valid && branch_dir && (warp_to_schedule == branch_warp_num)); + // calculate next warp schedule - assign hazard = (should_jal || should_bra) && schedule; + reg schedule_valid; + reg [`NUM_THREADS-1:0] thread_mask; + + wire [`NUM_WARPS-1:0] schedule_ready = schedule_table & ~(stalled_warps | total_barrier_stall | fetch_lock); - assign real_schedule = schedule && !warp_stalled[warp_to_schedule] && !total_barrier_stall[warp_to_schedule] && !warp_lock[0]; + always @(*) begin + schedule_valid = 0; + thread_mask = 'x; + warp_pc = 'x; + warp_to_schedule = 'x; + for (integer i = 0; i < `NUM_WARPS; ++i) begin + if (schedule_ready[i]) begin + schedule_valid = 1; + thread_mask = use_wspawn[i] ? `NUM_THREADS'(1) : thread_masks[i]; + warp_pc = use_wspawn[i] ? use_wspawn_pc : warp_pcs[i]; + warp_to_schedule = `NW_BITS'(i); + break; + end + end + end - assign global_stall = (stall || wstall_this_cycle || hazard || !real_schedule || is_join); + wire stall_out = ~ifetch_req_if.ready && ifetch_req_if.valid; - assign scheduled_warp = !(wstall_this_cycle || hazard || !real_schedule || is_join) && !reset; + assign scheduled_warp = schedule_valid && ~stall_out; - wire real_use_wspawn = use_wsapwn[warp_to_schedule]; - - assign warp_pc = real_use_wspawn ? use_wsapwn_pc : warp_pcs[warp_to_schedule]; - assign thread_mask = (global_stall) ? 0 : (real_use_wspawn ? `NUM_THREADS'b1 : thread_masks[warp_to_schedule]); - assign warp_num = warp_to_schedule; - - assign update_use_wspawn = use_wsapwn[warp_to_schedule] && !global_stall; - - assign new_pc = warp_pc + 4; - - assign use_active = (count_visible_active != 0) ? visible_active : (warp_active & (~warp_stalled) & (~total_barrier_stall) & (~warp_lock)); - - // Choosing a warp to schedule - VX_fixed_arbiter #( - .N(`NUM_WARPS) - ) choose_schedule ( - .clk (clk), - .reset (reset), - .requests (use_active), - .grant_index (warp_to_schedule), - .grant_valid (schedule), - `UNUSED_PIN (grant_onehot) + VX_generic_register #( + .N(1 + `NUM_THREADS + 32 + `NW_BITS) + ) fetch_reg ( + .clk (clk), + .reset (reset), + .stall (stall_out), + .flush (1'b0), + .in ({scheduled_warp, thread_mask, warp_pc, warp_to_schedule}), + .out ({ifetch_req_if.valid, ifetch_req_if.tmask, ifetch_req_if.PC, ifetch_req_if.wid}) ); - // always @(*) begin - // $display("WarpPC: %h",warp_pc); - // $display("real_schedule: %d, schedule: %d, warp_stalled: %d, warp_to_schedule: %d, total_barrier_stall: %d",real_schedule, schedule, warp_stalled[warp_to_schedule], warp_to_schedule, total_barrier_stall[warp_to_schedule]); - // end - - assign busy = (warp_active != 0); + assign busy = (active_warps != 0); endmodule \ No newline at end of file diff --git a/hw/rtl/VX_writeback.v b/hw/rtl/VX_writeback.v index 4baddbfb..58e01f55 100644 --- a/hw/rtl/VX_writeback.v +++ b/hw/rtl/VX_writeback.v @@ -1,93 +1,96 @@ `include "VX_define.vh" -module VX_writeback ( +module VX_writeback #( + parameter CORE_ID = 0 +) ( input wire clk, input wire reset, - // Mem WB info - VX_wb_if mem_wb_if, + // inputs + VX_exu_to_cmt_if alu_commit_if, + VX_exu_to_cmt_if lsu_commit_if, + VX_exu_to_cmt_if csr_commit_if, + VX_exu_to_cmt_if mul_commit_if, + VX_fpu_to_cmt_if fpu_commit_if, + VX_exu_to_cmt_if gpu_commit_if, - // EXEC Unit WB info - VX_wb_if inst_exec_wb_if, - - // CSR Unit WB info - VX_wb_if csr_wb_if, - - // Actual WB to GPR - VX_wb_if writeback_if, - output wire no_slot_mem, - output wire no_slot_exec, - output wire no_slot_csr + // outputs + VX_writeback_if writeback_if ); + wire alu_valid = alu_commit_if.valid && alu_commit_if.wb; + wire lsu_valid = lsu_commit_if.valid && lsu_commit_if.wb; + wire csr_valid = csr_commit_if.valid && csr_commit_if.wb; + wire mul_valid = mul_commit_if.valid && mul_commit_if.wb; + wire fpu_valid = fpu_commit_if.valid && fpu_commit_if.wb; - VX_wb_if writeback_tmp_if(); + wire wb_valid; + wire [`NW_BITS-1:0] wb_wid; + wire [`NUM_THREADS-1:0] wb_tmask; + wire [`NR_BITS-1:0] wb_rd; + wire [`NUM_THREADS-1:0][31:0] wb_data; + + assign wb_valid = alu_valid ? alu_commit_if.valid : + lsu_valid ? lsu_commit_if.valid : + csr_valid ? csr_commit_if.valid : + mul_valid ? mul_commit_if.valid : + fpu_valid ? fpu_commit_if.valid : + 0; - wire exec_wb = (inst_exec_wb_if.wb != 0) && (| inst_exec_wb_if.valid); - wire mem_wb = (mem_wb_if.wb != 0) && (| mem_wb_if.valid); - wire csr_wb = (csr_wb_if.wb != 0) && (| csr_wb_if.valid); + assign wb_wid = alu_valid ? alu_commit_if.wid : + lsu_valid ? lsu_commit_if.wid : + csr_valid ? csr_commit_if.wid : + mul_valid ? mul_commit_if.wid : + fpu_valid ? fpu_commit_if.wid : + 0; + + assign wb_tmask = alu_valid ? alu_commit_if.tmask : + lsu_valid ? lsu_commit_if.tmask : + csr_valid ? csr_commit_if.tmask : + mul_valid ? mul_commit_if.tmask : + fpu_valid ? fpu_commit_if.tmask : + 0; - assign no_slot_mem = mem_wb && (exec_wb || csr_wb); - assign no_slot_csr = csr_wb && exec_wb; - assign no_slot_exec = 0; + assign wb_rd = alu_valid ? alu_commit_if.rd : + lsu_valid ? lsu_commit_if.rd : + csr_valid ? csr_commit_if.rd : + mul_valid ? mul_commit_if.rd : + fpu_valid ? fpu_commit_if.rd : + 0; - assign writeback_tmp_if.data = exec_wb ? inst_exec_wb_if.data : - csr_wb ? csr_wb_if.data : - mem_wb ? mem_wb_if.data : - 0; - - assign writeback_tmp_if.valid = exec_wb ? inst_exec_wb_if.valid : - csr_wb ? csr_wb_if.valid : - mem_wb ? mem_wb_if.valid : - 0; - - assign writeback_tmp_if.rd = exec_wb ? inst_exec_wb_if.rd : - csr_wb ? csr_wb_if.rd : - mem_wb ? mem_wb_if.rd : - 0; - - assign writeback_tmp_if.wb = exec_wb ? inst_exec_wb_if.wb : - csr_wb ? csr_wb_if.wb : - mem_wb ? mem_wb_if.wb : - 0; - - assign writeback_tmp_if.warp_num = exec_wb ? inst_exec_wb_if.warp_num : - csr_wb ? csr_wb_if.warp_num : - mem_wb ? mem_wb_if.warp_num : - 0; - - assign writeback_tmp_if.curr_PC = exec_wb ? inst_exec_wb_if.curr_PC : - csr_wb ? 32'hdeadbeef : - mem_wb ? mem_wb_if.curr_PC : - 32'hdeadbeef; - - wire [`NUM_THREADS-1:0][31:0] use_wb_data; + assign wb_data = alu_valid ? alu_commit_if.data : + lsu_valid ? lsu_commit_if.data : + csr_valid ? csr_commit_if.data : + mul_valid ? mul_commit_if.data : + fpu_valid ? fpu_commit_if.data : + 0; + always @(*) assert(writeback_if.ready); + wire stall = 0/*~writeback_if.ready && writeback_if.valid*/; + VX_generic_register #( - .N(39 + `NW_BITS-1 + 1 + `NUM_THREADS*33) - ) wb_register ( - .clk (clk), - .reset(reset), - .stall(1'b0), - .flush(1'b0), - .in ({writeback_tmp_if.data, writeback_tmp_if.valid, writeback_tmp_if.rd, writeback_tmp_if.wb, writeback_tmp_if.warp_num, writeback_tmp_if.curr_PC}), - .out ({use_wb_data, writeback_if.valid, writeback_if.rd, writeback_if.wb, writeback_if.warp_num, writeback_if.curr_PC}) + .N(1 + `NW_BITS + `NUM_THREADS + `NR_BITS + (`NUM_THREADS * 32)) + ) wb_reg ( + .clk (clk), + .reset (reset), + .stall (stall), + .flush (1'b0), + .in ({wb_valid, wb_wid, wb_tmask, wb_rd, wb_data}), + .out ({writeback_if.valid, writeback_if.wid, writeback_if.tmask, writeback_if.rd, writeback_if.data}) ); - reg [31:0] last_data_wb /* verilator public */; - + assign alu_commit_if.ready = !stall; + assign lsu_commit_if.ready = !stall && !alu_valid; + assign csr_commit_if.ready = !stall && !alu_valid && !lsu_valid; + assign mul_commit_if.ready = !stall && !alu_valid && !lsu_valid && !csr_valid; + assign fpu_commit_if.ready = !stall && !alu_valid && !lsu_valid && !csr_valid && !mul_valid; + assign gpu_commit_if.ready = 1'b1; + + // special workaround to get RISC-V tests Pass/Fail status + reg [31:0] last_wb_value [`NUM_REGS-1:0] /* verilator public */; always @(posedge clk) begin - if ( (| writeback_if.valid) && (writeback_if.wb != 0) && (writeback_if.rd == 28)) begin - last_data_wb <= use_wb_data[0]; + if (writeback_if.valid && writeback_if.ready) begin + last_wb_value[writeback_if.rd] <= writeback_if.data[0]; end end - assign writeback_if.data = use_wb_data; - -endmodule : VX_writeback - - - - - - - +endmodule \ No newline at end of file diff --git a/hw/rtl/Vortex.v b/hw/rtl/Vortex.v index dfbf0e4a..5f055aeb 100644 --- a/hw/rtl/Vortex.v +++ b/hw/rtl/Vortex.v @@ -3,10 +3,9 @@ module Vortex ( `SCOPE_SIGNALS_ISTAGE_IO `SCOPE_SIGNALS_LSU_IO - `SCOPE_SIGNALS_CORE_IO `SCOPE_SIGNALS_CACHE_IO - `SCOPE_SIGNALS_PIPELINE_IO - `SCOPE_SIGNALS_BE_IO + `SCOPE_SIGNALS_ISSUE_IO + `SCOPE_SIGNALS_EXECUTE_IO // Clock input wire clk, @@ -78,10 +77,9 @@ module Vortex ( ) cluster ( `SCOPE_SIGNALS_ISTAGE_BIND `SCOPE_SIGNALS_LSU_BIND - `SCOPE_SIGNALS_CORE_BIND `SCOPE_SIGNALS_CACHE_BIND - `SCOPE_SIGNALS_PIPELINE_BIND - `SCOPE_SIGNALS_BE_BIND + `SCOPE_SIGNALS_ISSUE_BIND + `SCOPE_SIGNALS_EXECUTE_BIND .clk (clk), .reset (reset), @@ -139,69 +137,67 @@ module Vortex ( end else begin - wire per_cluster_dram_req_valid [`NUM_CLUSTERS-1:0]; - wire per_cluster_dram_req_rw [`NUM_CLUSTERS-1:0]; - wire [`L2DRAM_BYTEEN_WIDTH-1:0] per_cluster_dram_req_byteen [`NUM_CLUSTERS-1:0]; - wire [`L2DRAM_ADDR_WIDTH-1:0] per_cluster_dram_req_addr [`NUM_CLUSTERS-1:0]; - wire [`L2DRAM_LINE_WIDTH-1:0] per_cluster_dram_req_data [`NUM_CLUSTERS-1:0]; - wire [`L2DRAM_TAG_WIDTH-1:0] per_cluster_dram_req_tag [`NUM_CLUSTERS-1:0]; - wire l3_core_req_ready; + wire [`NUM_CLUSTERS-1:0] per_cluster_dram_req_valid; + wire [`NUM_CLUSTERS-1:0] per_cluster_dram_req_rw; + wire [`NUM_CLUSTERS-1:0][`L2DRAM_BYTEEN_WIDTH-1:0] per_cluster_dram_req_byteen; + wire [`NUM_CLUSTERS-1:0][`L2DRAM_ADDR_WIDTH-1:0] per_cluster_dram_req_addr; + wire [`NUM_CLUSTERS-1:0][`L2DRAM_LINE_WIDTH-1:0] per_cluster_dram_req_data; + wire [`NUM_CLUSTERS-1:0][`L2DRAM_TAG_WIDTH-1:0] per_cluster_dram_req_tag; + wire l3_core_req_ready; - wire per_cluster_dram_rsp_valid [`NUM_CLUSTERS-1:0]; - wire [`L2DRAM_LINE_WIDTH-1:0] per_cluster_dram_rsp_data [`NUM_CLUSTERS-1:0]; - wire [`L2DRAM_TAG_WIDTH-1:0] per_cluster_dram_rsp_tag [`NUM_CLUSTERS-1:0]; - wire per_cluster_dram_rsp_ready [`NUM_CLUSTERS-1:0]; + wire [`NUM_CLUSTERS-1:0] per_cluster_dram_rsp_valid; + wire [`NUM_CLUSTERS-1:0][`L2DRAM_LINE_WIDTH-1:0] per_cluster_dram_rsp_data; + wire [`NUM_CLUSTERS-1:0][`L2DRAM_TAG_WIDTH-1:0] per_cluster_dram_rsp_tag; + wire [`NUM_CLUSTERS-1:0] per_cluster_dram_rsp_ready; - wire per_cluster_snp_req_valid [`NUM_CLUSTERS-1:0]; - wire [`L2DRAM_ADDR_WIDTH-1:0] per_cluster_snp_req_addr [`NUM_CLUSTERS-1:0]; - wire per_cluster_snp_req_invalidate [`NUM_CLUSTERS-1:0]; - wire [`L2SNP_TAG_WIDTH-1:0] per_cluster_snp_req_tag [`NUM_CLUSTERS-1:0]; - wire per_cluster_snp_req_ready [`NUM_CLUSTERS-1:0]; + wire [`NUM_CLUSTERS-1:0] per_cluster_snp_req_valid; + wire [`NUM_CLUSTERS-1:0][`L2DRAM_ADDR_WIDTH-1:0] per_cluster_snp_req_addr; + wire [`NUM_CLUSTERS-1:0] per_cluster_snp_req_invalidate; + wire [`NUM_CLUSTERS-1:0][`L2SNP_TAG_WIDTH-1:0] per_cluster_snp_req_tag; + wire [`NUM_CLUSTERS-1:0] per_cluster_snp_req_ready; - wire per_cluster_snp_rsp_valid [`NUM_CLUSTERS-1:0]; - wire [`L2SNP_TAG_WIDTH-1:0] per_cluster_snp_rsp_tag [`NUM_CLUSTERS-1:0]; - wire per_cluster_snp_rsp_ready [`NUM_CLUSTERS-1:0]; + wire [`NUM_CLUSTERS-1:0] per_cluster_snp_rsp_valid; + wire [`NUM_CLUSTERS-1:0][`L2SNP_TAG_WIDTH-1:0] per_cluster_snp_rsp_tag; + wire [`NUM_CLUSTERS-1:0] per_cluster_snp_rsp_ready; - wire per_cluster_io_req_valid [`NUM_CLUSTERS-1:0]; - wire per_cluster_io_req_rw [`NUM_CLUSTERS-1:0]; - wire [3:0] per_cluster_io_req_byteen [`NUM_CLUSTERS-1:0]; - wire [29:0] per_cluster_io_req_addr [`NUM_CLUSTERS-1:0]; - wire [31:0] per_cluster_io_req_data [`NUM_CLUSTERS-1:0]; - wire [`L2CORE_TAG_WIDTH-1:0] per_cluster_io_req_tag [`NUM_CLUSTERS-1:0]; - wire per_cluster_io_req_ready [`NUM_CLUSTERS-1:0]; + wire [`NUM_CLUSTERS-1:0] per_cluster_io_req_valid; + wire [`NUM_CLUSTERS-1:0] per_cluster_io_req_rw; + wire [`NUM_CLUSTERS-1:0][3:0] per_cluster_io_req_byteen; + wire [`NUM_CLUSTERS-1:0][29:0] per_cluster_io_req_addr; + wire [`NUM_CLUSTERS-1:0][31:0] per_cluster_io_req_data; + wire [`NUM_CLUSTERS-1:0][`L2CORE_TAG_WIDTH-1:0] per_cluster_io_req_tag; + wire [`NUM_CLUSTERS-1:0] per_cluster_io_req_ready; - wire per_cluster_io_rsp_valid [`NUM_CLUSTERS-1:0]; - wire [`L2CORE_TAG_WIDTH-1:0] per_cluster_io_rsp_tag [`NUM_CLUSTERS-1:0]; - wire [31:0] per_cluster_io_rsp_data [`NUM_CLUSTERS-1:0]; - wire per_cluster_io_rsp_ready [`NUM_CLUSTERS-1:0]; + wire [`NUM_CLUSTERS-1:0] per_cluster_io_rsp_valid; + wire [`NUM_CLUSTERS-1:0][`L2CORE_TAG_WIDTH-1:0] per_cluster_io_rsp_tag; + wire [`NUM_CLUSTERS-1:0][31:0] per_cluster_io_rsp_data; + wire [`NUM_CLUSTERS-1:0] per_cluster_io_rsp_ready; - wire per_cluster_csr_io_req_valid [`NUM_CLUSTERS-1:0]; - wire [11:0] per_cluster_csr_io_req_addr [`NUM_CLUSTERS-1:0]; - wire per_cluster_csr_io_req_rw [`NUM_CLUSTERS-1:0]; - wire [31:0] per_cluster_csr_io_req_data [`NUM_CLUSTERS-1:0]; - wire per_cluster_csr_io_req_ready [`NUM_CLUSTERS-1:0]; + wire [`NUM_CLUSTERS-1:0] per_cluster_csr_io_req_valid; + wire [`NUM_CLUSTERS-1:0][11:0] per_cluster_csr_io_req_addr; + wire [`NUM_CLUSTERS-1:0] per_cluster_csr_io_req_rw; + wire [`NUM_CLUSTERS-1:0][31:0] per_cluster_csr_io_req_data; + wire [`NUM_CLUSTERS-1:0] per_cluster_csr_io_req_ready; - wire per_cluster_csr_io_rsp_valid [`NUM_CLUSTERS-1:0]; - wire [31:0] per_cluster_csr_io_rsp_data [`NUM_CLUSTERS-1:0]; - wire per_cluster_csr_io_rsp_ready [`NUM_CLUSTERS-1:0]; + wire [`NUM_CLUSTERS-1:0] per_cluster_csr_io_rsp_valid; + wire [`NUM_CLUSTERS-1:0][31:0] per_cluster_csr_io_rsp_data; + wire [`NUM_CLUSTERS-1:0] per_cluster_csr_io_rsp_ready; - wire per_cluster_busy [`NUM_CLUSTERS-1:0]; - wire per_cluster_ebreak [`NUM_CLUSTERS-1:0]; + wire [`NUM_CLUSTERS-1:0] per_cluster_busy; + wire [`NUM_CLUSTERS-1:0] per_cluster_ebreak; wire [`CLOG2(`NUM_CLUSTERS)-1:0] csr_io_request_id = `CLOG2(`NUM_CLUSTERS)'(csr_io_req_coreid >> `CLOG2(`NUM_CLUSTERS)); wire [`NC_BITS-1:0] per_cluster_csr_io_req_coreid = `NC_BITS'(csr_io_req_coreid); - genvar i; - for (i = 0; i < `NUM_CLUSTERS; i++) begin + for (genvar i = 0; i < `NUM_CLUSTERS; i++) begin VX_cluster #( .CLUSTER_ID(i) ) cluster ( `SCOPE_SIGNALS_ISTAGE_BIND `SCOPE_SIGNALS_LSU_BIND - `SCOPE_SIGNALS_CORE_BIND `SCOPE_SIGNALS_CACHE_BIND - `SCOPE_SIGNALS_PIPELINE_BIND - `SCOPE_SIGNALS_BE_BIND + `SCOPE_SIGNALS_ISSUE_BIND + `SCOPE_SIGNALS_EXECUTE_BIND .clk (clk), .reset (reset), @@ -336,29 +332,29 @@ module Vortex ( // L3 Cache /////////////////////////////////////////////////////////// - wire l3_core_req_valid [`L3NUM_REQUESTS-1:0]; - wire l3_core_req_rw [`L3NUM_REQUESTS-1:0]; - wire [`L2DRAM_BYTEEN_WIDTH-1:0] l3_core_req_byteen [`L3NUM_REQUESTS-1:0]; - wire [`L2DRAM_ADDR_WIDTH-1:0] l3_core_req_addr [`L3NUM_REQUESTS-1:0]; - wire [`L2DRAM_LINE_WIDTH-1:0] l3_core_req_data [`L3NUM_REQUESTS-1:0]; - wire [`L2DRAM_TAG_WIDTH-1:0] l3_core_req_tag [`L3NUM_REQUESTS-1:0]; + wire [`L3NUM_REQUESTS-1:0] l3_core_req_valid; + wire [`L3NUM_REQUESTS-1:0] l3_core_req_rw; + wire [`L3NUM_REQUESTS-1:0][`L2DRAM_BYTEEN_WIDTH-1:0] l3_core_req_byteen; + wire [`L3NUM_REQUESTS-1:0][`L2DRAM_ADDR_WIDTH-1:0] l3_core_req_addr; + wire [`L3NUM_REQUESTS-1:0][`L2DRAM_LINE_WIDTH-1:0] l3_core_req_data; + wire [`L3NUM_REQUESTS-1:0][`L2DRAM_TAG_WIDTH-1:0] l3_core_req_tag; - wire l3_core_rsp_valid [`L3NUM_REQUESTS-1:0]; - wire [`L2DRAM_LINE_WIDTH-1:0] l3_core_rsp_data [`L3NUM_REQUESTS-1:0]; - wire [`L2DRAM_TAG_WIDTH-1:0] l3_core_rsp_tag [`L3NUM_REQUESTS-1:0]; - wire l3_core_rsp_ready; + wire [`L3NUM_REQUESTS-1:0] l3_core_rsp_valid; + wire [`L3NUM_REQUESTS-1:0][`L2DRAM_LINE_WIDTH-1:0] l3_core_rsp_data; + wire [`L3NUM_REQUESTS-1:0][`L2DRAM_TAG_WIDTH-1:0] l3_core_rsp_tag; + wire l3_core_rsp_ready; - wire l3_snp_fwdout_valid [`NUM_CLUSTERS-1:0]; - wire [`L2DRAM_ADDR_WIDTH-1:0] l3_snp_fwdout_addr [`NUM_CLUSTERS-1:0]; - wire l3_snp_fwdout_invalidate [`NUM_CLUSTERS-1:0]; - wire [`L2SNP_TAG_WIDTH-1:0] l3_snp_fwdout_tag [`NUM_CLUSTERS-1:0]; - wire l3_snp_fwdout_ready [`NUM_CLUSTERS-1:0]; + wire [`NUM_CLUSTERS-1:0] l3_snp_fwdout_valid; + wire [`NUM_CLUSTERS-1:0][`L2DRAM_ADDR_WIDTH-1:0] l3_snp_fwdout_addr; + wire [`NUM_CLUSTERS-1:0] l3_snp_fwdout_invalidate; + wire [`NUM_CLUSTERS-1:0][`L2SNP_TAG_WIDTH-1:0] l3_snp_fwdout_tag; + wire [`NUM_CLUSTERS-1:0] l3_snp_fwdout_ready; - wire l3_snp_fwdin_valid [`NUM_CLUSTERS-1:0]; - wire [`L2SNP_TAG_WIDTH-1:0] l3_snp_fwdin_tag [`NUM_CLUSTERS-1:0]; - wire l3_snp_fwdin_ready [`NUM_CLUSTERS-1:0]; + wire [`NUM_CLUSTERS-1:0] l3_snp_fwdin_valid; + wire [`NUM_CLUSTERS-1:0][`L2SNP_TAG_WIDTH-1:0] l3_snp_fwdin_tag; + wire [`NUM_CLUSTERS-1:0] l3_snp_fwdin_ready; - for (i = 0; i < `L3NUM_REQUESTS; i++) begin + for (genvar i = 0; i < `L3NUM_REQUESTS; i++) begin // Core Request assign l3_core_req_valid [i] = per_cluster_dram_req_valid [i]; assign l3_core_req_rw [i] = per_cluster_dram_req_rw [i]; @@ -394,7 +390,6 @@ module Vortex ( .NUM_BANKS (`L3NUM_BANKS), .WORD_SIZE (`L3WORD_SIZE), .NUM_REQUESTS (`L3NUM_REQUESTS), - .STAGE_1_CYCLES (`L3STAGE_1_CYCLES), .CREQ_SIZE (`L3CREQ_SIZE), .MRVQ_SIZE (`L3MRVQ_SIZE), .DFPQ_SIZE (`L3DFPQ_SIZE), diff --git a/hw/rtl/cache/VX_bank.v b/hw/rtl/cache/VX_bank.v index 57b6efe5..0f1fb8b8 100644 --- a/hw/rtl/cache/VX_bank.v +++ b/hw/rtl/cache/VX_bank.v @@ -13,8 +13,6 @@ module VX_bank #( parameter WORD_SIZE = 0, // Number of Word requests per cycle {1, 2, 4, 8, ...} parameter NUM_REQUESTS = 0, - // Number of cycles to complete i 1 (read from memory) - parameter STAGE_1_CYCLES = 0, // Queues feeding into banks Knobs {1, 2, 4, 8, ...} // Core Request Queue Size @@ -105,28 +103,25 @@ module VX_bank #( `ifdef DBG_CORE_REQ_INFO /* verilator lint_off UNUSED */ - wire[31:0] debug_use_pc_st0; - wire[1:0] debug_wb_st0; - wire[4:0] debug_rd_st0; - wire[`NW_BITS-1:0] debug_warp_num_st0; + wire[31:0] debug_pc_st0; + wire[`NR_BITS-1:0] debug_rd_st0; + wire[`NW_BITS-1:0] debug_wid_st0; wire debug_rw_st0; wire[WORD_SIZE-1:0] debug_byteen_st0; wire[`REQS_BITS-1:0] debug_tid_st0; wire[`UP(CORE_TAG_ID_BITS)-1:0] debug_tagid_st0; - wire[31:0] debug_use_pc_st1e; - wire[1:0] debug_wb_st1e; - wire[4:0] debug_rd_st1e; - wire[`NW_BITS-1:0] debug_warp_num_st1e; - wire debug_rw_st1e; - wire[WORD_SIZE-1:0] debug_byteen_st1e; - wire[`REQS_BITS-1:0] debug_tid_st1e; - wire[`UP(CORE_TAG_ID_BITS)-1:0] debug_tagid_st1e; + wire[31:0] debug_pc_st1; + wire[`NR_BITS-1:0] debug_rd_st1; + wire[`NW_BITS-1:0] debug_wid_st1; + wire debug_rw_st1; + wire[WORD_SIZE-1:0] debug_byteen_st1; + wire[`REQS_BITS-1:0] debug_tid_st1; + wire[`UP(CORE_TAG_ID_BITS)-1:0] debug_tagid_st1; - wire[31:0] debug_use_pc_st2; - wire[1:0] debug_wb_st2; - wire[4:0] debug_rd_st2; - wire[`NW_BITS-1:0] debug_warp_num_st2; + wire[31:0] debug_pc_st2; + wire[`NR_BITS-1:0] debug_rd_st2; + wire[`NW_BITS-1:0] debug_wid_st2; wire debug_rw_st2; wire[WORD_SIZE-1:0] debug_byteen_st2; wire[`REQS_BITS-1:0] debug_tid_st2; @@ -244,9 +239,9 @@ module VX_bank #( wire mrvq_is_snp_st0; wire mrvq_snp_invalidate_st0; - wire mrvq_pending_hazard_st1e; - wire st2_pending_hazard_st1e; - wire force_request_miss_st1e; + wire mrvq_pending_hazard_st1; + wire st2_pending_hazard_st1; + wire force_request_miss_st1; wire[`REQS_BITS-1:0] miss_add_tid; wire[`REQ_TAG_WIDTH-1:0] miss_add_tag; @@ -263,27 +258,15 @@ module VX_bank #( wire dwbq_push_stall; wire dram_fill_req_stall; wire stall_bank_pipe; - - reg is_fill_in_pipe; - wire is_fill_st1 [STAGE_1_CYCLES-1:0]; + wire is_fill_st1; `DEBUG_BEGIN - wire going_to_write_st1 [STAGE_1_CYCLES-1:0]; + wire going_to_write_st1; `DEBUG_END - - integer j; - always @(*) begin - is_fill_in_pipe = 0; - for (j = 0; j < STAGE_1_CYCLES; j++) begin - if (is_fill_st1[j]) begin - is_fill_in_pipe = 1; - end - end - end wire mrvq_pop_unqual = mrvq_valid_st0; wire dfpq_pop_unqual = !mrvq_pop_unqual && !dfpq_empty; - wire reqq_pop_unqual = !mrvq_stop && !mrvq_pop_unqual && !dfpq_pop_unqual && !reqq_empty && reqq_req_st0 && !is_fill_st1[0] && !is_fill_in_pipe; + wire reqq_pop_unqual = !mrvq_stop && !mrvq_pop_unqual && !dfpq_pop_unqual && !reqq_empty && reqq_req_st0 && !is_fill_st1 && !is_fill_st1; wire snrq_pop_unqual = !mrvq_stop && !reqq_pop_unqual && !reqq_pop_unqual && !mrvq_pop_unqual && !dfpq_pop_unqual && !snrq_empty && !reqq_req_st0; // if there's any reqq_req, don't schedule snrq. assign mrvq_pop = mrvq_pop_unqual && !stall_bank_pipe && !recover_mrvq_state_st2; @@ -304,15 +287,15 @@ module VX_bank #( wire qual_is_snp_st0; wire qual_snp_invalidate_st0; - wire valid_st1 [STAGE_1_CYCLES-1:0]; - wire [`LINE_ADDR_WIDTH-1:0] addr_st1 [STAGE_1_CYCLES-1:0]; - wire [`UP(`WORD_SELECT_WIDTH)-1:0] wsel_st1 [STAGE_1_CYCLES-1:0]; - wire [`WORD_WIDTH-1:0] writeword_st1 [STAGE_1_CYCLES-1:0]; - wire [`REQ_INST_META_WIDTH-1:0] inst_meta_st1 [STAGE_1_CYCLES-1:0]; - wire [`BANK_LINE_WIDTH-1:0] writedata_st1 [STAGE_1_CYCLES-1:0]; - wire is_snp_st1 [STAGE_1_CYCLES-1:0]; - wire snp_invalidate_st1 [STAGE_1_CYCLES-1:0]; - wire is_mrvq_st1 [STAGE_1_CYCLES-1:0]; + wire valid_st1; + wire [`LINE_ADDR_WIDTH-1:0] addr_st1; + wire [`UP(`WORD_SELECT_WIDTH)-1:0] wsel_st1; + wire [`WORD_WIDTH-1:0] writeword_st1; + wire [`REQ_INST_META_WIDTH-1:0] inst_meta_st1; + wire [`BANK_LINE_WIDTH-1:0] writedata_st1; + wire is_snp_st1; + wire snp_invalidate_st1; + wire is_mrvq_st1; assign qual_is_fill_st0 = dfpq_pop_unqual; @@ -360,130 +343,115 @@ module VX_bank #( `ifdef DBG_CORE_REQ_INFO if (WORD_SIZE != `GLOBAL_BLOCK_SIZE) begin - assign {debug_use_pc_st0, debug_wb_st0, debug_rd_st0, debug_warp_num_st0, debug_tagid_st0, debug_rw_st0, debug_byteen_st0, debug_tid_st0} = qual_inst_meta_st0; + assign {debug_pc_st0, debug_rd_st0, debug_wid_st0, debug_tagid_st0, debug_rw_st0, debug_byteen_st0, debug_tid_st0} = qual_inst_meta_st0; end `endif VX_generic_register #( .N(1 + 1 + 1 + 1 + 1 + `LINE_ADDR_WIDTH + `UP(`WORD_SELECT_WIDTH) + `WORD_WIDTH + `REQ_INST_META_WIDTH + 1 + `BANK_LINE_WIDTH) - ) s0_1_c0 ( + ) pipe_reg0 ( .clk (clk), .reset (reset), .stall (stall_bank_pipe), - .flush (1'b0), + .flush (0), .in ({qual_is_mrvq_st0, qual_is_snp_st0, qual_snp_invalidate_st0, qual_going_to_write_st0, qual_valid_st0, qual_addr_st0, qual_wsel_st0, qual_writeword_st0, qual_inst_meta_st0, qual_is_fill_st0, qual_writedata_st0}), - .out ({is_mrvq_st1[0] , is_snp_st1[0], snp_invalidate_st1[0], going_to_write_st1[0], valid_st1[0], addr_st1[0], wsel_st1[0], writeword_st1[0], inst_meta_st1[0], is_fill_st1[0], writedata_st1[0]}) + .out ({is_mrvq_st1 , is_snp_st1, snp_invalidate_st1, going_to_write_st1, valid_st1, addr_st1, wsel_st1, writeword_st1, inst_meta_st1, is_fill_st1, writedata_st1}) ); - genvar i; - for (i = 1; i < STAGE_1_CYCLES; i++) begin - VX_generic_register #( - .N(1 + 1 + 1 + 1 + 1 + `LINE_ADDR_WIDTH + `UP(`WORD_SELECT_WIDTH) + `WORD_WIDTH + `REQ_INST_META_WIDTH + 1 + `BANK_LINE_WIDTH) - ) s0_1_cc ( - .clk (clk), - .reset (reset), - .stall (stall_bank_pipe), - .flush (1'b0), - .in ({is_mrvq_st1[i-1], is_snp_st1[i-1], snp_invalidate_st1[i-1], going_to_write_st1[i-1], valid_st1[i-1], addr_st1[i-1], wsel_st1[i-1], writeword_st1[i-1], inst_meta_st1[i-1], is_fill_st1[i-1], writedata_st1[i-1]}), - .out ({is_mrvq_st1[i] , is_snp_st1[i], snp_invalidate_st1[i], going_to_write_st1[i], valid_st1[i], addr_st1[i], wsel_st1[i], writeword_st1[i], inst_meta_st1[i], is_fill_st1[i], writedata_st1[i]}) - ); - end - - wire[`WORD_WIDTH-1:0] readword_st1e; - wire[`BANK_LINE_WIDTH-1:0] readdata_st1e; - wire[`TAG_SELECT_BITS-1:0] readtag_st1e; - wire miss_st1e; - wire dirty_st1e; - wire[BANK_LINE_SIZE-1:0] dirtyb_st1e; + wire[`WORD_WIDTH-1:0] readword_st1; + wire[`BANK_LINE_WIDTH-1:0] readdata_st1; + wire[`TAG_SELECT_BITS-1:0] readtag_st1; + wire miss_st1; + wire dirty_st1; + wire[BANK_LINE_SIZE-1:0] dirtyb_st1; `DEBUG_BEGIN - wire [`REQ_TAG_WIDTH-1:0] tag_st1e; - wire [`REQS_BITS-1:0] tid_st1e; + wire [`REQ_TAG_WIDTH-1:0] tag_st1; + wire [`REQS_BITS-1:0] tid_st1; `DEBUG_END - wire mem_rw_st1e; - wire [WORD_SIZE-1:0] mem_byteen_st1e; - wire fill_saw_dirty_st1e; - wire is_snp_st1e; - wire snp_invalidate_st1e; - wire snp_to_mrvq_st1e; - wire mrvq_init_ready_state_st1e; + wire mem_rw_st1; + wire [WORD_SIZE-1:0] mem_byteen_st1; + wire fill_saw_dirty_st1; + wire snp_to_mrvq_st1; + wire mrvq_init_ready_state_st1; wire miss_add_because_miss; - wire valid_st1e; - wire is_mrvq_st1e; - wire mrvq_recover_ready_state_st1e; - wire[`LINE_ADDR_WIDTH-1:0] addr_st1e; + wire mrvq_recover_ready_state_st1; - assign is_mrvq_st1e = is_mrvq_st1[STAGE_1_CYCLES-1]; - assign valid_st1e = valid_st1 [STAGE_1_CYCLES-1]; - assign is_snp_st1e = is_snp_st1 [STAGE_1_CYCLES-1]; - assign snp_invalidate_st1e = snp_invalidate_st1 [STAGE_1_CYCLES-1]; - assign addr_st1e = addr_st1[STAGE_1_CYCLES-1]; + assign {tag_st1, mem_rw_st1, mem_byteen_st1, tid_st1} = inst_meta_st1; - assign {tag_st1e, mem_rw_st1e, mem_byteen_st1e, tid_st1e} = inst_meta_st1[STAGE_1_CYCLES-1]; + assign st2_pending_hazard_st1 = (miss_add_because_miss) + && ((addr_st2 == addr_st1) && !is_fill_st2); - assign st2_pending_hazard_st1e = (miss_add_because_miss) - && ((addr_st2 == addr_st1e) && !is_fill_st2); + assign force_request_miss_st1 = (valid_st1 && !is_mrvq_st1 && (mrvq_pending_hazard_st1 || st2_pending_hazard_st1)) + || (valid_st1 && is_mrvq_st1 && recover_mrvq_state_st2); - assign force_request_miss_st1e = (valid_st1e && !is_mrvq_st1e && (mrvq_pending_hazard_st1e || st2_pending_hazard_st1e)) - || (valid_st1e && is_mrvq_st1e && recover_mrvq_state_st2); - - assign mrvq_recover_ready_state_st1e = valid_st1e - && is_mrvq_st1e + assign mrvq_recover_ready_state_st1 = valid_st1 + && is_mrvq_st1 && recover_mrvq_state_st2 - && (addr_st2 == addr_st1e); + && (addr_st2 == addr_st1); VX_tag_data_access #( + .BANK_ID (BANK_ID), + .CACHE_ID (CACHE_ID), + .CORE_TAG_ID_BITS(CORE_TAG_ID_BITS), .CACHE_SIZE (CACHE_SIZE), .BANK_LINE_SIZE (BANK_LINE_SIZE), .NUM_BANKS (NUM_BANKS), .WORD_SIZE (WORD_SIZE), - .STAGE_1_CYCLES (STAGE_1_CYCLES), .DRAM_ENABLE (DRAM_ENABLE), .WRITE_ENABLE (WRITE_ENABLE) ) tag_data_access ( .clk (clk), .reset (reset), + + `ifdef DBG_CORE_REQ_INFO + .debug_pc_st1 (debug_pc_st1), + .debug_rd_st1 (debug_rd_st1), + .debug_wid_st1 (debug_wid_st1), + .debug_tagid_st1(debug_tagid_st1), + `endif + .stall (stall_bank_pipe), .stall_bank_pipe(stall_bank_pipe), - .force_request_miss_st1e(force_request_miss_st1e), + .force_request_miss_st1(force_request_miss_st1), // Initial Read - .readaddr_st10(addr_st1[0][`LINE_SELECT_BITS-1:0]), + .readaddr_st1(addr_st1[`LINE_SELECT_BITS-1:0]), // Actual Read/Write - .valid_req_st1e (valid_st1e), - .writefill_st1e (is_fill_st1[STAGE_1_CYCLES-1]), - .writeaddr_st1e (addr_st1e), - .wordsel_st1e (wsel_st1[STAGE_1_CYCLES-1]), - .writeword_st1e (writeword_st1[STAGE_1_CYCLES-1]), - .writedata_st1e (writedata_st1[STAGE_1_CYCLES-1]), + .valid_req_st1 (valid_st1), + .writefill_st1 (is_fill_st1), + .writeaddr_st1 (addr_st1), + .wordsel_st1 (wsel_st1), + .writeword_st1 (writeword_st1), + .writedata_st1 (writedata_st1), - .mem_rw_st1e (mem_rw_st1e), - .mem_byteen_st1e (mem_byteen_st1e), + .mem_rw_st1 (mem_rw_st1), + .mem_byteen_st1 (mem_byteen_st1), - .is_snp_st1e (is_snp_st1e), - .snp_invalidate_st1e (snp_invalidate_st1e), + .is_snp_st1 (is_snp_st1), + .snp_invalidate_st1(snp_invalidate_st1), // Read Data - .readword_st1e (readword_st1e), - .readdata_st1e (readdata_st1e), - .readtag_st1e (readtag_st1e), - .miss_st1e (miss_st1e), - .dirty_st1e (dirty_st1e), - .dirtyb_st1e (dirtyb_st1e), - .fill_saw_dirty_st1e (fill_saw_dirty_st1e), - .snp_to_mrvq_st1e (snp_to_mrvq_st1e), - .mrvq_init_ready_state_st1e(mrvq_init_ready_state_st1e) + .readword_st1 (readword_st1), + .readdata_st1 (readdata_st1), + .readtag_st1 (readtag_st1), + .miss_st1 (miss_st1), + .dirty_st1 (dirty_st1), + .dirtyb_st1 (dirtyb_st1), + .fill_saw_dirty_st1(fill_saw_dirty_st1), + .snp_to_mrvq_st1(snp_to_mrvq_st1), + .mrvq_init_ready_state_st1(mrvq_init_ready_state_st1) ); `ifdef DBG_CORE_REQ_INFO if (WORD_SIZE != `GLOBAL_BLOCK_SIZE) begin - assign {debug_use_pc_st1e, debug_wb_st1e, debug_rd_st1e, debug_warp_num_st1e, debug_tagid_st1e, debug_rw_st1e, debug_byteen_st1e, debug_tid_st1e} = inst_meta_st1[STAGE_1_CYCLES-1]; + assign {debug_pc_st1, debug_rd_st1, debug_wid_st1, debug_tagid_st1, debug_rw_st1, debug_byteen_st1, debug_tid_st1} = inst_meta_st1; end `endif - wire qual_valid_st1e_2 = valid_st1e && !is_fill_st1[STAGE_1_CYCLES-1]; - wire is_mrvq_st1e_st2 = is_mrvq_st1e; + wire qual_valid_st1_2 = valid_st1 && !is_fill_st1; + wire is_mrvq_st1_st2 = is_mrvq_st1; wire valid_st2; wire [`UP(`WORD_SELECT_WIDTH)-1:0] wsel_st2; @@ -504,22 +472,22 @@ module VX_bank #( wire mrvq_recover_ready_state_st2; wire mrvq_init_ready_state_unqual_st2; wire mrvq_init_ready_state_hazard_st0_st1; - wire mrvq_init_ready_state_hazard_st1e_st1; + wire mrvq_init_ready_state_hazard_st1_st1; VX_generic_register #( .N(1+ 1+ 1 + 1 + 1 + 1 + 1 + 1 + 1 + `LINE_ADDR_WIDTH + `UP(`WORD_SELECT_WIDTH) + `WORD_WIDTH + `WORD_WIDTH + `BANK_LINE_WIDTH + `TAG_SELECT_BITS + 1 + 1 + BANK_LINE_SIZE + `REQ_INST_META_WIDTH) - ) st_1e_2 ( + ) pipe_reg1 ( .clk (clk), .reset (reset), .stall (stall_bank_pipe), - .flush (1'b0), - .in ({mrvq_recover_ready_state_st1e, is_mrvq_st1e_st2, mrvq_init_ready_state_st1e , snp_to_mrvq_st1e, is_snp_st1e, snp_invalidate_st1e, fill_saw_dirty_st1e, is_fill_st1[STAGE_1_CYCLES-1] , qual_valid_st1e_2, addr_st1e, wsel_st1[STAGE_1_CYCLES-1], writeword_st1[STAGE_1_CYCLES-1], readword_st1e, readdata_st1e, readtag_st1e, miss_st1e, dirty_st1e, dirtyb_st1e, inst_meta_st1[STAGE_1_CYCLES-1]}), - .out ({mrvq_recover_ready_state_st2 , is_mrvq_st2 , mrvq_init_ready_state_unqual_st2, snp_to_mrvq_st2 , is_snp_st2 , snp_invalidate_st2, fill_saw_dirty_st2 , is_fill_st2 , valid_st2 , addr_st2 , wsel_st2, writeword_st2 , readword_st2 , readdata_st2 , readtag_st2 , miss_st2 , dirty_st2 , dirtyb_st2, inst_meta_st2 }) + .flush (0), + .in ({mrvq_recover_ready_state_st1, is_mrvq_st1_st2, mrvq_init_ready_state_st1, snp_to_mrvq_st1, is_snp_st1, snp_invalidate_st1, fill_saw_dirty_st1, is_fill_st1, qual_valid_st1_2, addr_st1, wsel_st1, writeword_st1, readword_st1, readdata_st1, readtag_st1, miss_st1, dirty_st1, dirtyb_st1, inst_meta_st1}), + .out ({mrvq_recover_ready_state_st2 , is_mrvq_st2 , mrvq_init_ready_state_unqual_st2, snp_to_mrvq_st2 , is_snp_st2 , snp_invalidate_st2, fill_saw_dirty_st2 , is_fill_st2 , valid_st2 , addr_st2, wsel_st2, writeword_st2, readword_st2, readdata_st2, readtag_st2, miss_st2, dirty_st2, dirtyb_st2, inst_meta_st2}) ); `ifdef DBG_CORE_REQ_INFO if (WORD_SIZE != `GLOBAL_BLOCK_SIZE) begin - assign {debug_use_pc_st2, debug_wb_st2, debug_rd_st2, debug_warp_num_st2, debug_tagid_st2, debug_rw_st2, debug_byteen_st2, debug_tid_st2} = inst_meta_st2; + assign {debug_pc_st2, debug_rd_st2, debug_wid_st2, debug_tagid_st2, debug_rw_st2, debug_byteen_st2, debug_tid_st2} = inst_meta_st2; end `endif @@ -531,10 +499,10 @@ module VX_bank #( assign mrvq_push_stall = miss_add_unqual && mrvq_full; wire miss_add = miss_add_unqual - && !mrvq_full - && !(cwbq_push_stall - || dwbq_push_stall - || dram_fill_req_stall); + && !mrvq_full + && !(cwbq_push_stall + || dwbq_push_stall + || dram_fill_req_stall); assign recover_mrvq_state_st2 = miss_add_unqual && is_mrvq_st2; // Doesn't need to include the stalls @@ -548,11 +516,11 @@ module VX_bank #( wire miss_add_is_mrvq = valid_st2 && is_mrvq_st2 && !stall_bank_pipe; assign mrvq_init_ready_state_hazard_st0_st1 = miss_add_unqual && qual_is_fill_st0 && (miss_add_addr == dfpq_addr_st0); // Doesn't need to be muxed to qual, only care about fills - assign mrvq_init_ready_state_hazard_st1e_st1 = miss_add_unqual && is_fill_st1[STAGE_1_CYCLES-1] && (miss_add_addr == addr_st1e); + assign mrvq_init_ready_state_hazard_st1_st1 = miss_add_unqual && is_fill_st1 && (miss_add_addr == addr_st1); assign mrvq_init_ready_state_st2 = mrvq_init_ready_state_unqual_st2 // When req was in st1e, either matched with an mrvq entery OR mrvq recovering state || mrvq_init_ready_state_hazard_st0_st1 // If there's a fill in st0 that has the same address as miss_add_addr - || mrvq_init_ready_state_hazard_st1e_st1; // If there's a fill in st1 that has the same address as miss_add_addr + || mrvq_init_ready_state_hazard_st1_st1; // If there's a fill in st1 that has the same address as miss_add_addr VX_cache_miss_resrv #( .BANK_ID (BANK_ID), @@ -585,9 +553,9 @@ module VX_bank #( .mrvq_init_ready_state (mrvq_init_ready_state_st2), // Broadcast - .is_fill_st1 (is_fill_st1[STAGE_1_CYCLES-1]), - .fill_addr_st1 (addr_st1e), - .pending_hazard (mrvq_pending_hazard_st1e), + .is_fill_st1 (is_fill_st1), + .fill_addr_st1 (addr_st1), + .pending_hazard_st1 (mrvq_pending_hazard_st1), // Dequeue .miss_resrv_pop (mrvq_pop), @@ -644,6 +612,7 @@ module VX_bank #( assign core_rsp_valid = !cwbq_empty; // Enqueue DRAM fill request + wire dram_fill_req_fast = miss_add_unqual; // Completely unqualified hint that we might send a dram_fill_req wire dram_fill_req_unqual = dram_fill_req_fast && (!mrvq_init_ready_state_st2 @@ -706,7 +675,9 @@ module VX_bank #( always @(posedge clk) begin if (reset) begin dwbq_dual_valid_sel <= 0; - end else if (dwbq_is_dwb_out && dwbq_is_snp_out && (dram_wb_req_fire || snp_rsp_fire)) begin + end else if (dwbq_is_dwb_out + && dwbq_is_snp_out + && (dram_wb_req_fire || snp_rsp_fire)) begin dwbq_dual_valid_sel <= ~dwbq_dual_valid_sel; end end @@ -728,41 +699,41 @@ module VX_bank #( `ifdef DBG_PRINT_CACHE_BANK always @(posedge clk) begin if ((|core_req_valid) && core_req_ready) begin - $display("%t: bank%0d:%0d core req: addr=%0h, tag=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(core_req_addr[0], BANK_ID), core_req_tag); + $display("%t: cache%0d:%0d core req: addr=%0h, tag=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(core_req_addr[0], BANK_ID), core_req_tag); end if (core_rsp_valid && core_rsp_ready) begin - $display("%t: bank%0d:%0d core rsp: tag=%0h, data=%0h", $time, CACHE_ID, BANK_ID, core_rsp_tag, core_rsp_data); + $display("%t: cache%0d:%0d core rsp: tag=%0h, data=%0h", $time, CACHE_ID, BANK_ID, core_rsp_tag, core_rsp_data); end if (dram_fill_req_valid && dram_fill_req_ready) begin - $display("%t: bank%0d:%0d dram_fill req: addr=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(dram_fill_req_addr, BANK_ID)); + $display("%t: cache%0d:%0d dram_fill req: addr=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(dram_fill_req_addr, BANK_ID)); end if (dram_wb_req_valid && dram_wb_req_ready) begin - $display("%t: bank%0d:%0d dram_wb req: addr=%0h, data=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(dram_wb_req_addr, BANK_ID), dram_wb_req_data); + $display("%t: cache%0d:%0d dram_wb req: addr=%0h, data=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(dram_wb_req_addr, BANK_ID), dram_wb_req_data); end if (dram_fill_rsp_valid && dram_fill_rsp_ready) begin - $display("%t: bank%0d:%0d dram_fill rsp: addr=%0h, data=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(dram_fill_rsp_addr, BANK_ID), dram_fill_rsp_data); + $display("%t: cache%0d:%0d dram_fill rsp: addr=%0h, data=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(dram_fill_rsp_addr, BANK_ID), dram_fill_rsp_data); end if (snp_req_valid && snp_req_ready) begin - $display("%t: bank%0d:%0d snp req: addr=%0h, invalidate=%0d, tag=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(snp_req_addr, BANK_ID), snp_req_invalidate, snp_req_tag); + $display("%t: cache%0d:%0d snp req: addr=%0h, invalidate=%0d, tag=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(snp_req_addr, BANK_ID), snp_req_invalidate, snp_req_tag); end if (snp_rsp_valid && snp_rsp_ready) begin - $display("%t: bank%0d:%0d snp rsp: tag=%0h", $time, CACHE_ID, BANK_ID, snp_rsp_tag); + $display("%t: cache%0d:%0d snp rsp: tag=%0h", $time, CACHE_ID, BANK_ID, snp_rsp_tag); end end `endif -`SCOPE_ASSIGN(scope_bank_valid_st0, qual_valid_st0); -`SCOPE_ASSIGN(scope_bank_valid_st1, valid_st1e); -`SCOPE_ASSIGN(scope_bank_valid_st2, valid_st2); +`SCOPE_ASSIGN (scope_bank_valid_st0, qual_valid_st0); +`SCOPE_ASSIGN (scope_bank_valid_st1, valid_st1); +`SCOPE_ASSIGN (scope_bank_valid_st2, valid_st2); -`SCOPE_ASSIGN(scope_bank_is_mrvq_st1, is_mrvq_st1e); -`SCOPE_ASSIGN(scope_bank_miss_st1, miss_st1e); -`SCOPE_ASSIGN(scope_bank_dirty_st1, dirty_st1e); -`SCOPE_ASSIGN(scope_bank_force_miss_st1, force_request_miss_st1e); -`SCOPE_ASSIGN(scope_bank_stall_pipe, stall_bank_pipe); +`SCOPE_ASSIGN (scope_bank_is_mrvq_st1, is_mrvq_st1); +`SCOPE_ASSIGN (scope_bank_miss_st1, miss_st1); +`SCOPE_ASSIGN (scope_bank_dirty_st1, dirty_st1); +`SCOPE_ASSIGN (scope_bank_force_miss_st1, force_request_miss_st1); +`SCOPE_ASSIGN (scope_bank_stall_pipe, stall_bank_pipe); -`SCOPE_ASSIGN(scope_bank_addr_st0, `LINE_TO_BYTE_ADDR(qual_addr_st0, BANK_ID)); -`SCOPE_ASSIGN(scope_bank_addr_st1, `LINE_TO_BYTE_ADDR(addr_st1e, BANK_ID)); -`SCOPE_ASSIGN(scope_bank_addr_st2, `LINE_TO_BYTE_ADDR(addr_st2, BANK_ID)); +`SCOPE_ASSIGN (scope_bank_addr_st0, `LINE_TO_BYTE_ADDR(qual_addr_st0, BANK_ID)); +`SCOPE_ASSIGN (scope_bank_addr_st1, `LINE_TO_BYTE_ADDR(addr_st1, BANK_ID)); +`SCOPE_ASSIGN (scope_bank_addr_st2, `LINE_TO_BYTE_ADDR(addr_st2, BANK_ID)); -endmodule : VX_bank +endmodule diff --git a/hw/rtl/cache/VX_cache.v b/hw/rtl/cache/VX_cache.v index e8bb3fb2..93bbc77e 100644 --- a/hw/rtl/cache/VX_cache.v +++ b/hw/rtl/cache/VX_cache.v @@ -12,8 +12,6 @@ module VX_cache #( parameter WORD_SIZE = 4, // Number of Word requests per cycle {1, 2, 4, 8, ...} parameter NUM_REQUESTS = 4, - // Number of cycles to complete stage 1 (read from memory) - parameter STAGE_1_CYCLES = 1, // Queues feeding into banks Knobs {1, 2, 4, 8, ...} @@ -130,14 +128,13 @@ module VX_cache #( `ifdef DBG_CORE_REQ_INFO /* verilator lint_off UNUSED */ wire[31:0] debug_core_req_use_pc; - wire[1:0] debug_core_req_wb; - wire[4:0] debug_core_req_rd; - wire[`NW_BITS-1:0] debug_core_req_warp_num; - wire[`LOG2UP(CREQ_SIZE)-1:0] debug_core_req_idx; + wire[`NR_BITS-1:0] debug_core_req_rd; + wire[`NW_BITS-1:0] debug_core_req_wid; + wire[`UP(CORE_TAG_ID_BITS)-1:0] debug_core_req_idx; /* verilator lint_on UNUSED */ if (WORD_SIZE != `GLOBAL_BLOCK_SIZE) begin - assign {debug_core_req_use_pc, debug_core_req_wb, debug_core_req_rd, debug_core_req_warp_num, debug_core_req_idx} = core_req_tag[0]; + assign {debug_core_req_use_pc, debug_core_req_rd, debug_core_req_wid, debug_core_req_idx} = core_req_tag[0]; end `endif @@ -246,190 +243,185 @@ module VX_cache #( assign dram_req_tag = dram_req_addr; assign dram_rsp_ready = (| per_bank_dram_fill_rsp_ready); - - genvar i; - generate - for (i = 0; i < NUM_BANKS; i++) begin - wire [NUM_REQUESTS-1:0] curr_bank_core_req_valid; - wire [NUM_REQUESTS-1:0] curr_bank_core_req_rw; - wire [NUM_REQUESTS-1:0][WORD_SIZE-1:0] curr_bank_core_req_byteen; - wire [NUM_REQUESTS-1:0][`WORD_ADDR_WIDTH-1:0] curr_bank_core_req_addr; - wire [`CORE_REQ_TAG_COUNT-1:0][CORE_TAG_WIDTH-1:0] curr_bank_core_req_tag; - wire [NUM_REQUESTS-1:0][`WORD_WIDTH-1:0] curr_bank_core_req_data; + for (genvar i = 0; i < NUM_BANKS; i++) begin + wire [NUM_REQUESTS-1:0] curr_bank_core_req_valid; + wire [NUM_REQUESTS-1:0] curr_bank_core_req_rw; + wire [NUM_REQUESTS-1:0][WORD_SIZE-1:0] curr_bank_core_req_byteen; + wire [NUM_REQUESTS-1:0][`WORD_ADDR_WIDTH-1:0] curr_bank_core_req_addr; + wire [`CORE_REQ_TAG_COUNT-1:0][CORE_TAG_WIDTH-1:0] curr_bank_core_req_tag; + wire [NUM_REQUESTS-1:0][`WORD_WIDTH-1:0] curr_bank_core_req_data; - wire curr_bank_core_rsp_valid; - wire [`REQS_BITS-1:0] curr_bank_core_rsp_tid; - wire [`WORD_WIDTH-1:0] curr_bank_core_rsp_data; - wire [CORE_TAG_WIDTH-1:0] curr_bank_core_rsp_tag; - wire curr_bank_core_rsp_ready; + wire curr_bank_core_rsp_valid; + wire [`REQS_BITS-1:0] curr_bank_core_rsp_tid; + wire [`WORD_WIDTH-1:0] curr_bank_core_rsp_data; + wire [CORE_TAG_WIDTH-1:0] curr_bank_core_rsp_tag; + wire curr_bank_core_rsp_ready; - wire curr_bank_dram_fill_rsp_valid; - wire [`BANK_LINE_WIDTH-1:0] curr_bank_dram_fill_rsp_data; - wire [`LINE_ADDR_WIDTH-1:0] curr_bank_dram_fill_rsp_addr; - wire curr_bank_dram_fill_rsp_ready; + wire curr_bank_dram_fill_rsp_valid; + wire [`BANK_LINE_WIDTH-1:0] curr_bank_dram_fill_rsp_data; + wire [`LINE_ADDR_WIDTH-1:0] curr_bank_dram_fill_rsp_addr; + wire curr_bank_dram_fill_rsp_ready; - wire curr_bank_dram_fill_req_valid; - wire [`LINE_ADDR_WIDTH-1:0] curr_bank_dram_fill_req_addr; - wire curr_bank_dram_fill_req_ready; + wire curr_bank_dram_fill_req_valid; + wire [`LINE_ADDR_WIDTH-1:0] curr_bank_dram_fill_req_addr; + wire curr_bank_dram_fill_req_ready; - wire curr_bank_dram_wb_req_valid; - wire [BANK_LINE_SIZE-1:0] curr_bank_dram_wb_req_byteen; - wire [`LINE_ADDR_WIDTH-1:0] curr_bank_dram_wb_req_addr; - wire[`BANK_LINE_WIDTH-1:0] curr_bank_dram_wb_req_data; - wire curr_bank_dram_wb_req_ready; + wire curr_bank_dram_wb_req_valid; + wire [BANK_LINE_SIZE-1:0] curr_bank_dram_wb_req_byteen; + wire [`LINE_ADDR_WIDTH-1:0] curr_bank_dram_wb_req_addr; + wire[`BANK_LINE_WIDTH-1:0] curr_bank_dram_wb_req_data; + wire curr_bank_dram_wb_req_ready; - wire curr_bank_snp_req_valid; - wire [`LINE_ADDR_WIDTH-1:0] curr_bank_snp_req_addr; - wire curr_bank_snp_req_invalidate; - wire [SNP_REQ_TAG_WIDTH-1:0] curr_bank_snp_req_tag; - wire curr_bank_snp_req_ready; + wire curr_bank_snp_req_valid; + wire [`LINE_ADDR_WIDTH-1:0] curr_bank_snp_req_addr; + wire curr_bank_snp_req_invalidate; + wire [SNP_REQ_TAG_WIDTH-1:0] curr_bank_snp_req_tag; + wire curr_bank_snp_req_ready; - wire curr_bank_snp_rsp_valid; - wire [SNP_REQ_TAG_WIDTH-1:0] curr_bank_snp_rsp_tag; - wire curr_bank_snp_rsp_ready; + wire curr_bank_snp_rsp_valid; + wire [SNP_REQ_TAG_WIDTH-1:0] curr_bank_snp_rsp_tag; + wire curr_bank_snp_rsp_ready; - wire curr_bank_core_req_ready; + wire curr_bank_core_req_ready; - // Core Req - assign curr_bank_core_req_valid = (per_bank_valid[i] & {NUM_REQUESTS{core_req_ready}}); - assign curr_bank_core_req_addr = core_req_addr; - assign curr_bank_core_req_rw = core_req_rw; - assign curr_bank_core_req_byteen = core_req_byteen; - assign curr_bank_core_req_data = core_req_data; - assign curr_bank_core_req_tag = core_req_tag; - assign per_bank_core_req_ready[i] = curr_bank_core_req_ready; + // Core Req + assign curr_bank_core_req_valid = (per_bank_valid[i] & {NUM_REQUESTS{core_req_ready}}); + assign curr_bank_core_req_addr = core_req_addr; + assign curr_bank_core_req_rw = core_req_rw; + assign curr_bank_core_req_byteen = core_req_byteen; + assign curr_bank_core_req_data = core_req_data; + assign curr_bank_core_req_tag = core_req_tag; + assign per_bank_core_req_ready[i] = curr_bank_core_req_ready; - // Core WB - assign curr_bank_core_rsp_ready = per_bank_core_rsp_ready[i]; - assign per_bank_core_rsp_valid [i] = curr_bank_core_rsp_valid; - assign per_bank_core_rsp_tid [i] = curr_bank_core_rsp_tid; - assign per_bank_core_rsp_tag [i] = curr_bank_core_rsp_tag; - assign per_bank_core_rsp_data [i] = curr_bank_core_rsp_data; + // Core WB + assign curr_bank_core_rsp_ready = per_bank_core_rsp_ready[i]; + assign per_bank_core_rsp_valid [i] = curr_bank_core_rsp_valid; + assign per_bank_core_rsp_tid [i] = curr_bank_core_rsp_tid; + assign per_bank_core_rsp_tag [i] = curr_bank_core_rsp_tag; + assign per_bank_core_rsp_data [i] = curr_bank_core_rsp_data; - // Dram fill request - assign per_bank_dram_fill_req_valid[i] = curr_bank_dram_fill_req_valid; - if (NUM_BANKS == 1) begin - assign per_bank_dram_fill_req_addr[i] = curr_bank_dram_fill_req_addr; - end else begin - assign per_bank_dram_fill_req_addr[i] = `LINE_TO_DRAM_ADDR(curr_bank_dram_fill_req_addr, i); - end - assign curr_bank_dram_fill_req_ready = dram_fill_req_ready; + // Dram fill request + assign per_bank_dram_fill_req_valid[i] = curr_bank_dram_fill_req_valid; + if (NUM_BANKS == 1) begin + assign per_bank_dram_fill_req_addr[i] = curr_bank_dram_fill_req_addr; + end else begin + assign per_bank_dram_fill_req_addr[i] = `LINE_TO_DRAM_ADDR(curr_bank_dram_fill_req_addr, i); + end + assign curr_bank_dram_fill_req_ready = dram_fill_req_ready; + + // Dram fill response + if (NUM_BANKS == 1) begin + assign curr_bank_dram_fill_rsp_valid = dram_rsp_valid; + assign curr_bank_dram_fill_rsp_addr = dram_rsp_tag; + end else begin + assign curr_bank_dram_fill_rsp_valid = dram_rsp_valid && (`DRAM_ADDR_BANK(dram_rsp_tag) == i); + assign curr_bank_dram_fill_rsp_addr = `DRAM_TO_LINE_ADDR(dram_rsp_tag); + end + assign curr_bank_dram_fill_rsp_data = dram_rsp_data; + assign per_bank_dram_fill_rsp_ready[i] = curr_bank_dram_fill_rsp_ready; + + // Dram writeback request + assign per_bank_dram_wb_req_valid[i] = curr_bank_dram_wb_req_valid; + assign per_bank_dram_wb_req_byteen[i] = curr_bank_dram_wb_req_byteen; + if (NUM_BANKS == 1) begin + assign per_bank_dram_wb_req_addr[i] = curr_bank_dram_wb_req_addr; + end else begin + assign per_bank_dram_wb_req_addr[i] = `LINE_TO_DRAM_ADDR(curr_bank_dram_wb_req_addr, i); + end + assign per_bank_dram_wb_req_data[i] = curr_bank_dram_wb_req_data; + assign curr_bank_dram_wb_req_ready = per_bank_dram_wb_req_ready[i]; + + // Snoop request + if (NUM_BANKS == 1) begin + assign curr_bank_snp_req_valid = snp_req_valid_qual; + assign curr_bank_snp_req_addr = snp_req_addr_qual; + end else begin + assign curr_bank_snp_req_valid = snp_req_valid_qual && (`DRAM_ADDR_BANK(snp_req_addr_qual) == i); + assign curr_bank_snp_req_addr = `DRAM_TO_LINE_ADDR(snp_req_addr_qual); + end + assign curr_bank_snp_req_invalidate = snp_req_invalidate_qual; + assign curr_bank_snp_req_tag = snp_req_tag_qual; + assign per_bank_snp_req_ready[i] = curr_bank_snp_req_ready; + + // Snoop response + assign per_bank_snp_rsp_valid[i] = curr_bank_snp_rsp_valid; + assign per_bank_snp_rsp_tag[i] = curr_bank_snp_rsp_tag; + assign curr_bank_snp_rsp_ready = per_bank_snp_rsp_ready[i]; + + VX_bank #( + .BANK_ID (i), + .CACHE_ID (CACHE_ID), + .CACHE_SIZE (CACHE_SIZE), + .BANK_LINE_SIZE (BANK_LINE_SIZE), + .NUM_BANKS (NUM_BANKS), + .WORD_SIZE (WORD_SIZE), + .NUM_REQUESTS (NUM_REQUESTS), + .CREQ_SIZE (CREQ_SIZE), + .MRVQ_SIZE (MRVQ_SIZE), + .DFPQ_SIZE (DFPQ_SIZE), + .SNRQ_SIZE (SNRQ_SIZE), + .CWBQ_SIZE (CWBQ_SIZE), + .DWBQ_SIZE (DWBQ_SIZE), + .DFQQ_SIZE (DFQQ_SIZE), + .DRAM_ENABLE (DRAM_ENABLE), + .WRITE_ENABLE (WRITE_ENABLE), + .SNOOP_FORWARDING (SNOOP_FORWARDING), + .CORE_TAG_WIDTH (CORE_TAG_WIDTH), + .CORE_TAG_ID_BITS (CORE_TAG_ID_BITS), + .SNP_REQ_TAG_WIDTH (SNP_REQ_TAG_WIDTH) + ) bank ( + `SCOPE_SIGNALS_CACHE_BANK_BIND + + .clk (clk), + .reset (reset), + // Core request + .core_req_valid (curr_bank_core_req_valid), + .core_req_rw (curr_bank_core_req_rw), + .core_req_byteen (curr_bank_core_req_byteen), + .core_req_addr (curr_bank_core_req_addr), + .core_req_data (curr_bank_core_req_data), + .core_req_tag (curr_bank_core_req_tag), + .core_req_ready (curr_bank_core_req_ready), + + // Core response + .core_rsp_valid (curr_bank_core_rsp_valid), + .core_rsp_tid (curr_bank_core_rsp_tid), + .core_rsp_data (curr_bank_core_rsp_data), + .core_rsp_tag (curr_bank_core_rsp_tag), + .core_rsp_ready (curr_bank_core_rsp_ready), + + // Dram fill request + .dram_fill_req_valid (curr_bank_dram_fill_req_valid), + .dram_fill_req_addr (curr_bank_dram_fill_req_addr), + .dram_fill_req_ready (curr_bank_dram_fill_req_ready), // Dram fill response - if (NUM_BANKS == 1) begin - assign curr_bank_dram_fill_rsp_valid = dram_rsp_valid; - assign curr_bank_dram_fill_rsp_addr = dram_rsp_tag; - end else begin - assign curr_bank_dram_fill_rsp_valid = dram_rsp_valid && (`DRAM_ADDR_BANK(dram_rsp_tag) == i); - assign curr_bank_dram_fill_rsp_addr = `DRAM_TO_LINE_ADDR(dram_rsp_tag); - end - assign curr_bank_dram_fill_rsp_data = dram_rsp_data; - assign per_bank_dram_fill_rsp_ready[i] = curr_bank_dram_fill_rsp_ready; + .dram_fill_rsp_valid (curr_bank_dram_fill_rsp_valid), + .dram_fill_rsp_data (curr_bank_dram_fill_rsp_data), + .dram_fill_rsp_addr (curr_bank_dram_fill_rsp_addr), + .dram_fill_rsp_ready (curr_bank_dram_fill_rsp_ready), - // Dram writeback request - assign per_bank_dram_wb_req_valid[i] = curr_bank_dram_wb_req_valid; - assign per_bank_dram_wb_req_byteen[i] = curr_bank_dram_wb_req_byteen; - if (NUM_BANKS == 1) begin - assign per_bank_dram_wb_req_addr[i] = curr_bank_dram_wb_req_addr; - end else begin - assign per_bank_dram_wb_req_addr[i] = `LINE_TO_DRAM_ADDR(curr_bank_dram_wb_req_addr, i); - end - assign per_bank_dram_wb_req_data[i] = curr_bank_dram_wb_req_data; - assign curr_bank_dram_wb_req_ready = per_bank_dram_wb_req_ready[i]; + // Dram writeback request + .dram_wb_req_valid (curr_bank_dram_wb_req_valid), + .dram_wb_req_byteen (curr_bank_dram_wb_req_byteen), + .dram_wb_req_addr (curr_bank_dram_wb_req_addr), + .dram_wb_req_data (curr_bank_dram_wb_req_data), + .dram_wb_req_ready (curr_bank_dram_wb_req_ready), // Snoop request - if (NUM_BANKS == 1) begin - assign curr_bank_snp_req_valid = snp_req_valid_qual; - assign curr_bank_snp_req_addr = snp_req_addr_qual; - end else begin - assign curr_bank_snp_req_valid = snp_req_valid_qual && (`DRAM_ADDR_BANK(snp_req_addr_qual) == i); - assign curr_bank_snp_req_addr = `DRAM_TO_LINE_ADDR(snp_req_addr_qual); - end - assign curr_bank_snp_req_invalidate = snp_req_invalidate_qual; - assign curr_bank_snp_req_tag = snp_req_tag_qual; - assign per_bank_snp_req_ready[i] = curr_bank_snp_req_ready; + .snp_req_valid (curr_bank_snp_req_valid), + .snp_req_addr (curr_bank_snp_req_addr), + .snp_req_invalidate (curr_bank_snp_req_invalidate), + .snp_req_tag (curr_bank_snp_req_tag), + .snp_req_ready (curr_bank_snp_req_ready), - // Snoop response - assign per_bank_snp_rsp_valid[i] = curr_bank_snp_rsp_valid; - assign per_bank_snp_rsp_tag[i] = curr_bank_snp_rsp_tag; - assign curr_bank_snp_rsp_ready = per_bank_snp_rsp_ready[i]; - - VX_bank #( - .BANK_ID (i), - .CACHE_ID (CACHE_ID), - .CACHE_SIZE (CACHE_SIZE), - .BANK_LINE_SIZE (BANK_LINE_SIZE), - .NUM_BANKS (NUM_BANKS), - .WORD_SIZE (WORD_SIZE), - .NUM_REQUESTS (NUM_REQUESTS), - .STAGE_1_CYCLES (STAGE_1_CYCLES), - .CREQ_SIZE (CREQ_SIZE), - .MRVQ_SIZE (MRVQ_SIZE), - .DFPQ_SIZE (DFPQ_SIZE), - .SNRQ_SIZE (SNRQ_SIZE), - .CWBQ_SIZE (CWBQ_SIZE), - .DWBQ_SIZE (DWBQ_SIZE), - .DFQQ_SIZE (DFQQ_SIZE), - .DRAM_ENABLE (DRAM_ENABLE), - .WRITE_ENABLE (WRITE_ENABLE), - .SNOOP_FORWARDING (SNOOP_FORWARDING), - .CORE_TAG_WIDTH (CORE_TAG_WIDTH), - .CORE_TAG_ID_BITS (CORE_TAG_ID_BITS), - .SNP_REQ_TAG_WIDTH (SNP_REQ_TAG_WIDTH) - ) bank ( - `SCOPE_SIGNALS_CACHE_BANK_BIND - - .clk (clk), - .reset (reset), - // Core request - .core_req_valid (curr_bank_core_req_valid), - .core_req_rw (curr_bank_core_req_rw), - .core_req_byteen (curr_bank_core_req_byteen), - .core_req_addr (curr_bank_core_req_addr), - .core_req_data (curr_bank_core_req_data), - .core_req_tag (curr_bank_core_req_tag), - .core_req_ready (curr_bank_core_req_ready), - - // Core response - .core_rsp_valid (curr_bank_core_rsp_valid), - .core_rsp_tid (curr_bank_core_rsp_tid), - .core_rsp_data (curr_bank_core_rsp_data), - .core_rsp_tag (curr_bank_core_rsp_tag), - .core_rsp_ready (curr_bank_core_rsp_ready), - - // Dram fill request - .dram_fill_req_valid (curr_bank_dram_fill_req_valid), - .dram_fill_req_addr (curr_bank_dram_fill_req_addr), - .dram_fill_req_ready (curr_bank_dram_fill_req_ready), - - // Dram fill response - .dram_fill_rsp_valid (curr_bank_dram_fill_rsp_valid), - .dram_fill_rsp_data (curr_bank_dram_fill_rsp_data), - .dram_fill_rsp_addr (curr_bank_dram_fill_rsp_addr), - .dram_fill_rsp_ready (curr_bank_dram_fill_rsp_ready), - - // Dram writeback request - .dram_wb_req_valid (curr_bank_dram_wb_req_valid), - .dram_wb_req_byteen (curr_bank_dram_wb_req_byteen), - .dram_wb_req_addr (curr_bank_dram_wb_req_addr), - .dram_wb_req_data (curr_bank_dram_wb_req_data), - .dram_wb_req_ready (curr_bank_dram_wb_req_ready), - - // Snoop request - .snp_req_valid (curr_bank_snp_req_valid), - .snp_req_addr (curr_bank_snp_req_addr), - .snp_req_invalidate (curr_bank_snp_req_invalidate), - .snp_req_tag (curr_bank_snp_req_tag), - .snp_req_ready (curr_bank_snp_req_ready), - - // Snoop response - .snp_rsp_valid (curr_bank_snp_rsp_valid), - .snp_rsp_tag (curr_bank_snp_rsp_tag), - .snp_rsp_ready (curr_bank_snp_rsp_ready) - ); - end - endgenerate + // Snoop response + .snp_rsp_valid (curr_bank_snp_rsp_valid), + .snp_rsp_tag (curr_bank_snp_rsp_tag), + .snp_rsp_ready (curr_bank_snp_rsp_ready) + ); + end VX_cache_dram_req_arb #( .BANK_LINE_SIZE (BANK_LINE_SIZE), diff --git a/hw/rtl/cache/VX_cache_config.vh b/hw/rtl/cache/VX_cache_config.vh index 3e835196..1237c1c6 100644 --- a/hw/rtl/cache/VX_cache_config.vh +++ b/hw/rtl/cache/VX_cache_config.vh @@ -1,10 +1,17 @@ `ifndef VX_CACHE_CONFIG `define VX_CACHE_CONFIG +`include "VX_platform.vh" +`include "VX_scope.vh" + +`ifdef DBG_CORE_REQ_INFO `include "VX_define.vh" +`endif `define REQ_TAG_WIDTH `MAX(CORE_TAG_WIDTH, SNP_REQ_TAG_WIDTH) +`define REQS_BITS `LOG2UP(NUM_REQUESTS) + // tag rw byteen tid `define REQ_INST_META_WIDTH (`REQ_TAG_WIDTH + 1 + WORD_SIZE + `REQS_BITS) @@ -74,4 +81,6 @@ `define LINE_TO_BYTE_ADDR(x, i) {x, (32-$bits(x))'(i << (32-$bits(x)-`BANK_SELECT_BITS))} +`define DRAM_TO_BYTE_ADDR(x) {x, (32-$bits(x))'(0)} + `endif diff --git a/hw/rtl/cache/VX_cache_core_req_bank_sel.v b/hw/rtl/cache/VX_cache_core_req_bank_sel.v index 46efa586..1a479b5c 100644 --- a/hw/rtl/cache/VX_cache_core_req_bank_sel.v +++ b/hw/rtl/cache/VX_cache_core_req_bank_sel.v @@ -1,4 +1,3 @@ - `include "VX_cache_config.vh" module VX_cache_core_req_bank_sel #( @@ -15,31 +14,33 @@ module VX_cache_core_req_bank_sel #( `IGNORE_WARNINGS_BEGIN input wire [NUM_REQUESTS-1:0][`WORD_ADDR_WIDTH-1:0] core_req_addr, `IGNORE_WARNINGS_END - input wire [NUM_BANKS-1:0] per_bank_ready, - output reg [NUM_BANKS-1:0][NUM_REQUESTS-1:0] per_bank_valid, + input wire [NUM_BANKS-1:0] per_bank_ready, + output wire [NUM_BANKS-1:0][NUM_REQUESTS-1:0] per_bank_valid, output wire core_req_ready ); - integer i; + reg [NUM_BANKS-1:0][NUM_REQUESTS-1:0] per_bank_valid_r; if (NUM_BANKS == 1) begin always @(*) begin - per_bank_valid = 0; - for (i = 0; i < NUM_REQUESTS; i++) begin - per_bank_valid[0][i] = core_req_valid[i]; + per_bank_valid_r = 0; + for (integer i = 0; i < NUM_REQUESTS; i++) begin + per_bank_valid_r[0][i] = core_req_valid[i]; end end assign core_req_ready = per_bank_ready; end else begin reg [NUM_BANKS-1:0] per_bank_ready_sel; always @(*) begin - per_bank_valid = 0; + per_bank_valid_r = 0; per_bank_ready_sel = {NUM_BANKS{1'b1}}; - for (i = 0; i < NUM_REQUESTS; i++) begin - per_bank_valid[core_req_addr[i][`BANK_SELECT_ADDR_RNG]][i] = core_req_valid[i]; + for (integer i = 0; i < NUM_REQUESTS; i++) begin + per_bank_valid_r[core_req_addr[i][`BANK_SELECT_ADDR_RNG]][i] = core_req_valid[i]; per_bank_ready_sel[core_req_addr[i][`BANK_SELECT_ADDR_RNG]] = 0; end end assign core_req_ready = & (per_bank_ready | per_bank_ready_sel); end + assign per_bank_valid = per_bank_valid_r; + endmodule \ No newline at end of file diff --git a/hw/rtl/cache/VX_cache_core_rsp_merge.v b/hw/rtl/cache/VX_cache_core_rsp_merge.v index 849d8907..7cf8b1c8 100644 --- a/hw/rtl/cache/VX_cache_core_rsp_merge.v +++ b/hw/rtl/cache/VX_cache_core_rsp_merge.v @@ -23,9 +23,9 @@ module VX_cache_core_rsp_merge #( output wire [NUM_BANKS-1:0] per_bank_core_rsp_ready, // Core Writeback - output reg [NUM_REQUESTS-1:0] core_rsp_valid, - output reg [NUM_REQUESTS-1:0][`WORD_WIDTH-1:0] core_rsp_data, - output reg [`CORE_REQ_TAG_COUNT-1:0][CORE_TAG_WIDTH-1:0] core_rsp_tag, + output wire [NUM_REQUESTS-1:0] core_rsp_valid, + output wire [NUM_REQUESTS-1:0][`WORD_WIDTH-1:0] core_rsp_data, + output wire [`CORE_REQ_TAG_COUNT-1:0][CORE_TAG_WIDTH-1:0] core_rsp_tag, input wire core_rsp_ready ); @@ -41,47 +41,61 @@ module VX_cache_core_rsp_merge #( `UNUSED_PIN (grant_onehot) ); - reg [NUM_BANKS-1:0] per_bank_core_rsp_pop_unqual; + reg [NUM_REQUESTS-1:0] core_rsp_valid_unqual; + reg [NUM_REQUESTS-1:0][`WORD_WIDTH-1:0] core_rsp_data_unqual; + reg [`CORE_REQ_TAG_COUNT-1:0][CORE_TAG_WIDTH-1:0] core_rsp_tag_unqual; + reg [NUM_BANKS-1:0] core_rsp_bank_select; - assign per_bank_core_rsp_ready = per_bank_core_rsp_pop_unqual & {NUM_BANKS{core_rsp_ready}}; - - integer i; + wire stall = ~core_rsp_ready && (| core_rsp_valid); if (CORE_TAG_ID_BITS != 0) begin - assign core_rsp_tag = per_bank_core_rsp_tag[main_bank_index]; always @(*) begin - core_rsp_valid = 0; - core_rsp_data = 0; - for (i = 0; i < NUM_BANKS; i++) begin + core_rsp_valid_unqual = 0; + core_rsp_data_unqual = 0; + core_rsp_tag_unqual = per_bank_core_rsp_tag[main_bank_index]; + for (integer i = 0; i < NUM_BANKS; i++) begin if (per_bank_core_rsp_valid[i] && (per_bank_core_rsp_tag[i][CORE_TAG_ID_BITS-1:0] == per_bank_core_rsp_tag[main_bank_index][CORE_TAG_ID_BITS-1:0])) begin - core_rsp_valid[per_bank_core_rsp_tid[i]] = 1; - core_rsp_data[per_bank_core_rsp_tid[i]] = per_bank_core_rsp_data[i]; - per_bank_core_rsp_pop_unqual[i] = 1; + core_rsp_valid_unqual[per_bank_core_rsp_tid[i]] = 1; + core_rsp_data_unqual[per_bank_core_rsp_tid[i]] = per_bank_core_rsp_data[i]; + core_rsp_bank_select[i] = 1; end else begin - per_bank_core_rsp_pop_unqual[i] = 0; + core_rsp_bank_select[i] = 0; end end end end else begin always @(*) begin - core_rsp_valid = 0; - core_rsp_data = 0; - core_rsp_tag = 0; - for (i = 0; i < NUM_BANKS; i++) begin + core_rsp_valid_unqual = 0; + core_rsp_data_unqual = 0; + core_rsp_tag_unqual = 0; + for (integer i = 0; i < NUM_BANKS; i++) begin if (per_bank_core_rsp_valid[i] - && !core_rsp_valid[per_bank_core_rsp_tid[i]] + && !core_rsp_valid_unqual[per_bank_core_rsp_tid[i]] && ((main_bank_index == `BANK_BITS'(i)) || (per_bank_core_rsp_tid[i] != per_bank_core_rsp_tid[main_bank_index]))) begin - core_rsp_valid[per_bank_core_rsp_tid[i]] = 1; - core_rsp_data[per_bank_core_rsp_tid[i]] = per_bank_core_rsp_data[i]; - core_rsp_tag[per_bank_core_rsp_tid[i]] = per_bank_core_rsp_tag[i]; - per_bank_core_rsp_pop_unqual[i] = 1; + core_rsp_valid_unqual[per_bank_core_rsp_tid[i]] = 1; + core_rsp_data_unqual[per_bank_core_rsp_tid[i]] = per_bank_core_rsp_data[i]; + core_rsp_tag_unqual[per_bank_core_rsp_tid[i]] = per_bank_core_rsp_tag[i]; + core_rsp_bank_select[i] = 1; end else begin - per_bank_core_rsp_pop_unqual[i] = 0; + core_rsp_bank_select[i] = 0; end end end end + VX_generic_register #( + .N(NUM_REQUESTS + (NUM_REQUESTS *`WORD_WIDTH) + (`CORE_REQ_TAG_COUNT * CORE_TAG_WIDTH)) + ) core_wb_reg ( + .clk (clk), + .reset (reset), + .stall (stall), + .flush (0), + .in ({core_rsp_valid_unqual, core_rsp_data_unqual, core_rsp_tag_unqual}), + .out ({core_rsp_valid, core_rsp_data, core_rsp_tag}) + ); + + assign per_bank_core_rsp_ready = core_rsp_bank_select & {NUM_BANKS{~stall}}; + endmodule diff --git a/hw/rtl/cache/VX_cache_dram_req_arb.v b/hw/rtl/cache/VX_cache_dram_req_arb.v index 03989a28..f3117fd2 100644 --- a/hw/rtl/cache/VX_cache_dram_req_arb.v +++ b/hw/rtl/cache/VX_cache_dram_req_arb.v @@ -106,8 +106,7 @@ module VX_cache_dram_req_arb #( `UNUSED_PIN (grant_onehot) ); - genvar i; - for (i = 0; i < NUM_BANKS; i++) begin + for (genvar i = 0; i < NUM_BANKS; i++) begin assign per_bank_dram_wb_req_ready[i] = dram_req_ready && (dwb_bank == `BANK_BITS'(i)); end diff --git a/hw/rtl/cache/VX_cache_miss_resrv.v b/hw/rtl/cache/VX_cache_miss_resrv.v index c851629c..61c4bcfb 100644 --- a/hw/rtl/cache/VX_cache_miss_resrv.v +++ b/hw/rtl/cache/VX_cache_miss_resrv.v @@ -41,7 +41,7 @@ module VX_cache_miss_resrv #( input wire is_fill_st1, input wire[`LINE_ADDR_WIDTH-1:0] fill_addr_st1, - output wire pending_hazard, + output wire pending_hazard_st1, // Miss dequeue input wire miss_resrv_pop, @@ -77,16 +77,13 @@ module VX_cache_miss_resrv #( reg [MRVQ_SIZE-1:0] make_ready; reg [MRVQ_SIZE-1:0] make_ready_push; reg [MRVQ_SIZE-1:0] valid_address_match; + + for (genvar i = 0; i < MRVQ_SIZE; i++) begin + assign valid_address_match[i] = valid_table[i] ? (addr_table[i] == fill_addr_st1) : 0; + assign make_ready[i] = is_fill_st1 && valid_address_match[i]; + end - genvar i; - generate - for (i = 0; i < MRVQ_SIZE; i++) begin - assign valid_address_match[i] = valid_table[i] ? (addr_table[i] == fill_addr_st1) : 0; - assign make_ready[i] = is_fill_st1 && valid_address_match[i]; - end - endgenerate - - assign pending_hazard = |(valid_address_match); + assign pending_hazard_st1 = |(valid_address_match); wire dequeue_possible = valid_table[schedule_ptr] && ready_table[schedule_ptr]; wire [`LOG2UP(MRVQ_SIZE)-1:0] dequeue_index = schedule_ptr; @@ -123,7 +120,6 @@ module VX_cache_miss_resrv #( head_ptr <= 0; tail_ptr <= 0; end else begin - if (mrvq_push) begin valid_table[enqueue_index] <= 1; ready_table[enqueue_index] <= mrvq_init_ready_state; @@ -159,11 +155,10 @@ module VX_cache_miss_resrv #( end `ifdef DBG_PRINT_CACHE_MSRQ - integer j; always @(posedge clk) begin if (mrvq_push || mrvq_pop || increment_head || recover_state) begin - $write("%t: bank%0d:%0d msrq: push=%b pop=%b incr=%d recv=%d", $time, CACHE_ID, BANK_ID, mrvq_push, mrvq_pop, increment_head, recover_state); - for (j = 0; j < MRVQ_SIZE; j++) begin + $write("%t: cache%0d:%0d msrq: push=%b pop=%b incr=%d recv=%d", $time, CACHE_ID, BANK_ID, mrvq_push, mrvq_pop, increment_head, recover_state); + for (integer j = 0; j < MRVQ_SIZE; j++) begin if (valid_table[j]) begin $write(" "); if (schedule_ptr == $bits(schedule_ptr)'(j)) $write("*"); diff --git a/hw/rtl/cache/VX_snp_forwarder.v b/hw/rtl/cache/VX_snp_forwarder.v index f54b6eba..d1a7433a 100644 --- a/hw/rtl/cache/VX_snp_forwarder.v +++ b/hw/rtl/cache/VX_snp_forwarder.v @@ -41,8 +41,8 @@ module VX_snp_forwarder #( reg [`REQS_BITS:0] pending_cntrs [SNRQ_SIZE-1:0]; - wire [`LOG2UP(SNRQ_SIZE)-1:0] sfq_write_addr, sfq_read_addr, dbg_sfq_write_addr; - wire sfq_push, sfq_pop, sfq_full; + wire [`LOG2UP(SNRQ_SIZE)-1:0] sfq_write_addr, sfq_read_addr; + wire sfq_acquire, sfq_release, sfq_full; wire fwdin_valid; wire [`LOG2UP(SNRQ_SIZE)-1:0] fwdin_tag; @@ -56,38 +56,35 @@ module VX_snp_forwarder #( assign sfq_read_addr = fwdin_tag; - assign sfq_push = snp_req_valid && !sfq_full && fwdout_ready; - assign sfq_pop = snp_rsp_valid; + assign sfq_acquire = snp_req_valid && !sfq_full && fwdout_ready; + assign sfq_release = snp_rsp_valid; - VX_indexable_queue #( - .DATAW (`LOG2UP(SNRQ_SIZE) + 1 +`DRAM_ADDR_WIDTH+SNP_REQ_TAG_WIDTH), + VX_cam_buffer #( + .DATAW (`DRAM_ADDR_WIDTH + 1 + SNP_REQ_TAG_WIDTH), .SIZE (SNRQ_SIZE) - ) snp_fwd_queue ( - .clk (clk), - .reset (reset), - .write_data ({sfq_write_addr, snp_req_addr, snp_req_invalidate, snp_req_tag}), - .write_addr (sfq_write_addr), - .push (sfq_push), - .pop (sfq_pop), - .full (sfq_full), - .read_addr (sfq_read_addr), - .read_data ({dbg_sfq_write_addr, snp_rsp_addr, snp_rsp_invalidate, snp_rsp_tag}), - `UNUSED_PIN (empty) + ) snp_fwd_cam ( + .clk (clk), + .reset (reset), + .write_addr (sfq_write_addr), + .acquire_slot (sfq_acquire), + .read_addr (sfq_read_addr), + .write_data ({snp_req_addr, snp_req_invalidate, snp_req_tag}), + .read_data ({snp_rsp_addr, snp_rsp_invalidate, snp_rsp_tag}), + .release_addr (sfq_read_addr), + .release_slot (sfq_release), + .full (sfq_full) ); always @(posedge clk) begin - if (sfq_push) begin + if (sfq_acquire) begin pending_cntrs[sfq_write_addr] <= NUM_REQUESTS; end if (fwdin_fire) begin pending_cntrs[sfq_read_addr] <= pending_cntrs[sfq_read_addr] - 1; - assert(sfq_read_addr == dbg_sfq_write_addr); end end - genvar i; - - for (i = 0; i < NUM_REQUESTS; i++) begin + for (genvar i = 0; i < NUM_REQUESTS; i++) begin assign snp_fwdout_valid[i] = snp_req_valid && snp_req_ready; assign snp_fwdout_addr[i] = snp_req_addr; assign snp_fwdout_invalidate[i] = snp_req_invalidate; @@ -112,7 +109,7 @@ module VX_snp_forwarder #( assign fwdin_valid = snp_fwdin_valid[fwdin_sel]; assign fwdin_tag = snp_fwdin_tag[fwdin_sel]; - for (i = 0; i < NUM_REQUESTS; i++) begin + for (genvar i = 0; i < NUM_REQUESTS; i++) begin assign snp_fwdin_ready[i] = fwdin_ready && (fwdin_sel == `REQS_BITS'(i)); end diff --git a/hw/rtl/cache/VX_snp_rsp_arb.v b/hw/rtl/cache/VX_snp_rsp_arb.v index e9662c34..331b73a1 100644 --- a/hw/rtl/cache/VX_snp_rsp_arb.v +++ b/hw/rtl/cache/VX_snp_rsp_arb.v @@ -34,8 +34,7 @@ module VX_snp_rsp_arb #( assign snp_rsp_valid = fsq_valid; assign snp_rsp_tag = per_bank_snp_rsp_tag[fsq_bank]; - genvar i; - for (i = 0; i < NUM_BANKS; i++) begin + for (genvar i = 0; i < NUM_BANKS; i++) begin assign per_bank_snp_rsp_ready[i] = snp_rsp_ready && (fsq_bank == `BANK_BITS'(i)); end diff --git a/hw/rtl/cache/VX_tag_data_access.v b/hw/rtl/cache/VX_tag_data_access.v index 6dfb5b98..a1b80838 100644 --- a/hw/rtl/cache/VX_tag_data_access.v +++ b/hw/rtl/cache/VX_tag_data_access.v @@ -1,75 +1,80 @@ `include "VX_cache_config.vh" module VX_tag_data_access #( + parameter CACHE_ID = 0, + parameter BANK_ID = 0, + parameter CORE_TAG_ID_BITS = 0, // Size of cache in bytes - parameter CACHE_SIZE = 0, + parameter CACHE_SIZE = 0, // Size of line inside a bank in bytes - parameter BANK_LINE_SIZE = 0, + parameter BANK_LINE_SIZE = 0, // Number of banks {1, 2, 4, 8,...} - parameter NUM_BANKS = 0, + parameter NUM_BANKS = 0, // Size of a word in bytes - parameter WORD_SIZE = 0, - - // Number of cycles to complete stage 1 (read from memory) - parameter STAGE_1_CYCLES = 0, + parameter WORD_SIZE = 0, // Enable cache writeable - parameter WRITE_ENABLE = 0, + parameter WRITE_ENABLE = 0, // Enable dram update - parameter DRAM_ENABLE = 0 + parameter DRAM_ENABLE = 0 ) ( input wire clk, input wire reset, + +`ifdef DBG_CORE_REQ_INFO +`IGNORE_WARNINGS_BEGIN + input wire[31:0] debug_pc_st1, + input wire[`NR_BITS-1:0] debug_rd_st1, + input wire[`NW_BITS-1:0] debug_wid_st1, + input wire[`UP(CORE_TAG_ID_BITS)-1:0] debug_tagid_st1, +`IGNORE_WARNINGS_END +`endif + input wire stall, - input wire is_snp_st1e, - input wire snp_invalidate_st1e, + input wire is_snp_st1, + input wire snp_invalidate_st1, input wire stall_bank_pipe, - input wire force_request_miss_st1e, + input wire force_request_miss_st1, - input wire[`LINE_SELECT_BITS-1:0] readaddr_st10, - input wire[`LINE_ADDR_WIDTH-1:0] writeaddr_st1e, + input wire[`LINE_SELECT_BITS-1:0] readaddr_st1, + input wire[`LINE_ADDR_WIDTH-1:0] writeaddr_st1, - input wire valid_req_st1e, - input wire writefill_st1e, - input wire[`WORD_WIDTH-1:0] writeword_st1e, - input wire[`BANK_LINE_WIDTH-1:0] writedata_st1e, + input wire valid_req_st1, + input wire writefill_st1, + input wire[`WORD_WIDTH-1:0] writeword_st1, + input wire[`BANK_LINE_WIDTH-1:0] writedata_st1, `IGNORE_WARNINGS_BEGIN - input wire mem_rw_st1e, - input wire[WORD_SIZE-1:0] mem_byteen_st1e, - input wire[`UP(`WORD_SELECT_WIDTH)-1:0] wordsel_st1e, + input wire mem_rw_st1, + input wire[WORD_SIZE-1:0] mem_byteen_st1, + input wire[`UP(`WORD_SELECT_WIDTH)-1:0] wordsel_st1, `IGNORE_WARNINGS_END - output wire[`WORD_WIDTH-1:0] readword_st1e, - output wire[`BANK_LINE_WIDTH-1:0] readdata_st1e, - output wire[`TAG_SELECT_BITS-1:0] readtag_st1e, - output wire miss_st1e, - output wire dirty_st1e, - output wire[BANK_LINE_SIZE-1:0] dirtyb_st1e, - output wire fill_saw_dirty_st1e, - output wire snp_to_mrvq_st1e, - output wire mrvq_init_ready_state_st1e + output wire[`WORD_WIDTH-1:0] readword_st1, + output wire[`BANK_LINE_WIDTH-1:0] readdata_st1, + output wire[`TAG_SELECT_BITS-1:0] readtag_st1, + output wire miss_st1, + output wire dirty_st1, + output wire[BANK_LINE_SIZE-1:0] dirtyb_st1, + output wire fill_saw_dirty_st1, + output wire snp_to_mrvq_st1, + output wire mrvq_init_ready_state_st1 ); - - wire read_valid_st1c[STAGE_1_CYCLES-1:0]; - wire read_dirty_st1c[STAGE_1_CYCLES-1:0]; - wire[BANK_LINE_SIZE-1:0] read_dirtyb_st1c[STAGE_1_CYCLES-1:0]; - wire[`TAG_SELECT_BITS-1:0] read_tag_st1c [STAGE_1_CYCLES-1:0]; - wire[`BANK_LINE_WIDTH-1:0] read_data_st1c [STAGE_1_CYCLES-1:0]; - + `UNUSED_VAR (stall) + wire qual_read_valid_st1; wire qual_read_dirty_st1; wire[BANK_LINE_SIZE-1:0] qual_read_dirtyb_st1; wire[`TAG_SELECT_BITS-1:0] qual_read_tag_st1; wire[`BANK_LINE_WIDTH-1:0] qual_read_data_st1; - wire use_read_valid_st1e; - wire use_read_dirty_st1e; - wire[BANK_LINE_SIZE-1:0] use_read_dirtyb_st1e; - wire[`TAG_SELECT_BITS-1:0] use_read_tag_st1e; - wire[`BANK_LINE_WIDTH-1:0] use_read_data_st1e; + wire use_read_valid_st1; + wire use_read_dirty_st1; + wire[BANK_LINE_SIZE-1:0] use_read_dirtyb_st1; + wire[`TAG_SELECT_BITS-1:0] use_read_tag_st1; + wire[`BANK_LINE_WIDTH-1:0] use_read_data_st1; wire[`BANK_LINE_WORDS-1:0][WORD_SIZE-1:0] use_write_enable; wire[`BANK_LINE_WIDTH-1:0] use_write_data; @@ -77,23 +82,23 @@ module VX_tag_data_access #( wire invalidate_line; wire tags_match; - wire real_writefill = valid_req_st1e && writefill_st1e - && ((!use_read_valid_st1e) || (use_read_valid_st1e && !tags_match)); + wire real_writefill = valid_req_st1 && writefill_st1 + && ((~use_read_valid_st1) || (use_read_valid_st1 && ~tags_match)); - wire[`TAG_SELECT_BITS-1:0] writetag_st1e = writeaddr_st1e[`TAG_LINE_ADDR_RNG]; - wire[`LINE_SELECT_BITS-1:0] writeladdr_st1e = writeaddr_st1e[`LINE_SELECT_BITS-1:0]; + wire[`TAG_SELECT_BITS-1:0] writetag_st1 = writeaddr_st1[`TAG_LINE_ADDR_RNG]; + wire[`LINE_SELECT_BITS-1:0] writeladdr_st1 = writeaddr_st1[`LINE_SELECT_BITS-1:0]; - VX_tag_data_structure #( - .CACHE_SIZE (CACHE_SIZE), - .BANK_LINE_SIZE (BANK_LINE_SIZE), - .NUM_BANKS (NUM_BANKS), - .WORD_SIZE (WORD_SIZE) - ) tag_data_structure ( + VX_tag_data_store #( + .CACHE_SIZE (CACHE_SIZE), + .BANK_LINE_SIZE (BANK_LINE_SIZE), + .NUM_BANKS (NUM_BANKS), + .WORD_SIZE (WORD_SIZE) + ) tag_data_store ( .clk (clk), .reset (reset), .stall_bank_pipe(stall_bank_pipe), - .read_addr (readaddr_st10), + .read_addr (readaddr_st1), .read_valid (qual_read_valid_st1), .read_dirty (qual_read_dirty_st1), .read_dirtyb (qual_read_dirtyb_st1), @@ -103,98 +108,93 @@ module VX_tag_data_access #( .invalidate (invalidate_line), .write_enable(use_write_enable), .write_fill (real_writefill), - .write_addr (writeladdr_st1e), - .tag_index (writetag_st1e), + .write_addr (writeladdr_st1), + .tag_index (writetag_st1), .write_data (use_write_data), .fill_sent (fill_sent) ); - VX_generic_register #( - .N(1 + 1 + BANK_LINE_SIZE + `TAG_SELECT_BITS + `BANK_LINE_WIDTH), - .PASSTHRU(1) - ) s0_1_c0 ( - .clk (clk), - .reset (reset), - .stall (stall), - .flush (1'b0), - .in ({qual_read_valid_st1, qual_read_dirty_st1, qual_read_dirtyb_st1, qual_read_tag_st1, qual_read_data_st1}), - .out ({read_valid_st1c[0], read_dirty_st1c[0], read_dirtyb_st1c[0], read_tag_st1c[0], read_data_st1c[0]}) - ); - - genvar i; - for (i = 1; i < STAGE_1_CYCLES-1; i++) begin - VX_generic_register #( - .N( 1 + 1 + BANK_LINE_SIZE + `TAG_SELECT_BITS + `BANK_LINE_WIDTH) - ) s0_1_cc ( - .clk (clk), - .reset (reset), - .stall (stall), - .flush (1'b0), - .in ({read_valid_st1c[i-1], read_dirty_st1c[i-1], read_dirtyb_st1c[i-1], read_tag_st1c[i-1], read_data_st1c[i-1]}), - .out ({read_valid_st1c[i], read_dirty_st1c[i], read_dirtyb_st1c[i], read_tag_st1c[i], read_data_st1c[i]}) - ); - end - - assign use_read_valid_st1e = read_valid_st1c[STAGE_1_CYCLES-1] || !DRAM_ENABLE; // If shared memory, always valid - assign use_read_dirty_st1e = read_dirty_st1c[STAGE_1_CYCLES-1] && DRAM_ENABLE && WRITE_ENABLE; // Dirty only applies in Dcache - assign use_read_tag_st1e = DRAM_ENABLE ? read_tag_st1c[STAGE_1_CYCLES-1] : writetag_st1e; // Tag is always the same in SM - assign use_read_dirtyb_st1e= read_dirtyb_st1c[STAGE_1_CYCLES-1]; - assign use_read_data_st1e = read_data_st1c[STAGE_1_CYCLES-1]; - + assign use_read_valid_st1 = qual_read_valid_st1 || !DRAM_ENABLE; // If shared memory, always valid + assign use_read_dirty_st1 = qual_read_dirty_st1 && DRAM_ENABLE && WRITE_ENABLE; // Dirty only applies in Dcache + assign use_read_tag_st1 = DRAM_ENABLE ? qual_read_tag_st1 : writetag_st1; // Tag is always the same in SM + assign use_read_dirtyb_st1= qual_read_dirtyb_st1; + assign use_read_data_st1 = qual_read_data_st1; + if (`WORD_SELECT_WIDTH != 0) begin - assign readword_st1e = use_read_data_st1e[wordsel_st1e * `WORD_WIDTH +: `WORD_WIDTH]; + wire [`WORD_WIDTH-1:0] readword = use_read_data_st1[wordsel_st1 * `WORD_WIDTH +: `WORD_WIDTH]; + for (genvar i = 0; i < WORD_SIZE; i++) begin + assign readword_st1[i * 8 +: 8] = readword[i * 8 +: 8] & {8{mem_byteen_st1[i]}}; + end end else begin - assign readword_st1e = use_read_data_st1e; + for (genvar i = 0; i < WORD_SIZE; i++) begin + assign readword_st1[i * 8 +: 8] = use_read_data_st1[i * 8 +: 8] & {8{mem_byteen_st1[i]}}; + end end wire [`BANK_LINE_WORDS-1:0][WORD_SIZE-1:0] we; wire [`BANK_LINE_WIDTH-1:0] data_write; - wire should_write = mem_rw_st1e - && valid_req_st1e - && use_read_valid_st1e - && !miss_st1e - && !is_snp_st1e - && !real_writefill; + wire should_write = mem_rw_st1 + && valid_req_st1 + && use_read_valid_st1 + && ~miss_st1 + && ~is_snp_st1 + && ~real_writefill; - for (i = 0; i < `BANK_LINE_WORDS; i++) begin - wire normal_write = ((`WORD_SELECT_WIDTH == 0) || (wordsel_st1e == `UP(`WORD_SELECT_WIDTH)'(i))) + for (genvar i = 0; i < `BANK_LINE_WORDS; i++) begin + wire normal_write = ((`WORD_SELECT_WIDTH == 0) || (wordsel_st1 == `UP(`WORD_SELECT_WIDTH)'(i))) && should_write; assign we[i] = real_writefill ? {WORD_SIZE{1'b1}} : - normal_write ? mem_byteen_st1e : + normal_write ? mem_byteen_st1 : {WORD_SIZE{1'b0}}; - assign data_write[i * `WORD_WIDTH +: `WORD_WIDTH] = real_writefill ? writedata_st1e[i * `WORD_WIDTH +: `WORD_WIDTH] : writeword_st1e; + assign data_write[i * `WORD_WIDTH +: `WORD_WIDTH] = real_writefill ? writedata_st1[i * `WORD_WIDTH +: `WORD_WIDTH] : writeword_st1; end - assign use_write_enable = (writefill_st1e && !real_writefill) ? 0 : we; + assign use_write_enable = (writefill_st1 && ~real_writefill) ? 0 : we; assign use_write_data = data_write; // use "case equality" to handle uninitialized tag when block entry is not valid - assign tags_match = (writetag_st1e === use_read_tag_st1e); + assign tags_match = (writetag_st1 === use_read_tag_st1); - wire snoop_hit_no_pending = valid_req_st1e && is_snp_st1e && use_read_valid_st1e && tags_match && (use_read_dirty_st1e || snp_invalidate_st1e) && !force_request_miss_st1e; - wire req_invalid = valid_req_st1e && !is_snp_st1e && !use_read_valid_st1e && !writefill_st1e; - wire req_miss = valid_req_st1e && !is_snp_st1e && use_read_valid_st1e && !writefill_st1e && !tags_match; + wire snoop_hit_no_pending = valid_req_st1 && is_snp_st1 && use_read_valid_st1 && tags_match && (use_read_dirty_st1 || snp_invalidate_st1) && ~force_request_miss_st1; + wire req_invalid = valid_req_st1 && ~is_snp_st1 && ~use_read_valid_st1 && ~writefill_st1; + wire req_miss = valid_req_st1 && ~is_snp_st1 && use_read_valid_st1 && ~writefill_st1 && ~tags_match; wire real_miss = req_invalid || req_miss; - wire force_core_miss = (force_request_miss_st1e && !is_snp_st1e && !writefill_st1e && valid_req_st1e && !real_miss); - assign snp_to_mrvq_st1e = valid_req_st1e && is_snp_st1e && force_request_miss_st1e; + wire force_core_miss = (force_request_miss_st1 && ~is_snp_st1 && ~writefill_st1 && valid_req_st1 && ~real_miss); + assign snp_to_mrvq_st1 = valid_req_st1 && is_snp_st1 && force_request_miss_st1; // The second term is basically saying always make an entry ready if there's already antoher entry waiting, even if you yourself see a miss - assign mrvq_init_ready_state_st1e = snp_to_mrvq_st1e - || (force_request_miss_st1e && !is_snp_st1e && !writefill_st1e && valid_req_st1e); - - assign miss_st1e = real_miss || snoop_hit_no_pending || force_core_miss; - assign dirty_st1e = valid_req_st1e && use_read_valid_st1e && use_read_dirty_st1e; - assign dirtyb_st1e = use_read_dirtyb_st1e; - assign readdata_st1e = use_read_data_st1e; - assign readtag_st1e = use_read_tag_st1e; - assign fill_sent = miss_st1e; - assign fill_saw_dirty_st1e = real_writefill && dirty_st1e; - assign invalidate_line = snoop_hit_no_pending; - -endmodule + assign mrvq_init_ready_state_st1 = snp_to_mrvq_st1 + || (force_request_miss_st1 && ~is_snp_st1 && ~writefill_st1 && valid_req_st1); + assign miss_st1 = real_miss || snoop_hit_no_pending || force_core_miss; + assign dirty_st1 = valid_req_st1 && use_read_valid_st1 && use_read_dirty_st1; + assign dirtyb_st1 = use_read_dirtyb_st1; + assign readdata_st1 = use_read_data_st1; + assign readtag_st1 = use_read_tag_st1; + assign fill_sent = miss_st1; + assign fill_saw_dirty_st1 = real_writefill && dirty_st1; + assign invalidate_line = snoop_hit_no_pending; +`ifdef DBG_PRINT_CACHE_BANK + always @(posedge clk) begin + if (valid_req_st1) begin + if ((| use_write_enable)) begin + if (writefill_st1) begin + $display("%t: cache%0d:%0d store-fill: wid=%0d, PC=%0h, tag=%0h, rd=%0d, dirty=%b, blk_addr=%0d, tag_id=%0h, data=%0h", $time, CACHE_ID, BANK_ID, debug_wid_st1, debug_pc_st1, debug_tagid_st1, debug_rd_st1, dirty_st1, writeladdr_st1, writetag_st1, use_write_data); + end else begin + $display("%t: cache%0d:%0d store-write: wid=%0d, PC=%0h, tag=%0h, rd=%0d, dirty=%b, blk_addr=%0d, tag_id=%0h, wsel=%0d, data=%0h", $time, CACHE_ID, BANK_ID, debug_wid_st1, debug_pc_st1, debug_tagid_st1, debug_rd_st1, dirty_st1, writeladdr_st1, writetag_st1, wordsel_st1, writeword_st1); + end + end else + if (miss_st1) begin + $display("%t: cache%0d:%0d store-miss: wid=%0d, PC=%0h, tag=%0h, rd=%0d, dirty=%b", $time, CACHE_ID, BANK_ID, debug_wid_st1, debug_pc_st1, debug_tagid_st1, debug_rd_st1, dirty_st1); + end else begin + $display("%t: cache%0d:%0d store-read: wid=%0d, PC=%0h, tag=%0h, rd=%0d, dirty=%b, blk_addr=%0d, tag_id=%0h, wsel=%0d, data=%0h", $time, CACHE_ID, BANK_ID, debug_wid_st1, debug_pc_st1, debug_tagid_st1, debug_rd_st1, dirty_st1, readaddr_st1, qual_read_tag_st1, wordsel_st1, qual_read_data_st1); + end + end + end +`endif +endmodule \ No newline at end of file diff --git a/hw/rtl/cache/VX_tag_data_structure.v b/hw/rtl/cache/VX_tag_data_store.v similarity index 88% rename from hw/rtl/cache/VX_tag_data_structure.v rename to hw/rtl/cache/VX_tag_data_store.v index 1d32f37d..e0f356cc 100644 --- a/hw/rtl/cache/VX_tag_data_structure.v +++ b/hw/rtl/cache/VX_tag_data_store.v @@ -1,6 +1,6 @@ `include "VX_cache_config.vh" -module VX_tag_data_structure #( +module VX_tag_data_store #( // Size of cache in bytes parameter CACHE_SIZE = 0, // Size of line inside a bank in bytes @@ -44,10 +44,9 @@ module VX_tag_data_structure #( wire do_write = (| write_enable); - integer i, j; always @(posedge clk) begin if (reset) begin - for (i = 0; i < `BANK_LINE_COUNT; i++) begin + for (integer i = 0; i < `BANK_LINE_COUNT; i++) begin valid[i] <= 0; dirty[i] <= 0; end @@ -71,10 +70,10 @@ module VX_tag_data_structure #( valid[write_addr] <= 0; end - for (i = 0; i < `BANK_LINE_WORDS; i++) begin - for (j = 0; j < WORD_SIZE; j++) begin - if (write_enable[i][j]) begin - data[write_addr][i][j] <= write_data[i * `WORD_WIDTH + j * 8 +: 8]; + for (integer j = 0; j < `BANK_LINE_WORDS; j++) begin + for (integer i = 0; i < WORD_SIZE; i++) begin + if (write_enable[j][i]) begin + data[write_addr][j][i] <= write_data[j * `WORD_WIDTH + i * 8 +: 8]; end end end diff --git a/hw/rtl/fp_cores/VX_fp_addmul.v b/hw/rtl/fp_cores/VX_fp_addmul.v new file mode 100644 index 00000000..b1053e95 --- /dev/null +++ b/hw/rtl/fp_cores/VX_fp_addmul.v @@ -0,0 +1,187 @@ +`include "VX_define.vh" + +`ifndef SYNTHESIS +`include "float_dpi.vh" +`endif + +module VX_fp_addmul #( + parameter TAGW = 1, + parameter LANES = 1 +) ( + input wire clk, + input wire reset, + + output wire ready_in, + input wire valid_in, + + input wire [TAGW-1:0] tag_in, + + input wire do_sub, + input wire do_mul, + + input wire [LANES-1:0][31:0] dataa, + input wire [LANES-1:0][31:0] datab, + output wire [LANES-1:0][31:0] result, + + output wire [TAGW-1:0] tag_out, + + input wire ready_out, + output wire valid_out +); + + wire stall = ~ready_out && valid_out; + wire enable = ~stall; + + reg do_sub_r, do_mul_r; + + for (genvar i = 0; i < LANES; i++) begin + + wire [31:0] result_add; + wire [31:0] result_sub; + wire [31:0] result_mul; + + `ifdef QUARTUS + twentynm_fp_mac mac_fp_add ( + // inputs + .accumulate(), + .chainin_overflow(), + .chainin_invalid(), + .chainin_underflow(), + .chainin_inexact(), + .ax(dataa[i]), + .ay(datab[i]), + .az(), + .clk({2'b00,clk}), + .ena({2'b11,enable}), + .aclr(2'b00), + .chainin(), + // outputs + .overflow(), + .invalid(), + .underflow(), + .inexact(), + .chainout_overflow(), + .chainout_invalid(), + .chainout_underflow(), + .chainout_inexact(), + .resulta(result_add), + .chainout() + ); + defparam mac_fp_add.operation_mode = "sp_add"; + defparam mac_fp_add.use_chainin = "false"; + defparam mac_fp_add.adder_subtract = "false"; + defparam mac_fp_add.ax_clock = "0"; + defparam mac_fp_add.ay_clock = "0"; + defparam mac_fp_add.az_clock = "none"; + defparam mac_fp_add.output_clock = "0"; + defparam mac_fp_add.accumulate_clock = "none"; + defparam mac_fp_add.ax_chainin_pl_clock = "none"; + defparam mac_fp_add.accum_pipeline_clock = "none"; + defparam mac_fp_add.mult_pipeline_clock = "none"; + defparam mac_fp_add.adder_input_clock = "0"; + defparam mac_fp_add.accum_adder_clock = "none"; + + twentynm_fp_mac mac_fp_sub ( + // inputs + .accumulate(), + .chainin_overflow(), + .chainin_invalid(), + .chainin_underflow(), + .chainin_inexact(), + .ax(dataa[i]), + .ay(datab[i]), + .az(), + .clk({2'b00,clk}), + .ena({2'b11,enable}), + .aclr(2'b00), + .chainin(), + // outputs + .overflow(), + .invalid(), + .underflow(), + .inexact(), + .chainout_overflow(), + .chainout_invalid(), + .chainout_underflow(), + .chainout_inexact(), + .resulta(result_sub), + .chainout() + ); + defparam mac_fp_sub.operation_mode = "sp_add"; + defparam mac_fp_sub.use_chainin = "false"; + defparam mac_fp_sub.adder_subtract = "true"; + defparam mac_fp_sub.ax_clock = "0"; + defparam mac_fp_sub.ay_clock = "0"; + defparam mac_fp_sub.az_clock = "none"; + defparam mac_fp_sub.output_clock = "0"; + defparam mac_fp_sub.accumulate_clock = "none"; + defparam mac_fp_sub.ax_chainin_pl_clock = "none"; + defparam mac_fp_sub.accum_pipeline_clock = "none"; + defparam mac_fp_sub.mult_pipeline_clock = "none"; + defparam mac_fp_sub.adder_input_clock = "0"; + defparam mac_fp_sub.accum_adder_clock = "none"; + + twentynm_fp_mac mac_fp_mul ( + // inputs + .accumulate(), + .chainin_overflow(), + .chainin_invalid(), + .chainin_underflow(), + .chainin_inexact(), + .ax(), + .ay(datab[i]), + .az(dataa[i]), + .clk({2'b00,clk}), + .ena({2'b11,enable}), + .aclr(2'b00), + .chainin(), + // outputs + .overflow(), + .invalid(), + .underflow(), + .inexact(), + .chainout_overflow(), + .chainout_invalid(), + .chainout_underflow(), + .chainout_inexact(), + .resulta(result_mul), + .chainout() + ); + defparam mac_fp_mul.operation_mode = "sp_mult"; + defparam mac_fp_mul.use_chainin = "false"; + defparam mac_fp_mul.adder_subtract = "false"; + defparam mac_fp_mul.ax_clock = "none"; + defparam mac_fp_mul.ay_clock = "0"; + defparam mac_fp_mul.az_clock = "0"; + defparam mac_fp_mul.output_clock = "0"; + defparam mac_fp_mul.accumulate_clock = "none"; + defparam mac_fp_mul.ax_chainin_pl_clock = "none"; + defparam mac_fp_mul.accum_pipeline_clock = "none"; + defparam mac_fp_mul.mult_pipeline_clock = "0"; + defparam mac_fp_mul.adder_input_clock = "none"; + defparam mac_fp_mul.accum_adder_clock = "none"; + `else + always @(posedge clk) begin + dpi_fadd(0*LANES+i, enable, dataa[i], datab[i], result_add); + dpi_fsub(1*LANES+i, enable, dataa[i], datab[i], result_sub); + dpi_fmul(2*LANES+i, enable, dataa[i], datab[i], result_mul); + end + `endif + + assign result[i] = do_mul_r ? result_mul : (do_sub_r ? result_sub : result_add); + end + + VX_shift_register #( + .DATAW(TAGW + 1 + 1 + 1), + .DEPTH(`LATENCY_FADDMUL) + ) shift_reg ( + .clk(clk), + .reset(reset), + .enable(enable), + .in({tag_in, valid_in, do_sub, do_mul}), + .out({tag_out, valid_out, do_sub_r, do_mul_r}) + ); + + assign ready_in = enable; + +endmodule diff --git a/hw/rtl/fp_cores/VX_fp_div.v b/hw/rtl/fp_cores/VX_fp_div.v new file mode 100644 index 00000000..f5e624ef --- /dev/null +++ b/hw/rtl/fp_cores/VX_fp_div.v @@ -0,0 +1,61 @@ +`include "VX_define.vh" + +`ifndef SYNTHESIS +`include "float_dpi.vh" +`endif + +module VX_fp_div #( + parameter TAGW = 1, + parameter LANES = 1 +) ( + input wire clk, + input wire reset, + + output wire ready_in, + input wire valid_in, + + input wire [TAGW-1:0] tag_in, + + input wire [LANES-1:0][31:0] dataa, + input wire [LANES-1:0][31:0] datab, + output wire [LANES-1:0][31:0] result, + + output wire [TAGW-1:0] tag_out, + + input wire ready_out, + output wire valid_out +); + wire stall = ~ready_out && valid_out; + wire enable = ~stall; + + for (genvar i = 0; i < LANES; i++) begin + `ifdef QUARTUS + acl_fdiv fdiv ( + .clk (clk), + .areset (1'b0), + .en (enable), + .a (dataa[i]), + .b (datab[i]), + .q (result[i]) + ); + `else + always @(posedge clk) begin + dpi_fdiv(8*LANES+i, enable, dataa[i], datab[i], result[i]); + end + `endif + end + + VX_shift_register #( + .DATAW(TAGW + 1), + .DEPTH(`LATENCY_FDIV) + ) shift_reg ( + .clk(clk), + .reset(reset), + .enable(enable), + .in ({tag_in, valid_in}), + .out({tag_out, valid_out}) + ); + + assign ready_in = enable; + +endmodule diff --git a/hw/rtl/fp_cores/VX_fp_fpga.v b/hw/rtl/fp_cores/VX_fp_fpga.v new file mode 100644 index 00000000..bb4cb412 --- /dev/null +++ b/hw/rtl/fp_cores/VX_fp_fpga.v @@ -0,0 +1,244 @@ +`include "VX_define.vh" + +module VX_fp_fpga #( + parameter TAGW = 1 +) ( + input wire clk, + input wire reset, + + input wire valid_in, + output wire ready_in, + + input wire [TAGW-1:0] tag_in, + + input wire [`FPU_BITS-1:0] op_type, + input wire [`MOD_BITS-1:0] frm, + + input wire [`NUM_THREADS-1:0][31:0] dataa, + input wire [`NUM_THREADS-1:0][31:0] datab, + input wire [`NUM_THREADS-1:0][31:0] datac, + output wire [`NUM_THREADS-1:0][31:0] result, + + output wire has_fflags, + output fflags_t [`NUM_THREADS-1:0] fflags, + + output wire [TAGW-1:0] tag_out, + + input wire ready_out, + output wire valid_out +); + localparam NUM_FPC = 8; + localparam FPC_BITS = `LOG2UP(NUM_FPC); + + wire [NUM_FPC-1:0] per_core_ready_in; + wire [NUM_FPC-1:0][`NUM_THREADS-1:0][31:0] per_core_result; + wire [NUM_FPC-1:0][TAGW-1:0] per_core_tag_out; + reg [NUM_FPC-1:0] per_core_ready_out; + wire [NUM_FPC-1:0] per_core_valid_out; + + wire fpnew_has_fflags; + fflags_t [`NUM_THREADS-1:0] fpnew_fflags; + + reg [FPC_BITS-1:0] core_select; + reg do_sub, do_mul; + reg is_signed; + + always @(*) begin + core_select = 'x; + do_sub = 'x; + do_mul = 'x; + is_signed = 'x; + case (op_type) + `FPU_ADD: begin core_select = 1; do_mul = 0; do_sub = 0; end + `FPU_SUB: begin core_select = 1; do_mul = 0; do_sub = 1; end + `FPU_MUL: begin core_select = 1; do_mul = 1; do_sub = 0; end + `FPU_MADD: begin core_select = 2; do_sub = 0; end + `FPU_MSUB: begin core_select = 2; do_sub = 1; end + `FPU_NMADD: begin core_select = 3; do_sub = 0; end + `FPU_NMSUB: begin core_select = 3; do_sub = 1; end + `FPU_DIV: begin core_select = 4; end + `FPU_SQRT: begin core_select = 5; end + `FPU_CVTWS: begin core_select = 6; is_signed = 1; end + `FPU_CVTWUS: begin core_select = 6; is_signed = 0; end + `FPU_CVTSW: begin core_select = 7; is_signed = 1; end + `FPU_CVTSWU: begin core_select = 7; is_signed = 0; end + default: begin core_select = 0; end + endcase + end + + VX_fp_noncomp #( + .TAGW (TAGW), + .LANES(`NUM_THREADS) + ) fp_noncomp ( + .clk (clk), + .reset (reset), + .valid_in (valid_in && (core_select == 0)), + .ready_in (per_core_ready_in[0]), + .tag_in (tag_in), + .op_type (op_type), + .frm (frm), + .dataa (dataa), + .datab (datab), + .result (per_core_result[0]), + .has_fflags (fpnew_has_fflags), + .fflags (fpnew_fflags), + .tag_out (per_core_tag_out[0]), + .ready_out (per_core_ready_out[0]), + .valid_out (per_core_valid_out[0]) + ); + + VX_fp_addmul #( + .TAGW (TAGW), + .LANES(`NUM_THREADS) + ) fp_addmul ( + .clk (clk), + .reset (reset), + .valid_in (valid_in && (core_select == 1)), + .ready_in (per_core_ready_in[1]), + .tag_in (tag_in), + .do_sub (do_sub), + .do_mul (do_mul), + .dataa (dataa), + .datab (datab), + .result (per_core_result[1]), + .tag_out (per_core_tag_out[1]), + .ready_out (per_core_ready_out[1]), + .valid_out (per_core_valid_out[1]) + ); + + VX_fp_madd #( + .TAGW (TAGW), + .LANES(`NUM_THREADS) + ) fp_madd ( + .clk (clk), + .reset (reset), + .valid_in (valid_in && (core_select == 2)), + .ready_in (per_core_ready_in[2]), + .tag_in (tag_in), + .do_sub (do_sub), + .dataa (dataa), + .datab (datab), + .datac (datac), + .result (per_core_result[2]), + .tag_out (per_core_tag_out[2]), + .ready_out (per_core_ready_out[2]), + .valid_out (per_core_valid_out[2]) + ); + + VX_fp_nmadd #( + .TAGW (TAGW), + .LANES(`NUM_THREADS) + ) fp_nmadd ( + .clk (clk), + .reset (reset), + .valid_in (valid_in && (core_select == 3)), + .ready_in (per_core_ready_in[3]), + .tag_in (tag_in), + .do_sub (do_sub), + .dataa (dataa), + .datab (datab), + .datac (datac), + .result (per_core_result[3]), + .tag_out (per_core_tag_out[3]), + .ready_out (per_core_ready_out[3]), + .valid_out (per_core_valid_out[3]) + ); + + VX_fp_div #( + .TAGW (TAGW), + .LANES(`NUM_THREADS) + ) fp_div ( + .clk (clk), + .reset (reset), + .valid_in (valid_in && (core_select == 4)), + .ready_in (per_core_ready_in[4]), + .tag_in (tag_in), + .dataa (dataa), + .datab (datab), + .result (per_core_result[4]), + .tag_out (per_core_tag_out[4]), + .ready_out (per_core_ready_out[4]), + .valid_out (per_core_valid_out[4]) + ); + + VX_fp_sqrt #( + .TAGW (TAGW), + .LANES(`NUM_THREADS) + ) fp_sqrt ( + .clk (clk), + .reset (reset), + .valid_in (valid_in && (core_select == 5)), + .ready_in (per_core_ready_in[5]), + .tag_in (tag_in), + .dataa (dataa), + .result (per_core_result[5]), + .tag_out (per_core_tag_out[5]), + .ready_out (per_core_ready_out[5]), + .valid_out (per_core_valid_out[5]) + ); + + VX_fp_ftoi #( + .TAGW (TAGW), + .LANES(`NUM_THREADS) + ) fp_ftoi ( + .clk (clk), + .reset (reset), + .valid_in (valid_in && (core_select == 6)), + .ready_in (per_core_ready_in[6]), + .tag_in (tag_in), + .is_signed (is_signed), + .dataa (dataa), + .result (per_core_result[6]), + .tag_out (per_core_tag_out[6]), + .ready_out (per_core_ready_out[6]), + .valid_out (per_core_valid_out[6]) + ); + + VX_fp_itof #( + .TAGW (TAGW), + .LANES(`NUM_THREADS) + ) fp_itof ( + .clk (clk), + .reset (reset), + .valid_in (valid_in && (core_select == 7)), + .ready_in (per_core_ready_in[7]), + .tag_in (tag_in), + .is_signed (is_signed), + .dataa (dataa), + .result (per_core_result[7]), + .tag_out (per_core_tag_out[7]), + .ready_out (per_core_ready_out[7]), + .valid_out (per_core_valid_out[7]) + ); + + reg valid_out_n; + reg has_fflags_n; + reg [`NUM_THREADS-1:0][31:0] result_n; + reg [TAGW-1:0] tag_out_n; + + always @(*) begin + per_core_ready_out = 0; + valid_out_n = 0; + has_fflags_n = 'x; + result_n = 'x; + tag_out_n = 'x; + for (integer i = 0; i < NUM_FPC; i++) begin + if (per_core_valid_out[i]) begin + per_core_ready_out[i] = ready_out; + valid_out_n = 1; + has_fflags_n = fpnew_has_fflags && (i == 0); + result_n = per_core_result[i]; + tag_out_n = per_core_tag_out[i]; + break; + end + end + end + + assign ready_in = (& per_core_ready_in); + assign valid_out = valid_out_n; + assign has_fflags = has_fflags_n; + assign tag_out = tag_out_n; + assign result = result_n; + assign fflags = fpnew_fflags; + +endmodule \ No newline at end of file diff --git a/hw/rtl/fp_cores/VX_fp_ftoi.v b/hw/rtl/fp_cores/VX_fp_ftoi.v new file mode 100644 index 00000000..e9e3f720 --- /dev/null +++ b/hw/rtl/fp_cores/VX_fp_ftoi.v @@ -0,0 +1,78 @@ +`include "VX_define.vh" + +`ifndef SYNTHESIS +`include "float_dpi.vh" +`endif + +module VX_fp_ftoi #( + parameter TAGW = 1, + parameter LANES = 1 +) ( + input wire clk, + input wire reset, + + output wire ready_in, + input wire valid_in, + + input wire [TAGW-1:0] tag_in, + + input wire is_signed, + + input wire [LANES-1:0][31:0] dataa, + output wire [LANES-1:0][31:0] result, + + output wire [TAGW-1:0] tag_out, + + input wire ready_out, + output wire valid_out +); + wire stall = ~ready_out && valid_out; + wire enable = ~stall; + + reg is_signed_r; + + for (genvar i = 0; i < LANES; i++) begin + + wire [31:0] result_s; + wire [31:0] result_u; + + `ifdef QUARTUS + acl_ftoi ftoi ( + .clk (clk), + .areset (1'b0), + .en (enable), + .a (dataa[i]), + .q (result_s) + ); + + acl_ftou ftou ( + .clk (clk), + .areset (1'b0), + .en (enable), + .a (dataa[i]), + .q (result_u) + ); + `else + always @(posedge clk) begin + dpi_ftoi(10*LANES+i, enable, dataa[i], result_s); + dpi_ftou(11*LANES+i, enable, dataa[i], result_u); + end + `endif + + assign result[i] = is_signed_r ? result_s : result_u; + end + + VX_shift_register #( + .DATAW(TAGW + 1 + 1), + .DEPTH(`LATENCY_FTOI) + ) shift_reg ( + .clk(clk), + .reset(reset), + .enable(enable), + .in ({tag_in, valid_in, is_signed}), + .out({tag_out, valid_out, is_signed_r}) + ); + + assign ready_in = enable; + +endmodule diff --git a/hw/rtl/fp_cores/VX_fp_itof.v b/hw/rtl/fp_cores/VX_fp_itof.v new file mode 100644 index 00000000..348bc673 --- /dev/null +++ b/hw/rtl/fp_cores/VX_fp_itof.v @@ -0,0 +1,78 @@ +`include "VX_define.vh" + +`ifndef SYNTHESIS +`include "float_dpi.vh" +`endif + +module VX_fp_itof #( + parameter TAGW = 1, + parameter LANES = 1 +) ( + input wire clk, + input wire reset, + + output wire ready_in, + input wire valid_in, + + input wire [TAGW-1:0] tag_in, + + input wire is_signed, + + input wire [LANES-1:0][31:0] dataa, + output wire [LANES-1:0][31:0] result, + + output wire [TAGW-1:0] tag_out, + + input wire ready_out, + output wire valid_out +); + wire stall = ~ready_out && valid_out; + wire enable = ~stall; + + reg is_signed_r; + + for (genvar i = 0; i < LANES; i++) begin + + wire [31:0] result_s; + wire [31:0] result_u; + + `ifdef QUARTUS + acl_itof itof ( + .clk (clk), + .areset (1'b0), + .en (enable), + .a (dataa[i]), + .q (result_s) + ); + + acl_utof utof ( + .clk (clk), + .areset (1'b0), + .en (enable), + .a (dataa[i]), + .q (result_u) + ); + `else + always @(posedge clk) begin + dpi_itof(12*LANES+i, enable, dataa[i], result_s); + dpi_utof(13*LANES+i, enable, dataa[i], result_u); + end + `endif + + assign result[i] = is_signed_r ? result_s : result_u; + end + + VX_shift_register #( + .DATAW(TAGW + 1 + 1), + .DEPTH(`LATENCY_ITOF) + ) shift_reg ( + .clk(clk), + .reset(reset), + .enable(enable), + .in ({tag_in, valid_in, is_signed}), + .out({tag_out, valid_out, is_signed_r}) + ); + + assign ready_in = enable; + +endmodule diff --git a/hw/rtl/fp_cores/VX_fp_madd.v b/hw/rtl/fp_cores/VX_fp_madd.v new file mode 100644 index 00000000..5b589dd2 --- /dev/null +++ b/hw/rtl/fp_cores/VX_fp_madd.v @@ -0,0 +1,145 @@ +`include "VX_define.vh" + +`ifndef SYNTHESIS +`include "float_dpi.vh" +`endif + +module VX_fp_madd #( + parameter TAGW = 1, + parameter LANES = 1 +) ( + input wire clk, + input wire reset, + + output wire ready_in, + input wire valid_in, + + input wire [TAGW-1:0] tag_in, + + input wire do_sub, + + input wire [LANES-1:0][31:0] dataa, + input wire [LANES-1:0][31:0] datab, + input wire [LANES-1:0][31:0] datac, + output wire [LANES-1:0][31:0] result, + + output wire [TAGW-1:0] tag_out, + + input wire ready_out, + output wire valid_out +); + + wire stall = ~ready_out && valid_out; + wire enable = ~stall; + + reg do_sub_r; + + for (genvar i = 0; i < LANES; i++) begin + + wire [31:0] result_madd; + wire [31:0] result_msub; + + `ifdef QUARTUS + twentynm_fp_mac mac_fp_madd ( + // inputs + .accumulate(), + .chainin_overflow(), + .chainin_invalid(), + .chainin_underflow(), + .chainin_inexact(), + .ax(datac[i]), + .ay(datab[i]), + .az(dataa[i]), + .clk({2'b00,clk}), + .ena({2'b11,enable}), + .aclr(2'b00), + .chainin(), + // outputs + .overflow(), + .invalid(), + .underflow(), + .inexact(), + .chainout_overflow(), + .chainout_invalid(), + .chainout_underflow(), + .chainout_inexact(), + .resulta(result_madd), + .chainout() + ); + defparam mac_fp_madd.operation_mode = "sp_mult_add"; + defparam mac_fp_madd.use_chainin = "false"; + defparam mac_fp_madd.adder_subtract = "false"; + defparam mac_fp_madd.ax_clock = "0"; + defparam mac_fp_madd.ay_clock = "0"; + defparam mac_fp_madd.az_clock = "0"; + defparam mac_fp_madd.output_clock = "0"; + defparam mac_fp_madd.accumulate_clock = "none"; + defparam mac_fp_madd.ax_chainin_pl_clock = "0"; + defparam mac_fp_madd.accum_pipeline_clock = "none"; + defparam mac_fp_madd.mult_pipeline_clock = "0"; + defparam mac_fp_madd.adder_input_clock = "0"; + defparam mac_fp_madd.accum_adder_clock = "none"; + + twentynm_fp_mac mac_fp_msub ( + // inputs + .accumulate(), + .chainin_overflow(), + .chainin_invalid(), + .chainin_underflow(), + .chainin_inexact(), + .ax(datac[i]), + .ay(datab[i]), + .az(dataa[i]), + .clk({2'b00,clk}), + .ena({2'b11,enable}), + .aclr(2'b00), + .chainin(), + // outputs + .overflow(), + .invalid(), + .underflow(), + .inexact(), + .chainout_overflow(), + .chainout_invalid(), + .chainout_underflow(), + .chainout_inexact(), + .resulta(result_msub), + .chainout() + ); + defparam mac_fp_msub.operation_mode = "sp_mult_add"; + defparam mac_fp_msub.use_chainin = "false"; + defparam mac_fp_msub.adder_subtract = "true"; + defparam mac_fp_msub.ax_clock = "0"; + defparam mac_fp_msub.ay_clock = "0"; + defparam mac_fp_msub.az_clock = "0"; + defparam mac_fp_msub.output_clock = "0"; + defparam mac_fp_msub.accumulate_clock = "none"; + defparam mac_fp_msub.ax_chainin_pl_clock = "0"; + defparam mac_fp_msub.accum_pipeline_clock = "none"; + defparam mac_fp_msub.mult_pipeline_clock = "0"; + defparam mac_fp_msub.adder_input_clock = "0"; + defparam mac_fp_msub.accum_adder_clock = "none"; + `else + always @(posedge clk) begin + dpi_fmadd(3*LANES+i, enable, dataa[i], datab[i], datac[i], result_madd); + dpi_fmsub(4*LANES+i, enable, dataa[i], datab[i], datac[i], result_msub); + end + `endif + + assign result[i] = do_sub_r ? result_msub : result_madd; + end + + VX_shift_register #( + .DATAW(TAGW + 1 + 1), + .DEPTH(`LATENCY_FMADD) + ) shift_reg ( + .clk(clk), + .reset(reset), + .enable(enable), + .in({tag_in, valid_in, do_sub}), + .out({tag_out, valid_out, do_sub_r}) + ); + + assign ready_in = enable; + +endmodule diff --git a/hw/rtl/fp_cores/VX_fp_nmadd.v b/hw/rtl/fp_cores/VX_fp_nmadd.v new file mode 100644 index 00000000..95350bc2 --- /dev/null +++ b/hw/rtl/fp_cores/VX_fp_nmadd.v @@ -0,0 +1,197 @@ +`include "VX_define.vh" + +`ifndef SYNTHESIS +`include "float_dpi.vh" +`endif + +module VX_fp_nmadd #( + parameter TAGW = 1, + parameter LANES = 1 +) ( + input wire clk, + input wire reset, + + output wire ready_in, + input wire valid_in, + + input wire [TAGW-1:0] tag_in, + + input wire do_sub, + + input wire [LANES-1:0][31:0] dataa, + input wire [LANES-1:0][31:0] datab, + input wire [LANES-1:0][31:0] datac, + output wire [LANES-1:0][31:0] result, + + output wire [TAGW-1:0] tag_out, + + input wire ready_out, + output wire valid_out +); + + wire stall = ~ready_out && valid_out; + wire enable = ~stall; + + reg do_sub_r; + + for (genvar i = 0; i < LANES; i++) begin + + wire [31:0] result_madd; + wire [31:0] result_msub; + + wire [31:0] result_st0 = do_sub_r ? result_msub : result_madd; + + `ifdef QUARTUS + twentynm_fp_mac mac_fp_madd ( + // inputs + .accumulate(), + .chainin_overflow(), + .chainin_invalid(), + .chainin_underflow(), + .chainin_inexact(), + .ax(datac[i]), + .ay(datab[i]), + .az(dataa[i]), + .clk({2'b00,clk}), + .ena({2'b11,enable}), + .aclr(2'b00), + .chainin(), + // outputs + .overflow(), + .invalid(), + .underflow(), + .inexact(), + .chainout_overflow(), + .chainout_invalid(), + .chainout_underflow(), + .chainout_inexact(), + .resulta(result_madd), + .chainout() + ); + defparam mac_fp_madd.operation_mode = "sp_mult_add"; + defparam mac_fp_madd.use_chainin = "false"; + defparam mac_fp_madd.adder_subtract = "false"; + defparam mac_fp_madd.ax_clock = "0"; + defparam mac_fp_madd.ay_clock = "0"; + defparam mac_fp_madd.az_clock = "0"; + defparam mac_fp_madd.output_clock = "0"; + defparam mac_fp_madd.accumulate_clock = "none"; + defparam mac_fp_madd.ax_chainin_pl_clock = "0"; + defparam mac_fp_madd.accum_pipeline_clock = "none"; + defparam mac_fp_madd.mult_pipeline_clock = "0"; + defparam mac_fp_madd.adder_input_clock = "0"; + defparam mac_fp_madd.accum_adder_clock = "none"; + + twentynm_fp_mac mac_fp_msub ( + // inputs + .accumulate(), + .chainin_overflow(), + .chainin_invalid(), + .chainin_underflow(), + .chainin_inexact(), + .ax(datac[i]), + .ay(datab[i]), + .az(dataa[i]), + .clk({2'b00,clk}), + .ena({2'b11,enable0}), + .aclr(2'b00), + .chainin(), + // outputs + .overflow(), + .invalid(), + .underflow(), + .inexact(), + .chainout_overflow(), + .chainout_invalid(), + .chainout_underflow(), + .chainout_inexact(), + .resulta(result_msub), + .chainout() + ); + defparam mac_fp_msub.operation_mode = "sp_mult_add"; + defparam mac_fp_msub.use_chainin = "false"; + defparam mac_fp_msub.adder_subtract = "true"; + defparam mac_fp_msub.ax_clock = "0"; + defparam mac_fp_msub.ay_clock = "0"; + defparam mac_fp_msub.az_clock = "0"; + defparam mac_fp_msub.output_clock = "0"; + defparam mac_fp_msub.accumulate_clock = "none"; + defparam mac_fp_msub.ax_chainin_pl_clock = "0"; + defparam mac_fp_msub.accum_pipeline_clock = "none"; + defparam mac_fp_msub.mult_pipeline_clock = "0"; + defparam mac_fp_msub.adder_input_clock = "0"; + defparam mac_fp_msub.accum_adder_clock = "none"; + + twentynm_fp_mac mac_fp_neg ( + // inputs + .accumulate(), + .chainin_overflow(), + .chainin_invalid(), + .chainin_underflow(), + .chainin_inexact(), + .ax(32'h0), + .ay(result_st0), + .az(), + .clk({2'b00,clk}), + .ena({2'b11,enable1}), + .aclr(2'b00), + .chainin(), + // outputs + .overflow(), + .invalid(), + .underflow(), + .inexact(), + .chainout_overflow(), + .chainout_invalid(), + .chainout_underflow(), + .chainout_inexact(), + .resulta(result[i]), + .chainout() + ); + defparam mac_fp_neg.operation_mode = "sp_add"; + defparam mac_fp_neg.use_chainin = "false"; + defparam mac_fp_neg.adder_subtract = "true"; + defparam mac_fp_neg.ax_clock = "0"; + defparam mac_fp_neg.ay_clock = "0"; + defparam mac_fp_neg.az_clock = "none"; + defparam mac_fp_neg.output_clock = "0"; + defparam mac_fp_neg.accumulate_clock = "none"; + defparam mac_fp_neg.ax_chainin_pl_clock = "none"; + defparam mac_fp_neg.accum_pipeline_clock = "none"; + defparam mac_fp_neg.mult_pipeline_clock = "none"; + defparam mac_fp_neg.adder_input_clock = "0"; + defparam mac_fp_neg.accum_adder_clock = "none"; + `else + always @(posedge clk) begin + dpi_fmadd(5*LANES+i, enable, dataa[i], datab[i], datac[i], result_madd); + dpi_fmsub(6*LANES+i, enable, dataa[i], datab[i], datac[i], result_msub); + dpi_fsub(7*LANES+i, enable, 32'b0, result_st0, result[i]); + end + `endif + end + + VX_shift_register #( + .DATAW(1), + .DEPTH(`LATENCY_FMADD) + ) shift_reg0 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in({do_sub}), + .out({do_sub_r}) + ); + + VX_shift_register #( + .DATAW(TAGW + 1), + .DEPTH(`LATENCY_FMADD + `LATENCY_FADDMUL) + ) shift_reg1 ( + .clk(clk), + .reset(reset), + .enable(enable), + .in({tag_in, valid_in}), + .out({tag_out, valid_out}) + ); + + assign ready_in = enable; + +endmodule \ No newline at end of file diff --git a/hw/rtl/fp_cores/VX_fp_noncomp.v b/hw/rtl/fp_cores/VX_fp_noncomp.v new file mode 100644 index 00000000..ba11dd67 --- /dev/null +++ b/hw/rtl/fp_cores/VX_fp_noncomp.v @@ -0,0 +1,263 @@ +`include "VX_define.vh" + +module VX_fp_noncomp #( + parameter TAGW = 1, + parameter LANES = 1 +) ( + input wire clk, + input wire reset, + + output wire ready_in, + input wire valid_in, + + input wire [TAGW-1:0] tag_in, + + input wire [`FPU_BITS-1:0] op_type, + input wire [`FRM_BITS-1:0] frm, + + input wire [LANES-1:0][31:0] dataa, + input wire [LANES-1:0][31:0] datab, + output wire [LANES-1:0][31:0] result, + + output wire has_fflags, + output fflags_t [LANES-1:0] fflags, + + output wire [TAGW-1:0] tag_out, + + input wire ready_out, + output wire valid_out +); + localparam NEG_INF = 32'h00000001, + NEG_NORM = 32'h00000002, + NEG_SUBNORM = 32'h00000004, + NEG_ZERO = 32'h00000008, + POS_ZERO = 32'h00000010, + POS_SUBNORM = 32'h00000020, + POS_NORM = 32'h00000040, + POS_INF = 32'h00000080, + SIG_NAN = 32'h00000100, + QUT_NAN = 32'h00000200; + + reg [`FPU_BITS-1:0] op_type_r; + reg [`FRM_BITS-1:0] frm_r; + + reg [LANES-1:0][31:0] dataa_r; + reg [LANES-1:0][31:0] datab_r; + + reg [LANES-1:0] a_sign, b_sign; + reg [LANES-1:0][7:0] a_exponent; + reg [LANES-1:0][22:0] a_mantissa; + fp_type_t [LANES-1:0] a_type, b_type; + reg [LANES-1:0] a_smaller, ab_equal; + + reg [LANES-1:0][31:0] fclass_mask; // generate a 10-bit mask for integer reg + reg [LANES-1:0][31:0] fminmax_res; // result of fmin/fmax + reg [LANES-1:0][31:0] fsgnj_res; // result of sign injection + reg [LANES-1:0][31:0] fcmp_res; // result of comparison + reg [LANES-1:0][ 4:0] fcmp_excp; // exception of comparison + + wire stall = ~ready_out && valid_out; + + // Setup + for (genvar i = 0; i < LANES; i++) begin + wire tmp_a_sign = dataa[i][31]; + wire [7:0] tmp_a_exponent = dataa[i][30:23]; + wire [22:0] tmp_a_mantissa = dataa[i][22:0]; + + wire tmp_b_sign = datab[i][31]; + wire [7:0] tmp_b_exponent = datab[i][30:23]; + wire [22:0] tmp_b_mantissa = datab[i][22:0]; + + fp_type_t tmp_a_type, tmp_b_type; + + VX_fp_type fp_type_a ( + .exponent(tmp_a_exponent), + .mantissa(tmp_a_mantissa), + .o_type(tmp_a_type) + ); + + VX_fp_type fp_type_b ( + .exponent(tmp_b_exponent), + .mantissa(tmp_b_mantissa), + .o_type(tmp_b_type) + ); + + wire tmp_a_smaller = $signed(dataa[i]) < $signed(datab[i]); + wire tmp_ab_equal = (dataa[i] == datab[i]) | (tmp_a_type[4] & tmp_b_type[4]); + + VX_generic_register #( + .N(1 + 1 + 8 + 23 + $bits(fp_type_t) + $bits(fp_type_t) + 1 + 1) + ) fnc1_reg ( + .clk (clk), + .reset (reset), + .stall (stall), + .flush (1'b0), + .in ({tmp_a_sign, tmp_b_sign, tmp_a_exponent, tmp_a_mantissa, tmp_a_type, tmp_b_type, tmp_a_smaller, tmp_ab_equal}), + .out ({a_sign[i], b_sign[i], a_exponent[i], a_mantissa[i], a_type[i], b_type[i], a_smaller[i], ab_equal[i]}) + ); + end + + VX_generic_register #( + .N(`FPU_BITS + `FRM_BITS + (2 * `NUM_THREADS * 32)) + ) fnc2_reg ( + .clk (clk), + .reset (reset), + .stall (stall), + .flush (1'b0), + .in ({op_type, frm, dataa, datab}), + .out ({op_type_r, frm_r, dataa_r, datab_r}) + ); + + // FCLASS + for (genvar i = 0; i < LANES; i++) begin + always @(*) begin + if (a_type[i].is_normal) begin + fclass_mask[i] = a_sign[i] ? NEG_NORM : POS_NORM; + end + else if (a_type[i].is_inf) begin + fclass_mask[i] = a_sign[i] ? NEG_INF : POS_INF; + end + else if (a_type[i].is_zero) begin + fclass_mask[i] = a_sign[i] ? NEG_ZERO : POS_ZERO; + end + else if (a_type[i].is_subnormal) begin + fclass_mask[i] = a_sign[i] ? NEG_SUBNORM : POS_SUBNORM; + end + else if (a_type[i].is_nan) begin + fclass_mask[i] = {22'h0, a_type[i].is_quiet, a_type[i].is_signaling, 8'h0}; + end + else begin + fclass_mask[i] = QUT_NAN; + end + end + end + + // Min/Max + for (genvar i = 0; i < LANES; i++) begin + always @(*) begin + if (a_type[i].is_nan && b_type[i].is_nan) + fminmax_res[i] = {1'b0, 8'hff, 1'b1, 22'd0}; // canonical qNaN + else if (a_type[i].is_nan) + fminmax_res[i] = datab_r[i]; + else if (b_type[i].is_nan) + fminmax_res[i] = dataa_r[i]; + else begin + case (frm_r) // use LSB to distinguish MIN and MAX + 3: fminmax_res[i] = a_smaller[i] ? dataa_r[i] : datab_r[i]; + 4: fminmax_res[i] = a_smaller[i] ? datab_r[i] : dataa_r[i]; + default: fminmax_res[i] = 32'hdeadbeaf; // don't care value + endcase + end + end + end + + // Sign Injection + for (genvar i = 0; i < LANES; i++) begin + always @(*) begin + case (frm_r) + 0: fsgnj_res[i] = { b_sign[i], a_exponent[i], a_mantissa[i]}; + 1: fsgnj_res[i] = {~b_sign[i], a_exponent[i], a_mantissa[i]}; + 2: fsgnj_res[i] = { a_sign[i] ^ b_sign[i], a_exponent[i], a_mantissa[i]}; + default: fsgnj_res[i] = 32'hdeadbeaf; // don't care value + endcase + end + end + + // Comparison + for (genvar i = 0; i < LANES; i++) begin + always @(*) begin + case (frm_r) + `FRM_RNE: begin + if (a_type[i].is_nan || b_type[i].is_nan) begin + fcmp_res[i] = 32'h0; // result is 0 when either operand is NaN + fcmp_excp[i] = {1'b1, 4'h0}; // raise NV flag when either operand is NaN + end + else begin + fcmp_res[i] = {31'h0, (a_smaller[i] | ab_equal[i])}; + fcmp_excp[i] = 5'h0; + end + end + `FRM_RTZ: begin + if (a_type[i].is_nan || b_type[i].is_nan) begin + fcmp_res[i] = 32'h0; // result is 0 when either operand is NaN + fcmp_excp[i] = {1'b1, 4'h0}; // raise NV flag when either operand is NaN + end + else begin + fcmp_res[i] = {31'h0, (a_smaller[i] & ~ab_equal[i])}; + fcmp_excp[i] = 5'h0; + end + end + `FRM_RDN: begin + if (a_type[i].is_nan || b_type[i].is_nan) begin + fcmp_res[i] = 32'h0; // result is 0 when either operand is NaN + // ** FEQS only raise NV flag when either operand is signaling NaN + fcmp_excp[i] = {(a_type[i].is_signaling | b_type[i].is_signaling), 4'h0}; + end + else begin + fcmp_res[i] = {31'h0, ab_equal[i]}; + fcmp_excp[i] = 5'h0; + end + end + default: begin + fcmp_res[i] = 32'hdeadbeaf; // don't care value + fcmp_excp[i] = 5'h0; + end + endcase + end + end + + // outputs + + fflags_t [LANES-1:0] tmp_fflags; + reg [LANES-1:0][31:0] tmp_result; + + for (genvar i = 0; i < LANES; i++) begin + always @(*) begin + case (op_type_r) + `FPU_CLASS: begin + tmp_result[i] = fclass_mask[i]; + {tmp_fflags[i].NV, tmp_fflags[i].DZ, tmp_fflags[i].OF, tmp_fflags[i].UF, tmp_fflags[i].NX} = 5'h0; + end + `FPU_CMP: begin + tmp_result[i] = fcmp_res[i]; + {tmp_fflags[i].NV, tmp_fflags[i].DZ, tmp_fflags[i].OF, tmp_fflags[i].UF, tmp_fflags[i].NX} = fcmp_excp[i]; + end + //`FPU_MISC: + default: begin + case (frm) + 0,1,2: begin + tmp_result[i] = fsgnj_res[i]; + {tmp_fflags[i].NV, tmp_fflags[i].DZ, tmp_fflags[i].OF, tmp_fflags[i].UF, tmp_fflags[i].NX} = 5'h0; + end + 3,4: begin + tmp_result[i] = fminmax_res[i]; + {tmp_fflags[i].NV, tmp_fflags[i].DZ, tmp_fflags[i].OF, tmp_fflags[i].UF, tmp_fflags[i].NX} = {a_type[i][0] | b_type[i][0], 4'h0}; + end + //5,6,7: + default: begin + tmp_result[i] = dataa[i]; + {tmp_fflags[i].NV, tmp_fflags[i].DZ, tmp_fflags[i].OF, tmp_fflags[i].UF, tmp_fflags[i].NX} = 5'h0; + end + endcase + end + endcase + end + end + + wire tmp_has_fflags = ((op_type_r == `FPU_MISC) && (frm == 3 || frm == 4)) // MIN/MAX + || (op_type_r == `FPU_CMP); // CMP + + VX_generic_register #( + .N(1 + TAGW + (LANES * 32) + 1 + (LANES * `FFG_BITS)) + ) nc_reg ( + .clk (clk), + .reset (reset), + .stall (stall), + .flush (1'b0), + .in ({valid_in, tag_in, tmp_result, tmp_has_fflags, tmp_fflags}), + .out ({valid_out, tag_out, result, has_fflags, fflags}) + ); + + assign ready_in = ~stall; + +endmodule \ No newline at end of file diff --git a/hw/rtl/fp_cores/VX_fp_sqrt.v b/hw/rtl/fp_cores/VX_fp_sqrt.v new file mode 100644 index 00000000..780fa041 --- /dev/null +++ b/hw/rtl/fp_cores/VX_fp_sqrt.v @@ -0,0 +1,59 @@ +`include "VX_define.vh" + +`ifndef SYNTHESIS +`include "float_dpi.vh" +`endif + +module VX_fp_sqrt #( + parameter TAGW = 1, + parameter LANES = 1 +) ( + input wire clk, + input wire reset, + + output wire ready_in, + input wire valid_in, + + input wire [TAGW-1:0] tag_in, + + input wire [LANES-1:0][31:0] dataa, + output wire [LANES-1:0][31:0] result, + + output wire [TAGW-1:0] tag_out, + + input wire ready_out, + output wire valid_out +); + wire stall = ~ready_out && valid_out; + wire enable = ~stall; + + for (genvar i = 0; i < LANES; i++) begin + `ifdef QUARTUS + acl_fsqrt fsqrt ( + .clk (clk), + .areset (1'b0), + .en (enable), + .a (dataa[i]), + .q (result[i]) + ); + `else + always @(posedge clk) begin + dpi_fsqrt(9*LANES+i, enable, dataa[i], result[i]); + end + `endif + end + + VX_shift_register #( + .DATAW(TAGW + 1), + .DEPTH(`LATENCY_FSQRT) + ) shift_reg ( + .clk(clk), + .reset(reset), + .enable(enable), + .in ({tag_in, valid_in}), + .out({tag_out, valid_out}) + ); + + assign ready_in = enable; + +endmodule diff --git a/hw/rtl/fp_cores/VX_fp_type.v b/hw/rtl/fp_cores/VX_fp_type.v new file mode 100644 index 00000000..f94e286e --- /dev/null +++ b/hw/rtl/fp_cores/VX_fp_type.v @@ -0,0 +1,27 @@ + +`include "VX_define.vh" + +module VX_fp_type ( + // inputs + input [7:0] exponent, + input [22:0] mantissa, + // outputs + output fp_type_t o_type +); + wire is_normal = (exponent != 8'd0) && (exponent != 8'hff); + wire is_zero = (exponent == 8'd0) && (mantissa == 23'd0); + wire is_subnormal = (exponent == 8'd0) && !is_zero; + wire is_inf = (exponent == 8'hff) && (mantissa == 23'd0); + wire is_nan = (exponent == 8'hff) && (mantissa != 23'd0); + wire is_signaling = is_nan && (mantissa[22] == 1'b0); + wire is_quiet = is_nan && !is_signaling; + + assign o_type.is_normal = is_normal; + assign o_type.is_zero = is_zero; + assign o_type.is_subnormal = is_subnormal; + assign o_type.is_inf = is_inf; + assign o_type.is_nan = is_nan; + assign o_type.is_signaling = is_signaling; + assign o_type.is_quiet = is_quiet; + +endmodule \ No newline at end of file diff --git a/hw/rtl/fp_cores/VX_fpnew.v b/hw/rtl/fp_cores/VX_fpnew.v new file mode 100644 index 00000000..b575759b --- /dev/null +++ b/hw/rtl/fp_cores/VX_fpnew.v @@ -0,0 +1,209 @@ +`include "VX_define.vh" +`include "fpnew_pkg.sv" +`include "defs_div_sqrt_mvp.sv" + +module VX_fpnew #( + parameter TAGW = 1, + parameter FMULADD = 1, + parameter FDIVSQRT = 1, + parameter FNONCOMP = 1, + parameter FCONV = 1 +) ( + input wire clk, + input wire reset, + + input wire valid_in, + output wire ready_in, + + input wire [TAGW-1:0] tag_in, + + input wire [`FPU_BITS-1:0] op_type, + input wire [`MOD_BITS-1:0] frm, + + input wire [`NUM_THREADS-1:0][31:0] dataa, + input wire [`NUM_THREADS-1:0][31:0] datab, + input wire [`NUM_THREADS-1:0][31:0] datac, + output wire [`NUM_THREADS-1:0][31:0] result, + + output wire has_fflags, + output fflags_t [`NUM_THREADS-1:0] fflags, + + output wire [TAGW-1:0] tag_out, + + input wire ready_out, + output wire valid_out +); + localparam UNIT_FMULADD = FMULADD ? fpnew_pkg::PARALLEL : fpnew_pkg::DISABLED; + localparam UNIT_FDIVSQRT = FDIVSQRT ? fpnew_pkg::MERGED : fpnew_pkg::DISABLED; + localparam UNIT_FNONCOMP = FNONCOMP ? fpnew_pkg::PARALLEL : fpnew_pkg::DISABLED; + localparam UNIT_FCONV = FCONV ? fpnew_pkg::MERGED : fpnew_pkg::DISABLED; + + localparam FOP_BITS = fpnew_pkg::OP_BITS; + localparam FMTF_BITS = $clog2(fpnew_pkg::NUM_FP_FORMATS); + localparam FMTI_BITS = $clog2(fpnew_pkg::NUM_INT_FORMATS); + + localparam FPU_DPATHW = 32'd32; + + localparam fpnew_pkg::fpu_features_t FPU_FEATURES = '{ + Width: FPU_DPATHW, + EnableVectors: 1'b0, + EnableNanBox: 1'b1, + FpFmtMask: 5'b10000, + IntFmtMask: 4'b0010 + }; + + localparam fpnew_pkg::fpu_implementation_t FPU_IMPLEMENTATION = '{ + PipeRegs:'{'{`LATENCY_FADDMUL, 0, 0, 0, 0}, // ADDMUL + '{default: `LATENCY_FDIVSQRT}, // DIVSQRT + '{default: `LATENCY_FNONCOMP}, // NONCOMP + '{default: `LATENCY_FCONV}}, // CONV + UnitTypes:'{'{default: UNIT_FMULADD}, // ADDMUL + '{default: UNIT_FDIVSQRT}, // DIVSQRT + '{default: UNIT_FNONCOMP}, // NONCOMP + '{default: UNIT_FCONV}}, // CONV + PipeConfig: fpnew_pkg::DISTRIBUTED + }; + + wire fpu_ready_in, fpu_valid_in; + wire fpu_ready_out, fpu_valid_out; + + reg [TAGW-1:0] fpu_tag_in, fpu_tag_out; + + reg [2:0][`NUM_THREADS-1:0][31:0] fpu_operands; + + wire [FMTF_BITS-1:0] fpu_src_fmt = fpnew_pkg::FP32; + wire [FMTF_BITS-1:0] fpu_dst_fmt = fpnew_pkg::FP32; + wire [FMTI_BITS-1:0] fpu_int_fmt = fpnew_pkg::INT32; + + wire [`NUM_THREADS-1:0][31:0] fpu_result; + fpnew_pkg::status_t [0:`NUM_THREADS-1] fpu_status; + + reg [FOP_BITS-1:0] fpu_op; + reg [`FRM_BITS-1:0] fpu_rnd; + reg fpu_op_mod; + reg fpu_has_fflags, fpu_has_fflags_out; + + always @(*) begin + fpu_op = fpnew_pkg::SGNJ; + fpu_rnd = frm; + fpu_op_mod = 0; + fpu_has_fflags = 1; + fpu_operands[0] = dataa; + fpu_operands[1] = datab; + fpu_operands[2] = datac; + case (op_type) + `FPU_ADD: begin + fpu_op = fpnew_pkg::ADD; + fpu_operands[1] = dataa; + fpu_operands[2] = datab; + end + `FPU_SUB: begin + fpu_op = fpnew_pkg::ADD; + fpu_operands[1] = dataa; + fpu_operands[2] = datab; + fpu_op_mod = 1; + end + `FPU_MUL: begin fpu_op = fpnew_pkg::MUL; end + `FPU_DIV: begin fpu_op = fpnew_pkg::DIV; end + `FPU_SQRT: begin fpu_op = fpnew_pkg::SQRT; end + `FPU_MADD: begin fpu_op = fpnew_pkg::FMADD; end + `FPU_MSUB: begin fpu_op = fpnew_pkg::FMADD; fpu_op_mod = 1; end + `FPU_NMSUB: begin fpu_op = fpnew_pkg::FNMSUB; end + `FPU_NMADD: begin fpu_op = fpnew_pkg::FNMSUB; fpu_op_mod = 1; end + `FPU_CVTWS: begin fpu_op = fpnew_pkg::F2I; end + `FPU_CVTWUS:begin fpu_op = fpnew_pkg::F2I; fpu_op_mod = 1; end + `FPU_CVTSW: begin fpu_op = fpnew_pkg::I2F; end + `FPU_CVTSWU:begin fpu_op = fpnew_pkg::I2F; fpu_op_mod = 1; end + `FPU_CLASS: begin fpu_op = fpnew_pkg::CLASSIFY; fpu_has_fflags = 0; end + `FPU_CMP: begin fpu_op = fpnew_pkg::CMP; end + `FPU_MISC: begin + case (frm) + 0: begin fpu_op = fpnew_pkg::SGNJ; fpu_rnd = `FRM_RNE; fpu_has_fflags = 0; end + 1: begin fpu_op = fpnew_pkg::SGNJ; fpu_rnd = `FRM_RTZ; fpu_has_fflags = 0; end + 2: begin fpu_op = fpnew_pkg::SGNJ; fpu_rnd = `FRM_RDN; fpu_has_fflags = 0; end + 3: begin fpu_op = fpnew_pkg::MINMAX; fpu_rnd = `FRM_RNE; end + 4: begin fpu_op = fpnew_pkg::MINMAX; fpu_rnd = `FRM_RTZ; end + default: begin fpu_op = fpnew_pkg::SGNJ; fpu_rnd = `FRM_RUP; fpu_has_fflags = 0; end + endcase + end + default:; + endcase + end + +`DISABLE_TRACING + + for (genvar i = 0; i < `NUM_THREADS; i++) begin + if (0 == i) begin + fpnew_top #( + .Features (FPU_FEATURES), + .Implementation (FPU_IMPLEMENTATION), + .TagType (logic[TAGW+1+1-1:0]) + ) fpnew_core ( + .clk_i (clk), + .rst_ni (1'b1), + .operands_i ({fpu_operands[2][0], fpu_operands[1][0], fpu_operands[0][0]}), + .rnd_mode_i (fpnew_pkg::roundmode_e'(fpu_rnd)), + .op_i (fpnew_pkg::operation_e'(fpu_op)), + .op_mod_i (fpu_op_mod), + .src_fmt_i (fpnew_pkg::fp_format_e'(fpu_src_fmt)), + .dst_fmt_i (fpnew_pkg::fp_format_e'(fpu_dst_fmt)), + .int_fmt_i (fpnew_pkg::int_format_e'(fpu_int_fmt)), + .vectorial_op_i (1'b0), + .tag_i ({fpu_tag_in, fpu_has_fflags}), + .in_valid_i (fpu_valid_in), + .in_ready_o (fpu_ready_in), + .flush_i (reset), + .result_o (fpu_result[0]), + .status_o (fpu_status[0]), + .tag_o ({fpu_tag_out, fpu_has_fflags_out}), + .out_valid_o (fpu_valid_out), + .out_ready_i (fpu_ready_out), + `UNUSED_PIN (busy_o) + ); + end else begin + fpnew_top #( + .Features (FPU_FEATURES), + .Implementation (FPU_IMPLEMENTATION), + .TagType (logic) + ) fpnew_core ( + .clk_i (clk), + .rst_ni (1'b1), + .operands_i ({fpu_operands[2][i], fpu_operands[1][i], fpu_operands[0][i]}), + .rnd_mode_i (fpnew_pkg::roundmode_e'(fpu_rnd)), + .op_i (fpnew_pkg::operation_e'(fpu_op)), + .op_mod_i (fpu_op_mod), + .src_fmt_i (fpnew_pkg::fp_format_e'(fpu_src_fmt)), + .dst_fmt_i (fpnew_pkg::fp_format_e'(fpu_dst_fmt)), + .int_fmt_i (fpnew_pkg::int_format_e'(fpu_int_fmt)), + .vectorial_op_i (1'b0), + .tag_i (1'b0), + .in_valid_i (fpu_valid_in), + `UNUSED_PIN (in_ready_o), + .flush_i (reset), + .result_o (fpu_result[i]), + .status_o (fpu_status[i]), + `UNUSED_PIN (tag_o), + `UNUSED_PIN (out_valid_o), + .out_ready_i (fpu_ready_out), + `UNUSED_PIN (busy_o) + ); + end + end + +`ENABLE_TRACING + + assign fpu_valid_in = valid_in; + assign ready_in = fpu_ready_in; + + assign fpu_tag_in = tag_in; + assign tag_out = fpu_tag_out; + + assign result = fpu_result; + + assign has_fflags = fpu_has_fflags_out; + assign fflags = fpu_status; + + assign valid_out = fpu_valid_out; + assign fpu_ready_out = ready_out; + +endmodule \ No newline at end of file diff --git a/hw/rtl/fp_cores/altera/acl_fdiv.sv b/hw/rtl/fp_cores/altera/acl_fdiv.sv new file mode 100644 index 00000000..c6c73008 --- /dev/null +++ b/hw/rtl/fp_cores/altera/acl_fdiv.sv @@ -0,0 +1,1592 @@ +// ------------------------------------------------------------------------- +// High Level Design Compiler for Intel(R) FPGAs Version 17.1 (Release Build #273) +// Quartus Prime development tool and MATLAB/Simulink Interface +// +// Legal Notice: Copyright 2017 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly +// subject to the terms and conditions of the Intel FPGA Software License +// Agreement, Intel MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for +// the sole purpose of programming logic devices manufactured by Intel +// and sold by Intel or its authorized distributors. Please refer to the +// applicable agreement for further details. +// --------------------------------------------------------------------------- + +// SystemVerilog created from acl_fdiv +// SystemVerilog created on Wed Sep 2 07:11:09 2020 + + +(* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007; -name MESSAGE_DISABLE 10958" *) +module acl_fdiv ( + input wire [31:0] a, + input wire [31:0] b, + input wire [0:0] en, + output wire [31:0] q, + input wire clk, + input wire areset + ); + + wire [0:0] GND_q; + wire [0:0] VCC_q; + wire [7:0] cstBiasM1_uid6_fpDivTest_q; + wire [7:0] expX_uid9_fpDivTest_b; + wire [22:0] fracX_uid10_fpDivTest_b; + wire [0:0] signX_uid11_fpDivTest_b; + wire [7:0] expY_uid12_fpDivTest_b; + wire [22:0] fracY_uid13_fpDivTest_b; + wire [0:0] signY_uid14_fpDivTest_b; + wire [22:0] paddingY_uid15_fpDivTest_q; + wire [23:0] updatedY_uid16_fpDivTest_q; + wire [23:0] fracYZero_uid15_fpDivTest_a; + wire [0:0] fracYZero_uid15_fpDivTest_qi; + reg [0:0] fracYZero_uid15_fpDivTest_q; + wire [7:0] cstAllOWE_uid18_fpDivTest_q; + wire [7:0] cstAllZWE_uid20_fpDivTest_q; + wire [0:0] excZ_x_uid23_fpDivTest_qi; + reg [0:0] excZ_x_uid23_fpDivTest_q; + wire [0:0] expXIsMax_uid24_fpDivTest_qi; + reg [0:0] expXIsMax_uid24_fpDivTest_q; + wire [0:0] fracXIsZero_uid25_fpDivTest_qi; + reg [0:0] fracXIsZero_uid25_fpDivTest_q; + wire [0:0] fracXIsNotZero_uid26_fpDivTest_q; + wire [0:0] excI_x_uid27_fpDivTest_q; + wire [0:0] excN_x_uid28_fpDivTest_q; + wire [0:0] invExpXIsMax_uid29_fpDivTest_q; + wire [0:0] InvExpXIsZero_uid30_fpDivTest_q; + wire [0:0] excR_x_uid31_fpDivTest_q; + wire [0:0] excZ_y_uid37_fpDivTest_qi; + reg [0:0] excZ_y_uid37_fpDivTest_q; + wire [0:0] expXIsMax_uid38_fpDivTest_qi; + reg [0:0] expXIsMax_uid38_fpDivTest_q; + wire [0:0] fracXIsZero_uid39_fpDivTest_qi; + reg [0:0] fracXIsZero_uid39_fpDivTest_q; + wire [0:0] fracXIsNotZero_uid40_fpDivTest_q; + wire [0:0] excI_y_uid41_fpDivTest_q; + wire [0:0] excN_y_uid42_fpDivTest_q; + wire [0:0] invExpXIsMax_uid43_fpDivTest_q; + wire [0:0] InvExpXIsZero_uid44_fpDivTest_q; + wire [0:0] excR_y_uid45_fpDivTest_q; + wire [0:0] signR_uid46_fpDivTest_qi; + reg [0:0] signR_uid46_fpDivTest_q; + wire [8:0] expXmY_uid47_fpDivTest_a; + wire [8:0] expXmY_uid47_fpDivTest_b; + logic [8:0] expXmY_uid47_fpDivTest_o; + wire [8:0] expXmY_uid47_fpDivTest_q; + wire [10:0] expR_uid48_fpDivTest_a; + wire [10:0] expR_uid48_fpDivTest_b; + logic [10:0] expR_uid48_fpDivTest_o; + wire [9:0] expR_uid48_fpDivTest_q; + wire [8:0] yAddr_uid51_fpDivTest_b; + wire [13:0] yPE_uid52_fpDivTest_b; + wire [0:0] fracYPostZ_uid56_fpDivTest_qi; + reg [0:0] fracYPostZ_uid56_fpDivTest_q; + wire [23:0] lOAdded_uid58_fpDivTest_q; + wire [1:0] oFracXSE_bottomExtension_uid61_fpDivTest_q; + wire [25:0] oFracXSE_mergedSignalTM_uid63_fpDivTest_q; + wire [0:0] divValPreNormTrunc_uid66_fpDivTest_s; + reg [25:0] divValPreNormTrunc_uid66_fpDivTest_q; + wire [0:0] norm_uid67_fpDivTest_b; + wire [24:0] divValPreNormHigh_uid68_fpDivTest_in; + wire [23:0] divValPreNormHigh_uid68_fpDivTest_b; + wire [23:0] divValPreNormLow_uid69_fpDivTest_in; + wire [23:0] divValPreNormLow_uid69_fpDivTest_b; + wire [0:0] normFracRnd_uid70_fpDivTest_s; + reg [23:0] normFracRnd_uid70_fpDivTest_q; + wire [33:0] expFracRnd_uid71_fpDivTest_q; + wire [24:0] rndOp_uid75_fpDivTest_q; + wire [35:0] expFracPostRnd_uid76_fpDivTest_a; + wire [35:0] expFracPostRnd_uid76_fpDivTest_b; + logic [35:0] expFracPostRnd_uid76_fpDivTest_o; + wire [34:0] expFracPostRnd_uid76_fpDivTest_q; + wire [23:0] fracRPreExc_uid78_fpDivTest_in; + wire [22:0] fracRPreExc_uid78_fpDivTest_b; + wire [31:0] excRPreExc_uid79_fpDivTest_in; + wire [7:0] excRPreExc_uid79_fpDivTest_b; + wire [10:0] expRExt_uid80_fpDivTest_b; + wire [12:0] expUdf_uid81_fpDivTest_a; + wire [12:0] expUdf_uid81_fpDivTest_b; + logic [12:0] expUdf_uid81_fpDivTest_o; + wire [0:0] expUdf_uid81_fpDivTest_n; + wire [12:0] expOvf_uid84_fpDivTest_a; + wire [12:0] expOvf_uid84_fpDivTest_b; + logic [12:0] expOvf_uid84_fpDivTest_o; + wire [0:0] expOvf_uid84_fpDivTest_n; + wire [0:0] zeroOverReg_uid85_fpDivTest_q; + wire [0:0] regOverRegWithUf_uid86_fpDivTest_q; + wire [0:0] xRegOrZero_uid87_fpDivTest_q; + wire [0:0] regOrZeroOverInf_uid88_fpDivTest_q; + wire [0:0] excRZero_uid89_fpDivTest_q; + wire [0:0] excXRYZ_uid90_fpDivTest_q; + wire [0:0] excXRYROvf_uid91_fpDivTest_q; + wire [0:0] excXIYZ_uid92_fpDivTest_q; + wire [0:0] excXIYR_uid93_fpDivTest_q; + wire [0:0] excRInf_uid94_fpDivTest_q; + wire [0:0] excXZYZ_uid95_fpDivTest_q; + wire [0:0] excXIYI_uid96_fpDivTest_q; + wire [0:0] excRNaN_uid97_fpDivTest_q; + wire [2:0] concExc_uid98_fpDivTest_q; + reg [1:0] excREnc_uid99_fpDivTest_q; + wire [22:0] oneFracRPostExc2_uid100_fpDivTest_q; + wire [1:0] fracRPostExc_uid103_fpDivTest_s; + reg [22:0] fracRPostExc_uid103_fpDivTest_q; + wire [1:0] expRPostExc_uid107_fpDivTest_s; + reg [7:0] expRPostExc_uid107_fpDivTest_q; + wire [0:0] invExcRNaN_uid108_fpDivTest_q; + wire [0:0] sRPostExc_uid109_fpDivTest_qi; + reg [0:0] sRPostExc_uid109_fpDivTest_q; + wire [31:0] divR_uid110_fpDivTest_q; + wire [11:0] yT1_uid124_invPolyEval_b; + wire [0:0] lowRangeB_uid126_invPolyEval_in; + wire [0:0] lowRangeB_uid126_invPolyEval_b; + wire [11:0] highBBits_uid127_invPolyEval_b; + wire [21:0] s1sumAHighB_uid128_invPolyEval_a; + wire [21:0] s1sumAHighB_uid128_invPolyEval_b; + logic [21:0] s1sumAHighB_uid128_invPolyEval_o; + wire [21:0] s1sumAHighB_uid128_invPolyEval_q; + wire [22:0] s1_uid129_invPolyEval_q; + wire [1:0] lowRangeB_uid132_invPolyEval_in; + wire [1:0] lowRangeB_uid132_invPolyEval_b; + wire [21:0] highBBits_uid133_invPolyEval_b; + wire [31:0] s2sumAHighB_uid134_invPolyEval_a; + wire [31:0] s2sumAHighB_uid134_invPolyEval_b; + logic [31:0] s2sumAHighB_uid134_invPolyEval_o; + wire [31:0] s2sumAHighB_uid134_invPolyEval_q; + wire [33:0] s2_uid135_invPolyEval_q; + wire [25:0] osig_uid138_prodDivPreNormProd_uid60_fpDivTest_b; + wire [12:0] osig_uid141_pT1_uid125_invPolyEval_b; + wire [23:0] osig_uid144_pT2_uid131_invPolyEval_b; + wire memoryC0_uid112_invTables_lutmem_reset0; + wire [30:0] memoryC0_uid112_invTables_lutmem_ia; + wire [8:0] memoryC0_uid112_invTables_lutmem_aa; + wire [8:0] memoryC0_uid112_invTables_lutmem_ab; + wire [30:0] memoryC0_uid112_invTables_lutmem_ir; + wire [30:0] memoryC0_uid112_invTables_lutmem_r; + wire memoryC1_uid115_invTables_lutmem_reset0; + wire [20:0] memoryC1_uid115_invTables_lutmem_ia; + wire [8:0] memoryC1_uid115_invTables_lutmem_aa; + wire [8:0] memoryC1_uid115_invTables_lutmem_ab; + wire [20:0] memoryC1_uid115_invTables_lutmem_ir; + wire [20:0] memoryC1_uid115_invTables_lutmem_r; + wire memoryC2_uid118_invTables_lutmem_reset0; + wire [11:0] memoryC2_uid118_invTables_lutmem_ia; + wire [8:0] memoryC2_uid118_invTables_lutmem_aa; + wire [8:0] memoryC2_uid118_invTables_lutmem_ab; + wire [11:0] memoryC2_uid118_invTables_lutmem_ir; + wire [11:0] memoryC2_uid118_invTables_lutmem_r; + wire prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_reset; + (* preserve, altera_attribute = "-name allow_synch_ctrl_usage off" *) reg [25:0] prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_a0 [0:0]; + (* preserve, altera_attribute = "-name allow_synch_ctrl_usage off" *) reg [25:0] prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_a1 [0:0]; + (* preserve, altera_attribute = "-name allow_synch_ctrl_usage off" *) reg [23:0] prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_c0 [0:0]; + (* preserve, altera_attribute = "-name allow_synch_ctrl_usage off" *) reg [23:0] prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_c1 [0:0]; + wire [49:0] prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_p [0:0]; + wire [49:0] prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_u [0:0]; + wire [49:0] prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_w [0:0]; + wire [49:0] prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_x [0:0]; + wire [49:0] prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_y [0:0]; + reg [49:0] prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_s [0:0]; + wire [49:0] prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_qq; + wire [49:0] prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_q; + wire prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_ena0; + wire prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_ena1; + wire prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_ena2; + wire prodXY_uid140_pT1_uid125_invPolyEval_cma_reset; + (* preserve, altera_attribute = "-name allow_synch_ctrl_usage off" *) reg [11:0] prodXY_uid140_pT1_uid125_invPolyEval_cma_a0 [0:0]; + (* preserve, altera_attribute = "-name allow_synch_ctrl_usage off" *) reg [11:0] prodXY_uid140_pT1_uid125_invPolyEval_cma_a1 [0:0]; + (* preserve, altera_attribute = "-name allow_synch_ctrl_usage off" *) reg signed [11:0] prodXY_uid140_pT1_uid125_invPolyEval_cma_c0 [0:0]; + (* preserve, altera_attribute = "-name allow_synch_ctrl_usage off" *) reg signed [11:0] prodXY_uid140_pT1_uid125_invPolyEval_cma_c1 [0:0]; + wire signed [12:0] prodXY_uid140_pT1_uid125_invPolyEval_cma_l [0:0]; + wire signed [24:0] prodXY_uid140_pT1_uid125_invPolyEval_cma_p [0:0]; + wire signed [24:0] prodXY_uid140_pT1_uid125_invPolyEval_cma_u [0:0]; + wire signed [24:0] prodXY_uid140_pT1_uid125_invPolyEval_cma_w [0:0]; + wire signed [24:0] prodXY_uid140_pT1_uid125_invPolyEval_cma_x [0:0]; + wire signed [24:0] prodXY_uid140_pT1_uid125_invPolyEval_cma_y [0:0]; + reg signed [24:0] prodXY_uid140_pT1_uid125_invPolyEval_cma_s [0:0]; + wire [23:0] prodXY_uid140_pT1_uid125_invPolyEval_cma_qq; + wire [23:0] prodXY_uid140_pT1_uid125_invPolyEval_cma_q; + wire prodXY_uid140_pT1_uid125_invPolyEval_cma_ena0; + wire prodXY_uid140_pT1_uid125_invPolyEval_cma_ena1; + wire prodXY_uid140_pT1_uid125_invPolyEval_cma_ena2; + wire prodXY_uid143_pT2_uid131_invPolyEval_cma_reset; + (* preserve, altera_attribute = "-name allow_synch_ctrl_usage off" *) reg [13:0] prodXY_uid143_pT2_uid131_invPolyEval_cma_a0 [0:0]; + (* preserve, altera_attribute = "-name allow_synch_ctrl_usage off" *) reg [13:0] prodXY_uid143_pT2_uid131_invPolyEval_cma_a1 [0:0]; + (* preserve, altera_attribute = "-name allow_synch_ctrl_usage off" *) reg signed [22:0] prodXY_uid143_pT2_uid131_invPolyEval_cma_c0 [0:0]; + (* preserve, altera_attribute = "-name allow_synch_ctrl_usage off" *) reg signed [22:0] prodXY_uid143_pT2_uid131_invPolyEval_cma_c1 [0:0]; + wire signed [14:0] prodXY_uid143_pT2_uid131_invPolyEval_cma_l [0:0]; + wire signed [37:0] prodXY_uid143_pT2_uid131_invPolyEval_cma_p [0:0]; + wire signed [37:0] prodXY_uid143_pT2_uid131_invPolyEval_cma_u [0:0]; + wire signed [37:0] prodXY_uid143_pT2_uid131_invPolyEval_cma_w [0:0]; + wire signed [37:0] prodXY_uid143_pT2_uid131_invPolyEval_cma_x [0:0]; + wire signed [37:0] prodXY_uid143_pT2_uid131_invPolyEval_cma_y [0:0]; + reg signed [37:0] prodXY_uid143_pT2_uid131_invPolyEval_cma_s [0:0]; + wire [36:0] prodXY_uid143_pT2_uid131_invPolyEval_cma_qq; + wire [36:0] prodXY_uid143_pT2_uid131_invPolyEval_cma_q; + wire prodXY_uid143_pT2_uid131_invPolyEval_cma_ena0; + wire prodXY_uid143_pT2_uid131_invPolyEval_cma_ena1; + wire prodXY_uid143_pT2_uid131_invPolyEval_cma_ena2; + wire [31:0] invY_uid54_fpDivTest_merged_bit_select_in; + wire [25:0] invY_uid54_fpDivTest_merged_bit_select_b; + wire [0:0] invY_uid54_fpDivTest_merged_bit_select_c; + reg [25:0] redist0_invY_uid54_fpDivTest_merged_bit_select_b_1_q; + reg [0:0] redist1_lowRangeB_uid126_invPolyEval_b_1_q; + reg [7:0] redist2_excRPreExc_uid79_fpDivTest_b_1_q; + reg [22:0] redist3_fracRPreExc_uid78_fpDivTest_b_1_q; + reg [23:0] redist4_lOAdded_uid58_fpDivTest_q_3_q; + reg [0:0] redist5_fracYPostZ_uid56_fpDivTest_q_4_q; + reg [13:0] redist6_yPE_uid52_fpDivTest_b_2_q; + reg [8:0] redist8_yAddr_uid51_fpDivTest_b_3_q; + reg [8:0] redist9_yAddr_uid51_fpDivTest_b_7_q; + reg [0:0] redist11_signR_uid46_fpDivTest_q_14_q; + reg [0:0] redist12_fracXIsZero_uid39_fpDivTest_q_14_q; + reg [0:0] redist13_expXIsMax_uid38_fpDivTest_q_14_q; + reg [0:0] redist14_excZ_y_uid37_fpDivTest_q_14_q; + reg [0:0] redist15_fracXIsZero_uid25_fpDivTest_q_4_q; + reg [0:0] redist16_expXIsMax_uid24_fpDivTest_q_14_q; + reg [0:0] redist17_excZ_x_uid23_fpDivTest_q_14_q; + reg [0:0] redist18_fracYZero_uid15_fpDivTest_q_9_q; + wire redist7_yPE_uid52_fpDivTest_b_6_mem_reset0; + wire [13:0] redist7_yPE_uid52_fpDivTest_b_6_mem_ia; + wire [1:0] redist7_yPE_uid52_fpDivTest_b_6_mem_aa; + wire [1:0] redist7_yPE_uid52_fpDivTest_b_6_mem_ab; + wire [13:0] redist7_yPE_uid52_fpDivTest_b_6_mem_iq; + wire [13:0] redist7_yPE_uid52_fpDivTest_b_6_mem_q; + wire [1:0] redist7_yPE_uid52_fpDivTest_b_6_rdcnt_q; + (* preserve *) reg [1:0] redist7_yPE_uid52_fpDivTest_b_6_rdcnt_i; + (* preserve *) reg redist7_yPE_uid52_fpDivTest_b_6_rdcnt_eq; + wire [0:0] redist7_yPE_uid52_fpDivTest_b_6_rdmux_s; + reg [1:0] redist7_yPE_uid52_fpDivTest_b_6_rdmux_q; + reg [1:0] redist7_yPE_uid52_fpDivTest_b_6_wraddr_q; + wire [1:0] redist7_yPE_uid52_fpDivTest_b_6_mem_last_q; + wire [0:0] redist7_yPE_uid52_fpDivTest_b_6_cmp_q; + reg [0:0] redist7_yPE_uid52_fpDivTest_b_6_cmpReg_q; + wire [0:0] redist7_yPE_uid52_fpDivTest_b_6_notEnable_q; + wire [0:0] redist7_yPE_uid52_fpDivTest_b_6_nor_q; + (* preserve_syn_only *) reg [0:0] redist7_yPE_uid52_fpDivTest_b_6_sticky_ena_q; + wire [0:0] redist7_yPE_uid52_fpDivTest_b_6_enaAnd_q; + reg [8:0] redist10_expXmY_uid47_fpDivTest_q_13_outputreg_q; + wire redist10_expXmY_uid47_fpDivTest_q_13_mem_reset0; + wire [8:0] redist10_expXmY_uid47_fpDivTest_q_13_mem_ia; + wire [3:0] redist10_expXmY_uid47_fpDivTest_q_13_mem_aa; + wire [3:0] redist10_expXmY_uid47_fpDivTest_q_13_mem_ab; + wire [8:0] redist10_expXmY_uid47_fpDivTest_q_13_mem_iq; + wire [8:0] redist10_expXmY_uid47_fpDivTest_q_13_mem_q; + wire [3:0] redist10_expXmY_uid47_fpDivTest_q_13_rdcnt_q; + (* preserve *) reg [3:0] redist10_expXmY_uid47_fpDivTest_q_13_rdcnt_i; + (* preserve *) reg redist10_expXmY_uid47_fpDivTest_q_13_rdcnt_eq; + wire [0:0] redist10_expXmY_uid47_fpDivTest_q_13_rdmux_s; + reg [3:0] redist10_expXmY_uid47_fpDivTest_q_13_rdmux_q; + reg [3:0] redist10_expXmY_uid47_fpDivTest_q_13_wraddr_q; + wire [4:0] redist10_expXmY_uid47_fpDivTest_q_13_mem_last_q; + wire [4:0] redist10_expXmY_uid47_fpDivTest_q_13_cmp_b; + wire [0:0] redist10_expXmY_uid47_fpDivTest_q_13_cmp_q; + reg [0:0] redist10_expXmY_uid47_fpDivTest_q_13_cmpReg_q; + wire [0:0] redist10_expXmY_uid47_fpDivTest_q_13_notEnable_q; + wire [0:0] redist10_expXmY_uid47_fpDivTest_q_13_nor_q; + (* preserve_syn_only *) reg [0:0] redist10_expXmY_uid47_fpDivTest_q_13_sticky_ena_q; + wire [0:0] redist10_expXmY_uid47_fpDivTest_q_13_enaAnd_q; + wire redist19_fracX_uid10_fpDivTest_b_10_mem_reset0; + wire [22:0] redist19_fracX_uid10_fpDivTest_b_10_mem_ia; + wire [3:0] redist19_fracX_uid10_fpDivTest_b_10_mem_aa; + wire [3:0] redist19_fracX_uid10_fpDivTest_b_10_mem_ab; + wire [22:0] redist19_fracX_uid10_fpDivTest_b_10_mem_iq; + wire [22:0] redist19_fracX_uid10_fpDivTest_b_10_mem_q; + wire [3:0] redist19_fracX_uid10_fpDivTest_b_10_rdcnt_q; + (* preserve *) reg [3:0] redist19_fracX_uid10_fpDivTest_b_10_rdcnt_i; + (* preserve *) reg redist19_fracX_uid10_fpDivTest_b_10_rdcnt_eq; + wire [0:0] redist19_fracX_uid10_fpDivTest_b_10_rdmux_s; + reg [3:0] redist19_fracX_uid10_fpDivTest_b_10_rdmux_q; + reg [3:0] redist19_fracX_uid10_fpDivTest_b_10_wraddr_q; + wire [3:0] redist19_fracX_uid10_fpDivTest_b_10_mem_last_q; + wire [0:0] redist19_fracX_uid10_fpDivTest_b_10_cmp_q; + reg [0:0] redist19_fracX_uid10_fpDivTest_b_10_cmpReg_q; + wire [0:0] redist19_fracX_uid10_fpDivTest_b_10_notEnable_q; + wire [0:0] redist19_fracX_uid10_fpDivTest_b_10_nor_q; + (* preserve_syn_only *) reg [0:0] redist19_fracX_uid10_fpDivTest_b_10_sticky_ena_q; + wire [0:0] redist19_fracX_uid10_fpDivTest_b_10_enaAnd_q; + + + // fracY_uid13_fpDivTest(BITSELECT,12)@0 + assign fracY_uid13_fpDivTest_b = b[22:0]; + + // paddingY_uid15_fpDivTest(CONSTANT,14) + assign paddingY_uid15_fpDivTest_q = 23'b00000000000000000000000; + + // fracXIsZero_uid39_fpDivTest(LOGICAL,38)@0 + 1 + assign fracXIsZero_uid39_fpDivTest_qi = paddingY_uid15_fpDivTest_q == fracY_uid13_fpDivTest_b ? 1'b1 : 1'b0; + dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) + fracXIsZero_uid39_fpDivTest_delay ( .xin(fracXIsZero_uid39_fpDivTest_qi), .xout(fracXIsZero_uid39_fpDivTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // redist12_fracXIsZero_uid39_fpDivTest_q_14(DELAY,164) + dspba_delay_ver #( .width(1), .depth(13), .reset_kind("ASYNC") ) + redist12_fracXIsZero_uid39_fpDivTest_q_14 ( .xin(fracXIsZero_uid39_fpDivTest_q), .xout(redist12_fracXIsZero_uid39_fpDivTest_q_14_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // cstAllOWE_uid18_fpDivTest(CONSTANT,17) + assign cstAllOWE_uid18_fpDivTest_q = 8'b11111111; + + // expY_uid12_fpDivTest(BITSELECT,11)@0 + assign expY_uid12_fpDivTest_b = b[30:23]; + + // expXIsMax_uid38_fpDivTest(LOGICAL,37)@0 + 1 + assign expXIsMax_uid38_fpDivTest_qi = expY_uid12_fpDivTest_b == cstAllOWE_uid18_fpDivTest_q ? 1'b1 : 1'b0; + dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) + expXIsMax_uid38_fpDivTest_delay ( .xin(expXIsMax_uid38_fpDivTest_qi), .xout(expXIsMax_uid38_fpDivTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // redist13_expXIsMax_uid38_fpDivTest_q_14(DELAY,165) + dspba_delay_ver #( .width(1), .depth(13), .reset_kind("ASYNC") ) + redist13_expXIsMax_uid38_fpDivTest_q_14 ( .xin(expXIsMax_uid38_fpDivTest_q), .xout(redist13_expXIsMax_uid38_fpDivTest_q_14_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // excI_y_uid41_fpDivTest(LOGICAL,40)@14 + assign excI_y_uid41_fpDivTest_q = redist13_expXIsMax_uid38_fpDivTest_q_14_q & redist12_fracXIsZero_uid39_fpDivTest_q_14_q; + + // redist19_fracX_uid10_fpDivTest_b_10_notEnable(LOGICAL,202) + assign redist19_fracX_uid10_fpDivTest_b_10_notEnable_q = ~ (en); + + // redist19_fracX_uid10_fpDivTest_b_10_nor(LOGICAL,203) + assign redist19_fracX_uid10_fpDivTest_b_10_nor_q = ~ (redist19_fracX_uid10_fpDivTest_b_10_notEnable_q | redist19_fracX_uid10_fpDivTest_b_10_sticky_ena_q); + + // redist19_fracX_uid10_fpDivTest_b_10_mem_last(CONSTANT,199) + assign redist19_fracX_uid10_fpDivTest_b_10_mem_last_q = 4'b0111; + + // redist19_fracX_uid10_fpDivTest_b_10_cmp(LOGICAL,200) + assign redist19_fracX_uid10_fpDivTest_b_10_cmp_q = redist19_fracX_uid10_fpDivTest_b_10_mem_last_q == redist19_fracX_uid10_fpDivTest_b_10_rdmux_q ? 1'b1 : 1'b0; + + // redist19_fracX_uid10_fpDivTest_b_10_cmpReg(REG,201) + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + redist19_fracX_uid10_fpDivTest_b_10_cmpReg_q <= 1'b0; + end + else if (en == 1'b1) + begin + redist19_fracX_uid10_fpDivTest_b_10_cmpReg_q <= redist19_fracX_uid10_fpDivTest_b_10_cmp_q; + end + end + + // redist19_fracX_uid10_fpDivTest_b_10_sticky_ena(REG,204) + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + redist19_fracX_uid10_fpDivTest_b_10_sticky_ena_q <= 1'b0; + end + else if (redist19_fracX_uid10_fpDivTest_b_10_nor_q == 1'b1) + begin + redist19_fracX_uid10_fpDivTest_b_10_sticky_ena_q <= redist19_fracX_uid10_fpDivTest_b_10_cmpReg_q; + end + end + + // redist19_fracX_uid10_fpDivTest_b_10_enaAnd(LOGICAL,205) + assign redist19_fracX_uid10_fpDivTest_b_10_enaAnd_q = redist19_fracX_uid10_fpDivTest_b_10_sticky_ena_q & en; + + // redist19_fracX_uid10_fpDivTest_b_10_rdcnt(COUNTER,196) + // low=0, high=8, step=1, init=0 + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + redist19_fracX_uid10_fpDivTest_b_10_rdcnt_i <= 4'd0; + redist19_fracX_uid10_fpDivTest_b_10_rdcnt_eq <= 1'b0; + end + else if (en == 1'b1) + begin + if (redist19_fracX_uid10_fpDivTest_b_10_rdcnt_i == 4'd7) + begin + redist19_fracX_uid10_fpDivTest_b_10_rdcnt_eq <= 1'b1; + end + else + begin + redist19_fracX_uid10_fpDivTest_b_10_rdcnt_eq <= 1'b0; + end + if (redist19_fracX_uid10_fpDivTest_b_10_rdcnt_eq == 1'b1) + begin + redist19_fracX_uid10_fpDivTest_b_10_rdcnt_i <= $unsigned(redist19_fracX_uid10_fpDivTest_b_10_rdcnt_i) + $unsigned(4'd8); + end + else + begin + redist19_fracX_uid10_fpDivTest_b_10_rdcnt_i <= $unsigned(redist19_fracX_uid10_fpDivTest_b_10_rdcnt_i) + $unsigned(4'd1); + end + end + end + assign redist19_fracX_uid10_fpDivTest_b_10_rdcnt_q = redist19_fracX_uid10_fpDivTest_b_10_rdcnt_i[3:0]; + + // redist19_fracX_uid10_fpDivTest_b_10_rdmux(MUX,197) + assign redist19_fracX_uid10_fpDivTest_b_10_rdmux_s = en; + always @(redist19_fracX_uid10_fpDivTest_b_10_rdmux_s or redist19_fracX_uid10_fpDivTest_b_10_wraddr_q or redist19_fracX_uid10_fpDivTest_b_10_rdcnt_q) + begin + unique case (redist19_fracX_uid10_fpDivTest_b_10_rdmux_s) + 1'b0 : redist19_fracX_uid10_fpDivTest_b_10_rdmux_q = redist19_fracX_uid10_fpDivTest_b_10_wraddr_q; + 1'b1 : redist19_fracX_uid10_fpDivTest_b_10_rdmux_q = redist19_fracX_uid10_fpDivTest_b_10_rdcnt_q; + default : redist19_fracX_uid10_fpDivTest_b_10_rdmux_q = 4'b0; + endcase + end + + // VCC(CONSTANT,1) + assign VCC_q = 1'b1; + + // fracX_uid10_fpDivTest(BITSELECT,9)@0 + assign fracX_uid10_fpDivTest_b = a[22:0]; + + // redist19_fracX_uid10_fpDivTest_b_10_wraddr(REG,198) + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + redist19_fracX_uid10_fpDivTest_b_10_wraddr_q <= 4'b1000; + end + else + begin + redist19_fracX_uid10_fpDivTest_b_10_wraddr_q <= redist19_fracX_uid10_fpDivTest_b_10_rdmux_q; + end + end + + // redist19_fracX_uid10_fpDivTest_b_10_mem(DUALMEM,195) + assign redist19_fracX_uid10_fpDivTest_b_10_mem_ia = fracX_uid10_fpDivTest_b; + assign redist19_fracX_uid10_fpDivTest_b_10_mem_aa = redist19_fracX_uid10_fpDivTest_b_10_wraddr_q; + assign redist19_fracX_uid10_fpDivTest_b_10_mem_ab = redist19_fracX_uid10_fpDivTest_b_10_rdmux_q; + assign redist19_fracX_uid10_fpDivTest_b_10_mem_reset0 = areset; + altera_syncram #( + .ram_block_type("MLAB"), + .operation_mode("DUAL_PORT"), + .width_a(23), + .widthad_a(4), + .numwords_a(9), + .width_b(23), + .widthad_b(4), + .numwords_b(9), + .lpm_type("altera_syncram"), + .width_byteena_a(1), + .address_reg_b("CLOCK0"), + .indata_reg_b("CLOCK0"), + .rdcontrol_reg_b("CLOCK0"), + .byteena_reg_b("CLOCK0"), + .outdata_reg_b("CLOCK1"), + .outdata_aclr_b("CLEAR1"), + .clock_enable_input_a("NORMAL"), + .clock_enable_input_b("NORMAL"), + .clock_enable_output_b("NORMAL"), + .read_during_write_mode_mixed_ports("DONT_CARE"), + .power_up_uninitialized("TRUE"), + .intended_device_family("Arria 10") + ) redist19_fracX_uid10_fpDivTest_b_10_mem_dmem ( + .clocken1(redist19_fracX_uid10_fpDivTest_b_10_enaAnd_q[0]), + .clocken0(VCC_q[0]), + .clock0(clk), + .aclr1(redist19_fracX_uid10_fpDivTest_b_10_mem_reset0), + .clock1(clk), + .address_a(redist19_fracX_uid10_fpDivTest_b_10_mem_aa), + .data_a(redist19_fracX_uid10_fpDivTest_b_10_mem_ia), + .wren_a(en[0]), + .address_b(redist19_fracX_uid10_fpDivTest_b_10_mem_ab), + .q_b(redist19_fracX_uid10_fpDivTest_b_10_mem_iq), + .wren_b(), + .rden_a(), + .rden_b(), + .data_b(), + .clocken2(), + .clocken3(), + .aclr0(), + .addressstall_a(), + .addressstall_b(), + .byteena_a(), + .byteena_b(), + .eccencbypass(), + .eccencparity(), + .sclr(), + .address2_a(), + .address2_b(), + .q_a(), + .eccstatus() + ); + assign redist19_fracX_uid10_fpDivTest_b_10_mem_q = redist19_fracX_uid10_fpDivTest_b_10_mem_iq[22:0]; + + // fracXIsZero_uid25_fpDivTest(LOGICAL,24)@10 + 1 + assign fracXIsZero_uid25_fpDivTest_qi = paddingY_uid15_fpDivTest_q == redist19_fracX_uid10_fpDivTest_b_10_mem_q ? 1'b1 : 1'b0; + dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) + fracXIsZero_uid25_fpDivTest_delay ( .xin(fracXIsZero_uid25_fpDivTest_qi), .xout(fracXIsZero_uid25_fpDivTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // redist15_fracXIsZero_uid25_fpDivTest_q_4(DELAY,167) + dspba_delay_ver #( .width(1), .depth(3), .reset_kind("ASYNC") ) + redist15_fracXIsZero_uid25_fpDivTest_q_4 ( .xin(fracXIsZero_uid25_fpDivTest_q), .xout(redist15_fracXIsZero_uid25_fpDivTest_q_4_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // expX_uid9_fpDivTest(BITSELECT,8)@0 + assign expX_uid9_fpDivTest_b = a[30:23]; + + // expXIsMax_uid24_fpDivTest(LOGICAL,23)@0 + 1 + assign expXIsMax_uid24_fpDivTest_qi = expX_uid9_fpDivTest_b == cstAllOWE_uid18_fpDivTest_q ? 1'b1 : 1'b0; + dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) + expXIsMax_uid24_fpDivTest_delay ( .xin(expXIsMax_uid24_fpDivTest_qi), .xout(expXIsMax_uid24_fpDivTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // redist16_expXIsMax_uid24_fpDivTest_q_14(DELAY,168) + dspba_delay_ver #( .width(1), .depth(13), .reset_kind("ASYNC") ) + redist16_expXIsMax_uid24_fpDivTest_q_14 ( .xin(expXIsMax_uid24_fpDivTest_q), .xout(redist16_expXIsMax_uid24_fpDivTest_q_14_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // excI_x_uid27_fpDivTest(LOGICAL,26)@14 + assign excI_x_uid27_fpDivTest_q = redist16_expXIsMax_uid24_fpDivTest_q_14_q & redist15_fracXIsZero_uid25_fpDivTest_q_4_q; + + // excXIYI_uid96_fpDivTest(LOGICAL,95)@14 + assign excXIYI_uid96_fpDivTest_q = excI_x_uid27_fpDivTest_q & excI_y_uid41_fpDivTest_q; + + // fracXIsNotZero_uid40_fpDivTest(LOGICAL,39)@14 + assign fracXIsNotZero_uid40_fpDivTest_q = ~ (redist12_fracXIsZero_uid39_fpDivTest_q_14_q); + + // excN_y_uid42_fpDivTest(LOGICAL,41)@14 + assign excN_y_uid42_fpDivTest_q = redist13_expXIsMax_uid38_fpDivTest_q_14_q & fracXIsNotZero_uid40_fpDivTest_q; + + // fracXIsNotZero_uid26_fpDivTest(LOGICAL,25)@14 + assign fracXIsNotZero_uid26_fpDivTest_q = ~ (redist15_fracXIsZero_uid25_fpDivTest_q_4_q); + + // excN_x_uid28_fpDivTest(LOGICAL,27)@14 + assign excN_x_uid28_fpDivTest_q = redist16_expXIsMax_uid24_fpDivTest_q_14_q & fracXIsNotZero_uid26_fpDivTest_q; + + // cstAllZWE_uid20_fpDivTest(CONSTANT,19) + assign cstAllZWE_uid20_fpDivTest_q = 8'b00000000; + + // excZ_y_uid37_fpDivTest(LOGICAL,36)@0 + 1 + assign excZ_y_uid37_fpDivTest_qi = expY_uid12_fpDivTest_b == cstAllZWE_uid20_fpDivTest_q ? 1'b1 : 1'b0; + dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) + excZ_y_uid37_fpDivTest_delay ( .xin(excZ_y_uid37_fpDivTest_qi), .xout(excZ_y_uid37_fpDivTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // redist14_excZ_y_uid37_fpDivTest_q_14(DELAY,166) + dspba_delay_ver #( .width(1), .depth(13), .reset_kind("ASYNC") ) + redist14_excZ_y_uid37_fpDivTest_q_14 ( .xin(excZ_y_uid37_fpDivTest_q), .xout(redist14_excZ_y_uid37_fpDivTest_q_14_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // excZ_x_uid23_fpDivTest(LOGICAL,22)@0 + 1 + assign excZ_x_uid23_fpDivTest_qi = expX_uid9_fpDivTest_b == cstAllZWE_uid20_fpDivTest_q ? 1'b1 : 1'b0; + dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) + excZ_x_uid23_fpDivTest_delay ( .xin(excZ_x_uid23_fpDivTest_qi), .xout(excZ_x_uid23_fpDivTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // redist17_excZ_x_uid23_fpDivTest_q_14(DELAY,169) + dspba_delay_ver #( .width(1), .depth(13), .reset_kind("ASYNC") ) + redist17_excZ_x_uid23_fpDivTest_q_14 ( .xin(excZ_x_uid23_fpDivTest_q), .xout(redist17_excZ_x_uid23_fpDivTest_q_14_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // excXZYZ_uid95_fpDivTest(LOGICAL,94)@14 + assign excXZYZ_uid95_fpDivTest_q = redist17_excZ_x_uid23_fpDivTest_q_14_q & redist14_excZ_y_uid37_fpDivTest_q_14_q; + + // excRNaN_uid97_fpDivTest(LOGICAL,96)@14 + assign excRNaN_uid97_fpDivTest_q = excXZYZ_uid95_fpDivTest_q | excN_x_uid28_fpDivTest_q | excN_y_uid42_fpDivTest_q | excXIYI_uid96_fpDivTest_q; + + // invExcRNaN_uid108_fpDivTest(LOGICAL,107)@14 + assign invExcRNaN_uid108_fpDivTest_q = ~ (excRNaN_uid97_fpDivTest_q); + + // signY_uid14_fpDivTest(BITSELECT,13)@0 + assign signY_uid14_fpDivTest_b = b[31:31]; + + // signX_uid11_fpDivTest(BITSELECT,10)@0 + assign signX_uid11_fpDivTest_b = a[31:31]; + + // signR_uid46_fpDivTest(LOGICAL,45)@0 + 1 + assign signR_uid46_fpDivTest_qi = signX_uid11_fpDivTest_b ^ signY_uid14_fpDivTest_b; + dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) + signR_uid46_fpDivTest_delay ( .xin(signR_uid46_fpDivTest_qi), .xout(signR_uid46_fpDivTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // redist11_signR_uid46_fpDivTest_q_14(DELAY,163) + dspba_delay_ver #( .width(1), .depth(13), .reset_kind("ASYNC") ) + redist11_signR_uid46_fpDivTest_q_14 ( .xin(signR_uid46_fpDivTest_q), .xout(redist11_signR_uid46_fpDivTest_q_14_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // sRPostExc_uid109_fpDivTest(LOGICAL,108)@14 + 1 + assign sRPostExc_uid109_fpDivTest_qi = redist11_signR_uid46_fpDivTest_q_14_q & invExcRNaN_uid108_fpDivTest_q; + dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) + sRPostExc_uid109_fpDivTest_delay ( .xin(sRPostExc_uid109_fpDivTest_qi), .xout(sRPostExc_uid109_fpDivTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // lOAdded_uid58_fpDivTest(BITJOIN,57)@10 + assign lOAdded_uid58_fpDivTest_q = {VCC_q, redist19_fracX_uid10_fpDivTest_b_10_mem_q}; + + // redist4_lOAdded_uid58_fpDivTest_q_3(DELAY,156) + dspba_delay_ver #( .width(24), .depth(3), .reset_kind("ASYNC") ) + redist4_lOAdded_uid58_fpDivTest_q_3 ( .xin(lOAdded_uid58_fpDivTest_q), .xout(redist4_lOAdded_uid58_fpDivTest_q_3_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // oFracXSE_bottomExtension_uid61_fpDivTest(CONSTANT,60) + assign oFracXSE_bottomExtension_uid61_fpDivTest_q = 2'b00; + + // oFracXSE_mergedSignalTM_uid63_fpDivTest(BITJOIN,62)@13 + assign oFracXSE_mergedSignalTM_uid63_fpDivTest_q = {redist4_lOAdded_uid58_fpDivTest_q_3_q, oFracXSE_bottomExtension_uid61_fpDivTest_q}; + + // yAddr_uid51_fpDivTest(BITSELECT,50)@0 + assign yAddr_uid51_fpDivTest_b = fracY_uid13_fpDivTest_b[22:14]; + + // memoryC2_uid118_invTables_lutmem(DUALMEM,147)@0 + 2 + // in j@20000000 + assign memoryC2_uid118_invTables_lutmem_aa = yAddr_uid51_fpDivTest_b; + assign memoryC2_uid118_invTables_lutmem_reset0 = areset; + altera_syncram #( + .ram_block_type("M20K"), + .operation_mode("ROM"), + .width_a(12), + .widthad_a(9), + .numwords_a(512), + .lpm_type("altera_syncram"), + .width_byteena_a(1), + .outdata_reg_a("CLOCK0"), + .outdata_aclr_a("CLEAR0"), + .clock_enable_input_a("NORMAL"), + .power_up_uninitialized("FALSE"), + .init_file("acl_fdiv_memoryC2_uid118_invTables_lutmem.hex"), + .init_file_layout("PORT_A"), + .intended_device_family("Arria 10") + ) memoryC2_uid118_invTables_lutmem_dmem ( + .clocken0(en[0]), + .aclr0(memoryC2_uid118_invTables_lutmem_reset0), + .clock0(clk), + .address_a(memoryC2_uid118_invTables_lutmem_aa), + .q_a(memoryC2_uid118_invTables_lutmem_ir), + .wren_a(), + .wren_b(), + .rden_a(), + .rden_b(), + .data_a(), + .data_b(), + .address_b(), + .clock1(), + .clocken1(), + .clocken2(), + .clocken3(), + .aclr1(), + .addressstall_a(), + .addressstall_b(), + .byteena_a(), + .byteena_b(), + .eccencbypass(), + .eccencparity(), + .sclr(), + .address2_a(), + .address2_b(), + .q_b(), + .eccstatus() + ); + assign memoryC2_uid118_invTables_lutmem_r = memoryC2_uid118_invTables_lutmem_ir[11:0]; + + // yPE_uid52_fpDivTest(BITSELECT,51)@0 + assign yPE_uid52_fpDivTest_b = b[13:0]; + + // redist6_yPE_uid52_fpDivTest_b_2(DELAY,158) + dspba_delay_ver #( .width(14), .depth(2), .reset_kind("ASYNC") ) + redist6_yPE_uid52_fpDivTest_b_2 ( .xin(yPE_uid52_fpDivTest_b), .xout(redist6_yPE_uid52_fpDivTest_b_2_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // yT1_uid124_invPolyEval(BITSELECT,123)@2 + assign yT1_uid124_invPolyEval_b = redist6_yPE_uid52_fpDivTest_b_2_q[13:2]; + + // prodXY_uid140_pT1_uid125_invPolyEval_cma(CHAINMULTADD,149)@2 + 3 + assign prodXY_uid140_pT1_uid125_invPolyEval_cma_reset = areset; + assign prodXY_uid140_pT1_uid125_invPolyEval_cma_ena0 = en[0]; + assign prodXY_uid140_pT1_uid125_invPolyEval_cma_ena1 = prodXY_uid140_pT1_uid125_invPolyEval_cma_ena0; + assign prodXY_uid140_pT1_uid125_invPolyEval_cma_ena2 = prodXY_uid140_pT1_uid125_invPolyEval_cma_ena0; + assign prodXY_uid140_pT1_uid125_invPolyEval_cma_l[0] = $signed({1'b0, prodXY_uid140_pT1_uid125_invPolyEval_cma_a1[0][11:0]}); + assign prodXY_uid140_pT1_uid125_invPolyEval_cma_p[0] = prodXY_uid140_pT1_uid125_invPolyEval_cma_l[0] * prodXY_uid140_pT1_uid125_invPolyEval_cma_c1[0]; + assign prodXY_uid140_pT1_uid125_invPolyEval_cma_u[0] = prodXY_uid140_pT1_uid125_invPolyEval_cma_p[0][24:0]; + assign prodXY_uid140_pT1_uid125_invPolyEval_cma_w[0] = prodXY_uid140_pT1_uid125_invPolyEval_cma_u[0]; + assign prodXY_uid140_pT1_uid125_invPolyEval_cma_x[0] = prodXY_uid140_pT1_uid125_invPolyEval_cma_w[0]; + assign prodXY_uid140_pT1_uid125_invPolyEval_cma_y[0] = prodXY_uid140_pT1_uid125_invPolyEval_cma_x[0]; + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + prodXY_uid140_pT1_uid125_invPolyEval_cma_a0 <= '{default: '0}; + prodXY_uid140_pT1_uid125_invPolyEval_cma_c0 <= '{default: '0}; + end + else + begin + if (prodXY_uid140_pT1_uid125_invPolyEval_cma_ena0 == 1'b1) + begin + prodXY_uid140_pT1_uid125_invPolyEval_cma_a0[0] <= yT1_uid124_invPolyEval_b; + prodXY_uid140_pT1_uid125_invPolyEval_cma_c0[0] <= memoryC2_uid118_invTables_lutmem_r; + end + end + end + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + prodXY_uid140_pT1_uid125_invPolyEval_cma_a1 <= '{default: '0}; + prodXY_uid140_pT1_uid125_invPolyEval_cma_c1 <= '{default: '0}; + end + else + begin + if (prodXY_uid140_pT1_uid125_invPolyEval_cma_ena2 == 1'b1) + begin + prodXY_uid140_pT1_uid125_invPolyEval_cma_a1 <= prodXY_uid140_pT1_uid125_invPolyEval_cma_a0; + prodXY_uid140_pT1_uid125_invPolyEval_cma_c1 <= prodXY_uid140_pT1_uid125_invPolyEval_cma_c0; + end + end + end + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + prodXY_uid140_pT1_uid125_invPolyEval_cma_s <= '{default: '0}; + end + else + begin + if (prodXY_uid140_pT1_uid125_invPolyEval_cma_ena1 == 1'b1) + begin + prodXY_uid140_pT1_uid125_invPolyEval_cma_s[0] <= prodXY_uid140_pT1_uid125_invPolyEval_cma_y[0]; + end + end + end + dspba_delay_ver #( .width(24), .depth(0), .reset_kind("ASYNC") ) + prodXY_uid140_pT1_uid125_invPolyEval_cma_delay ( .xin(prodXY_uid140_pT1_uid125_invPolyEval_cma_s[0][23:0]), .xout(prodXY_uid140_pT1_uid125_invPolyEval_cma_qq), .ena(en[0]), .clk(clk), .aclr(areset) ); + assign prodXY_uid140_pT1_uid125_invPolyEval_cma_q = prodXY_uid140_pT1_uid125_invPolyEval_cma_qq[23:0]; + + // osig_uid141_pT1_uid125_invPolyEval(BITSELECT,140)@5 + assign osig_uid141_pT1_uid125_invPolyEval_b = prodXY_uid140_pT1_uid125_invPolyEval_cma_q[23:11]; + + // highBBits_uid127_invPolyEval(BITSELECT,126)@5 + assign highBBits_uid127_invPolyEval_b = osig_uid141_pT1_uid125_invPolyEval_b[12:1]; + + // redist8_yAddr_uid51_fpDivTest_b_3(DELAY,160) + dspba_delay_ver #( .width(9), .depth(3), .reset_kind("ASYNC") ) + redist8_yAddr_uid51_fpDivTest_b_3 ( .xin(yAddr_uid51_fpDivTest_b), .xout(redist8_yAddr_uid51_fpDivTest_b_3_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // memoryC1_uid115_invTables_lutmem(DUALMEM,146)@3 + 2 + // in j@20000000 + assign memoryC1_uid115_invTables_lutmem_aa = redist8_yAddr_uid51_fpDivTest_b_3_q; + assign memoryC1_uid115_invTables_lutmem_reset0 = areset; + altera_syncram #( + .ram_block_type("M20K"), + .operation_mode("ROM"), + .width_a(21), + .widthad_a(9), + .numwords_a(512), + .lpm_type("altera_syncram"), + .width_byteena_a(1), + .outdata_reg_a("CLOCK0"), + .outdata_aclr_a("CLEAR0"), + .clock_enable_input_a("NORMAL"), + .power_up_uninitialized("FALSE"), + .init_file("acl_fdiv_memoryC1_uid115_invTables_lutmem.hex"), + .init_file_layout("PORT_A"), + .intended_device_family("Arria 10") + ) memoryC1_uid115_invTables_lutmem_dmem ( + .clocken0(en[0]), + .aclr0(memoryC1_uid115_invTables_lutmem_reset0), + .clock0(clk), + .address_a(memoryC1_uid115_invTables_lutmem_aa), + .q_a(memoryC1_uid115_invTables_lutmem_ir), + .wren_a(), + .wren_b(), + .rden_a(), + .rden_b(), + .data_a(), + .data_b(), + .address_b(), + .clock1(), + .clocken1(), + .clocken2(), + .clocken3(), + .aclr1(), + .addressstall_a(), + .addressstall_b(), + .byteena_a(), + .byteena_b(), + .eccencbypass(), + .eccencparity(), + .sclr(), + .address2_a(), + .address2_b(), + .q_b(), + .eccstatus() + ); + assign memoryC1_uid115_invTables_lutmem_r = memoryC1_uid115_invTables_lutmem_ir[20:0]; + + // s1sumAHighB_uid128_invPolyEval(ADD,127)@5 + 1 + assign s1sumAHighB_uid128_invPolyEval_a = {{1{memoryC1_uid115_invTables_lutmem_r[20]}}, memoryC1_uid115_invTables_lutmem_r}; + assign s1sumAHighB_uid128_invPolyEval_b = {{10{highBBits_uid127_invPolyEval_b[11]}}, highBBits_uid127_invPolyEval_b}; + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + s1sumAHighB_uid128_invPolyEval_o <= 22'b0; + end + else if (en == 1'b1) + begin + s1sumAHighB_uid128_invPolyEval_o <= $signed(s1sumAHighB_uid128_invPolyEval_a) + $signed(s1sumAHighB_uid128_invPolyEval_b); + end + end + assign s1sumAHighB_uid128_invPolyEval_q = s1sumAHighB_uid128_invPolyEval_o[21:0]; + + // lowRangeB_uid126_invPolyEval(BITSELECT,125)@5 + assign lowRangeB_uid126_invPolyEval_in = osig_uid141_pT1_uid125_invPolyEval_b[0:0]; + assign lowRangeB_uid126_invPolyEval_b = lowRangeB_uid126_invPolyEval_in[0:0]; + + // redist1_lowRangeB_uid126_invPolyEval_b_1(DELAY,153) + dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) + redist1_lowRangeB_uid126_invPolyEval_b_1 ( .xin(lowRangeB_uid126_invPolyEval_b), .xout(redist1_lowRangeB_uid126_invPolyEval_b_1_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // s1_uid129_invPolyEval(BITJOIN,128)@6 + assign s1_uid129_invPolyEval_q = {s1sumAHighB_uid128_invPolyEval_q, redist1_lowRangeB_uid126_invPolyEval_b_1_q}; + + // redist7_yPE_uid52_fpDivTest_b_6_notEnable(LOGICAL,179) + assign redist7_yPE_uid52_fpDivTest_b_6_notEnable_q = ~ (en); + + // redist7_yPE_uid52_fpDivTest_b_6_nor(LOGICAL,180) + assign redist7_yPE_uid52_fpDivTest_b_6_nor_q = ~ (redist7_yPE_uid52_fpDivTest_b_6_notEnable_q | redist7_yPE_uid52_fpDivTest_b_6_sticky_ena_q); + + // redist7_yPE_uid52_fpDivTest_b_6_mem_last(CONSTANT,176) + assign redist7_yPE_uid52_fpDivTest_b_6_mem_last_q = 2'b01; + + // redist7_yPE_uid52_fpDivTest_b_6_cmp(LOGICAL,177) + assign redist7_yPE_uid52_fpDivTest_b_6_cmp_q = redist7_yPE_uid52_fpDivTest_b_6_mem_last_q == redist7_yPE_uid52_fpDivTest_b_6_rdmux_q ? 1'b1 : 1'b0; + + // redist7_yPE_uid52_fpDivTest_b_6_cmpReg(REG,178) + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + redist7_yPE_uid52_fpDivTest_b_6_cmpReg_q <= 1'b0; + end + else if (en == 1'b1) + begin + redist7_yPE_uid52_fpDivTest_b_6_cmpReg_q <= redist7_yPE_uid52_fpDivTest_b_6_cmp_q; + end + end + + // redist7_yPE_uid52_fpDivTest_b_6_sticky_ena(REG,181) + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + redist7_yPE_uid52_fpDivTest_b_6_sticky_ena_q <= 1'b0; + end + else if (redist7_yPE_uid52_fpDivTest_b_6_nor_q == 1'b1) + begin + redist7_yPE_uid52_fpDivTest_b_6_sticky_ena_q <= redist7_yPE_uid52_fpDivTest_b_6_cmpReg_q; + end + end + + // redist7_yPE_uid52_fpDivTest_b_6_enaAnd(LOGICAL,182) + assign redist7_yPE_uid52_fpDivTest_b_6_enaAnd_q = redist7_yPE_uid52_fpDivTest_b_6_sticky_ena_q & en; + + // redist7_yPE_uid52_fpDivTest_b_6_rdcnt(COUNTER,173) + // low=0, high=2, step=1, init=0 + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + redist7_yPE_uid52_fpDivTest_b_6_rdcnt_i <= 2'd0; + redist7_yPE_uid52_fpDivTest_b_6_rdcnt_eq <= 1'b0; + end + else if (en == 1'b1) + begin + if (redist7_yPE_uid52_fpDivTest_b_6_rdcnt_i == 2'd1) + begin + redist7_yPE_uid52_fpDivTest_b_6_rdcnt_eq <= 1'b1; + end + else + begin + redist7_yPE_uid52_fpDivTest_b_6_rdcnt_eq <= 1'b0; + end + if (redist7_yPE_uid52_fpDivTest_b_6_rdcnt_eq == 1'b1) + begin + redist7_yPE_uid52_fpDivTest_b_6_rdcnt_i <= $unsigned(redist7_yPE_uid52_fpDivTest_b_6_rdcnt_i) + $unsigned(2'd2); + end + else + begin + redist7_yPE_uid52_fpDivTest_b_6_rdcnt_i <= $unsigned(redist7_yPE_uid52_fpDivTest_b_6_rdcnt_i) + $unsigned(2'd1); + end + end + end + assign redist7_yPE_uid52_fpDivTest_b_6_rdcnt_q = redist7_yPE_uid52_fpDivTest_b_6_rdcnt_i[1:0]; + + // redist7_yPE_uid52_fpDivTest_b_6_rdmux(MUX,174) + assign redist7_yPE_uid52_fpDivTest_b_6_rdmux_s = en; + always @(redist7_yPE_uid52_fpDivTest_b_6_rdmux_s or redist7_yPE_uid52_fpDivTest_b_6_wraddr_q or redist7_yPE_uid52_fpDivTest_b_6_rdcnt_q) + begin + unique case (redist7_yPE_uid52_fpDivTest_b_6_rdmux_s) + 1'b0 : redist7_yPE_uid52_fpDivTest_b_6_rdmux_q = redist7_yPE_uid52_fpDivTest_b_6_wraddr_q; + 1'b1 : redist7_yPE_uid52_fpDivTest_b_6_rdmux_q = redist7_yPE_uid52_fpDivTest_b_6_rdcnt_q; + default : redist7_yPE_uid52_fpDivTest_b_6_rdmux_q = 2'b0; + endcase + end + + // redist7_yPE_uid52_fpDivTest_b_6_wraddr(REG,175) + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + redist7_yPE_uid52_fpDivTest_b_6_wraddr_q <= 2'b10; + end + else + begin + redist7_yPE_uid52_fpDivTest_b_6_wraddr_q <= redist7_yPE_uid52_fpDivTest_b_6_rdmux_q; + end + end + + // redist7_yPE_uid52_fpDivTest_b_6_mem(DUALMEM,172) + assign redist7_yPE_uid52_fpDivTest_b_6_mem_ia = redist6_yPE_uid52_fpDivTest_b_2_q; + assign redist7_yPE_uid52_fpDivTest_b_6_mem_aa = redist7_yPE_uid52_fpDivTest_b_6_wraddr_q; + assign redist7_yPE_uid52_fpDivTest_b_6_mem_ab = redist7_yPE_uid52_fpDivTest_b_6_rdmux_q; + assign redist7_yPE_uid52_fpDivTest_b_6_mem_reset0 = areset; + altera_syncram #( + .ram_block_type("MLAB"), + .operation_mode("DUAL_PORT"), + .width_a(14), + .widthad_a(2), + .numwords_a(3), + .width_b(14), + .widthad_b(2), + .numwords_b(3), + .lpm_type("altera_syncram"), + .width_byteena_a(1), + .address_reg_b("CLOCK0"), + .indata_reg_b("CLOCK0"), + .rdcontrol_reg_b("CLOCK0"), + .byteena_reg_b("CLOCK0"), + .outdata_reg_b("CLOCK1"), + .outdata_aclr_b("CLEAR1"), + .clock_enable_input_a("NORMAL"), + .clock_enable_input_b("NORMAL"), + .clock_enable_output_b("NORMAL"), + .read_during_write_mode_mixed_ports("DONT_CARE"), + .power_up_uninitialized("TRUE"), + .intended_device_family("Arria 10") + ) redist7_yPE_uid52_fpDivTest_b_6_mem_dmem ( + .clocken1(redist7_yPE_uid52_fpDivTest_b_6_enaAnd_q[0]), + .clocken0(VCC_q[0]), + .clock0(clk), + .aclr1(redist7_yPE_uid52_fpDivTest_b_6_mem_reset0), + .clock1(clk), + .address_a(redist7_yPE_uid52_fpDivTest_b_6_mem_aa), + .data_a(redist7_yPE_uid52_fpDivTest_b_6_mem_ia), + .wren_a(en[0]), + .address_b(redist7_yPE_uid52_fpDivTest_b_6_mem_ab), + .q_b(redist7_yPE_uid52_fpDivTest_b_6_mem_iq), + .wren_b(), + .rden_a(), + .rden_b(), + .data_b(), + .clocken2(), + .clocken3(), + .aclr0(), + .addressstall_a(), + .addressstall_b(), + .byteena_a(), + .byteena_b(), + .eccencbypass(), + .eccencparity(), + .sclr(), + .address2_a(), + .address2_b(), + .q_a(), + .eccstatus() + ); + assign redist7_yPE_uid52_fpDivTest_b_6_mem_q = redist7_yPE_uid52_fpDivTest_b_6_mem_iq[13:0]; + + // prodXY_uid143_pT2_uid131_invPolyEval_cma(CHAINMULTADD,150)@6 + 3 + assign prodXY_uid143_pT2_uid131_invPolyEval_cma_reset = areset; + assign prodXY_uid143_pT2_uid131_invPolyEval_cma_ena0 = en[0]; + assign prodXY_uid143_pT2_uid131_invPolyEval_cma_ena1 = prodXY_uid143_pT2_uid131_invPolyEval_cma_ena0; + assign prodXY_uid143_pT2_uid131_invPolyEval_cma_ena2 = prodXY_uid143_pT2_uid131_invPolyEval_cma_ena0; + assign prodXY_uid143_pT2_uid131_invPolyEval_cma_l[0] = $signed({1'b0, prodXY_uid143_pT2_uid131_invPolyEval_cma_a1[0][13:0]}); + assign prodXY_uid143_pT2_uid131_invPolyEval_cma_p[0] = prodXY_uid143_pT2_uid131_invPolyEval_cma_l[0] * prodXY_uid143_pT2_uid131_invPolyEval_cma_c1[0]; + assign prodXY_uid143_pT2_uid131_invPolyEval_cma_u[0] = prodXY_uid143_pT2_uid131_invPolyEval_cma_p[0][37:0]; + assign prodXY_uid143_pT2_uid131_invPolyEval_cma_w[0] = prodXY_uid143_pT2_uid131_invPolyEval_cma_u[0]; + assign prodXY_uid143_pT2_uid131_invPolyEval_cma_x[0] = prodXY_uid143_pT2_uid131_invPolyEval_cma_w[0]; + assign prodXY_uid143_pT2_uid131_invPolyEval_cma_y[0] = prodXY_uid143_pT2_uid131_invPolyEval_cma_x[0]; + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + prodXY_uid143_pT2_uid131_invPolyEval_cma_a0 <= '{default: '0}; + prodXY_uid143_pT2_uid131_invPolyEval_cma_c0 <= '{default: '0}; + end + else + begin + if (prodXY_uid143_pT2_uid131_invPolyEval_cma_ena0 == 1'b1) + begin + prodXY_uid143_pT2_uid131_invPolyEval_cma_a0[0] <= redist7_yPE_uid52_fpDivTest_b_6_mem_q; + prodXY_uid143_pT2_uid131_invPolyEval_cma_c0[0] <= s1_uid129_invPolyEval_q; + end + end + end + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + prodXY_uid143_pT2_uid131_invPolyEval_cma_a1 <= '{default: '0}; + prodXY_uid143_pT2_uid131_invPolyEval_cma_c1 <= '{default: '0}; + end + else + begin + if (prodXY_uid143_pT2_uid131_invPolyEval_cma_ena2 == 1'b1) + begin + prodXY_uid143_pT2_uid131_invPolyEval_cma_a1 <= prodXY_uid143_pT2_uid131_invPolyEval_cma_a0; + prodXY_uid143_pT2_uid131_invPolyEval_cma_c1 <= prodXY_uid143_pT2_uid131_invPolyEval_cma_c0; + end + end + end + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + prodXY_uid143_pT2_uid131_invPolyEval_cma_s <= '{default: '0}; + end + else + begin + if (prodXY_uid143_pT2_uid131_invPolyEval_cma_ena1 == 1'b1) + begin + prodXY_uid143_pT2_uid131_invPolyEval_cma_s[0] <= prodXY_uid143_pT2_uid131_invPolyEval_cma_y[0]; + end + end + end + dspba_delay_ver #( .width(37), .depth(0), .reset_kind("ASYNC") ) + prodXY_uid143_pT2_uid131_invPolyEval_cma_delay ( .xin(prodXY_uid143_pT2_uid131_invPolyEval_cma_s[0][36:0]), .xout(prodXY_uid143_pT2_uid131_invPolyEval_cma_qq), .ena(en[0]), .clk(clk), .aclr(areset) ); + assign prodXY_uid143_pT2_uid131_invPolyEval_cma_q = prodXY_uid143_pT2_uid131_invPolyEval_cma_qq[36:0]; + + // osig_uid144_pT2_uid131_invPolyEval(BITSELECT,143)@9 + assign osig_uid144_pT2_uid131_invPolyEval_b = prodXY_uid143_pT2_uid131_invPolyEval_cma_q[36:13]; + + // highBBits_uid133_invPolyEval(BITSELECT,132)@9 + assign highBBits_uid133_invPolyEval_b = osig_uid144_pT2_uid131_invPolyEval_b[23:2]; + + // redist9_yAddr_uid51_fpDivTest_b_7(DELAY,161) + dspba_delay_ver #( .width(9), .depth(4), .reset_kind("ASYNC") ) + redist9_yAddr_uid51_fpDivTest_b_7 ( .xin(redist8_yAddr_uid51_fpDivTest_b_3_q), .xout(redist9_yAddr_uid51_fpDivTest_b_7_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // memoryC0_uid112_invTables_lutmem(DUALMEM,145)@7 + 2 + // in j@20000000 + assign memoryC0_uid112_invTables_lutmem_aa = redist9_yAddr_uid51_fpDivTest_b_7_q; + assign memoryC0_uid112_invTables_lutmem_reset0 = areset; + altera_syncram #( + .ram_block_type("M20K"), + .operation_mode("ROM"), + .width_a(31), + .widthad_a(9), + .numwords_a(512), + .lpm_type("altera_syncram"), + .width_byteena_a(1), + .outdata_reg_a("CLOCK0"), + .outdata_aclr_a("CLEAR0"), + .clock_enable_input_a("NORMAL"), + .power_up_uninitialized("FALSE"), + .init_file("acl_fdiv_memoryC0_uid112_invTables_lutmem.hex"), + .init_file_layout("PORT_A"), + .intended_device_family("Arria 10") + ) memoryC0_uid112_invTables_lutmem_dmem ( + .clocken0(en[0]), + .aclr0(memoryC0_uid112_invTables_lutmem_reset0), + .clock0(clk), + .address_a(memoryC0_uid112_invTables_lutmem_aa), + .q_a(memoryC0_uid112_invTables_lutmem_ir), + .wren_a(), + .wren_b(), + .rden_a(), + .rden_b(), + .data_a(), + .data_b(), + .address_b(), + .clock1(), + .clocken1(), + .clocken2(), + .clocken3(), + .aclr1(), + .addressstall_a(), + .addressstall_b(), + .byteena_a(), + .byteena_b(), + .eccencbypass(), + .eccencparity(), + .sclr(), + .address2_a(), + .address2_b(), + .q_b(), + .eccstatus() + ); + assign memoryC0_uid112_invTables_lutmem_r = memoryC0_uid112_invTables_lutmem_ir[30:0]; + + // s2sumAHighB_uid134_invPolyEval(ADD,133)@9 + assign s2sumAHighB_uid134_invPolyEval_a = {{1{memoryC0_uid112_invTables_lutmem_r[30]}}, memoryC0_uid112_invTables_lutmem_r}; + assign s2sumAHighB_uid134_invPolyEval_b = {{10{highBBits_uid133_invPolyEval_b[21]}}, highBBits_uid133_invPolyEval_b}; + assign s2sumAHighB_uid134_invPolyEval_o = $signed(s2sumAHighB_uid134_invPolyEval_a) + $signed(s2sumAHighB_uid134_invPolyEval_b); + assign s2sumAHighB_uid134_invPolyEval_q = s2sumAHighB_uid134_invPolyEval_o[31:0]; + + // lowRangeB_uid132_invPolyEval(BITSELECT,131)@9 + assign lowRangeB_uid132_invPolyEval_in = osig_uid144_pT2_uid131_invPolyEval_b[1:0]; + assign lowRangeB_uid132_invPolyEval_b = lowRangeB_uid132_invPolyEval_in[1:0]; + + // s2_uid135_invPolyEval(BITJOIN,134)@9 + assign s2_uid135_invPolyEval_q = {s2sumAHighB_uid134_invPolyEval_q, lowRangeB_uid132_invPolyEval_b}; + + // invY_uid54_fpDivTest_merged_bit_select(BITSELECT,151)@9 + assign invY_uid54_fpDivTest_merged_bit_select_in = s2_uid135_invPolyEval_q[31:0]; + assign invY_uid54_fpDivTest_merged_bit_select_b = invY_uid54_fpDivTest_merged_bit_select_in[30:5]; + assign invY_uid54_fpDivTest_merged_bit_select_c = invY_uid54_fpDivTest_merged_bit_select_in[31:31]; + + // redist0_invY_uid54_fpDivTest_merged_bit_select_b_1(DELAY,152) + dspba_delay_ver #( .width(26), .depth(1), .reset_kind("ASYNC") ) + redist0_invY_uid54_fpDivTest_merged_bit_select_b_1 ( .xin(invY_uid54_fpDivTest_merged_bit_select_b), .xout(redist0_invY_uid54_fpDivTest_merged_bit_select_b_1_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // GND(CONSTANT,0) + assign GND_q = 1'b0; + + // prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma(CHAINMULTADD,148)@10 + 3 + assign prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_reset = areset; + assign prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_ena0 = en[0]; + assign prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_ena1 = prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_ena0; + assign prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_ena2 = prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_ena0; + assign prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_p[0] = prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_a1[0] * prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_c1[0]; + assign prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_u[0] = prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_p[0][49:0]; + assign prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_w[0] = prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_u[0]; + assign prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_x[0] = prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_w[0]; + assign prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_y[0] = prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_x[0]; + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_a0 <= '{default: '0}; + prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_c0 <= '{default: '0}; + end + else + begin + if (prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_ena0 == 1'b1) + begin + prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_a0[0] <= redist0_invY_uid54_fpDivTest_merged_bit_select_b_1_q; + prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_c0[0] <= lOAdded_uid58_fpDivTest_q; + end + end + end + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_a1 <= '{default: '0}; + prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_c1 <= '{default: '0}; + end + else + begin + if (prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_ena2 == 1'b1) + begin + prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_a1 <= prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_a0; + prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_c1 <= prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_c0; + end + end + end + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_s <= '{default: '0}; + end + else + begin + if (prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_ena1 == 1'b1) + begin + prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_s[0] <= prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_y[0]; + end + end + end + dspba_delay_ver #( .width(50), .depth(0), .reset_kind("ASYNC") ) + prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_delay ( .xin(prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_s[0][49:0]), .xout(prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_qq), .ena(en[0]), .clk(clk), .aclr(areset) ); + assign prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_q = prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_qq[49:0]; + + // osig_uid138_prodDivPreNormProd_uid60_fpDivTest(BITSELECT,137)@13 + assign osig_uid138_prodDivPreNormProd_uid60_fpDivTest_b = prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_q[49:24]; + + // updatedY_uid16_fpDivTest(BITJOIN,15)@0 + assign updatedY_uid16_fpDivTest_q = {GND_q, paddingY_uid15_fpDivTest_q}; + + // fracYZero_uid15_fpDivTest(LOGICAL,16)@0 + 1 + assign fracYZero_uid15_fpDivTest_a = {1'b0, fracY_uid13_fpDivTest_b}; + assign fracYZero_uid15_fpDivTest_qi = fracYZero_uid15_fpDivTest_a == updatedY_uid16_fpDivTest_q ? 1'b1 : 1'b0; + dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) + fracYZero_uid15_fpDivTest_delay ( .xin(fracYZero_uid15_fpDivTest_qi), .xout(fracYZero_uid15_fpDivTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // redist18_fracYZero_uid15_fpDivTest_q_9(DELAY,170) + dspba_delay_ver #( .width(1), .depth(8), .reset_kind("ASYNC") ) + redist18_fracYZero_uid15_fpDivTest_q_9 ( .xin(fracYZero_uid15_fpDivTest_q), .xout(redist18_fracYZero_uid15_fpDivTest_q_9_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // fracYPostZ_uid56_fpDivTest(LOGICAL,55)@9 + 1 + assign fracYPostZ_uid56_fpDivTest_qi = redist18_fracYZero_uid15_fpDivTest_q_9_q | invY_uid54_fpDivTest_merged_bit_select_c; + dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) + fracYPostZ_uid56_fpDivTest_delay ( .xin(fracYPostZ_uid56_fpDivTest_qi), .xout(fracYPostZ_uid56_fpDivTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // redist5_fracYPostZ_uid56_fpDivTest_q_4(DELAY,157) + dspba_delay_ver #( .width(1), .depth(3), .reset_kind("ASYNC") ) + redist5_fracYPostZ_uid56_fpDivTest_q_4 ( .xin(fracYPostZ_uid56_fpDivTest_q), .xout(redist5_fracYPostZ_uid56_fpDivTest_q_4_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // divValPreNormTrunc_uid66_fpDivTest(MUX,65)@13 + assign divValPreNormTrunc_uid66_fpDivTest_s = redist5_fracYPostZ_uid56_fpDivTest_q_4_q; + always @(divValPreNormTrunc_uid66_fpDivTest_s or en or osig_uid138_prodDivPreNormProd_uid60_fpDivTest_b or oFracXSE_mergedSignalTM_uid63_fpDivTest_q) + begin + unique case (divValPreNormTrunc_uid66_fpDivTest_s) + 1'b0 : divValPreNormTrunc_uid66_fpDivTest_q = osig_uid138_prodDivPreNormProd_uid60_fpDivTest_b; + 1'b1 : divValPreNormTrunc_uid66_fpDivTest_q = oFracXSE_mergedSignalTM_uid63_fpDivTest_q; + default : divValPreNormTrunc_uid66_fpDivTest_q = 26'b0; + endcase + end + + // norm_uid67_fpDivTest(BITSELECT,66)@13 + assign norm_uid67_fpDivTest_b = divValPreNormTrunc_uid66_fpDivTest_q[25:25]; + + // rndOp_uid75_fpDivTest(BITJOIN,74)@13 + assign rndOp_uid75_fpDivTest_q = {norm_uid67_fpDivTest_b, paddingY_uid15_fpDivTest_q, VCC_q}; + + // cstBiasM1_uid6_fpDivTest(CONSTANT,5) + assign cstBiasM1_uid6_fpDivTest_q = 8'b01111110; + + // redist10_expXmY_uid47_fpDivTest_q_13_notEnable(LOGICAL,191) + assign redist10_expXmY_uid47_fpDivTest_q_13_notEnable_q = ~ (en); + + // redist10_expXmY_uid47_fpDivTest_q_13_nor(LOGICAL,192) + assign redist10_expXmY_uid47_fpDivTest_q_13_nor_q = ~ (redist10_expXmY_uid47_fpDivTest_q_13_notEnable_q | redist10_expXmY_uid47_fpDivTest_q_13_sticky_ena_q); + + // redist10_expXmY_uid47_fpDivTest_q_13_mem_last(CONSTANT,188) + assign redist10_expXmY_uid47_fpDivTest_q_13_mem_last_q = 5'b01000; + + // redist10_expXmY_uid47_fpDivTest_q_13_cmp(LOGICAL,189) + assign redist10_expXmY_uid47_fpDivTest_q_13_cmp_b = {1'b0, redist10_expXmY_uid47_fpDivTest_q_13_rdmux_q}; + assign redist10_expXmY_uid47_fpDivTest_q_13_cmp_q = redist10_expXmY_uid47_fpDivTest_q_13_mem_last_q == redist10_expXmY_uid47_fpDivTest_q_13_cmp_b ? 1'b1 : 1'b0; + + // redist10_expXmY_uid47_fpDivTest_q_13_cmpReg(REG,190) + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + redist10_expXmY_uid47_fpDivTest_q_13_cmpReg_q <= 1'b0; + end + else if (en == 1'b1) + begin + redist10_expXmY_uid47_fpDivTest_q_13_cmpReg_q <= redist10_expXmY_uid47_fpDivTest_q_13_cmp_q; + end + end + + // redist10_expXmY_uid47_fpDivTest_q_13_sticky_ena(REG,193) + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + redist10_expXmY_uid47_fpDivTest_q_13_sticky_ena_q <= 1'b0; + end + else if (redist10_expXmY_uid47_fpDivTest_q_13_nor_q == 1'b1) + begin + redist10_expXmY_uid47_fpDivTest_q_13_sticky_ena_q <= redist10_expXmY_uid47_fpDivTest_q_13_cmpReg_q; + end + end + + // redist10_expXmY_uid47_fpDivTest_q_13_enaAnd(LOGICAL,194) + assign redist10_expXmY_uid47_fpDivTest_q_13_enaAnd_q = redist10_expXmY_uid47_fpDivTest_q_13_sticky_ena_q & en; + + // redist10_expXmY_uid47_fpDivTest_q_13_rdcnt(COUNTER,185) + // low=0, high=9, step=1, init=0 + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + redist10_expXmY_uid47_fpDivTest_q_13_rdcnt_i <= 4'd0; + redist10_expXmY_uid47_fpDivTest_q_13_rdcnt_eq <= 1'b0; + end + else if (en == 1'b1) + begin + if (redist10_expXmY_uid47_fpDivTest_q_13_rdcnt_i == 4'd8) + begin + redist10_expXmY_uid47_fpDivTest_q_13_rdcnt_eq <= 1'b1; + end + else + begin + redist10_expXmY_uid47_fpDivTest_q_13_rdcnt_eq <= 1'b0; + end + if (redist10_expXmY_uid47_fpDivTest_q_13_rdcnt_eq == 1'b1) + begin + redist10_expXmY_uid47_fpDivTest_q_13_rdcnt_i <= $unsigned(redist10_expXmY_uid47_fpDivTest_q_13_rdcnt_i) + $unsigned(4'd7); + end + else + begin + redist10_expXmY_uid47_fpDivTest_q_13_rdcnt_i <= $unsigned(redist10_expXmY_uid47_fpDivTest_q_13_rdcnt_i) + $unsigned(4'd1); + end + end + end + assign redist10_expXmY_uid47_fpDivTest_q_13_rdcnt_q = redist10_expXmY_uid47_fpDivTest_q_13_rdcnt_i[3:0]; + + // redist10_expXmY_uid47_fpDivTest_q_13_rdmux(MUX,186) + assign redist10_expXmY_uid47_fpDivTest_q_13_rdmux_s = en; + always @(redist10_expXmY_uid47_fpDivTest_q_13_rdmux_s or redist10_expXmY_uid47_fpDivTest_q_13_wraddr_q or redist10_expXmY_uid47_fpDivTest_q_13_rdcnt_q) + begin + unique case (redist10_expXmY_uid47_fpDivTest_q_13_rdmux_s) + 1'b0 : redist10_expXmY_uid47_fpDivTest_q_13_rdmux_q = redist10_expXmY_uid47_fpDivTest_q_13_wraddr_q; + 1'b1 : redist10_expXmY_uid47_fpDivTest_q_13_rdmux_q = redist10_expXmY_uid47_fpDivTest_q_13_rdcnt_q; + default : redist10_expXmY_uid47_fpDivTest_q_13_rdmux_q = 4'b0; + endcase + end + + // expXmY_uid47_fpDivTest(SUB,46)@0 + 1 + assign expXmY_uid47_fpDivTest_a = {1'b0, expX_uid9_fpDivTest_b}; + assign expXmY_uid47_fpDivTest_b = {1'b0, expY_uid12_fpDivTest_b}; + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + expXmY_uid47_fpDivTest_o <= 9'b0; + end + else if (en == 1'b1) + begin + expXmY_uid47_fpDivTest_o <= $unsigned(expXmY_uid47_fpDivTest_a) - $unsigned(expXmY_uid47_fpDivTest_b); + end + end + assign expXmY_uid47_fpDivTest_q = expXmY_uid47_fpDivTest_o[8:0]; + + // redist10_expXmY_uid47_fpDivTest_q_13_wraddr(REG,187) + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + redist10_expXmY_uid47_fpDivTest_q_13_wraddr_q <= 4'b1001; + end + else + begin + redist10_expXmY_uid47_fpDivTest_q_13_wraddr_q <= redist10_expXmY_uid47_fpDivTest_q_13_rdmux_q; + end + end + + // redist10_expXmY_uid47_fpDivTest_q_13_mem(DUALMEM,184) + assign redist10_expXmY_uid47_fpDivTest_q_13_mem_ia = expXmY_uid47_fpDivTest_q; + assign redist10_expXmY_uid47_fpDivTest_q_13_mem_aa = redist10_expXmY_uid47_fpDivTest_q_13_wraddr_q; + assign redist10_expXmY_uid47_fpDivTest_q_13_mem_ab = redist10_expXmY_uid47_fpDivTest_q_13_rdmux_q; + assign redist10_expXmY_uid47_fpDivTest_q_13_mem_reset0 = areset; + altera_syncram #( + .ram_block_type("MLAB"), + .operation_mode("DUAL_PORT"), + .width_a(9), + .widthad_a(4), + .numwords_a(10), + .width_b(9), + .widthad_b(4), + .numwords_b(10), + .lpm_type("altera_syncram"), + .width_byteena_a(1), + .address_reg_b("CLOCK0"), + .indata_reg_b("CLOCK0"), + .rdcontrol_reg_b("CLOCK0"), + .byteena_reg_b("CLOCK0"), + .outdata_reg_b("CLOCK1"), + .outdata_aclr_b("CLEAR1"), + .clock_enable_input_a("NORMAL"), + .clock_enable_input_b("NORMAL"), + .clock_enable_output_b("NORMAL"), + .read_during_write_mode_mixed_ports("DONT_CARE"), + .power_up_uninitialized("TRUE"), + .intended_device_family("Arria 10") + ) redist10_expXmY_uid47_fpDivTest_q_13_mem_dmem ( + .clocken1(redist10_expXmY_uid47_fpDivTest_q_13_enaAnd_q[0]), + .clocken0(VCC_q[0]), + .clock0(clk), + .aclr1(redist10_expXmY_uid47_fpDivTest_q_13_mem_reset0), + .clock1(clk), + .address_a(redist10_expXmY_uid47_fpDivTest_q_13_mem_aa), + .data_a(redist10_expXmY_uid47_fpDivTest_q_13_mem_ia), + .wren_a(en[0]), + .address_b(redist10_expXmY_uid47_fpDivTest_q_13_mem_ab), + .q_b(redist10_expXmY_uid47_fpDivTest_q_13_mem_iq), + .wren_b(), + .rden_a(), + .rden_b(), + .data_b(), + .clocken2(), + .clocken3(), + .aclr0(), + .addressstall_a(), + .addressstall_b(), + .byteena_a(), + .byteena_b(), + .eccencbypass(), + .eccencparity(), + .sclr(), + .address2_a(), + .address2_b(), + .q_a(), + .eccstatus() + ); + assign redist10_expXmY_uid47_fpDivTest_q_13_mem_q = redist10_expXmY_uid47_fpDivTest_q_13_mem_iq[8:0]; + + // redist10_expXmY_uid47_fpDivTest_q_13_outputreg(DELAY,183) + dspba_delay_ver #( .width(9), .depth(1), .reset_kind("ASYNC") ) + redist10_expXmY_uid47_fpDivTest_q_13_outputreg ( .xin(redist10_expXmY_uid47_fpDivTest_q_13_mem_q), .xout(redist10_expXmY_uid47_fpDivTest_q_13_outputreg_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // expR_uid48_fpDivTest(ADD,47)@13 + assign expR_uid48_fpDivTest_a = {{2{redist10_expXmY_uid47_fpDivTest_q_13_outputreg_q[8]}}, redist10_expXmY_uid47_fpDivTest_q_13_outputreg_q}; + assign expR_uid48_fpDivTest_b = {3'b000, cstBiasM1_uid6_fpDivTest_q}; + assign expR_uid48_fpDivTest_o = $signed(expR_uid48_fpDivTest_a) + $signed(expR_uid48_fpDivTest_b); + assign expR_uid48_fpDivTest_q = expR_uid48_fpDivTest_o[9:0]; + + // divValPreNormHigh_uid68_fpDivTest(BITSELECT,67)@13 + assign divValPreNormHigh_uid68_fpDivTest_in = divValPreNormTrunc_uid66_fpDivTest_q[24:0]; + assign divValPreNormHigh_uid68_fpDivTest_b = divValPreNormHigh_uid68_fpDivTest_in[24:1]; + + // divValPreNormLow_uid69_fpDivTest(BITSELECT,68)@13 + assign divValPreNormLow_uid69_fpDivTest_in = divValPreNormTrunc_uid66_fpDivTest_q[23:0]; + assign divValPreNormLow_uid69_fpDivTest_b = divValPreNormLow_uid69_fpDivTest_in[23:0]; + + // normFracRnd_uid70_fpDivTest(MUX,69)@13 + assign normFracRnd_uid70_fpDivTest_s = norm_uid67_fpDivTest_b; + always @(normFracRnd_uid70_fpDivTest_s or en or divValPreNormLow_uid69_fpDivTest_b or divValPreNormHigh_uid68_fpDivTest_b) + begin + unique case (normFracRnd_uid70_fpDivTest_s) + 1'b0 : normFracRnd_uid70_fpDivTest_q = divValPreNormLow_uid69_fpDivTest_b; + 1'b1 : normFracRnd_uid70_fpDivTest_q = divValPreNormHigh_uid68_fpDivTest_b; + default : normFracRnd_uid70_fpDivTest_q = 24'b0; + endcase + end + + // expFracRnd_uid71_fpDivTest(BITJOIN,70)@13 + assign expFracRnd_uid71_fpDivTest_q = {expR_uid48_fpDivTest_q, normFracRnd_uid70_fpDivTest_q}; + + // expFracPostRnd_uid76_fpDivTest(ADD,75)@13 + 1 + assign expFracPostRnd_uid76_fpDivTest_a = {{2{expFracRnd_uid71_fpDivTest_q[33]}}, expFracRnd_uid71_fpDivTest_q}; + assign expFracPostRnd_uid76_fpDivTest_b = {11'b00000000000, rndOp_uid75_fpDivTest_q}; + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + expFracPostRnd_uid76_fpDivTest_o <= 36'b0; + end + else if (en == 1'b1) + begin + expFracPostRnd_uid76_fpDivTest_o <= $signed(expFracPostRnd_uid76_fpDivTest_a) + $signed(expFracPostRnd_uid76_fpDivTest_b); + end + end + assign expFracPostRnd_uid76_fpDivTest_q = expFracPostRnd_uid76_fpDivTest_o[34:0]; + + // excRPreExc_uid79_fpDivTest(BITSELECT,78)@14 + assign excRPreExc_uid79_fpDivTest_in = expFracPostRnd_uid76_fpDivTest_q[31:0]; + assign excRPreExc_uid79_fpDivTest_b = excRPreExc_uid79_fpDivTest_in[31:24]; + + // redist2_excRPreExc_uid79_fpDivTest_b_1(DELAY,154) + dspba_delay_ver #( .width(8), .depth(1), .reset_kind("ASYNC") ) + redist2_excRPreExc_uid79_fpDivTest_b_1 ( .xin(excRPreExc_uid79_fpDivTest_b), .xout(redist2_excRPreExc_uid79_fpDivTest_b_1_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // invExpXIsMax_uid43_fpDivTest(LOGICAL,42)@14 + assign invExpXIsMax_uid43_fpDivTest_q = ~ (redist13_expXIsMax_uid38_fpDivTest_q_14_q); + + // InvExpXIsZero_uid44_fpDivTest(LOGICAL,43)@14 + assign InvExpXIsZero_uid44_fpDivTest_q = ~ (redist14_excZ_y_uid37_fpDivTest_q_14_q); + + // excR_y_uid45_fpDivTest(LOGICAL,44)@14 + assign excR_y_uid45_fpDivTest_q = InvExpXIsZero_uid44_fpDivTest_q & invExpXIsMax_uid43_fpDivTest_q; + + // excXIYR_uid93_fpDivTest(LOGICAL,92)@14 + assign excXIYR_uid93_fpDivTest_q = excI_x_uid27_fpDivTest_q & excR_y_uid45_fpDivTest_q; + + // excXIYZ_uid92_fpDivTest(LOGICAL,91)@14 + assign excXIYZ_uid92_fpDivTest_q = excI_x_uid27_fpDivTest_q & redist14_excZ_y_uid37_fpDivTest_q_14_q; + + // expRExt_uid80_fpDivTest(BITSELECT,79)@14 + assign expRExt_uid80_fpDivTest_b = expFracPostRnd_uid76_fpDivTest_q[34:24]; + + // expOvf_uid84_fpDivTest(COMPARE,83)@14 + assign expOvf_uid84_fpDivTest_a = {{2{expRExt_uid80_fpDivTest_b[10]}}, expRExt_uid80_fpDivTest_b}; + assign expOvf_uid84_fpDivTest_b = {5'b00000, cstAllOWE_uid18_fpDivTest_q}; + assign expOvf_uid84_fpDivTest_o = $signed(expOvf_uid84_fpDivTest_a) - $signed(expOvf_uid84_fpDivTest_b); + assign expOvf_uid84_fpDivTest_n[0] = ~ (expOvf_uid84_fpDivTest_o[12]); + + // invExpXIsMax_uid29_fpDivTest(LOGICAL,28)@14 + assign invExpXIsMax_uid29_fpDivTest_q = ~ (redist16_expXIsMax_uid24_fpDivTest_q_14_q); + + // InvExpXIsZero_uid30_fpDivTest(LOGICAL,29)@14 + assign InvExpXIsZero_uid30_fpDivTest_q = ~ (redist17_excZ_x_uid23_fpDivTest_q_14_q); + + // excR_x_uid31_fpDivTest(LOGICAL,30)@14 + assign excR_x_uid31_fpDivTest_q = InvExpXIsZero_uid30_fpDivTest_q & invExpXIsMax_uid29_fpDivTest_q; + + // excXRYROvf_uid91_fpDivTest(LOGICAL,90)@14 + assign excXRYROvf_uid91_fpDivTest_q = excR_x_uid31_fpDivTest_q & excR_y_uid45_fpDivTest_q & expOvf_uid84_fpDivTest_n; + + // excXRYZ_uid90_fpDivTest(LOGICAL,89)@14 + assign excXRYZ_uid90_fpDivTest_q = excR_x_uid31_fpDivTest_q & redist14_excZ_y_uid37_fpDivTest_q_14_q; + + // excRInf_uid94_fpDivTest(LOGICAL,93)@14 + assign excRInf_uid94_fpDivTest_q = excXRYZ_uid90_fpDivTest_q | excXRYROvf_uid91_fpDivTest_q | excXIYZ_uid92_fpDivTest_q | excXIYR_uid93_fpDivTest_q; + + // xRegOrZero_uid87_fpDivTest(LOGICAL,86)@14 + assign xRegOrZero_uid87_fpDivTest_q = excR_x_uid31_fpDivTest_q | redist17_excZ_x_uid23_fpDivTest_q_14_q; + + // regOrZeroOverInf_uid88_fpDivTest(LOGICAL,87)@14 + assign regOrZeroOverInf_uid88_fpDivTest_q = xRegOrZero_uid87_fpDivTest_q & excI_y_uid41_fpDivTest_q; + + // expUdf_uid81_fpDivTest(COMPARE,80)@14 + assign expUdf_uid81_fpDivTest_a = {12'b000000000000, GND_q}; + assign expUdf_uid81_fpDivTest_b = {{2{expRExt_uid80_fpDivTest_b[10]}}, expRExt_uid80_fpDivTest_b}; + assign expUdf_uid81_fpDivTest_o = $signed(expUdf_uid81_fpDivTest_a) - $signed(expUdf_uid81_fpDivTest_b); + assign expUdf_uid81_fpDivTest_n[0] = ~ (expUdf_uid81_fpDivTest_o[12]); + + // regOverRegWithUf_uid86_fpDivTest(LOGICAL,85)@14 + assign regOverRegWithUf_uid86_fpDivTest_q = expUdf_uid81_fpDivTest_n & excR_x_uid31_fpDivTest_q & excR_y_uid45_fpDivTest_q; + + // zeroOverReg_uid85_fpDivTest(LOGICAL,84)@14 + assign zeroOverReg_uid85_fpDivTest_q = redist17_excZ_x_uid23_fpDivTest_q_14_q & excR_y_uid45_fpDivTest_q; + + // excRZero_uid89_fpDivTest(LOGICAL,88)@14 + assign excRZero_uid89_fpDivTest_q = zeroOverReg_uid85_fpDivTest_q | regOverRegWithUf_uid86_fpDivTest_q | regOrZeroOverInf_uid88_fpDivTest_q; + + // concExc_uid98_fpDivTest(BITJOIN,97)@14 + assign concExc_uid98_fpDivTest_q = {excRNaN_uid97_fpDivTest_q, excRInf_uid94_fpDivTest_q, excRZero_uid89_fpDivTest_q}; + + // excREnc_uid99_fpDivTest(LOOKUP,98)@14 + 1 + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + excREnc_uid99_fpDivTest_q <= 2'b01; + end + else if (en == 1'b1) + begin + unique case (concExc_uid98_fpDivTest_q) + 3'b000 : excREnc_uid99_fpDivTest_q <= 2'b01; + 3'b001 : excREnc_uid99_fpDivTest_q <= 2'b00; + 3'b010 : excREnc_uid99_fpDivTest_q <= 2'b10; + 3'b011 : excREnc_uid99_fpDivTest_q <= 2'b00; + 3'b100 : excREnc_uid99_fpDivTest_q <= 2'b11; + 3'b101 : excREnc_uid99_fpDivTest_q <= 2'b00; + 3'b110 : excREnc_uid99_fpDivTest_q <= 2'b00; + 3'b111 : excREnc_uid99_fpDivTest_q <= 2'b00; + default : begin + // unreachable + excREnc_uid99_fpDivTest_q <= 2'bxx; + end + endcase + end + end + + // expRPostExc_uid107_fpDivTest(MUX,106)@15 + assign expRPostExc_uid107_fpDivTest_s = excREnc_uid99_fpDivTest_q; + always @(expRPostExc_uid107_fpDivTest_s or en or cstAllZWE_uid20_fpDivTest_q or redist2_excRPreExc_uid79_fpDivTest_b_1_q or cstAllOWE_uid18_fpDivTest_q) + begin + unique case (expRPostExc_uid107_fpDivTest_s) + 2'b00 : expRPostExc_uid107_fpDivTest_q = cstAllZWE_uid20_fpDivTest_q; + 2'b01 : expRPostExc_uid107_fpDivTest_q = redist2_excRPreExc_uid79_fpDivTest_b_1_q; + 2'b10 : expRPostExc_uid107_fpDivTest_q = cstAllOWE_uid18_fpDivTest_q; + 2'b11 : expRPostExc_uid107_fpDivTest_q = cstAllOWE_uid18_fpDivTest_q; + default : expRPostExc_uid107_fpDivTest_q = 8'b0; + endcase + end + + // oneFracRPostExc2_uid100_fpDivTest(CONSTANT,99) + assign oneFracRPostExc2_uid100_fpDivTest_q = 23'b00000000000000000000001; + + // fracRPreExc_uid78_fpDivTest(BITSELECT,77)@14 + assign fracRPreExc_uid78_fpDivTest_in = expFracPostRnd_uid76_fpDivTest_q[23:0]; + assign fracRPreExc_uid78_fpDivTest_b = fracRPreExc_uid78_fpDivTest_in[23:1]; + + // redist3_fracRPreExc_uid78_fpDivTest_b_1(DELAY,155) + dspba_delay_ver #( .width(23), .depth(1), .reset_kind("ASYNC") ) + redist3_fracRPreExc_uid78_fpDivTest_b_1 ( .xin(fracRPreExc_uid78_fpDivTest_b), .xout(redist3_fracRPreExc_uid78_fpDivTest_b_1_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // fracRPostExc_uid103_fpDivTest(MUX,102)@15 + assign fracRPostExc_uid103_fpDivTest_s = excREnc_uid99_fpDivTest_q; + always @(fracRPostExc_uid103_fpDivTest_s or en or paddingY_uid15_fpDivTest_q or redist3_fracRPreExc_uid78_fpDivTest_b_1_q or oneFracRPostExc2_uid100_fpDivTest_q) + begin + unique case (fracRPostExc_uid103_fpDivTest_s) + 2'b00 : fracRPostExc_uid103_fpDivTest_q = paddingY_uid15_fpDivTest_q; + 2'b01 : fracRPostExc_uid103_fpDivTest_q = redist3_fracRPreExc_uid78_fpDivTest_b_1_q; + 2'b10 : fracRPostExc_uid103_fpDivTest_q = paddingY_uid15_fpDivTest_q; + 2'b11 : fracRPostExc_uid103_fpDivTest_q = oneFracRPostExc2_uid100_fpDivTest_q; + default : fracRPostExc_uid103_fpDivTest_q = 23'b0; + endcase + end + + // divR_uid110_fpDivTest(BITJOIN,109)@15 + assign divR_uid110_fpDivTest_q = {sRPostExc_uid109_fpDivTest_q, expRPostExc_uid107_fpDivTest_q, fracRPostExc_uid103_fpDivTest_q}; + + // xOut(GPOUT,4)@15 + assign q = divR_uid110_fpDivTest_q; + +endmodule diff --git a/hw/rtl/fp_cores/altera/acl_fdiv_memoryC0_uid112_invTables_lutmem.hex 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+:0201E500011403 +:0201E600011303 +:0201E700011302 +:0201E800011400 +:0201E9000114FF +:0201EA00011002 +:0201EB00011100 +:0201EC00010F01 +:0201ED00010E01 +:0201EE00010D01 +:0201EF00010C01 +:0201F000010B01 +:0201F100010902 +:0201F200010BFF +:0201F300010801 +:0201F400010800 +:0201F500010601 +:0201F600010600 +:0201F7000107FE +:0201F8000105FF +:0201F900010300 +:0201FA00010200 +:0201FB000102FF +:0201FC000103FD +:0201FD000102FD +:0201FE000100FE +:0201FF000100FD +:00000001ff diff --git a/hw/rtl/fp_cores/altera/acl_fsqrt.sv b/hw/rtl/fp_cores/altera/acl_fsqrt.sv new file mode 100644 index 00000000..165effd6 --- /dev/null +++ b/hw/rtl/fp_cores/altera/acl_fsqrt.sv @@ -0,0 +1,1128 @@ +// ------------------------------------------------------------------------- +// High Level Design Compiler for Intel(R) FPGAs Version 17.1 (Release Build #273) +// Quartus Prime development tool and MATLAB/Simulink Interface +// +// Legal Notice: Copyright 2017 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly +// subject to the terms and conditions of the Intel FPGA Software License +// Agreement, Intel MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for +// the sole purpose of programming logic devices manufactured by Intel +// and sold by Intel or its authorized distributors. Please refer to the +// applicable agreement for further details. +// --------------------------------------------------------------------------- + +// SystemVerilog created from acl_fsqrt +// SystemVerilog created on Wed Sep 2 07:11:09 2020 + + +(* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007; -name MESSAGE_DISABLE 10958" *) +module acl_fsqrt ( + input wire [31:0] a, + input wire [0:0] en, + output wire [31:0] q, + input wire clk, + input wire areset + ); + + wire [0:0] GND_q; + wire [0:0] VCC_q; + wire [7:0] expX_uid6_fpSqrtTest_b; + wire [0:0] signX_uid7_fpSqrtTest_b; + wire [7:0] cstAllOWE_uid8_fpSqrtTest_q; + wire [22:0] cstZeroWF_uid9_fpSqrtTest_q; + wire [7:0] cstAllZWE_uid10_fpSqrtTest_q; + wire [22:0] frac_x_uid12_fpSqrtTest_b; + wire [0:0] excZ_x_uid13_fpSqrtTest_qi; + reg [0:0] excZ_x_uid13_fpSqrtTest_q; + wire [0:0] expXIsMax_uid14_fpSqrtTest_qi; + reg [0:0] expXIsMax_uid14_fpSqrtTest_q; + wire [0:0] fracXIsZero_uid15_fpSqrtTest_qi; + reg [0:0] fracXIsZero_uid15_fpSqrtTest_q; + wire [0:0] fracXIsNotZero_uid16_fpSqrtTest_q; + wire [0:0] excI_x_uid17_fpSqrtTest_q; + wire [0:0] excN_x_uid18_fpSqrtTest_q; + wire [0:0] invExpXIsMax_uid19_fpSqrtTest_q; + wire [0:0] InvExpXIsZero_uid20_fpSqrtTest_q; + wire [0:0] excR_x_uid21_fpSqrtTest_q; + wire [7:0] sBias_uid22_fpSqrtTest_q; + wire [8:0] expEvenSig_uid24_fpSqrtTest_a; + wire [8:0] expEvenSig_uid24_fpSqrtTest_b; + logic [8:0] expEvenSig_uid24_fpSqrtTest_o; + wire [8:0] expEvenSig_uid24_fpSqrtTest_q; + wire [7:0] expREven_uid25_fpSqrtTest_b; + wire [7:0] sBiasM1_uid26_fpSqrtTest_q; + wire [8:0] expOddSig_uid27_fpSqrtTest_a; + wire [8:0] expOddSig_uid27_fpSqrtTest_b; + logic [8:0] expOddSig_uid27_fpSqrtTest_o; + wire [8:0] expOddSig_uid27_fpSqrtTest_q; + wire [7:0] expROdd_uid28_fpSqrtTest_b; + wire [0:0] expX0PS_uid29_fpSqrtTest_in; + wire [0:0] expX0PS_uid29_fpSqrtTest_b; + wire [0:0] expOddSelect_uid30_fpSqrtTest_q; + wire [0:0] expRMux_uid31_fpSqrtTest_s; + reg [7:0] expRMux_uid31_fpSqrtTest_q; + wire [23:0] addrFull_uid33_fpSqrtTest_q; + wire [7:0] yAddr_uid35_fpSqrtTest_b; + wire [15:0] yForPe_uid36_fpSqrtTest_in; + wire [15:0] yForPe_uid36_fpSqrtTest_b; + wire [30:0] expInc_uid38_fpSqrtTest_in; + wire [0:0] expInc_uid38_fpSqrtTest_b; + wire [28:0] fracRPostProcessings_uid39_fpSqrtTest_in; + wire [22:0] fracRPostProcessings_uid39_fpSqrtTest_b; + wire [8:0] expR_uid40_fpSqrtTest_a; + wire [8:0] expR_uid40_fpSqrtTest_b; + logic [8:0] expR_uid40_fpSqrtTest_o; + wire [8:0] expR_uid40_fpSqrtTest_q; + wire [0:0] invSignX_uid41_fpSqrtTest_q; + wire [0:0] inInfAndNotNeg_uid42_fpSqrtTest_q; + wire [0:0] minReg_uid43_fpSqrtTest_q; + wire [0:0] minInf_uid44_fpSqrtTest_q; + wire [0:0] excRNaN_uid45_fpSqrtTest_q; + wire [2:0] excConc_uid46_fpSqrtTest_q; + wire [3:0] fracSelIn_uid47_fpSqrtTest_q; + reg [1:0] fracSel_uid48_fpSqrtTest_q; + wire [7:0] expRR_uid51_fpSqrtTest_in; + wire [7:0] expRR_uid51_fpSqrtTest_b; + wire [1:0] expRPostExc_uid53_fpSqrtTest_s; + reg [7:0] expRPostExc_uid53_fpSqrtTest_q; + wire [22:0] fracNaN_uid54_fpSqrtTest_q; + wire [1:0] fracRPostExc_uid58_fpSqrtTest_s; + reg [22:0] fracRPostExc_uid58_fpSqrtTest_q; + wire [0:0] negZero_uid59_fpSqrtTest_qi; + reg [0:0] negZero_uid59_fpSqrtTest_q; + wire [31:0] RSqrt_uid60_fpSqrtTest_q; + wire [11:0] yT1_uid74_invPolyEval_b; + wire [0:0] lowRangeB_uid76_invPolyEval_in; + wire [0:0] lowRangeB_uid76_invPolyEval_b; + wire [11:0] highBBits_uid77_invPolyEval_b; + wire [21:0] s1sumAHighB_uid78_invPolyEval_a; + wire [21:0] s1sumAHighB_uid78_invPolyEval_b; + logic [21:0] s1sumAHighB_uid78_invPolyEval_o; + wire [21:0] s1sumAHighB_uid78_invPolyEval_q; + wire [22:0] s1_uid79_invPolyEval_q; + wire [1:0] lowRangeB_uid82_invPolyEval_in; + wire [1:0] lowRangeB_uid82_invPolyEval_b; + wire [21:0] highBBits_uid83_invPolyEval_b; + wire [29:0] s2sumAHighB_uid84_invPolyEval_a; + wire [29:0] s2sumAHighB_uid84_invPolyEval_b; + logic [29:0] s2sumAHighB_uid84_invPolyEval_o; + wire [29:0] s2sumAHighB_uid84_invPolyEval_q; + wire [31:0] s2_uid85_invPolyEval_q; + wire [12:0] osig_uid88_pT1_uid75_invPolyEval_b; + wire [23:0] osig_uid91_pT2_uid81_invPolyEval_b; + wire memoryC0_uid62_sqrtTables_lutmem_reset0; + wire [28:0] memoryC0_uid62_sqrtTables_lutmem_ia; + wire [7:0] memoryC0_uid62_sqrtTables_lutmem_aa; + wire [7:0] memoryC0_uid62_sqrtTables_lutmem_ab; + wire [28:0] memoryC0_uid62_sqrtTables_lutmem_ir; + wire [28:0] memoryC0_uid62_sqrtTables_lutmem_r; + wire memoryC1_uid65_sqrtTables_lutmem_reset0; + wire [20:0] memoryC1_uid65_sqrtTables_lutmem_ia; + wire [7:0] memoryC1_uid65_sqrtTables_lutmem_aa; + wire [7:0] memoryC1_uid65_sqrtTables_lutmem_ab; + wire [20:0] memoryC1_uid65_sqrtTables_lutmem_ir; + wire [20:0] memoryC1_uid65_sqrtTables_lutmem_r; + wire memoryC2_uid68_sqrtTables_lutmem_reset0; + wire [11:0] memoryC2_uid68_sqrtTables_lutmem_ia; + wire [7:0] memoryC2_uid68_sqrtTables_lutmem_aa; + wire [7:0] memoryC2_uid68_sqrtTables_lutmem_ab; + wire [11:0] memoryC2_uid68_sqrtTables_lutmem_ir; + wire [11:0] memoryC2_uid68_sqrtTables_lutmem_r; + wire prodXY_uid87_pT1_uid75_invPolyEval_cma_reset; + (* preserve, altera_attribute = "-name allow_synch_ctrl_usage off" *) reg [11:0] prodXY_uid87_pT1_uid75_invPolyEval_cma_a0 [0:0]; + (* preserve, altera_attribute = "-name allow_synch_ctrl_usage off" *) reg [11:0] prodXY_uid87_pT1_uid75_invPolyEval_cma_a1 [0:0]; + (* preserve, altera_attribute = "-name allow_synch_ctrl_usage off" *) reg signed [11:0] prodXY_uid87_pT1_uid75_invPolyEval_cma_c0 [0:0]; + (* preserve, altera_attribute = "-name allow_synch_ctrl_usage off" *) reg signed [11:0] prodXY_uid87_pT1_uid75_invPolyEval_cma_c1 [0:0]; + wire signed [12:0] prodXY_uid87_pT1_uid75_invPolyEval_cma_l [0:0]; + wire signed [24:0] prodXY_uid87_pT1_uid75_invPolyEval_cma_p [0:0]; + wire signed [24:0] prodXY_uid87_pT1_uid75_invPolyEval_cma_u [0:0]; + wire signed [24:0] prodXY_uid87_pT1_uid75_invPolyEval_cma_w [0:0]; + wire signed [24:0] prodXY_uid87_pT1_uid75_invPolyEval_cma_x [0:0]; + wire signed [24:0] prodXY_uid87_pT1_uid75_invPolyEval_cma_y [0:0]; + reg signed [24:0] prodXY_uid87_pT1_uid75_invPolyEval_cma_s [0:0]; + wire [23:0] prodXY_uid87_pT1_uid75_invPolyEval_cma_qq; + wire [23:0] prodXY_uid87_pT1_uid75_invPolyEval_cma_q; + wire prodXY_uid87_pT1_uid75_invPolyEval_cma_ena0; + wire prodXY_uid87_pT1_uid75_invPolyEval_cma_ena1; + wire prodXY_uid87_pT1_uid75_invPolyEval_cma_ena2; + wire prodXY_uid90_pT2_uid81_invPolyEval_cma_reset; + (* preserve, altera_attribute = "-name allow_synch_ctrl_usage off" *) reg [15:0] prodXY_uid90_pT2_uid81_invPolyEval_cma_a0 [0:0]; + (* preserve, altera_attribute = "-name allow_synch_ctrl_usage off" *) reg [15:0] prodXY_uid90_pT2_uid81_invPolyEval_cma_a1 [0:0]; + (* preserve, altera_attribute = "-name allow_synch_ctrl_usage off" *) reg signed [22:0] prodXY_uid90_pT2_uid81_invPolyEval_cma_c0 [0:0]; + (* preserve, altera_attribute = "-name allow_synch_ctrl_usage off" *) reg signed [22:0] prodXY_uid90_pT2_uid81_invPolyEval_cma_c1 [0:0]; + wire signed [16:0] prodXY_uid90_pT2_uid81_invPolyEval_cma_l [0:0]; + wire signed [39:0] prodXY_uid90_pT2_uid81_invPolyEval_cma_p [0:0]; + wire signed [39:0] prodXY_uid90_pT2_uid81_invPolyEval_cma_u [0:0]; + wire signed [39:0] prodXY_uid90_pT2_uid81_invPolyEval_cma_w [0:0]; + wire signed [39:0] prodXY_uid90_pT2_uid81_invPolyEval_cma_x [0:0]; + wire signed [39:0] prodXY_uid90_pT2_uid81_invPolyEval_cma_y [0:0]; + reg signed [39:0] prodXY_uid90_pT2_uid81_invPolyEval_cma_s [0:0]; + wire [38:0] prodXY_uid90_pT2_uid81_invPolyEval_cma_qq; + wire [38:0] prodXY_uid90_pT2_uid81_invPolyEval_cma_q; + wire prodXY_uid90_pT2_uid81_invPolyEval_cma_ena0; + wire prodXY_uid90_pT2_uid81_invPolyEval_cma_ena1; + wire prodXY_uid90_pT2_uid81_invPolyEval_cma_ena2; + reg [0:0] redist0_lowRangeB_uid76_invPolyEval_b_1_q; + reg [0:0] redist1_negZero_uid59_fpSqrtTest_q_9_q; + reg [1:0] redist2_fracSel_uid48_fpSqrtTest_q_9_q; + reg [22:0] redist3_fracRPostProcessings_uid39_fpSqrtTest_b_1_q; + reg [0:0] redist4_expInc_uid38_fpSqrtTest_b_1_q; + reg [15:0] redist5_yForPe_uid36_fpSqrtTest_b_2_q; + reg [7:0] redist7_yAddr_uid35_fpSqrtTest_b_3_q; + reg [7:0] redist8_yAddr_uid35_fpSqrtTest_b_7_q; + reg [0:0] redist10_signX_uid7_fpSqrtTest_b_1_q; + wire redist6_yForPe_uid36_fpSqrtTest_b_6_mem_reset0; + wire [15:0] redist6_yForPe_uid36_fpSqrtTest_b_6_mem_ia; + wire [1:0] redist6_yForPe_uid36_fpSqrtTest_b_6_mem_aa; + wire [1:0] redist6_yForPe_uid36_fpSqrtTest_b_6_mem_ab; + wire [15:0] redist6_yForPe_uid36_fpSqrtTest_b_6_mem_iq; + wire [15:0] redist6_yForPe_uid36_fpSqrtTest_b_6_mem_q; + wire [1:0] redist6_yForPe_uid36_fpSqrtTest_b_6_rdcnt_q; + (* preserve *) reg [1:0] redist6_yForPe_uid36_fpSqrtTest_b_6_rdcnt_i; + (* preserve *) reg redist6_yForPe_uid36_fpSqrtTest_b_6_rdcnt_eq; + wire [0:0] redist6_yForPe_uid36_fpSqrtTest_b_6_rdmux_s; + reg [1:0] redist6_yForPe_uid36_fpSqrtTest_b_6_rdmux_q; + reg [1:0] redist6_yForPe_uid36_fpSqrtTest_b_6_wraddr_q; + wire [1:0] redist6_yForPe_uid36_fpSqrtTest_b_6_mem_last_q; + wire [0:0] redist6_yForPe_uid36_fpSqrtTest_b_6_cmp_q; + reg [0:0] redist6_yForPe_uid36_fpSqrtTest_b_6_cmpReg_q; + wire [0:0] redist6_yForPe_uid36_fpSqrtTest_b_6_notEnable_q; + wire [0:0] redist6_yForPe_uid36_fpSqrtTest_b_6_nor_q; + (* preserve_syn_only *) reg [0:0] redist6_yForPe_uid36_fpSqrtTest_b_6_sticky_ena_q; + wire [0:0] redist6_yForPe_uid36_fpSqrtTest_b_6_enaAnd_q; + reg [7:0] redist9_expRMux_uid31_fpSqrtTest_q_10_outputreg_q; + wire redist9_expRMux_uid31_fpSqrtTest_q_10_mem_reset0; + wire [7:0] redist9_expRMux_uid31_fpSqrtTest_q_10_mem_ia; + wire [2:0] redist9_expRMux_uid31_fpSqrtTest_q_10_mem_aa; + wire [2:0] redist9_expRMux_uid31_fpSqrtTest_q_10_mem_ab; + wire [7:0] redist9_expRMux_uid31_fpSqrtTest_q_10_mem_iq; + wire [7:0] redist9_expRMux_uid31_fpSqrtTest_q_10_mem_q; + wire [2:0] redist9_expRMux_uid31_fpSqrtTest_q_10_rdcnt_q; + (* preserve *) reg [2:0] redist9_expRMux_uid31_fpSqrtTest_q_10_rdcnt_i; + (* preserve *) reg redist9_expRMux_uid31_fpSqrtTest_q_10_rdcnt_eq; + wire [0:0] redist9_expRMux_uid31_fpSqrtTest_q_10_rdmux_s; + reg [2:0] redist9_expRMux_uid31_fpSqrtTest_q_10_rdmux_q; + reg [2:0] redist9_expRMux_uid31_fpSqrtTest_q_10_wraddr_q; + wire [3:0] redist9_expRMux_uid31_fpSqrtTest_q_10_mem_last_q; + wire [3:0] redist9_expRMux_uid31_fpSqrtTest_q_10_cmp_b; + wire [0:0] redist9_expRMux_uid31_fpSqrtTest_q_10_cmp_q; + reg [0:0] redist9_expRMux_uid31_fpSqrtTest_q_10_cmpReg_q; + wire [0:0] redist9_expRMux_uid31_fpSqrtTest_q_10_notEnable_q; + wire [0:0] redist9_expRMux_uid31_fpSqrtTest_q_10_nor_q; + (* preserve_syn_only *) reg [0:0] redist9_expRMux_uid31_fpSqrtTest_q_10_sticky_ena_q; + wire [0:0] redist9_expRMux_uid31_fpSqrtTest_q_10_enaAnd_q; + + + // signX_uid7_fpSqrtTest(BITSELECT,6)@0 + assign signX_uid7_fpSqrtTest_b = a[31:31]; + + // redist10_signX_uid7_fpSqrtTest_b_1(DELAY,107) + dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) + redist10_signX_uid7_fpSqrtTest_b_1 ( .xin(signX_uid7_fpSqrtTest_b), .xout(redist10_signX_uid7_fpSqrtTest_b_1_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // cstAllZWE_uid10_fpSqrtTest(CONSTANT,9) + assign cstAllZWE_uid10_fpSqrtTest_q = 8'b00000000; + + // expX_uid6_fpSqrtTest(BITSELECT,5)@0 + assign expX_uid6_fpSqrtTest_b = a[30:23]; + + // excZ_x_uid13_fpSqrtTest(LOGICAL,12)@0 + 1 + assign excZ_x_uid13_fpSqrtTest_qi = expX_uid6_fpSqrtTest_b == cstAllZWE_uid10_fpSqrtTest_q ? 1'b1 : 1'b0; + dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) + excZ_x_uid13_fpSqrtTest_delay ( .xin(excZ_x_uid13_fpSqrtTest_qi), .xout(excZ_x_uid13_fpSqrtTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // negZero_uid59_fpSqrtTest(LOGICAL,58)@1 + 1 + assign negZero_uid59_fpSqrtTest_qi = excZ_x_uid13_fpSqrtTest_q & redist10_signX_uid7_fpSqrtTest_b_1_q; + dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) + negZero_uid59_fpSqrtTest_delay ( .xin(negZero_uid59_fpSqrtTest_qi), .xout(negZero_uid59_fpSqrtTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // redist1_negZero_uid59_fpSqrtTest_q_9(DELAY,98) + dspba_delay_ver #( .width(1), .depth(8), .reset_kind("ASYNC") ) + redist1_negZero_uid59_fpSqrtTest_q_9 ( .xin(negZero_uid59_fpSqrtTest_q), .xout(redist1_negZero_uid59_fpSqrtTest_q_9_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // cstAllOWE_uid8_fpSqrtTest(CONSTANT,7) + assign cstAllOWE_uid8_fpSqrtTest_q = 8'b11111111; + + // expX0PS_uid29_fpSqrtTest(BITSELECT,28)@0 + assign expX0PS_uid29_fpSqrtTest_in = expX_uid6_fpSqrtTest_b[0:0]; + assign expX0PS_uid29_fpSqrtTest_b = expX0PS_uid29_fpSqrtTest_in[0:0]; + + // expOddSelect_uid30_fpSqrtTest(LOGICAL,29)@0 + assign expOddSelect_uid30_fpSqrtTest_q = ~ (expX0PS_uid29_fpSqrtTest_b); + + // frac_x_uid12_fpSqrtTest(BITSELECT,11)@0 + assign frac_x_uid12_fpSqrtTest_b = a[22:0]; + + // addrFull_uid33_fpSqrtTest(BITJOIN,32)@0 + assign addrFull_uid33_fpSqrtTest_q = {expOddSelect_uid30_fpSqrtTest_q, frac_x_uid12_fpSqrtTest_b}; + + // yAddr_uid35_fpSqrtTest(BITSELECT,34)@0 + assign yAddr_uid35_fpSqrtTest_b = addrFull_uid33_fpSqrtTest_q[23:16]; + + // memoryC2_uid68_sqrtTables_lutmem(DUALMEM,94)@0 + 2 + // in j@20000000 + assign memoryC2_uid68_sqrtTables_lutmem_aa = yAddr_uid35_fpSqrtTest_b; + assign memoryC2_uid68_sqrtTables_lutmem_reset0 = areset; + altera_syncram #( + .ram_block_type("M20K"), + .operation_mode("ROM"), + .width_a(12), + .widthad_a(8), + .numwords_a(256), + .lpm_type("altera_syncram"), + .width_byteena_a(1), + .outdata_reg_a("CLOCK0"), + .outdata_aclr_a("CLEAR0"), + .clock_enable_input_a("NORMAL"), + .power_up_uninitialized("FALSE"), + .init_file("acl_fsqrt_memoryC2_uid68_sqrtTables_lutmem.hex"), + .init_file_layout("PORT_A"), + .intended_device_family("Arria 10") + ) memoryC2_uid68_sqrtTables_lutmem_dmem ( + .clocken0(en[0]), + .aclr0(memoryC2_uid68_sqrtTables_lutmem_reset0), + .clock0(clk), + .address_a(memoryC2_uid68_sqrtTables_lutmem_aa), + .q_a(memoryC2_uid68_sqrtTables_lutmem_ir), + .wren_a(), + .wren_b(), + .rden_a(), + .rden_b(), + .data_a(), + .data_b(), + .address_b(), + .clock1(), + .clocken1(), + .clocken2(), + .clocken3(), + .aclr1(), + .addressstall_a(), + .addressstall_b(), + .byteena_a(), + .byteena_b(), + .eccencbypass(), + .eccencparity(), + .sclr(), + .address2_a(), + .address2_b(), + .q_b(), + .eccstatus() + ); + assign memoryC2_uid68_sqrtTables_lutmem_r = memoryC2_uid68_sqrtTables_lutmem_ir[11:0]; + + // yForPe_uid36_fpSqrtTest(BITSELECT,35)@0 + assign yForPe_uid36_fpSqrtTest_in = frac_x_uid12_fpSqrtTest_b[15:0]; + assign yForPe_uid36_fpSqrtTest_b = yForPe_uid36_fpSqrtTest_in[15:0]; + + // redist5_yForPe_uid36_fpSqrtTest_b_2(DELAY,102) + dspba_delay_ver #( .width(16), .depth(2), .reset_kind("ASYNC") ) + redist5_yForPe_uid36_fpSqrtTest_b_2 ( .xin(yForPe_uid36_fpSqrtTest_b), .xout(redist5_yForPe_uid36_fpSqrtTest_b_2_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // yT1_uid74_invPolyEval(BITSELECT,73)@2 + assign yT1_uid74_invPolyEval_b = redist5_yForPe_uid36_fpSqrtTest_b_2_q[15:4]; + + // prodXY_uid87_pT1_uid75_invPolyEval_cma(CHAINMULTADD,95)@2 + 3 + assign prodXY_uid87_pT1_uid75_invPolyEval_cma_reset = areset; + assign prodXY_uid87_pT1_uid75_invPolyEval_cma_ena0 = en[0]; + assign prodXY_uid87_pT1_uid75_invPolyEval_cma_ena1 = prodXY_uid87_pT1_uid75_invPolyEval_cma_ena0; + assign prodXY_uid87_pT1_uid75_invPolyEval_cma_ena2 = prodXY_uid87_pT1_uid75_invPolyEval_cma_ena0; + assign prodXY_uid87_pT1_uid75_invPolyEval_cma_l[0] = $signed({1'b0, prodXY_uid87_pT1_uid75_invPolyEval_cma_a1[0][11:0]}); + assign prodXY_uid87_pT1_uid75_invPolyEval_cma_p[0] = prodXY_uid87_pT1_uid75_invPolyEval_cma_l[0] * prodXY_uid87_pT1_uid75_invPolyEval_cma_c1[0]; + assign prodXY_uid87_pT1_uid75_invPolyEval_cma_u[0] = prodXY_uid87_pT1_uid75_invPolyEval_cma_p[0][24:0]; + assign prodXY_uid87_pT1_uid75_invPolyEval_cma_w[0] = prodXY_uid87_pT1_uid75_invPolyEval_cma_u[0]; + assign prodXY_uid87_pT1_uid75_invPolyEval_cma_x[0] = prodXY_uid87_pT1_uid75_invPolyEval_cma_w[0]; + assign prodXY_uid87_pT1_uid75_invPolyEval_cma_y[0] = prodXY_uid87_pT1_uid75_invPolyEval_cma_x[0]; + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + prodXY_uid87_pT1_uid75_invPolyEval_cma_a0 <= '{default: '0}; + prodXY_uid87_pT1_uid75_invPolyEval_cma_c0 <= '{default: '0}; + end + else + begin + if (prodXY_uid87_pT1_uid75_invPolyEval_cma_ena0 == 1'b1) + begin + prodXY_uid87_pT1_uid75_invPolyEval_cma_a0[0] <= yT1_uid74_invPolyEval_b; + prodXY_uid87_pT1_uid75_invPolyEval_cma_c0[0] <= memoryC2_uid68_sqrtTables_lutmem_r; + end + end + end + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + prodXY_uid87_pT1_uid75_invPolyEval_cma_a1 <= '{default: '0}; + prodXY_uid87_pT1_uid75_invPolyEval_cma_c1 <= '{default: '0}; + end + else + begin + if (prodXY_uid87_pT1_uid75_invPolyEval_cma_ena2 == 1'b1) + begin + prodXY_uid87_pT1_uid75_invPolyEval_cma_a1 <= prodXY_uid87_pT1_uid75_invPolyEval_cma_a0; + prodXY_uid87_pT1_uid75_invPolyEval_cma_c1 <= prodXY_uid87_pT1_uid75_invPolyEval_cma_c0; + end + end + end + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + prodXY_uid87_pT1_uid75_invPolyEval_cma_s <= '{default: '0}; + end + else + begin + if (prodXY_uid87_pT1_uid75_invPolyEval_cma_ena1 == 1'b1) + begin + prodXY_uid87_pT1_uid75_invPolyEval_cma_s[0] <= prodXY_uid87_pT1_uid75_invPolyEval_cma_y[0]; + end + end + end + dspba_delay_ver #( .width(24), .depth(0), .reset_kind("ASYNC") ) + prodXY_uid87_pT1_uid75_invPolyEval_cma_delay ( .xin(prodXY_uid87_pT1_uid75_invPolyEval_cma_s[0][23:0]), .xout(prodXY_uid87_pT1_uid75_invPolyEval_cma_qq), .ena(en[0]), .clk(clk), .aclr(areset) ); + assign prodXY_uid87_pT1_uid75_invPolyEval_cma_q = prodXY_uid87_pT1_uid75_invPolyEval_cma_qq[23:0]; + + // osig_uid88_pT1_uid75_invPolyEval(BITSELECT,87)@5 + assign osig_uid88_pT1_uid75_invPolyEval_b = prodXY_uid87_pT1_uid75_invPolyEval_cma_q[23:11]; + + // highBBits_uid77_invPolyEval(BITSELECT,76)@5 + assign highBBits_uid77_invPolyEval_b = osig_uid88_pT1_uid75_invPolyEval_b[12:1]; + + // redist7_yAddr_uid35_fpSqrtTest_b_3(DELAY,104) + dspba_delay_ver #( .width(8), .depth(3), .reset_kind("ASYNC") ) + redist7_yAddr_uid35_fpSqrtTest_b_3 ( .xin(yAddr_uid35_fpSqrtTest_b), .xout(redist7_yAddr_uid35_fpSqrtTest_b_3_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // memoryC1_uid65_sqrtTables_lutmem(DUALMEM,93)@3 + 2 + // in j@20000000 + assign memoryC1_uid65_sqrtTables_lutmem_aa = redist7_yAddr_uid35_fpSqrtTest_b_3_q; + assign memoryC1_uid65_sqrtTables_lutmem_reset0 = areset; + altera_syncram #( + .ram_block_type("M20K"), + .operation_mode("ROM"), + .width_a(21), + .widthad_a(8), + .numwords_a(256), + .lpm_type("altera_syncram"), + .width_byteena_a(1), + .outdata_reg_a("CLOCK0"), + .outdata_aclr_a("CLEAR0"), + .clock_enable_input_a("NORMAL"), + .power_up_uninitialized("FALSE"), + .init_file("acl_fsqrt_memoryC1_uid65_sqrtTables_lutmem.hex"), + .init_file_layout("PORT_A"), + .intended_device_family("Arria 10") + ) memoryC1_uid65_sqrtTables_lutmem_dmem ( + .clocken0(en[0]), + .aclr0(memoryC1_uid65_sqrtTables_lutmem_reset0), + .clock0(clk), + .address_a(memoryC1_uid65_sqrtTables_lutmem_aa), + .q_a(memoryC1_uid65_sqrtTables_lutmem_ir), + .wren_a(), + .wren_b(), + .rden_a(), + .rden_b(), + .data_a(), + .data_b(), + .address_b(), + .clock1(), + .clocken1(), + .clocken2(), + .clocken3(), + .aclr1(), + .addressstall_a(), + .addressstall_b(), + .byteena_a(), + .byteena_b(), + .eccencbypass(), + .eccencparity(), + .sclr(), + .address2_a(), + .address2_b(), + .q_b(), + .eccstatus() + ); + assign memoryC1_uid65_sqrtTables_lutmem_r = memoryC1_uid65_sqrtTables_lutmem_ir[20:0]; + + // s1sumAHighB_uid78_invPolyEval(ADD,77)@5 + 1 + assign s1sumAHighB_uid78_invPolyEval_a = {{1{memoryC1_uid65_sqrtTables_lutmem_r[20]}}, memoryC1_uid65_sqrtTables_lutmem_r}; + assign s1sumAHighB_uid78_invPolyEval_b = {{10{highBBits_uid77_invPolyEval_b[11]}}, highBBits_uid77_invPolyEval_b}; + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + s1sumAHighB_uid78_invPolyEval_o <= 22'b0; + end + else if (en == 1'b1) + begin + s1sumAHighB_uid78_invPolyEval_o <= $signed(s1sumAHighB_uid78_invPolyEval_a) + $signed(s1sumAHighB_uid78_invPolyEval_b); + end + end + assign s1sumAHighB_uid78_invPolyEval_q = s1sumAHighB_uid78_invPolyEval_o[21:0]; + + // lowRangeB_uid76_invPolyEval(BITSELECT,75)@5 + assign lowRangeB_uid76_invPolyEval_in = osig_uid88_pT1_uid75_invPolyEval_b[0:0]; + assign lowRangeB_uid76_invPolyEval_b = lowRangeB_uid76_invPolyEval_in[0:0]; + + // redist0_lowRangeB_uid76_invPolyEval_b_1(DELAY,97) + dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) + redist0_lowRangeB_uid76_invPolyEval_b_1 ( .xin(lowRangeB_uid76_invPolyEval_b), .xout(redist0_lowRangeB_uid76_invPolyEval_b_1_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // s1_uid79_invPolyEval(BITJOIN,78)@6 + assign s1_uid79_invPolyEval_q = {s1sumAHighB_uid78_invPolyEval_q, redist0_lowRangeB_uid76_invPolyEval_b_1_q}; + + // redist6_yForPe_uid36_fpSqrtTest_b_6_notEnable(LOGICAL,115) + assign redist6_yForPe_uid36_fpSqrtTest_b_6_notEnable_q = ~ (en); + + // redist6_yForPe_uid36_fpSqrtTest_b_6_nor(LOGICAL,116) + assign redist6_yForPe_uid36_fpSqrtTest_b_6_nor_q = ~ (redist6_yForPe_uid36_fpSqrtTest_b_6_notEnable_q | redist6_yForPe_uid36_fpSqrtTest_b_6_sticky_ena_q); + + // redist6_yForPe_uid36_fpSqrtTest_b_6_mem_last(CONSTANT,112) + assign redist6_yForPe_uid36_fpSqrtTest_b_6_mem_last_q = 2'b01; + + // redist6_yForPe_uid36_fpSqrtTest_b_6_cmp(LOGICAL,113) + assign redist6_yForPe_uid36_fpSqrtTest_b_6_cmp_q = redist6_yForPe_uid36_fpSqrtTest_b_6_mem_last_q == redist6_yForPe_uid36_fpSqrtTest_b_6_rdmux_q ? 1'b1 : 1'b0; + + // redist6_yForPe_uid36_fpSqrtTest_b_6_cmpReg(REG,114) + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + redist6_yForPe_uid36_fpSqrtTest_b_6_cmpReg_q <= 1'b0; + end + else if (en == 1'b1) + begin + redist6_yForPe_uid36_fpSqrtTest_b_6_cmpReg_q <= redist6_yForPe_uid36_fpSqrtTest_b_6_cmp_q; + end + end + + // redist6_yForPe_uid36_fpSqrtTest_b_6_sticky_ena(REG,117) + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + redist6_yForPe_uid36_fpSqrtTest_b_6_sticky_ena_q <= 1'b0; + end + else if (redist6_yForPe_uid36_fpSqrtTest_b_6_nor_q == 1'b1) + begin + redist6_yForPe_uid36_fpSqrtTest_b_6_sticky_ena_q <= redist6_yForPe_uid36_fpSqrtTest_b_6_cmpReg_q; + end + end + + // redist6_yForPe_uid36_fpSqrtTest_b_6_enaAnd(LOGICAL,118) + assign redist6_yForPe_uid36_fpSqrtTest_b_6_enaAnd_q = redist6_yForPe_uid36_fpSqrtTest_b_6_sticky_ena_q & en; + + // redist6_yForPe_uid36_fpSqrtTest_b_6_rdcnt(COUNTER,109) + // low=0, high=2, step=1, init=0 + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + redist6_yForPe_uid36_fpSqrtTest_b_6_rdcnt_i <= 2'd0; + redist6_yForPe_uid36_fpSqrtTest_b_6_rdcnt_eq <= 1'b0; + end + else if (en == 1'b1) + begin + if (redist6_yForPe_uid36_fpSqrtTest_b_6_rdcnt_i == 2'd1) + begin + redist6_yForPe_uid36_fpSqrtTest_b_6_rdcnt_eq <= 1'b1; + end + else + begin + redist6_yForPe_uid36_fpSqrtTest_b_6_rdcnt_eq <= 1'b0; + end + if (redist6_yForPe_uid36_fpSqrtTest_b_6_rdcnt_eq == 1'b1) + begin + redist6_yForPe_uid36_fpSqrtTest_b_6_rdcnt_i <= $unsigned(redist6_yForPe_uid36_fpSqrtTest_b_6_rdcnt_i) + $unsigned(2'd2); + end + else + begin + redist6_yForPe_uid36_fpSqrtTest_b_6_rdcnt_i <= $unsigned(redist6_yForPe_uid36_fpSqrtTest_b_6_rdcnt_i) + $unsigned(2'd1); + end + end + end + assign redist6_yForPe_uid36_fpSqrtTest_b_6_rdcnt_q = redist6_yForPe_uid36_fpSqrtTest_b_6_rdcnt_i[1:0]; + + // redist6_yForPe_uid36_fpSqrtTest_b_6_rdmux(MUX,110) + assign redist6_yForPe_uid36_fpSqrtTest_b_6_rdmux_s = en; + always @(redist6_yForPe_uid36_fpSqrtTest_b_6_rdmux_s or redist6_yForPe_uid36_fpSqrtTest_b_6_wraddr_q or redist6_yForPe_uid36_fpSqrtTest_b_6_rdcnt_q) + begin + unique case (redist6_yForPe_uid36_fpSqrtTest_b_6_rdmux_s) + 1'b0 : redist6_yForPe_uid36_fpSqrtTest_b_6_rdmux_q = redist6_yForPe_uid36_fpSqrtTest_b_6_wraddr_q; + 1'b1 : redist6_yForPe_uid36_fpSqrtTest_b_6_rdmux_q = redist6_yForPe_uid36_fpSqrtTest_b_6_rdcnt_q; + default : redist6_yForPe_uid36_fpSqrtTest_b_6_rdmux_q = 2'b0; + endcase + end + + // VCC(CONSTANT,1) + assign VCC_q = 1'b1; + + // redist6_yForPe_uid36_fpSqrtTest_b_6_wraddr(REG,111) + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + redist6_yForPe_uid36_fpSqrtTest_b_6_wraddr_q <= 2'b10; + end + else + begin + redist6_yForPe_uid36_fpSqrtTest_b_6_wraddr_q <= redist6_yForPe_uid36_fpSqrtTest_b_6_rdmux_q; + end + end + + // redist6_yForPe_uid36_fpSqrtTest_b_6_mem(DUALMEM,108) + assign redist6_yForPe_uid36_fpSqrtTest_b_6_mem_ia = redist5_yForPe_uid36_fpSqrtTest_b_2_q; + assign redist6_yForPe_uid36_fpSqrtTest_b_6_mem_aa = redist6_yForPe_uid36_fpSqrtTest_b_6_wraddr_q; + assign redist6_yForPe_uid36_fpSqrtTest_b_6_mem_ab = redist6_yForPe_uid36_fpSqrtTest_b_6_rdmux_q; + assign redist6_yForPe_uid36_fpSqrtTest_b_6_mem_reset0 = areset; + altera_syncram #( + .ram_block_type("MLAB"), + .operation_mode("DUAL_PORT"), + .width_a(16), + .widthad_a(2), + .numwords_a(3), + .width_b(16), + .widthad_b(2), + .numwords_b(3), + .lpm_type("altera_syncram"), + .width_byteena_a(1), + .address_reg_b("CLOCK0"), + .indata_reg_b("CLOCK0"), + .rdcontrol_reg_b("CLOCK0"), + .byteena_reg_b("CLOCK0"), + .outdata_reg_b("CLOCK1"), + .outdata_aclr_b("CLEAR1"), + .clock_enable_input_a("NORMAL"), + .clock_enable_input_b("NORMAL"), + .clock_enable_output_b("NORMAL"), + .read_during_write_mode_mixed_ports("DONT_CARE"), + .power_up_uninitialized("TRUE"), + .intended_device_family("Arria 10") + ) redist6_yForPe_uid36_fpSqrtTest_b_6_mem_dmem ( + .clocken1(redist6_yForPe_uid36_fpSqrtTest_b_6_enaAnd_q[0]), + .clocken0(VCC_q[0]), + .clock0(clk), + .aclr1(redist6_yForPe_uid36_fpSqrtTest_b_6_mem_reset0), + .clock1(clk), + .address_a(redist6_yForPe_uid36_fpSqrtTest_b_6_mem_aa), + .data_a(redist6_yForPe_uid36_fpSqrtTest_b_6_mem_ia), + .wren_a(en[0]), + .address_b(redist6_yForPe_uid36_fpSqrtTest_b_6_mem_ab), + .q_b(redist6_yForPe_uid36_fpSqrtTest_b_6_mem_iq), + .wren_b(), + .rden_a(), + .rden_b(), + .data_b(), + .clocken2(), + .clocken3(), + .aclr0(), + .addressstall_a(), + .addressstall_b(), + .byteena_a(), + .byteena_b(), + .eccencbypass(), + .eccencparity(), + .sclr(), + .address2_a(), + .address2_b(), + .q_a(), + .eccstatus() + ); + assign redist6_yForPe_uid36_fpSqrtTest_b_6_mem_q = redist6_yForPe_uid36_fpSqrtTest_b_6_mem_iq[15:0]; + + // GND(CONSTANT,0) + assign GND_q = 1'b0; + + // prodXY_uid90_pT2_uid81_invPolyEval_cma(CHAINMULTADD,96)@6 + 3 + assign prodXY_uid90_pT2_uid81_invPolyEval_cma_reset = areset; + assign prodXY_uid90_pT2_uid81_invPolyEval_cma_ena0 = en[0]; + assign prodXY_uid90_pT2_uid81_invPolyEval_cma_ena1 = prodXY_uid90_pT2_uid81_invPolyEval_cma_ena0; + assign prodXY_uid90_pT2_uid81_invPolyEval_cma_ena2 = prodXY_uid90_pT2_uid81_invPolyEval_cma_ena0; + assign prodXY_uid90_pT2_uid81_invPolyEval_cma_l[0] = $signed({1'b0, prodXY_uid90_pT2_uid81_invPolyEval_cma_a1[0][15:0]}); + assign prodXY_uid90_pT2_uid81_invPolyEval_cma_p[0] = prodXY_uid90_pT2_uid81_invPolyEval_cma_l[0] * prodXY_uid90_pT2_uid81_invPolyEval_cma_c1[0]; + assign prodXY_uid90_pT2_uid81_invPolyEval_cma_u[0] = prodXY_uid90_pT2_uid81_invPolyEval_cma_p[0][39:0]; + assign prodXY_uid90_pT2_uid81_invPolyEval_cma_w[0] = prodXY_uid90_pT2_uid81_invPolyEval_cma_u[0]; + assign prodXY_uid90_pT2_uid81_invPolyEval_cma_x[0] = prodXY_uid90_pT2_uid81_invPolyEval_cma_w[0]; + assign prodXY_uid90_pT2_uid81_invPolyEval_cma_y[0] = prodXY_uid90_pT2_uid81_invPolyEval_cma_x[0]; + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + prodXY_uid90_pT2_uid81_invPolyEval_cma_a0 <= '{default: '0}; + prodXY_uid90_pT2_uid81_invPolyEval_cma_c0 <= '{default: '0}; + end + else + begin + if (prodXY_uid90_pT2_uid81_invPolyEval_cma_ena0 == 1'b1) + begin + prodXY_uid90_pT2_uid81_invPolyEval_cma_a0[0] <= redist6_yForPe_uid36_fpSqrtTest_b_6_mem_q; + prodXY_uid90_pT2_uid81_invPolyEval_cma_c0[0] <= s1_uid79_invPolyEval_q; + end + end + end + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + prodXY_uid90_pT2_uid81_invPolyEval_cma_a1 <= '{default: '0}; + prodXY_uid90_pT2_uid81_invPolyEval_cma_c1 <= '{default: '0}; + end + else + begin + if (prodXY_uid90_pT2_uid81_invPolyEval_cma_ena2 == 1'b1) + begin + prodXY_uid90_pT2_uid81_invPolyEval_cma_a1 <= prodXY_uid90_pT2_uid81_invPolyEval_cma_a0; + prodXY_uid90_pT2_uid81_invPolyEval_cma_c1 <= prodXY_uid90_pT2_uid81_invPolyEval_cma_c0; + end + end + end + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + prodXY_uid90_pT2_uid81_invPolyEval_cma_s <= '{default: '0}; + end + else + begin + if (prodXY_uid90_pT2_uid81_invPolyEval_cma_ena1 == 1'b1) + begin + prodXY_uid90_pT2_uid81_invPolyEval_cma_s[0] <= prodXY_uid90_pT2_uid81_invPolyEval_cma_y[0]; + end + end + end + dspba_delay_ver #( .width(39), .depth(0), .reset_kind("ASYNC") ) + prodXY_uid90_pT2_uid81_invPolyEval_cma_delay ( .xin(prodXY_uid90_pT2_uid81_invPolyEval_cma_s[0][38:0]), .xout(prodXY_uid90_pT2_uid81_invPolyEval_cma_qq), .ena(en[0]), .clk(clk), .aclr(areset) ); + assign prodXY_uid90_pT2_uid81_invPolyEval_cma_q = prodXY_uid90_pT2_uid81_invPolyEval_cma_qq[38:0]; + + // osig_uid91_pT2_uid81_invPolyEval(BITSELECT,90)@9 + assign osig_uid91_pT2_uid81_invPolyEval_b = prodXY_uid90_pT2_uid81_invPolyEval_cma_q[38:15]; + + // highBBits_uid83_invPolyEval(BITSELECT,82)@9 + assign highBBits_uid83_invPolyEval_b = osig_uid91_pT2_uid81_invPolyEval_b[23:2]; + + // redist8_yAddr_uid35_fpSqrtTest_b_7(DELAY,105) + dspba_delay_ver #( .width(8), .depth(4), .reset_kind("ASYNC") ) + redist8_yAddr_uid35_fpSqrtTest_b_7 ( .xin(redist7_yAddr_uid35_fpSqrtTest_b_3_q), .xout(redist8_yAddr_uid35_fpSqrtTest_b_7_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // memoryC0_uid62_sqrtTables_lutmem(DUALMEM,92)@7 + 2 + // in j@20000000 + assign memoryC0_uid62_sqrtTables_lutmem_aa = redist8_yAddr_uid35_fpSqrtTest_b_7_q; + assign memoryC0_uid62_sqrtTables_lutmem_reset0 = areset; + altera_syncram #( + .ram_block_type("M20K"), + .operation_mode("ROM"), + .width_a(29), + .widthad_a(8), + .numwords_a(256), + .lpm_type("altera_syncram"), + .width_byteena_a(1), + .outdata_reg_a("CLOCK0"), + .outdata_aclr_a("CLEAR0"), + .clock_enable_input_a("NORMAL"), + .power_up_uninitialized("FALSE"), + .init_file("acl_fsqrt_memoryC0_uid62_sqrtTables_lutmem.hex"), + .init_file_layout("PORT_A"), + .intended_device_family("Arria 10") + ) memoryC0_uid62_sqrtTables_lutmem_dmem ( + .clocken0(en[0]), + .aclr0(memoryC0_uid62_sqrtTables_lutmem_reset0), + .clock0(clk), + .address_a(memoryC0_uid62_sqrtTables_lutmem_aa), + .q_a(memoryC0_uid62_sqrtTables_lutmem_ir), + .wren_a(), + .wren_b(), + .rden_a(), + .rden_b(), + .data_a(), + .data_b(), + .address_b(), + .clock1(), + .clocken1(), + .clocken2(), + .clocken3(), + .aclr1(), + .addressstall_a(), + .addressstall_b(), + .byteena_a(), + .byteena_b(), + .eccencbypass(), + .eccencparity(), + .sclr(), + .address2_a(), + .address2_b(), + .q_b(), + .eccstatus() + ); + assign memoryC0_uid62_sqrtTables_lutmem_r = memoryC0_uid62_sqrtTables_lutmem_ir[28:0]; + + // s2sumAHighB_uid84_invPolyEval(ADD,83)@9 + assign s2sumAHighB_uid84_invPolyEval_a = {{1{memoryC0_uid62_sqrtTables_lutmem_r[28]}}, memoryC0_uid62_sqrtTables_lutmem_r}; + assign s2sumAHighB_uid84_invPolyEval_b = {{8{highBBits_uid83_invPolyEval_b[21]}}, highBBits_uid83_invPolyEval_b}; + assign s2sumAHighB_uid84_invPolyEval_o = $signed(s2sumAHighB_uid84_invPolyEval_a) + $signed(s2sumAHighB_uid84_invPolyEval_b); + assign s2sumAHighB_uid84_invPolyEval_q = s2sumAHighB_uid84_invPolyEval_o[29:0]; + + // lowRangeB_uid82_invPolyEval(BITSELECT,81)@9 + assign lowRangeB_uid82_invPolyEval_in = osig_uid91_pT2_uid81_invPolyEval_b[1:0]; + assign lowRangeB_uid82_invPolyEval_b = lowRangeB_uid82_invPolyEval_in[1:0]; + + // s2_uid85_invPolyEval(BITJOIN,84)@9 + assign s2_uid85_invPolyEval_q = {s2sumAHighB_uid84_invPolyEval_q, lowRangeB_uid82_invPolyEval_b}; + + // expInc_uid38_fpSqrtTest(BITSELECT,37)@9 + assign expInc_uid38_fpSqrtTest_in = s2_uid85_invPolyEval_q[30:0]; + assign expInc_uid38_fpSqrtTest_b = expInc_uid38_fpSqrtTest_in[30:30]; + + // redist4_expInc_uid38_fpSqrtTest_b_1(DELAY,101) + dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) + redist4_expInc_uid38_fpSqrtTest_b_1 ( .xin(expInc_uid38_fpSqrtTest_b), .xout(redist4_expInc_uid38_fpSqrtTest_b_1_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // redist9_expRMux_uid31_fpSqrtTest_q_10_notEnable(LOGICAL,127) + assign redist9_expRMux_uid31_fpSqrtTest_q_10_notEnable_q = ~ (en); + + // redist9_expRMux_uid31_fpSqrtTest_q_10_nor(LOGICAL,128) + assign redist9_expRMux_uid31_fpSqrtTest_q_10_nor_q = ~ (redist9_expRMux_uid31_fpSqrtTest_q_10_notEnable_q | redist9_expRMux_uid31_fpSqrtTest_q_10_sticky_ena_q); + + // redist9_expRMux_uid31_fpSqrtTest_q_10_mem_last(CONSTANT,124) + assign redist9_expRMux_uid31_fpSqrtTest_q_10_mem_last_q = 4'b0101; + + // redist9_expRMux_uid31_fpSqrtTest_q_10_cmp(LOGICAL,125) + assign redist9_expRMux_uid31_fpSqrtTest_q_10_cmp_b = {1'b0, redist9_expRMux_uid31_fpSqrtTest_q_10_rdmux_q}; + assign redist9_expRMux_uid31_fpSqrtTest_q_10_cmp_q = redist9_expRMux_uid31_fpSqrtTest_q_10_mem_last_q == redist9_expRMux_uid31_fpSqrtTest_q_10_cmp_b ? 1'b1 : 1'b0; + + // redist9_expRMux_uid31_fpSqrtTest_q_10_cmpReg(REG,126) + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + redist9_expRMux_uid31_fpSqrtTest_q_10_cmpReg_q <= 1'b0; + end + else if (en == 1'b1) + begin + redist9_expRMux_uid31_fpSqrtTest_q_10_cmpReg_q <= redist9_expRMux_uid31_fpSqrtTest_q_10_cmp_q; + end + end + + // redist9_expRMux_uid31_fpSqrtTest_q_10_sticky_ena(REG,129) + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + redist9_expRMux_uid31_fpSqrtTest_q_10_sticky_ena_q <= 1'b0; + end + else if (redist9_expRMux_uid31_fpSqrtTest_q_10_nor_q == 1'b1) + begin + redist9_expRMux_uid31_fpSqrtTest_q_10_sticky_ena_q <= redist9_expRMux_uid31_fpSqrtTest_q_10_cmpReg_q; + end + end + + // redist9_expRMux_uid31_fpSqrtTest_q_10_enaAnd(LOGICAL,130) + assign redist9_expRMux_uid31_fpSqrtTest_q_10_enaAnd_q = redist9_expRMux_uid31_fpSqrtTest_q_10_sticky_ena_q & en; + + // redist9_expRMux_uid31_fpSqrtTest_q_10_rdcnt(COUNTER,121) + // low=0, high=6, step=1, init=0 + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + redist9_expRMux_uid31_fpSqrtTest_q_10_rdcnt_i <= 3'd0; + redist9_expRMux_uid31_fpSqrtTest_q_10_rdcnt_eq <= 1'b0; + end + else if (en == 1'b1) + begin + if (redist9_expRMux_uid31_fpSqrtTest_q_10_rdcnt_i == 3'd5) + begin + redist9_expRMux_uid31_fpSqrtTest_q_10_rdcnt_eq <= 1'b1; + end + else + begin + redist9_expRMux_uid31_fpSqrtTest_q_10_rdcnt_eq <= 1'b0; + end + if (redist9_expRMux_uid31_fpSqrtTest_q_10_rdcnt_eq == 1'b1) + begin + redist9_expRMux_uid31_fpSqrtTest_q_10_rdcnt_i <= $unsigned(redist9_expRMux_uid31_fpSqrtTest_q_10_rdcnt_i) + $unsigned(3'd2); + end + else + begin + redist9_expRMux_uid31_fpSqrtTest_q_10_rdcnt_i <= $unsigned(redist9_expRMux_uid31_fpSqrtTest_q_10_rdcnt_i) + $unsigned(3'd1); + end + end + end + assign redist9_expRMux_uid31_fpSqrtTest_q_10_rdcnt_q = redist9_expRMux_uid31_fpSqrtTest_q_10_rdcnt_i[2:0]; + + // redist9_expRMux_uid31_fpSqrtTest_q_10_rdmux(MUX,122) + assign redist9_expRMux_uid31_fpSqrtTest_q_10_rdmux_s = en; + always @(redist9_expRMux_uid31_fpSqrtTest_q_10_rdmux_s or redist9_expRMux_uid31_fpSqrtTest_q_10_wraddr_q or redist9_expRMux_uid31_fpSqrtTest_q_10_rdcnt_q) + begin + unique case (redist9_expRMux_uid31_fpSqrtTest_q_10_rdmux_s) + 1'b0 : redist9_expRMux_uid31_fpSqrtTest_q_10_rdmux_q = redist9_expRMux_uid31_fpSqrtTest_q_10_wraddr_q; + 1'b1 : redist9_expRMux_uid31_fpSqrtTest_q_10_rdmux_q = redist9_expRMux_uid31_fpSqrtTest_q_10_rdcnt_q; + default : redist9_expRMux_uid31_fpSqrtTest_q_10_rdmux_q = 3'b0; + endcase + end + + // sBiasM1_uid26_fpSqrtTest(CONSTANT,25) + assign sBiasM1_uid26_fpSqrtTest_q = 8'b01111110; + + // expOddSig_uid27_fpSqrtTest(ADD,26)@0 + assign expOddSig_uid27_fpSqrtTest_a = {1'b0, expX_uid6_fpSqrtTest_b}; + assign expOddSig_uid27_fpSqrtTest_b = {1'b0, sBiasM1_uid26_fpSqrtTest_q}; + assign expOddSig_uid27_fpSqrtTest_o = $unsigned(expOddSig_uid27_fpSqrtTest_a) + $unsigned(expOddSig_uid27_fpSqrtTest_b); + assign expOddSig_uid27_fpSqrtTest_q = expOddSig_uid27_fpSqrtTest_o[8:0]; + + // expROdd_uid28_fpSqrtTest(BITSELECT,27)@0 + assign expROdd_uid28_fpSqrtTest_b = expOddSig_uid27_fpSqrtTest_q[8:1]; + + // sBias_uid22_fpSqrtTest(CONSTANT,21) + assign sBias_uid22_fpSqrtTest_q = 8'b01111111; + + // expEvenSig_uid24_fpSqrtTest(ADD,23)@0 + assign expEvenSig_uid24_fpSqrtTest_a = {1'b0, expX_uid6_fpSqrtTest_b}; + assign expEvenSig_uid24_fpSqrtTest_b = {1'b0, sBias_uid22_fpSqrtTest_q}; + assign expEvenSig_uid24_fpSqrtTest_o = $unsigned(expEvenSig_uid24_fpSqrtTest_a) + $unsigned(expEvenSig_uid24_fpSqrtTest_b); + assign expEvenSig_uid24_fpSqrtTest_q = expEvenSig_uid24_fpSqrtTest_o[8:0]; + + // expREven_uid25_fpSqrtTest(BITSELECT,24)@0 + assign expREven_uid25_fpSqrtTest_b = expEvenSig_uid24_fpSqrtTest_q[8:1]; + + // expRMux_uid31_fpSqrtTest(MUX,30)@0 + 1 + assign expRMux_uid31_fpSqrtTest_s = expOddSelect_uid30_fpSqrtTest_q; + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + expRMux_uid31_fpSqrtTest_q <= 8'b0; + end + else if (en == 1'b1) + begin + unique case (expRMux_uid31_fpSqrtTest_s) + 1'b0 : expRMux_uid31_fpSqrtTest_q <= expREven_uid25_fpSqrtTest_b; + 1'b1 : expRMux_uid31_fpSqrtTest_q <= expROdd_uid28_fpSqrtTest_b; + default : expRMux_uid31_fpSqrtTest_q <= 8'b0; + endcase + end + end + + // redist9_expRMux_uid31_fpSqrtTest_q_10_wraddr(REG,123) + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + redist9_expRMux_uid31_fpSqrtTest_q_10_wraddr_q <= 3'b110; + end + else + begin + redist9_expRMux_uid31_fpSqrtTest_q_10_wraddr_q <= redist9_expRMux_uid31_fpSqrtTest_q_10_rdmux_q; + end + end + + // redist9_expRMux_uid31_fpSqrtTest_q_10_mem(DUALMEM,120) + assign redist9_expRMux_uid31_fpSqrtTest_q_10_mem_ia = expRMux_uid31_fpSqrtTest_q; + assign redist9_expRMux_uid31_fpSqrtTest_q_10_mem_aa = redist9_expRMux_uid31_fpSqrtTest_q_10_wraddr_q; + assign redist9_expRMux_uid31_fpSqrtTest_q_10_mem_ab = redist9_expRMux_uid31_fpSqrtTest_q_10_rdmux_q; + assign redist9_expRMux_uid31_fpSqrtTest_q_10_mem_reset0 = areset; + altera_syncram #( + .ram_block_type("MLAB"), + .operation_mode("DUAL_PORT"), + .width_a(8), + .widthad_a(3), + .numwords_a(7), + .width_b(8), + .widthad_b(3), + .numwords_b(7), + .lpm_type("altera_syncram"), + .width_byteena_a(1), + .address_reg_b("CLOCK0"), + .indata_reg_b("CLOCK0"), + .rdcontrol_reg_b("CLOCK0"), + .byteena_reg_b("CLOCK0"), + .outdata_reg_b("CLOCK1"), + .outdata_aclr_b("CLEAR1"), + .clock_enable_input_a("NORMAL"), + .clock_enable_input_b("NORMAL"), + .clock_enable_output_b("NORMAL"), + .read_during_write_mode_mixed_ports("DONT_CARE"), + .power_up_uninitialized("TRUE"), + .intended_device_family("Arria 10") + ) redist9_expRMux_uid31_fpSqrtTest_q_10_mem_dmem ( + .clocken1(redist9_expRMux_uid31_fpSqrtTest_q_10_enaAnd_q[0]), + .clocken0(VCC_q[0]), + .clock0(clk), + .aclr1(redist9_expRMux_uid31_fpSqrtTest_q_10_mem_reset0), + .clock1(clk), + .address_a(redist9_expRMux_uid31_fpSqrtTest_q_10_mem_aa), + .data_a(redist9_expRMux_uid31_fpSqrtTest_q_10_mem_ia), + .wren_a(en[0]), + .address_b(redist9_expRMux_uid31_fpSqrtTest_q_10_mem_ab), + .q_b(redist9_expRMux_uid31_fpSqrtTest_q_10_mem_iq), + .wren_b(), + .rden_a(), + .rden_b(), + .data_b(), + .clocken2(), + .clocken3(), + .aclr0(), + .addressstall_a(), + .addressstall_b(), + .byteena_a(), + .byteena_b(), + .eccencbypass(), + .eccencparity(), + .sclr(), + .address2_a(), + .address2_b(), + .q_a(), + .eccstatus() + ); + assign redist9_expRMux_uid31_fpSqrtTest_q_10_mem_q = redist9_expRMux_uid31_fpSqrtTest_q_10_mem_iq[7:0]; + + // redist9_expRMux_uid31_fpSqrtTest_q_10_outputreg(DELAY,119) + dspba_delay_ver #( .width(8), .depth(1), .reset_kind("ASYNC") ) + redist9_expRMux_uid31_fpSqrtTest_q_10_outputreg ( .xin(redist9_expRMux_uid31_fpSqrtTest_q_10_mem_q), .xout(redist9_expRMux_uid31_fpSqrtTest_q_10_outputreg_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // expR_uid40_fpSqrtTest(ADD,39)@10 + assign expR_uid40_fpSqrtTest_a = {1'b0, redist9_expRMux_uid31_fpSqrtTest_q_10_outputreg_q}; + assign expR_uid40_fpSqrtTest_b = {8'b00000000, redist4_expInc_uid38_fpSqrtTest_b_1_q}; + assign expR_uid40_fpSqrtTest_o = $unsigned(expR_uid40_fpSqrtTest_a) + $unsigned(expR_uid40_fpSqrtTest_b); + assign expR_uid40_fpSqrtTest_q = expR_uid40_fpSqrtTest_o[8:0]; + + // expRR_uid51_fpSqrtTest(BITSELECT,50)@10 + assign expRR_uid51_fpSqrtTest_in = expR_uid40_fpSqrtTest_q[7:0]; + assign expRR_uid51_fpSqrtTest_b = expRR_uid51_fpSqrtTest_in[7:0]; + + // expXIsMax_uid14_fpSqrtTest(LOGICAL,13)@0 + 1 + assign expXIsMax_uid14_fpSqrtTest_qi = expX_uid6_fpSqrtTest_b == cstAllOWE_uid8_fpSqrtTest_q ? 1'b1 : 1'b0; + dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) + expXIsMax_uid14_fpSqrtTest_delay ( .xin(expXIsMax_uid14_fpSqrtTest_qi), .xout(expXIsMax_uid14_fpSqrtTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // invExpXIsMax_uid19_fpSqrtTest(LOGICAL,18)@1 + assign invExpXIsMax_uid19_fpSqrtTest_q = ~ (expXIsMax_uid14_fpSqrtTest_q); + + // InvExpXIsZero_uid20_fpSqrtTest(LOGICAL,19)@1 + assign InvExpXIsZero_uid20_fpSqrtTest_q = ~ (excZ_x_uid13_fpSqrtTest_q); + + // excR_x_uid21_fpSqrtTest(LOGICAL,20)@1 + assign excR_x_uid21_fpSqrtTest_q = InvExpXIsZero_uid20_fpSqrtTest_q & invExpXIsMax_uid19_fpSqrtTest_q; + + // minReg_uid43_fpSqrtTest(LOGICAL,42)@1 + assign minReg_uid43_fpSqrtTest_q = excR_x_uid21_fpSqrtTest_q & redist10_signX_uid7_fpSqrtTest_b_1_q; + + // cstZeroWF_uid9_fpSqrtTest(CONSTANT,8) + assign cstZeroWF_uid9_fpSqrtTest_q = 23'b00000000000000000000000; + + // fracXIsZero_uid15_fpSqrtTest(LOGICAL,14)@0 + 1 + assign fracXIsZero_uid15_fpSqrtTest_qi = cstZeroWF_uid9_fpSqrtTest_q == frac_x_uid12_fpSqrtTest_b ? 1'b1 : 1'b0; + dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) + fracXIsZero_uid15_fpSqrtTest_delay ( .xin(fracXIsZero_uid15_fpSqrtTest_qi), .xout(fracXIsZero_uid15_fpSqrtTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // excI_x_uid17_fpSqrtTest(LOGICAL,16)@1 + assign excI_x_uid17_fpSqrtTest_q = expXIsMax_uid14_fpSqrtTest_q & fracXIsZero_uid15_fpSqrtTest_q; + + // minInf_uid44_fpSqrtTest(LOGICAL,43)@1 + assign minInf_uid44_fpSqrtTest_q = excI_x_uid17_fpSqrtTest_q & redist10_signX_uid7_fpSqrtTest_b_1_q; + + // fracXIsNotZero_uid16_fpSqrtTest(LOGICAL,15)@1 + assign fracXIsNotZero_uid16_fpSqrtTest_q = ~ (fracXIsZero_uid15_fpSqrtTest_q); + + // excN_x_uid18_fpSqrtTest(LOGICAL,17)@1 + assign excN_x_uid18_fpSqrtTest_q = expXIsMax_uid14_fpSqrtTest_q & fracXIsNotZero_uid16_fpSqrtTest_q; + + // excRNaN_uid45_fpSqrtTest(LOGICAL,44)@1 + assign excRNaN_uid45_fpSqrtTest_q = excN_x_uid18_fpSqrtTest_q | minInf_uid44_fpSqrtTest_q | minReg_uid43_fpSqrtTest_q; + + // invSignX_uid41_fpSqrtTest(LOGICAL,40)@1 + assign invSignX_uid41_fpSqrtTest_q = ~ (redist10_signX_uid7_fpSqrtTest_b_1_q); + + // inInfAndNotNeg_uid42_fpSqrtTest(LOGICAL,41)@1 + assign inInfAndNotNeg_uid42_fpSqrtTest_q = excI_x_uid17_fpSqrtTest_q & invSignX_uid41_fpSqrtTest_q; + + // excConc_uid46_fpSqrtTest(BITJOIN,45)@1 + assign excConc_uid46_fpSqrtTest_q = {excRNaN_uid45_fpSqrtTest_q, inInfAndNotNeg_uid42_fpSqrtTest_q, excZ_x_uid13_fpSqrtTest_q}; + + // fracSelIn_uid47_fpSqrtTest(BITJOIN,46)@1 + assign fracSelIn_uid47_fpSqrtTest_q = {redist10_signX_uid7_fpSqrtTest_b_1_q, excConc_uid46_fpSqrtTest_q}; + + // fracSel_uid48_fpSqrtTest(LOOKUP,47)@1 + 1 + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + fracSel_uid48_fpSqrtTest_q <= 2'b01; + end + else if (en == 1'b1) + begin + unique case (fracSelIn_uid47_fpSqrtTest_q) + 4'b0000 : fracSel_uid48_fpSqrtTest_q <= 2'b01; + 4'b0001 : fracSel_uid48_fpSqrtTest_q <= 2'b00; + 4'b0010 : fracSel_uid48_fpSqrtTest_q <= 2'b10; + 4'b0011 : fracSel_uid48_fpSqrtTest_q <= 2'b00; + 4'b0100 : fracSel_uid48_fpSqrtTest_q <= 2'b11; + 4'b0101 : fracSel_uid48_fpSqrtTest_q <= 2'b00; + 4'b0110 : fracSel_uid48_fpSqrtTest_q <= 2'b10; + 4'b0111 : fracSel_uid48_fpSqrtTest_q <= 2'b00; + 4'b1000 : fracSel_uid48_fpSqrtTest_q <= 2'b11; + 4'b1001 : fracSel_uid48_fpSqrtTest_q <= 2'b00; + 4'b1010 : fracSel_uid48_fpSqrtTest_q <= 2'b11; + 4'b1011 : fracSel_uid48_fpSqrtTest_q <= 2'b11; + 4'b1100 : fracSel_uid48_fpSqrtTest_q <= 2'b11; + 4'b1101 : fracSel_uid48_fpSqrtTest_q <= 2'b11; + 4'b1110 : fracSel_uid48_fpSqrtTest_q <= 2'b11; + 4'b1111 : fracSel_uid48_fpSqrtTest_q <= 2'b11; + default : begin + // unreachable + fracSel_uid48_fpSqrtTest_q <= 2'bxx; + end + endcase + end + end + + // redist2_fracSel_uid48_fpSqrtTest_q_9(DELAY,99) + dspba_delay_ver #( .width(2), .depth(8), .reset_kind("ASYNC") ) + redist2_fracSel_uid48_fpSqrtTest_q_9 ( .xin(fracSel_uid48_fpSqrtTest_q), .xout(redist2_fracSel_uid48_fpSqrtTest_q_9_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // expRPostExc_uid53_fpSqrtTest(MUX,52)@10 + assign expRPostExc_uid53_fpSqrtTest_s = redist2_fracSel_uid48_fpSqrtTest_q_9_q; + always @(expRPostExc_uid53_fpSqrtTest_s or en or cstAllZWE_uid10_fpSqrtTest_q or expRR_uid51_fpSqrtTest_b or cstAllOWE_uid8_fpSqrtTest_q) + begin + unique case (expRPostExc_uid53_fpSqrtTest_s) + 2'b00 : expRPostExc_uid53_fpSqrtTest_q = cstAllZWE_uid10_fpSqrtTest_q; + 2'b01 : expRPostExc_uid53_fpSqrtTest_q = expRR_uid51_fpSqrtTest_b; + 2'b10 : expRPostExc_uid53_fpSqrtTest_q = cstAllOWE_uid8_fpSqrtTest_q; + 2'b11 : expRPostExc_uid53_fpSqrtTest_q = cstAllOWE_uid8_fpSqrtTest_q; + default : expRPostExc_uid53_fpSqrtTest_q = 8'b0; + endcase + end + + // fracNaN_uid54_fpSqrtTest(CONSTANT,53) + assign fracNaN_uid54_fpSqrtTest_q = 23'b00000000000000000000001; + + // fracRPostProcessings_uid39_fpSqrtTest(BITSELECT,38)@9 + assign fracRPostProcessings_uid39_fpSqrtTest_in = s2_uid85_invPolyEval_q[28:0]; + assign fracRPostProcessings_uid39_fpSqrtTest_b = fracRPostProcessings_uid39_fpSqrtTest_in[28:6]; + + // redist3_fracRPostProcessings_uid39_fpSqrtTest_b_1(DELAY,100) + dspba_delay_ver #( .width(23), .depth(1), .reset_kind("ASYNC") ) + redist3_fracRPostProcessings_uid39_fpSqrtTest_b_1 ( .xin(fracRPostProcessings_uid39_fpSqrtTest_b), .xout(redist3_fracRPostProcessings_uid39_fpSqrtTest_b_1_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // fracRPostExc_uid58_fpSqrtTest(MUX,57)@10 + assign fracRPostExc_uid58_fpSqrtTest_s = redist2_fracSel_uid48_fpSqrtTest_q_9_q; + always @(fracRPostExc_uid58_fpSqrtTest_s or en or cstZeroWF_uid9_fpSqrtTest_q or redist3_fracRPostProcessings_uid39_fpSqrtTest_b_1_q or fracNaN_uid54_fpSqrtTest_q) + begin + unique case (fracRPostExc_uid58_fpSqrtTest_s) + 2'b00 : fracRPostExc_uid58_fpSqrtTest_q = cstZeroWF_uid9_fpSqrtTest_q; + 2'b01 : fracRPostExc_uid58_fpSqrtTest_q = redist3_fracRPostProcessings_uid39_fpSqrtTest_b_1_q; + 2'b10 : fracRPostExc_uid58_fpSqrtTest_q = cstZeroWF_uid9_fpSqrtTest_q; + 2'b11 : fracRPostExc_uid58_fpSqrtTest_q = fracNaN_uid54_fpSqrtTest_q; + default : fracRPostExc_uid58_fpSqrtTest_q = 23'b0; + endcase + end + + // RSqrt_uid60_fpSqrtTest(BITJOIN,59)@10 + assign RSqrt_uid60_fpSqrtTest_q = {redist1_negZero_uid59_fpSqrtTest_q_9_q, expRPostExc_uid53_fpSqrtTest_q, fracRPostExc_uid58_fpSqrtTest_q}; + + // xOut(GPOUT,4)@10 + assign q = RSqrt_uid60_fpSqrtTest_q; + +endmodule diff --git a/hw/rtl/fp_cores/altera/acl_fsqrt_memoryC0_uid62_sqrtTables_lutmem.hex b/hw/rtl/fp_cores/altera/acl_fsqrt_memoryC0_uid62_sqrtTables_lutmem.hex new file mode 100644 index 00000000..dacc8b55 --- /dev/null +++ b/hw/rtl/fp_cores/altera/acl_fsqrt_memoryC0_uid62_sqrtTables_lutmem.hex @@ -0,0 +1,258 @@ +:020000040000FA +:0400000008000004F0 +:040001000807FC08E8 +:04000200080FF024CF +:040003000817DC6F8F +:04000400081FC0FF12 +:0400050008279DEC3F +:04000600082F734C00 +:040007000837413342 +:04000800083F07B7EF +:040009000846C6EEF1 +:04000A00084E7EEB33 +:04000B0008562FC2A2 +:04000C00085DD9882A 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+:0200F6000DDE1D +:0200F7000DE416 +:0200F8000DEC0D +:0200F9000DEC0C +:0200FA000DEE09 +:0200FB000DF600 +:0200FC000DF401 +:0200FD000DF6FE +:0200FE000DF8FB +:0200FF000E02EF +:00000001ff diff --git a/hw/rtl/fp_cores/altera/acl_ftoi.sv b/hw/rtl/fp_cores/altera/acl_ftoi.sv new file mode 100644 index 00000000..e800b01d --- /dev/null +++ b/hw/rtl/fp_cores/altera/acl_ftoi.sv @@ -0,0 +1,508 @@ +// ------------------------------------------------------------------------- +// High Level Design Compiler for Intel(R) FPGAs Version 17.1 (Release Build #273) +// Quartus Prime development tool and MATLAB/Simulink Interface +// +// Legal Notice: Copyright 2017 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly +// subject to the terms and conditions of the Intel FPGA Software License +// Agreement, Intel MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for +// the sole purpose of programming logic devices manufactured by Intel +// and sold by Intel or its authorized distributors. Please refer to the +// applicable agreement for further details. +// --------------------------------------------------------------------------- + +// SystemVerilog created from acl_ftoi +// SystemVerilog created on Wed Sep 2 07:11:09 2020 + + +(* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007; -name MESSAGE_DISABLE 10958" *) +module acl_ftoi ( + input wire [31:0] a, + input wire [0:0] en, + output wire [31:0] q, + input wire clk, + input wire areset + ); + + wire [0:0] GND_q; + wire [7:0] cstAllOWE_uid6_fpToFxPTest_q; + wire [22:0] cstZeroWF_uid7_fpToFxPTest_q; + wire [7:0] cstAllZWE_uid8_fpToFxPTest_q; + wire [7:0] exp_x_uid9_fpToFxPTest_b; + wire [22:0] frac_x_uid10_fpToFxPTest_b; + wire [0:0] excZ_x_uid11_fpToFxPTest_qi; + reg [0:0] excZ_x_uid11_fpToFxPTest_q; + wire [0:0] expXIsMax_uid12_fpToFxPTest_qi; + reg [0:0] expXIsMax_uid12_fpToFxPTest_q; + wire [0:0] fracXIsZero_uid13_fpToFxPTest_qi; + reg [0:0] fracXIsZero_uid13_fpToFxPTest_q; + wire [0:0] fracXIsNotZero_uid14_fpToFxPTest_q; + wire [0:0] excI_x_uid15_fpToFxPTest_q; + wire [0:0] excN_x_uid16_fpToFxPTest_q; + wire [0:0] invExcXZ_uid22_fpToFxPTest_q; + wire [23:0] oFracX_uid23_fpToFxPTest_q; + wire [0:0] signX_uid25_fpToFxPTest_b; + wire [8:0] ovfExpVal_uid26_fpToFxPTest_q; + wire [10:0] ovfExpRange_uid27_fpToFxPTest_a; + wire [10:0] ovfExpRange_uid27_fpToFxPTest_b; + logic [10:0] ovfExpRange_uid27_fpToFxPTest_o; + wire [0:0] ovfExpRange_uid27_fpToFxPTest_n; + wire [7:0] udfExpVal_uid28_fpToFxPTest_q; + wire [10:0] udf_uid29_fpToFxPTest_a; + wire [10:0] udf_uid29_fpToFxPTest_b; + logic [10:0] udf_uid29_fpToFxPTest_o; + wire [0:0] udf_uid29_fpToFxPTest_n; + wire [8:0] ovfExpVal_uid30_fpToFxPTest_q; + wire [10:0] shiftValE_uid31_fpToFxPTest_a; + wire [10:0] shiftValE_uid31_fpToFxPTest_b; + logic [10:0] shiftValE_uid31_fpToFxPTest_o; + wire [9:0] shiftValE_uid31_fpToFxPTest_q; + wire [5:0] shiftValRaw_uid32_fpToFxPTest_in; + wire [5:0] shiftValRaw_uid32_fpToFxPTest_b; + wire [5:0] maxShiftCst_uid33_fpToFxPTest_q; + wire [11:0] shiftOutOfRange_uid34_fpToFxPTest_a; + wire [11:0] shiftOutOfRange_uid34_fpToFxPTest_b; + logic [11:0] shiftOutOfRange_uid34_fpToFxPTest_o; + wire [0:0] shiftOutOfRange_uid34_fpToFxPTest_n; + wire [0:0] shiftVal_uid35_fpToFxPTest_s; + reg [5:0] shiftVal_uid35_fpToFxPTest_q; + wire [31:0] shifterIn_uid37_fpToFxPTest_q; + wire [31:0] maxPosValueS_uid39_fpToFxPTest_q; + wire [31:0] maxNegValueS_uid40_fpToFxPTest_q; + wire [32:0] zRightShiferNoStickyOut_uid41_fpToFxPTest_q; + wire [32:0] xXorSignE_uid42_fpToFxPTest_b; + wire [32:0] xXorSignE_uid42_fpToFxPTest_q; + wire [2:0] d0_uid43_fpToFxPTest_q; + wire [33:0] sPostRndFull_uid44_fpToFxPTest_a; + wire [33:0] sPostRndFull_uid44_fpToFxPTest_b; + logic [33:0] sPostRndFull_uid44_fpToFxPTest_o; + wire [33:0] sPostRndFull_uid44_fpToFxPTest_q; + wire [32:0] sPostRnd_uid45_fpToFxPTest_in; + wire [31:0] sPostRnd_uid45_fpToFxPTest_b; + wire [34:0] sPostRnd_uid46_fpToFxPTest_in; + wire [33:0] sPostRnd_uid46_fpToFxPTest_b; + wire [35:0] rndOvfPos_uid47_fpToFxPTest_a; + wire [35:0] rndOvfPos_uid47_fpToFxPTest_b; + logic [35:0] rndOvfPos_uid47_fpToFxPTest_o; + wire [0:0] rndOvfPos_uid47_fpToFxPTest_c; + wire [0:0] ovfPostRnd_uid48_fpToFxPTest_q; + wire [2:0] muxSelConc_uid49_fpToFxPTest_q; + reg [1:0] muxSel_uid50_fpToFxPTest_q; + wire [31:0] maxNegValueU_uid51_fpToFxPTest_q; + wire [1:0] finalOut_uid52_fpToFxPTest_s; + reg [31:0] finalOut_uid52_fpToFxPTest_q; + wire [15:0] rightShiftStage0Idx1Rng16_uid56_rightShiferNoStickyOut_uid38_fpToFxPTest_b; + wire [15:0] rightShiftStage0Idx1Pad16_uid57_rightShiferNoStickyOut_uid38_fpToFxPTest_q; + wire [31:0] rightShiftStage0Idx1_uid58_rightShiferNoStickyOut_uid38_fpToFxPTest_q; + wire [1:0] rightShiftStage0_uid62_rightShiferNoStickyOut_uid38_fpToFxPTest_s; + reg [31:0] rightShiftStage0_uid62_rightShiferNoStickyOut_uid38_fpToFxPTest_q; + wire [27:0] rightShiftStage1Idx1Rng4_uid63_rightShiferNoStickyOut_uid38_fpToFxPTest_b; + wire [3:0] rightShiftStage1Idx1Pad4_uid64_rightShiferNoStickyOut_uid38_fpToFxPTest_q; + wire [31:0] rightShiftStage1Idx1_uid65_rightShiferNoStickyOut_uid38_fpToFxPTest_q; + wire [23:0] rightShiftStage1Idx2Rng8_uid66_rightShiferNoStickyOut_uid38_fpToFxPTest_b; + wire [31:0] rightShiftStage1Idx2_uid68_rightShiferNoStickyOut_uid38_fpToFxPTest_q; + wire [19:0] rightShiftStage1Idx3Rng12_uid69_rightShiferNoStickyOut_uid38_fpToFxPTest_b; + wire [11:0] rightShiftStage1Idx3Pad12_uid70_rightShiferNoStickyOut_uid38_fpToFxPTest_q; + wire [31:0] rightShiftStage1Idx3_uid71_rightShiferNoStickyOut_uid38_fpToFxPTest_q; + wire [1:0] rightShiftStage1_uid73_rightShiferNoStickyOut_uid38_fpToFxPTest_s; + reg [31:0] rightShiftStage1_uid73_rightShiferNoStickyOut_uid38_fpToFxPTest_q; + wire [30:0] rightShiftStage2Idx1Rng1_uid74_rightShiferNoStickyOut_uid38_fpToFxPTest_b; + wire [31:0] rightShiftStage2Idx1_uid76_rightShiferNoStickyOut_uid38_fpToFxPTest_q; + wire [29:0] rightShiftStage2Idx2Rng2_uid77_rightShiferNoStickyOut_uid38_fpToFxPTest_b; + wire [1:0] rightShiftStage2Idx2Pad2_uid78_rightShiferNoStickyOut_uid38_fpToFxPTest_q; + wire [31:0] rightShiftStage2Idx2_uid79_rightShiferNoStickyOut_uid38_fpToFxPTest_q; + wire [28:0] rightShiftStage2Idx3Rng3_uid80_rightShiferNoStickyOut_uid38_fpToFxPTest_b; + wire [2:0] rightShiftStage2Idx3Pad3_uid81_rightShiferNoStickyOut_uid38_fpToFxPTest_q; + wire [31:0] rightShiftStage2Idx3_uid82_rightShiferNoStickyOut_uid38_fpToFxPTest_q; + wire [1:0] rightShiftStage2_uid84_rightShiferNoStickyOut_uid38_fpToFxPTest_s; + reg [31:0] rightShiftStage2_uid84_rightShiferNoStickyOut_uid38_fpToFxPTest_q; + wire [1:0] rightShiftStageSel5Dto4_uid61_rightShiferNoStickyOut_uid38_fpToFxPTest_merged_bit_select_b; + wire [1:0] rightShiftStageSel5Dto4_uid61_rightShiferNoStickyOut_uid38_fpToFxPTest_merged_bit_select_c; + wire [1:0] rightShiftStageSel5Dto4_uid61_rightShiferNoStickyOut_uid38_fpToFxPTest_merged_bit_select_d; + reg [31:0] redist0_sPostRnd_uid45_fpToFxPTest_b_1_q; + reg [5:0] redist1_shiftValRaw_uid32_fpToFxPTest_b_1_q; + reg [0:0] redist2_udf_uid29_fpToFxPTest_n_3_q; + reg [0:0] redist3_ovfExpRange_uid27_fpToFxPTest_n_3_q; + reg [0:0] redist4_signX_uid25_fpToFxPTest_b_2_q; + reg [0:0] redist5_signX_uid25_fpToFxPTest_b_3_q; + reg [0:0] redist6_fracXIsZero_uid13_fpToFxPTest_q_2_q; + reg [0:0] redist7_expXIsMax_uid12_fpToFxPTest_q_3_q; + reg [22:0] redist8_frac_x_uid10_fpToFxPTest_b_1_q; + + + // maxNegValueU_uid51_fpToFxPTest(CONSTANT,50) + assign maxNegValueU_uid51_fpToFxPTest_q = 32'b00000000000000000000000000000000; + + // maxNegValueS_uid40_fpToFxPTest(CONSTANT,39) + assign maxNegValueS_uid40_fpToFxPTest_q = 32'b10000000000000000000000000000000; + + // maxPosValueS_uid39_fpToFxPTest(CONSTANT,38) + assign maxPosValueS_uid39_fpToFxPTest_q = 32'b01111111111111111111111111111111; + + // d0_uid43_fpToFxPTest(CONSTANT,42) + assign d0_uid43_fpToFxPTest_q = 3'b001; + + // signX_uid25_fpToFxPTest(BITSELECT,24)@0 + assign signX_uid25_fpToFxPTest_b = a[31:31]; + + // redist4_signX_uid25_fpToFxPTest_b_2(DELAY,90) + dspba_delay_ver #( .width(1), .depth(2), .reset_kind("ASYNC") ) + redist4_signX_uid25_fpToFxPTest_b_2 ( .xin(signX_uid25_fpToFxPTest_b), .xout(redist4_signX_uid25_fpToFxPTest_b_2_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // GND(CONSTANT,0) + assign GND_q = 1'b0; + + // rightShiftStage2Idx3Pad3_uid81_rightShiferNoStickyOut_uid38_fpToFxPTest(CONSTANT,80) + assign rightShiftStage2Idx3Pad3_uid81_rightShiferNoStickyOut_uid38_fpToFxPTest_q = 3'b000; + + // rightShiftStage2Idx3Rng3_uid80_rightShiferNoStickyOut_uid38_fpToFxPTest(BITSELECT,79)@1 + assign rightShiftStage2Idx3Rng3_uid80_rightShiferNoStickyOut_uid38_fpToFxPTest_b = rightShiftStage1_uid73_rightShiferNoStickyOut_uid38_fpToFxPTest_q[31:3]; + + // rightShiftStage2Idx3_uid82_rightShiferNoStickyOut_uid38_fpToFxPTest(BITJOIN,81)@1 + assign rightShiftStage2Idx3_uid82_rightShiferNoStickyOut_uid38_fpToFxPTest_q = {rightShiftStage2Idx3Pad3_uid81_rightShiferNoStickyOut_uid38_fpToFxPTest_q, rightShiftStage2Idx3Rng3_uid80_rightShiferNoStickyOut_uid38_fpToFxPTest_b}; + + // rightShiftStage2Idx2Pad2_uid78_rightShiferNoStickyOut_uid38_fpToFxPTest(CONSTANT,77) + assign rightShiftStage2Idx2Pad2_uid78_rightShiferNoStickyOut_uid38_fpToFxPTest_q = 2'b00; + + // rightShiftStage2Idx2Rng2_uid77_rightShiferNoStickyOut_uid38_fpToFxPTest(BITSELECT,76)@1 + assign rightShiftStage2Idx2Rng2_uid77_rightShiferNoStickyOut_uid38_fpToFxPTest_b = rightShiftStage1_uid73_rightShiferNoStickyOut_uid38_fpToFxPTest_q[31:2]; + + // rightShiftStage2Idx2_uid79_rightShiferNoStickyOut_uid38_fpToFxPTest(BITJOIN,78)@1 + assign rightShiftStage2Idx2_uid79_rightShiferNoStickyOut_uid38_fpToFxPTest_q = {rightShiftStage2Idx2Pad2_uid78_rightShiferNoStickyOut_uid38_fpToFxPTest_q, rightShiftStage2Idx2Rng2_uid77_rightShiferNoStickyOut_uid38_fpToFxPTest_b}; + + // rightShiftStage2Idx1Rng1_uid74_rightShiferNoStickyOut_uid38_fpToFxPTest(BITSELECT,73)@1 + assign rightShiftStage2Idx1Rng1_uid74_rightShiferNoStickyOut_uid38_fpToFxPTest_b = rightShiftStage1_uid73_rightShiferNoStickyOut_uid38_fpToFxPTest_q[31:1]; + + // rightShiftStage2Idx1_uid76_rightShiferNoStickyOut_uid38_fpToFxPTest(BITJOIN,75)@1 + assign rightShiftStage2Idx1_uid76_rightShiferNoStickyOut_uid38_fpToFxPTest_q = {GND_q, rightShiftStage2Idx1Rng1_uid74_rightShiferNoStickyOut_uid38_fpToFxPTest_b}; + + // rightShiftStage1Idx3Pad12_uid70_rightShiferNoStickyOut_uid38_fpToFxPTest(CONSTANT,69) + assign rightShiftStage1Idx3Pad12_uid70_rightShiferNoStickyOut_uid38_fpToFxPTest_q = 12'b000000000000; + + // rightShiftStage1Idx3Rng12_uid69_rightShiferNoStickyOut_uid38_fpToFxPTest(BITSELECT,68)@1 + assign rightShiftStage1Idx3Rng12_uid69_rightShiferNoStickyOut_uid38_fpToFxPTest_b = rightShiftStage0_uid62_rightShiferNoStickyOut_uid38_fpToFxPTest_q[31:12]; + + // rightShiftStage1Idx3_uid71_rightShiferNoStickyOut_uid38_fpToFxPTest(BITJOIN,70)@1 + assign rightShiftStage1Idx3_uid71_rightShiferNoStickyOut_uid38_fpToFxPTest_q = {rightShiftStage1Idx3Pad12_uid70_rightShiferNoStickyOut_uid38_fpToFxPTest_q, rightShiftStage1Idx3Rng12_uid69_rightShiferNoStickyOut_uid38_fpToFxPTest_b}; + + // cstAllZWE_uid8_fpToFxPTest(CONSTANT,7) + assign cstAllZWE_uid8_fpToFxPTest_q = 8'b00000000; + + // rightShiftStage1Idx2Rng8_uid66_rightShiferNoStickyOut_uid38_fpToFxPTest(BITSELECT,65)@1 + assign rightShiftStage1Idx2Rng8_uid66_rightShiferNoStickyOut_uid38_fpToFxPTest_b = rightShiftStage0_uid62_rightShiferNoStickyOut_uid38_fpToFxPTest_q[31:8]; + + // rightShiftStage1Idx2_uid68_rightShiferNoStickyOut_uid38_fpToFxPTest(BITJOIN,67)@1 + assign rightShiftStage1Idx2_uid68_rightShiferNoStickyOut_uid38_fpToFxPTest_q = {cstAllZWE_uid8_fpToFxPTest_q, rightShiftStage1Idx2Rng8_uid66_rightShiferNoStickyOut_uid38_fpToFxPTest_b}; + + // rightShiftStage1Idx1Pad4_uid64_rightShiferNoStickyOut_uid38_fpToFxPTest(CONSTANT,63) + assign rightShiftStage1Idx1Pad4_uid64_rightShiferNoStickyOut_uid38_fpToFxPTest_q = 4'b0000; + + // rightShiftStage1Idx1Rng4_uid63_rightShiferNoStickyOut_uid38_fpToFxPTest(BITSELECT,62)@1 + assign rightShiftStage1Idx1Rng4_uid63_rightShiferNoStickyOut_uid38_fpToFxPTest_b = rightShiftStage0_uid62_rightShiferNoStickyOut_uid38_fpToFxPTest_q[31:4]; + + // rightShiftStage1Idx1_uid65_rightShiferNoStickyOut_uid38_fpToFxPTest(BITJOIN,64)@1 + assign rightShiftStage1Idx1_uid65_rightShiferNoStickyOut_uid38_fpToFxPTest_q = {rightShiftStage1Idx1Pad4_uid64_rightShiferNoStickyOut_uid38_fpToFxPTest_q, rightShiftStage1Idx1Rng4_uid63_rightShiferNoStickyOut_uid38_fpToFxPTest_b}; + + // rightShiftStage0Idx1Pad16_uid57_rightShiferNoStickyOut_uid38_fpToFxPTest(CONSTANT,56) + assign rightShiftStage0Idx1Pad16_uid57_rightShiferNoStickyOut_uid38_fpToFxPTest_q = 16'b0000000000000000; + + // rightShiftStage0Idx1Rng16_uid56_rightShiferNoStickyOut_uid38_fpToFxPTest(BITSELECT,55)@1 + assign rightShiftStage0Idx1Rng16_uid56_rightShiferNoStickyOut_uid38_fpToFxPTest_b = shifterIn_uid37_fpToFxPTest_q[31:16]; + + // rightShiftStage0Idx1_uid58_rightShiferNoStickyOut_uid38_fpToFxPTest(BITJOIN,57)@1 + assign rightShiftStage0Idx1_uid58_rightShiferNoStickyOut_uid38_fpToFxPTest_q = {rightShiftStage0Idx1Pad16_uid57_rightShiferNoStickyOut_uid38_fpToFxPTest_q, rightShiftStage0Idx1Rng16_uid56_rightShiferNoStickyOut_uid38_fpToFxPTest_b}; + + // exp_x_uid9_fpToFxPTest(BITSELECT,8)@0 + assign exp_x_uid9_fpToFxPTest_b = a[30:23]; + + // excZ_x_uid11_fpToFxPTest(LOGICAL,10)@0 + 1 + assign excZ_x_uid11_fpToFxPTest_qi = exp_x_uid9_fpToFxPTest_b == cstAllZWE_uid8_fpToFxPTest_q ? 1'b1 : 1'b0; + dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) + excZ_x_uid11_fpToFxPTest_delay ( .xin(excZ_x_uid11_fpToFxPTest_qi), .xout(excZ_x_uid11_fpToFxPTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // invExcXZ_uid22_fpToFxPTest(LOGICAL,21)@1 + assign invExcXZ_uid22_fpToFxPTest_q = ~ (excZ_x_uid11_fpToFxPTest_q); + + // frac_x_uid10_fpToFxPTest(BITSELECT,9)@0 + assign frac_x_uid10_fpToFxPTest_b = a[22:0]; + + // redist8_frac_x_uid10_fpToFxPTest_b_1(DELAY,94) + dspba_delay_ver #( .width(23), .depth(1), .reset_kind("ASYNC") ) + redist8_frac_x_uid10_fpToFxPTest_b_1 ( .xin(frac_x_uid10_fpToFxPTest_b), .xout(redist8_frac_x_uid10_fpToFxPTest_b_1_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // oFracX_uid23_fpToFxPTest(BITJOIN,22)@1 + assign oFracX_uid23_fpToFxPTest_q = {invExcXZ_uid22_fpToFxPTest_q, redist8_frac_x_uid10_fpToFxPTest_b_1_q}; + + // shifterIn_uid37_fpToFxPTest(BITJOIN,36)@1 + assign shifterIn_uid37_fpToFxPTest_q = {oFracX_uid23_fpToFxPTest_q, cstAllZWE_uid8_fpToFxPTest_q}; + + // rightShiftStage0_uid62_rightShiferNoStickyOut_uid38_fpToFxPTest(MUX,61)@1 + assign rightShiftStage0_uid62_rightShiferNoStickyOut_uid38_fpToFxPTest_s = rightShiftStageSel5Dto4_uid61_rightShiferNoStickyOut_uid38_fpToFxPTest_merged_bit_select_b; + always @(rightShiftStage0_uid62_rightShiferNoStickyOut_uid38_fpToFxPTest_s or en or shifterIn_uid37_fpToFxPTest_q or rightShiftStage0Idx1_uid58_rightShiferNoStickyOut_uid38_fpToFxPTest_q or maxNegValueU_uid51_fpToFxPTest_q) + begin + unique case (rightShiftStage0_uid62_rightShiferNoStickyOut_uid38_fpToFxPTest_s) + 2'b00 : rightShiftStage0_uid62_rightShiferNoStickyOut_uid38_fpToFxPTest_q = shifterIn_uid37_fpToFxPTest_q; + 2'b01 : rightShiftStage0_uid62_rightShiferNoStickyOut_uid38_fpToFxPTest_q = rightShiftStage0Idx1_uid58_rightShiferNoStickyOut_uid38_fpToFxPTest_q; + 2'b10 : rightShiftStage0_uid62_rightShiferNoStickyOut_uid38_fpToFxPTest_q = maxNegValueU_uid51_fpToFxPTest_q; + 2'b11 : rightShiftStage0_uid62_rightShiferNoStickyOut_uid38_fpToFxPTest_q = maxNegValueU_uid51_fpToFxPTest_q; + default : rightShiftStage0_uid62_rightShiferNoStickyOut_uid38_fpToFxPTest_q = 32'b0; + endcase + end + + // rightShiftStage1_uid73_rightShiferNoStickyOut_uid38_fpToFxPTest(MUX,72)@1 + assign rightShiftStage1_uid73_rightShiferNoStickyOut_uid38_fpToFxPTest_s = rightShiftStageSel5Dto4_uid61_rightShiferNoStickyOut_uid38_fpToFxPTest_merged_bit_select_c; + always @(rightShiftStage1_uid73_rightShiferNoStickyOut_uid38_fpToFxPTest_s or en or rightShiftStage0_uid62_rightShiferNoStickyOut_uid38_fpToFxPTest_q or rightShiftStage1Idx1_uid65_rightShiferNoStickyOut_uid38_fpToFxPTest_q or rightShiftStage1Idx2_uid68_rightShiferNoStickyOut_uid38_fpToFxPTest_q or rightShiftStage1Idx3_uid71_rightShiferNoStickyOut_uid38_fpToFxPTest_q) + begin + unique case (rightShiftStage1_uid73_rightShiferNoStickyOut_uid38_fpToFxPTest_s) + 2'b00 : rightShiftStage1_uid73_rightShiferNoStickyOut_uid38_fpToFxPTest_q = rightShiftStage0_uid62_rightShiferNoStickyOut_uid38_fpToFxPTest_q; + 2'b01 : rightShiftStage1_uid73_rightShiferNoStickyOut_uid38_fpToFxPTest_q = rightShiftStage1Idx1_uid65_rightShiferNoStickyOut_uid38_fpToFxPTest_q; + 2'b10 : rightShiftStage1_uid73_rightShiferNoStickyOut_uid38_fpToFxPTest_q = rightShiftStage1Idx2_uid68_rightShiferNoStickyOut_uid38_fpToFxPTest_q; + 2'b11 : rightShiftStage1_uid73_rightShiferNoStickyOut_uid38_fpToFxPTest_q = rightShiftStage1Idx3_uid71_rightShiferNoStickyOut_uid38_fpToFxPTest_q; + default : rightShiftStage1_uid73_rightShiferNoStickyOut_uid38_fpToFxPTest_q = 32'b0; + endcase + end + + // maxShiftCst_uid33_fpToFxPTest(CONSTANT,32) + assign maxShiftCst_uid33_fpToFxPTest_q = 6'b100000; + + // ovfExpVal_uid30_fpToFxPTest(CONSTANT,29) + assign ovfExpVal_uid30_fpToFxPTest_q = 9'b010011101; + + // shiftValE_uid31_fpToFxPTest(SUB,30)@0 + assign shiftValE_uid31_fpToFxPTest_a = {{2{ovfExpVal_uid30_fpToFxPTest_q[8]}}, ovfExpVal_uid30_fpToFxPTest_q}; + assign shiftValE_uid31_fpToFxPTest_b = {3'b000, exp_x_uid9_fpToFxPTest_b}; + assign shiftValE_uid31_fpToFxPTest_o = $signed(shiftValE_uid31_fpToFxPTest_a) - $signed(shiftValE_uid31_fpToFxPTest_b); + assign shiftValE_uid31_fpToFxPTest_q = shiftValE_uid31_fpToFxPTest_o[9:0]; + + // shiftValRaw_uid32_fpToFxPTest(BITSELECT,31)@0 + assign shiftValRaw_uid32_fpToFxPTest_in = shiftValE_uid31_fpToFxPTest_q[5:0]; + assign shiftValRaw_uid32_fpToFxPTest_b = shiftValRaw_uid32_fpToFxPTest_in[5:0]; + + // redist1_shiftValRaw_uid32_fpToFxPTest_b_1(DELAY,87) + dspba_delay_ver #( .width(6), .depth(1), .reset_kind("ASYNC") ) + redist1_shiftValRaw_uid32_fpToFxPTest_b_1 ( .xin(shiftValRaw_uid32_fpToFxPTest_b), .xout(redist1_shiftValRaw_uid32_fpToFxPTest_b_1_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // shiftOutOfRange_uid34_fpToFxPTest(COMPARE,33)@0 + 1 + assign shiftOutOfRange_uid34_fpToFxPTest_a = {{2{shiftValE_uid31_fpToFxPTest_q[9]}}, shiftValE_uid31_fpToFxPTest_q}; + assign shiftOutOfRange_uid34_fpToFxPTest_b = {6'b000000, maxShiftCst_uid33_fpToFxPTest_q}; + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + shiftOutOfRange_uid34_fpToFxPTest_o <= 12'b0; + end + else if (en == 1'b1) + begin + shiftOutOfRange_uid34_fpToFxPTest_o <= $signed(shiftOutOfRange_uid34_fpToFxPTest_a) - $signed(shiftOutOfRange_uid34_fpToFxPTest_b); + end + end + assign shiftOutOfRange_uid34_fpToFxPTest_n[0] = ~ (shiftOutOfRange_uid34_fpToFxPTest_o[11]); + + // shiftVal_uid35_fpToFxPTest(MUX,34)@1 + assign shiftVal_uid35_fpToFxPTest_s = shiftOutOfRange_uid34_fpToFxPTest_n; + always @(shiftVal_uid35_fpToFxPTest_s or en or redist1_shiftValRaw_uid32_fpToFxPTest_b_1_q or maxShiftCst_uid33_fpToFxPTest_q) + begin + unique case (shiftVal_uid35_fpToFxPTest_s) + 1'b0 : shiftVal_uid35_fpToFxPTest_q = redist1_shiftValRaw_uid32_fpToFxPTest_b_1_q; + 1'b1 : shiftVal_uid35_fpToFxPTest_q = maxShiftCst_uid33_fpToFxPTest_q; + default : shiftVal_uid35_fpToFxPTest_q = 6'b0; + endcase + end + + // rightShiftStageSel5Dto4_uid61_rightShiferNoStickyOut_uid38_fpToFxPTest_merged_bit_select(BITSELECT,85)@1 + assign rightShiftStageSel5Dto4_uid61_rightShiferNoStickyOut_uid38_fpToFxPTest_merged_bit_select_b = shiftVal_uid35_fpToFxPTest_q[5:4]; + assign rightShiftStageSel5Dto4_uid61_rightShiferNoStickyOut_uid38_fpToFxPTest_merged_bit_select_c = shiftVal_uid35_fpToFxPTest_q[3:2]; + assign rightShiftStageSel5Dto4_uid61_rightShiferNoStickyOut_uid38_fpToFxPTest_merged_bit_select_d = shiftVal_uid35_fpToFxPTest_q[1:0]; + + // rightShiftStage2_uid84_rightShiferNoStickyOut_uid38_fpToFxPTest(MUX,83)@1 + 1 + assign rightShiftStage2_uid84_rightShiferNoStickyOut_uid38_fpToFxPTest_s = rightShiftStageSel5Dto4_uid61_rightShiferNoStickyOut_uid38_fpToFxPTest_merged_bit_select_d; + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + rightShiftStage2_uid84_rightShiferNoStickyOut_uid38_fpToFxPTest_q <= 32'b0; + end + else if (en == 1'b1) + begin + unique case (rightShiftStage2_uid84_rightShiferNoStickyOut_uid38_fpToFxPTest_s) + 2'b00 : rightShiftStage2_uid84_rightShiferNoStickyOut_uid38_fpToFxPTest_q <= rightShiftStage1_uid73_rightShiferNoStickyOut_uid38_fpToFxPTest_q; + 2'b01 : rightShiftStage2_uid84_rightShiferNoStickyOut_uid38_fpToFxPTest_q <= rightShiftStage2Idx1_uid76_rightShiferNoStickyOut_uid38_fpToFxPTest_q; + 2'b10 : rightShiftStage2_uid84_rightShiferNoStickyOut_uid38_fpToFxPTest_q <= rightShiftStage2Idx2_uid79_rightShiferNoStickyOut_uid38_fpToFxPTest_q; + 2'b11 : rightShiftStage2_uid84_rightShiferNoStickyOut_uid38_fpToFxPTest_q <= rightShiftStage2Idx3_uid82_rightShiferNoStickyOut_uid38_fpToFxPTest_q; + default : rightShiftStage2_uid84_rightShiferNoStickyOut_uid38_fpToFxPTest_q <= 32'b0; + endcase + end + end + + // zRightShiferNoStickyOut_uid41_fpToFxPTest(BITJOIN,40)@2 + assign zRightShiferNoStickyOut_uid41_fpToFxPTest_q = {GND_q, rightShiftStage2_uid84_rightShiferNoStickyOut_uid38_fpToFxPTest_q}; + + // xXorSignE_uid42_fpToFxPTest(LOGICAL,41)@2 + assign xXorSignE_uid42_fpToFxPTest_b = {{32{redist4_signX_uid25_fpToFxPTest_b_2_q[0]}}, redist4_signX_uid25_fpToFxPTest_b_2_q}; + assign xXorSignE_uid42_fpToFxPTest_q = zRightShiferNoStickyOut_uid41_fpToFxPTest_q ^ xXorSignE_uid42_fpToFxPTest_b; + + // sPostRndFull_uid44_fpToFxPTest(ADD,43)@2 + assign sPostRndFull_uid44_fpToFxPTest_a = {{1{xXorSignE_uid42_fpToFxPTest_q[32]}}, xXorSignE_uid42_fpToFxPTest_q}; + assign sPostRndFull_uid44_fpToFxPTest_b = {{31{d0_uid43_fpToFxPTest_q[2]}}, d0_uid43_fpToFxPTest_q}; + assign sPostRndFull_uid44_fpToFxPTest_o = $signed(sPostRndFull_uid44_fpToFxPTest_a) + $signed(sPostRndFull_uid44_fpToFxPTest_b); + assign sPostRndFull_uid44_fpToFxPTest_q = sPostRndFull_uid44_fpToFxPTest_o[33:0]; + + // sPostRnd_uid45_fpToFxPTest(BITSELECT,44)@2 + assign sPostRnd_uid45_fpToFxPTest_in = sPostRndFull_uid44_fpToFxPTest_q[32:0]; + assign sPostRnd_uid45_fpToFxPTest_b = sPostRnd_uid45_fpToFxPTest_in[32:1]; + + // redist0_sPostRnd_uid45_fpToFxPTest_b_1(DELAY,86) + dspba_delay_ver #( .width(32), .depth(1), .reset_kind("ASYNC") ) + redist0_sPostRnd_uid45_fpToFxPTest_b_1 ( .xin(sPostRnd_uid45_fpToFxPTest_b), .xout(redist0_sPostRnd_uid45_fpToFxPTest_b_1_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // redist5_signX_uid25_fpToFxPTest_b_3(DELAY,91) + dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) + redist5_signX_uid25_fpToFxPTest_b_3 ( .xin(redist4_signX_uid25_fpToFxPTest_b_2_q), .xout(redist5_signX_uid25_fpToFxPTest_b_3_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // udfExpVal_uid28_fpToFxPTest(CONSTANT,27) + assign udfExpVal_uid28_fpToFxPTest_q = 8'b01111101; + + // udf_uid29_fpToFxPTest(COMPARE,28)@0 + 1 + assign udf_uid29_fpToFxPTest_a = {{3{udfExpVal_uid28_fpToFxPTest_q[7]}}, udfExpVal_uid28_fpToFxPTest_q}; + assign udf_uid29_fpToFxPTest_b = {3'b000, exp_x_uid9_fpToFxPTest_b}; + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + udf_uid29_fpToFxPTest_o <= 11'b0; + end + else if (en == 1'b1) + begin + udf_uid29_fpToFxPTest_o <= $signed(udf_uid29_fpToFxPTest_a) - $signed(udf_uid29_fpToFxPTest_b); + end + end + assign udf_uid29_fpToFxPTest_n[0] = ~ (udf_uid29_fpToFxPTest_o[10]); + + // redist2_udf_uid29_fpToFxPTest_n_3(DELAY,88) + dspba_delay_ver #( .width(1), .depth(2), .reset_kind("ASYNC") ) + redist2_udf_uid29_fpToFxPTest_n_3 ( .xin(udf_uid29_fpToFxPTest_n), .xout(redist2_udf_uid29_fpToFxPTest_n_3_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // sPostRnd_uid46_fpToFxPTest(BITSELECT,45)@2 + assign sPostRnd_uid46_fpToFxPTest_in = {{1{sPostRndFull_uid44_fpToFxPTest_q[33]}}, sPostRndFull_uid44_fpToFxPTest_q}; + assign sPostRnd_uid46_fpToFxPTest_b = sPostRnd_uid46_fpToFxPTest_in[34:1]; + + // rndOvfPos_uid47_fpToFxPTest(COMPARE,46)@2 + 1 + assign rndOvfPos_uid47_fpToFxPTest_a = {4'b0000, maxPosValueS_uid39_fpToFxPTest_q}; + assign rndOvfPos_uid47_fpToFxPTest_b = {{2{sPostRnd_uid46_fpToFxPTest_b[33]}}, sPostRnd_uid46_fpToFxPTest_b}; + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + rndOvfPos_uid47_fpToFxPTest_o <= 36'b0; + end + else if (en == 1'b1) + begin + rndOvfPos_uid47_fpToFxPTest_o <= $signed(rndOvfPos_uid47_fpToFxPTest_a) - $signed(rndOvfPos_uid47_fpToFxPTest_b); + end + end + assign rndOvfPos_uid47_fpToFxPTest_c[0] = rndOvfPos_uid47_fpToFxPTest_o[35]; + + // ovfExpVal_uid26_fpToFxPTest(CONSTANT,25) + assign ovfExpVal_uid26_fpToFxPTest_q = 9'b010011110; + + // ovfExpRange_uid27_fpToFxPTest(COMPARE,26)@0 + 1 + assign ovfExpRange_uid27_fpToFxPTest_a = {3'b000, exp_x_uid9_fpToFxPTest_b}; + assign ovfExpRange_uid27_fpToFxPTest_b = {{2{ovfExpVal_uid26_fpToFxPTest_q[8]}}, ovfExpVal_uid26_fpToFxPTest_q}; + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + ovfExpRange_uid27_fpToFxPTest_o <= 11'b0; + end + else if (en == 1'b1) + begin + ovfExpRange_uid27_fpToFxPTest_o <= $signed(ovfExpRange_uid27_fpToFxPTest_a) - $signed(ovfExpRange_uid27_fpToFxPTest_b); + end + end + assign ovfExpRange_uid27_fpToFxPTest_n[0] = ~ (ovfExpRange_uid27_fpToFxPTest_o[10]); + + // redist3_ovfExpRange_uid27_fpToFxPTest_n_3(DELAY,89) + dspba_delay_ver #( .width(1), .depth(2), .reset_kind("ASYNC") ) + redist3_ovfExpRange_uid27_fpToFxPTest_n_3 ( .xin(ovfExpRange_uid27_fpToFxPTest_n), .xout(redist3_ovfExpRange_uid27_fpToFxPTest_n_3_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // cstZeroWF_uid7_fpToFxPTest(CONSTANT,6) + assign cstZeroWF_uid7_fpToFxPTest_q = 23'b00000000000000000000000; + + // fracXIsZero_uid13_fpToFxPTest(LOGICAL,12)@1 + 1 + assign fracXIsZero_uid13_fpToFxPTest_qi = cstZeroWF_uid7_fpToFxPTest_q == redist8_frac_x_uid10_fpToFxPTest_b_1_q ? 1'b1 : 1'b0; + dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) + fracXIsZero_uid13_fpToFxPTest_delay ( .xin(fracXIsZero_uid13_fpToFxPTest_qi), .xout(fracXIsZero_uid13_fpToFxPTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // redist6_fracXIsZero_uid13_fpToFxPTest_q_2(DELAY,92) + dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) + redist6_fracXIsZero_uid13_fpToFxPTest_q_2 ( .xin(fracXIsZero_uid13_fpToFxPTest_q), .xout(redist6_fracXIsZero_uid13_fpToFxPTest_q_2_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // cstAllOWE_uid6_fpToFxPTest(CONSTANT,5) + assign cstAllOWE_uid6_fpToFxPTest_q = 8'b11111111; + + // expXIsMax_uid12_fpToFxPTest(LOGICAL,11)@0 + 1 + assign expXIsMax_uid12_fpToFxPTest_qi = exp_x_uid9_fpToFxPTest_b == cstAllOWE_uid6_fpToFxPTest_q ? 1'b1 : 1'b0; + dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) + expXIsMax_uid12_fpToFxPTest_delay ( .xin(expXIsMax_uid12_fpToFxPTest_qi), .xout(expXIsMax_uid12_fpToFxPTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // redist7_expXIsMax_uid12_fpToFxPTest_q_3(DELAY,93) + dspba_delay_ver #( .width(1), .depth(2), .reset_kind("ASYNC") ) + redist7_expXIsMax_uid12_fpToFxPTest_q_3 ( .xin(expXIsMax_uid12_fpToFxPTest_q), .xout(redist7_expXIsMax_uid12_fpToFxPTest_q_3_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // excI_x_uid15_fpToFxPTest(LOGICAL,14)@3 + assign excI_x_uid15_fpToFxPTest_q = redist7_expXIsMax_uid12_fpToFxPTest_q_3_q & redist6_fracXIsZero_uid13_fpToFxPTest_q_2_q; + + // fracXIsNotZero_uid14_fpToFxPTest(LOGICAL,13)@3 + assign fracXIsNotZero_uid14_fpToFxPTest_q = ~ (redist6_fracXIsZero_uid13_fpToFxPTest_q_2_q); + + // excN_x_uid16_fpToFxPTest(LOGICAL,15)@3 + assign excN_x_uid16_fpToFxPTest_q = redist7_expXIsMax_uid12_fpToFxPTest_q_3_q & fracXIsNotZero_uid14_fpToFxPTest_q; + + // ovfPostRnd_uid48_fpToFxPTest(LOGICAL,47)@3 + assign ovfPostRnd_uid48_fpToFxPTest_q = excN_x_uid16_fpToFxPTest_q | excI_x_uid15_fpToFxPTest_q | redist3_ovfExpRange_uid27_fpToFxPTest_n_3_q | rndOvfPos_uid47_fpToFxPTest_c; + + // muxSelConc_uid49_fpToFxPTest(BITJOIN,48)@3 + assign muxSelConc_uid49_fpToFxPTest_q = {redist5_signX_uid25_fpToFxPTest_b_3_q, redist2_udf_uid29_fpToFxPTest_n_3_q, ovfPostRnd_uid48_fpToFxPTest_q}; + + // muxSel_uid50_fpToFxPTest(LOOKUP,49)@3 + always @(muxSelConc_uid49_fpToFxPTest_q) + begin + // Begin reserved scope level + unique case (muxSelConc_uid49_fpToFxPTest_q) + 3'b000 : muxSel_uid50_fpToFxPTest_q = 2'b00; + 3'b001 : muxSel_uid50_fpToFxPTest_q = 2'b01; + 3'b010 : muxSel_uid50_fpToFxPTest_q = 2'b11; + 3'b011 : muxSel_uid50_fpToFxPTest_q = 2'b11; + 3'b100 : muxSel_uid50_fpToFxPTest_q = 2'b00; + 3'b101 : muxSel_uid50_fpToFxPTest_q = 2'b10; + 3'b110 : muxSel_uid50_fpToFxPTest_q = 2'b11; + 3'b111 : muxSel_uid50_fpToFxPTest_q = 2'b11; + default : begin + // unreachable + muxSel_uid50_fpToFxPTest_q = 2'bxx; + end + endcase + // End reserved scope level + end + + // finalOut_uid52_fpToFxPTest(MUX,51)@3 + assign finalOut_uid52_fpToFxPTest_s = muxSel_uid50_fpToFxPTest_q; + always @(finalOut_uid52_fpToFxPTest_s or en or redist0_sPostRnd_uid45_fpToFxPTest_b_1_q or maxPosValueS_uid39_fpToFxPTest_q or maxNegValueS_uid40_fpToFxPTest_q or maxNegValueU_uid51_fpToFxPTest_q) + begin + unique case (finalOut_uid52_fpToFxPTest_s) + 2'b00 : finalOut_uid52_fpToFxPTest_q = redist0_sPostRnd_uid45_fpToFxPTest_b_1_q; + 2'b01 : finalOut_uid52_fpToFxPTest_q = maxPosValueS_uid39_fpToFxPTest_q; + 2'b10 : finalOut_uid52_fpToFxPTest_q = maxNegValueS_uid40_fpToFxPTest_q; + 2'b11 : finalOut_uid52_fpToFxPTest_q = maxNegValueU_uid51_fpToFxPTest_q; + default : finalOut_uid52_fpToFxPTest_q = 32'b0; + endcase + end + + // xOut(GPOUT,4)@3 + assign q = finalOut_uid52_fpToFxPTest_q; + +endmodule diff --git a/hw/rtl/fp_cores/altera/acl_ftou.sv b/hw/rtl/fp_cores/altera/acl_ftou.sv new file mode 100644 index 00000000..cd5de555 --- /dev/null +++ b/hw/rtl/fp_cores/altera/acl_ftou.sv @@ -0,0 +1,493 @@ +// ------------------------------------------------------------------------- +// High Level Design Compiler for Intel(R) FPGAs Version 17.1 (Release Build #273) +// Quartus Prime development tool and MATLAB/Simulink Interface +// +// Legal Notice: Copyright 2017 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly +// subject to the terms and conditions of the Intel FPGA Software License +// Agreement, Intel MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for +// the sole purpose of programming logic devices manufactured by Intel +// and sold by Intel or its authorized distributors. Please refer to the +// applicable agreement for further details. +// --------------------------------------------------------------------------- + +// SystemVerilog created from acl_ftou +// SystemVerilog created on Wed Sep 2 07:11:09 2020 + + +(* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007; -name MESSAGE_DISABLE 10958" *) +module acl_ftou ( + input wire [31:0] a, + input wire [0:0] en, + output wire [31:0] q, + input wire clk, + input wire areset + ); + + wire [0:0] GND_q; + wire [0:0] VCC_q; + wire [7:0] cstAllOWE_uid6_fpToFxPTest_q; + wire [22:0] cstZeroWF_uid7_fpToFxPTest_q; + wire [7:0] cstAllZWE_uid8_fpToFxPTest_q; + wire [7:0] exp_x_uid9_fpToFxPTest_b; + wire [22:0] frac_x_uid10_fpToFxPTest_b; + wire [0:0] excZ_x_uid11_fpToFxPTest_qi; + reg [0:0] excZ_x_uid11_fpToFxPTest_q; + wire [0:0] expXIsMax_uid12_fpToFxPTest_qi; + reg [0:0] expXIsMax_uid12_fpToFxPTest_q; + wire [0:0] fracXIsZero_uid13_fpToFxPTest_qi; + reg [0:0] fracXIsZero_uid13_fpToFxPTest_q; + wire [0:0] fracXIsNotZero_uid14_fpToFxPTest_q; + wire [0:0] excI_x_uid15_fpToFxPTest_q; + wire [0:0] excN_x_uid16_fpToFxPTest_q; + wire [0:0] invExcXZ_uid22_fpToFxPTest_q; + wire [23:0] oFracX_uid23_fpToFxPTest_q; + wire [0:0] signX_uid25_fpToFxPTest_b; + wire [8:0] ovfExpVal_uid26_fpToFxPTest_q; + wire [10:0] ovf_uid27_fpToFxPTest_a; + wire [10:0] ovf_uid27_fpToFxPTest_b; + logic [10:0] ovf_uid27_fpToFxPTest_o; + wire [0:0] ovf_uid27_fpToFxPTest_n; + wire [0:0] negOrOvf_uid28_fpToFxPTest_q; + wire [7:0] udfExpVal_uid29_fpToFxPTest_q; + wire [10:0] udf_uid30_fpToFxPTest_a; + wire [10:0] udf_uid30_fpToFxPTest_b; + logic [10:0] udf_uid30_fpToFxPTest_o; + wire [0:0] udf_uid30_fpToFxPTest_n; + wire [8:0] ovfExpVal_uid31_fpToFxPTest_q; + wire [10:0] shiftValE_uid32_fpToFxPTest_a; + wire [10:0] shiftValE_uid32_fpToFxPTest_b; + logic [10:0] shiftValE_uid32_fpToFxPTest_o; + wire [9:0] shiftValE_uid32_fpToFxPTest_q; + wire [5:0] shiftValRaw_uid33_fpToFxPTest_in; + wire [5:0] shiftValRaw_uid33_fpToFxPTest_b; + wire [5:0] maxShiftCst_uid34_fpToFxPTest_q; + wire [11:0] shiftOutOfRange_uid35_fpToFxPTest_a; + wire [11:0] shiftOutOfRange_uid35_fpToFxPTest_b; + logic [11:0] shiftOutOfRange_uid35_fpToFxPTest_o; + wire [0:0] shiftOutOfRange_uid35_fpToFxPTest_n; + wire [0:0] shiftVal_uid36_fpToFxPTest_s; + reg [5:0] shiftVal_uid36_fpToFxPTest_q; + wire [8:0] zPadd_uid37_fpToFxPTest_q; + wire [32:0] shifterIn_uid38_fpToFxPTest_q; + wire [31:0] maxPosValueU_uid40_fpToFxPTest_q; + wire [31:0] maxNegValueU_uid41_fpToFxPTest_q; + wire [33:0] zRightShiferNoStickyOut_uid43_fpToFxPTest_q; + wire [34:0] sPostRndFull_uid44_fpToFxPTest_a; + wire [34:0] sPostRndFull_uid44_fpToFxPTest_b; + logic [34:0] sPostRndFull_uid44_fpToFxPTest_o; + wire [34:0] sPostRndFull_uid44_fpToFxPTest_q; + wire [32:0] sPostRnd_uid45_fpToFxPTest_in; + wire [31:0] sPostRnd_uid45_fpToFxPTest_b; + wire [33:0] sPostRndFullMSBU_uid46_fpToFxPTest_in; + wire [0:0] sPostRndFullMSBU_uid46_fpToFxPTest_b; + wire [0:0] ovfPostRnd_uid47_fpToFxPTest_q; + wire [2:0] muxSelConc_uid48_fpToFxPTest_q; + reg [1:0] muxSel_uid49_fpToFxPTest_q; + wire [1:0] finalOut_uid51_fpToFxPTest_s; + reg [31:0] finalOut_uid51_fpToFxPTest_q; + wire [16:0] rightShiftStage0Idx1Rng16_uid55_rightShiferNoStickyOut_uid39_fpToFxPTest_b; + wire [15:0] rightShiftStage0Idx1Pad16_uid56_rightShiferNoStickyOut_uid39_fpToFxPTest_q; + wire [32:0] rightShiftStage0Idx1_uid57_rightShiferNoStickyOut_uid39_fpToFxPTest_q; + wire [0:0] rightShiftStage0Idx2Rng32_uid58_rightShiferNoStickyOut_uid39_fpToFxPTest_b; + wire [32:0] rightShiftStage0Idx2_uid60_rightShiferNoStickyOut_uid39_fpToFxPTest_q; + wire [32:0] rightShiftStage0Idx3_uid61_rightShiferNoStickyOut_uid39_fpToFxPTest_q; + wire [1:0] rightShiftStage0_uid63_rightShiferNoStickyOut_uid39_fpToFxPTest_s; + reg [32:0] rightShiftStage0_uid63_rightShiferNoStickyOut_uid39_fpToFxPTest_q; + wire [28:0] rightShiftStage1Idx1Rng4_uid64_rightShiferNoStickyOut_uid39_fpToFxPTest_b; + wire [3:0] rightShiftStage1Idx1Pad4_uid65_rightShiferNoStickyOut_uid39_fpToFxPTest_q; + wire [32:0] rightShiftStage1Idx1_uid66_rightShiferNoStickyOut_uid39_fpToFxPTest_q; + wire [24:0] rightShiftStage1Idx2Rng8_uid67_rightShiferNoStickyOut_uid39_fpToFxPTest_b; + wire [32:0] rightShiftStage1Idx2_uid69_rightShiferNoStickyOut_uid39_fpToFxPTest_q; + wire [20:0] rightShiftStage1Idx3Rng12_uid70_rightShiferNoStickyOut_uid39_fpToFxPTest_b; + wire [11:0] rightShiftStage1Idx3Pad12_uid71_rightShiferNoStickyOut_uid39_fpToFxPTest_q; + wire [32:0] rightShiftStage1Idx3_uid72_rightShiferNoStickyOut_uid39_fpToFxPTest_q; + wire [1:0] rightShiftStage1_uid74_rightShiferNoStickyOut_uid39_fpToFxPTest_s; + reg [32:0] rightShiftStage1_uid74_rightShiferNoStickyOut_uid39_fpToFxPTest_q; + wire [31:0] rightShiftStage2Idx1Rng1_uid75_rightShiferNoStickyOut_uid39_fpToFxPTest_b; + wire [32:0] rightShiftStage2Idx1_uid77_rightShiferNoStickyOut_uid39_fpToFxPTest_q; + wire [30:0] rightShiftStage2Idx2Rng2_uid78_rightShiferNoStickyOut_uid39_fpToFxPTest_b; + wire [1:0] rightShiftStage2Idx2Pad2_uid79_rightShiferNoStickyOut_uid39_fpToFxPTest_q; + wire [32:0] rightShiftStage2Idx2_uid80_rightShiferNoStickyOut_uid39_fpToFxPTest_q; + wire [29:0] rightShiftStage2Idx3Rng3_uid81_rightShiferNoStickyOut_uid39_fpToFxPTest_b; + wire [2:0] rightShiftStage2Idx3Pad3_uid82_rightShiferNoStickyOut_uid39_fpToFxPTest_q; + wire [32:0] rightShiftStage2Idx3_uid83_rightShiferNoStickyOut_uid39_fpToFxPTest_q; + wire [1:0] rightShiftStage2_uid85_rightShiferNoStickyOut_uid39_fpToFxPTest_s; + reg [32:0] rightShiftStage2_uid85_rightShiferNoStickyOut_uid39_fpToFxPTest_q; + wire [1:0] rightShiftStageSel5Dto4_uid62_rightShiferNoStickyOut_uid39_fpToFxPTest_merged_bit_select_b; + wire [1:0] rightShiftStageSel5Dto4_uid62_rightShiferNoStickyOut_uid39_fpToFxPTest_merged_bit_select_c; + wire [1:0] rightShiftStageSel5Dto4_uid62_rightShiferNoStickyOut_uid39_fpToFxPTest_merged_bit_select_d; + reg [31:0] redist0_sPostRnd_uid45_fpToFxPTest_b_1_q; + reg [5:0] redist1_shiftValRaw_uid33_fpToFxPTest_b_1_q; + reg [0:0] redist2_udf_uid30_fpToFxPTest_n_2_q; + reg [0:0] redist3_ovf_uid27_fpToFxPTest_n_2_q; + reg [0:0] redist4_signX_uid25_fpToFxPTest_b_2_q; + reg [0:0] redist5_expXIsMax_uid12_fpToFxPTest_q_2_q; + reg [22:0] redist6_frac_x_uid10_fpToFxPTest_b_1_q; + + + // maxNegValueU_uid41_fpToFxPTest(CONSTANT,40) + assign maxNegValueU_uid41_fpToFxPTest_q = 32'b00000000000000000000000000000000; + + // maxPosValueU_uid40_fpToFxPTest(CONSTANT,39) + assign maxPosValueU_uid40_fpToFxPTest_q = 32'b11111111111111111111111111111111; + + // VCC(CONSTANT,1) + assign VCC_q = 1'b1; + + // GND(CONSTANT,0) + assign GND_q = 1'b0; + + // rightShiftStage2Idx3Pad3_uid82_rightShiferNoStickyOut_uid39_fpToFxPTest(CONSTANT,81) + assign rightShiftStage2Idx3Pad3_uid82_rightShiferNoStickyOut_uid39_fpToFxPTest_q = 3'b000; + + // rightShiftStage2Idx3Rng3_uid81_rightShiferNoStickyOut_uid39_fpToFxPTest(BITSELECT,80)@1 + assign rightShiftStage2Idx3Rng3_uid81_rightShiferNoStickyOut_uid39_fpToFxPTest_b = rightShiftStage1_uid74_rightShiferNoStickyOut_uid39_fpToFxPTest_q[32:3]; + + // rightShiftStage2Idx3_uid83_rightShiferNoStickyOut_uid39_fpToFxPTest(BITJOIN,82)@1 + assign rightShiftStage2Idx3_uid83_rightShiferNoStickyOut_uid39_fpToFxPTest_q = {rightShiftStage2Idx3Pad3_uid82_rightShiferNoStickyOut_uid39_fpToFxPTest_q, rightShiftStage2Idx3Rng3_uid81_rightShiferNoStickyOut_uid39_fpToFxPTest_b}; + + // rightShiftStage2Idx2Pad2_uid79_rightShiferNoStickyOut_uid39_fpToFxPTest(CONSTANT,78) + assign rightShiftStage2Idx2Pad2_uid79_rightShiferNoStickyOut_uid39_fpToFxPTest_q = 2'b00; + + // rightShiftStage2Idx2Rng2_uid78_rightShiferNoStickyOut_uid39_fpToFxPTest(BITSELECT,77)@1 + assign rightShiftStage2Idx2Rng2_uid78_rightShiferNoStickyOut_uid39_fpToFxPTest_b = rightShiftStage1_uid74_rightShiferNoStickyOut_uid39_fpToFxPTest_q[32:2]; + + // rightShiftStage2Idx2_uid80_rightShiferNoStickyOut_uid39_fpToFxPTest(BITJOIN,79)@1 + assign rightShiftStage2Idx2_uid80_rightShiferNoStickyOut_uid39_fpToFxPTest_q = {rightShiftStage2Idx2Pad2_uid79_rightShiferNoStickyOut_uid39_fpToFxPTest_q, rightShiftStage2Idx2Rng2_uid78_rightShiferNoStickyOut_uid39_fpToFxPTest_b}; + + // rightShiftStage2Idx1Rng1_uid75_rightShiferNoStickyOut_uid39_fpToFxPTest(BITSELECT,74)@1 + assign rightShiftStage2Idx1Rng1_uid75_rightShiferNoStickyOut_uid39_fpToFxPTest_b = rightShiftStage1_uid74_rightShiferNoStickyOut_uid39_fpToFxPTest_q[32:1]; + + // rightShiftStage2Idx1_uid77_rightShiferNoStickyOut_uid39_fpToFxPTest(BITJOIN,76)@1 + assign rightShiftStage2Idx1_uid77_rightShiferNoStickyOut_uid39_fpToFxPTest_q = {GND_q, rightShiftStage2Idx1Rng1_uid75_rightShiferNoStickyOut_uid39_fpToFxPTest_b}; + + // rightShiftStage1Idx3Pad12_uid71_rightShiferNoStickyOut_uid39_fpToFxPTest(CONSTANT,70) + assign rightShiftStage1Idx3Pad12_uid71_rightShiferNoStickyOut_uid39_fpToFxPTest_q = 12'b000000000000; + + // rightShiftStage1Idx3Rng12_uid70_rightShiferNoStickyOut_uid39_fpToFxPTest(BITSELECT,69)@1 + assign rightShiftStage1Idx3Rng12_uid70_rightShiferNoStickyOut_uid39_fpToFxPTest_b = rightShiftStage0_uid63_rightShiferNoStickyOut_uid39_fpToFxPTest_q[32:12]; + + // rightShiftStage1Idx3_uid72_rightShiferNoStickyOut_uid39_fpToFxPTest(BITJOIN,71)@1 + assign rightShiftStage1Idx3_uid72_rightShiferNoStickyOut_uid39_fpToFxPTest_q = {rightShiftStage1Idx3Pad12_uid71_rightShiferNoStickyOut_uid39_fpToFxPTest_q, rightShiftStage1Idx3Rng12_uid70_rightShiferNoStickyOut_uid39_fpToFxPTest_b}; + + // cstAllZWE_uid8_fpToFxPTest(CONSTANT,7) + assign cstAllZWE_uid8_fpToFxPTest_q = 8'b00000000; + + // rightShiftStage1Idx2Rng8_uid67_rightShiferNoStickyOut_uid39_fpToFxPTest(BITSELECT,66)@1 + assign rightShiftStage1Idx2Rng8_uid67_rightShiferNoStickyOut_uid39_fpToFxPTest_b = rightShiftStage0_uid63_rightShiferNoStickyOut_uid39_fpToFxPTest_q[32:8]; + + // rightShiftStage1Idx2_uid69_rightShiferNoStickyOut_uid39_fpToFxPTest(BITJOIN,68)@1 + assign rightShiftStage1Idx2_uid69_rightShiferNoStickyOut_uid39_fpToFxPTest_q = {cstAllZWE_uid8_fpToFxPTest_q, rightShiftStage1Idx2Rng8_uid67_rightShiferNoStickyOut_uid39_fpToFxPTest_b}; + + // rightShiftStage1Idx1Pad4_uid65_rightShiferNoStickyOut_uid39_fpToFxPTest(CONSTANT,64) + assign rightShiftStage1Idx1Pad4_uid65_rightShiferNoStickyOut_uid39_fpToFxPTest_q = 4'b0000; + + // rightShiftStage1Idx1Rng4_uid64_rightShiferNoStickyOut_uid39_fpToFxPTest(BITSELECT,63)@1 + assign rightShiftStage1Idx1Rng4_uid64_rightShiferNoStickyOut_uid39_fpToFxPTest_b = rightShiftStage0_uid63_rightShiferNoStickyOut_uid39_fpToFxPTest_q[32:4]; + + // rightShiftStage1Idx1_uid66_rightShiferNoStickyOut_uid39_fpToFxPTest(BITJOIN,65)@1 + assign rightShiftStage1Idx1_uid66_rightShiferNoStickyOut_uid39_fpToFxPTest_q = {rightShiftStage1Idx1Pad4_uid65_rightShiferNoStickyOut_uid39_fpToFxPTest_q, rightShiftStage1Idx1Rng4_uid64_rightShiferNoStickyOut_uid39_fpToFxPTest_b}; + + // rightShiftStage0Idx3_uid61_rightShiferNoStickyOut_uid39_fpToFxPTest(CONSTANT,60) + assign rightShiftStage0Idx3_uid61_rightShiferNoStickyOut_uid39_fpToFxPTest_q = 33'b000000000000000000000000000000000; + + // rightShiftStage0Idx2Rng32_uid58_rightShiferNoStickyOut_uid39_fpToFxPTest(BITSELECT,57)@1 + assign rightShiftStage0Idx2Rng32_uid58_rightShiferNoStickyOut_uid39_fpToFxPTest_b = shifterIn_uid38_fpToFxPTest_q[32:32]; + + // rightShiftStage0Idx2_uid60_rightShiferNoStickyOut_uid39_fpToFxPTest(BITJOIN,59)@1 + assign rightShiftStage0Idx2_uid60_rightShiferNoStickyOut_uid39_fpToFxPTest_q = {maxNegValueU_uid41_fpToFxPTest_q, rightShiftStage0Idx2Rng32_uid58_rightShiferNoStickyOut_uid39_fpToFxPTest_b}; + + // rightShiftStage0Idx1Pad16_uid56_rightShiferNoStickyOut_uid39_fpToFxPTest(CONSTANT,55) + assign rightShiftStage0Idx1Pad16_uid56_rightShiferNoStickyOut_uid39_fpToFxPTest_q = 16'b0000000000000000; + + // rightShiftStage0Idx1Rng16_uid55_rightShiferNoStickyOut_uid39_fpToFxPTest(BITSELECT,54)@1 + assign rightShiftStage0Idx1Rng16_uid55_rightShiferNoStickyOut_uid39_fpToFxPTest_b = shifterIn_uid38_fpToFxPTest_q[32:16]; + + // rightShiftStage0Idx1_uid57_rightShiferNoStickyOut_uid39_fpToFxPTest(BITJOIN,56)@1 + assign rightShiftStage0Idx1_uid57_rightShiferNoStickyOut_uid39_fpToFxPTest_q = {rightShiftStage0Idx1Pad16_uid56_rightShiferNoStickyOut_uid39_fpToFxPTest_q, rightShiftStage0Idx1Rng16_uid55_rightShiferNoStickyOut_uid39_fpToFxPTest_b}; + + // exp_x_uid9_fpToFxPTest(BITSELECT,8)@0 + assign exp_x_uid9_fpToFxPTest_b = a[30:23]; + + // excZ_x_uid11_fpToFxPTest(LOGICAL,10)@0 + 1 + assign excZ_x_uid11_fpToFxPTest_qi = exp_x_uid9_fpToFxPTest_b == cstAllZWE_uid8_fpToFxPTest_q ? 1'b1 : 1'b0; + dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) + excZ_x_uid11_fpToFxPTest_delay ( .xin(excZ_x_uid11_fpToFxPTest_qi), .xout(excZ_x_uid11_fpToFxPTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // invExcXZ_uid22_fpToFxPTest(LOGICAL,21)@1 + assign invExcXZ_uid22_fpToFxPTest_q = ~ (excZ_x_uid11_fpToFxPTest_q); + + // frac_x_uid10_fpToFxPTest(BITSELECT,9)@0 + assign frac_x_uid10_fpToFxPTest_b = a[22:0]; + + // redist6_frac_x_uid10_fpToFxPTest_b_1(DELAY,93) + dspba_delay_ver #( .width(23), .depth(1), .reset_kind("ASYNC") ) + redist6_frac_x_uid10_fpToFxPTest_b_1 ( .xin(frac_x_uid10_fpToFxPTest_b), .xout(redist6_frac_x_uid10_fpToFxPTest_b_1_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // oFracX_uid23_fpToFxPTest(BITJOIN,22)@1 + assign oFracX_uid23_fpToFxPTest_q = {invExcXZ_uid22_fpToFxPTest_q, redist6_frac_x_uid10_fpToFxPTest_b_1_q}; + + // zPadd_uid37_fpToFxPTest(CONSTANT,36) + assign zPadd_uid37_fpToFxPTest_q = 9'b000000000; + + // shifterIn_uid38_fpToFxPTest(BITJOIN,37)@1 + assign shifterIn_uid38_fpToFxPTest_q = {oFracX_uid23_fpToFxPTest_q, zPadd_uid37_fpToFxPTest_q}; + + // rightShiftStage0_uid63_rightShiferNoStickyOut_uid39_fpToFxPTest(MUX,62)@1 + assign rightShiftStage0_uid63_rightShiferNoStickyOut_uid39_fpToFxPTest_s = rightShiftStageSel5Dto4_uid62_rightShiferNoStickyOut_uid39_fpToFxPTest_merged_bit_select_b; + always @(rightShiftStage0_uid63_rightShiferNoStickyOut_uid39_fpToFxPTest_s or en or shifterIn_uid38_fpToFxPTest_q or rightShiftStage0Idx1_uid57_rightShiferNoStickyOut_uid39_fpToFxPTest_q or rightShiftStage0Idx2_uid60_rightShiferNoStickyOut_uid39_fpToFxPTest_q or rightShiftStage0Idx3_uid61_rightShiferNoStickyOut_uid39_fpToFxPTest_q) + begin + unique case (rightShiftStage0_uid63_rightShiferNoStickyOut_uid39_fpToFxPTest_s) + 2'b00 : rightShiftStage0_uid63_rightShiferNoStickyOut_uid39_fpToFxPTest_q = shifterIn_uid38_fpToFxPTest_q; + 2'b01 : rightShiftStage0_uid63_rightShiferNoStickyOut_uid39_fpToFxPTest_q = rightShiftStage0Idx1_uid57_rightShiferNoStickyOut_uid39_fpToFxPTest_q; + 2'b10 : rightShiftStage0_uid63_rightShiferNoStickyOut_uid39_fpToFxPTest_q = rightShiftStage0Idx2_uid60_rightShiferNoStickyOut_uid39_fpToFxPTest_q; + 2'b11 : rightShiftStage0_uid63_rightShiferNoStickyOut_uid39_fpToFxPTest_q = rightShiftStage0Idx3_uid61_rightShiferNoStickyOut_uid39_fpToFxPTest_q; + default : rightShiftStage0_uid63_rightShiferNoStickyOut_uid39_fpToFxPTest_q = 33'b0; + endcase + end + + // rightShiftStage1_uid74_rightShiferNoStickyOut_uid39_fpToFxPTest(MUX,73)@1 + assign rightShiftStage1_uid74_rightShiferNoStickyOut_uid39_fpToFxPTest_s = rightShiftStageSel5Dto4_uid62_rightShiferNoStickyOut_uid39_fpToFxPTest_merged_bit_select_c; + always @(rightShiftStage1_uid74_rightShiferNoStickyOut_uid39_fpToFxPTest_s or en or rightShiftStage0_uid63_rightShiferNoStickyOut_uid39_fpToFxPTest_q or rightShiftStage1Idx1_uid66_rightShiferNoStickyOut_uid39_fpToFxPTest_q or rightShiftStage1Idx2_uid69_rightShiferNoStickyOut_uid39_fpToFxPTest_q or rightShiftStage1Idx3_uid72_rightShiferNoStickyOut_uid39_fpToFxPTest_q) + begin + unique case (rightShiftStage1_uid74_rightShiferNoStickyOut_uid39_fpToFxPTest_s) + 2'b00 : rightShiftStage1_uid74_rightShiferNoStickyOut_uid39_fpToFxPTest_q = rightShiftStage0_uid63_rightShiferNoStickyOut_uid39_fpToFxPTest_q; + 2'b01 : rightShiftStage1_uid74_rightShiferNoStickyOut_uid39_fpToFxPTest_q = rightShiftStage1Idx1_uid66_rightShiferNoStickyOut_uid39_fpToFxPTest_q; + 2'b10 : rightShiftStage1_uid74_rightShiferNoStickyOut_uid39_fpToFxPTest_q = rightShiftStage1Idx2_uid69_rightShiferNoStickyOut_uid39_fpToFxPTest_q; + 2'b11 : rightShiftStage1_uid74_rightShiferNoStickyOut_uid39_fpToFxPTest_q = rightShiftStage1Idx3_uid72_rightShiferNoStickyOut_uid39_fpToFxPTest_q; + default : rightShiftStage1_uid74_rightShiferNoStickyOut_uid39_fpToFxPTest_q = 33'b0; + endcase + end + + // maxShiftCst_uid34_fpToFxPTest(CONSTANT,33) + assign maxShiftCst_uid34_fpToFxPTest_q = 6'b100001; + + // ovfExpVal_uid31_fpToFxPTest(CONSTANT,30) + assign ovfExpVal_uid31_fpToFxPTest_q = 9'b010011110; + + // shiftValE_uid32_fpToFxPTest(SUB,31)@0 + assign shiftValE_uid32_fpToFxPTest_a = {{2{ovfExpVal_uid31_fpToFxPTest_q[8]}}, ovfExpVal_uid31_fpToFxPTest_q}; + assign shiftValE_uid32_fpToFxPTest_b = {3'b000, exp_x_uid9_fpToFxPTest_b}; + assign shiftValE_uid32_fpToFxPTest_o = $signed(shiftValE_uid32_fpToFxPTest_a) - $signed(shiftValE_uid32_fpToFxPTest_b); + assign shiftValE_uid32_fpToFxPTest_q = shiftValE_uid32_fpToFxPTest_o[9:0]; + + // shiftValRaw_uid33_fpToFxPTest(BITSELECT,32)@0 + assign shiftValRaw_uid33_fpToFxPTest_in = shiftValE_uid32_fpToFxPTest_q[5:0]; + assign shiftValRaw_uid33_fpToFxPTest_b = shiftValRaw_uid33_fpToFxPTest_in[5:0]; + + // redist1_shiftValRaw_uid33_fpToFxPTest_b_1(DELAY,88) + dspba_delay_ver #( .width(6), .depth(1), .reset_kind("ASYNC") ) + redist1_shiftValRaw_uid33_fpToFxPTest_b_1 ( .xin(shiftValRaw_uid33_fpToFxPTest_b), .xout(redist1_shiftValRaw_uid33_fpToFxPTest_b_1_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // shiftOutOfRange_uid35_fpToFxPTest(COMPARE,34)@0 + 1 + assign shiftOutOfRange_uid35_fpToFxPTest_a = {{2{shiftValE_uid32_fpToFxPTest_q[9]}}, shiftValE_uid32_fpToFxPTest_q}; + assign shiftOutOfRange_uid35_fpToFxPTest_b = {6'b000000, maxShiftCst_uid34_fpToFxPTest_q}; + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + shiftOutOfRange_uid35_fpToFxPTest_o <= 12'b0; + end + else if (en == 1'b1) + begin + shiftOutOfRange_uid35_fpToFxPTest_o <= $signed(shiftOutOfRange_uid35_fpToFxPTest_a) - $signed(shiftOutOfRange_uid35_fpToFxPTest_b); + end + end + assign shiftOutOfRange_uid35_fpToFxPTest_n[0] = ~ (shiftOutOfRange_uid35_fpToFxPTest_o[11]); + + // shiftVal_uid36_fpToFxPTest(MUX,35)@1 + assign shiftVal_uid36_fpToFxPTest_s = shiftOutOfRange_uid35_fpToFxPTest_n; + always @(shiftVal_uid36_fpToFxPTest_s or en or redist1_shiftValRaw_uid33_fpToFxPTest_b_1_q or maxShiftCst_uid34_fpToFxPTest_q) + begin + unique case (shiftVal_uid36_fpToFxPTest_s) + 1'b0 : shiftVal_uid36_fpToFxPTest_q = redist1_shiftValRaw_uid33_fpToFxPTest_b_1_q; + 1'b1 : shiftVal_uid36_fpToFxPTest_q = maxShiftCst_uid34_fpToFxPTest_q; + default : shiftVal_uid36_fpToFxPTest_q = 6'b0; + endcase + end + + // rightShiftStageSel5Dto4_uid62_rightShiferNoStickyOut_uid39_fpToFxPTest_merged_bit_select(BITSELECT,86)@1 + assign rightShiftStageSel5Dto4_uid62_rightShiferNoStickyOut_uid39_fpToFxPTest_merged_bit_select_b = shiftVal_uid36_fpToFxPTest_q[5:4]; + assign rightShiftStageSel5Dto4_uid62_rightShiferNoStickyOut_uid39_fpToFxPTest_merged_bit_select_c = shiftVal_uid36_fpToFxPTest_q[3:2]; + assign rightShiftStageSel5Dto4_uid62_rightShiferNoStickyOut_uid39_fpToFxPTest_merged_bit_select_d = shiftVal_uid36_fpToFxPTest_q[1:0]; + + // rightShiftStage2_uid85_rightShiferNoStickyOut_uid39_fpToFxPTest(MUX,84)@1 + 1 + assign rightShiftStage2_uid85_rightShiferNoStickyOut_uid39_fpToFxPTest_s = rightShiftStageSel5Dto4_uid62_rightShiferNoStickyOut_uid39_fpToFxPTest_merged_bit_select_d; + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + rightShiftStage2_uid85_rightShiferNoStickyOut_uid39_fpToFxPTest_q <= 33'b0; + end + else if (en == 1'b1) + begin + unique case (rightShiftStage2_uid85_rightShiferNoStickyOut_uid39_fpToFxPTest_s) + 2'b00 : rightShiftStage2_uid85_rightShiferNoStickyOut_uid39_fpToFxPTest_q <= rightShiftStage1_uid74_rightShiferNoStickyOut_uid39_fpToFxPTest_q; + 2'b01 : rightShiftStage2_uid85_rightShiferNoStickyOut_uid39_fpToFxPTest_q <= rightShiftStage2Idx1_uid77_rightShiferNoStickyOut_uid39_fpToFxPTest_q; + 2'b10 : rightShiftStage2_uid85_rightShiferNoStickyOut_uid39_fpToFxPTest_q <= rightShiftStage2Idx2_uid80_rightShiferNoStickyOut_uid39_fpToFxPTest_q; + 2'b11 : rightShiftStage2_uid85_rightShiferNoStickyOut_uid39_fpToFxPTest_q <= rightShiftStage2Idx3_uid83_rightShiferNoStickyOut_uid39_fpToFxPTest_q; + default : rightShiftStage2_uid85_rightShiferNoStickyOut_uid39_fpToFxPTest_q <= 33'b0; + endcase + end + end + + // zRightShiferNoStickyOut_uid43_fpToFxPTest(BITJOIN,42)@2 + assign zRightShiferNoStickyOut_uid43_fpToFxPTest_q = {GND_q, rightShiftStage2_uid85_rightShiferNoStickyOut_uid39_fpToFxPTest_q}; + + // sPostRndFull_uid44_fpToFxPTest(ADD,43)@2 + assign sPostRndFull_uid44_fpToFxPTest_a = {1'b0, zRightShiferNoStickyOut_uid43_fpToFxPTest_q}; + assign sPostRndFull_uid44_fpToFxPTest_b = {34'b0000000000000000000000000000000000, VCC_q}; + assign sPostRndFull_uid44_fpToFxPTest_o = $unsigned(sPostRndFull_uid44_fpToFxPTest_a) + $unsigned(sPostRndFull_uid44_fpToFxPTest_b); + assign sPostRndFull_uid44_fpToFxPTest_q = sPostRndFull_uid44_fpToFxPTest_o[34:0]; + + // sPostRnd_uid45_fpToFxPTest(BITSELECT,44)@2 + assign sPostRnd_uid45_fpToFxPTest_in = sPostRndFull_uid44_fpToFxPTest_q[32:0]; + assign sPostRnd_uid45_fpToFxPTest_b = sPostRnd_uid45_fpToFxPTest_in[32:1]; + + // redist0_sPostRnd_uid45_fpToFxPTest_b_1(DELAY,87) + dspba_delay_ver #( .width(32), .depth(1), .reset_kind("ASYNC") ) + redist0_sPostRnd_uid45_fpToFxPTest_b_1 ( .xin(sPostRnd_uid45_fpToFxPTest_b), .xout(redist0_sPostRnd_uid45_fpToFxPTest_b_1_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // signX_uid25_fpToFxPTest(BITSELECT,24)@0 + assign signX_uid25_fpToFxPTest_b = a[31:31]; + + // redist4_signX_uid25_fpToFxPTest_b_2(DELAY,91) + dspba_delay_ver #( .width(1), .depth(2), .reset_kind("ASYNC") ) + redist4_signX_uid25_fpToFxPTest_b_2 ( .xin(signX_uid25_fpToFxPTest_b), .xout(redist4_signX_uid25_fpToFxPTest_b_2_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // udfExpVal_uid29_fpToFxPTest(CONSTANT,28) + assign udfExpVal_uid29_fpToFxPTest_q = 8'b01111101; + + // udf_uid30_fpToFxPTest(COMPARE,29)@0 + 1 + assign udf_uid30_fpToFxPTest_a = {{3{udfExpVal_uid29_fpToFxPTest_q[7]}}, udfExpVal_uid29_fpToFxPTest_q}; + assign udf_uid30_fpToFxPTest_b = {3'b000, exp_x_uid9_fpToFxPTest_b}; + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + udf_uid30_fpToFxPTest_o <= 11'b0; + end + else if (en == 1'b1) + begin + udf_uid30_fpToFxPTest_o <= $signed(udf_uid30_fpToFxPTest_a) - $signed(udf_uid30_fpToFxPTest_b); + end + end + assign udf_uid30_fpToFxPTest_n[0] = ~ (udf_uid30_fpToFxPTest_o[10]); + + // redist2_udf_uid30_fpToFxPTest_n_2(DELAY,89) + dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) + redist2_udf_uid30_fpToFxPTest_n_2 ( .xin(udf_uid30_fpToFxPTest_n), .xout(redist2_udf_uid30_fpToFxPTest_n_2_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // sPostRndFullMSBU_uid46_fpToFxPTest(BITSELECT,45)@2 + assign sPostRndFullMSBU_uid46_fpToFxPTest_in = sPostRndFull_uid44_fpToFxPTest_q[33:0]; + assign sPostRndFullMSBU_uid46_fpToFxPTest_b = sPostRndFullMSBU_uid46_fpToFxPTest_in[33:33]; + + // ovfExpVal_uid26_fpToFxPTest(CONSTANT,25) + assign ovfExpVal_uid26_fpToFxPTest_q = 9'b010011111; + + // ovf_uid27_fpToFxPTest(COMPARE,26)@0 + 1 + assign ovf_uid27_fpToFxPTest_a = {3'b000, exp_x_uid9_fpToFxPTest_b}; + assign ovf_uid27_fpToFxPTest_b = {{2{ovfExpVal_uid26_fpToFxPTest_q[8]}}, ovfExpVal_uid26_fpToFxPTest_q}; + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + ovf_uid27_fpToFxPTest_o <= 11'b0; + end + else if (en == 1'b1) + begin + ovf_uid27_fpToFxPTest_o <= $signed(ovf_uid27_fpToFxPTest_a) - $signed(ovf_uid27_fpToFxPTest_b); + end + end + assign ovf_uid27_fpToFxPTest_n[0] = ~ (ovf_uid27_fpToFxPTest_o[10]); + + // redist3_ovf_uid27_fpToFxPTest_n_2(DELAY,90) + dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) + redist3_ovf_uid27_fpToFxPTest_n_2 ( .xin(ovf_uid27_fpToFxPTest_n), .xout(redist3_ovf_uid27_fpToFxPTest_n_2_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // negOrOvf_uid28_fpToFxPTest(LOGICAL,27)@2 + assign negOrOvf_uid28_fpToFxPTest_q = redist4_signX_uid25_fpToFxPTest_b_2_q | redist3_ovf_uid27_fpToFxPTest_n_2_q; + + // cstZeroWF_uid7_fpToFxPTest(CONSTANT,6) + assign cstZeroWF_uid7_fpToFxPTest_q = 23'b00000000000000000000000; + + // fracXIsZero_uid13_fpToFxPTest(LOGICAL,12)@1 + 1 + assign fracXIsZero_uid13_fpToFxPTest_qi = cstZeroWF_uid7_fpToFxPTest_q == redist6_frac_x_uid10_fpToFxPTest_b_1_q ? 1'b1 : 1'b0; + dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) + fracXIsZero_uid13_fpToFxPTest_delay ( .xin(fracXIsZero_uid13_fpToFxPTest_qi), .xout(fracXIsZero_uid13_fpToFxPTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // cstAllOWE_uid6_fpToFxPTest(CONSTANT,5) + assign cstAllOWE_uid6_fpToFxPTest_q = 8'b11111111; + + // expXIsMax_uid12_fpToFxPTest(LOGICAL,11)@0 + 1 + assign expXIsMax_uid12_fpToFxPTest_qi = exp_x_uid9_fpToFxPTest_b == cstAllOWE_uid6_fpToFxPTest_q ? 1'b1 : 1'b0; + dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) + expXIsMax_uid12_fpToFxPTest_delay ( .xin(expXIsMax_uid12_fpToFxPTest_qi), .xout(expXIsMax_uid12_fpToFxPTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // redist5_expXIsMax_uid12_fpToFxPTest_q_2(DELAY,92) + dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) + redist5_expXIsMax_uid12_fpToFxPTest_q_2 ( .xin(expXIsMax_uid12_fpToFxPTest_q), .xout(redist5_expXIsMax_uid12_fpToFxPTest_q_2_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // excI_x_uid15_fpToFxPTest(LOGICAL,14)@2 + assign excI_x_uid15_fpToFxPTest_q = redist5_expXIsMax_uid12_fpToFxPTest_q_2_q & fracXIsZero_uid13_fpToFxPTest_q; + + // fracXIsNotZero_uid14_fpToFxPTest(LOGICAL,13)@2 + assign fracXIsNotZero_uid14_fpToFxPTest_q = ~ (fracXIsZero_uid13_fpToFxPTest_q); + + // excN_x_uid16_fpToFxPTest(LOGICAL,15)@2 + assign excN_x_uid16_fpToFxPTest_q = redist5_expXIsMax_uid12_fpToFxPTest_q_2_q & fracXIsNotZero_uid14_fpToFxPTest_q; + + // ovfPostRnd_uid47_fpToFxPTest(LOGICAL,46)@2 + assign ovfPostRnd_uid47_fpToFxPTest_q = excN_x_uid16_fpToFxPTest_q | excI_x_uid15_fpToFxPTest_q | negOrOvf_uid28_fpToFxPTest_q | sPostRndFullMSBU_uid46_fpToFxPTest_b; + + // muxSelConc_uid48_fpToFxPTest(BITJOIN,47)@2 + assign muxSelConc_uid48_fpToFxPTest_q = {redist4_signX_uid25_fpToFxPTest_b_2_q, redist2_udf_uid30_fpToFxPTest_n_2_q, ovfPostRnd_uid47_fpToFxPTest_q}; + + // muxSel_uid49_fpToFxPTest(LOOKUP,48)@2 + 1 + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + muxSel_uid49_fpToFxPTest_q <= 2'b00; + end + else if (en == 1'b1) + begin + unique case (muxSelConc_uid48_fpToFxPTest_q) + 3'b000 : muxSel_uid49_fpToFxPTest_q <= 2'b00; + 3'b001 : muxSel_uid49_fpToFxPTest_q <= 2'b01; + 3'b010 : muxSel_uid49_fpToFxPTest_q <= 2'b11; + 3'b011 : muxSel_uid49_fpToFxPTest_q <= 2'b00; + 3'b100 : muxSel_uid49_fpToFxPTest_q <= 2'b10; + 3'b101 : muxSel_uid49_fpToFxPTest_q <= 2'b10; + 3'b110 : muxSel_uid49_fpToFxPTest_q <= 2'b10; + 3'b111 : muxSel_uid49_fpToFxPTest_q <= 2'b10; + default : begin + // unreachable + muxSel_uid49_fpToFxPTest_q <= 2'bxx; + end + endcase + end + end + + // finalOut_uid51_fpToFxPTest(MUX,50)@3 + assign finalOut_uid51_fpToFxPTest_s = muxSel_uid49_fpToFxPTest_q; + always @(finalOut_uid51_fpToFxPTest_s or en or redist0_sPostRnd_uid45_fpToFxPTest_b_1_q or maxPosValueU_uid40_fpToFxPTest_q or maxNegValueU_uid41_fpToFxPTest_q) + begin + unique case (finalOut_uid51_fpToFxPTest_s) + 2'b00 : finalOut_uid51_fpToFxPTest_q = redist0_sPostRnd_uid45_fpToFxPTest_b_1_q; + 2'b01 : finalOut_uid51_fpToFxPTest_q = maxPosValueU_uid40_fpToFxPTest_q; + 2'b10 : finalOut_uid51_fpToFxPTest_q = maxNegValueU_uid41_fpToFxPTest_q; + 2'b11 : finalOut_uid51_fpToFxPTest_q = maxNegValueU_uid41_fpToFxPTest_q; + default : finalOut_uid51_fpToFxPTest_q = 32'b0; + endcase + end + + // xOut(GPOUT,4)@3 + assign q = finalOut_uid51_fpToFxPTest_q; + +endmodule diff --git a/hw/rtl/fp_cores/altera/acl_gen.log b/hw/rtl/fp_cores/altera/acl_gen.log new file mode 100644 index 00000000..3e694b39 --- /dev/null +++ b/hw/rtl/fp_cores/altera/acl_gen.log @@ -0,0 +1,169 @@ +starting execution ... +build model options ... +argc=21 +Generation context: + HardFP is enabled enabling set to true + Faithful rounding constraint detected + Will not generate valid and channel signals + The new component name is acl_fdiv + Frequency 250MHz + Deployment FPGA Arria10 +Estimated resources LUTs 539, DSPs 5, RAMBits 32768, RAMBlocks 3 +The pipeline depth of the block is 15 cycle(s) +@@start +@name FPDiv@ +@latency 15@ +@LUT 539@ +@DSP 5@ +@RAMBits 32768@ +@RAMBlockUsage 3@ +@enable 1@ +@subnormals 0@ +@error 1.00@ +@rounding NA@ +@method polynomial approximation@ +@inPort 0 fpieee 8 23@ +@inPort 1 fpieee 8 23@ +@outPort 0 fpieee 8 23@ +@nochanvalid 1@ +@@end +starting execution ... +build model options ... +argc=20 +Generation context: + HardFP is enabled enabling set to true + Faithful rounding constraint detected + Will not generate valid and channel signals + The new component name is acl_fsqrt + Frequency 250MHz + Deployment FPGA Arria10 +Estimated resources LUTs 271, DSPs 3, RAMBits 15872, RAMBlocks 3 +The pipeline depth of the block is 10 cycle(s) +@@start +@name FPSqrt@ +@latency 10@ +@LUT 271@ +@DSP 3@ +@RAMBits 15872@ +@RAMBlockUsage 3@ +@enable 1@ +@subnormals 0@ +@error 1.00@ +@rounding NA@ +@method polynomial approximation@ +@inPort 0 fpieee 8 23@ +@outPort 0 fpieee 8 23@ +@nochanvalid 1@ +@@end +starting execution ... +build model options ... +argc=23 +Generation context: + HardFP is enabled enabling set to true + Faithful rounding constraint detected + Will not generate valid and channel signals + The new component name is acl_ftoi + Frequency 250MHz + Deployment FPGA Arria10 +Estimated resources LUTs 327, DSPs 0, RAMBits 0, RAMBlocks 0 +The pipeline depth of the block is 3 cycle(s) +@@start +@name FPToFXP@ +@latency 3@ +@LUT 327@ +@DSP 0@ +@RAMBits 0@ +@RAMBlockUsage 0@ +@enable 1@ +@subnormals 0@ +@error 1.00@ +@rounding NA@ +@method default@ +@inPort 0 fpieee 8 23@ +@outPort 0 fxp 32 0 1@ +@nochanvalid 1@ +@@end +starting execution ... +build model options ... +argc=23 +Generation context: + HardFP is enabled enabling set to true + Faithful rounding constraint detected + Will not generate valid and channel signals + The new component name is acl_ftou + Frequency 250MHz + Deployment FPGA Arria10 +Estimated resources LUTs 287, DSPs 0, RAMBits 0, RAMBlocks 0 +The pipeline depth of the block is 3 cycle(s) +@@start +@name FPToFXP@ +@latency 3@ +@LUT 287@ +@DSP 0@ +@RAMBits 0@ +@RAMBlockUsage 0@ +@enable 1@ +@subnormals 0@ +@error 1.00@ +@rounding NA@ +@method default@ +@inPort 0 fpieee 8 23@ +@outPort 0 fxp 32 0 0@ +@nochanvalid 1@ +@@end +starting execution ... +build model options ... +argc=23 +Generation context: + HardFP is enabled enabling set to true + Faithful rounding constraint detected + Will not generate valid and channel signals + The new component name is acl_itof + Frequency 250MHz + Deployment FPGA Arria10 +Estimated resources LUTs 397, DSPs 0, RAMBits 0, RAMBlocks 0 +The pipeline depth of the block is 7 cycle(s) +@@start +@name FXPToFP@ +@latency 7@ +@LUT 397@ +@DSP 0@ +@RAMBits 0@ +@RAMBlockUsage 0@ +@enable 1@ +@subnormals 0@ +@error 1.00@ +@rounding NA@ +@method default@ +@inPort 0 fxp 32 0 1@ +@outPort 0 fpieee 8 23@ +@nochanvalid 1@ +@@end +starting execution ... +build model options ... +argc=23 +Generation context: + HardFP is enabled enabling set to true + Faithful rounding constraint detected + Will not generate valid and channel signals + The new component name is acl_utof + Frequency 300MHz + Deployment FPGA Arria10 +Estimated resources LUTs 363, DSPs 0, RAMBits 0, RAMBlocks 0 +The pipeline depth of the block is 7 cycle(s) +@@start +@name FXPToFP@ +@latency 7@ +@LUT 363@ +@DSP 0@ +@RAMBits 0@ +@RAMBlockUsage 0@ +@enable 1@ +@subnormals 0@ +@error 1.00@ +@rounding NA@ +@method default@ +@inPort 0 fxp 32 0 0@ +@outPort 0 fpieee 8 23@ +@nochanvalid 1@ +@@end diff --git a/hw/rtl/fp_cores/altera/acl_gen.sh b/hw/rtl/fp_cores/altera/acl_gen.sh new file mode 100755 index 00000000..f26058eb --- /dev/null +++ b/hw/rtl/fp_cores/altera/acl_gen.sh @@ -0,0 +1,25 @@ +#!/bin/bash + +CMD_POLY_EVAL_PATH=$QUARTUS_HOME/dspba/backend/linux64 + +OPTIONS="-target Arria10 -lang verilog -enableHardFP 1 -printMachineReadable -faithfulRounding -noChanValid -enable -speedgrade 2" + +export LD_LIBRARY_PATH=$CMD_POLY_EVAL_PATH:$LD_LIBRARY_PATH + +CMD="$CMD_POLY_EVAL_PATH/cmdPolyEval $OPTIONS" + +EXP_BITS=8 +MAN_BITS=23 +FBITS="f$(($EXP_BITS + $MAN_BITS + 1))" + +echo Generating IP cores for $FBITS +{ + $CMD -name acl_fdiv -frequency 250 FPDiv $EXP_BITS $MAN_BITS 0 + $CMD -name acl_fsqrt -frequency 250 FPSqrt $EXP_BITS $MAN_BITS + $CMD -name acl_ftoi -frequency 250 FPToFXP $EXP_BITS $MAN_BITS 32 0 1 + $CMD -name acl_ftou -frequency 250 FPToFXP $EXP_BITS $MAN_BITS 32 0 0 + $CMD -name acl_itof -frequency 250 FXPToFP 32 0 1 $EXP_BITS $MAN_BITS + $CMD -name acl_utof -frequency 300 FXPToFP 32 0 0 $EXP_BITS $MAN_BITS +} > acl_gen.log 2>&1 + +#cp $QUARTUS_HOME/dspba/backend/Libraries/sv/base/dspba_library_ver.sv . \ No newline at end of file diff --git a/hw/rtl/fp_cores/altera/acl_itof.sv b/hw/rtl/fp_cores/altera/acl_itof.sv new file mode 100644 index 00000000..5e6a74aa --- /dev/null +++ b/hw/rtl/fp_cores/altera/acl_itof.sv @@ -0,0 +1,520 @@ +// ------------------------------------------------------------------------- +// High Level Design Compiler for Intel(R) FPGAs Version 17.1 (Release Build #273) +// Quartus Prime development tool and MATLAB/Simulink Interface +// +// Legal Notice: Copyright 2017 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly +// subject to the terms and conditions of the Intel FPGA Software License +// Agreement, Intel MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for +// the sole purpose of programming logic devices manufactured by Intel +// and sold by Intel or its authorized distributors. Please refer to the +// applicable agreement for further details. +// --------------------------------------------------------------------------- + +// SystemVerilog created from acl_itof +// SystemVerilog created on Wed Sep 2 07:11:09 2020 + + +(* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007; -name MESSAGE_DISABLE 10958" *) +module acl_itof ( + input wire [31:0] a, + input wire [0:0] en, + output wire [31:0] q, + input wire clk, + input wire areset + ); + + wire [0:0] GND_q; + wire [0:0] signX_uid6_fxpToFPTest_b; + wire [31:0] xXorSign_uid7_fxpToFPTest_b; + wire [31:0] xXorSign_uid7_fxpToFPTest_qi; + reg [31:0] xXorSign_uid7_fxpToFPTest_q; + wire [32:0] yE_uid8_fxpToFPTest_a; + wire [32:0] yE_uid8_fxpToFPTest_b; + logic [32:0] yE_uid8_fxpToFPTest_o; + wire [32:0] yE_uid8_fxpToFPTest_q; + wire [31:0] y_uid9_fxpToFPTest_in; + wire [31:0] y_uid9_fxpToFPTest_b; + wire [5:0] maxCount_uid11_fxpToFPTest_q; + wire [0:0] inIsZero_uid12_fxpToFPTest_qi; + reg [0:0] inIsZero_uid12_fxpToFPTest_q; + wire [7:0] msbIn_uid13_fxpToFPTest_q; + wire [8:0] expPreRnd_uid14_fxpToFPTest_a; + wire [8:0] expPreRnd_uid14_fxpToFPTest_b; + logic [8:0] expPreRnd_uid14_fxpToFPTest_o; + wire [8:0] expPreRnd_uid14_fxpToFPTest_q; + wire [32:0] expFracRnd_uid16_fxpToFPTest_q; + wire [0:0] sticky_uid20_fxpToFPTest_qi; + reg [0:0] sticky_uid20_fxpToFPTest_q; + wire [0:0] nr_uid21_fxpToFPTest_q; + wire [0:0] rnd_uid22_fxpToFPTest_q; + wire [34:0] expFracR_uid24_fxpToFPTest_a; + wire [34:0] expFracR_uid24_fxpToFPTest_b; + logic [34:0] expFracR_uid24_fxpToFPTest_o; + wire [33:0] expFracR_uid24_fxpToFPTest_q; + wire [23:0] fracR_uid25_fxpToFPTest_in; + wire [22:0] fracR_uid25_fxpToFPTest_b; + wire [9:0] expR_uid26_fxpToFPTest_b; + wire [11:0] udf_uid27_fxpToFPTest_a; + wire [11:0] udf_uid27_fxpToFPTest_b; + logic [11:0] udf_uid27_fxpToFPTest_o; + wire [0:0] udf_uid27_fxpToFPTest_n; + wire [7:0] expInf_uid28_fxpToFPTest_q; + wire [11:0] ovf_uid29_fxpToFPTest_a; + wire [11:0] ovf_uid29_fxpToFPTest_b; + logic [11:0] ovf_uid29_fxpToFPTest_o; + wire [0:0] ovf_uid29_fxpToFPTest_n; + wire [0:0] excSelector_uid30_fxpToFPTest_q; + wire [22:0] fracZ_uid31_fxpToFPTest_q; + wire [0:0] fracRPostExc_uid32_fxpToFPTest_s; + reg [22:0] fracRPostExc_uid32_fxpToFPTest_q; + wire [0:0] udfOrInZero_uid33_fxpToFPTest_q; + wire [1:0] excSelector_uid34_fxpToFPTest_q; + wire [7:0] expZ_uid37_fxpToFPTest_q; + wire [7:0] expR_uid38_fxpToFPTest_in; + wire [7:0] expR_uid38_fxpToFPTest_b; + wire [1:0] expRPostExc_uid39_fxpToFPTest_s; + reg [7:0] expRPostExc_uid39_fxpToFPTest_q; + wire [31:0] outRes_uid40_fxpToFPTest_q; + wire [31:0] zs_uid42_lzcShifterZ1_uid10_fxpToFPTest_q; + wire [0:0] vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_qi; + reg [0:0] vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_q; + wire [0:0] vStagei_uid46_lzcShifterZ1_uid10_fxpToFPTest_s; + reg [31:0] vStagei_uid46_lzcShifterZ1_uid10_fxpToFPTest_q; + wire [15:0] zs_uid47_lzcShifterZ1_uid10_fxpToFPTest_q; + wire [0:0] vCount_uid49_lzcShifterZ1_uid10_fxpToFPTest_q; + wire [31:0] cStage_uid52_lzcShifterZ1_uid10_fxpToFPTest_q; + wire [0:0] vStagei_uid53_lzcShifterZ1_uid10_fxpToFPTest_s; + reg [31:0] vStagei_uid53_lzcShifterZ1_uid10_fxpToFPTest_q; + wire [0:0] vCount_uid56_lzcShifterZ1_uid10_fxpToFPTest_q; + wire [31:0] cStage_uid59_lzcShifterZ1_uid10_fxpToFPTest_q; + wire [0:0] vStagei_uid60_lzcShifterZ1_uid10_fxpToFPTest_s; + reg [31:0] vStagei_uid60_lzcShifterZ1_uid10_fxpToFPTest_q; + wire [3:0] zs_uid61_lzcShifterZ1_uid10_fxpToFPTest_q; + wire [0:0] vCount_uid63_lzcShifterZ1_uid10_fxpToFPTest_q; + wire [31:0] cStage_uid66_lzcShifterZ1_uid10_fxpToFPTest_q; + wire [0:0] vStagei_uid67_lzcShifterZ1_uid10_fxpToFPTest_s; + reg [31:0] vStagei_uid67_lzcShifterZ1_uid10_fxpToFPTest_q; + wire [1:0] zs_uid68_lzcShifterZ1_uid10_fxpToFPTest_q; + wire [0:0] vCount_uid70_lzcShifterZ1_uid10_fxpToFPTest_q; + wire [31:0] cStage_uid73_lzcShifterZ1_uid10_fxpToFPTest_q; + wire [0:0] vStagei_uid74_lzcShifterZ1_uid10_fxpToFPTest_s; + reg [31:0] vStagei_uid74_lzcShifterZ1_uid10_fxpToFPTest_q; + wire [0:0] vCount_uid77_lzcShifterZ1_uid10_fxpToFPTest_q; + wire [31:0] cStage_uid80_lzcShifterZ1_uid10_fxpToFPTest_q; + wire [0:0] vStagei_uid81_lzcShifterZ1_uid10_fxpToFPTest_s; + reg [31:0] vStagei_uid81_lzcShifterZ1_uid10_fxpToFPTest_q; + wire [5:0] vCount_uid82_lzcShifterZ1_uid10_fxpToFPTest_q; + wire [7:0] vCountBig_uid84_lzcShifterZ1_uid10_fxpToFPTest_a; + wire [7:0] vCountBig_uid84_lzcShifterZ1_uid10_fxpToFPTest_b; + logic [7:0] vCountBig_uid84_lzcShifterZ1_uid10_fxpToFPTest_o; + wire [0:0] vCountBig_uid84_lzcShifterZ1_uid10_fxpToFPTest_c; + wire [0:0] vCountFinal_uid86_lzcShifterZ1_uid10_fxpToFPTest_s; + reg [5:0] vCountFinal_uid86_lzcShifterZ1_uid10_fxpToFPTest_q; + wire [1:0] l_uid17_fxpToFPTest_merged_bit_select_in; + wire [0:0] l_uid17_fxpToFPTest_merged_bit_select_b; + wire [0:0] l_uid17_fxpToFPTest_merged_bit_select_c; + wire [15:0] rVStage_uid48_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_b; + wire [15:0] rVStage_uid48_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_c; + wire [7:0] rVStage_uid55_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_b; + wire [23:0] rVStage_uid55_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_c; + wire [3:0] rVStage_uid62_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_b; + wire [27:0] rVStage_uid62_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_c; + wire [1:0] rVStage_uid69_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_b; + wire [29:0] rVStage_uid69_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_c; + wire [0:0] rVStage_uid76_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_b; + wire [30:0] rVStage_uid76_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_c; + wire [30:0] fracRnd_uid15_fxpToFPTest_merged_bit_select_in; + wire [23:0] fracRnd_uid15_fxpToFPTest_merged_bit_select_b; + wire [6:0] fracRnd_uid15_fxpToFPTest_merged_bit_select_c; + reg [23:0] redist0_fracRnd_uid15_fxpToFPTest_merged_bit_select_b_2_q; + reg [0:0] redist1_vCount_uid63_lzcShifterZ1_uid10_fxpToFPTest_q_1_q; + reg [0:0] redist2_vCount_uid56_lzcShifterZ1_uid10_fxpToFPTest_q_1_q; + reg [0:0] redist3_vCount_uid49_lzcShifterZ1_uid10_fxpToFPTest_q_2_q; + reg [0:0] redist4_vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_q_3_q; + reg [9:0] redist5_expR_uid26_fxpToFPTest_b_1_q; + reg [22:0] redist6_fracR_uid25_fxpToFPTest_b_1_q; + reg [0:0] redist7_sticky_uid20_fxpToFPTest_q_2_q; + reg [0:0] redist8_inIsZero_uid12_fxpToFPTest_q_2_q; + reg [31:0] redist9_y_uid9_fxpToFPTest_b_1_q; + reg [0:0] redist10_signX_uid6_fxpToFPTest_b_1_q; + reg [0:0] redist11_signX_uid6_fxpToFPTest_b_7_q; + + + // signX_uid6_fxpToFPTest(BITSELECT,5)@0 + assign signX_uid6_fxpToFPTest_b = a[31:31]; + + // redist10_signX_uid6_fxpToFPTest_b_1(DELAY,105) + dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) + redist10_signX_uid6_fxpToFPTest_b_1 ( .xin(signX_uid6_fxpToFPTest_b), .xout(redist10_signX_uid6_fxpToFPTest_b_1_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // redist11_signX_uid6_fxpToFPTest_b_7(DELAY,106) + dspba_delay_ver #( .width(1), .depth(6), .reset_kind("ASYNC") ) + redist11_signX_uid6_fxpToFPTest_b_7 ( .xin(redist10_signX_uid6_fxpToFPTest_b_1_q), .xout(redist11_signX_uid6_fxpToFPTest_b_7_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // expInf_uid28_fxpToFPTest(CONSTANT,27) + assign expInf_uid28_fxpToFPTest_q = 8'b11111111; + + // expZ_uid37_fxpToFPTest(CONSTANT,36) + assign expZ_uid37_fxpToFPTest_q = 8'b00000000; + + // rVStage_uid76_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select(BITSELECT,93)@4 + assign rVStage_uid76_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_b = vStagei_uid74_lzcShifterZ1_uid10_fxpToFPTest_q[31:31]; + assign rVStage_uid76_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_c = vStagei_uid74_lzcShifterZ1_uid10_fxpToFPTest_q[30:0]; + + // GND(CONSTANT,0) + assign GND_q = 1'b0; + + // cStage_uid80_lzcShifterZ1_uid10_fxpToFPTest(BITJOIN,79)@4 + assign cStage_uid80_lzcShifterZ1_uid10_fxpToFPTest_q = {rVStage_uid76_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_c, GND_q}; + + // rVStage_uid69_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select(BITSELECT,92)@4 + assign rVStage_uid69_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_b = vStagei_uid67_lzcShifterZ1_uid10_fxpToFPTest_q[31:30]; + assign rVStage_uid69_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_c = vStagei_uid67_lzcShifterZ1_uid10_fxpToFPTest_q[29:0]; + + // zs_uid68_lzcShifterZ1_uid10_fxpToFPTest(CONSTANT,67) + assign zs_uid68_lzcShifterZ1_uid10_fxpToFPTest_q = 2'b00; + + // cStage_uid73_lzcShifterZ1_uid10_fxpToFPTest(BITJOIN,72)@4 + assign cStage_uid73_lzcShifterZ1_uid10_fxpToFPTest_q = {rVStage_uid69_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_c, zs_uid68_lzcShifterZ1_uid10_fxpToFPTest_q}; + + // rVStage_uid62_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select(BITSELECT,91)@3 + assign rVStage_uid62_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_b = vStagei_uid60_lzcShifterZ1_uid10_fxpToFPTest_q[31:28]; + assign rVStage_uid62_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_c = vStagei_uid60_lzcShifterZ1_uid10_fxpToFPTest_q[27:0]; + + // zs_uid61_lzcShifterZ1_uid10_fxpToFPTest(CONSTANT,60) + assign zs_uid61_lzcShifterZ1_uid10_fxpToFPTest_q = 4'b0000; + + // cStage_uid66_lzcShifterZ1_uid10_fxpToFPTest(BITJOIN,65)@3 + assign cStage_uid66_lzcShifterZ1_uid10_fxpToFPTest_q = {rVStage_uid62_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_c, zs_uid61_lzcShifterZ1_uid10_fxpToFPTest_q}; + + // rVStage_uid55_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select(BITSELECT,90)@3 + assign rVStage_uid55_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_b = vStagei_uid53_lzcShifterZ1_uid10_fxpToFPTest_q[31:24]; + assign rVStage_uid55_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_c = vStagei_uid53_lzcShifterZ1_uid10_fxpToFPTest_q[23:0]; + + // cStage_uid59_lzcShifterZ1_uid10_fxpToFPTest(BITJOIN,58)@3 + assign cStage_uid59_lzcShifterZ1_uid10_fxpToFPTest_q = {rVStage_uid55_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_c, expZ_uid37_fxpToFPTest_q}; + + // rVStage_uid48_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select(BITSELECT,89)@2 + assign rVStage_uid48_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_b = vStagei_uid46_lzcShifterZ1_uid10_fxpToFPTest_q[31:16]; + assign rVStage_uid48_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_c = vStagei_uid46_lzcShifterZ1_uid10_fxpToFPTest_q[15:0]; + + // zs_uid47_lzcShifterZ1_uid10_fxpToFPTest(CONSTANT,46) + assign zs_uid47_lzcShifterZ1_uid10_fxpToFPTest_q = 16'b0000000000000000; + + // cStage_uid52_lzcShifterZ1_uid10_fxpToFPTest(BITJOIN,51)@2 + assign cStage_uid52_lzcShifterZ1_uid10_fxpToFPTest_q = {rVStage_uid48_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_c, zs_uid47_lzcShifterZ1_uid10_fxpToFPTest_q}; + + // zs_uid42_lzcShifterZ1_uid10_fxpToFPTest(CONSTANT,41) + assign zs_uid42_lzcShifterZ1_uid10_fxpToFPTest_q = 32'b00000000000000000000000000000000; + + // xXorSign_uid7_fxpToFPTest(LOGICAL,6)@0 + 1 + assign xXorSign_uid7_fxpToFPTest_b = {{31{signX_uid6_fxpToFPTest_b[0]}}, signX_uid6_fxpToFPTest_b}; + assign xXorSign_uid7_fxpToFPTest_qi = a ^ xXorSign_uid7_fxpToFPTest_b; + dspba_delay_ver #( .width(32), .depth(1), .reset_kind("ASYNC") ) + xXorSign_uid7_fxpToFPTest_delay ( .xin(xXorSign_uid7_fxpToFPTest_qi), .xout(xXorSign_uid7_fxpToFPTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // yE_uid8_fxpToFPTest(ADD,7)@1 + assign yE_uid8_fxpToFPTest_a = {1'b0, xXorSign_uid7_fxpToFPTest_q}; + assign yE_uid8_fxpToFPTest_b = {32'b00000000000000000000000000000000, redist10_signX_uid6_fxpToFPTest_b_1_q}; + assign yE_uid8_fxpToFPTest_o = $unsigned(yE_uid8_fxpToFPTest_a) + $unsigned(yE_uid8_fxpToFPTest_b); + assign yE_uid8_fxpToFPTest_q = yE_uid8_fxpToFPTest_o[32:0]; + + // y_uid9_fxpToFPTest(BITSELECT,8)@1 + assign y_uid9_fxpToFPTest_in = yE_uid8_fxpToFPTest_q[31:0]; + assign y_uid9_fxpToFPTest_b = y_uid9_fxpToFPTest_in[31:0]; + + // redist9_y_uid9_fxpToFPTest_b_1(DELAY,104) + dspba_delay_ver #( .width(32), .depth(1), .reset_kind("ASYNC") ) + redist9_y_uid9_fxpToFPTest_b_1 ( .xin(y_uid9_fxpToFPTest_b), .xout(redist9_y_uid9_fxpToFPTest_b_1_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest(LOGICAL,43)@1 + 1 + assign vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_qi = y_uid9_fxpToFPTest_b == zs_uid42_lzcShifterZ1_uid10_fxpToFPTest_q ? 1'b1 : 1'b0; + dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) + vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_delay ( .xin(vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_qi), .xout(vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // vStagei_uid46_lzcShifterZ1_uid10_fxpToFPTest(MUX,45)@2 + assign vStagei_uid46_lzcShifterZ1_uid10_fxpToFPTest_s = vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_q; + always @(vStagei_uid46_lzcShifterZ1_uid10_fxpToFPTest_s or en or redist9_y_uid9_fxpToFPTest_b_1_q or zs_uid42_lzcShifterZ1_uid10_fxpToFPTest_q) + begin + unique case (vStagei_uid46_lzcShifterZ1_uid10_fxpToFPTest_s) + 1'b0 : vStagei_uid46_lzcShifterZ1_uid10_fxpToFPTest_q = redist9_y_uid9_fxpToFPTest_b_1_q; + 1'b1 : vStagei_uid46_lzcShifterZ1_uid10_fxpToFPTest_q = zs_uid42_lzcShifterZ1_uid10_fxpToFPTest_q; + default : vStagei_uid46_lzcShifterZ1_uid10_fxpToFPTest_q = 32'b0; + endcase + end + + // vCount_uid49_lzcShifterZ1_uid10_fxpToFPTest(LOGICAL,48)@2 + assign vCount_uid49_lzcShifterZ1_uid10_fxpToFPTest_q = rVStage_uid48_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_b == zs_uid47_lzcShifterZ1_uid10_fxpToFPTest_q ? 1'b1 : 1'b0; + + // vStagei_uid53_lzcShifterZ1_uid10_fxpToFPTest(MUX,52)@2 + 1 + assign vStagei_uid53_lzcShifterZ1_uid10_fxpToFPTest_s = vCount_uid49_lzcShifterZ1_uid10_fxpToFPTest_q; + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + vStagei_uid53_lzcShifterZ1_uid10_fxpToFPTest_q <= 32'b0; + end + else if (en == 1'b1) + begin + unique case (vStagei_uid53_lzcShifterZ1_uid10_fxpToFPTest_s) + 1'b0 : vStagei_uid53_lzcShifterZ1_uid10_fxpToFPTest_q <= vStagei_uid46_lzcShifterZ1_uid10_fxpToFPTest_q; + 1'b1 : vStagei_uid53_lzcShifterZ1_uid10_fxpToFPTest_q <= cStage_uid52_lzcShifterZ1_uid10_fxpToFPTest_q; + default : vStagei_uid53_lzcShifterZ1_uid10_fxpToFPTest_q <= 32'b0; + endcase + end + end + + // vCount_uid56_lzcShifterZ1_uid10_fxpToFPTest(LOGICAL,55)@3 + assign vCount_uid56_lzcShifterZ1_uid10_fxpToFPTest_q = rVStage_uid55_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_b == expZ_uid37_fxpToFPTest_q ? 1'b1 : 1'b0; + + // vStagei_uid60_lzcShifterZ1_uid10_fxpToFPTest(MUX,59)@3 + assign vStagei_uid60_lzcShifterZ1_uid10_fxpToFPTest_s = vCount_uid56_lzcShifterZ1_uid10_fxpToFPTest_q; + always @(vStagei_uid60_lzcShifterZ1_uid10_fxpToFPTest_s or en or vStagei_uid53_lzcShifterZ1_uid10_fxpToFPTest_q or cStage_uid59_lzcShifterZ1_uid10_fxpToFPTest_q) + begin + unique case (vStagei_uid60_lzcShifterZ1_uid10_fxpToFPTest_s) + 1'b0 : vStagei_uid60_lzcShifterZ1_uid10_fxpToFPTest_q = vStagei_uid53_lzcShifterZ1_uid10_fxpToFPTest_q; + 1'b1 : vStagei_uid60_lzcShifterZ1_uid10_fxpToFPTest_q = cStage_uid59_lzcShifterZ1_uid10_fxpToFPTest_q; + default : vStagei_uid60_lzcShifterZ1_uid10_fxpToFPTest_q = 32'b0; + endcase + end + + // vCount_uid63_lzcShifterZ1_uid10_fxpToFPTest(LOGICAL,62)@3 + assign vCount_uid63_lzcShifterZ1_uid10_fxpToFPTest_q = rVStage_uid62_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_b == zs_uid61_lzcShifterZ1_uid10_fxpToFPTest_q ? 1'b1 : 1'b0; + + // vStagei_uid67_lzcShifterZ1_uid10_fxpToFPTest(MUX,66)@3 + 1 + assign vStagei_uid67_lzcShifterZ1_uid10_fxpToFPTest_s = vCount_uid63_lzcShifterZ1_uid10_fxpToFPTest_q; + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + vStagei_uid67_lzcShifterZ1_uid10_fxpToFPTest_q <= 32'b0; + end + else if (en == 1'b1) + begin + unique case (vStagei_uid67_lzcShifterZ1_uid10_fxpToFPTest_s) + 1'b0 : vStagei_uid67_lzcShifterZ1_uid10_fxpToFPTest_q <= vStagei_uid60_lzcShifterZ1_uid10_fxpToFPTest_q; + 1'b1 : vStagei_uid67_lzcShifterZ1_uid10_fxpToFPTest_q <= cStage_uid66_lzcShifterZ1_uid10_fxpToFPTest_q; + default : vStagei_uid67_lzcShifterZ1_uid10_fxpToFPTest_q <= 32'b0; + endcase + end + end + + // vCount_uid70_lzcShifterZ1_uid10_fxpToFPTest(LOGICAL,69)@4 + assign vCount_uid70_lzcShifterZ1_uid10_fxpToFPTest_q = rVStage_uid69_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_b == zs_uid68_lzcShifterZ1_uid10_fxpToFPTest_q ? 1'b1 : 1'b0; + + // vStagei_uid74_lzcShifterZ1_uid10_fxpToFPTest(MUX,73)@4 + assign vStagei_uid74_lzcShifterZ1_uid10_fxpToFPTest_s = vCount_uid70_lzcShifterZ1_uid10_fxpToFPTest_q; + always @(vStagei_uid74_lzcShifterZ1_uid10_fxpToFPTest_s or en or vStagei_uid67_lzcShifterZ1_uid10_fxpToFPTest_q or cStage_uid73_lzcShifterZ1_uid10_fxpToFPTest_q) + begin + unique case (vStagei_uid74_lzcShifterZ1_uid10_fxpToFPTest_s) + 1'b0 : vStagei_uid74_lzcShifterZ1_uid10_fxpToFPTest_q = vStagei_uid67_lzcShifterZ1_uid10_fxpToFPTest_q; + 1'b1 : vStagei_uid74_lzcShifterZ1_uid10_fxpToFPTest_q = cStage_uid73_lzcShifterZ1_uid10_fxpToFPTest_q; + default : vStagei_uid74_lzcShifterZ1_uid10_fxpToFPTest_q = 32'b0; + endcase + end + + // vCount_uid77_lzcShifterZ1_uid10_fxpToFPTest(LOGICAL,76)@4 + assign vCount_uid77_lzcShifterZ1_uid10_fxpToFPTest_q = rVStage_uid76_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_b == GND_q ? 1'b1 : 1'b0; + + // vStagei_uid81_lzcShifterZ1_uid10_fxpToFPTest(MUX,80)@4 + assign vStagei_uid81_lzcShifterZ1_uid10_fxpToFPTest_s = vCount_uid77_lzcShifterZ1_uid10_fxpToFPTest_q; + always @(vStagei_uid81_lzcShifterZ1_uid10_fxpToFPTest_s or en or vStagei_uid74_lzcShifterZ1_uid10_fxpToFPTest_q or cStage_uid80_lzcShifterZ1_uid10_fxpToFPTest_q) + begin + unique case (vStagei_uid81_lzcShifterZ1_uid10_fxpToFPTest_s) + 1'b0 : vStagei_uid81_lzcShifterZ1_uid10_fxpToFPTest_q = vStagei_uid74_lzcShifterZ1_uid10_fxpToFPTest_q; + 1'b1 : vStagei_uid81_lzcShifterZ1_uid10_fxpToFPTest_q = cStage_uid80_lzcShifterZ1_uid10_fxpToFPTest_q; + default : vStagei_uid81_lzcShifterZ1_uid10_fxpToFPTest_q = 32'b0; + endcase + end + + // fracRnd_uid15_fxpToFPTest_merged_bit_select(BITSELECT,94)@4 + assign fracRnd_uid15_fxpToFPTest_merged_bit_select_in = vStagei_uid81_lzcShifterZ1_uid10_fxpToFPTest_q[30:0]; + assign fracRnd_uid15_fxpToFPTest_merged_bit_select_b = fracRnd_uid15_fxpToFPTest_merged_bit_select_in[30:7]; + assign fracRnd_uid15_fxpToFPTest_merged_bit_select_c = fracRnd_uid15_fxpToFPTest_merged_bit_select_in[6:0]; + + // sticky_uid20_fxpToFPTest(LOGICAL,19)@4 + 1 + assign sticky_uid20_fxpToFPTest_qi = fracRnd_uid15_fxpToFPTest_merged_bit_select_c != 7'b0000000 ? 1'b1 : 1'b0; + dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) + sticky_uid20_fxpToFPTest_delay ( .xin(sticky_uid20_fxpToFPTest_qi), .xout(sticky_uid20_fxpToFPTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // redist7_sticky_uid20_fxpToFPTest_q_2(DELAY,102) + dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) + redist7_sticky_uid20_fxpToFPTest_q_2 ( .xin(sticky_uid20_fxpToFPTest_q), .xout(redist7_sticky_uid20_fxpToFPTest_q_2_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // nr_uid21_fxpToFPTest(LOGICAL,20)@6 + assign nr_uid21_fxpToFPTest_q = ~ (l_uid17_fxpToFPTest_merged_bit_select_c); + + // l_uid17_fxpToFPTest_merged_bit_select(BITSELECT,88)@6 + assign l_uid17_fxpToFPTest_merged_bit_select_in = expFracRnd_uid16_fxpToFPTest_q[1:0]; + assign l_uid17_fxpToFPTest_merged_bit_select_b = l_uid17_fxpToFPTest_merged_bit_select_in[1:1]; + assign l_uid17_fxpToFPTest_merged_bit_select_c = l_uid17_fxpToFPTest_merged_bit_select_in[0:0]; + + // rnd_uid22_fxpToFPTest(LOGICAL,21)@6 + assign rnd_uid22_fxpToFPTest_q = l_uid17_fxpToFPTest_merged_bit_select_b | nr_uid21_fxpToFPTest_q | redist7_sticky_uid20_fxpToFPTest_q_2_q; + + // maxCount_uid11_fxpToFPTest(CONSTANT,10) + assign maxCount_uid11_fxpToFPTest_q = 6'b100000; + + // redist4_vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_q_3(DELAY,99) + dspba_delay_ver #( .width(1), .depth(2), .reset_kind("ASYNC") ) + redist4_vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_q_3 ( .xin(vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_q), .xout(redist4_vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_q_3_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // redist3_vCount_uid49_lzcShifterZ1_uid10_fxpToFPTest_q_2(DELAY,98) + dspba_delay_ver #( .width(1), .depth(2), .reset_kind("ASYNC") ) + redist3_vCount_uid49_lzcShifterZ1_uid10_fxpToFPTest_q_2 ( .xin(vCount_uid49_lzcShifterZ1_uid10_fxpToFPTest_q), .xout(redist3_vCount_uid49_lzcShifterZ1_uid10_fxpToFPTest_q_2_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // redist2_vCount_uid56_lzcShifterZ1_uid10_fxpToFPTest_q_1(DELAY,97) + dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) + redist2_vCount_uid56_lzcShifterZ1_uid10_fxpToFPTest_q_1 ( .xin(vCount_uid56_lzcShifterZ1_uid10_fxpToFPTest_q), .xout(redist2_vCount_uid56_lzcShifterZ1_uid10_fxpToFPTest_q_1_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // redist1_vCount_uid63_lzcShifterZ1_uid10_fxpToFPTest_q_1(DELAY,96) + dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) + redist1_vCount_uid63_lzcShifterZ1_uid10_fxpToFPTest_q_1 ( .xin(vCount_uid63_lzcShifterZ1_uid10_fxpToFPTest_q), .xout(redist1_vCount_uid63_lzcShifterZ1_uid10_fxpToFPTest_q_1_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // vCount_uid82_lzcShifterZ1_uid10_fxpToFPTest(BITJOIN,81)@4 + assign vCount_uid82_lzcShifterZ1_uid10_fxpToFPTest_q = {redist4_vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_q_3_q, redist3_vCount_uid49_lzcShifterZ1_uid10_fxpToFPTest_q_2_q, redist2_vCount_uid56_lzcShifterZ1_uid10_fxpToFPTest_q_1_q, redist1_vCount_uid63_lzcShifterZ1_uid10_fxpToFPTest_q_1_q, vCount_uid70_lzcShifterZ1_uid10_fxpToFPTest_q, vCount_uid77_lzcShifterZ1_uid10_fxpToFPTest_q}; + + // vCountBig_uid84_lzcShifterZ1_uid10_fxpToFPTest(COMPARE,83)@4 + assign vCountBig_uid84_lzcShifterZ1_uid10_fxpToFPTest_a = {2'b00, maxCount_uid11_fxpToFPTest_q}; + assign vCountBig_uid84_lzcShifterZ1_uid10_fxpToFPTest_b = {2'b00, vCount_uid82_lzcShifterZ1_uid10_fxpToFPTest_q}; + assign vCountBig_uid84_lzcShifterZ1_uid10_fxpToFPTest_o = $unsigned(vCountBig_uid84_lzcShifterZ1_uid10_fxpToFPTest_a) - $unsigned(vCountBig_uid84_lzcShifterZ1_uid10_fxpToFPTest_b); + assign vCountBig_uid84_lzcShifterZ1_uid10_fxpToFPTest_c[0] = vCountBig_uid84_lzcShifterZ1_uid10_fxpToFPTest_o[7]; + + // vCountFinal_uid86_lzcShifterZ1_uid10_fxpToFPTest(MUX,85)@4 + 1 + assign vCountFinal_uid86_lzcShifterZ1_uid10_fxpToFPTest_s = vCountBig_uid84_lzcShifterZ1_uid10_fxpToFPTest_c; + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + vCountFinal_uid86_lzcShifterZ1_uid10_fxpToFPTest_q <= 6'b0; + end + else if (en == 1'b1) + begin + unique case (vCountFinal_uid86_lzcShifterZ1_uid10_fxpToFPTest_s) + 1'b0 : vCountFinal_uid86_lzcShifterZ1_uid10_fxpToFPTest_q <= vCount_uid82_lzcShifterZ1_uid10_fxpToFPTest_q; + 1'b1 : vCountFinal_uid86_lzcShifterZ1_uid10_fxpToFPTest_q <= maxCount_uid11_fxpToFPTest_q; + default : vCountFinal_uid86_lzcShifterZ1_uid10_fxpToFPTest_q <= 6'b0; + endcase + end + end + + // msbIn_uid13_fxpToFPTest(CONSTANT,12) + assign msbIn_uid13_fxpToFPTest_q = 8'b10011110; + + // expPreRnd_uid14_fxpToFPTest(SUB,13)@5 + 1 + assign expPreRnd_uid14_fxpToFPTest_a = {1'b0, msbIn_uid13_fxpToFPTest_q}; + assign expPreRnd_uid14_fxpToFPTest_b = {3'b000, vCountFinal_uid86_lzcShifterZ1_uid10_fxpToFPTest_q}; + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + expPreRnd_uid14_fxpToFPTest_o <= 9'b0; + end + else if (en == 1'b1) + begin + expPreRnd_uid14_fxpToFPTest_o <= $unsigned(expPreRnd_uid14_fxpToFPTest_a) - $unsigned(expPreRnd_uid14_fxpToFPTest_b); + end + end + assign expPreRnd_uid14_fxpToFPTest_q = expPreRnd_uid14_fxpToFPTest_o[8:0]; + + // redist0_fracRnd_uid15_fxpToFPTest_merged_bit_select_b_2(DELAY,95) + dspba_delay_ver #( .width(24), .depth(2), .reset_kind("ASYNC") ) + redist0_fracRnd_uid15_fxpToFPTest_merged_bit_select_b_2 ( .xin(fracRnd_uid15_fxpToFPTest_merged_bit_select_b), .xout(redist0_fracRnd_uid15_fxpToFPTest_merged_bit_select_b_2_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // expFracRnd_uid16_fxpToFPTest(BITJOIN,15)@6 + assign expFracRnd_uid16_fxpToFPTest_q = {expPreRnd_uid14_fxpToFPTest_q, redist0_fracRnd_uid15_fxpToFPTest_merged_bit_select_b_2_q}; + + // expFracR_uid24_fxpToFPTest(ADD,23)@6 + assign expFracR_uid24_fxpToFPTest_a = {{2{expFracRnd_uid16_fxpToFPTest_q[32]}}, expFracRnd_uid16_fxpToFPTest_q}; + assign expFracR_uid24_fxpToFPTest_b = {34'b0000000000000000000000000000000000, rnd_uid22_fxpToFPTest_q}; + assign expFracR_uid24_fxpToFPTest_o = $signed(expFracR_uid24_fxpToFPTest_a) + $signed(expFracR_uid24_fxpToFPTest_b); + assign expFracR_uid24_fxpToFPTest_q = expFracR_uid24_fxpToFPTest_o[33:0]; + + // expR_uid26_fxpToFPTest(BITSELECT,25)@6 + assign expR_uid26_fxpToFPTest_b = expFracR_uid24_fxpToFPTest_q[33:24]; + + // redist5_expR_uid26_fxpToFPTest_b_1(DELAY,100) + dspba_delay_ver #( .width(10), .depth(1), .reset_kind("ASYNC") ) + redist5_expR_uid26_fxpToFPTest_b_1 ( .xin(expR_uid26_fxpToFPTest_b), .xout(redist5_expR_uid26_fxpToFPTest_b_1_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // expR_uid38_fxpToFPTest(BITSELECT,37)@7 + assign expR_uid38_fxpToFPTest_in = redist5_expR_uid26_fxpToFPTest_b_1_q[7:0]; + assign expR_uid38_fxpToFPTest_b = expR_uid38_fxpToFPTest_in[7:0]; + + // ovf_uid29_fxpToFPTest(COMPARE,28)@7 + assign ovf_uid29_fxpToFPTest_a = {{2{redist5_expR_uid26_fxpToFPTest_b_1_q[9]}}, redist5_expR_uid26_fxpToFPTest_b_1_q}; + assign ovf_uid29_fxpToFPTest_b = {4'b0000, expInf_uid28_fxpToFPTest_q}; + assign ovf_uid29_fxpToFPTest_o = $signed(ovf_uid29_fxpToFPTest_a) - $signed(ovf_uid29_fxpToFPTest_b); + assign ovf_uid29_fxpToFPTest_n[0] = ~ (ovf_uid29_fxpToFPTest_o[11]); + + // inIsZero_uid12_fxpToFPTest(LOGICAL,11)@5 + 1 + assign inIsZero_uid12_fxpToFPTest_qi = vCountFinal_uid86_lzcShifterZ1_uid10_fxpToFPTest_q == maxCount_uid11_fxpToFPTest_q ? 1'b1 : 1'b0; + dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) + inIsZero_uid12_fxpToFPTest_delay ( .xin(inIsZero_uid12_fxpToFPTest_qi), .xout(inIsZero_uid12_fxpToFPTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // redist8_inIsZero_uid12_fxpToFPTest_q_2(DELAY,103) + dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) + redist8_inIsZero_uid12_fxpToFPTest_q_2 ( .xin(inIsZero_uid12_fxpToFPTest_q), .xout(redist8_inIsZero_uid12_fxpToFPTest_q_2_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // udf_uid27_fxpToFPTest(COMPARE,26)@7 + assign udf_uid27_fxpToFPTest_a = {11'b00000000000, GND_q}; + assign udf_uid27_fxpToFPTest_b = {{2{redist5_expR_uid26_fxpToFPTest_b_1_q[9]}}, redist5_expR_uid26_fxpToFPTest_b_1_q}; + assign udf_uid27_fxpToFPTest_o = $signed(udf_uid27_fxpToFPTest_a) - $signed(udf_uid27_fxpToFPTest_b); + assign udf_uid27_fxpToFPTest_n[0] = ~ (udf_uid27_fxpToFPTest_o[11]); + + // udfOrInZero_uid33_fxpToFPTest(LOGICAL,32)@7 + assign udfOrInZero_uid33_fxpToFPTest_q = udf_uid27_fxpToFPTest_n | redist8_inIsZero_uid12_fxpToFPTest_q_2_q; + + // excSelector_uid34_fxpToFPTest(BITJOIN,33)@7 + assign excSelector_uid34_fxpToFPTest_q = {ovf_uid29_fxpToFPTest_n, udfOrInZero_uid33_fxpToFPTest_q}; + + // expRPostExc_uid39_fxpToFPTest(MUX,38)@7 + assign expRPostExc_uid39_fxpToFPTest_s = excSelector_uid34_fxpToFPTest_q; + always @(expRPostExc_uid39_fxpToFPTest_s or en or expR_uid38_fxpToFPTest_b or expZ_uid37_fxpToFPTest_q or expInf_uid28_fxpToFPTest_q) + begin + unique case (expRPostExc_uid39_fxpToFPTest_s) + 2'b00 : expRPostExc_uid39_fxpToFPTest_q = expR_uid38_fxpToFPTest_b; + 2'b01 : expRPostExc_uid39_fxpToFPTest_q = expZ_uid37_fxpToFPTest_q; + 2'b10 : expRPostExc_uid39_fxpToFPTest_q = expInf_uid28_fxpToFPTest_q; + 2'b11 : expRPostExc_uid39_fxpToFPTest_q = expInf_uid28_fxpToFPTest_q; + default : expRPostExc_uid39_fxpToFPTest_q = 8'b0; + endcase + end + + // fracZ_uid31_fxpToFPTest(CONSTANT,30) + assign fracZ_uid31_fxpToFPTest_q = 23'b00000000000000000000000; + + // fracR_uid25_fxpToFPTest(BITSELECT,24)@6 + assign fracR_uid25_fxpToFPTest_in = expFracR_uid24_fxpToFPTest_q[23:0]; + assign fracR_uid25_fxpToFPTest_b = fracR_uid25_fxpToFPTest_in[23:1]; + + // redist6_fracR_uid25_fxpToFPTest_b_1(DELAY,101) + dspba_delay_ver #( .width(23), .depth(1), .reset_kind("ASYNC") ) + redist6_fracR_uid25_fxpToFPTest_b_1 ( .xin(fracR_uid25_fxpToFPTest_b), .xout(redist6_fracR_uid25_fxpToFPTest_b_1_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // excSelector_uid30_fxpToFPTest(LOGICAL,29)@7 + assign excSelector_uid30_fxpToFPTest_q = redist8_inIsZero_uid12_fxpToFPTest_q_2_q | ovf_uid29_fxpToFPTest_n | udf_uid27_fxpToFPTest_n; + + // fracRPostExc_uid32_fxpToFPTest(MUX,31)@7 + assign fracRPostExc_uid32_fxpToFPTest_s = excSelector_uid30_fxpToFPTest_q; + always @(fracRPostExc_uid32_fxpToFPTest_s or en or redist6_fracR_uid25_fxpToFPTest_b_1_q or fracZ_uid31_fxpToFPTest_q) + begin + unique case (fracRPostExc_uid32_fxpToFPTest_s) + 1'b0 : fracRPostExc_uid32_fxpToFPTest_q = redist6_fracR_uid25_fxpToFPTest_b_1_q; + 1'b1 : fracRPostExc_uid32_fxpToFPTest_q = fracZ_uid31_fxpToFPTest_q; + default : fracRPostExc_uid32_fxpToFPTest_q = 23'b0; + endcase + end + + // outRes_uid40_fxpToFPTest(BITJOIN,39)@7 + assign outRes_uid40_fxpToFPTest_q = {redist11_signX_uid6_fxpToFPTest_b_7_q, expRPostExc_uid39_fxpToFPTest_q, fracRPostExc_uid32_fxpToFPTest_q}; + + // xOut(GPOUT,4)@7 + assign q = outRes_uid40_fxpToFPTest_q; + +endmodule diff --git a/hw/rtl/fp_cores/altera/acl_utof.sv b/hw/rtl/fp_cores/altera/acl_utof.sv new file mode 100644 index 00000000..4b404625 --- /dev/null +++ b/hw/rtl/fp_cores/altera/acl_utof.sv @@ -0,0 +1,486 @@ +// ------------------------------------------------------------------------- +// High Level Design Compiler for Intel(R) FPGAs Version 17.1 (Release Build #273) +// Quartus Prime development tool and MATLAB/Simulink Interface +// +// Legal Notice: Copyright 2017 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly +// subject to the terms and conditions of the Intel FPGA Software License +// Agreement, Intel MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for +// the sole purpose of programming logic devices manufactured by Intel +// and sold by Intel or its authorized distributors. Please refer to the +// applicable agreement for further details. +// --------------------------------------------------------------------------- + +// SystemVerilog created from acl_utof +// SystemVerilog created on Wed Sep 2 07:11:09 2020 + + +(* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007; -name MESSAGE_DISABLE 10958" *) +module acl_utof ( + input wire [31:0] a, + input wire [0:0] en, + output wire [31:0] q, + input wire clk, + input wire areset + ); + + wire [0:0] GND_q; + wire [5:0] maxCount_uid7_fxpToFPTest_q; + wire [0:0] inIsZero_uid8_fxpToFPTest_qi; + reg [0:0] inIsZero_uid8_fxpToFPTest_q; + wire [7:0] msbIn_uid9_fxpToFPTest_q; + wire [8:0] expPreRnd_uid10_fxpToFPTest_a; + wire [8:0] expPreRnd_uid10_fxpToFPTest_b; + logic [8:0] expPreRnd_uid10_fxpToFPTest_o; + wire [8:0] expPreRnd_uid10_fxpToFPTest_q; + wire [32:0] expFracRnd_uid12_fxpToFPTest_q; + wire [0:0] sticky_uid16_fxpToFPTest_qi; + reg [0:0] sticky_uid16_fxpToFPTest_q; + wire [0:0] nr_uid17_fxpToFPTest_q; + wire [0:0] rnd_uid18_fxpToFPTest_qi; + reg [0:0] rnd_uid18_fxpToFPTest_q; + wire [34:0] expFracR_uid20_fxpToFPTest_a; + wire [34:0] expFracR_uid20_fxpToFPTest_b; + logic [34:0] expFracR_uid20_fxpToFPTest_o; + wire [33:0] expFracR_uid20_fxpToFPTest_q; + wire [23:0] fracR_uid21_fxpToFPTest_in; + wire [22:0] fracR_uid21_fxpToFPTest_b; + wire [9:0] expR_uid22_fxpToFPTest_b; + wire [11:0] udf_uid23_fxpToFPTest_a; + wire [11:0] udf_uid23_fxpToFPTest_b; + logic [11:0] udf_uid23_fxpToFPTest_o; + wire [0:0] udf_uid23_fxpToFPTest_n; + wire [7:0] expInf_uid24_fxpToFPTest_q; + wire [11:0] ovf_uid25_fxpToFPTest_a; + wire [11:0] ovf_uid25_fxpToFPTest_b; + logic [11:0] ovf_uid25_fxpToFPTest_o; + wire [0:0] ovf_uid25_fxpToFPTest_n; + wire [0:0] excSelector_uid26_fxpToFPTest_q; + wire [22:0] fracZ_uid27_fxpToFPTest_q; + wire [0:0] fracRPostExc_uid28_fxpToFPTest_s; + reg [22:0] fracRPostExc_uid28_fxpToFPTest_q; + wire [0:0] udfOrInZero_uid29_fxpToFPTest_q; + wire [1:0] excSelector_uid30_fxpToFPTest_q; + wire [7:0] expZ_uid33_fxpToFPTest_q; + wire [7:0] expR_uid34_fxpToFPTest_in; + wire [7:0] expR_uid34_fxpToFPTest_b; + wire [1:0] expRPostExc_uid35_fxpToFPTest_s; + reg [7:0] expRPostExc_uid35_fxpToFPTest_q; + wire [31:0] outRes_uid36_fxpToFPTest_q; + wire [31:0] zs_uid38_lzcShifterZ1_uid6_fxpToFPTest_q; + wire [0:0] vCount_uid40_lzcShifterZ1_uid6_fxpToFPTest_qi; + reg [0:0] vCount_uid40_lzcShifterZ1_uid6_fxpToFPTest_q; + wire [0:0] vStagei_uid42_lzcShifterZ1_uid6_fxpToFPTest_s; + reg [31:0] vStagei_uid42_lzcShifterZ1_uid6_fxpToFPTest_q; + wire [15:0] zs_uid43_lzcShifterZ1_uid6_fxpToFPTest_q; + wire [0:0] vCount_uid45_lzcShifterZ1_uid6_fxpToFPTest_q; + wire [31:0] cStage_uid48_lzcShifterZ1_uid6_fxpToFPTest_q; + wire [0:0] vStagei_uid49_lzcShifterZ1_uid6_fxpToFPTest_s; + reg [31:0] vStagei_uid49_lzcShifterZ1_uid6_fxpToFPTest_q; + wire [0:0] vCount_uid52_lzcShifterZ1_uid6_fxpToFPTest_q; + wire [31:0] cStage_uid55_lzcShifterZ1_uid6_fxpToFPTest_q; + wire [0:0] vStagei_uid56_lzcShifterZ1_uid6_fxpToFPTest_s; + reg [31:0] vStagei_uid56_lzcShifterZ1_uid6_fxpToFPTest_q; + wire [3:0] zs_uid57_lzcShifterZ1_uid6_fxpToFPTest_q; + wire [0:0] vCount_uid59_lzcShifterZ1_uid6_fxpToFPTest_q; + wire [31:0] cStage_uid62_lzcShifterZ1_uid6_fxpToFPTest_q; + wire [0:0] vStagei_uid63_lzcShifterZ1_uid6_fxpToFPTest_s; + reg [31:0] vStagei_uid63_lzcShifterZ1_uid6_fxpToFPTest_q; + wire [1:0] zs_uid64_lzcShifterZ1_uid6_fxpToFPTest_q; + wire [0:0] vCount_uid66_lzcShifterZ1_uid6_fxpToFPTest_q; + wire [31:0] cStage_uid69_lzcShifterZ1_uid6_fxpToFPTest_q; + wire [0:0] vStagei_uid70_lzcShifterZ1_uid6_fxpToFPTest_s; + reg [31:0] vStagei_uid70_lzcShifterZ1_uid6_fxpToFPTest_q; + wire [0:0] vCount_uid73_lzcShifterZ1_uid6_fxpToFPTest_q; + wire [31:0] cStage_uid76_lzcShifterZ1_uid6_fxpToFPTest_q; + wire [0:0] vStagei_uid77_lzcShifterZ1_uid6_fxpToFPTest_s; + reg [31:0] vStagei_uid77_lzcShifterZ1_uid6_fxpToFPTest_q; + wire [5:0] vCount_uid78_lzcShifterZ1_uid6_fxpToFPTest_q; + wire [7:0] vCountBig_uid80_lzcShifterZ1_uid6_fxpToFPTest_a; + wire [7:0] vCountBig_uid80_lzcShifterZ1_uid6_fxpToFPTest_b; + logic [7:0] vCountBig_uid80_lzcShifterZ1_uid6_fxpToFPTest_o; + wire [0:0] vCountBig_uid80_lzcShifterZ1_uid6_fxpToFPTest_c; + wire [0:0] vCountFinal_uid82_lzcShifterZ1_uid6_fxpToFPTest_s; + reg [5:0] vCountFinal_uid82_lzcShifterZ1_uid6_fxpToFPTest_q; + wire [1:0] l_uid13_fxpToFPTest_merged_bit_select_in; + wire [0:0] l_uid13_fxpToFPTest_merged_bit_select_b; + wire [0:0] l_uid13_fxpToFPTest_merged_bit_select_c; + wire [15:0] rVStage_uid44_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_b; + wire [15:0] rVStage_uid44_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_c; + wire [7:0] rVStage_uid51_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_b; + wire [23:0] rVStage_uid51_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_c; + wire [3:0] rVStage_uid58_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_b; + wire [27:0] rVStage_uid58_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_c; + wire [1:0] rVStage_uid65_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_b; + wire [29:0] rVStage_uid65_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_c; + wire [0:0] rVStage_uid72_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_b; + wire [30:0] rVStage_uid72_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_c; + wire [30:0] fracRnd_uid11_fxpToFPTest_merged_bit_select_in; + wire [23:0] fracRnd_uid11_fxpToFPTest_merged_bit_select_b; + wire [6:0] fracRnd_uid11_fxpToFPTest_merged_bit_select_c; + reg [23:0] redist0_fracRnd_uid11_fxpToFPTest_merged_bit_select_b_1_q; + reg [0:0] redist1_vCount_uid66_lzcShifterZ1_uid6_fxpToFPTest_q_1_q; + reg [0:0] redist2_vCount_uid59_lzcShifterZ1_uid6_fxpToFPTest_q_1_q; + reg [0:0] redist3_vCount_uid52_lzcShifterZ1_uid6_fxpToFPTest_q_2_q; + reg [0:0] redist4_vCount_uid45_lzcShifterZ1_uid6_fxpToFPTest_q_3_q; + reg [0:0] redist5_vCount_uid40_lzcShifterZ1_uid6_fxpToFPTest_q_4_q; + reg [9:0] redist6_expR_uid22_fxpToFPTest_b_1_q; + reg [22:0] redist7_fracR_uid21_fxpToFPTest_b_1_q; + reg [32:0] redist8_expFracRnd_uid12_fxpToFPTest_q_1_q; + reg [0:0] redist9_inIsZero_uid8_fxpToFPTest_q_2_q; + reg [31:0] redist10_xIn_a_1_q; + + + // GND(CONSTANT,0) + assign GND_q = 1'b0; + + // expInf_uid24_fxpToFPTest(CONSTANT,23) + assign expInf_uid24_fxpToFPTest_q = 8'b11111111; + + // expZ_uid33_fxpToFPTest(CONSTANT,32) + assign expZ_uid33_fxpToFPTest_q = 8'b00000000; + + // rVStage_uid72_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select(BITSELECT,89)@4 + assign rVStage_uid72_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_b = vStagei_uid70_lzcShifterZ1_uid6_fxpToFPTest_q[31:31]; + assign rVStage_uid72_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_c = vStagei_uid70_lzcShifterZ1_uid6_fxpToFPTest_q[30:0]; + + // cStage_uid76_lzcShifterZ1_uid6_fxpToFPTest(BITJOIN,75)@4 + assign cStage_uid76_lzcShifterZ1_uid6_fxpToFPTest_q = {rVStage_uid72_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_c, GND_q}; + + // rVStage_uid65_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select(BITSELECT,88)@3 + assign rVStage_uid65_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_b = vStagei_uid63_lzcShifterZ1_uid6_fxpToFPTest_q[31:30]; + assign rVStage_uid65_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_c = vStagei_uid63_lzcShifterZ1_uid6_fxpToFPTest_q[29:0]; + + // zs_uid64_lzcShifterZ1_uid6_fxpToFPTest(CONSTANT,63) + assign zs_uid64_lzcShifterZ1_uid6_fxpToFPTest_q = 2'b00; + + // cStage_uid69_lzcShifterZ1_uid6_fxpToFPTest(BITJOIN,68)@3 + assign cStage_uid69_lzcShifterZ1_uid6_fxpToFPTest_q = {rVStage_uid65_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_c, zs_uid64_lzcShifterZ1_uid6_fxpToFPTest_q}; + + // rVStage_uid58_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select(BITSELECT,87)@3 + assign rVStage_uid58_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_b = vStagei_uid56_lzcShifterZ1_uid6_fxpToFPTest_q[31:28]; + assign rVStage_uid58_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_c = vStagei_uid56_lzcShifterZ1_uid6_fxpToFPTest_q[27:0]; + + // zs_uid57_lzcShifterZ1_uid6_fxpToFPTest(CONSTANT,56) + assign zs_uid57_lzcShifterZ1_uid6_fxpToFPTest_q = 4'b0000; + + // cStage_uid62_lzcShifterZ1_uid6_fxpToFPTest(BITJOIN,61)@3 + assign cStage_uid62_lzcShifterZ1_uid6_fxpToFPTest_q = {rVStage_uid58_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_c, zs_uid57_lzcShifterZ1_uid6_fxpToFPTest_q}; + + // rVStage_uid51_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select(BITSELECT,86)@2 + assign rVStage_uid51_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_b = vStagei_uid49_lzcShifterZ1_uid6_fxpToFPTest_q[31:24]; + assign rVStage_uid51_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_c = vStagei_uid49_lzcShifterZ1_uid6_fxpToFPTest_q[23:0]; + + // cStage_uid55_lzcShifterZ1_uid6_fxpToFPTest(BITJOIN,54)@2 + assign cStage_uid55_lzcShifterZ1_uid6_fxpToFPTest_q = {rVStage_uid51_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_c, expZ_uid33_fxpToFPTest_q}; + + // rVStage_uid44_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select(BITSELECT,85)@1 + assign rVStage_uid44_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_b = vStagei_uid42_lzcShifterZ1_uid6_fxpToFPTest_q[31:16]; + assign rVStage_uid44_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_c = vStagei_uid42_lzcShifterZ1_uid6_fxpToFPTest_q[15:0]; + + // zs_uid43_lzcShifterZ1_uid6_fxpToFPTest(CONSTANT,42) + assign zs_uid43_lzcShifterZ1_uid6_fxpToFPTest_q = 16'b0000000000000000; + + // cStage_uid48_lzcShifterZ1_uid6_fxpToFPTest(BITJOIN,47)@1 + assign cStage_uid48_lzcShifterZ1_uid6_fxpToFPTest_q = {rVStage_uid44_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_c, zs_uid43_lzcShifterZ1_uid6_fxpToFPTest_q}; + + // zs_uid38_lzcShifterZ1_uid6_fxpToFPTest(CONSTANT,37) + assign zs_uid38_lzcShifterZ1_uid6_fxpToFPTest_q = 32'b00000000000000000000000000000000; + + // redist10_xIn_a_1(DELAY,101) + dspba_delay_ver #( .width(32), .depth(1), .reset_kind("ASYNC") ) + redist10_xIn_a_1 ( .xin(a), .xout(redist10_xIn_a_1_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // vCount_uid40_lzcShifterZ1_uid6_fxpToFPTest(LOGICAL,39)@0 + 1 + assign vCount_uid40_lzcShifterZ1_uid6_fxpToFPTest_qi = a == zs_uid38_lzcShifterZ1_uid6_fxpToFPTest_q ? 1'b1 : 1'b0; + dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) + vCount_uid40_lzcShifterZ1_uid6_fxpToFPTest_delay ( .xin(vCount_uid40_lzcShifterZ1_uid6_fxpToFPTest_qi), .xout(vCount_uid40_lzcShifterZ1_uid6_fxpToFPTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // vStagei_uid42_lzcShifterZ1_uid6_fxpToFPTest(MUX,41)@1 + assign vStagei_uid42_lzcShifterZ1_uid6_fxpToFPTest_s = vCount_uid40_lzcShifterZ1_uid6_fxpToFPTest_q; + always @(vStagei_uid42_lzcShifterZ1_uid6_fxpToFPTest_s or en or redist10_xIn_a_1_q or zs_uid38_lzcShifterZ1_uid6_fxpToFPTest_q) + begin + unique case (vStagei_uid42_lzcShifterZ1_uid6_fxpToFPTest_s) + 1'b0 : vStagei_uid42_lzcShifterZ1_uid6_fxpToFPTest_q = redist10_xIn_a_1_q; + 1'b1 : vStagei_uid42_lzcShifterZ1_uid6_fxpToFPTest_q = zs_uid38_lzcShifterZ1_uid6_fxpToFPTest_q; + default : vStagei_uid42_lzcShifterZ1_uid6_fxpToFPTest_q = 32'b0; + endcase + end + + // vCount_uid45_lzcShifterZ1_uid6_fxpToFPTest(LOGICAL,44)@1 + assign vCount_uid45_lzcShifterZ1_uid6_fxpToFPTest_q = rVStage_uid44_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_b == zs_uid43_lzcShifterZ1_uid6_fxpToFPTest_q ? 1'b1 : 1'b0; + + // vStagei_uid49_lzcShifterZ1_uid6_fxpToFPTest(MUX,48)@1 + 1 + assign vStagei_uid49_lzcShifterZ1_uid6_fxpToFPTest_s = vCount_uid45_lzcShifterZ1_uid6_fxpToFPTest_q; + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + vStagei_uid49_lzcShifterZ1_uid6_fxpToFPTest_q <= 32'b0; + end + else if (en == 1'b1) + begin + unique case (vStagei_uid49_lzcShifterZ1_uid6_fxpToFPTest_s) + 1'b0 : vStagei_uid49_lzcShifterZ1_uid6_fxpToFPTest_q <= vStagei_uid42_lzcShifterZ1_uid6_fxpToFPTest_q; + 1'b1 : vStagei_uid49_lzcShifterZ1_uid6_fxpToFPTest_q <= cStage_uid48_lzcShifterZ1_uid6_fxpToFPTest_q; + default : vStagei_uid49_lzcShifterZ1_uid6_fxpToFPTest_q <= 32'b0; + endcase + end + end + + // vCount_uid52_lzcShifterZ1_uid6_fxpToFPTest(LOGICAL,51)@2 + assign vCount_uid52_lzcShifterZ1_uid6_fxpToFPTest_q = rVStage_uid51_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_b == expZ_uid33_fxpToFPTest_q ? 1'b1 : 1'b0; + + // vStagei_uid56_lzcShifterZ1_uid6_fxpToFPTest(MUX,55)@2 + 1 + assign vStagei_uid56_lzcShifterZ1_uid6_fxpToFPTest_s = vCount_uid52_lzcShifterZ1_uid6_fxpToFPTest_q; + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + vStagei_uid56_lzcShifterZ1_uid6_fxpToFPTest_q <= 32'b0; + end + else if (en == 1'b1) + begin + unique case (vStagei_uid56_lzcShifterZ1_uid6_fxpToFPTest_s) + 1'b0 : vStagei_uid56_lzcShifterZ1_uid6_fxpToFPTest_q <= vStagei_uid49_lzcShifterZ1_uid6_fxpToFPTest_q; + 1'b1 : vStagei_uid56_lzcShifterZ1_uid6_fxpToFPTest_q <= cStage_uid55_lzcShifterZ1_uid6_fxpToFPTest_q; + default : vStagei_uid56_lzcShifterZ1_uid6_fxpToFPTest_q <= 32'b0; + endcase + end + end + + // vCount_uid59_lzcShifterZ1_uid6_fxpToFPTest(LOGICAL,58)@3 + assign vCount_uid59_lzcShifterZ1_uid6_fxpToFPTest_q = rVStage_uid58_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_b == zs_uid57_lzcShifterZ1_uid6_fxpToFPTest_q ? 1'b1 : 1'b0; + + // vStagei_uid63_lzcShifterZ1_uid6_fxpToFPTest(MUX,62)@3 + assign vStagei_uid63_lzcShifterZ1_uid6_fxpToFPTest_s = vCount_uid59_lzcShifterZ1_uid6_fxpToFPTest_q; + always @(vStagei_uid63_lzcShifterZ1_uid6_fxpToFPTest_s or en or vStagei_uid56_lzcShifterZ1_uid6_fxpToFPTest_q or cStage_uid62_lzcShifterZ1_uid6_fxpToFPTest_q) + begin + unique case (vStagei_uid63_lzcShifterZ1_uid6_fxpToFPTest_s) + 1'b0 : vStagei_uid63_lzcShifterZ1_uid6_fxpToFPTest_q = vStagei_uid56_lzcShifterZ1_uid6_fxpToFPTest_q; + 1'b1 : vStagei_uid63_lzcShifterZ1_uid6_fxpToFPTest_q = cStage_uid62_lzcShifterZ1_uid6_fxpToFPTest_q; + default : vStagei_uid63_lzcShifterZ1_uid6_fxpToFPTest_q = 32'b0; + endcase + end + + // vCount_uid66_lzcShifterZ1_uid6_fxpToFPTest(LOGICAL,65)@3 + assign vCount_uid66_lzcShifterZ1_uid6_fxpToFPTest_q = rVStage_uid65_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_b == zs_uid64_lzcShifterZ1_uid6_fxpToFPTest_q ? 1'b1 : 1'b0; + + // vStagei_uid70_lzcShifterZ1_uid6_fxpToFPTest(MUX,69)@3 + 1 + assign vStagei_uid70_lzcShifterZ1_uid6_fxpToFPTest_s = vCount_uid66_lzcShifterZ1_uid6_fxpToFPTest_q; + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + vStagei_uid70_lzcShifterZ1_uid6_fxpToFPTest_q <= 32'b0; + end + else if (en == 1'b1) + begin + unique case (vStagei_uid70_lzcShifterZ1_uid6_fxpToFPTest_s) + 1'b0 : vStagei_uid70_lzcShifterZ1_uid6_fxpToFPTest_q <= vStagei_uid63_lzcShifterZ1_uid6_fxpToFPTest_q; + 1'b1 : vStagei_uid70_lzcShifterZ1_uid6_fxpToFPTest_q <= cStage_uid69_lzcShifterZ1_uid6_fxpToFPTest_q; + default : vStagei_uid70_lzcShifterZ1_uid6_fxpToFPTest_q <= 32'b0; + endcase + end + end + + // vCount_uid73_lzcShifterZ1_uid6_fxpToFPTest(LOGICAL,72)@4 + assign vCount_uid73_lzcShifterZ1_uid6_fxpToFPTest_q = rVStage_uid72_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_b == GND_q ? 1'b1 : 1'b0; + + // vStagei_uid77_lzcShifterZ1_uid6_fxpToFPTest(MUX,76)@4 + assign vStagei_uid77_lzcShifterZ1_uid6_fxpToFPTest_s = vCount_uid73_lzcShifterZ1_uid6_fxpToFPTest_q; + always @(vStagei_uid77_lzcShifterZ1_uid6_fxpToFPTest_s or en or vStagei_uid70_lzcShifterZ1_uid6_fxpToFPTest_q or cStage_uid76_lzcShifterZ1_uid6_fxpToFPTest_q) + begin + unique case (vStagei_uid77_lzcShifterZ1_uid6_fxpToFPTest_s) + 1'b0 : vStagei_uid77_lzcShifterZ1_uid6_fxpToFPTest_q = vStagei_uid70_lzcShifterZ1_uid6_fxpToFPTest_q; + 1'b1 : vStagei_uid77_lzcShifterZ1_uid6_fxpToFPTest_q = cStage_uid76_lzcShifterZ1_uid6_fxpToFPTest_q; + default : vStagei_uid77_lzcShifterZ1_uid6_fxpToFPTest_q = 32'b0; + endcase + end + + // fracRnd_uid11_fxpToFPTest_merged_bit_select(BITSELECT,90)@4 + assign fracRnd_uid11_fxpToFPTest_merged_bit_select_in = vStagei_uid77_lzcShifterZ1_uid6_fxpToFPTest_q[30:0]; + assign fracRnd_uid11_fxpToFPTest_merged_bit_select_b = fracRnd_uid11_fxpToFPTest_merged_bit_select_in[30:7]; + assign fracRnd_uid11_fxpToFPTest_merged_bit_select_c = fracRnd_uid11_fxpToFPTest_merged_bit_select_in[6:0]; + + // sticky_uid16_fxpToFPTest(LOGICAL,15)@4 + 1 + assign sticky_uid16_fxpToFPTest_qi = fracRnd_uid11_fxpToFPTest_merged_bit_select_c != 7'b0000000 ? 1'b1 : 1'b0; + dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) + sticky_uid16_fxpToFPTest_delay ( .xin(sticky_uid16_fxpToFPTest_qi), .xout(sticky_uid16_fxpToFPTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // nr_uid17_fxpToFPTest(LOGICAL,16)@5 + assign nr_uid17_fxpToFPTest_q = ~ (l_uid13_fxpToFPTest_merged_bit_select_c); + + // maxCount_uid7_fxpToFPTest(CONSTANT,6) + assign maxCount_uid7_fxpToFPTest_q = 6'b100000; + + // redist5_vCount_uid40_lzcShifterZ1_uid6_fxpToFPTest_q_4(DELAY,96) + dspba_delay_ver #( .width(1), .depth(3), .reset_kind("ASYNC") ) + redist5_vCount_uid40_lzcShifterZ1_uid6_fxpToFPTest_q_4 ( .xin(vCount_uid40_lzcShifterZ1_uid6_fxpToFPTest_q), .xout(redist5_vCount_uid40_lzcShifterZ1_uid6_fxpToFPTest_q_4_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // redist4_vCount_uid45_lzcShifterZ1_uid6_fxpToFPTest_q_3(DELAY,95) + dspba_delay_ver #( .width(1), .depth(3), .reset_kind("ASYNC") ) + redist4_vCount_uid45_lzcShifterZ1_uid6_fxpToFPTest_q_3 ( .xin(vCount_uid45_lzcShifterZ1_uid6_fxpToFPTest_q), .xout(redist4_vCount_uid45_lzcShifterZ1_uid6_fxpToFPTest_q_3_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // redist3_vCount_uid52_lzcShifterZ1_uid6_fxpToFPTest_q_2(DELAY,94) + dspba_delay_ver #( .width(1), .depth(2), .reset_kind("ASYNC") ) + redist3_vCount_uid52_lzcShifterZ1_uid6_fxpToFPTest_q_2 ( .xin(vCount_uid52_lzcShifterZ1_uid6_fxpToFPTest_q), .xout(redist3_vCount_uid52_lzcShifterZ1_uid6_fxpToFPTest_q_2_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // redist2_vCount_uid59_lzcShifterZ1_uid6_fxpToFPTest_q_1(DELAY,93) + dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) + redist2_vCount_uid59_lzcShifterZ1_uid6_fxpToFPTest_q_1 ( .xin(vCount_uid59_lzcShifterZ1_uid6_fxpToFPTest_q), .xout(redist2_vCount_uid59_lzcShifterZ1_uid6_fxpToFPTest_q_1_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // redist1_vCount_uid66_lzcShifterZ1_uid6_fxpToFPTest_q_1(DELAY,92) + dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) + redist1_vCount_uid66_lzcShifterZ1_uid6_fxpToFPTest_q_1 ( .xin(vCount_uid66_lzcShifterZ1_uid6_fxpToFPTest_q), .xout(redist1_vCount_uid66_lzcShifterZ1_uid6_fxpToFPTest_q_1_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // vCount_uid78_lzcShifterZ1_uid6_fxpToFPTest(BITJOIN,77)@4 + assign vCount_uid78_lzcShifterZ1_uid6_fxpToFPTest_q = {redist5_vCount_uid40_lzcShifterZ1_uid6_fxpToFPTest_q_4_q, redist4_vCount_uid45_lzcShifterZ1_uid6_fxpToFPTest_q_3_q, redist3_vCount_uid52_lzcShifterZ1_uid6_fxpToFPTest_q_2_q, redist2_vCount_uid59_lzcShifterZ1_uid6_fxpToFPTest_q_1_q, redist1_vCount_uid66_lzcShifterZ1_uid6_fxpToFPTest_q_1_q, vCount_uid73_lzcShifterZ1_uid6_fxpToFPTest_q}; + + // vCountBig_uid80_lzcShifterZ1_uid6_fxpToFPTest(COMPARE,79)@4 + assign vCountBig_uid80_lzcShifterZ1_uid6_fxpToFPTest_a = {2'b00, maxCount_uid7_fxpToFPTest_q}; + assign vCountBig_uid80_lzcShifterZ1_uid6_fxpToFPTest_b = {2'b00, vCount_uid78_lzcShifterZ1_uid6_fxpToFPTest_q}; + assign vCountBig_uid80_lzcShifterZ1_uid6_fxpToFPTest_o = $unsigned(vCountBig_uid80_lzcShifterZ1_uid6_fxpToFPTest_a) - $unsigned(vCountBig_uid80_lzcShifterZ1_uid6_fxpToFPTest_b); + assign vCountBig_uid80_lzcShifterZ1_uid6_fxpToFPTest_c[0] = vCountBig_uid80_lzcShifterZ1_uid6_fxpToFPTest_o[7]; + + // vCountFinal_uid82_lzcShifterZ1_uid6_fxpToFPTest(MUX,81)@4 + 1 + assign vCountFinal_uid82_lzcShifterZ1_uid6_fxpToFPTest_s = vCountBig_uid80_lzcShifterZ1_uid6_fxpToFPTest_c; + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + vCountFinal_uid82_lzcShifterZ1_uid6_fxpToFPTest_q <= 6'b0; + end + else if (en == 1'b1) + begin + unique case (vCountFinal_uid82_lzcShifterZ1_uid6_fxpToFPTest_s) + 1'b0 : vCountFinal_uid82_lzcShifterZ1_uid6_fxpToFPTest_q <= vCount_uid78_lzcShifterZ1_uid6_fxpToFPTest_q; + 1'b1 : vCountFinal_uid82_lzcShifterZ1_uid6_fxpToFPTest_q <= maxCount_uid7_fxpToFPTest_q; + default : vCountFinal_uid82_lzcShifterZ1_uid6_fxpToFPTest_q <= 6'b0; + endcase + end + end + + // msbIn_uid9_fxpToFPTest(CONSTANT,8) + assign msbIn_uid9_fxpToFPTest_q = 8'b10011110; + + // expPreRnd_uid10_fxpToFPTest(SUB,9)@5 + assign expPreRnd_uid10_fxpToFPTest_a = {1'b0, msbIn_uid9_fxpToFPTest_q}; + assign expPreRnd_uid10_fxpToFPTest_b = {3'b000, vCountFinal_uid82_lzcShifterZ1_uid6_fxpToFPTest_q}; + assign expPreRnd_uid10_fxpToFPTest_o = $unsigned(expPreRnd_uid10_fxpToFPTest_a) - $unsigned(expPreRnd_uid10_fxpToFPTest_b); + assign expPreRnd_uid10_fxpToFPTest_q = expPreRnd_uid10_fxpToFPTest_o[8:0]; + + // redist0_fracRnd_uid11_fxpToFPTest_merged_bit_select_b_1(DELAY,91) + dspba_delay_ver #( .width(24), .depth(1), .reset_kind("ASYNC") ) + redist0_fracRnd_uid11_fxpToFPTest_merged_bit_select_b_1 ( .xin(fracRnd_uid11_fxpToFPTest_merged_bit_select_b), .xout(redist0_fracRnd_uid11_fxpToFPTest_merged_bit_select_b_1_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // expFracRnd_uid12_fxpToFPTest(BITJOIN,11)@5 + assign expFracRnd_uid12_fxpToFPTest_q = {expPreRnd_uid10_fxpToFPTest_q, redist0_fracRnd_uid11_fxpToFPTest_merged_bit_select_b_1_q}; + + // l_uid13_fxpToFPTest_merged_bit_select(BITSELECT,84)@5 + assign l_uid13_fxpToFPTest_merged_bit_select_in = expFracRnd_uid12_fxpToFPTest_q[1:0]; + assign l_uid13_fxpToFPTest_merged_bit_select_b = l_uid13_fxpToFPTest_merged_bit_select_in[1:1]; + assign l_uid13_fxpToFPTest_merged_bit_select_c = l_uid13_fxpToFPTest_merged_bit_select_in[0:0]; + + // rnd_uid18_fxpToFPTest(LOGICAL,17)@5 + 1 + assign rnd_uid18_fxpToFPTest_qi = l_uid13_fxpToFPTest_merged_bit_select_b | nr_uid17_fxpToFPTest_q | sticky_uid16_fxpToFPTest_q; + dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) + rnd_uid18_fxpToFPTest_delay ( .xin(rnd_uid18_fxpToFPTest_qi), .xout(rnd_uid18_fxpToFPTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // redist8_expFracRnd_uid12_fxpToFPTest_q_1(DELAY,99) + dspba_delay_ver #( .width(33), .depth(1), .reset_kind("ASYNC") ) + redist8_expFracRnd_uid12_fxpToFPTest_q_1 ( .xin(expFracRnd_uid12_fxpToFPTest_q), .xout(redist8_expFracRnd_uid12_fxpToFPTest_q_1_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // expFracR_uid20_fxpToFPTest(ADD,19)@6 + assign expFracR_uid20_fxpToFPTest_a = {{2{redist8_expFracRnd_uid12_fxpToFPTest_q_1_q[32]}}, redist8_expFracRnd_uid12_fxpToFPTest_q_1_q}; + assign expFracR_uid20_fxpToFPTest_b = {34'b0000000000000000000000000000000000, rnd_uid18_fxpToFPTest_q}; + assign expFracR_uid20_fxpToFPTest_o = $signed(expFracR_uid20_fxpToFPTest_a) + $signed(expFracR_uid20_fxpToFPTest_b); + assign expFracR_uid20_fxpToFPTest_q = expFracR_uid20_fxpToFPTest_o[33:0]; + + // expR_uid22_fxpToFPTest(BITSELECT,21)@6 + assign expR_uid22_fxpToFPTest_b = expFracR_uid20_fxpToFPTest_q[33:24]; + + // redist6_expR_uid22_fxpToFPTest_b_1(DELAY,97) + dspba_delay_ver #( .width(10), .depth(1), .reset_kind("ASYNC") ) + redist6_expR_uid22_fxpToFPTest_b_1 ( .xin(expR_uid22_fxpToFPTest_b), .xout(redist6_expR_uid22_fxpToFPTest_b_1_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // expR_uid34_fxpToFPTest(BITSELECT,33)@7 + assign expR_uid34_fxpToFPTest_in = redist6_expR_uid22_fxpToFPTest_b_1_q[7:0]; + assign expR_uid34_fxpToFPTest_b = expR_uid34_fxpToFPTest_in[7:0]; + + // ovf_uid25_fxpToFPTest(COMPARE,24)@7 + assign ovf_uid25_fxpToFPTest_a = {{2{redist6_expR_uid22_fxpToFPTest_b_1_q[9]}}, redist6_expR_uid22_fxpToFPTest_b_1_q}; + assign ovf_uid25_fxpToFPTest_b = {4'b0000, expInf_uid24_fxpToFPTest_q}; + assign ovf_uid25_fxpToFPTest_o = $signed(ovf_uid25_fxpToFPTest_a) - $signed(ovf_uid25_fxpToFPTest_b); + assign ovf_uid25_fxpToFPTest_n[0] = ~ (ovf_uid25_fxpToFPTest_o[11]); + + // inIsZero_uid8_fxpToFPTest(LOGICAL,7)@5 + 1 + assign inIsZero_uid8_fxpToFPTest_qi = vCountFinal_uid82_lzcShifterZ1_uid6_fxpToFPTest_q == maxCount_uid7_fxpToFPTest_q ? 1'b1 : 1'b0; + dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) + inIsZero_uid8_fxpToFPTest_delay ( .xin(inIsZero_uid8_fxpToFPTest_qi), .xout(inIsZero_uid8_fxpToFPTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // redist9_inIsZero_uid8_fxpToFPTest_q_2(DELAY,100) + dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) + redist9_inIsZero_uid8_fxpToFPTest_q_2 ( .xin(inIsZero_uid8_fxpToFPTest_q), .xout(redist9_inIsZero_uid8_fxpToFPTest_q_2_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // udf_uid23_fxpToFPTest(COMPARE,22)@7 + assign udf_uid23_fxpToFPTest_a = {11'b00000000000, GND_q}; + assign udf_uid23_fxpToFPTest_b = {{2{redist6_expR_uid22_fxpToFPTest_b_1_q[9]}}, redist6_expR_uid22_fxpToFPTest_b_1_q}; + assign udf_uid23_fxpToFPTest_o = $signed(udf_uid23_fxpToFPTest_a) - $signed(udf_uid23_fxpToFPTest_b); + assign udf_uid23_fxpToFPTest_n[0] = ~ (udf_uid23_fxpToFPTest_o[11]); + + // udfOrInZero_uid29_fxpToFPTest(LOGICAL,28)@7 + assign udfOrInZero_uid29_fxpToFPTest_q = udf_uid23_fxpToFPTest_n | redist9_inIsZero_uid8_fxpToFPTest_q_2_q; + + // excSelector_uid30_fxpToFPTest(BITJOIN,29)@7 + assign excSelector_uid30_fxpToFPTest_q = {ovf_uid25_fxpToFPTest_n, udfOrInZero_uid29_fxpToFPTest_q}; + + // expRPostExc_uid35_fxpToFPTest(MUX,34)@7 + assign expRPostExc_uid35_fxpToFPTest_s = excSelector_uid30_fxpToFPTest_q; + always @(expRPostExc_uid35_fxpToFPTest_s or en or expR_uid34_fxpToFPTest_b or expZ_uid33_fxpToFPTest_q or expInf_uid24_fxpToFPTest_q) + begin + unique case (expRPostExc_uid35_fxpToFPTest_s) + 2'b00 : expRPostExc_uid35_fxpToFPTest_q = expR_uid34_fxpToFPTest_b; + 2'b01 : expRPostExc_uid35_fxpToFPTest_q = expZ_uid33_fxpToFPTest_q; + 2'b10 : expRPostExc_uid35_fxpToFPTest_q = expInf_uid24_fxpToFPTest_q; + 2'b11 : expRPostExc_uid35_fxpToFPTest_q = expInf_uid24_fxpToFPTest_q; + default : expRPostExc_uid35_fxpToFPTest_q = 8'b0; + endcase + end + + // fracZ_uid27_fxpToFPTest(CONSTANT,26) + assign fracZ_uid27_fxpToFPTest_q = 23'b00000000000000000000000; + + // fracR_uid21_fxpToFPTest(BITSELECT,20)@6 + assign fracR_uid21_fxpToFPTest_in = expFracR_uid20_fxpToFPTest_q[23:0]; + assign fracR_uid21_fxpToFPTest_b = fracR_uid21_fxpToFPTest_in[23:1]; + + // redist7_fracR_uid21_fxpToFPTest_b_1(DELAY,98) + dspba_delay_ver #( .width(23), .depth(1), .reset_kind("ASYNC") ) + redist7_fracR_uid21_fxpToFPTest_b_1 ( .xin(fracR_uid21_fxpToFPTest_b), .xout(redist7_fracR_uid21_fxpToFPTest_b_1_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // excSelector_uid26_fxpToFPTest(LOGICAL,25)@7 + assign excSelector_uid26_fxpToFPTest_q = redist9_inIsZero_uid8_fxpToFPTest_q_2_q | ovf_uid25_fxpToFPTest_n | udf_uid23_fxpToFPTest_n; + + // fracRPostExc_uid28_fxpToFPTest(MUX,27)@7 + assign fracRPostExc_uid28_fxpToFPTest_s = excSelector_uid26_fxpToFPTest_q; + always @(fracRPostExc_uid28_fxpToFPTest_s or en or redist7_fracR_uid21_fxpToFPTest_b_1_q or fracZ_uid27_fxpToFPTest_q) + begin + unique case (fracRPostExc_uid28_fxpToFPTest_s) + 1'b0 : fracRPostExc_uid28_fxpToFPTest_q = redist7_fracR_uid21_fxpToFPTest_b_1_q; + 1'b1 : fracRPostExc_uid28_fxpToFPTest_q = fracZ_uid27_fxpToFPTest_q; + default : fracRPostExc_uid28_fxpToFPTest_q = 23'b0; + endcase + end + + // outRes_uid36_fxpToFPTest(BITJOIN,35)@7 + assign outRes_uid36_fxpToFPTest_q = {GND_q, expRPostExc_uid35_fxpToFPTest_q, fracRPostExc_uid28_fxpToFPTest_q}; + + // xOut(GPOUT,4)@7 + assign q = outRes_uid36_fxpToFPTest_q; + +endmodule diff --git a/hw/rtl/fp_cores/altera/dspba_delay_ver.sv b/hw/rtl/fp_cores/altera/dspba_delay_ver.sv new file mode 100644 index 00000000..526de10a --- /dev/null +++ b/hw/rtl/fp_cores/altera/dspba_delay_ver.sv @@ -0,0 +1,95 @@ +// Legal Notice: Copyright 2017 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing device programming or simulation files), and +// any associated documentation or information are expressly subject to the +// terms and conditions of the Intel FPGA Software License Agreement, +// Intel MegaCore Function License Agreement, or other applicable license +// agreement, including, without limitation, that your use is for the sole +// purpose of programming logic devices manufactured by Intel and sold by +// Intel or its authorized distributors. Please refer to the applicable +// agreement for further details. + +module dspba_delay_ver +#( + parameter width = 8, + parameter depth = 1, + parameter reset_high = 1'b1, + parameter reset_kind = "ASYNC" +) ( + input clk, + input aclr, + input ena, + input [width-1:0] xin, + output [width-1:0] xout +); + + wire reset; + reg [width-1:0] delays [depth-1:0]; + + assign reset = aclr ^ reset_high; + + generate + if (depth > 0) + begin + genvar i; + for (i = 0; i < depth; ++i) + begin : delay_block + if (reset_kind == "ASYNC") + begin : sync_reset + always @ (posedge clk or negedge reset) + begin: a + if (!reset) begin + delays[i] <= 0; + end else begin + if (ena) begin + if (i > 0) begin + delays[i] <= delays[i - 1]; + end else begin + delays[i] <= xin; + end + end + end + end + end + + if (reset_kind == "SYNC") + begin : async_reset + always @ (posedge clk) + begin: a + if (!reset) begin + delays[i] <= 0; + end else begin + if (ena) begin + if (i > 0) begin + delays[i] <= delays[i - 1]; + end else begin + delays[i] <= xin; + end + end + end + end + end + + if (reset_kind == "NONE") + begin : no_reset + always @ (posedge clk) + begin: a + if (ena) begin + if (i > 0) begin + delays[i] <= delays[i - 1]; + end else begin + delays[i] <= xin; + end + end + end + end + end + + assign xout = delays[depth - 1]; + end else begin + assign xout = xin; + end + endgenerate + +endmodule \ No newline at end of file diff --git a/hw/rtl/fp_cores/fpnew b/hw/rtl/fp_cores/fpnew new file mode 160000 index 00000000..1def7bb6 --- /dev/null +++ b/hw/rtl/fp_cores/fpnew @@ -0,0 +1 @@ +Subproject commit 1def7bb630ceae2ebc58921f6b5ee3e686fb6d5a diff --git a/hw/rtl/fp_cores/svdpi/float_dpi.cpp b/hw/rtl/fp_cores/svdpi/float_dpi.cpp new file mode 100644 index 00000000..dc5d1bcd --- /dev/null +++ b/hw/rtl/fp_cores/svdpi/float_dpi.cpp @@ -0,0 +1,230 @@ +#include +#include +#include +#include +#include +#include "svdpi.h" +#include "verilated_vpi.h" +#include "VX_config.h" + +extern "C" { + void dpi_fadd(int inst, bool enable, int a, int b, int* result); + void dpi_fsub(int inst, bool enable, int a, int b, int* result); + void dpi_fmul(int inst, bool enable, int a, int b, int* result); + void dpi_fmadd(int inst, bool enable, int a, int b, int c, int* result); + void dpi_fmsub(int inst, bool enable, int a, int b, int c, int* result); + void dpi_fdiv(int inst, bool enable, int a, int b, int* result); + void dpi_fsqrt(int inst, bool enable, int a, int* result); + void dpi_ftoi(int inst, bool enable, int a, int* result); + void dpi_ftou(int inst, bool enable, int a, int* result); + void dpi_itof(int inst, bool enable, int a, int* result); + void dpi_utof(int inst, bool enable, int a, int* result); +} + +class ShiftRegister { +public: + ShiftRegister() : init_(false), depth_(0) {} + + void ensure_init(int depth) { + if (!init_) { + buffer_.resize(depth); + init_ = true; + depth_ = depth; + } + } + + void push(int value, bool enable) { + if (!enable) + return; + for (unsigned i = 0; i < depth_-1; ++i) { + buffer_[i] = buffer_[i+1]; + } + buffer_[depth_-1] = value; + } + + int top() const { + return buffer_[0]; + } + +private: + + std::vector buffer_; + bool init_; + unsigned depth_; +}; + +union Float_t { + float f; + int i; + struct { + uint32_t man : 23; + uint32_t exp : 8; + uint32_t sign : 1; + } parts; +}; + +class Instances { +public: + ShiftRegister& get(int inst) { + mutex_.lock(); + ShiftRegister& sr = instances_[inst]; + mutex_.unlock(); + return sr; + } + +private: + std::unordered_map instances_; + std::mutex mutex_; +}; + +Instances instances; + +void dpi_fadd(int inst, bool enable, int a, int b, int* result) { + ShiftRegister& sr = instances.get(inst); + + Float_t fa, fb, fr; + + fa.i = a; + fb.i = b; + fr.f = fa.f + fb.f; + + sr.ensure_init(LATENCY_FADDMUL); + sr.push(fr.i, enable); + *result = sr.top(); +} + +void dpi_fsub(int inst, bool enable, int a, int b, int* result) { + ShiftRegister& sr = instances.get(inst); + + Float_t fa, fb, fr; + + fa.i = a; + fb.i = b; + fr.f = fa.f - fb.f; + + sr.ensure_init(LATENCY_FADDMUL); + sr.push(fr.i, enable); + *result = sr.top(); +} + +void dpi_fmul(int inst, bool enable, int a, int b, int* result) { + ShiftRegister& sr = instances.get(inst); + + Float_t fa, fb, fr; + + fa.i = a; + fb.i = b; + fr.f = fa.f * fb.f; + + sr.ensure_init(LATENCY_FADDMUL); + sr.push(fr.i, enable); + *result = sr.top(); +} + +void dpi_fmadd(int inst, bool enable, int a, int b, int c, int* result) { + ShiftRegister& sr = instances.get(inst); + + Float_t fa, fb, fc, fr; + + fa.i = a; + fb.i = b; + fc.i = c; + fr.f = fa.f * fb.f + fc.f; + + sr.ensure_init(LATENCY_FMADD); + sr.push(fr.i, enable); + *result = sr.top(); +} + +void dpi_fmsub(int inst, bool enable, int a, int b, int c, int* result) { + ShiftRegister& sr = instances.get(inst); + + Float_t fa, fb, fc, fr; + + fa.i = a; + fb.i = b; + fc.i = c; + fr.f = fa.f * fb.f - fc.f; + + sr.ensure_init(LATENCY_FMADD); + sr.push(fr.i, enable); + *result = sr.top(); +} + +void dpi_fdiv(int inst, bool enable, int a, int b, int* result) { + ShiftRegister& sr = instances.get(inst); + + Float_t fa, fb, fr; + + fa.i = a; + fb.i = b; + fr.f = fa.f / fb.f; + + sr.ensure_init(LATENCY_FDIV); + sr.push(fr.i, enable); + *result = sr.top(); +} + +void dpi_fsqrt(int inst, bool enable, int a, int* result) { + ShiftRegister& sr = instances.get(inst); + + Float_t fa, fr; + + fa.i = a; + fr.f = sqrtf(fa.f); + + sr.ensure_init(LATENCY_FSQRT); + sr.push(fr.i, enable); + *result = sr.top(); +} + +void dpi_ftoi(int inst, bool enable, int a, int* result) { + ShiftRegister& sr = instances.get(inst); + + Float_t fa, fr; + + fa.i = a; + fr.i = int(fa.f); + + sr.ensure_init(LATENCY_FTOI); + sr.push(fr.i, enable); + *result = sr.top(); +} + +void dpi_ftou(int inst, bool enable, int a, int* result) { + ShiftRegister& sr = instances.get(inst); + + Float_t fa, fr; + + fa.i = a; + fr.i = unsigned(fa.f); + + sr.ensure_init(LATENCY_FTOI); + sr.push(fr.i, enable); + *result = sr.top(); +} + +void dpi_itof(int inst, bool enable, int a, int* result) { + ShiftRegister& sr = instances.get(inst); + + Float_t fa, fr; + + fr.f = (float)a; + + sr.ensure_init(LATENCY_ITOF); + sr.push(fr.i, enable); + *result = sr.top(); +} + +void dpi_utof(int inst, bool enable, int a, int* result) { + ShiftRegister& sr = instances.get(inst); + + Float_t fa, fr; + + unsigned ua = a; + fr.f = (float)ua; + + sr.ensure_init(LATENCY_ITOF); + sr.push(fr.i, enable); + *result = sr.top(); +} \ No newline at end of file diff --git a/hw/rtl/fp_cores/svdpi/float_dpi.vh b/hw/rtl/fp_cores/svdpi/float_dpi.vh new file mode 100644 index 00000000..a94dc34c --- /dev/null +++ b/hw/rtl/fp_cores/svdpi/float_dpi.vh @@ -0,0 +1,16 @@ +`ifndef FLOAT_DPI +`define FLOAT_DPI + +import "DPI-C" context function void dpi_fadd(int inst, input logic enable, input int a, input int b, output int result); +import "DPI-C" context function void dpi_fsub(int inst, input logic enable, input int a, input int b, output int result); +import "DPI-C" context function void dpi_fmul(int inst, input logic enable, input int a, input int b, output int result); +import "DPI-C" context function void dpi_fmadd(int inst, input logic enable, input int a, input int b, input int c, output int result); +import "DPI-C" context function void dpi_fmsub(int inst, input logic enable, input int a, input int b, input int c, output int result); +import "DPI-C" context function void dpi_fdiv(int inst, input logic enable, input int a, input int b, output int result); +import "DPI-C" context function void dpi_fsqrt(int inst, input logic enable, input int a, output int result); +import "DPI-C" context function void dpi_ftoi(int inst, input logic enable, input int a, output int result); +import "DPI-C" context function void dpi_ftou(int inst, input logic enable, input int a, output int result); +import "DPI-C" context function void dpi_itof(int inst, input logic enable, input int a, output int result); +import "DPI-C" context function void dpi_utof(int inst, input logic enable, input int a, output int result); + +`endif \ No newline at end of file diff --git a/hw/rtl/interfaces/VX_alu_req_if.v b/hw/rtl/interfaces/VX_alu_req_if.v new file mode 100644 index 00000000..d940cc7a --- /dev/null +++ b/hw/rtl/interfaces/VX_alu_req_if.v @@ -0,0 +1,29 @@ +`ifndef VX_ALU_REQ_IF +`define VX_ALU_REQ_IF + +`include "VX_define.vh" + +interface VX_alu_req_if (); + + wire valid; + + wire [`NW_BITS-1:0] wid; + wire [`NUM_THREADS-1:0] tmask; + wire [31:0] PC; + wire [31:0] next_PC; + wire [`ALU_BR_BITS-1:0] op_type; + wire is_br_op; + wire rs1_is_PC; + wire rs2_is_imm; + wire [31:0] imm; + wire [`NT_BITS-1:0] tid; + wire [`NUM_THREADS-1:0][31:0] rs1_data; + wire [`NUM_THREADS-1:0][31:0] rs2_data; + wire [`NR_BITS-1:0] rd; + wire wb; + + wire ready; + +endinterface + +`endif \ No newline at end of file diff --git a/hw/rtl/interfaces/VX_backend_req_if.v b/hw/rtl/interfaces/VX_backend_req_if.v deleted file mode 100644 index f153f1b6..00000000 --- a/hw/rtl/interfaces/VX_backend_req_if.v +++ /dev/null @@ -1,40 +0,0 @@ -`ifndef VX_FrE_to_BCKBE_REQ_IF -`define VX_FrE_to_BCKBE_REQ_IF - -`include "VX_define.vh" - -interface VX_backend_req_if (); - - wire [`NUM_THREADS-1:0] valid; - wire [`NW_BITS-1:0] warp_num; - wire [31:0] curr_PC; - wire [11:0] csr_addr; - wire is_csr; - wire csr_immed; - wire [31:0] csr_mask; - wire [4:0] rd; - wire [4:0] rs1; - wire [4:0] rs2; - wire [4:0] alu_op; - wire [1:0] wb; - wire rs2_src; - wire [31:0] itype_immed; - wire [`BYTE_EN_BITS-1:0] mem_read; - wire [`BYTE_EN_BITS-1:0] mem_write; - wire [2:0] branch_type; - wire [19:0] upper_immed; - wire is_etype; - wire is_jal; - wire jal; - wire [31:0] jal_offset; - wire [31:0] next_PC; - - // GPGPU stuff - wire is_wspawn; - wire is_tmc; - wire is_split; - wire is_barrier; - -endinterface - -`endif \ No newline at end of file diff --git a/hw/rtl/interfaces/VX_branch_ctl_if.v b/hw/rtl/interfaces/VX_branch_ctl_if.v new file mode 100644 index 00000000..5e5e840a --- /dev/null +++ b/hw/rtl/interfaces/VX_branch_ctl_if.v @@ -0,0 +1,15 @@ +`ifndef VX_BRANCH_RSP_IF +`define VX_BRANCH_RSP_IF + +`include "VX_define.vh" + +interface VX_branch_ctl_if (); + + wire valid; + wire [`NW_BITS-1:0] wid; + wire taken; + wire [31:0] dest; + +endinterface + +`endif \ No newline at end of file diff --git a/hw/rtl/interfaces/VX_branch_rsp_if.v b/hw/rtl/interfaces/VX_branch_rsp_if.v deleted file mode 100644 index a8f01d44..00000000 --- a/hw/rtl/interfaces/VX_branch_rsp_if.v +++ /dev/null @@ -1,15 +0,0 @@ -`ifndef VX_BRANCH_RSP_IF -`define VX_BRANCH_RSP_IF - -`include "VX_define.vh" - -interface VX_branch_rsp_if (); - - wire valid; - wire dir; - wire [31:0] dest; - wire [`NW_BITS-1:0] warp_num; - -endinterface - -`endif \ No newline at end of file diff --git a/hw/rtl/interfaces/VX_cmt_to_csr_if.v b/hw/rtl/interfaces/VX_cmt_to_csr_if.v new file mode 100644 index 00000000..592206a4 --- /dev/null +++ b/hw/rtl/interfaces/VX_cmt_to_csr_if.v @@ -0,0 +1,19 @@ +`ifndef VX_CMT_TO_CSR_IF +`define VX_CMT_TO_CSR_IF + +`include "VX_define.vh" + +interface VX_cmt_to_csr_if (); + + wire valid; + + wire [`NW_BITS-1:0] wid; + + wire [$clog2(`NUM_EXS+1)-1:0] num_commits; + + wire has_fflags; + fflags_t fflags; + +endinterface + +`endif \ No newline at end of file diff --git a/hw/rtl/interfaces/VX_csr_io_req_if.v b/hw/rtl/interfaces/VX_csr_io_req_if.v index ce8d2fed..a5307a08 100644 --- a/hw/rtl/interfaces/VX_csr_io_req_if.v +++ b/hw/rtl/interfaces/VX_csr_io_req_if.v @@ -5,11 +5,11 @@ interface VX_csr_io_req_if (); - wire valid; - wire rw; - wire [11:0] addr; - wire [31:0] data; - wire ready; + wire valid; + wire [`CSR_ADDR_BITS-1:0] addr; + wire rw; + wire [31:0] data; + wire ready; endinterface diff --git a/hw/rtl/interfaces/VX_csr_req_if.v b/hw/rtl/interfaces/VX_csr_req_if.v index 6eeddf74..2c4a79a2 100644 --- a/hw/rtl/interfaces/VX_csr_req_if.v +++ b/hw/rtl/interfaces/VX_csr_req_if.v @@ -5,18 +5,20 @@ interface VX_csr_req_if (); - wire [`NUM_THREADS-1:0] valid; - wire [`NW_BITS-1:0] warp_num; - wire [4:0] rd; - wire [1:0] wb; - wire [4:0] alu_op; - wire is_csr; - wire [11:0] csr_addr; - wire csr_immed; - wire [31:0] csr_mask; - - wire is_io; + wire valid; + wire [`NW_BITS-1:0] wid; + wire [`NUM_THREADS-1:0] tmask; + wire [31:0] PC; + wire [`CSR_BITS-1:0] op_type; + wire [`CSR_ADDR_BITS-1:0] csr_addr; + wire [31:0] csr_mask; + wire [`NR_BITS-1:0] rd; + wire wb; + wire is_io; + + wire ready; + endinterface -`endif +`endif \ No newline at end of file diff --git a/hw/rtl/interfaces/VX_csr_to_issue_if.v b/hw/rtl/interfaces/VX_csr_to_issue_if.v new file mode 100644 index 00000000..f222370c --- /dev/null +++ b/hw/rtl/interfaces/VX_csr_to_issue_if.v @@ -0,0 +1,17 @@ +`ifndef VX_CSR_TO_ISSUE_IF +`define VX_CSR_TO_ISSUE_IF + +`include "VX_define.vh" + +`ifndef EXTF_F_ENABLE + `IGNORE_WARNINGS_BEGIN +`endif + +interface VX_csr_to_issue_if (); + + wire [`NW_BITS-1:0] wid; + wire [`FRM_BITS-1:0] frm; + +endinterface + +`endif \ No newline at end of file diff --git a/hw/rtl/interfaces/VX_decode_if.v b/hw/rtl/interfaces/VX_decode_if.v new file mode 100644 index 00000000..b253ecbe --- /dev/null +++ b/hw/rtl/interfaces/VX_decode_if.v @@ -0,0 +1,34 @@ +`ifndef VX_DECODE_IF +`define VX_DECODE_IF + +`include "VX_define.vh" + +interface VX_decode_if (); + + wire valid; + + wire [`NW_BITS-1:0] wid; + wire [`NUM_THREADS-1:0] tmask; + wire [31:0] PC; + + wire [`EX_BITS-1:0] ex_type; + wire [`OP_BITS-1:0] op_type; + wire [`MOD_BITS-1:0] op_mod; + wire wb; + + wire [`NR_BITS-1:0] rd; + wire [`NR_BITS-1:0] rs1; + wire [`NR_BITS-1:0] rs2; + wire [`NR_BITS-1:0] rs3; + wire [31:0] imm; + + wire rs1_is_PC; + wire rs2_is_imm; + wire use_rs3; + wire [`NUM_REGS-1:0] used_regs; + + wire ready; + +endinterface + +`endif \ No newline at end of file diff --git a/hw/rtl/interfaces/VX_exec_unit_req_if.v b/hw/rtl/interfaces/VX_exec_unit_req_if.v deleted file mode 100644 index 918cb456..00000000 --- a/hw/rtl/interfaces/VX_exec_unit_req_if.v +++ /dev/null @@ -1,47 +0,0 @@ -`ifndef VX_EXE_UNIT_REQ_IF -`define VX_EXE_UNIT_REQ_IF - -`include "VX_define.vh" - -interface VX_exec_unit_req_if (); - - // Meta - wire [`NUM_THREADS-1:0] valid; - wire [`NW_BITS-1:0] warp_num; - wire [31:0] curr_PC; - wire [31:0] next_PC; - - // Write Back Info - wire [4:0] rd; - wire [1:0] wb; - - // Data and alu op - wire [`NUM_THREADS-1:0][31:0] a_reg_data; - wire [`NUM_THREADS-1:0][31:0] b_reg_data; - wire [4:0] alu_op; - wire [4:0] rs1; - wire [4:0] rs2; - wire rs2_src; - wire [31:0] itype_immed; - wire [19:0] upper_immed; - - // Branch type - wire [2:0] branch_type; - - // Jal info - wire is_jal; - wire jal; - wire [31:0] jal_offset; - - wire is_etype; - wire wspawn; - - // CSR info - wire is_csr; - wire [11:0] csr_addr; - wire csr_immed; - wire [31:0] csr_mask; - -endinterface - -`endif \ No newline at end of file diff --git a/hw/rtl/interfaces/VX_exu_to_cmt_if.v b/hw/rtl/interfaces/VX_exu_to_cmt_if.v new file mode 100644 index 00000000..86763e2a --- /dev/null +++ b/hw/rtl/interfaces/VX_exu_to_cmt_if.v @@ -0,0 +1,19 @@ +`ifndef VX_EXU_TO_CMT_IF +`define VX_EXU_TO_CMT_IF + +`include "VX_define.vh" + +interface VX_exu_to_cmt_if (); + + wire valid; + wire [`NW_BITS-1:0] wid; + wire [`NUM_THREADS-1:0] tmask; + wire [31:0] PC; + wire [`NUM_THREADS-1:0][31:0] data; + wire [`NR_BITS-1:0] rd; + wire wb; + wire ready; + +endinterface + +`endif \ No newline at end of file diff --git a/hw/rtl/interfaces/VX_fpu_req_if.v b/hw/rtl/interfaces/VX_fpu_req_if.v new file mode 100644 index 00000000..bb0ee172 --- /dev/null +++ b/hw/rtl/interfaces/VX_fpu_req_if.v @@ -0,0 +1,29 @@ +`ifndef VX_FPU_REQ_IF +`define VX_FPU_REQ_IF + +`include "VX_define.vh" + +`ifndef EXTF_F_ENABLE + `IGNORE_WARNINGS_BEGIN +`endif + +interface VX_fpu_req_if (); + + wire valid; + + wire [`NW_BITS-1:0] wid; + wire [`NUM_THREADS-1:0] tmask; + wire [31:0] PC; + wire [`FPU_BITS-1:0] op_type; + wire [`FRM_BITS-1:0] frm; + wire [`NUM_THREADS-1:0][31:0] rs1_data; + wire [`NUM_THREADS-1:0][31:0] rs2_data; + wire [`NUM_THREADS-1:0][31:0] rs3_data; + wire [`NR_BITS-1:0] rd; + wire wb; + + wire ready; + +endinterface + +`endif \ No newline at end of file diff --git a/hw/rtl/interfaces/VX_fpu_to_cmt_if.v b/hw/rtl/interfaces/VX_fpu_to_cmt_if.v new file mode 100644 index 00000000..066949d1 --- /dev/null +++ b/hw/rtl/interfaces/VX_fpu_to_cmt_if.v @@ -0,0 +1,21 @@ +`ifndef VX_FPU_TO_CMT_IF +`define VX_FPU_TO_CMT_IF + +`include "VX_define.vh" + +interface VX_fpu_to_cmt_if (); + + wire valid; + wire [`NW_BITS-1:0] wid; + wire [`NUM_THREADS-1:0] tmask; + wire [31:0] PC; + wire [`NUM_THREADS-1:0][31:0] data; + wire [`NR_BITS-1:0] rd; + wire wb; + wire has_fflags; + fflags_t [`NUM_THREADS-1:0] fflags; + wire ready; + +endinterface + +`endif \ No newline at end of file diff --git a/hw/rtl/interfaces/VX_fpu_to_csr_if.v b/hw/rtl/interfaces/VX_fpu_to_csr_if.v new file mode 100644 index 00000000..1dfae0ac --- /dev/null +++ b/hw/rtl/interfaces/VX_fpu_to_csr_if.v @@ -0,0 +1,24 @@ +`ifndef VX_FPU_TO_CSR_IF +`define VX_FPU_TO_CSR_IF + +`include "VX_define.vh" + +`ifndef EXTF_F_ENABLE + `IGNORE_WARNINGS_BEGIN +`endif + +interface VX_fpu_to_csr_if (); + + wire valid; + + wire [`NW_BITS-1:0] wid; + + wire fflags_NV; + wire fflags_DZ; + wire fflags_OF; + wire fflags_UF; + wire fflags_NX; + +endinterface + +`endif \ No newline at end of file diff --git a/hw/rtl/interfaces/VX_gpr_read_if.v b/hw/rtl/interfaces/VX_gpr_read_if.v deleted file mode 100644 index 5673c319..00000000 --- a/hw/rtl/interfaces/VX_gpr_read_if.v +++ /dev/null @@ -1,19 +0,0 @@ -`ifndef VX_GPR_READ_IF -`define VX_GPR_READ_IF - -`include "VX_define.vh" - -interface VX_gpr_read_if (); - - wire [4:0] rs1; - wire [4:0] rs2; - wire [`NW_BITS-1:0] warp_num; - wire is_jal; - wire[31:0] curr_PC; - - wire [`NUM_THREADS-1:0][31:0] a_reg_data; - wire [`NUM_THREADS-1:0][31:0] b_reg_data; - -endinterface - -`endif \ No newline at end of file diff --git a/hw/rtl/interfaces/VX_gpr_req_if.v b/hw/rtl/interfaces/VX_gpr_req_if.v new file mode 100644 index 00000000..2e2e6e98 --- /dev/null +++ b/hw/rtl/interfaces/VX_gpr_req_if.v @@ -0,0 +1,21 @@ +`ifndef VX_GPR_REQ_IF +`define VX_GPR_REQ_IF + +`include "VX_define.vh" + +interface VX_gpr_req_if (); + + wire valid; + + wire [`NW_BITS-1:0] wid; + wire [31:0] PC; + wire [`NR_BITS-1:0] rs1; + wire [`NR_BITS-1:0] rs2; + wire [`NR_BITS-1:0] rs3; + wire use_rs3; + + wire ready; + +endinterface + +`endif \ No newline at end of file diff --git a/hw/rtl/interfaces/VX_gpr_rsp_if.v b/hw/rtl/interfaces/VX_gpr_rsp_if.v new file mode 100644 index 00000000..4b953e06 --- /dev/null +++ b/hw/rtl/interfaces/VX_gpr_rsp_if.v @@ -0,0 +1,21 @@ +`ifndef VX_GPR_RSP_IF +`define VX_GPR_RSP_IF + +`include "VX_define.vh" + +interface VX_gpr_rsp_if (); + wire valid; +`IGNORE_WARNINGS_BEGIN + wire [`NW_BITS-1:0] wid; + wire [31:0] PC; +`IGNORE_WARNINGS_END + + wire [`NUM_THREADS-1:0][31:0] rs1_data; + wire [`NUM_THREADS-1:0][31:0] rs2_data; + wire [`NUM_THREADS-1:0][31:0] rs3_data; + + wire ready; + +endinterface + +`endif \ No newline at end of file diff --git a/hw/rtl/interfaces/VX_gpu_inst_req_if.v b/hw/rtl/interfaces/VX_gpu_inst_req_if.v deleted file mode 100644 index a39800b0..00000000 --- a/hw/rtl/interfaces/VX_gpu_inst_req_if.v +++ /dev/null @@ -1,23 +0,0 @@ -`ifndef VX_GPGPU_INST_REQ_IF -`define VX_GPGPU_INST_REQ_IF - -`include "VX_define.vh" - -interface VX_gpu_inst_req_if(); - - wire [`NUM_THREADS-1:0] valid; - wire [`NW_BITS-1:0] warp_num; - wire is_wspawn; - wire is_tmc; - wire is_split; - - wire is_barrier; - - wire[31:0] next_PC; - - wire [`NUM_THREADS-1:0][31:0] a_reg_data; - wire [31:0] rd2; - -endinterface - -`endif \ No newline at end of file diff --git a/hw/rtl/interfaces/VX_gpu_req_if.v b/hw/rtl/interfaces/VX_gpu_req_if.v new file mode 100644 index 00000000..5f024ae9 --- /dev/null +++ b/hw/rtl/interfaces/VX_gpu_req_if.v @@ -0,0 +1,24 @@ +`ifndef VX_GPU_REQ_IF +`define VX_GPU_REQ_IF + +`include "VX_define.vh" + +interface VX_gpu_req_if(); + + wire valid; + + wire [`NW_BITS-1:0] wid; + wire [`NUM_THREADS-1:0] tmask; + wire [31:0] PC; + wire [31:0] next_PC; + wire [`GPU_BITS-1:0] op_type; + wire [`NUM_THREADS-1:0][31:0] rs1_data; + wire [31:0] rs2_data; + wire [`NR_BITS-1:0] rd; + wire wb; + + wire ready; + +endinterface + +`endif \ No newline at end of file diff --git a/hw/rtl/interfaces/VX_ifetch_req_if.v b/hw/rtl/interfaces/VX_ifetch_req_if.v new file mode 100644 index 00000000..c4f34bcb --- /dev/null +++ b/hw/rtl/interfaces/VX_ifetch_req_if.v @@ -0,0 +1,16 @@ +`ifndef VX_IFETCH_REQ_IF +`define VX_IFETCH_REQ_IF + +`include "VX_define.vh" + +interface VX_ifetch_req_if (); + + wire valid; + wire [`NUM_THREADS-1:0] tmask; + wire [`NW_BITS-1:0] wid; + wire [31:0] PC; + wire ready; + +endinterface + +`endif \ No newline at end of file diff --git a/hw/rtl/interfaces/VX_ifetch_rsp_if.v b/hw/rtl/interfaces/VX_ifetch_rsp_if.v new file mode 100644 index 00000000..7a8c14fd --- /dev/null +++ b/hw/rtl/interfaces/VX_ifetch_rsp_if.v @@ -0,0 +1,17 @@ +`ifndef VX_IFETCH_RSP_IF +`define VX_IFETCH_RSP_IF + +`include "VX_define.vh" + +interface VX_ifetch_rsp_if (); + + wire valid; + wire [`NUM_THREADS-1:0] tmask; + wire [`NW_BITS-1:0] wid; + wire [31:0] PC; + wire [31:0] instr; + wire ready; + +endinterface + +`endif \ No newline at end of file diff --git a/hw/rtl/interfaces/VX_inst_meta_if.v b/hw/rtl/interfaces/VX_inst_meta_if.v deleted file mode 100644 index 8ebfa87f..00000000 --- a/hw/rtl/interfaces/VX_inst_meta_if.v +++ /dev/null @@ -1,15 +0,0 @@ -`ifndef VX_INST_META_IF -`define VX_INST_META_IF - -`include "VX_define.vh" - -interface VX_inst_meta_if (); - - wire [`NUM_THREADS-1:0] valid; - wire [31:0] curr_PC; - wire [`NW_BITS-1:0] warp_num; - wire [31:0] instruction; - -endinterface - -`endif \ No newline at end of file diff --git a/hw/rtl/interfaces/VX_jal_rsp_if.v b/hw/rtl/interfaces/VX_jal_rsp_if.v deleted file mode 100644 index 3f6796a0..00000000 --- a/hw/rtl/interfaces/VX_jal_rsp_if.v +++ /dev/null @@ -1,15 +0,0 @@ - -`ifndef VX_JAL_RSP_IF -`define VX_JAL_RSP_IF - -`include "VX_define.vh" - -interface VX_jal_rsp_if (); - - wire valid; - wire [31:0] dest; - wire [`NW_BITS-1:0] warp_num; - -endinterface - -`endif \ No newline at end of file diff --git a/hw/rtl/interfaces/VX_join_if.v b/hw/rtl/interfaces/VX_join_if.v index bc48bfee..0ee163ab 100644 --- a/hw/rtl/interfaces/VX_join_if.v +++ b/hw/rtl/interfaces/VX_join_if.v @@ -1,4 +1,3 @@ - `ifndef VX_JOIN_IF `define VX_JOIN_IF @@ -6,8 +5,8 @@ interface VX_join_if (); - wire is_join; - wire [`NW_BITS-1:0] warp_num; + wire valid; + wire [`NW_BITS-1:0] wid; endinterface diff --git a/hw/rtl/interfaces/VX_lsu_req_if.v b/hw/rtl/interfaces/VX_lsu_req_if.v index 216853cf..bff05720 100644 --- a/hw/rtl/interfaces/VX_lsu_req_if.v +++ b/hw/rtl/interfaces/VX_lsu_req_if.v @@ -1,4 +1,3 @@ - `ifndef VX_LSU_REQ_IF `define VX_LSU_REQ_IF @@ -6,16 +5,23 @@ interface VX_lsu_req_if (); - wire [`NUM_THREADS-1:0] valid; - wire [31:0] curr_PC; - wire [`NW_BITS-1:0] warp_num; + wire valid; + + wire [`NW_BITS-1:0] wid; + wire [`NUM_THREADS-1:0] tmask; + wire [31:0] PC; + + wire rw; + wire [`BYTEEN_BITS-1:0] byteen; + wire [`NUM_THREADS-1:0][31:0] store_data; - wire [`NUM_THREADS-1:0][31:0] base_addr; // A reg data - wire [31:0] offset; // itype_immed - wire [`BYTE_EN_BITS-1:0] mem_read; - wire [`BYTE_EN_BITS-1:0] mem_write; - wire [4:0] rd; // dest register - wire [1:0] wb; // + wire [`NUM_THREADS-1:0][31:0] base_addr; + wire [31:0] offset; + + wire [`NR_BITS-1:0] rd; + wire wb; + + wire ready; endinterface diff --git a/hw/rtl/interfaces/VX_mul_req_if.v b/hw/rtl/interfaces/VX_mul_req_if.v new file mode 100644 index 00000000..713761eb --- /dev/null +++ b/hw/rtl/interfaces/VX_mul_req_if.v @@ -0,0 +1,27 @@ +`ifndef VX_MUL_REQ_IF +`define VX_MUL_REQ_IF + +`include "VX_define.vh" + +`ifndef EXT_M_ENABLE + `IGNORE_WARNINGS_BEGIN +`endif + +interface VX_mul_req_if (); + + wire valid; + + wire [`NW_BITS-1:0] wid; + wire [`NUM_THREADS-1:0] tmask; + wire [31:0] PC; + wire [`MUL_BITS-1:0] op_type; + wire [`NUM_THREADS-1:0][31:0] rs1_data; + wire [`NUM_THREADS-1:0][31:0] rs2_data; + wire [`NR_BITS-1:0] rd; + wire wb; + + wire ready; + +endinterface + +`endif \ No newline at end of file diff --git a/hw/rtl/interfaces/VX_warp_ctl_if.v b/hw/rtl/interfaces/VX_warp_ctl_if.v index a8169d0c..c7eb8a4b 100644 --- a/hw/rtl/interfaces/VX_warp_ctl_if.v +++ b/hw/rtl/interfaces/VX_warp_ctl_if.v @@ -1,4 +1,3 @@ - `ifndef VX_WARP_CTL_IF `define VX_WARP_CTL_IF @@ -6,29 +5,13 @@ interface VX_warp_ctl_if (); - wire [`NW_BITS-1:0] warp_num; - wire change_mask; - wire [`NUM_THREADS-1:0] thread_mask; + wire valid; + wire [`NW_BITS-1:0] wid; - wire wspawn; - wire [31:0] wspawn_pc; - wire [`NUM_WARPS-1:0] wspawn_new_active; - - wire whalt; - - // barrier - wire is_barrier; - wire [31:0] barrier_id; - wire [$clog2(`NUM_WARPS):0] num_warps; - - wire is_split; - wire dont_split; -`IGNORE_WARNINGS_BEGIN - wire [`NW_BITS-1:0] split_warp_num; -`IGNORE_WARNINGS_END - wire [`NUM_THREADS-1:0] split_new_mask; - wire [`NUM_THREADS-1:0] split_later_mask; - wire [31:0] split_save_pc; + gpu_tmc_t tmc; + gpu_wspawn_t wspawn; + gpu_barrier_t barrier; + gpu_split_t split; endinterface diff --git a/hw/rtl/interfaces/VX_wb_if.v b/hw/rtl/interfaces/VX_wb_if.v deleted file mode 100644 index 96b8acef..00000000 --- a/hw/rtl/interfaces/VX_wb_if.v +++ /dev/null @@ -1,18 +0,0 @@ -`ifndef VX_WB_IF -`define VX_WB_IF - -`include "VX_define.vh" - -interface VX_wb_if (); - - wire [`NUM_THREADS-1:0] valid; - wire [`NUM_THREADS-1:0][31:0] data; - wire [`NW_BITS-1:0] warp_num; - wire [4:0] rd; - wire [1:0] wb; - wire [31:0] curr_PC; - wire is_io; - -endinterface - -`endif diff --git a/hw/rtl/interfaces/VX_writeback_if.v b/hw/rtl/interfaces/VX_writeback_if.v new file mode 100644 index 00000000..5cb412be --- /dev/null +++ b/hw/rtl/interfaces/VX_writeback_if.v @@ -0,0 +1,23 @@ +`ifndef VX_WRITEBACK_IF +`define VX_WRITEBACK_IF + +`include "VX_define.vh" + +interface VX_writeback_if (); + + wire valid; + wire [`NUM_THREADS-1:0] tmask; + wire [`NW_BITS-1:0] wid; + +`IGNORE_WARNINGS_BEGIN + wire [31:0] PC; +`IGNORE_WARNINGS_END + + wire [`NR_BITS-1:0] rd; + wire [`NUM_THREADS-1:0][31:0] data; + + wire ready; + +endinterface + +`endif diff --git a/hw/rtl/interfaces/VX_wstall_if.v b/hw/rtl/interfaces/VX_wstall_if.v index d2bef0d8..2e984085 100644 --- a/hw/rtl/interfaces/VX_wstall_if.v +++ b/hw/rtl/interfaces/VX_wstall_if.v @@ -5,8 +5,8 @@ interface VX_wstall_if(); - wire wstall; - wire [`NW_BITS-1:0] warp_num; + wire valid; + wire [`NW_BITS-1:0] wid; endinterface diff --git a/hw/rtl/libs/VX_bypass_buffer.v b/hw/rtl/libs/VX_bypass_buffer.v new file mode 100644 index 00000000..1a002d10 --- /dev/null +++ b/hw/rtl/libs/VX_bypass_buffer.v @@ -0,0 +1,47 @@ +`include "VX_platform.vh" + +module VX_bypass_buffer #( + parameter DATAW = 1, + parameter PASSTHRU = 0 +) ( + input wire clk, + input wire reset, + input wire valid_in, + output wire ready_in, + input wire [DATAW-1:0] data_in, + output wire [DATAW-1:0] data_out, + input wire ready_out, + output wire valid_out +); + if (PASSTHRU) begin + `UNUSED_VAR (clk) + `UNUSED_VAR (reset) + assign ready_in = ready_out; + assign valid_out = valid_in; + assign data_out = data_in; + end else begin + reg [DATAW-1:0] buffer; + reg buffer_valid; + + always @(posedge clk) begin + if (reset) begin + buffer_valid <= 0; + buffer <= 0; + end else begin + if (ready_out) begin + buffer_valid <= 0; + end + if (valid_in && ~ready_out) begin + assert(!buffer_valid); + buffer <= data_in; + buffer_valid <= 1; + end + end + end + + assign ready_in = ready_out || !buffer_valid; + assign data_out = buffer_valid ? buffer : data_in; + assign valid_out = valid_in || buffer_valid; + end + +endmodule \ No newline at end of file diff --git a/hw/rtl/libs/VX_cam_buffer.v b/hw/rtl/libs/VX_cam_buffer.v new file mode 100644 index 00000000..cb34af4c --- /dev/null +++ b/hw/rtl/libs/VX_cam_buffer.v @@ -0,0 +1,77 @@ +`include "VX_platform.vh" + +module VX_cam_buffer #( + parameter DATAW = 1, + parameter SIZE = 1, + parameter RPORTS = 1, + parameter CPORTS = 1, + parameter ADDRW = `LOG2UP(SIZE) +) ( + input wire clk, + input wire reset, + output wire [ADDRW-1:0] write_addr, + input wire [DATAW-1:0] write_data, + input wire acquire_slot, + input wire [RPORTS-1:0][ADDRW-1:0] read_addr, + output wire [RPORTS-1:0][DATAW-1:0] read_data, + input wire [CPORTS-1:0][ADDRW-1:0] release_addr, + input wire [CPORTS-1:0] release_slot, + output wire full +); + reg [DATAW-1:0] entries [SIZE-1:0]; + reg [SIZE-1:0] free_slots, free_slots_n; + reg [ADDRW-1:0] write_addr_r; + reg full_r; + + wire free_valid; + wire [ADDRW-1:0] free_index; + + VX_priority_encoder #( + .N(SIZE) + ) free_slots_encoder ( + .data_in (free_slots_n), + .data_out (free_index), + .valid_out (free_valid) + ); + + always @(*) begin + free_slots_n = free_slots; + for (integer i = 0; i < CPORTS; i++) begin + if (release_slot[i]) begin + free_slots_n[release_addr[i]] = 1; + end + end + if (acquire_slot) begin + free_slots_n[write_addr_r] = 0; + end + end + + always @(posedge clk) begin + if (reset) begin + free_slots <= {SIZE{1'b1}}; + full_r <= 1'b0; + write_addr_r <= ADDRW'(1'b0); + end else begin + if (acquire_slot) begin + assert(1 == free_slots[write_addr]) else $display("%t: inused slot at port %d", $time, write_addr); + entries[write_addr] <= write_data; + end + for (integer i = 0; i < CPORTS; i++) begin + if (release_slot[i]) begin + assert(0 == free_slots[release_addr[i]]) else $display("%t: freed slot at port %d", $time, release_addr[i]); + end + end + free_slots <= free_slots_n; + write_addr_r <= free_index; + full_r <= ~free_valid; + end + end + + for (genvar i = 0; i < RPORTS; i++) begin + assign read_data[i] = entries[read_addr[i]]; + end + + assign write_addr = write_addr_r; + assign full = full_r; + +endmodule \ No newline at end of file diff --git a/hw/rtl/libs/VX_countones.v b/hw/rtl/libs/VX_countones.v index 6d77b934..0d1f4129 100644 --- a/hw/rtl/libs/VX_countones.v +++ b/hw/rtl/libs/VX_countones.v @@ -1,18 +1,24 @@ -module VX_countones #( - parameter N = 10 -) ( - input wire[N-1:0] valids, - output reg[$clog2(N):0] count -); - integer i; +`include "VX_platform.vh" + +module VX_countones #( + parameter N = 10, + parameter N_BITS = $clog2(N+1) +) ( + input wire [N-1:0] valids, + output wire [N_BITS-1:0] count +); + reg [N_BITS-1:0] count_r; + always @(*) begin - count = 0; - for (i = N-1; i >= 0; i = i - 1) begin + count_r = 0; + for (integer i = N-1; i >= 0; i = i - 1) begin if (valids[i]) begin - count = count + 1; + count_r = count_r + N_BITS'(1); end end end + assign count = count_r; + endmodule \ No newline at end of file diff --git a/hw/rtl/libs/VX_divide.v b/hw/rtl/libs/VX_divide.v index 510abf26..f960ba52 100644 --- a/hw/rtl/libs/VX_divide.v +++ b/hw/rtl/libs/VX_divide.v @@ -1,42 +1,47 @@ -`include "VX_define.vh" +`include "VX_platform.vh" module VX_divide #( - parameter WIDTHN = 1, - parameter WIDTHD = 1, + parameter WIDTHN = 1, + parameter WIDTHD = 1, + parameter WIDTHQ = 1, + parameter WIDTHR = 1, parameter NSIGNED = 0, parameter DSIGNED = 0, - parameter PIPELINE = 0 + parameter LATENCY = 0 ) ( input wire clk, - input wire reset, - + input wire enable, input wire [WIDTHN-1:0] numer, input wire [WIDTHD-1:0] denom, - - output wire [WIDTHN-1:0] quotient, - output wire [WIDTHD-1:0] remainder + output wire [WIDTHQ-1:0] quotient, + output wire [WIDTHR-1:0] remainder ); `ifdef QUARTUS - lpm_divide quartus_div ( + wire [WIDTHN-1:0] quotient_unqual; + wire [WIDTHD-1:0] remainder_unqual; + + lpm_divide divide ( .clock (clk), + .clken (enable), .numer (numer), .denom (denom), - .quotient (quotient), - .remain (remainder), - .aclr (1'b0), - .clken (1'b1) + .quotient (quotient_unqual), + .remain (remainder_unqual) ); defparam - quartus_div.lpm_type = "LPM_DIVIDE", - quartus_div.lpm_widthn = WIDTHN, - quartus_div.lpm_widthd = WIDTHD, - quartus_div.lpm_nrepresentation = NSIGNED ? "SIGNED" : "UNSIGNED", - quartus_div.lpm_drepresentation = DSIGNED ? "SIGNED" : "UNSIGNED", - quartus_div.lpm_hint = "MAXIMIZE_SPEED=6,LPM_REMAINDERPOSITIVE=FALSE", - quartus_div.lpm_pipeline = PIPELINE; + divide.lpm_type = "LPM_DIVIDE", + divide.lpm_widthn = WIDTHN, + divide.lpm_widthd = WIDTHD, + divide.lpm_nrepresentation = NSIGNED ? "SIGNED" : "UNSIGNED", + divide.lpm_drepresentation = DSIGNED ? "SIGNED" : "UNSIGNED", + divide.lpm_hint = "MAXIMIZE_SPEED=6,LPM_REMAINDERPOSITIVE=FALSE", + divide.lpm_pipeline = LATENCY; + + assign quotient = quotient_unqual [WIDTHQ-1:0]; + assign remainder = remainder_unqual [WIDTHR-1:0]; `else @@ -44,15 +49,6 @@ module VX_divide #( reg [WIDTHD-1:0] remainder_unqual; always @(*) begin - `ifndef SYNTHESIS - // this edge case kills verilator in some cases by causing a division - // overflow exception. INT_MIN / -1 (on x86) - if (numer == {1'b1, (WIDTHN-1)'(0)} - && denom == {WIDTHD{1'b1}}) begin - quotient_unqual = 0; - remainder_unqual = 0; - end else - `endif begin if (NSIGNED && DSIGNED) begin quotient_unqual = $signed(numer) / $signed(denom); @@ -73,34 +69,24 @@ module VX_divide #( end end - if (PIPELINE == 0) begin - assign quotient = quotient_unqual; - assign remainder = remainder_unqual; + if (LATENCY == 0) begin + assign quotient = quotient_unqual [WIDTHQ-1:0]; + assign remainder = remainder_unqual [WIDTHR-1:0]; end else begin - reg [WIDTHN-1:0] quotient_pipe [0:PIPELINE-1]; - reg [WIDTHD-1:0] remainder_pipe [0:PIPELINE-1]; + reg [WIDTHN-1:0] quotient_pipe [0:LATENCY-1]; + reg [WIDTHD-1:0] remainder_pipe [0:LATENCY-1]; - genvar i; - for (i = 0; i < PIPELINE; i++) begin - always @(posedge clk) begin - if (reset) begin - quotient_pipe[i] <= 0; - remainder_pipe[i] <= 0; - end - else begin - if (i == 0) begin - quotient_pipe[0] <= quotient_unqual; - remainder_pipe[0] <= remainder_unqual; - end else begin - quotient_pipe[i] <= quotient_pipe[i-1]; - remainder_pipe[i] <= remainder_pipe[i-1]; - end + for (genvar i = 0; i < LATENCY; i++) begin + always @(posedge clk) begin + if (enable) begin + quotient_pipe[i] <= (0 == i) ? quotient_unqual : quotient_pipe[i-1]; + remainder_pipe[i] <= (0 == i) ? remainder_unqual : remainder_pipe[i-1]; end end end - assign quotient = quotient_pipe[PIPELINE-1]; - assign remainder = remainder_pipe[PIPELINE-1]; + assign quotient = quotient_pipe[LATENCY-1][WIDTHQ-1:0]; + assign remainder = remainder_pipe[LATENCY-1][WIDTHR-1:0]; end `endif diff --git a/hw/rtl/libs/VX_elastic_buffer.v b/hw/rtl/libs/VX_elastic_buffer.v new file mode 100644 index 00000000..a62b4122 --- /dev/null +++ b/hw/rtl/libs/VX_elastic_buffer.v @@ -0,0 +1,38 @@ +`include "VX_platform.vh" + +module VX_elastic_buffer #( + parameter DATAW = 1, + parameter SIZE = 2, + parameter BUFFERED = 0 +) ( + input wire clk, + input wire reset, + input wire valid_in, + output wire ready_in, + input wire [DATAW-1:0] data_in, + output wire [DATAW-1:0] data_out, + input wire ready_out, + output wire valid_out +); + wire empty, full; + + VX_generic_queue #( + .DATAW (DATAW), + .SIZE (SIZE), + .BUFFERED (BUFFERED) + ) queue ( + .clk (clk), + .reset (reset), + .push (valid_in), + .pop (ready_out), + .data_in(data_in), + .data_out(data_out), + .empty (empty), + .full (full), + `UNUSED_PIN (size) + ); + + assign ready_in = ~full; + assign valid_out = ~empty; + +endmodule \ No newline at end of file diff --git a/hw/rtl/libs/VX_encoder_onehot.v b/hw/rtl/libs/VX_encoder_onehot.v deleted file mode 100644 index a4e0e72e..00000000 --- a/hw/rtl/libs/VX_encoder_onehot.v +++ /dev/null @@ -1,24 +0,0 @@ -`include "VX_define.vh" - -module VX_encoder_onehot #( - parameter N = 6 -) ( - input wire [N-1:0] onehot, - output reg [`LOG2UP(N)-1:0] binary, - output reg valid -); - integer i; - - always @(*) begin - valid = 1'b0; - binary = `LOG2UP(N)'(0); - for (i = 0; i < N; i++) begin - if (onehot[i]) begin - valid = 1'b1; - binary = `LOG2UP(N)'(i); - end - end - end - -endmodule - diff --git a/hw/rtl/libs/VX_fair_arbiter.v b/hw/rtl/libs/VX_fair_arbiter.v index 9ffc1ecd..8f9cbbff 100644 --- a/hw/rtl/libs/VX_fair_arbiter.v +++ b/hw/rtl/libs/VX_fair_arbiter.v @@ -1,4 +1,4 @@ -`include "VX_define.vh" +`include "VX_platform.vh" module VX_fair_arbiter #( parameter N = 1 @@ -11,7 +11,7 @@ module VX_fair_arbiter #( output wire grant_valid ); - if (N == 1) begin + if (N == 1) begin `UNUSED_VAR (clk) `UNUSED_VAR (reset) @@ -33,11 +33,13 @@ module VX_fair_arbiter #( if (reset) begin requests_use <= 0; refill_original <= 0; - end else if (refill) begin - requests_use <= refill_value; - refill_original <= refill_value; end else begin - requests_use <= update_value; + if (refill) begin + requests_use <= refill_value; + refill_original <= refill_value; + end else begin + requests_use <= update_value; + end end end diff --git a/hw/rtl/libs/VX_fixed_arbiter.v b/hw/rtl/libs/VX_fixed_arbiter.v index 7f6fbfa3..3bcab5bf 100644 --- a/hw/rtl/libs/VX_fixed_arbiter.v +++ b/hw/rtl/libs/VX_fixed_arbiter.v @@ -1,4 +1,4 @@ -`include "VX_define.vh" +`include "VX_platform.vh" module VX_fixed_arbiter #( parameter N = 1 diff --git a/hw/rtl/libs/VX_generic_queue.v b/hw/rtl/libs/VX_generic_queue.v index e1919eca..4164fdad 100644 --- a/hw/rtl/libs/VX_generic_queue.v +++ b/hw/rtl/libs/VX_generic_queue.v @@ -1,9 +1,11 @@ -`include "VX_define.vh" +`include "VX_platform.vh" module VX_generic_queue #( - parameter DATAW = 0, - parameter SIZE = 1, - parameter BUFFERED_OUTPUT = 1 + parameter DATAW = 1, + parameter SIZE = 2, + parameter BUFFERED = 0, + parameter ADDRW = $clog2(SIZE), + parameter SIZEW = $clog2(SIZE+1) ) ( input wire clk, input wire reset, @@ -13,13 +15,13 @@ module VX_generic_queue #( output wire [DATAW-1:0] data_out, output wire empty, output wire full, - output wire [`LOG2UP(SIZE+1)-1:0] size + output wire [SIZEW-1:0] size ); `STATIC_ASSERT(`ISPOW2(SIZE), "must be 0 or power of 2!") - reg [`LOG2UP(SIZE+1)-1:0] size_r; - wire reading; - wire writing; + reg [SIZEW-1:0] size_r; + wire reading; + wire writing; assign reading = pop && !empty; assign writing = push && !full; @@ -38,7 +40,6 @@ module VX_generic_queue #( end else if (reading && !writing) begin size_r <= 0; end - if (writing) begin head_r <= data_in; end @@ -52,19 +53,15 @@ module VX_generic_queue #( end else begin // (SIZE > 1) - `ifdef QUEUE_FORCE_MLAB - (* syn_ramstyle = "mlab" *) reg [DATAW-1:0] data [SIZE-1:0]; - `else - reg [DATAW-1:0] data [SIZE-1:0]; - `endif + `USE_FAST_BRAM reg [DATAW-1:0] data [SIZE-1:0]; - if (0 == BUFFERED_OUTPUT) begin + if (0 == BUFFERED) begin - reg [`LOG2UP(SIZE):0] rd_ptr_r; - reg [`LOG2UP(SIZE):0] wr_ptr_r; + reg [ADDRW:0] rd_ptr_r; + reg [ADDRW:0] wr_ptr_r; - wire [`LOG2UP(SIZE)-1:0] rd_ptr_a = rd_ptr_r[`LOG2UP(SIZE)-1:0]; - wire [`LOG2UP(SIZE)-1:0] wr_ptr_a = wr_ptr_r[`LOG2UP(SIZE)-1:0]; + wire [ADDRW-1:0] rd_ptr_a = rd_ptr_r[ADDRW-1:0]; + wire [ADDRW-1:0] wr_ptr_a = wr_ptr_r[ADDRW-1:0]; always @(posedge clk) begin if (reset) begin @@ -75,7 +72,6 @@ module VX_generic_queue #( if (writing) begin data[wr_ptr_a] <= data_in; wr_ptr_r <= wr_ptr_r + 1; - if (!reading) begin size_r <= size_r + 1; end @@ -92,19 +88,19 @@ module VX_generic_queue #( assign data_out = data[rd_ptr_a]; assign empty = (wr_ptr_r == rd_ptr_r); - assign full = (wr_ptr_a == rd_ptr_a) && (wr_ptr_r[`LOG2UP(SIZE)] != rd_ptr_r[`LOG2UP(SIZE)]); + assign full = (wr_ptr_a == rd_ptr_a) && (wr_ptr_r[ADDRW] != rd_ptr_r[ADDRW]); assign size = size_r; end else begin - reg [DATAW-1:0] head_r; - reg [DATAW-1:0] curr_r; - reg [`LOG2UP(SIZE)-1:0] wr_ptr_r; - reg [`LOG2UP(SIZE)-1:0] rd_ptr_r; - reg [`LOG2UP(SIZE)-1:0] rd_ptr_next_r; - reg empty_r; - reg full_r; - reg bypass_r; + reg [DATAW-1:0] head_r; + reg [DATAW-1:0] curr_r; + reg [ADDRW-1:0] wr_ptr_r; + reg [ADDRW-1:0] rd_ptr_r; + reg [ADDRW-1:0] rd_ptr_next_r; + reg empty_r; + reg full_r; + reg bypass_r; always @(posedge clk) begin if (reset) begin @@ -150,7 +146,7 @@ module VX_generic_queue #( end bypass_r <= writing - && (empty_r || ((1 == size_r) && reading)); // empty or about to go empty + && (empty_r || ((1 == size_r) && reading)); // empty or about to go empty curr_r <= data_in; head_r <= data[reading ? rd_ptr_next_r : rd_ptr_r]; diff --git a/hw/rtl/libs/VX_generic_register.v b/hw/rtl/libs/VX_generic_register.v index 7234b0a2..637f4f43 100644 --- a/hw/rtl/libs/VX_generic_register.v +++ b/hw/rtl/libs/VX_generic_register.v @@ -1,4 +1,4 @@ -`include "VX_define.vh" +`include "VX_platform.vh" module VX_generic_register #( parameter N = 1, @@ -11,18 +11,23 @@ module VX_generic_register #( input wire[N-1:0] in, output wire[N-1:0] out ); - reg [(N-1):0] value; + if (PASSTHRU) begin + `UNUSED_VAR (clk) + `UNUSED_VAR (reset) + `UNUSED_VAR (stall) + assign out = flush ? N'(0) : in; + end else begin + reg [(N-1):0] value; - always @(posedge clk) begin - if (reset) begin - value <= 0; - end else if (flush) begin - value <= 0; - end else if (~stall) begin - value <= in; + always @(posedge clk) begin + if (reset || flush) begin + value <= N'(0); + end else if (~stall) begin + value <= in; + end end - end - assign out = PASSTHRU ? in : value; + assign out = value; + end endmodule \ No newline at end of file diff --git a/hw/rtl/libs/VX_generic_stack.v b/hw/rtl/libs/VX_generic_stack.v deleted file mode 100644 index fdebbacf..00000000 --- a/hw/rtl/libs/VX_generic_stack.v +++ /dev/null @@ -1,32 +0,0 @@ - -module VX_generic_stack #( - parameter WIDTH = 40, - parameter DEPTH = 2 -) ( - input wire clk, - input wire reset, - input wire push, - input wire pop, - input reg [WIDTH - 1:0] q1, - input reg [WIDTH - 1:0] q2, - output wire[WIDTH - 1:0] d -); - - reg [DEPTH - 1:0] ptr; - reg [WIDTH - 1:0] stack [0:(1 << DEPTH) - 1]; - - always @(posedge clk) begin - if (reset) begin - ptr <= 0; - end else if (push) begin - stack[ptr] <= q1; - stack[ptr+1] <= q2; - ptr <= ptr + 2; - end else if (pop) begin - ptr <= ptr - 1; - end - end - - assign d = stack[ptr - 1]; - -endmodule \ No newline at end of file diff --git a/hw/rtl/libs/VX_indexable_queue.v b/hw/rtl/libs/VX_index_queue.v similarity index 88% rename from hw/rtl/libs/VX_indexable_queue.v rename to hw/rtl/libs/VX_index_queue.v index 886b05f6..bee8ccb9 100644 --- a/hw/rtl/libs/VX_indexable_queue.v +++ b/hw/rtl/libs/VX_index_queue.v @@ -1,6 +1,6 @@ -`include "VX_define.vh" +`include "VX_platform.vh" -module VX_indexable_queue #( +module VX_index_queue #( parameter DATAW = 1, parameter SIZE = 1 ) ( @@ -15,7 +15,7 @@ module VX_indexable_queue #( input wire [`LOG2UP(SIZE)-1:0] read_addr, output wire [DATAW-1:0] read_data ); - reg [DATAW-1:0] data [SIZE-1:0]; + reg [DATAW-1:0] entries [SIZE-1:0]; reg [SIZE-1:0] valid; reg [`LOG2UP(SIZE):0] rd_ptr, wr_ptr; @@ -38,7 +38,7 @@ module VX_indexable_queue #( valid <= 0; end else begin if (enqueue) begin - data[wr_a] <= write_data; + entries[wr_a] <= write_data; valid[wr_a] <= 1; wr_ptr <= wr_ptr + 1; end @@ -52,6 +52,6 @@ module VX_indexable_queue #( end assign write_addr = wr_a; - assign read_data = data[read_addr]; + assign read_data = entries[read_addr]; endmodule \ No newline at end of file diff --git a/hw/rtl/libs/VX_matrix_arbiter.v b/hw/rtl/libs/VX_matrix_arbiter.v index 8c467974..7ccda7dc 100644 --- a/hw/rtl/libs/VX_matrix_arbiter.v +++ b/hw/rtl/libs/VX_matrix_arbiter.v @@ -1,4 +1,4 @@ -`include "VX_define.vh" +`include "VX_platform.vh" module VX_matrix_arbiter #( parameter N = 1 @@ -24,11 +24,9 @@ module VX_matrix_arbiter #( reg [N-1:1] state [0:N-1]; wire [N-1:0] pri [0:N-1]; - - genvar i, j; - - for (i = 0; i < N; i++) begin - for (j = 0; j < N; j++) begin + + for (genvar i = 0; i < N; i++) begin + for (genvar j = 0; j < N; j++) begin if (j > i) begin assign pri[j][i] = requests[i] && state[i][j]; end @@ -43,20 +41,19 @@ module VX_matrix_arbiter #( assign grant_onehot[i] = requests[i] && !(| pri[i]); end - for (i = 0; i < N; i++) begin - for (j = i + 1; j < N; j++) begin + for (genvar i = 0; i < N; i++) begin + for (genvar j = i + 1; j < N; j++) begin always @(posedge clk) begin if (reset) begin state[i][j] <= 0; - end - else begin + end else begin state[i][j] <= (state[i][j] || grant_onehot[j]) && !grant_onehot[i]; end end end end - VX_encoder_onehot #( + VX_onehot_encoder #( .N(N) ) encoder ( .onehot (grant_onehot), diff --git a/hw/rtl/libs/VX_mult.v b/hw/rtl/libs/VX_mult.v deleted file mode 100644 index 1dd77aea..00000000 --- a/hw/rtl/libs/VX_mult.v +++ /dev/null @@ -1,75 +0,0 @@ -`include "VX_define.vh" - -module VX_mult #( - parameter WIDTHA = 1, - parameter WIDTHB = 1, - parameter WIDTHP = 1, - parameter SIGNED = 0, - parameter PIPELINE = 0 -) ( - input wire clk, - input wire reset, - - input wire [WIDTHA-1:0] dataa, - input wire [WIDTHB-1:0] datab, - output wire [WIDTHP-1:0] result -); - -`ifdef QUARTUS - - lpm_mult quartus_mult ( - .clock (clk), - .dataa (dataa), - .datab (datab), - .result (result), - .sclr (reset), - .aclr (1'b0), - .clken (1'b1), - .sum (1'b0) - ); - - defparam quartus_mult.lpm_type = "LPM_MULT", - quartus_mult.lpm_widtha = WIDTHA, - quartus_mult.lpm_widthb = WIDTHB, - quartus_mult.lpm_widthp = WIDTHP, - quartus_mult.lpm_representation = SIGNED ? "SIGNED" : "UNSIGNED", - quartus_mult.lpm_pipeline = PIPELINE, - quartus_mult.lpm_hint = "DEDICATED_MULTIPLIER_CIRCUITRY=YES,MAXIMIZE_SPEED=9"; -`else - - wire [WIDTHP-1:0] result_unqual; - - if (SIGNED) begin - assign result_unqual = $signed(dataa) * $signed(datab); - end else begin - assign result_unqual = dataa * datab; - end - - if (PIPELINE == 0) begin - assign result = result_unqual; - end else begin - - reg [WIDTHP-1:0] result_pipe [0:PIPELINE-1]; - - genvar i; - for (i = 0; i < PIPELINE; i++) begin - always @(posedge clk) begin - if (reset) begin - result_pipe[i] <= 0; - end - else begin - if (i == 0) begin - result_pipe[0] <= result_unqual; - end else begin - result_pipe[i] <= result_pipe[i-1]; - end - end - end - end - - assign result = result_pipe[PIPELINE-1]; - end - -`endif - -endmodule \ No newline at end of file diff --git a/hw/rtl/libs/VX_multiplier.v b/hw/rtl/libs/VX_multiplier.v new file mode 100644 index 00000000..ed7c5946 --- /dev/null +++ b/hw/rtl/libs/VX_multiplier.v @@ -0,0 +1,65 @@ +`include "VX_platform.vh" + +module VX_multiplier #( + parameter WIDTHA = 1, + parameter WIDTHB = 1, + parameter WIDTHP = 1, + parameter SIGNED = 0, + parameter LATENCY = 0 +) ( + input wire clk, + input wire enable, + input wire [WIDTHA-1:0] dataa, + input wire [WIDTHB-1:0] datab, + output wire [WIDTHP-1:0] result +); + +`ifdef QUARTUS + + lpm_mult mult ( + .clock (clk), + .clken (enable), + .dataa (dataa), + .datab (datab), + .result (result), + .aclr (1'b0), + .sclr (1'b0), + .sum (1'b0) + ); + + defparam mult.lpm_type = "LPM_MULT", + mult.lpm_widtha = WIDTHA, + mult.lpm_widthb = WIDTHB, + mult.lpm_widthp = WIDTHP, + mult.lpm_representation = SIGNED ? "SIGNED" : "UNSIGNED", + mult.lpm_pipeline = LATENCY, + mult.lpm_hint = "DEDICATED_MULTIPLIER_CIRCUITRY=YES,MAXIMIZE_SPEED=9"; +`else + + wire [WIDTHP-1:0] result_unqual; + + if (SIGNED) begin + assign result_unqual = $signed(dataa) * $signed(datab); + end else begin + assign result_unqual = dataa * datab; + end + + if (LATENCY == 0) begin + assign result = result_unqual; + end else begin + reg [WIDTHP-1:0] result_pipe [0:LATENCY-1]; + + for (genvar i = 0; i < LATENCY; i++) begin + always @(posedge clk) begin + if (enable) begin + result_pipe[i] <= (0 == i) ? result_unqual : result_pipe[i-1]; + end + end + end + + assign result = result_pipe[LATENCY-1]; + end + +`endif + +endmodule \ No newline at end of file diff --git a/hw/rtl/libs/VX_onehot_encooder.v b/hw/rtl/libs/VX_onehot_encooder.v new file mode 100644 index 00000000..6b5881bc --- /dev/null +++ b/hw/rtl/libs/VX_onehot_encooder.v @@ -0,0 +1,28 @@ +`include "VX_platform.vh" + +module VX_onehot_encoder #( + parameter N = 6 +) ( + input wire [N-1:0] onehot, + output wire [`LOG2UP(N)-1:0] binary, + output wire valid +); + reg [`LOG2UP(N)-1:0] binary_r; + reg valid_r; + + always @(*) begin + binary_r = `LOG2UP(N)'(0); + valid_r = 1'b0; + for (integer i = 0; i < N; i++) begin + if (onehot[i]) begin + binary_r = `LOG2UP(N)'(i); + valid_r = 1'b1; + end + end + end + + assign binary = binary_r; + assign valid = valid_r; + +endmodule + diff --git a/hw/rtl/libs/VX_priority_encoder.v b/hw/rtl/libs/VX_priority_encoder.v index 24c91724..6d8361ae 100644 --- a/hw/rtl/libs/VX_priority_encoder.v +++ b/hw/rtl/libs/VX_priority_encoder.v @@ -1,22 +1,28 @@ -`include "VX_define.vh" +`include "VX_platform.vh" module VX_priority_encoder #( parameter N = 1 ) ( - input wire [N-1:0] data_in, - output reg [`LOG2UP(N)-1:0] data_out, - output reg valid_out -); - integer i; + input wire [N-1:0] data_in, + output wire [`LOG2UP(N)-1:0] data_out, + output wire valid_out +); + reg [`LOG2UP(N)-1:0] data_out_r; + reg valid_out_r; + always @(*) begin - data_out = 0; - valid_out = 0; - for (i = N-1; i >= 0; i = i - 1) begin + data_out_r = 0; + valid_out_r = 0; + for (integer i = 0; i < N; i++) begin if (data_in[i]) begin - data_out = `LOG2UP(N)'(i); - valid_out = 1; + data_out_r = `LOG2UP(N)'(i); + valid_out_r = 1; + break; end end end + + assign data_out = data_out_r; + assign valid_out = valid_out_r; endmodule \ No newline at end of file diff --git a/hw/rtl/libs/VX_rr_arbiter.v b/hw/rtl/libs/VX_rr_arbiter.v index fb19e108..c876590e 100644 --- a/hw/rtl/libs/VX_rr_arbiter.v +++ b/hw/rtl/libs/VX_rr_arbiter.v @@ -1,4 +1,4 @@ -`include "VX_define.vh" +`include "VX_platform.vh" module VX_rr_arbiter #( parameter N = 1 @@ -26,27 +26,24 @@ module VX_rr_arbiter #( reg [`CLOG2(N)-1:0] state; reg [N-1:0] grant_onehot_r; - integer i, j; - always @(*) begin - for (i = 0; i < N; i++) begin + for (integer i = 0; i < N; i++) begin grant_table[i] = `CLOG2(N)'(i); - for (j = 0; j < N; j++) begin + for (integer j = 0; j < N; j++) begin if (requests[(i+j) % N]) begin grant_table[i] = `CLOG2(N)'((i+j) % N); end end end grant_onehot_r = N'(0); - grant_onehot_r[grant_index] = 1; + grant_onehot_r[grant_table[state]] = 1; end always @(posedge clk) begin if (reset) begin state <= 0; - end - else begin - state <= grant_index; + end else begin + state <= grant_table[state]; end end diff --git a/hw/rtl/libs/VX_scope.v b/hw/rtl/libs/VX_scope.v index 7ec7b5f3..2b924776 100644 --- a/hw/rtl/libs/VX_scope.v +++ b/hw/rtl/libs/VX_scope.v @@ -1,4 +1,4 @@ -`include "VX_define.vh" +`include "VX_platform.vh" module VX_scope #( parameter DATAW = 64, @@ -14,7 +14,7 @@ module VX_scope #( input wire changed, input wire [DATAW-1:0] data_in, input wire [BUSW-1:0] bus_in, - output reg [BUSW-1:0] bus_out, + output wire [BUSW-1:0] bus_out, input wire bus_write, input wire bus_read ); @@ -39,6 +39,7 @@ module VX_scope #( reg [DELTAW-1:0] delta_store [SIZE-1:0]; reg [UPDW-1:0] prev_trigger_id; reg [DELTAW-1:0] delta; + reg [BUSW-1:0] bus_out_r; reg [`CLOG2(SIZE)-1:0] raddr, waddr, waddr_end; @@ -74,7 +75,6 @@ module VX_scope #( read_delta <= 0; data_valid <= 0; end else begin - if (bus_write) begin case (cmd_type) CMD_GET_VALID, @@ -169,14 +169,16 @@ module VX_scope #( always @(*) begin case (out_cmd) - GET_VALID : bus_out = BUSW'(data_valid); - GET_WIDTH : bus_out = BUSW'(DATAW); - GET_COUNT : bus_out = BUSW'(waddr) + BUSW'(1); - GET_DATA : bus_out = read_delta ? BUSW'(delta_store[raddr]) : BUSW'(data_store[raddr] >> read_offset); - default : bus_out = 0; + GET_VALID : bus_out_r = BUSW'(data_valid); + GET_WIDTH : bus_out_r = BUSW'(DATAW); + GET_COUNT : bus_out_r = BUSW'(waddr) + BUSW'(1); + GET_DATA : bus_out_r = read_delta ? BUSW'(delta_store[raddr]) : BUSW'(data_store[raddr] >> read_offset); + default : bus_out_r = 0; endcase end + assign bus_out = bus_out_r; + `ifdef DBG_PRINT_SCOPE always @(posedge clk) begin if (bus_read) begin diff --git a/hw/rtl/libs/VX_serial_div.v b/hw/rtl/libs/VX_serial_div.v new file mode 100644 index 00000000..f3a5d09f --- /dev/null +++ b/hw/rtl/libs/VX_serial_div.v @@ -0,0 +1,100 @@ +`include "VX_platform.vh" + +module VX_serial_div #( + parameter WIDTHN = 1, + parameter WIDTHD = 1, + parameter WIDTHQ = 1, + parameter WIDTHR = 1, + parameter LANES = 1, + parameter TAGW = 1 +) ( + input wire clk, + input wire reset, + + input wire valid_in, + output wire ready_in, + input wire [LANES-1:0][WIDTHN-1:0] numer, + input wire [LANES-1:0][WIDTHD-1:0] denom, + input wire signed_mode, + input wire [TAGW-1:0] tag_in, + + output wire [LANES-1:0][WIDTHQ-1:0] quotient, + output wire [LANES-1:0][WIDTHR-1:0] remainder, + input wire ready_out, + output wire valid_out, + output wire [TAGW-1:0] tag_out +); + localparam MIN_ND = (WIDTHN < WIDTHD) ? WIDTHN : WIDTHD; + localparam CNTRW = $clog2(WIDTHN+1); + + reg [LANES-1:0][WIDTHN + MIN_ND:0] working; + reg [LANES-1:0][WIDTHD-1:0] denom_r; + + wire [LANES-1:0][WIDTHN-1:0] numer_qual; + wire [LANES-1:0][WIDTHD-1:0] denom_qual; + wire [LANES-1:0][WIDTHD:0] sub_result; + + reg [LANES-1:0] inv_quot, inv_rem; + + reg [CNTRW-1:0] cntr; + reg is_busy; + + reg [TAGW-1:0] tag_r; + + wire done = ~(| cntr); + + wire push = valid_in && ready_in; + wire pop = valid_out && ready_out; + + for (genvar i = 0; i < LANES; ++i) begin + wire negate_numer = signed_mode && numer[i][WIDTHN-1]; + wire negate_denom = signed_mode && denom[i][WIDTHD-1]; + assign numer_qual[i] = negate_numer ? -$signed(numer[i]) : numer[i]; + assign denom_qual[i] = negate_denom ? -$signed(denom[i]) : denom[i]; + assign sub_result[i] = working[i][WIDTHN + MIN_ND : WIDTHN] - denom_r[i]; + end + + always @(posedge clk) begin + if (reset) begin + cntr <= 0; + is_busy <= 0; + end + else begin + if (push) begin + for (integer i = 0; i < LANES; ++i) begin + working[i] <= {{WIDTHD{1'b0}}, numer_qual[i], 1'b0}; + denom_r[i] <= denom_qual[i]; + inv_quot[i] <= (denom[i] != 0) && signed_mode && (numer[i][31] ^ denom[i][31]); + inv_rem[i] <= signed_mode && numer[i][31]; + end + tag_r <= tag_in; + cntr <= WIDTHN; + is_busy <= 1; + end + else begin + if (!done) begin + for (integer i = 0; i < LANES; ++i) begin + working[i] <= sub_result[i][WIDTHD] ? {working[i][WIDTHN+MIN_ND-1:0], 1'b0} : + {sub_result[i][WIDTHD-1:0], working[i][WIDTHN-1:0], 1'b1}; + end + cntr <= cntr - CNTRW'(1); + end + end + if (pop) begin + is_busy <= 0; + end + end + end + + for (genvar i = 0; i < LANES; ++i) begin + wire [WIDTHQ-1:0] q = working[i][WIDTHQ-1:0]; + wire [WIDTHR-1:0] r = working[i][WIDTHN+WIDTHR:WIDTHN+1]; + assign quotient[i] = inv_quot[i] ? -$signed(q) : q; + assign remainder[i] = inv_rem[i] ? -$signed(r) : r; + end + + assign ready_in = !is_busy; + assign tag_out = tag_r; + assign valid_out = is_busy && done; + +endmodule \ No newline at end of file diff --git a/hw/rtl/libs/VX_shift_register.v b/hw/rtl/libs/VX_shift_register.v new file mode 100644 index 00000000..a82a4607 --- /dev/null +++ b/hw/rtl/libs/VX_shift_register.v @@ -0,0 +1,42 @@ +`include "VX_platform.vh" + +module VX_shift_register #( + parameter DATAW = 1, + parameter DEPTH = 1 +) ( + input wire clk, + input wire reset, + input wire enable, + input wire [DATAW-1:0] in, + output wire [DATAW-1:0] out +); + reg [DEPTH-1:0][DATAW-1:0] entries; + + if (1 == DEPTH) begin + + always @(posedge clk) begin + if (reset) begin + entries <= (DEPTH * DATAW)'(0); + end else begin + if (enable) begin + entries <= in; + end + end + end + + end else begin + + always @(posedge clk) begin + if (reset) begin + entries <= (DEPTH * DATAW)'(0); + end else begin + if (enable) begin + entries <= {entries[DEPTH-2:0], in}; + end + end + end + end + + assign out = entries [DEPTH-1]; + +endmodule \ No newline at end of file diff --git a/hw/rtl/libs/VX_skid_buffer.v b/hw/rtl/libs/VX_skid_buffer.v new file mode 100644 index 00000000..d179ed31 --- /dev/null +++ b/hw/rtl/libs/VX_skid_buffer.v @@ -0,0 +1,48 @@ +`include "VX_platform.vh" + +module VX_skid_buffer #( + parameter DATAW = 1 +) ( + input wire clk, + input wire reset, + input wire valid_in, + output wire ready_in, + input wire [DATAW-1:0] data_in, + output wire [DATAW-1:0] data_out, + input wire ready_out, + output wire valid_out +); + reg [DATAW-1:0] data_out_r; + reg [DATAW-1:0] buffer; + reg valid_out_r; + reg use_buffer; + + always @(posedge clk) begin + if (reset) begin + data_out_r <= 0; + buffer <= 0; + use_buffer <= 0; + valid_out_r <= 0; + end else begin + if (valid_in && ready_in && valid_out && !ready_out) begin + assert(!use_buffer); + use_buffer <= 1; + end + if (ready_out) begin + use_buffer <= 0; + end + if (valid_in && ready_in) begin + buffer <= data_in; + end + if (!valid_out || ready_out) begin + valid_out_r <= valid_in || use_buffer; + data_out_r <= use_buffer ? buffer : data_in; + end + end + end + + assign ready_in = !use_buffer; + assign valid_out = valid_out_r; + assign data_out = data_out_r; + +endmodule \ No newline at end of file diff --git a/hw/rtl/tex_unit/VX_tex_mgr.v b/hw/rtl/tex_unit/VX_tex_mgr.v index 42184037..a7de9180 100644 --- a/hw/rtl/tex_unit/VX_tex_mgr.v +++ b/hw/rtl/tex_unit/VX_tex_mgr.v @@ -1,8 +1,8 @@ -`include "VX_define.vh" +`include "VX_platform.vh" module VX_tex_mgr ( input wire clk, - input wire reset, + input wire reset ); //-- diff --git a/hw/rtl/tex_unit/VX_tex_unit.v b/hw/rtl/tex_unit/VX_tex_unit.v index b7eef8d8..a7c38cfe 100644 --- a/hw/rtl/tex_unit/VX_tex_unit.v +++ b/hw/rtl/tex_unit/VX_tex_unit.v @@ -1,4 +1,4 @@ -`include "VX_define.vh" +`include "VX_platform.vh" module VX_tex_unit #( parameter TADDRW = 32, @@ -11,7 +11,7 @@ module VX_tex_unit #( parameter MAXAMW = 2, parameter TAGW = 16, - parameter NUMCRQS = 32, + parameter NUMCRQS = 32 ) ( input wire clk, input wire reset, diff --git a/hw/scripts/gen_config.py b/hw/scripts/gen_config.py index 426c83a8..05ecb8bb 100755 --- a/hw/scripts/gen_config.py +++ b/hw/scripts/gen_config.py @@ -58,13 +58,12 @@ if args.outc != 'none': translation_rules = [ (re.compile(r'^$'), r''), - (re.compile(r'^( *)`ifndef ([^ ]+)$'), r'\1#ifndef \2'), - (re.compile(r'^( *)`define ([^ ]+)$'), r'\1#define \2'), - # (re.compile(r'^( *)`include "\./VX_define_synth\.v"$'), r'\1#include "VX_define_synth.h"'), - (re.compile(r'^( *)`include "VX_user_config\.vh"$'), r''), - (re.compile(r'^( *)`define ([^ ]+) (.+)$'), r'\1#define \2 \3'), - (re.compile(r'^( *)`endif$'), r'\1#endif'), - (re.compile(r'^( *)// (.*)$'), r'\1// \2'), + (re.compile(r'^(\s*)`ifndef\s+([^ ]+)'), r'\1#ifndef \2'), + (re.compile(r'^(\s*)`define\s+([^ ]+)'), r'\1#define \2'), + (re.compile(r'^(\s*)`include "VX_user_config\.vh"'), r''), + (re.compile(r'^(\s*)`define\s+([^ ]+) (.+)'), r'\1#define \2 \3'), + (re.compile(r'^(\s*)`endif\s+'), r'\1#endif'), + (re.compile(r'^(\s*)//(.*)'), r'\1// \2'), ] post_rules = [ @@ -78,7 +77,6 @@ post_rules = [ (re.compile(r"`([A-Za-z_][$_0-9A-Za-z]*)"), r'\1'), ] - def post_process_line(line): for pat, repl in post_rules: line = pat.sub(repl, line) @@ -96,6 +94,7 @@ if args.outc != 'none': // Translated from VX_config.vh: '''[1:].format(date=datetime.now()), file=f) with open(path.join(script_dir, '../rtl/VX_config.vh'), 'r') as r: + lineno = 0 for line in r: if in_expansion: f.write(post_process_line(line)) @@ -109,7 +108,8 @@ if args.outc != 'none': f.write(post_process_line(pat.sub(repl, line))) break else: - raise ValueError('failed to find rule for: ' + line) + raise ValueError('failed to find rule for: "' + line + '" (' + str(lineno) + ')') + lineno = lineno + 1 print(''' // Misc diff --git a/hw/simulate/Makefile b/hw/simulate/Makefile index 7b665714..1a31fd2d 100644 --- a/hw/simulate/Makefile +++ b/hw/simulate/Makefile @@ -1,6 +1,8 @@ +SINGLECORE += -DNUM_CLUSTERS=1 -DNUM_CORES=1 + #MULTICORE += -DNUM_CLUSTERS=2 -DNUM_CORES=4 -DL2_ENABLE=1 #MULTICORE += -DNUM_CLUSTERS=1 -DNUM_CORES=4 -DL2_ENABLE=1 -MULTICORE += -DNUM_CLUSTERS=1 -DNUM_CORES=2 +MULTICORE += -DNUM_CLUSTERS=1 -DNUM_CORES=2 -DL2_ENABLE=0 # control RTL debug print states DBG_PRINT_FLAGS += -DDBG_PRINT_CORE_ICACHE @@ -12,12 +14,14 @@ DBG_PRINT_FLAGS += -DDBG_PRINT_DRAM DBG_PRINT_FLAGS += -DDBG_PRINT_PIPELINE DBG_PRINT_FLAGS += -DDBG_PRINT_OPAE -#DBG_FLAGS += $(DBG_PRINT_FLAGS) +DBG_FLAGS += $(DBG_PRINT_FLAGS) DBG_FLAGS += -DDBG_CORE_REQ_INFO -INCLUDE = -I../rtl/ -I../rtl/libs -I../rtl/interfaces -I../rtl/cache -I../rtl/simulate +FPU_INCLUDE = -I../rtl/fp_cores -I../rtl/fp_cores/svdpi -I../rtl/fp_cores/fpnew/src/common_cells/include -I../rtl/fp_cores/fpnew/src/common_cells/src -I../rtl/fp_cores/fpnew/src/fpu_div_sqrt_mvp/hdl -I../rtl/fp_cores/fpnew/src +INCLUDE = -I../rtl/ -I../rtl/libs -I../rtl/interfaces -I../rtl/cache -I../rtl/simulate $(FPU_INCLUDE) SRCS = simulator.cpp testbench.cpp +SRCS += ../rtl/fp_cores/svdpi/float_dpi.cpp all: build-s @@ -26,30 +30,31 @@ CF += -std=c++11 -fms-extensions -I../.. VF += --language 1800-2009 --assert -Wall -Wpedantic VF += -Wno-DECLFILENAME VF += --x-initial unique --x-assign unique -VF += -exe $(SRCS) $(INCLUDE) +VF += --exe $(SRCS) $(INCLUDE) +VF += --cc Vortex.v --top-module Vortex +VF += verilator.vlt DBG += -DVCD_OUTPUT $(DBG_FLAGS) -DBG += -DDBG_CORE_REQ_INFO THREADS ?= $(shell python3 -c 'import multiprocessing as mp; print(max(1, mp.cpu_count() // 2))') gen-s: - verilator $(VF) -DNDEBUG -cc Vortex.v -CFLAGS '$(CF) -DNDEBUG' + verilator $(VF) -DNDEBUG $(SINGLECORE) -CFLAGS '$(CF) -DNDEBUG $(SINGLECORE)' gen-sd: - verilator $(VF) -cc Vortex.v -CFLAGS '$(CF) -g -O0 $(DBG)' --trace $(DBG) + verilator $(VF) $(SINGLECORE) -CFLAGS '$(CF) -g -O0 $(DBG) $(SINGLECORE)' --trace $(DBG) gen-st: - verilator $(VF) -DNDEBUG -cc Vortex.v -CFLAGS '$(CF) -DNDEBUG -O2' --threads $(THREADS) + verilator $(VF) -DNDEBUG $(SINGLECORE) -CFLAGS '$(CF) -DNDEBUG -O2 $(SINGLECORE)' --threads $(THREADS) gen-m: - verilator $(VF) -DNDEBUG -cc Vortex.v $(MULTICORE) -CFLAGS '$(CF) -DNDEBUG $(MULTICORE)' + verilator $(VF) -DNDEBUG $(MULTICORE) -CFLAGS '$(CF) -DNDEBUG $(MULTICORE)' gen-md: - verilator $(VF) -cc Vortex.v $(MULTICORE) -CFLAGS '$(CF) -g -O0 $(DBG) $(MULTICORE)' --trace $(DBG) + verilator $(VF) $(MULTICORE) -CFLAGS '$(CF) -g -O0 $(DBG) $(MULTICORE)' --trace $(DBG) gen-mt: - verilator $(VF) -DNDEBUG -cc Vortex.v $(MULTICORE) -CFLAGS '$(CF) -DNDEBUG -O2 $(MULTICORE)' --threads $(THREADS) + verilator $(VF) -DNDEBUG $(MULTICORE) -CFLAGS '$(CF) -DNDEBUG -O2 $(MULTICORE)' --threads $(THREADS) build-s: gen-s (cd obj_dir && make -j -f VVortex.mk) @@ -89,4 +94,4 @@ run-mt: build-mt (cd obj_dir && ./VVortex) clean: - rm -rf obj_dir \ No newline at end of file + rm -rf obj_dir diff --git a/hw/simulate/ram.h b/hw/simulate/ram.h index 53df7e0f..0ddd3e47 100644 --- a/hw/simulate/ram.h +++ b/hw/simulate/ram.h @@ -36,7 +36,7 @@ public: void clear() { for (uint32_t i = 0; i < (1 << 12); i++) { if (mem_[i]) { - delete mem_[i]; + delete [] mem_[i]; mem_[i] = NULL; } } diff --git a/hw/simulate/simulator.cpp b/hw/simulate/simulator.cpp index 2976a43c..99a5599f 100644 --- a/hw/simulate/simulator.cpp +++ b/hw/simulate/simulator.cpp @@ -12,16 +12,21 @@ double sc_time_stamp() { Simulator::Simulator() { // force random values for unitialized signals Verilated::randReset(2); + Verilated::randSeed(50); + + // Turn off assertion before reset + Verilated::assertOn(false); ram_ = nullptr; vortex_ = new VVortex(); dram_rsp_active_ = false; snp_req_active_ = false; + csr_req_active_ = false; #ifdef VCD_OUTPUT Verilated::traceEverOn(true); - trace_ = new VerilatedVcdC; + trace_ = new VerilatedVcdC(); vortex_->trace(trace_, 99); trace_->open("trace.vcd"); #endif @@ -49,6 +54,9 @@ void Simulator::reset() { vortex_->reset = 0; dram_rsp_vec_.clear(); + + // Turn on assertion after reset + Verilated::assertOn(true); } void Simulator::step() { @@ -60,6 +68,7 @@ void Simulator::step() { this->eval_dram_bus(); this->eval_io_bus(); + this->eval_csr_bus(); this->eval_snp_bus(); } @@ -98,9 +107,8 @@ void Simulator::eval_dram_bus() { if (!dram_rsp_active_) { if (dequeue_index != -1) { vortex_->dram_rsp_valid = 1; - memcpy((uint8_t*)vortex_->dram_rsp_data, dram_rsp_vec_[dequeue_index].data, GLOBAL_BLOCK_SIZE); - vortex_->dram_rsp_tag = dram_rsp_vec_[dequeue_index].tag; - free(dram_rsp_vec_[dequeue_index].data); + memcpy((uint8_t*)vortex_->dram_rsp_data, dram_rsp_vec_[dequeue_index].block.data(), GLOBAL_BLOCK_SIZE); + vortex_->dram_rsp_tag = dram_rsp_vec_[dequeue_index].tag; dram_rsp_vec_.erase(dram_rsp_vec_.begin() + dequeue_index); dram_rsp_active_ = true; } else { @@ -134,9 +142,8 @@ void Simulator::eval_dram_bus() { } else { dram_req_t dram_req; dram_req.cycles_left = DRAM_LATENCY; - dram_req.data = (uint8_t*)malloc(GLOBAL_BLOCK_SIZE); dram_req.tag = vortex_->dram_req_tag; - ram_->read(vortex_->dram_req_addr * GLOBAL_BLOCK_SIZE, GLOBAL_BLOCK_SIZE, dram_req.data); + ram_->read(vortex_->dram_req_addr * GLOBAL_BLOCK_SIZE, GLOBAL_BLOCK_SIZE, dram_req.block.data()); dram_rsp_vec_.push_back(dram_req); } } @@ -189,14 +196,37 @@ void Simulator::eval_snp_bus() { } } +void Simulator::eval_csr_bus() { + if (csr_req_active_) { + if (vortex_->csr_io_req_rw) { + if (vortex_->csr_io_req_ready) { + vortex_->snp_req_valid = 0; + csr_req_active_ = false; + } + } else { + if (vortex_->csr_io_rsp_valid) { + *csr_rsp_value_ = vortex_->csr_io_rsp_data; + vortex_->snp_req_valid = 0; + vortex_->csr_io_rsp_ready = 0; + csr_req_active_ = false; + } + } + } else { + vortex_->csr_io_req_valid = 0; + vortex_->csr_io_rsp_ready = 0; + } +} + void Simulator::wait(uint32_t cycles) { for (int i = 0; i < cycles; ++i) { this->step(); } } -bool Simulator::is_busy() { - return vortex_->busy || snp_req_active_; +bool Simulator::is_busy() const { + return vortex_->busy + || snp_req_active_ + || csr_req_active_; } void Simulator::flush_caches(uint32_t mem_addr, uint32_t size) { @@ -206,23 +236,53 @@ void Simulator::flush_caches(uint32_t mem_addr, uint32_t size) { if (0 == size) return; - snp_req_active_ = true; - snp_req_size_ = (size + GLOBAL_BLOCK_SIZE - 1) / GLOBAL_BLOCK_SIZE; - vortex_->snp_req_addr = mem_addr / GLOBAL_BLOCK_SIZE; vortex_->snp_req_tag = 0; vortex_->snp_req_valid = 1; vortex_->snp_rsp_ready = 1; + snp_req_size_ = (size + GLOBAL_BLOCK_SIZE - 1) / GLOBAL_BLOCK_SIZE; --snp_req_size_; pending_snp_reqs_ = 1; + + snp_req_active_ = true; #ifdef DBG_PRINT_CACHE_SNP std::cout << timestamp << ": [sim] snp req: addr=" << std::hex << vortex_->snp_req_addr << std::dec << " tag=" << vortex_->snp_req_tag << " remain=" << snp_req_size_ << std::endl; #endif } -bool Simulator::run() { +void Simulator::set_csr(int core_id, int addr, unsigned value) { +#ifndef NDEBUG + std::cout << timestamp << ": [sim] set_csr()" << std::endl; +#endif + + vortex_->csr_io_req_valid = 1; + vortex_->csr_io_req_coreid = core_id; + vortex_->csr_io_req_addr = addr; + vortex_->csr_io_req_rw = 1; + vortex_->csr_io_req_data = value; + vortex_->csr_io_rsp_ready = 0; + + csr_req_active_ = true; +} + +void Simulator::get_csr(int core_id, int addr, unsigned *value) { +#ifndef NDEBUG + std::cout << timestamp << ": [sim] get_csr()" << std::endl; +#endif + + vortex_->csr_io_req_valid = 1; + vortex_->csr_io_req_coreid = core_id; + vortex_->csr_io_req_addr = addr; + vortex_->csr_io_req_rw = 0; + vortex_->csr_io_rsp_ready = 1; + + csr_rsp_value_ = value; + csr_req_active_ = true; +} + +void Simulator::run() { #ifndef NDEBUG std::cout << timestamp << ": [sim] run()" << std::endl; #endif @@ -237,22 +297,16 @@ bool Simulator::run() { } // wait 5 cycles to flush the pipeline - this->wait(5); - - // check riscv-tests PASSED/FAILED status -#if (NUM_CLUSTERS == 1 && NUM_CORES == 1) - int status = (int)vortex_->Vortex->genblk1__DOT__cluster->genblk1__BRA__0__KET____DOT__core->pipeline->back_end->writeback->last_data_wb & 0xf; -#else -#if (NUM_CLUSTERS == 1) - int status = (int)vortex_->Vortex->genblk1__DOT__cluster->genblk1__BRA__0__KET____DOT__core->pipeline->back_end->writeback->last_data_wb & 0xf; -#else - int status = (int)vortex_->Vortex->genblk2__DOT__genblk1__BRA__0__KET____DOT__cluster->genblk1__BRA__0__KET____DOT__core->pipeline->back_end->writeback->last_data_wb & 0xf; -#endif -#endif - - return (status == 1); + this->wait(5); } +int Simulator::get_last_wb_value(int reg) const { + #if (NUM_CLUSTERS != 1) + return (int)vortex_->Vortex->genblk2__DOT__genblk1__BRA__0__KET____DOT__cluster->genblk1__BRA__0__KET____DOT__core->pipeline->commit->writeback->last_wb_value[reg]; + #else + return (int)vortex_->Vortex->genblk1__DOT__cluster->genblk1__BRA__0__KET____DOT__core->pipeline->commit->writeback->last_wb_value[reg]; + #endif +} void Simulator::load_bin(const char* program_file) { if (ram_ == nullptr) diff --git a/hw/simulate/simulator.h b/hw/simulate/simulator.h index 27803754..a16218bb 100644 --- a/hw/simulate/simulator.h +++ b/hw/simulate/simulator.h @@ -15,13 +15,13 @@ #include #define ENABLE_DRAM_STALLS -#define DRAM_LATENCY 100 +#define DRAM_LATENCY 4 #define DRAM_RQ_SIZE 16 #define DRAM_STALLS_MODULO 16 typedef struct { int cycles_left; - uint8_t *data; + std::array block; unsigned tag; } dram_req_t; @@ -31,19 +31,24 @@ public: Simulator(); virtual ~Simulator(); + void attach_ram(RAM* ram); + void load_bin(const char* program_file); void load_ihex(const char* program_file); - bool is_busy(); + bool is_busy() const; void reset(); void step(); void wait(uint32_t cycles); + void flush_caches(uint32_t mem_addr, uint32_t size); + void set_csr(int core_id, int addr, unsigned value); + void get_csr(int core_id, int addr, unsigned *value); - void attach_ram(RAM* ram); + void run(); + int get_last_wb_value(int reg) const; - bool run(); void print_stats(std::ostream& out); private: @@ -52,14 +57,18 @@ private: void eval_dram_bus(); void eval_io_bus(); + void eval_csr_bus(); void eval_snp_bus(); std::vector dram_rsp_vec_; int dram_rsp_active_; bool snp_req_active_; + bool csr_req_active_; + uint32_t snp_req_size_; uint32_t pending_snp_reqs_; + uint32_t* csr_rsp_value_; RAM *ram_; VVortex *vortex_; diff --git a/hw/simulate/testbench.cpp b/hw/simulate/testbench.cpp index d037fc18..63c0cd66 100644 --- a/hw/simulate/testbench.cpp +++ b/hw/simulate/testbench.cpp @@ -3,59 +3,78 @@ #include #include -int main(int argc, char **argv) -{ -//#define ALL_TESTS +#define ALL_TESTS + +int main(int argc, char **argv) { + if (argc == 1) { #ifdef ALL_TESTS bool passed = true; std::string tests[] = { - "../../../benchmarks/riscv_tests/rv32ui-p-add.hex", - "../../../benchmarks/riscv_tests/rv32ui-p-addi.hex", - "../../../benchmarks/riscv_tests/rv32ui-p-and.hex", - "../../../benchmarks/riscv_tests/rv32ui-p-andi.hex", - "../../../benchmarks/riscv_tests/rv32ui-p-auipc.hex", - "../../../benchmarks/riscv_tests/rv32ui-p-beq.hex", - "../../../benchmarks/riscv_tests/rv32ui-p-bge.hex", - "../../../benchmarks/riscv_tests/rv32ui-p-bgeu.hex", - "../../../benchmarks/riscv_tests/rv32ui-p-blt.hex", - "../../../benchmarks/riscv_tests/rv32ui-p-bltu.hex", - "../../../benchmarks/riscv_tests/rv32ui-p-bne.hex", - "../../../benchmarks/riscv_tests/rv32ui-p-jal.hex", - "../../../benchmarks/riscv_tests/rv32ui-p-jalr.hex", - "../../../benchmarks/riscv_tests/rv32ui-p-lb.hex", - "../../../benchmarks/riscv_tests/rv32ui-p-lbu.hex", - "../../../benchmarks/riscv_tests/rv32ui-p-lh.hex", - "../../../benchmarks/riscv_tests/rv32ui-p-lhu.hex", - "../../../benchmarks/riscv_tests/rv32ui-p-lui.hex", - "../../../benchmarks/riscv_tests/rv32ui-p-lw.hex", - "../../../benchmarks/riscv_tests/rv32ui-p-or.hex", - "../../../benchmarks/riscv_tests/rv32ui-p-ori.hex", - "../../../benchmarks/riscv_tests/rv32ui-p-sb.hex", - "../../../benchmarks/riscv_tests/rv32ui-p-sh.hex", - "../../../benchmarks/riscv_tests/rv32ui-p-simple.hex", - "../../../benchmarks/riscv_tests/rv32ui-p-sll.hex", - "../../../benchmarks/riscv_tests/rv32ui-p-slli.hex", - "../../../benchmarks/riscv_tests/rv32ui-p-slt.hex", - "../../../benchmarks/riscv_tests/rv32ui-p-slti.hex", - "../../../benchmarks/riscv_tests/rv32ui-p-sltiu.hex", - "../../../benchmarks/riscv_tests/rv32ui-p-sltu.hex", - "../../../benchmarks/riscv_tests/rv32ui-p-sra.hex", - "../../../benchmarks/riscv_tests/rv32ui-p-srai.hex", - "../../../benchmarks/riscv_tests/rv32ui-p-srl.hex", - "../../../benchmarks/riscv_tests/rv32ui-p-srli.hex", - "../../../benchmarks/riscv_tests/rv32ui-p-sub.hex", - "../../../benchmarks/riscv_tests/rv32ui-p-sw.hex", - "../../../benchmarks/riscv_tests/rv32ui-p-xor.hex", - "../../../benchmarks/riscv_tests/rv32ui-p-xori.hex", - "../../../benchmarks/riscv_tests/rv32um-p-div.hex", - "../../../benchmarks/riscv_tests/rv32um-p-divu.hex", - "../../../benchmarks/riscv_tests/rv32um-p-mul.hex", - "../../../benchmarks/riscv_tests/rv32um-p-mulh.hex", - "../../../benchmarks/riscv_tests/rv32um-p-mulhsu.hex", - "../../../benchmarks/riscv_tests/rv32um-p-mulhu.hex", - "../../../benchmarks/riscv_tests/rv32um-p-rem.hex", - "../../../benchmarks/riscv_tests/rv32um-p-remu.hex" + "../../../benchmarks/riscv_tests/isa/rv32ui-p-add.hex", + "../../../benchmarks/riscv_tests/isa/rv32ui-p-addi.hex", + "../../../benchmarks/riscv_tests/isa/rv32ui-p-and.hex", + "../../../benchmarks/riscv_tests/isa/rv32ui-p-andi.hex", + "../../../benchmarks/riscv_tests/isa/rv32ui-p-auipc.hex", + "../../../benchmarks/riscv_tests/isa/rv32ui-p-beq.hex", + "../../../benchmarks/riscv_tests/isa/rv32ui-p-bge.hex", + "../../../benchmarks/riscv_tests/isa/rv32ui-p-bgeu.hex", + "../../../benchmarks/riscv_tests/isa/rv32ui-p-blt.hex", + "../../../benchmarks/riscv_tests/isa/rv32ui-p-bltu.hex", + "../../../benchmarks/riscv_tests/isa/rv32ui-p-bne.hex", + "../../../benchmarks/riscv_tests/isa/rv32ui-p-jal.hex", + "../../../benchmarks/riscv_tests/isa/rv32ui-p-jalr.hex", + "../../../benchmarks/riscv_tests/isa/rv32ui-p-lb.hex", + "../../../benchmarks/riscv_tests/isa/rv32ui-p-lbu.hex", + "../../../benchmarks/riscv_tests/isa/rv32ui-p-lh.hex", + "../../../benchmarks/riscv_tests/isa/rv32ui-p-lhu.hex", + "../../../benchmarks/riscv_tests/isa/rv32ui-p-lui.hex", + "../../../benchmarks/riscv_tests/isa/rv32ui-p-lw.hex", + "../../../benchmarks/riscv_tests/isa/rv32ui-p-or.hex", + "../../../benchmarks/riscv_tests/isa/rv32ui-p-ori.hex", + "../../../benchmarks/riscv_tests/isa/rv32ui-p-sb.hex", + "../../../benchmarks/riscv_tests/isa/rv32ui-p-sh.hex", + "../../../benchmarks/riscv_tests/isa/rv32ui-p-simple.hex", + "../../../benchmarks/riscv_tests/isa/rv32ui-p-sll.hex", + "../../../benchmarks/riscv_tests/isa/rv32ui-p-slli.hex", + "../../../benchmarks/riscv_tests/isa/rv32ui-p-slt.hex", + "../../../benchmarks/riscv_tests/isa/rv32ui-p-slti.hex", + "../../../benchmarks/riscv_tests/isa/rv32ui-p-sltiu.hex", + "../../../benchmarks/riscv_tests/isa/rv32ui-p-sltu.hex", + "../../../benchmarks/riscv_tests/isa/rv32ui-p-sra.hex", + "../../../benchmarks/riscv_tests/isa/rv32ui-p-srai.hex", + "../../../benchmarks/riscv_tests/isa/rv32ui-p-srl.hex", + "../../../benchmarks/riscv_tests/isa/rv32ui-p-srli.hex", + "../../../benchmarks/riscv_tests/isa/rv32ui-p-sub.hex", + "../../../benchmarks/riscv_tests/isa/rv32ui-p-sw.hex", + "../../../benchmarks/riscv_tests/isa/rv32ui-p-xor.hex", + "../../../benchmarks/riscv_tests/isa/rv32ui-p-xori.hex", +#ifdef EXT_M_ENABLE + "../../../benchmarks/riscv_tests/isa/rv32um-p-div.hex", + "../../../benchmarks/riscv_tests/isa/rv32um-p-divu.hex", + "../../../benchmarks/riscv_tests/isa/rv32um-p-mul.hex", + "../../../benchmarks/riscv_tests/isa/rv32um-p-mulh.hex", + "../../../benchmarks/riscv_tests/isa/rv32um-p-mulhsu.hex", + "../../../benchmarks/riscv_tests/isa/rv32um-p-mulhu.hex", + "../../../benchmarks/riscv_tests/isa/rv32um-p-rem.hex", + "../../../benchmarks/riscv_tests/isa/rv32um-p-remu.hex", +#endif + }; + + std::string tests_fp[] = { +#ifdef EXT_F_ENABLE + "../../../benchmarks/riscv_tests/isa/rv32uf-p-fadd.hex", + "../../../benchmarks/riscv_tests/isa/rv32uf-p-fdiv.hex", + "../../../benchmarks/riscv_tests/isa/rv32uf-p-fmadd.hex", + "../../../benchmarks/riscv_tests/isa/rv32uf-p-fmin.hex", + "../../../benchmarks/riscv_tests/isa/rv32uf-p-fcmp.hex", + "../../../benchmarks/riscv_tests/isa/rv32uf-p-ldst.hex", + "../../../benchmarks/riscv_tests/isa/rv32uf-p-fcvt.hex", + "../../../benchmarks/riscv_tests/isa/rv32uf-p-fcvt_w.hex", + "../../../benchmarks/riscv_tests/isa/rv32uf-p-fclass.hex", + "../../../benchmarks/riscv_tests/isa/rv32uf-p-move.hex", + "../../../benchmarks/riscv_tests/isa/rv32uf-p-recoding.hex", +#endif }; for (std::string test : tests) { @@ -67,12 +86,37 @@ int main(int argc, char **argv) Simulator simulator; simulator.attach_ram(&ram); simulator.load_ihex(test.c_str()); - bool curr = simulator.run(); + simulator.run(); - if (curr) std::cerr << GREEN << "Test Passed: " << test << std::endl; - if (!curr) std::cerr << RED << "Test Failed: " << test << std::endl; + bool status = (1 == simulator.get_last_wb_value(3)); + + if (status) std::cerr << GREEN << "Test Passed: " << test << std::endl; + if (!status) std::cerr << RED << "Test Failed: " << test << std::endl; std::cerr << DEFAULT; - passed = passed && curr; + passed = passed && status; + if (!passed) + break; + } + + for (std::string test : tests_fp) { + std::cerr << DEFAULT << "\n---------------------------------------\n"; + + std::cerr << test << std::endl; + + RAM ram; + Simulator simulator; + simulator.attach_ram(&ram); + simulator.load_ihex(test.c_str()); + simulator.run(); + + bool status = (1 == simulator.get_last_wb_value(3)); + + if (status) std::cerr << GREEN << "Test Passed: " << test << std::endl; + if (!status) std::cerr << RED << "Test Failed: " << test << std::endl; + std::cerr << DEFAULT; + passed = passed && status; + if (!passed) + break; } std::cerr << DEFAULT << "\n***************************************\n"; @@ -85,9 +129,6 @@ int main(int argc, char **argv) #else char test[] = "../../../runtime/tests/simple/vx_simple.hex"; - //char test[] = "../../../benchmarks/riscv_tests/rv32ui-p-lb.hex"; - //char test[] = "../../../benchmarks/riscv_tests/rv32ui-p-lw.hex"; - //char test[] = "../../../benchmarks/riscv_tests/rv32ui-p-sw.hex"; std::cerr << test << std::endl; @@ -95,12 +136,37 @@ int main(int argc, char **argv) Simulator simulator; simulator.attach_ram(&ram); simulator.load_ihex(test); - bool curr = simulator.run(); + simulator.run(); - if (curr) std::cerr << GREEN << "Test Passed: " << test << std::endl; - if (!curr) std::cerr << RED << "Test Failed: " << test << std::endl; - - return !curr; + return 0; #endif -} \ No newline at end of file + +} else { + bool passed = true; + + std::vector tests(argv+2, argv+argc); + for (std::string test : tests) { + std::cerr << DEFAULT << "\n---------------------------------------\n"; + + std::cerr << test << std::endl; + + RAM ram; + Simulator simulator; + simulator.attach_ram(&ram); + simulator.load_ihex(test.c_str()); + simulator.run(); + + bool status = (1 == simulator.get_last_wb_value(3)); + + if (status) std::cerr << GREEN << "Test Passed: " << test << std::endl; + if (!status) std::cerr << RED << "Test Failed: " << test << std::endl; + std::cerr << DEFAULT; + passed = passed && status; + if (!passed) + break; + } + return 0; +} + +} diff --git a/hw/simulate/verilator.vlt b/hw/simulate/verilator.vlt new file mode 100644 index 00000000..5598b43e --- /dev/null +++ b/hw/simulate/verilator.vlt @@ -0,0 +1,9 @@ +`verilator_config + +lint_off -rule BLKANDNBLK -file "../rtl/fp_cores/fpnew/*" +lint_off -rule UNOPTFLAT -file "../rtl/fp_cores/fpnew/*" +lint_off -rule WIDTH -file "../rtl/fp_cores/fpnew/*" +lint_off -rule UNUSED -file "../rtl/fp_cores/fpnew/*" +lint_off -rule LITENDIAN -file "../rtl/fp_cores/fpnew/*" +lint_off -rule IMPORTSTAR -file "../rtl/fp_cores/fpnew/*" +lint_off -rule PINCONNECTEMPTY -file "../rtl/fp_cores/fpnew/*" \ No newline at end of file diff --git a/hw/syn/quartus/cache/Makefile b/hw/syn/quartus/cache/Makefile index 8c69066f..444a8d29 100755 --- a/hw/syn/quartus/cache/Makefile +++ b/hw/syn/quartus/cache/Makefile @@ -9,9 +9,9 @@ DEVICE = 10AX115N3F40E2SG # Executable Configuration SYN_ARGS = --parallel --read_settings_files=on -FIT_ARGS = --part=$(DEVICE) --read_settings_files=on +FIT_ARGS = --parallel --part=$(DEVICE) --read_settings_files=on ASM_ARGS = -STA_ARGS = --do_report_timing +STA_ARGS = --parallel --do_report_timing # Build targets all: $(PROJECT).sta.rpt diff --git a/hw/syn/quartus/core/Makefile b/hw/syn/quartus/core/Makefile index 0968b478..477d454d 100644 --- a/hw/syn/quartus/core/Makefile +++ b/hw/syn/quartus/core/Makefile @@ -1,6 +1,8 @@ PROJECT = Core TOP_LEVEL_ENTITY = VX_core SRC_FILE = VX_core.v +FPU_INCLUDE = ../../../rtl/fp_cores;../../../rtl/fp_cores/altera;../../../rtl/fp_cores/fpnew/src;../../../rtl/fp_cores/fpnew/src/fpu_div_sqrt_mvp/hdl;../../../rtl/fp_cores/fpnew/src/common_cells/include;../../../rtl/fp_cores/fpnew/src/common_cells/src +RTL_INCLUDE = $(FPU_INCLUDE);../../../rtl;../../../rtl/libs;../../../rtl/interfaces;../../../rtl/cache PROJECT_FILES = $(PROJECT).qpf $(PROJECT).qsf # Part, Family @@ -9,9 +11,9 @@ DEVICE = 10AX115N3F40E2SG # Executable Configuration SYN_ARGS = --parallel --read_settings_files=on -FIT_ARGS = --part=$(DEVICE) --read_settings_files=on +FIT_ARGS = --parallel --part=$(DEVICE) --read_settings_files=on ASM_ARGS = -STA_ARGS = --do_report_timing +STA_ARGS = --parallel --do_report_timing # Build targets all: $(PROJECT).sta.rpt @@ -49,7 +51,7 @@ smart.log: $(PROJECT_FILES) # Project initialization $(PROJECT_FILES): - quartus_sh -t ../project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src $(SRC_FILE) -sdc ../project.sdc -inc "../../../rtl;../../../rtl/libs;../../../rtl/interfaces;../../../rtl/cache" + quartus_sh -t ../project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src "$(SRC_FILE)" -sdc ../project.sdc -inc "$(RTL_INCLUDE)" syn.chg: $(STAMP) syn.chg diff --git a/hw/syn/quartus/pipeline/Makefile b/hw/syn/quartus/pipeline/Makefile index 49232fe8..76bad071 100644 --- a/hw/syn/quartus/pipeline/Makefile +++ b/hw/syn/quartus/pipeline/Makefile @@ -1,6 +1,8 @@ PROJECT = VX_pipeline TOP_LEVEL_ENTITY = VX_pipeline SRC_FILE = VX_pipeline.v +FPU_INCLUDE = ../../../rtl/fp_cores;../../../rtl/fp_cores/altera;../../../rtl/fp_cores/fpnew/src;../../../rtl/fp_cores/fpnew/src/fpu_div_sqrt_mvp/hdl;../../../rtl/fp_cores/fpnew/src/common_cells/include;../../../rtl/fp_cores/fpnew/src/common_cells/src +RTL_INCLUDE = $(FPU_INCLUDE);../../../rtl;../../../rtl/libs;../../../rtl/interfaces PROJECT_FILES = $(PROJECT).qpf $(PROJECT).qsf # Part, Family @@ -9,9 +11,9 @@ DEVICE = 10AX115N3F40E2SG # Executable Configuration SYN_ARGS = --parallel --read_settings_files=on -FIT_ARGS = --part=$(DEVICE) --read_settings_files=on +FIT_ARGS = --parallel --part=$(DEVICE) --read_settings_files=on ASM_ARGS = -STA_ARGS = --do_report_timing +STA_ARGS = --parallel --do_report_timing # Build targets all: $(PROJECT).sta.rpt @@ -49,7 +51,7 @@ smart.log: $(PROJECT_FILES) # Project initialization $(PROJECT_FILES): - quartus_sh -t ../project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src $(SRC_FILE) -sdc ../project.sdc -inc "../../../rtl;../../../rtl/libs;../../../rtl/interfaces" + quartus_sh -t ../project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src "$(SRC_FILE)" -sdc ../project.sdc -inc "$(RTL_INCLUDE)" syn.chg: $(STAMP) syn.chg diff --git a/hw/syn/quartus/project.tcl b/hw/syn/quartus/project.tcl index e3d1f2cc..93102ec5 100644 --- a/hw/syn/quartus/project.tcl +++ b/hw/syn/quartus/project.tcl @@ -33,9 +33,27 @@ set_global_assignment -name TOP_LEVEL_ENTITY $opts(top) set_global_assignment -name PROJECT_OUTPUT_DIRECTORY bin set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2009 +set_global_assignment -name ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS OFF set_global_assignment -name VERILOG_MACRO QUARTUS set_global_assignment -name VERILOG_MACRO SYNTHESIS set_global_assignment -name VERILOG_MACRO NDEBUG +set_global_assignment -name MESSAGE_DISABLE 16818 +set_global_assignment -name VERILOG_MACRO FPU_FAST + +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100 +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON +set_global_assignment -name FITTER_EFFORT "STANDARD FIT" +set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS ON +set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION ON +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON +set_global_assignment -name OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON +set_global_assignment -name POWER_USE_TA_VALUE 65 +set_global_assignment -name SEED 1 set idx 0 foreach arg $q_args_orig { diff --git a/hw/syn/quartus/timing.tcl b/hw/syn/quartus/timing.tcl index 411379dc..5e9def4d 100644 --- a/hw/syn/quartus/timing.tcl +++ b/hw/syn/quartus/timing.tcl @@ -1,4 +1,4 @@ -project_open Vortex_Socket +project_open VX_pipeline set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL diff --git a/hw/syn/quartus/top/Makefile b/hw/syn/quartus/top/Makefile index c6219230..6258682f 100644 --- a/hw/syn/quartus/top/Makefile +++ b/hw/syn/quartus/top/Makefile @@ -1,6 +1,8 @@ PROJECT = vortex_afu TOP_LEVEL_ENTITY = vortex_afu SRC_FILE = vortex_afu.sv +FPU_INCLUDE = ../../../rtl/fp_cores;../../../rtl/fp_cores/altera;../../../rtl/fp_cores/fpnew/src;../../../rtl/fp_cores/fpnew/src/fpu_div_sqrt_mvp/hdl;../../../rtl/fp_cores/fpnew/src/common_cells/include;../../../rtl/fp_cores/fpnew/src/common_cells/src +RTL_INCLUDE = $(FPU_INCLUDE);../../../rtl;../../../rtl/libs;../../../rtl/interfaces;../../../rtl/cache;../../../opae;../../../opae/ccip PROJECT_FILES = $(PROJECT).qpf $(PROJECT).qsf # Part, Family @@ -9,9 +11,9 @@ DEVICE = 10AX115N3F40E2SG # Executable Configuration SYN_ARGS = --parallel --read_settings_files=on --set=VERILOG_MACRO=NOPAE=1 -FIT_ARGS = --part=$(DEVICE) --read_settings_files=on +FIT_ARGS = --parallel --part=$(DEVICE) --read_settings_files=on ASM_ARGS = -STA_ARGS = --do_report_timing +STA_ARGS = --parallel --do_report_timing # Build targets all: $(PROJECT).sta.rpt @@ -49,7 +51,7 @@ smart.log: $(PROJECT_FILES) # Project initialization $(PROJECT_FILES): - quartus_sh -t ../project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src $(SRC_FILE) -set "NOPAE" -sdc ../project.sdc -inc "../../../rtl;../../../rtl/libs;../../../rtl/interfaces;../../../rtl/cache;../../../opae;../../../opae/ccip" + quartus_sh -t ../project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src "$(SRC_FILE)" -sdc ../project.sdc -inc "$(RTL_INCLUDE)" syn.chg: $(STAMP) syn.chg diff --git a/hw/syn/quartus/vortex/Makefile b/hw/syn/quartus/vortex/Makefile index f8db7cc8..e424db86 100644 --- a/hw/syn/quartus/vortex/Makefile +++ b/hw/syn/quartus/vortex/Makefile @@ -1,6 +1,8 @@ PROJECT = Vortex TOP_LEVEL_ENTITY = Vortex SRC_FILE = Vortex.v +FPU_INCLUDE = ../../../rtl/fp_cores;../../../rtl/fp_cores/altera;../../../rtl/fp_cores/fpnew/src;../../../rtl/fp_cores/fpnew/src/fpu_div_sqrt_mvp/hdl;../../../rtl/fp_cores/fpnew/src/common_cells/include;../../../rtl/fp_cores/fpnew/src/common_cells/src +RTL_INCLUDE = $(FPU_INCLUDE);../../../rtl;../../../rtl/libs;../../../rtl/interfaces;../../../rtl/cache PROJECT_FILES = $(PROJECT).qpf $(PROJECT).qsf # Part, Family @@ -9,9 +11,9 @@ DEVICE = 10AX115N3F40E2SG # Executable Configuration SYN_ARGS = --parallel --read_settings_files=on -FIT_ARGS = --part=$(DEVICE) --read_settings_files=on +FIT_ARGS = --parallel --part=$(DEVICE) --read_settings_files=on ASM_ARGS = -STA_ARGS = --do_report_timing +STA_ARGS = --parallel --do_report_timing # Build targets all: $(PROJECT).sta.rpt @@ -49,7 +51,7 @@ smart.log: $(PROJECT_FILES) # Project initialization $(PROJECT_FILES): - quartus_sh -t ../project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src $(SRC_FILE) -sdc ../project.sdc -inc "../../../rtl;../../../rtl/libs;../../../rtl/interfaces;../../../rtl/cache" + quartus_sh -t ../project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src "$(SRC_FILE)" -sdc ../project.sdc -inc "$(RTL_INCLUDE)" syn.chg: $(STAMP) syn.chg diff --git a/hw/syn/yosys/synth.sh b/hw/syn/yosys/synth.sh index 621866f1..544bbad0 100755 --- a/hw/syn/yosys/synth.sh +++ b/hw/syn/yosys/synth.sh @@ -12,7 +12,7 @@ echo "inc_list=$inc_list" { # read design sources for dir in $dir_list; do - for file in $(find $dir -name '*.v' -o -name '*.sv' -type f) + for file in $(find $dir -maxdepth 1 -name '*.v' -o -name '*.sv' -type f) do echo "read_verilog -sv $inc_list $file" done diff --git a/hw/syn/yosys/synth.ys b/hw/syn/yosys/synth.ys new file mode 100644 index 00000000..958f0353 --- /dev/null +++ b/hw/syn/yosys/synth.ys @@ -0,0 +1,136 @@ +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/libs/VX_countones.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/libs/VX_divide.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/libs/VX_encoder_onehot.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/libs/VX_fair_arbiter.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/libs/VX_fixed_arbiter.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/libs/VX_generic_queue.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/libs/VX_generic_register.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/libs/VX_generic_stack.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/libs/VX_indexable_queue.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/libs/VX_matrix_arbiter.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/libs/VX_mult.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/libs/VX_priority_encoder.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/libs/VX_rr_arbiter.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/libs/VX_scope.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/cache/VX_bank.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/cache/VX_bank_core_req_arb.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/cache/VX_cache.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/cache/VX_cache_core_req_bank_sel.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/cache/VX_cache_core_rsp_merge.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/cache/VX_cache_dram_fill_arb.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/cache/VX_cache_dram_req_arb.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/cache/VX_cache_miss_resrv.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/cache/VX_prefetcher.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/cache/VX_snp_forwarder.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/cache/VX_snp_rsp_arb.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/cache/VX_tag_data_access.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/cache/VX_tag_data_structure.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/interfaces/VX_backend_req_if.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/interfaces/VX_branch_rsp_if.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/interfaces/VX_cache_core_req_if.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/interfaces/VX_cache_core_rsp_if.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/interfaces/VX_cache_dram_req_if.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/interfaces/VX_cache_dram_rsp_if.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/interfaces/VX_cache_snp_req_if.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/interfaces/VX_cache_snp_rsp_if.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/interfaces/VX_csr_io_req_if.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/interfaces/VX_csr_io_rsp_if.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/interfaces/VX_csr_req_if.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/interfaces/VX_exec_unit_req_if.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/interfaces/VX_gpr_read_if.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/interfaces/VX_gpu_inst_req_if.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/interfaces/VX_inst_meta_if.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/interfaces/VX_jal_rsp_if.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/interfaces/VX_join_if.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/interfaces/VX_lsu_req_if.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/interfaces/VX_warp_ctl_if.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/interfaces/VX_wb_if.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/interfaces/VX_wstall_if.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/VX_alu_unit.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/VX_back_end.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/VX_cluster.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/VX_core.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/VX_csr_arb.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/VX_csr_data.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/VX_csr_io_arb.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/VX_csr_pipe.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/VX_d_e_reg.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/VX_dcache_arb.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/VX_decode.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/VX_exec_unit.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/VX_f_d_reg.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/VX_fetch.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/VX_front_end.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/VX_gpr_ram.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/VX_gpr_stage.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/VX_gpr_wrapper.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/VX_gpu_inst.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/VX_i_d_reg.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/VX_icache_stage.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/VX_inst_multiplex.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/VX_lsu_unit.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/VX_mem_arb.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/VX_mem_unit.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/VX_pipeline.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/VX_scheduler.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/VX_user_config.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/VX_warp.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/VX_warp_sched.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/VX_writeback.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/Vortex.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/cache/VX_bank.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/cache/VX_bank_core_req_arb.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/cache/VX_cache.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/cache/VX_cache_core_req_bank_sel.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/cache/VX_cache_core_rsp_merge.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/cache/VX_cache_dram_fill_arb.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/cache/VX_cache_dram_req_arb.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/cache/VX_cache_miss_resrv.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/cache/VX_prefetcher.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/cache/VX_snp_forwarder.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/cache/VX_snp_rsp_arb.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/cache/VX_tag_data_access.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/cache/VX_tag_data_structure.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/interfaces/VX_backend_req_if.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/interfaces/VX_branch_rsp_if.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/interfaces/VX_cache_core_req_if.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/interfaces/VX_cache_core_rsp_if.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/interfaces/VX_cache_dram_req_if.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/interfaces/VX_cache_dram_rsp_if.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/interfaces/VX_cache_snp_req_if.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/interfaces/VX_cache_snp_rsp_if.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/interfaces/VX_csr_io_req_if.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/interfaces/VX_csr_io_rsp_if.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/interfaces/VX_csr_req_if.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/interfaces/VX_exec_unit_req_if.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/interfaces/VX_gpr_read_if.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/interfaces/VX_gpu_inst_req_if.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/interfaces/VX_inst_meta_if.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/interfaces/VX_jal_rsp_if.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/interfaces/VX_join_if.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/interfaces/VX_lsu_req_if.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/interfaces/VX_warp_ctl_if.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/interfaces/VX_wb_if.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/interfaces/VX_wstall_if.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/libs/VX_countones.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/libs/VX_divide.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/libs/VX_encoder_onehot.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/libs/VX_fair_arbiter.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/libs/VX_fixed_arbiter.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/libs/VX_generic_queue.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/libs/VX_generic_register.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/libs/VX_generic_stack.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/libs/VX_indexable_queue.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/libs/VX_matrix_arbiter.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/libs/VX_mult.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/libs/VX_priority_encoder.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/libs/VX_rr_arbiter.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/libs/VX_scope.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/tex_unit/VX_tex_mgr.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/tex_unit/VX_tex_unit.v +hierarchy -check -top Vortex +add -global_input reset 1 +proc -global_arst reset +synth -run coarse; opt -fine +tee -o brams.log memory_bram -rules scripts/brams.txt;; +write_verilog -noexpr -noattr synth.v diff --git a/hw/unit_tests/VX_divide_tb.v b/hw/unit_tests/VX_divide_tb.v index 02e63e1f..a4ba539e 100644 --- a/hw/unit_tests/VX_divide_tb.v +++ b/hw/unit_tests/VX_divide_tb.v @@ -2,13 +2,13 @@ module VX_tb_divide(); - `ifdef TRACE +`ifdef TRACE initial begin $dumpfile("trace.vcd"); $dumpvars(0,test); end - `endif +`endif reg clk; reg rst; @@ -17,24 +17,23 @@ module VX_tb_divide(); wire [31:0] o_div[0:7], o_rem[0:7]; - genvar i; - generate - for (i = 0; i < 8; i++) begin : div_loop - VX_divide#( - .WIDTHN(32), - .WIDTHD(32), - .PIPELINE(i) - ) div( - .clock(clk), - .aclr(rst), - .clken(1'b1), - .numer(numer), - .denom(denom), - .quotient(o_div[i]), - .remainder(o_rem[i]) - ); - end - endgenerate + for (genvar i = 0; i < 8; i++) begin + VX_divide#( + .WIDTHN(32), + .WIDTHD(32), + .WIDTHQ(32), + .WIDTHR(32), + .PIPELINE(i) + ) div( + .clock(clk), + .aclr(rst), + .clken(1'b1), + .numer(numer), + .denom(denom), + .quotient(o_div[i]), + .remainder(o_rem[i]) + ); + end initial begin clk = 0; rst = 0; @@ -157,4 +156,4 @@ module VX_tb_divide(); always #1 clk = !clk; -endmodule: VX_tb_divide \ No newline at end of file +endmodule \ No newline at end of file diff --git a/runtime/src/vx_intrinsics.S b/runtime/src/vx_intrinsics.S index b0dbd628..1e99c794 100644 --- a/runtime/src/vx_intrinsics.S +++ b/runtime/src/vx_intrinsics.S @@ -83,11 +83,11 @@ vx_num_cores: .type vx_num_cycles, @function .global vx_num_cycles vx_num_cycles: - csrr a0, CSR_CYCLL + csrr a0, CSR_CYCLE ret .type vx_num_instrs, @function .global vx_num_instrs vx_num_instrs: - csrr a0, CSR_INSTL + csrr a0, CSR_INSTRET ret \ No newline at end of file diff --git a/runtime/src/vx_start.S b/runtime/src/vx_start.S index 029fbb90..62eb8025 100644 --- a/runtime/src/vx_start.S +++ b/runtime/src/vx_start.S @@ -49,7 +49,7 @@ vx_set_sp: slli a1, a1, 10 # multiply by 1024 csrr a2, CSR_LTID # get local thread id slli a2, a2, 2 # multiply by 4 - lui sp, STACK_BASE_ADDR # load base sp + lui sp, (SHARED_MEM_BASE_ADDR>>12) # load base sp sub sp, sp, a1 # sub thread block add sp, sp, a2 # reduce addr collision for perf diff --git a/runtime/tests/Makefile b/runtime/tests/Makefile index 3ddc4fdd..9741cb76 100644 --- a/runtime/tests/Makefile +++ b/runtime/tests/Makefile @@ -3,9 +3,19 @@ all: $(MAKE) -C dev $(MAKE) -C hello $(MAKE) -C nlTest + $(MAKE) -C vecadd + +run: + $(MAKE) -C simple run + $(MAKE) -C dev run + $(MAKE) -C hello run + $(MAKE) -C nlTest run + $(MAKE) -C vecadd run clean: $(MAKE) -C simple clean $(MAKE) -C dev clean $(MAKE) -C hello clean $(MAKE) -C nlTest clean + $(MAKE) -C vecadd clean + diff --git a/runtime/tests/dev/Makefile b/runtime/tests/dev/Makefile index a6faf9bd..f0f4719b 100644 --- a/runtime/tests/dev/Makefile +++ b/runtime/tests/dev/Makefile @@ -27,6 +27,9 @@ $(PROJECT).hex: $(PROJECT).elf $(PROJECT).elf: $(SRCS) $(CC) $(CFLAGS) $(SRCS) $(LDFLAGS) -o $(PROJECT).elf +run: $(PROJECT).hex + (cd ../../../hw/simulate/obj_dir && ./VVortex -f ../../../runtime/tests/dev/$(PROJECT).hex) + .depend: $(SRCS) $(CC) $(CFLAGS) -MM $^ > .depend; diff --git a/runtime/tests/dev/vx_dev_main.elf b/runtime/tests/dev/vx_dev_main.elf index 1c8589f0..da8b3c1b 100755 Binary files a/runtime/tests/dev/vx_dev_main.elf and b/runtime/tests/dev/vx_dev_main.elf differ diff --git a/runtime/tests/dev/vx_dev_main.hex b/runtime/tests/dev/vx_dev_main.hex index b3c5130b..b9f91d8c 100644 --- a/runtime/tests/dev/vx_dev_main.hex +++ b/runtime/tests/dev/vx_dev_main.hex @@ -1,5741 +1,245 @@ :0200000480007A -:100000009705000093854506130500026B10B500A7 -:10001000EF004005130510006B0005001385013249 -:100020001386813E3306A64093050000EF0010536F -:1000300017150000130545C3EF00903EEF00504830 -:08004000EF00102C6F00103FCF -:10004800B70700009387070063880700371500800B -:10005800130545C66F00503C678000001305000279 -:100068006B000500976101009381C179F3261002A6 -:100078009396A601732600029315A6001316260070 -:1000880037F1FF6F3301B1403301D1403301C10073 -:10009800F326100263860600130500006B000500B6 -:1000A800678000006B10B500678000006B000500DA -:1000B800678000006B40B500678000006B2005007A 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.depend: $(SRCS) $(CC) $(CFLAGS) -MM $^ > .depend; diff --git a/runtime/tests/nlTest/vx_nl_main.elf b/runtime/tests/nlTest/vx_nl_main.elf old mode 100644 new mode 100755 index 48f6879d..9e2daf69 Binary files a/runtime/tests/nlTest/vx_nl_main.elf and b/runtime/tests/nlTest/vx_nl_main.elf differ diff --git a/runtime/tests/nlTest/vx_nl_main.hex b/runtime/tests/nlTest/vx_nl_main.hex index ea030cd1..3f80bf01 100644 --- a/runtime/tests/nlTest/vx_nl_main.hex +++ b/runtime/tests/nlTest/vx_nl_main.hex @@ -1,4675 +1,5503 @@ :0200000480007A -:100000009705000093850502130540006B10B500AD -:10001000EF000001EF005040130500006B000500E9 -:10002000130540006B000500F32610029396A6010D -:10003000732600029315A6001316260037F1FF6FF2 -:100040003301B1403301D1403301C100F326100226 -:1000500063860600130500006B0005006780000042 -:10006000130101FD2326810213040103232EA4FCA6 -:10007000232CB4FC232AC4FC8327C4FD83A70700D8 -:100080002326F4FE832744FD2322F4FE832744FE27 -:1000900003C707008327C4FE2380E7008327C4FE2D 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+:1058E80000000000000000000000000000000000B0 +:1058F800430000000000000000000000000000005D +:10590800000000000000000000000000000000008F +:10591800A0F300808CD4008000000000BC4A018005 +:105928002C490180EC480180EC480180EC4801805A +:10593800EC480180EC480180EC480180EC4801808B +:10594800EC480180EC480180FFFFFFFFFFFFFFFFED +:10595800FFFFFFFFFFFF00000100415343494900DB +:10596800000000000000000000000000000000002F +:1059780000000000000000000000415343494900B6 +:10598800000000000000000000000000000000000F +:0C59980000000000000000000000000003 +:1059A800000000000000F03F00000000000024405C +:1059B800000000000000504308500180085001809A +:0859C800FFFFFFFF00000200D9 :040000058000000077 :00000001FF diff --git a/runtime/tests/simple/Makefile b/runtime/tests/simple/Makefile index db04672b..b862c64c 100644 --- a/runtime/tests/simple/Makefile +++ b/runtime/tests/simple/Makefile @@ -8,7 +8,7 @@ CP = $(RISCV_TOOLCHAIN_PATH)/bin/riscv32-unknown-elf-objcopy CFLAGS += -march=rv32im -mabi=ilp32 -O3 -Wl,-Bstatic,-T,$(VORTEX_RT_PATH)/linker/vx_link.ld CFLAGS += -nostartfiles -ffreestanding -fno-exceptions -Wl,--gc-sections -CFLAGS += -I$(VORTEX_RT_PATH)/include +CFLAGS += -I$(VORTEX_RT_PATH)/include -I../../../hw LDFLAGS += $(VORTEX_RT_PATH)/libvortexrt.a @@ -27,8 +27,11 @@ $(PROJECT).hex: $(PROJECT).elf $(PROJECT).elf: $(SRCS) $(CC) $(CFLAGS) $(SRCS) $(LDFLAGS) -o $(PROJECT).elf +run: $(PROJECT).hex + (cd ../../../hw/simulate/obj_dir && ./VVortex -f ../../../runtime/tests/simple/$(PROJECT).hex) + .depend: $(SRCS) $(CC) $(CFLAGS) -MM $^ > .depend; clean: - rm -rf *.elf *.hex *.dump .depend \ No newline at end of file + rm -rf *.elf *.hex *.dump .depend diff --git a/runtime/tests/simple/main.c b/runtime/tests/simple/main.c index 7c5c40ab..1d177987 100644 --- a/runtime/tests/simple/main.c +++ b/runtime/tests/simple/main.c @@ -3,6 +3,7 @@ #include #include #include +#include typedef struct @@ -100,7 +101,7 @@ int main() test_wsapwn(); vx_print_str("Shared Memory test\n"); - unsigned * ptr = (unsigned *) 0xFFFF0000; + unsigned * ptr = (unsigned *) SHARED_MEM_BASE_ADDR; unsigned value = 0; for (int i = 0; i < 5; i++) { @@ -112,7 +113,6 @@ int main() vx_print_str("-------------------\n"); value++; ptr++; - } vx_print_str("vx_spawn_warps mat_add_kernel\n"); diff --git a/runtime/tests/simple/tests.c b/runtime/tests/simple/tests.c index 3ad7860f..1efd0a3a 100644 --- a/runtime/tests/simple/tests.c +++ b/runtime/tests/simple/tests.c @@ -125,16 +125,4 @@ void intrinsics_tests() // Test wspawn vx_print_str("test_spawn\n"); test_wsapwn(); -} - - - - - - - - - - - - +} \ No newline at end of file diff --git a/runtime/tests/simple/vx_simple.dump b/runtime/tests/simple/vx_simple.dump index 9b2c4b73..9b62df87 100644 --- a/runtime/tests/simple/vx_simple.dump +++ b/runtime/tests/simple/vx_simple.dump @@ -12,17 +12,17 @@ Disassembly of section .init: 80000010: 684000ef jal ra,80000694 80000014: 00100513 li a0,1 80000018: 0005006b 0x5006b -8000001c: 0d818513 addi a0,gp,216 # 800048e0 <__malloc_max_total_mem> -80000020: 19018613 addi a2,gp,400 # 80004998 <__BSS_END__> +8000001c: cc418513 addi a0,gp,-828 # 800014cc +80000020: d2818613 addi a2,gp,-728 # 80001530 <__BSS_END__> 80000024: 40a60633 sub a2,a2,a0 80000028: 00000593 li a1,0 -8000002c: 381000ef jal ra,80000bac +8000002c: 289000ef jal ra,80000ab4 80000030: 00001517 auipc a0,0x1 -80000034: a8450513 addi a0,a0,-1404 # 80000ab4 <__libc_fini_array> -80000038: 239000ef jal ra,80000a70 -8000003c: 2d5000ef jal ra,80000b10 <__libc_init_array> +80000034: 98c50513 addi a0,a0,-1652 # 800009bc <__libc_fini_array> +80000038: 141000ef jal ra,80000978 +8000003c: 1dd000ef jal ra,80000a18 <__libc_init_array> 80000040: 008000ef jal ra,80000048
-80000044: 2410006f j 80000a84 +80000044: 1490006f j 8000098c Disassembly of section .text: @@ -38,8 +38,8 @@ Disassembly of section .text: 80000068: 0b512a23 sw s5,180(sp) 8000006c: 0b612823 sw s6,176(sp) 80000070: 66c000ef jal ra,800006dc -80000074: 80004537 lui a0,0x80004 -80000078: be850513 addi a0,a0,-1048 # 80003be8 <__BSS_END__+0xfffff250> +80000074: 80001537 lui a0,0x80001 +80000078: d4850513 addi a0,a0,-696 # 80000d48 <__global_pointer$+0xfffff540> 8000007c: 6d0000ef jal ra,8000074c 80000080: 02010493 addi s1,sp,32 80000084: 00048713 mv a4,s1 @@ -51,11 +51,11 @@ Disassembly of section .text: 8000009c: fed79ae3 bne a5,a3,80000090 800000a0: 00000413 li s0,0 800000a4: 00100713 li a4,1 -800000a8: 800049b7 lui s3,0x80004 +800000a8: 800019b7 lui s3,0x80001 800000ac: 02400913 li s2,36 800000b0: 0004a783 lw a5,0(s1) 800000b4: 00040593 mv a1,s0 -800000b8: c1498513 addi a0,s3,-1004 # 80003c14 <__BSS_END__+0xfffff27c> +800000b8: d7498513 addi a0,s3,-652 # 80000d74 <__global_pointer$+0xfffff56c> 800000bc: 00878663 beq a5,s0,800000c8 800000c0: 76c000ef jal ra,8000082c 800000c4: 00000713 li a4,0 @@ -63,72 +63,72 @@ Disassembly of section .text: 800000cc: 00448493 addi s1,s1,4 800000d0: ff2410e3 bne s0,s2,800000b0 800000d4: 16071e63 bnez a4,80000250 -800000d8: 80004537 lui a0,0x80004 -800000dc: c4850513 addi a0,a0,-952 # 80003c48 <__BSS_END__+0xfffff2b0> +800000d8: 80001537 lui a0,0x80001 +800000dc: da850513 addi a0,a0,-600 # 80000da8 <__global_pointer$+0xfffff5a0> 800000e0: 66c000ef jal ra,8000074c 800000e4: 264000ef jal ra,80000348 -800000e8: 80004537 lui a0,0x80004 -800000ec: c5850513 addi a0,a0,-936 # 80003c58 <__BSS_END__+0xfffff2c0> +800000e8: 80001537 lui a0,0x80001 +800000ec: db850513 addi a0,a0,-584 # 80000db8 <__global_pointer$+0xfffff5b0> 800000f0: 65c000ef jal ra,8000074c 800000f4: 00400513 li a0,4 800000f8: 5e4000ef jal ra,800006dc 800000fc: 2e4000ef jal ra,800003e0 80000100: 00100513 li a0,1 80000104: 5d8000ef jal ra,800006dc -80000108: 80004537 lui a0,0x80004 -8000010c: c6c50513 addi a0,a0,-916 # 80003c6c <__BSS_END__+0xfffff2d4> +80000108: 80001537 lui a0,0x80001 +8000010c: dcc50513 addi a0,a0,-564 # 80000dcc <__global_pointer$+0xfffff5c4> 80000110: 63c000ef jal ra,8000074c 80000114: 3a8000ef jal ra,800004bc -80000118: 80004537 lui a0,0x80004 -8000011c: c7c50513 addi a0,a0,-900 # 80003c7c <__BSS_END__+0xfffff2e4> -80000120: ffff0437 lui s0,0xffff0 +80000118: 80001537 lui a0,0x80001 +8000011c: ddc50513 addi a0,a0,-548 # 80000ddc <__global_pointer$+0xfffff5d4> +80000120: 6ffff437 lui s0,0x6ffff 80000124: 628000ef jal ra,8000074c 80000128: 00000493 li s1,0 -8000012c: 80004b37 lui s6,0x80004 -80000130: 80004ab7 lui s5,0x80004 -80000134: 80004a37 lui s4,0x80004 -80000138: 800049b7 lui s3,0x80004 -8000013c: 01440913 addi s2,s0,20 # ffff0014 <__BSS_END__+0x7ffeb67c> +8000012c: 80001b37 lui s6,0x80001 +80000130: 80001ab7 lui s5,0x80001 +80000134: 80001a37 lui s4,0x80001 +80000138: 800019b7 lui s3,0x80001 +8000013c: 01440913 addi s2,s0,20 # 6ffff014 <_start-0x10000fec> 80000140: 00942023 sw s1,0(s0) 80000144: 00040593 mv a1,s0 -80000148: c90b0513 addi a0,s6,-880 # 80003c90 <__BSS_END__+0xfffff2f8> +80000148: df0b0513 addi a0,s6,-528 # 80000df0 <__global_pointer$+0xfffff5e8> 8000014c: 6e0000ef jal ra,8000082c 80000150: 00048593 mv a1,s1 -80000154: c98a8513 addi a0,s5,-872 # 80003c98 <__BSS_END__+0xfffff300> +80000154: df8a8513 addi a0,s5,-520 # 80000df8 <__global_pointer$+0xfffff5f0> 80000158: 6d4000ef jal ra,8000082c 8000015c: 00048593 mv a1,s1 -80000160: caca0513 addi a0,s4,-852 # 80003cac <__BSS_END__+0xfffff314> +80000160: e0ca0513 addi a0,s4,-500 # 80000e0c <__global_pointer$+0xfffff604> 80000164: 6c8000ef jal ra,8000082c -80000168: cbc98513 addi a0,s3,-836 # 80003cbc <__BSS_END__+0xfffff324> +80000168: e1c98513 addi a0,s3,-484 # 80000e1c <__global_pointer$+0xfffff614> 8000016c: 00440413 addi s0,s0,4 80000170: 5dc000ef jal ra,8000074c 80000174: 00148493 addi s1,s1,1 80000178: fd2414e3 bne s0,s2,80000140 -8000017c: 80004537 lui a0,0x80004 -80000180: cd450513 addi a0,a0,-812 # 80003cd4 <__BSS_END__+0xfffff33c> +8000017c: 80001537 lui a0,0x80001 +80000180: e3450513 addi a0,a0,-460 # 80000e34 <__global_pointer$+0xfffff62c> 80000184: 5c8000ef jal ra,8000074c -80000188: 800047b7 lui a5,0x80004 -8000018c: 00878793 addi a5,a5,8 # 80004008 <__BSS_END__+0xfffff670> +80000188: 800017b7 lui a5,0x80001 +8000018c: 00878793 addi a5,a5,8 # 80001008 <__global_pointer$+0xfffff800> 80000190: 80000637 lui a2,0x80000 80000194: 00400713 li a4,4 80000198: 04078813 addi a6,a5,64 8000019c: 00c10693 addi a3,sp,12 -800001a0: 27860613 addi a2,a2,632 # 80000278 <__BSS_END__+0xffffb8e0> +800001a0: 27860613 addi a2,a2,632 # 80000278 <__global_pointer$+0xffffea70> 800001a4: 00400593 li a1,4 800001a8: 00400513 li a0,4 -800001ac: 0e818913 addi s2,gp,232 # 800048f0 +800001ac: cc818913 addi s2,gp,-824 # 800014d0 800001b0: 00f12623 sw a5,12(sp) 800001b4: 01012823 sw a6,16(sp) 800001b8: 00e12c23 sw a4,24(sp) 800001bc: 00e12e23 sw a4,28(sp) 800001c0: 01212a23 sw s2,20(sp) -800001c4: 788000ef jal ra,8000094c -800001c8: 80004537 lui a0,0x80004 -800001cc: cf450513 addi a0,a0,-780 # 80003cf4 <__BSS_END__+0xfffff35c> +800001c4: 744000ef jal ra,80000908 +800001c8: 80001537 lui a0,0x80001 +800001cc: e5450513 addi a0,a0,-428 # 80000e54 <__global_pointer$+0xfffff64c> 800001d0: 57c000ef jal ra,8000074c 800001d4: 00000493 li s1,0 -800001d8: 80004a37 lui s4,0x80004 -800001dc: 80004ab7 lui s5,0x80004 +800001d8: 80001a37 lui s4,0x80001 +800001dc: 80001ab7 lui s5,0x80001 800001e0: 00400993 li s3,4 800001e4: 00000413 li s0,0 800001e8: 01812783 lw a5,24(sp) @@ -139,11 +139,11 @@ Disassembly of section .text: 800001fc: 0007a503 lw a0,0(a5) 80000200: 00140413 addi s0,s0,1 80000204: 588000ef jal ra,8000078c -80000208: c94a0513 addi a0,s4,-876 # 80003c94 <__BSS_END__+0xfffff2fc> +80000208: df4a0513 addi a0,s4,-524 # 80000df4 <__global_pointer$+0xfffff5ec> 8000020c: 540000ef jal ra,8000074c 80000210: fd341ce3 bne s0,s3,800001e8 80000214: 00148493 addi s1,s1,1 -80000218: c10a8513 addi a0,s5,-1008 # 80003c10 <__BSS_END__+0xfffff278> +80000218: d70a8513 addi a0,s5,-656 # 80000d70 <__global_pointer$+0xfffff568> 8000021c: 530000ef jal ra,8000074c 80000220: fc8492e3 bne s1,s0,800001e4 80000224: 0cc12083 lw ra,204(sp) @@ -157,8 +157,8 @@ Disassembly of section .text: 80000244: 00000513 li a0,0 80000248: 0d010113 addi sp,sp,208 8000024c: 00008067 ret -80000250: 80004537 lui a0,0x80004 -80000254: c2050513 addi a0,a0,-992 # 80003c20 <__BSS_END__+0xfffff288> +80000250: 80001537 lui a0,0x80001 +80000254: d8050513 addi a0,a0,-640 # 80000d80 <__global_pointer$+0xfffff578> 80000258: 4f4000ef jal ra,8000074c 8000025c: e7dff06f j 800000d8 @@ -166,8 +166,8 @@ Disassembly of section .text: 80000260: 00000793 li a5,0 80000264: 00078863 beqz a5,80000274 80000268: 80001537 lui a0,0x80001 -8000026c: ab450513 addi a0,a0,-1356 # 80000ab4 <__BSS_END__+0xffffc11c> -80000270: 0010006f j 80000a70 +8000026c: 9bc50513 addi a0,a0,-1604 # 800009bc <__global_pointer$+0xfffff1b4> +80000270: 7080006f j 80000978 80000274: 00008067 ret 80000278 : @@ -204,7 +204,7 @@ Disassembly of section .text: 800002e8: 00112623 sw ra,12(sp) 800002ec: 410000ef jal ra,800006fc 800002f0: 00251713 slli a4,a0,0x2 -800002f4: 15018793 addi a5,gp,336 # 80004958 +800002f4: d0818793 addi a5,gp,-760 # 80001510 800002f8: 00e787b3 add a5,a5,a4 800002fc: 00a7a023 sw a0,0(a5) 80000300: 00051863 bnez a0,80000310 @@ -222,16 +222,16 @@ Disassembly of section .text: 80000328: 3e4000ef jal ra,8000070c 8000032c: 00c12083 lw ra,12(sp) 80000330: 00251713 slli a4,a0,0x2 -80000334: 88018793 addi a5,gp,-1920 # 80004088 +80000334: 88018793 addi a5,gp,-1920 # 80001088 80000338: 00e787b3 add a5,a5,a4 8000033c: 00a7a023 sw a0,0(a5) 80000340: 01010113 addi sp,sp,16 80000344: 00008067 ret 80000348 : -80000348: 80004537 lui a0,0x80004 +80000348: 80001537 lui a0,0x80001 8000034c: ff010113 addi sp,sp,-16 -80000350: d3050513 addi a0,a0,-720 # 80003d30 <__BSS_END__+0xfffff398> +80000350: e9050513 addi a0,a0,-368 # 80000e90 <__global_pointer$+0xfffff688> 80000354: 00112623 sw ra,12(sp) 80000358: 00812423 sw s0,8(sp) 8000035c: 00912223 sw s1,4(sp) @@ -239,7 +239,7 @@ Disassembly of section .text: 80000364: 00400513 li a0,4 80000368: 374000ef jal ra,800006dc 8000036c: 3a0000ef jal ra,8000070c -80000370: 88018413 addi s0,gp,-1920 # 80004088 +80000370: 88018413 addi s0,gp,-1920 # 80001088 80000374: 00251713 slli a4,a0,0x2 80000378: 00050793 mv a5,a0 8000037c: 00e40733 add a4,s0,a4 @@ -247,23 +247,23 @@ Disassembly of section .text: 80000384: 00f72023 sw a5,0(a4) 80000388: 354000ef jal ra,800006dc 8000038c: 00042503 lw a0,0(s0) -80000390: 800044b7 lui s1,0x80004 +80000390: 800014b7 lui s1,0x80001 80000394: 3f8000ef jal ra,8000078c -80000398: c1048513 addi a0,s1,-1008 # 80003c10 <__BSS_END__+0xfffff278> +80000398: d7048513 addi a0,s1,-656 # 80000d70 <__global_pointer$+0xfffff568> 8000039c: 3b0000ef jal ra,8000074c 800003a0: 00442503 lw a0,4(s0) 800003a4: 3e8000ef jal ra,8000078c -800003a8: c1048513 addi a0,s1,-1008 +800003a8: d7048513 addi a0,s1,-656 800003ac: 3a0000ef jal ra,8000074c 800003b0: 00842503 lw a0,8(s0) 800003b4: 3d8000ef jal ra,8000078c -800003b8: c1048513 addi a0,s1,-1008 +800003b8: d7048513 addi a0,s1,-656 800003bc: 390000ef jal ra,8000074c 800003c0: 00c42503 lw a0,12(s0) 800003c4: 3c8000ef jal ra,8000078c 800003c8: 00812403 lw s0,8(sp) 800003cc: 00c12083 lw ra,12(sp) -800003d0: c1048513 addi a0,s1,-1008 +800003d0: d7048513 addi a0,s1,-656 800003d4: 00412483 lw s1,4(sp) 800003d8: 01010113 addi sp,sp,16 800003dc: 3700006f j 8000074c @@ -282,7 +282,7 @@ Disassembly of section .text: 80000408: 00343513 sltiu a0,s0,3 8000040c: 2e0000ef jal ra,800006ec 80000410: 00200793 li a5,2 -80000414: 16018493 addi s1,gp,352 # 80004968 +80000414: d1818493 addi s1,gp,-744 # 80001520 80000418: 06f40863 beq s0,a5,80000488 8000041c: 00241413 slli s0,s0,0x2 80000420: 00848433 add s0,s1,s0 @@ -291,21 +291,21 @@ Disassembly of section .text: 8000042c: 2c8000ef jal ra,800006f4 80000430: 2c4000ef jal ra,800006f4 80000434: 0004a503 lw a0,0(s1) -80000438: 80004437 lui s0,0x80004 +80000438: 80001437 lui s0,0x80001 8000043c: 350000ef jal ra,8000078c -80000440: c1040513 addi a0,s0,-1008 # 80003c10 <__BSS_END__+0xfffff278> +80000440: d7040513 addi a0,s0,-656 # 80000d70 <__global_pointer$+0xfffff568> 80000444: 308000ef jal ra,8000074c 80000448: 0044a503 lw a0,4(s1) 8000044c: 340000ef jal ra,8000078c -80000450: c1040513 addi a0,s0,-1008 +80000450: d7040513 addi a0,s0,-656 80000454: 2f8000ef jal ra,8000074c 80000458: 0084a503 lw a0,8(s1) 8000045c: 330000ef jal ra,8000078c -80000460: c1040513 addi a0,s0,-1008 +80000460: d7040513 addi a0,s0,-656 80000464: 2e8000ef jal ra,8000074c 80000468: 00c4a503 lw a0,12(s1) 8000046c: 320000ef jal ra,8000078c -80000470: c1040513 addi a0,s0,-1008 +80000470: d7040513 addi a0,s0,-656 80000474: 00812403 lw s0,8(sp) 80000478: 00c12083 lw ra,12(sp) 8000047c: 00412483 lw s1,4(sp) @@ -316,7 +316,7 @@ Disassembly of section .text: 80000490: f9dff06f j 8000042c 80000494: 00144513 xori a0,s0,1 80000498: 254000ef jal ra,800006ec -8000049c: 16018493 addi s1,gp,352 # 80004968 +8000049c: d1818493 addi s1,gp,-744 # 80001520 800004a0: 00041863 bnez s0,800004b0 800004a4: 00a00793 li a5,10 800004a8: 00f4a023 sw a5,0(s1) @@ -328,36 +328,36 @@ Disassembly of section .text: 800004bc : 800004bc: 800005b7 lui a1,0x80000 800004c0: ff010113 addi sp,sp,-16 -800004c4: 2e458593 addi a1,a1,740 # 800002e4 <__BSS_END__+0xffffb94c> +800004c4: 2e458593 addi a1,a1,740 # 800002e4 <__global_pointer$+0xffffeadc> 800004c8: 00400513 li a0,4 800004cc: 00112623 sw ra,12(sp) 800004d0: 00812423 sw s0,8(sp) 800004d4: 00912223 sw s1,4(sp) 800004d8: 1fc000ef jal ra,800006d4 800004dc: 220000ef jal ra,800006fc -800004e0: 15018413 addi s0,gp,336 # 80004958 +800004e0: d0818413 addi s0,gp,-760 # 80001510 800004e4: 00251793 slli a5,a0,0x2 800004e8: 00f407b3 add a5,s0,a5 800004ec: 00a7a023 sw a0,0(a5) 800004f0: 04051c63 bnez a0,80000548 800004f4: 00042503 lw a0,0(s0) -800004f8: 800044b7 lui s1,0x80004 +800004f8: 800014b7 lui s1,0x80001 800004fc: 290000ef jal ra,8000078c -80000500: c1048513 addi a0,s1,-1008 # 80003c10 <__BSS_END__+0xfffff278> +80000500: d7048513 addi a0,s1,-656 # 80000d70 <__global_pointer$+0xfffff568> 80000504: 248000ef jal ra,8000074c 80000508: 00442503 lw a0,4(s0) 8000050c: 280000ef jal ra,8000078c -80000510: c1048513 addi a0,s1,-1008 +80000510: d7048513 addi a0,s1,-656 80000514: 238000ef jal ra,8000074c 80000518: 00842503 lw a0,8(s0) 8000051c: 270000ef jal ra,8000078c -80000520: c1048513 addi a0,s1,-1008 +80000520: d7048513 addi a0,s1,-656 80000524: 228000ef jal ra,8000074c 80000528: 00c42503 lw a0,12(s0) 8000052c: 260000ef jal ra,8000078c 80000530: 00812403 lw s0,8(sp) 80000534: 00c12083 lw ra,12(sp) -80000538: c1048513 addi a0,s1,-1008 +80000538: d7048513 addi a0,s1,-656 8000053c: 00412483 lw s1,4(sp) 80000540: 01010113 addi sp,sp,16 80000544: 2080006f j 8000074c @@ -366,9 +366,9 @@ Disassembly of section .text: 80000550: fa5ff06f j 800004f4 80000554 : -80000554: 80004537 lui a0,0x80004 +80000554: 80001537 lui a0,0x80001 80000558: ff010113 addi sp,sp,-16 -8000055c: d3050513 addi a0,a0,-720 # 80003d30 <__BSS_END__+0xfffff398> +8000055c: e9050513 addi a0,a0,-368 # 80000e90 <__global_pointer$+0xfffff688> 80000560: 00112623 sw ra,12(sp) 80000564: 00812423 sw s0,8(sp) 80000568: 00912223 sw s1,4(sp) @@ -376,7 +376,7 @@ Disassembly of section .text: 80000570: 00400513 li a0,4 80000574: 168000ef jal ra,800006dc 80000578: 194000ef jal ra,8000070c -8000057c: 88018493 addi s1,gp,-1920 # 80004088 +8000057c: 88018493 addi s1,gp,-1920 # 80001088 80000580: 00251713 slli a4,a0,0x2 80000584: 00050793 mv a5,a0 80000588: 00e48733 add a4,s1,a4 @@ -384,36 +384,36 @@ Disassembly of section .text: 80000590: 00f72023 sw a5,0(a4) 80000594: 148000ef jal ra,800006dc 80000598: 0004a503 lw a0,0(s1) -8000059c: 80004437 lui s0,0x80004 +8000059c: 80001437 lui s0,0x80001 800005a0: 1ec000ef jal ra,8000078c -800005a4: c1040513 addi a0,s0,-1008 # 80003c10 <__BSS_END__+0xfffff278> +800005a4: d7040513 addi a0,s0,-656 # 80000d70 <__global_pointer$+0xfffff568> 800005a8: 1a4000ef jal ra,8000074c 800005ac: 0044a503 lw a0,4(s1) 800005b0: 1dc000ef jal ra,8000078c -800005b4: c1040513 addi a0,s0,-1008 +800005b4: d7040513 addi a0,s0,-656 800005b8: 194000ef jal ra,8000074c 800005bc: 0084a503 lw a0,8(s1) 800005c0: 1cc000ef jal ra,8000078c -800005c4: c1040513 addi a0,s0,-1008 +800005c4: d7040513 addi a0,s0,-656 800005c8: 184000ef jal ra,8000074c 800005cc: 00c4a503 lw a0,12(s1) -800005d0: 15018493 addi s1,gp,336 # 80004958 +800005d0: d0818493 addi s1,gp,-760 # 80001510 800005d4: 1b8000ef jal ra,8000078c -800005d8: c1040513 addi a0,s0,-1008 +800005d8: d7040513 addi a0,s0,-656 800005dc: 170000ef jal ra,8000074c -800005e0: 80004537 lui a0,0x80004 -800005e4: c5850513 addi a0,a0,-936 # 80003c58 <__BSS_END__+0xfffff2c0> +800005e0: 80001537 lui a0,0x80001 +800005e4: db850513 addi a0,a0,-584 # 80000db8 <__global_pointer$+0xfffff5b0> 800005e8: 164000ef jal ra,8000074c 800005ec: 00400513 li a0,4 800005f0: 0ec000ef jal ra,800006dc 800005f4: dedff0ef jal ra,800003e0 800005f8: 00100513 li a0,1 800005fc: 0e0000ef jal ra,800006dc -80000600: 80004537 lui a0,0x80004 -80000604: d4050513 addi a0,a0,-704 # 80003d40 <__BSS_END__+0xfffff3a8> +80000600: 80001537 lui a0,0x80001 +80000604: ea050513 addi a0,a0,-352 # 80000ea0 <__global_pointer$+0xfffff698> 80000608: 144000ef jal ra,8000074c 8000060c: 800005b7 lui a1,0x80000 -80000610: 2e458593 addi a1,a1,740 # 800002e4 <__BSS_END__+0xffffb94c> +80000610: 2e458593 addi a1,a1,740 # 800002e4 <__global_pointer$+0xffffeadc> 80000614: 00400513 li a0,4 80000618: 0bc000ef jal ra,800006d4 8000061c: 0e0000ef jal ra,800006fc @@ -423,19 +423,19 @@ Disassembly of section .text: 8000062c: 04051a63 bnez a0,80000680 80000630: 0004a503 lw a0,0(s1) 80000634: 158000ef jal ra,8000078c -80000638: c1040513 addi a0,s0,-1008 +80000638: d7040513 addi a0,s0,-656 8000063c: 110000ef jal ra,8000074c 80000640: 0044a503 lw a0,4(s1) 80000644: 148000ef jal ra,8000078c -80000648: c1040513 addi a0,s0,-1008 +80000648: d7040513 addi a0,s0,-656 8000064c: 100000ef jal ra,8000074c 80000650: 0084a503 lw a0,8(s1) 80000654: 138000ef jal ra,8000078c -80000658: c1040513 addi a0,s0,-1008 +80000658: d7040513 addi a0,s0,-656 8000065c: 0f0000ef jal ra,8000074c 80000660: 00c4a503 lw a0,12(s1) 80000664: 128000ef jal ra,8000078c -80000668: c1040513 addi a0,s0,-1008 +80000668: d7040513 addi a0,s0,-656 8000066c: 00812403 lw s0,8(sp) 80000670: 00c12083 lw ra,12(sp) 80000674: 00412483 lw s1,4(sp) @@ -452,9 +452,9 @@ Disassembly of section .text: 80000694 : 80000694: 02502573 csrr a0,0x25 80000698: 0005006b 0x5006b -8000069c: 00004197 auipc gp,0x4 -800006a0: 16c18193 addi gp,gp,364 # 80004808 <__global_pointer$> -800006a4: f14025f3 csrr a1,mhartid +8000069c: 00001197 auipc gp,0x1 +800006a0: 16c18193 addi gp,gp,364 # 80001808 <__global_pointer$> +800006a4: 022025f3 csrr a1,0x22 800006a8: 00a59593 slli a1,a1,0xa 800006ac: 02002673 csrr a2,0x20 800006b0: 00261613 slli a2,a2,0x2 @@ -502,7 +502,7 @@ Disassembly of section .text: 80000710: 00008067 ret 80000714 : -80000714: f1402573 csrr a0,mhartid +80000714: 02202573 csrr a0,0x22 80000718: 00008067 ret 8000071c : @@ -548,7 +548,7 @@ Disassembly of section .text: 80000778: 00008067 ret 8000077c : -8000077c: 89018293 addi t0,gp,-1904 # 80004098 +8000077c: 89018293 addi t0,gp,-1904 # 80001098 80000780: 0002a283 lw t0,0(t0) 80000784: 00b2a023 sw a1,0(t0) 80000788: 00008067 ret @@ -562,10 +562,10 @@ Disassembly of section .text: 800007a0: 00f00793 li a5,15 800007a4: 00050493 mv s1,a0 800007a8: 04a7fc63 bgeu a5,a0,80000800 -800007ac: 80004937 lui s2,0x80004 +800007ac: 80001937 lui s2,0x80001 800007b0: 00000693 li a3,0 800007b4: 02000413 li s0,32 -800007b8: d8c90913 addi s2,s2,-628 # 80003d8c <__BSS_END__+0xfffff3f4> +800007b8: eec90913 addi s2,s2,-276 # 80000eec <__global_pointer$+0xfffff6e4> 800007bc: ffc40413 addi s0,s0,-4 800007c0: 0084d7b3 srl a5,s1,s0 800007c4: 00f7f793 andi a5,a5,15 @@ -583,9 +583,9 @@ Disassembly of section .text: 800007f4: 00012903 lw s2,0(sp) 800007f8: 01010113 addi sp,sp,16 800007fc: 00008067 ret -80000800: 800047b7 lui a5,0x80004 +80000800: 800017b7 lui a5,0x80001 80000804: 00251493 slli s1,a0,0x2 -80000808: d8c78793 addi a5,a5,-628 # 80003d8c <__BSS_END__+0xfffff3f4> +80000808: eec78793 addi a5,a5,-276 # 80000eec <__global_pointer$+0xfffff6e4> 8000080c: 00812403 lw s0,8(sp) 80000810: 009784b3 add s1,a5,s1 80000814: 0004a503 lw a0,0(s1) @@ -605,10 +605,10 @@ Disassembly of section .text: 80000844: f09ff0ef jal ra,8000074c 80000848: 00f00793 li a5,15 8000084c: 0687f063 bgeu a5,s0,800008ac -80000850: 80004937 lui s2,0x80004 +80000850: 80001937 lui s2,0x80001 80000854: 00000693 li a3,0 80000858: 02000493 li s1,32 -8000085c: d8c90913 addi s2,s2,-628 # 80003d8c <__BSS_END__+0xfffff3f4> +8000085c: eec90913 addi s2,s2,-276 # 80000eec <__global_pointer$+0xfffff6e4> 80000860: ffc48493 addi s1,s1,-4 80000864: 009457b3 srl a5,s0,s1 80000868: 00f7f793 andi a5,a5,15 @@ -624,12 +624,12 @@ Disassembly of section .text: 80000890: 00c12083 lw ra,12(sp) 80000894: 00412483 lw s1,4(sp) 80000898: 00012903 lw s2,0(sp) -8000089c: 80004537 lui a0,0x80004 -800008a0: c1050513 addi a0,a0,-1008 # 80003c10 <__BSS_END__+0xfffff278> +8000089c: 80001537 lui a0,0x80001 +800008a0: d7050513 addi a0,a0,-656 # 80000d70 <__global_pointer$+0xfffff568> 800008a4: 01010113 addi sp,sp,16 800008a8: ea5ff06f j 8000074c -800008ac: 800047b7 lui a5,0x80004 -800008b0: d8c78793 addi a5,a5,-628 # 80003d8c <__BSS_END__+0xfffff3f4> +800008ac: 800017b7 lui a5,0x80001 +800008b0: eec78793 addi a5,a5,-276 # 80000eec <__global_pointer$+0xfffff6e4> 800008b4: 00241413 slli s0,s0,0x2 800008b8: 00878433 add s0,a5,s0 800008bc: 00042503 lw a0,0(s0) @@ -637,4356 +637,656 @@ Disassembly of section .text: 800008c4: fc9ff06f j 8000088c 800008c8 : -800008c8: 1881a503 lw a0,392(gp) # 80004990 -800008cc: ff010113 addi sp,sp,-16 -800008d0: 00112623 sw ra,12(sp) -800008d4: e09ff0ef jal ra,800006dc -800008d8: 1741a503 lw a0,372(gp) # 8000497c -800008dc: 1781a783 lw a5,376(gp) # 80004980 -800008e0: 000780e7 jalr a5 -800008e4: e19ff0ef jal ra,800006fc -800008e8: 00c12083 lw ra,12(sp) -800008ec: 00153513 seqz a0,a0 -800008f0: 01010113 addi sp,sp,16 -800008f4: de9ff06f j 800006dc +800008c8: ff010113 addi sp,sp,-16 +800008cc: 00812423 sw s0,8(sp) +800008d0: cc41a783 lw a5,-828(gp) # 800014cc +800008d4: 00112623 sw ra,12(sp) +800008d8: 0087a503 lw a0,8(a5) +800008dc: e01ff0ef jal ra,800006dc +800008e0: cc41a783 lw a5,-828(gp) # 800014cc +800008e4: 0047a503 lw a0,4(a5) +800008e8: 0007a783 lw a5,0(a5) +800008ec: 000780e7 jalr a5 +800008f0: e0dff0ef jal ra,800006fc +800008f4: 00812403 lw s0,8(sp) +800008f8: 00c12083 lw ra,12(sp) +800008fc: 00153513 seqz a0,a0 +80000900: 01010113 addi sp,sp,16 +80000904: dd9ff06f j 800006dc -800008f8 : -800008f8: 17c1a503 lw a0,380(gp) # 80004984 -800008fc: ff010113 addi sp,sp,-16 -80000900: 00112623 sw ra,12(sp) -80000904: 00812423 sw s0,8(sp) -80000908: dd5ff0ef jal ra,800006dc -8000090c: e01ff0ef jal ra,8000070c -80000910: 00050413 mv s0,a0 -80000914: df1ff0ef jal ra,80000704 -80000918: 1841a583 lw a1,388(gp) # 8000498c -8000091c: 00050693 mv a3,a0 -80000920: 1801a503 lw a0,384(gp) # 80004988 -80000924: 1701a783 lw a5,368(gp) # 80004978 -80000928: 00040613 mv a2,s0 -8000092c: 00000713 li a4,0 -80000930: 000780e7 jalr a5 -80000934: dc9ff0ef jal ra,800006fc -80000938: 00812403 lw s0,8(sp) -8000093c: 00c12083 lw ra,12(sp) -80000940: 00153513 seqz a0,a0 -80000944: 01010113 addi sp,sp,16 -80000948: d95ff06f j 800006dc +80000908 : +80000908: fe010113 addi sp,sp,-32 +8000090c: 00410793 addi a5,sp,4 +80000910: 00812c23 sw s0,24(sp) +80000914: ccf1a223 sw a5,-828(gp) # 800014cc +80000918: 00112e23 sw ra,28(sp) +8000091c: 00c12223 sw a2,4(sp) +80000920: 00d12423 sw a3,8(sp) +80000924: 00b12623 sw a1,12(sp) +80000928: 00100793 li a5,1 +8000092c: 00a7dc63 bge a5,a0,80000944 +80000930: 800015b7 lui a1,0x80001 +80000934: 8c858593 addi a1,a1,-1848 # 800008c8 <__global_pointer$+0xfffff0c0> +80000938: d9dff0ef jal ra,800006d4 +8000093c: cc41a783 lw a5,-828(gp) # 800014cc +80000940: 0087a583 lw a1,8(a5) +80000944: 00058513 mv a0,a1 +80000948: d95ff0ef jal ra,800006dc +8000094c: cc41a783 lw a5,-828(gp) # 800014cc +80000950: 0047a503 lw a0,4(a5) +80000954: 0007a783 lw a5,0(a5) +80000958: 000780e7 jalr a5 +8000095c: da1ff0ef jal ra,800006fc +80000960: 00153513 seqz a0,a0 +80000964: d79ff0ef jal ra,800006dc +80000968: 01c12083 lw ra,28(sp) +8000096c: 01812403 lw s0,24(sp) +80000970: 02010113 addi sp,sp,32 +80000974: 00008067 ret -8000094c : -8000094c: ff010113 addi sp,sp,-16 -80000950: 00812423 sw s0,8(sp) -80000954: 00912223 sw s1,4(sp) -80000958: 01212023 sw s2,0(sp) -8000095c: 00112623 sw ra,12(sp) -80000960: 16c1ac23 sw a2,376(gp) # 80004980 -80000964: 16d1aa23 sw a3,372(gp) # 8000497c -80000968: 18b1a423 sw a1,392(gp) # 80004990 -8000096c: 00100793 li a5,1 -80000970: 00a7da63 bge a5,a0,80000984 -80000974: 800015b7 lui a1,0x80001 -80000978: 8c858593 addi a1,a1,-1848 # 800008c8 <__BSS_END__+0xffffbf30> -8000097c: d59ff0ef jal ra,800006d4 -80000980: 1881a583 lw a1,392(gp) # 80004990 -80000984: 00058513 mv a0,a1 -80000988: d55ff0ef jal ra,800006dc -8000098c: 1741a503 lw a0,372(gp) # 8000497c -80000990: 1781a783 lw a5,376(gp) # 80004980 -80000994: 000780e7 jalr a5 -80000998: d65ff0ef jal ra,800006fc -8000099c: 00812403 lw s0,8(sp) -800009a0: 00c12083 lw ra,12(sp) -800009a4: 00412483 lw s1,4(sp) -800009a8: 00012903 lw s2,0(sp) -800009ac: 00153513 seqz a0,a0 -800009b0: 01010113 addi sp,sp,16 -800009b4: d29ff06f j 800006dc +80000978 : +80000978: 00050593 mv a1,a0 +8000097c: 00000693 li a3,0 +80000980: 00000613 li a2,0 +80000984: 00000513 li a0,0 +80000988: 2080006f j 80000b90 <__register_exitproc> -800009b8 : -800009b8: 00852683 lw a3,8(a0) -800009bc: 00100713 li a4,1 -800009c0: 0ad76263 bltu a4,a3,80000a64 -800009c4: 00050793 mv a5,a0 -800009c8: 00052503 lw a0,0(a0) -800009cc: fe010113 addi sp,sp,-32 -800009d0: 0047a683 lw a3,4(a5) -800009d4: 00812c23 sw s0,24(sp) -800009d8: 00912a23 sw s1,20(sp) -800009dc: 01212823 sw s2,16(sp) -800009e0: 01312623 sw s3,12(sp) -800009e4: 00112e23 sw ra,28(sp) -800009e8: 16a1ae23 sw a0,380(gp) # 80004984 -800009ec: 18f1a223 sw a5,388(gp) # 8000498c -800009f0: 16b1a823 sw a1,368(gp) # 80004978 -800009f4: 18c1a023 sw a2,384(gp) # 80004988 -800009f8: 04d76a63 bltu a4,a3,80000a4c -800009fc: ce1ff0ef jal ra,800006dc -80000a00: d0dff0ef jal ra,8000070c -80000a04: 00050413 mv s0,a0 -80000a08: cfdff0ef jal ra,80000704 -80000a0c: 1841a583 lw a1,388(gp) # 8000498c -80000a10: 1701a783 lw a5,368(gp) # 80004978 -80000a14: 00050693 mv a3,a0 -80000a18: 1801a503 lw a0,384(gp) # 80004988 -80000a1c: 00040613 mv a2,s0 -80000a20: 00000713 li a4,0 -80000a24: 000780e7 jalr a5 -80000a28: cd5ff0ef jal ra,800006fc -80000a2c: 01812403 lw s0,24(sp) -80000a30: 01c12083 lw ra,28(sp) -80000a34: 01412483 lw s1,20(sp) -80000a38: 01012903 lw s2,16(sp) -80000a3c: 00c12983 lw s3,12(sp) -80000a40: 00153513 seqz a0,a0 -80000a44: 02010113 addi sp,sp,32 -80000a48: c95ff06f j 800006dc -80000a4c: 800015b7 lui a1,0x80001 -80000a50: 00068513 mv a0,a3 -80000a54: 8f858593 addi a1,a1,-1800 # 800008f8 <__BSS_END__+0xffffbf60> -80000a58: c7dff0ef jal ra,800006d4 -80000a5c: 17c1a503 lw a0,380(gp) # 80004984 -80000a60: f9dff06f j 800009fc -80000a64: 80004537 lui a0,0x80004 -80000a68: dcc50513 addi a0,a0,-564 # 80003dcc <__BSS_END__+0xfffff434> -80000a6c: 2ec0006f j 80000d58 +8000098c : +8000098c: ff010113 addi sp,sp,-16 +80000990: 00000593 li a1,0 +80000994: 00812423 sw s0,8(sp) +80000998: 00112623 sw ra,12(sp) +8000099c: 00050413 mv s0,a0 +800009a0: 288000ef jal ra,80000c28 <__call_exitprocs> +800009a4: cc01a503 lw a0,-832(gp) # 800014c8 <_global_impure_ptr> +800009a8: 03c52783 lw a5,60(a0) +800009ac: 00078463 beqz a5,800009b4 +800009b0: 000780e7 jalr a5 +800009b4: 00040513 mv a0,s0 +800009b8: cd5ff0ef jal ra,8000068c <_exit> -80000a70 : -80000a70: 00050593 mv a1,a0 -80000a74: 00000693 li a3,0 -80000a78: 00000613 li a2,0 -80000a7c: 00000513 li a0,0 -80000a80: 3700006f j 80000df0 <__register_exitproc> +800009bc <__libc_fini_array>: +800009bc: ff010113 addi sp,sp,-16 +800009c0: 00812423 sw s0,8(sp) +800009c4: 800017b7 lui a5,0x80001 +800009c8: 80001437 lui s0,0x80001 +800009cc: 00440413 addi s0,s0,4 # 80001004 <__global_pointer$+0xfffff7fc> +800009d0: 00478793 addi a5,a5,4 # 80001004 <__global_pointer$+0xfffff7fc> +800009d4: 408787b3 sub a5,a5,s0 +800009d8: 00912223 sw s1,4(sp) +800009dc: 00112623 sw ra,12(sp) +800009e0: 4027d493 srai s1,a5,0x2 +800009e4: 02048063 beqz s1,80000a04 <__libc_fini_array+0x48> +800009e8: ffc78793 addi a5,a5,-4 +800009ec: 00878433 add s0,a5,s0 +800009f0: 00042783 lw a5,0(s0) +800009f4: fff48493 addi s1,s1,-1 +800009f8: ffc40413 addi s0,s0,-4 +800009fc: 000780e7 jalr a5 +80000a00: fe0498e3 bnez s1,800009f0 <__libc_fini_array+0x34> +80000a04: 00c12083 lw ra,12(sp) +80000a08: 00812403 lw s0,8(sp) +80000a0c: 00412483 lw s1,4(sp) +80000a10: 01010113 addi sp,sp,16 +80000a14: 00008067 ret -80000a84 : -80000a84: ff010113 addi sp,sp,-16 -80000a88: 00000593 li a1,0 -80000a8c: 00812423 sw s0,8(sp) -80000a90: 00112623 sw ra,12(sp) -80000a94: 00050413 mv s0,a0 -80000a98: 3f0000ef jal ra,80000e88 <__call_exitprocs> -80000a9c: 0c81a503 lw a0,200(gp) # 800048d0 <_global_impure_ptr> -80000aa0: 03c52783 lw a5,60(a0) -80000aa4: 00078463 beqz a5,80000aac -80000aa8: 000780e7 jalr a5 -80000aac: 00040513 mv a0,s0 -80000ab0: bddff0ef jal ra,8000068c <_exit> +80000a18 <__libc_init_array>: +80000a18: ff010113 addi sp,sp,-16 +80000a1c: 00812423 sw s0,8(sp) +80000a20: 01212023 sw s2,0(sp) +80000a24: 80001437 lui s0,0x80001 +80000a28: 80001937 lui s2,0x80001 +80000a2c: 00040793 mv a5,s0 +80000a30: 00090913 mv s2,s2 +80000a34: 40f90933 sub s2,s2,a5 +80000a38: 00112623 sw ra,12(sp) +80000a3c: 00912223 sw s1,4(sp) +80000a40: 40295913 srai s2,s2,0x2 +80000a44: 02090063 beqz s2,80000a64 <__libc_init_array+0x4c> +80000a48: 00040413 mv s0,s0 +80000a4c: 00000493 li s1,0 +80000a50: 00042783 lw a5,0(s0) # 80001000 <__global_pointer$+0xfffff7f8> +80000a54: 00148493 addi s1,s1,1 +80000a58: 00440413 addi s0,s0,4 +80000a5c: 000780e7 jalr a5 +80000a60: fe9918e3 bne s2,s1,80000a50 <__libc_init_array+0x38> +80000a64: 80001437 lui s0,0x80001 +80000a68: 80001937 lui s2,0x80001 +80000a6c: 00040793 mv a5,s0 +80000a70: 00490913 addi s2,s2,4 # 80001004 <__global_pointer$+0xfffff7fc> +80000a74: 40f90933 sub s2,s2,a5 +80000a78: 40295913 srai s2,s2,0x2 +80000a7c: 02090063 beqz s2,80000a9c <__libc_init_array+0x84> +80000a80: 00040413 mv s0,s0 +80000a84: 00000493 li s1,0 +80000a88: 00042783 lw a5,0(s0) # 80001000 <__global_pointer$+0xfffff7f8> +80000a8c: 00148493 addi s1,s1,1 +80000a90: 00440413 addi s0,s0,4 +80000a94: 000780e7 jalr a5 +80000a98: fe9918e3 bne s2,s1,80000a88 <__libc_init_array+0x70> +80000a9c: 00c12083 lw ra,12(sp) +80000aa0: 00812403 lw s0,8(sp) +80000aa4: 00412483 lw s1,4(sp) +80000aa8: 00012903 lw s2,0(sp) +80000aac: 01010113 addi sp,sp,16 +80000ab0: 00008067 ret -80000ab4 <__libc_fini_array>: -80000ab4: ff010113 addi sp,sp,-16 -80000ab8: 00812423 sw s0,8(sp) -80000abc: 800047b7 lui a5,0x80004 -80000ac0: 80004437 lui s0,0x80004 -80000ac4: 00440413 addi s0,s0,4 # 80004004 <__BSS_END__+0xfffff66c> -80000ac8: 00478793 addi a5,a5,4 # 80004004 <__BSS_END__+0xfffff66c> -80000acc: 408787b3 sub a5,a5,s0 -80000ad0: 00912223 sw s1,4(sp) -80000ad4: 00112623 sw ra,12(sp) -80000ad8: 4027d493 srai s1,a5,0x2 -80000adc: 02048063 beqz s1,80000afc <__libc_fini_array+0x48> -80000ae0: ffc78793 addi a5,a5,-4 -80000ae4: 00878433 add s0,a5,s0 -80000ae8: 00042783 lw a5,0(s0) -80000aec: fff48493 addi s1,s1,-1 -80000af0: ffc40413 addi s0,s0,-4 -80000af4: 000780e7 jalr a5 -80000af8: fe0498e3 bnez s1,80000ae8 <__libc_fini_array+0x34> -80000afc: 00c12083 lw ra,12(sp) -80000b00: 00812403 lw s0,8(sp) -80000b04: 00412483 lw s1,4(sp) -80000b08: 01010113 addi sp,sp,16 -80000b0c: 00008067 ret +80000ab4 : +80000ab4: 00f00313 li t1,15 +80000ab8: 00050713 mv a4,a0 +80000abc: 02c37e63 bgeu t1,a2,80000af8 +80000ac0: 00f77793 andi a5,a4,15 +80000ac4: 0a079063 bnez a5,80000b64 +80000ac8: 08059263 bnez a1,80000b4c +80000acc: ff067693 andi a3,a2,-16 +80000ad0: 00f67613 andi a2,a2,15 +80000ad4: 00e686b3 add a3,a3,a4 +80000ad8: 00b72023 sw a1,0(a4) +80000adc: 00b72223 sw a1,4(a4) +80000ae0: 00b72423 sw a1,8(a4) +80000ae4: 00b72623 sw a1,12(a4) +80000ae8: 01070713 addi a4,a4,16 +80000aec: fed766e3 bltu a4,a3,80000ad8 +80000af0: 00061463 bnez a2,80000af8 +80000af4: 00008067 ret +80000af8: 40c306b3 sub a3,t1,a2 +80000afc: 00269693 slli a3,a3,0x2 +80000b00: 00000297 auipc t0,0x0 +80000b04: 005686b3 add a3,a3,t0 +80000b08: 00c68067 jr 12(a3) +80000b0c: 00b70723 sb a1,14(a4) +80000b10: 00b706a3 sb a1,13(a4) +80000b14: 00b70623 sb a1,12(a4) +80000b18: 00b705a3 sb a1,11(a4) +80000b1c: 00b70523 sb a1,10(a4) +80000b20: 00b704a3 sb a1,9(a4) +80000b24: 00b70423 sb a1,8(a4) +80000b28: 00b703a3 sb a1,7(a4) +80000b2c: 00b70323 sb a1,6(a4) +80000b30: 00b702a3 sb a1,5(a4) +80000b34: 00b70223 sb a1,4(a4) +80000b38: 00b701a3 sb a1,3(a4) +80000b3c: 00b70123 sb a1,2(a4) +80000b40: 00b700a3 sb a1,1(a4) +80000b44: 00b70023 sb a1,0(a4) +80000b48: 00008067 ret +80000b4c: 0ff5f593 andi a1,a1,255 +80000b50: 00859693 slli a3,a1,0x8 +80000b54: 00d5e5b3 or a1,a1,a3 +80000b58: 01059693 slli a3,a1,0x10 +80000b5c: 00d5e5b3 or a1,a1,a3 +80000b60: f6dff06f j 80000acc +80000b64: 00279693 slli a3,a5,0x2 +80000b68: 00000297 auipc t0,0x0 +80000b6c: 005686b3 add a3,a3,t0 +80000b70: 00008293 mv t0,ra +80000b74: fa0680e7 jalr -96(a3) +80000b78: 00028093 mv ra,t0 +80000b7c: ff078793 addi a5,a5,-16 +80000b80: 40f70733 sub a4,a4,a5 +80000b84: 00f60633 add a2,a2,a5 +80000b88: f6c378e3 bgeu t1,a2,80000af8 +80000b8c: f3dff06f j 80000ac8 -80000b10 <__libc_init_array>: -80000b10: ff010113 addi sp,sp,-16 -80000b14: 00812423 sw s0,8(sp) -80000b18: 01212023 sw s2,0(sp) -80000b1c: 80004437 lui s0,0x80004 -80000b20: 80004937 lui s2,0x80004 -80000b24: 00040793 mv a5,s0 -80000b28: 00090913 mv s2,s2 -80000b2c: 40f90933 sub s2,s2,a5 -80000b30: 00112623 sw ra,12(sp) -80000b34: 00912223 sw s1,4(sp) -80000b38: 40295913 srai s2,s2,0x2 -80000b3c: 02090063 beqz s2,80000b5c <__libc_init_array+0x4c> -80000b40: 00040413 mv s0,s0 -80000b44: 00000493 li s1,0 -80000b48: 00042783 lw a5,0(s0) # 80004000 <__BSS_END__+0xfffff668> -80000b4c: 00148493 addi s1,s1,1 -80000b50: 00440413 addi s0,s0,4 -80000b54: 000780e7 jalr a5 -80000b58: fe9918e3 bne s2,s1,80000b48 <__libc_init_array+0x38> -80000b5c: 80004437 lui s0,0x80004 -80000b60: 80004937 lui s2,0x80004 -80000b64: 00040793 mv a5,s0 -80000b68: 00490913 addi s2,s2,4 # 80004004 <__BSS_END__+0xfffff66c> -80000b6c: 40f90933 sub s2,s2,a5 -80000b70: 40295913 srai s2,s2,0x2 -80000b74: 02090063 beqz s2,80000b94 <__libc_init_array+0x84> -80000b78: 00040413 mv s0,s0 -80000b7c: 00000493 li s1,0 -80000b80: 00042783 lw a5,0(s0) # 80004000 <__BSS_END__+0xfffff668> -80000b84: 00148493 addi s1,s1,1 -80000b88: 00440413 addi s0,s0,4 -80000b8c: 000780e7 jalr a5 -80000b90: fe9918e3 bne s2,s1,80000b80 <__libc_init_array+0x70> -80000b94: 00c12083 lw ra,12(sp) -80000b98: 00812403 lw s0,8(sp) -80000b9c: 00412483 lw s1,4(sp) -80000ba0: 00012903 lw s2,0(sp) -80000ba4: 01010113 addi sp,sp,16 -80000ba8: 00008067 ret - -80000bac : -80000bac: 00f00313 li t1,15 -80000bb0: 00050713 mv a4,a0 -80000bb4: 02c37e63 bgeu t1,a2,80000bf0 -80000bb8: 00f77793 andi a5,a4,15 -80000bbc: 0a079063 bnez a5,80000c5c -80000bc0: 08059263 bnez a1,80000c44 -80000bc4: ff067693 andi a3,a2,-16 -80000bc8: 00f67613 andi a2,a2,15 -80000bcc: 00e686b3 add a3,a3,a4 -80000bd0: 00b72023 sw a1,0(a4) -80000bd4: 00b72223 sw a1,4(a4) -80000bd8: 00b72423 sw a1,8(a4) -80000bdc: 00b72623 sw a1,12(a4) -80000be0: 01070713 addi a4,a4,16 -80000be4: fed766e3 bltu a4,a3,80000bd0 -80000be8: 00061463 bnez a2,80000bf0 +80000b90 <__register_exitproc>: +80000b90: cc01a703 lw a4,-832(gp) # 800014c8 <_global_impure_ptr> +80000b94: 14872783 lw a5,328(a4) +80000b98: 04078c63 beqz a5,80000bf0 <__register_exitproc+0x60> +80000b9c: 0047a703 lw a4,4(a5) +80000ba0: 01f00813 li a6,31 +80000ba4: 06e84e63 blt a6,a4,80000c20 <__register_exitproc+0x90> +80000ba8: 00271813 slli a6,a4,0x2 +80000bac: 02050663 beqz a0,80000bd8 <__register_exitproc+0x48> +80000bb0: 01078333 add t1,a5,a6 +80000bb4: 08c32423 sw a2,136(t1) +80000bb8: 1887a883 lw a7,392(a5) +80000bbc: 00100613 li a2,1 +80000bc0: 00e61633 sll a2,a2,a4 +80000bc4: 00c8e8b3 or a7,a7,a2 +80000bc8: 1917a423 sw a7,392(a5) +80000bcc: 10d32423 sw a3,264(t1) +80000bd0: 00200693 li a3,2 +80000bd4: 02d50463 beq a0,a3,80000bfc <__register_exitproc+0x6c> +80000bd8: 00170713 addi a4,a4,1 +80000bdc: 00e7a223 sw a4,4(a5) +80000be0: 010787b3 add a5,a5,a6 +80000be4: 00b7a423 sw a1,8(a5) +80000be8: 00000513 li a0,0 80000bec: 00008067 ret -80000bf0: 40c306b3 sub a3,t1,a2 -80000bf4: 00269693 slli a3,a3,0x2 -80000bf8: 00000297 auipc t0,0x0 -80000bfc: 005686b3 add a3,a3,t0 -80000c00: 00c68067 jr 12(a3) -80000c04: 00b70723 sb a1,14(a4) -80000c08: 00b706a3 sb a1,13(a4) -80000c0c: 00b70623 sb a1,12(a4) -80000c10: 00b705a3 sb a1,11(a4) -80000c14: 00b70523 sb a1,10(a4) -80000c18: 00b704a3 sb a1,9(a4) -80000c1c: 00b70423 sb a1,8(a4) -80000c20: 00b703a3 sb a1,7(a4) -80000c24: 00b70323 sb a1,6(a4) -80000c28: 00b702a3 sb a1,5(a4) -80000c2c: 00b70223 sb a1,4(a4) -80000c30: 00b701a3 sb a1,3(a4) -80000c34: 00b70123 sb a1,2(a4) -80000c38: 00b700a3 sb a1,1(a4) -80000c3c: 00b70023 sb a1,0(a4) -80000c40: 00008067 ret -80000c44: 0ff5f593 andi a1,a1,255 -80000c48: 00859693 slli a3,a1,0x8 -80000c4c: 00d5e5b3 or a1,a1,a3 -80000c50: 01059693 slli a3,a1,0x10 -80000c54: 00d5e5b3 or a1,a1,a3 -80000c58: f6dff06f j 80000bc4 -80000c5c: 00279693 slli a3,a5,0x2 -80000c60: 00000297 auipc t0,0x0 -80000c64: 005686b3 add a3,a3,t0 -80000c68: 00008293 mv t0,ra -80000c6c: fa0680e7 jalr -96(a3) -80000c70: 00028093 mv ra,t0 -80000c74: ff078793 addi a5,a5,-16 -80000c78: 40f70733 sub a4,a4,a5 -80000c7c: 00f60633 add a2,a2,a5 -80000c80: f6c378e3 bgeu t1,a2,80000bf0 -80000c84: f3dff06f j 80000bc0 +80000bf0: 14c70793 addi a5,a4,332 +80000bf4: 14f72423 sw a5,328(a4) +80000bf8: fa5ff06f j 80000b9c <__register_exitproc+0xc> +80000bfc: 18c7a683 lw a3,396(a5) +80000c00: 00170713 addi a4,a4,1 +80000c04: 00e7a223 sw a4,4(a5) +80000c08: 00c6e633 or a2,a3,a2 +80000c0c: 18c7a623 sw a2,396(a5) +80000c10: 010787b3 add a5,a5,a6 +80000c14: 00b7a423 sw a1,8(a5) +80000c18: 00000513 li a0,0 +80000c1c: 00008067 ret +80000c20: fff00513 li a0,-1 +80000c24: 00008067 ret -80000c88 <_puts_r>: -80000c88: fc010113 addi sp,sp,-64 -80000c8c: 02812c23 sw s0,56(sp) -80000c90: 00050413 mv s0,a0 -80000c94: 00058513 mv a0,a1 -80000c98: 02912a23 sw s1,52(sp) -80000c9c: 02112e23 sw ra,60(sp) -80000ca0: 00058493 mv s1,a1 -80000ca4: 0c0000ef jal ra,80000d64 -80000ca8: 800047b7 lui a5,0x80004 -80000cac: c1078793 addi a5,a5,-1008 # 80003c10 <__BSS_END__+0xfffff278> -80000cb0: 02f12423 sw a5,40(sp) -80000cb4: 00100793 li a5,1 -80000cb8: 02f12623 sw a5,44(sp) -80000cbc: 03842703 lw a4,56(s0) -80000cc0: 02010793 addi a5,sp,32 -80000cc4: 00150693 addi a3,a0,1 -80000cc8: 00f12a23 sw a5,20(sp) -80000ccc: 00200793 li a5,2 -80000cd0: 02912023 sw s1,32(sp) -80000cd4: 02a12223 sw a0,36(sp) -80000cd8: 00d12e23 sw a3,28(sp) -80000cdc: 00f12c23 sw a5,24(sp) -80000ce0: 00842583 lw a1,8(s0) -80000ce4: 06070063 beqz a4,80000d44 <_puts_r+0xbc> -80000ce8: 00c59783 lh a5,12(a1) -80000cec: 01279713 slli a4,a5,0x12 -80000cf0: 02074263 bltz a4,80000d14 <_puts_r+0x8c> -80000cf4: 0645a703 lw a4,100(a1) -80000cf8: 000026b7 lui a3,0x2 -80000cfc: 00d7e7b3 or a5,a5,a3 -80000d00: ffffe6b7 lui a3,0xffffe -80000d04: fff68693 addi a3,a3,-1 # ffffdfff <__BSS_END__+0x7fff9667> -80000d08: 00d77733 and a4,a4,a3 -80000d0c: 00f59623 sh a5,12(a1) -80000d10: 06e5a223 sw a4,100(a1) -80000d14: 01410613 addi a2,sp,20 -80000d18: 00040513 mv a0,s0 -80000d1c: 5e8000ef jal ra,80001304 <__sfvwrite_r> -80000d20: 03c12083 lw ra,60(sp) -80000d24: 03812403 lw s0,56(sp) -80000d28: 00a03533 snez a0,a0 -80000d2c: 40a00533 neg a0,a0 -80000d30: ff557513 andi a0,a0,-11 -80000d34: 03412483 lw s1,52(sp) -80000d38: 00a50513 addi a0,a0,10 -80000d3c: 04010113 addi sp,sp,64 -80000d40: 00008067 ret -80000d44: 00040513 mv a0,s0 -80000d48: 00b12623 sw a1,12(sp) -80000d4c: 578000ef jal ra,800012c4 <__sinit> -80000d50: 00c12583 lw a1,12(sp) -80000d54: f95ff06f j 80000ce8 <_puts_r+0x60> - -80000d58 : -80000d58: 00050593 mv a1,a0 -80000d5c: 0cc1a503 lw a0,204(gp) # 800048d4 <_impure_ptr> -80000d60: f29ff06f j 80000c88 <_puts_r> - -80000d64 : -80000d64: 00357793 andi a5,a0,3 -80000d68: 00050713 mv a4,a0 -80000d6c: 04079c63 bnez a5,80000dc4 -80000d70: 7f7f86b7 lui a3,0x7f7f8 -80000d74: f7f68693 addi a3,a3,-129 # 7f7f7f7f <_start-0x808081> -80000d78: fff00593 li a1,-1 -80000d7c: 00072603 lw a2,0(a4) -80000d80: 00470713 addi a4,a4,4 -80000d84: 00d677b3 and a5,a2,a3 -80000d88: 00d787b3 add a5,a5,a3 -80000d8c: 00c7e7b3 or a5,a5,a2 -80000d90: 00d7e7b3 or a5,a5,a3 -80000d94: feb784e3 beq a5,a1,80000d7c -80000d98: ffc74683 lbu a3,-4(a4) -80000d9c: ffd74603 lbu a2,-3(a4) -80000da0: ffe74783 lbu a5,-2(a4) -80000da4: 40a70733 sub a4,a4,a0 -80000da8: 04068063 beqz a3,80000de8 -80000dac: 02060a63 beqz a2,80000de0 -80000db0: 00f03533 snez a0,a5 -80000db4: 00e50533 add a0,a0,a4 -80000db8: ffe50513 addi a0,a0,-2 -80000dbc: 00008067 ret -80000dc0: fa0688e3 beqz a3,80000d70 -80000dc4: 00074783 lbu a5,0(a4) -80000dc8: 00170713 addi a4,a4,1 -80000dcc: 00377693 andi a3,a4,3 -80000dd0: fe0798e3 bnez a5,80000dc0 -80000dd4: 40a70733 sub a4,a4,a0 -80000dd8: fff70513 addi a0,a4,-1 -80000ddc: 00008067 ret -80000de0: ffd70513 addi a0,a4,-3 -80000de4: 00008067 ret -80000de8: ffc70513 addi a0,a4,-4 -80000dec: 00008067 ret - -80000df0 <__register_exitproc>: -80000df0: 0c81a703 lw a4,200(gp) # 800048d0 <_global_impure_ptr> -80000df4: 14872783 lw a5,328(a4) -80000df8: 04078c63 beqz a5,80000e50 <__register_exitproc+0x60> -80000dfc: 0047a703 lw a4,4(a5) -80000e00: 01f00813 li a6,31 -80000e04: 06e84e63 blt a6,a4,80000e80 <__register_exitproc+0x90> -80000e08: 00271813 slli a6,a4,0x2 -80000e0c: 02050663 beqz a0,80000e38 <__register_exitproc+0x48> -80000e10: 01078333 add t1,a5,a6 -80000e14: 08c32423 sw a2,136(t1) -80000e18: 1887a883 lw a7,392(a5) -80000e1c: 00100613 li a2,1 -80000e20: 00e61633 sll a2,a2,a4 -80000e24: 00c8e8b3 or a7,a7,a2 -80000e28: 1917a423 sw a7,392(a5) -80000e2c: 10d32423 sw a3,264(t1) -80000e30: 00200693 li a3,2 -80000e34: 02d50463 beq a0,a3,80000e5c <__register_exitproc+0x6c> -80000e38: 00170713 addi a4,a4,1 -80000e3c: 00e7a223 sw a4,4(a5) -80000e40: 010787b3 add a5,a5,a6 -80000e44: 00b7a423 sw a1,8(a5) -80000e48: 00000513 li a0,0 -80000e4c: 00008067 ret -80000e50: 14c70793 addi a5,a4,332 -80000e54: 14f72423 sw a5,328(a4) -80000e58: fa5ff06f j 80000dfc <__register_exitproc+0xc> -80000e5c: 18c7a683 lw a3,396(a5) -80000e60: 00170713 addi a4,a4,1 -80000e64: 00e7a223 sw a4,4(a5) -80000e68: 00c6e633 or a2,a3,a2 -80000e6c: 18c7a623 sw a2,396(a5) -80000e70: 010787b3 add a5,a5,a6 -80000e74: 00b7a423 sw a1,8(a5) -80000e78: 00000513 li a0,0 -80000e7c: 00008067 ret -80000e80: fff00513 li a0,-1 -80000e84: 00008067 ret - -80000e88 <__call_exitprocs>: -80000e88: fd010113 addi sp,sp,-48 -80000e8c: 01412c23 sw s4,24(sp) -80000e90: 0c81aa03 lw s4,200(gp) # 800048d0 <_global_impure_ptr> -80000e94: 03212023 sw s2,32(sp) -80000e98: 02112623 sw ra,44(sp) -80000e9c: 148a2903 lw s2,328(s4) -80000ea0: 02812423 sw s0,40(sp) -80000ea4: 02912223 sw s1,36(sp) -80000ea8: 01312e23 sw s3,28(sp) -80000eac: 01512a23 sw s5,20(sp) -80000eb0: 01612823 sw s6,16(sp) -80000eb4: 01712623 sw s7,12(sp) -80000eb8: 01812423 sw s8,8(sp) -80000ebc: 04090063 beqz s2,80000efc <__call_exitprocs+0x74> -80000ec0: 00050b13 mv s6,a0 -80000ec4: 00058b93 mv s7,a1 -80000ec8: 00100a93 li s5,1 -80000ecc: fff00993 li s3,-1 -80000ed0: 00492483 lw s1,4(s2) -80000ed4: fff48413 addi s0,s1,-1 -80000ed8: 02044263 bltz s0,80000efc <__call_exitprocs+0x74> -80000edc: 00249493 slli s1,s1,0x2 -80000ee0: 009904b3 add s1,s2,s1 -80000ee4: 040b8463 beqz s7,80000f2c <__call_exitprocs+0xa4> -80000ee8: 1044a783 lw a5,260(s1) -80000eec: 05778063 beq a5,s7,80000f2c <__call_exitprocs+0xa4> -80000ef0: fff40413 addi s0,s0,-1 -80000ef4: ffc48493 addi s1,s1,-4 -80000ef8: ff3416e3 bne s0,s3,80000ee4 <__call_exitprocs+0x5c> -80000efc: 02c12083 lw ra,44(sp) -80000f00: 02812403 lw s0,40(sp) -80000f04: 02412483 lw s1,36(sp) -80000f08: 02012903 lw s2,32(sp) -80000f0c: 01c12983 lw s3,28(sp) -80000f10: 01812a03 lw s4,24(sp) -80000f14: 01412a83 lw s5,20(sp) -80000f18: 01012b03 lw s6,16(sp) -80000f1c: 00c12b83 lw s7,12(sp) -80000f20: 00812c03 lw s8,8(sp) -80000f24: 03010113 addi sp,sp,48 -80000f28: 00008067 ret -80000f2c: 00492783 lw a5,4(s2) -80000f30: 0044a683 lw a3,4(s1) -80000f34: fff78793 addi a5,a5,-1 -80000f38: 04878e63 beq a5,s0,80000f94 <__call_exitprocs+0x10c> -80000f3c: 0004a223 sw zero,4(s1) -80000f40: fa0688e3 beqz a3,80000ef0 <__call_exitprocs+0x68> -80000f44: 18892783 lw a5,392(s2) -80000f48: 008a9733 sll a4,s5,s0 -80000f4c: 00492c03 lw s8,4(s2) -80000f50: 00f777b3 and a5,a4,a5 -80000f54: 02079263 bnez a5,80000f78 <__call_exitprocs+0xf0> -80000f58: 000680e7 jalr a3 -80000f5c: 00492703 lw a4,4(s2) -80000f60: 148a2783 lw a5,328(s4) -80000f64: 01871463 bne a4,s8,80000f6c <__call_exitprocs+0xe4> -80000f68: f8f904e3 beq s2,a5,80000ef0 <__call_exitprocs+0x68> -80000f6c: f80788e3 beqz a5,80000efc <__call_exitprocs+0x74> -80000f70: 00078913 mv s2,a5 -80000f74: f5dff06f j 80000ed0 <__call_exitprocs+0x48> -80000f78: 18c92783 lw a5,396(s2) -80000f7c: 0844a583 lw a1,132(s1) -80000f80: 00f77733 and a4,a4,a5 -80000f84: 00071c63 bnez a4,80000f9c <__call_exitprocs+0x114> -80000f88: 000b0513 mv a0,s6 -80000f8c: 000680e7 jalr a3 -80000f90: fcdff06f j 80000f5c <__call_exitprocs+0xd4> -80000f94: 00892223 sw s0,4(s2) -80000f98: fa9ff06f j 80000f40 <__call_exitprocs+0xb8> -80000f9c: 00058513 mv a0,a1 -80000fa0: 000680e7 jalr a3 -80000fa4: fb9ff06f j 80000f5c <__call_exitprocs+0xd4> - -80000fa8 <__fp_lock>: -80000fa8: 00000513 li a0,0 -80000fac: 00008067 ret - -80000fb0 <_cleanup_r>: -80000fb0: 800035b7 lui a1,0x80003 -80000fb4: d0058593 addi a1,a1,-768 # 80002d00 <__BSS_END__+0xffffe368> -80000fb8: 0990006f j 80001850 <_fwalk_reent> - -80000fbc <__sinit.part.0>: -80000fbc: fe010113 addi sp,sp,-32 -80000fc0: 800017b7 lui a5,0x80001 -80000fc4: 00112e23 sw ra,28(sp) -80000fc8: 00812c23 sw s0,24(sp) -80000fcc: 00912a23 sw s1,20(sp) -80000fd0: 01212823 sw s2,16(sp) -80000fd4: 01312623 sw s3,12(sp) -80000fd8: 01412423 sw s4,8(sp) -80000fdc: 01512223 sw s5,4(sp) -80000fe0: 01612023 sw s6,0(sp) -80000fe4: 00452403 lw s0,4(a0) -80000fe8: fb078793 addi a5,a5,-80 # 80000fb0 <__BSS_END__+0xffffc618> -80000fec: 02f52e23 sw a5,60(a0) -80000ff0: 2ec50713 addi a4,a0,748 -80000ff4: 00300793 li a5,3 -80000ff8: 2ee52423 sw a4,744(a0) -80000ffc: 2ef52223 sw a5,740(a0) -80001000: 2e052023 sw zero,736(a0) -80001004: 00400793 li a5,4 -80001008: 00050913 mv s2,a0 -8000100c: 00f42623 sw a5,12(s0) -80001010: 00800613 li a2,8 -80001014: 00000593 li a1,0 -80001018: 06042223 sw zero,100(s0) -8000101c: 00042023 sw zero,0(s0) -80001020: 00042223 sw zero,4(s0) -80001024: 00042423 sw zero,8(s0) -80001028: 00042823 sw zero,16(s0) -8000102c: 00042a23 sw zero,20(s0) -80001030: 00042c23 sw zero,24(s0) -80001034: 05c40513 addi a0,s0,92 -80001038: b75ff0ef jal ra,80000bac -8000103c: 80003b37 lui s6,0x80003 -80001040: 00892483 lw s1,8(s2) -80001044: 80003ab7 lui s5,0x80003 -80001048: 80003a37 lui s4,0x80003 -8000104c: 800039b7 lui s3,0x80003 -80001050: 984b0b13 addi s6,s6,-1660 # 80002984 <__BSS_END__+0xffffdfec> -80001054: 9e8a8a93 addi s5,s5,-1560 # 800029e8 <__BSS_END__+0xffffe050> -80001058: a70a0a13 addi s4,s4,-1424 # 80002a70 <__BSS_END__+0xffffe0d8> -8000105c: ad898993 addi s3,s3,-1320 # 80002ad8 <__BSS_END__+0xffffe140> -80001060: 000107b7 lui a5,0x10 -80001064: 03642023 sw s6,32(s0) -80001068: 03542223 sw s5,36(s0) -8000106c: 03442423 sw s4,40(s0) -80001070: 03342623 sw s3,44(s0) -80001074: 00842e23 sw s0,28(s0) -80001078: 00978793 addi a5,a5,9 # 10009 <_start-0x7ffefff7> -8000107c: 00f4a623 sw a5,12(s1) -80001080: 00800613 li a2,8 -80001084: 00000593 li a1,0 -80001088: 0604a223 sw zero,100(s1) -8000108c: 0004a023 sw zero,0(s1) -80001090: 0004a223 sw zero,4(s1) -80001094: 0004a423 sw zero,8(s1) -80001098: 0004a823 sw zero,16(s1) -8000109c: 0004aa23 sw zero,20(s1) -800010a0: 0004ac23 sw zero,24(s1) -800010a4: 05c48513 addi a0,s1,92 -800010a8: b05ff0ef jal ra,80000bac -800010ac: 00c92403 lw s0,12(s2) -800010b0: 000207b7 lui a5,0x20 -800010b4: 0364a023 sw s6,32(s1) -800010b8: 0354a223 sw s5,36(s1) -800010bc: 0344a423 sw s4,40(s1) -800010c0: 0334a623 sw s3,44(s1) -800010c4: 0094ae23 sw s1,28(s1) -800010c8: 01278793 addi a5,a5,18 # 20012 <_start-0x7ffdffee> -800010cc: 00f42623 sw a5,12(s0) -800010d0: 06042223 sw zero,100(s0) -800010d4: 00042023 sw zero,0(s0) -800010d8: 00042223 sw zero,4(s0) -800010dc: 00042423 sw zero,8(s0) -800010e0: 00042823 sw zero,16(s0) -800010e4: 00042a23 sw zero,20(s0) -800010e8: 00042c23 sw zero,24(s0) -800010ec: 05c40513 addi a0,s0,92 -800010f0: 00800613 li a2,8 -800010f4: 00000593 li a1,0 -800010f8: ab5ff0ef jal ra,80000bac -800010fc: 01c12083 lw ra,28(sp) -80001100: 03642023 sw s6,32(s0) -80001104: 03542223 sw s5,36(s0) -80001108: 03442423 sw s4,40(s0) -8000110c: 03342623 sw s3,44(s0) -80001110: 00842e23 sw s0,28(s0) -80001114: 01812403 lw s0,24(sp) -80001118: 00100793 li a5,1 -8000111c: 02f92c23 sw a5,56(s2) -80001120: 01412483 lw s1,20(sp) -80001124: 01012903 lw s2,16(sp) -80001128: 00c12983 lw s3,12(sp) -8000112c: 00812a03 lw s4,8(sp) -80001130: 00412a83 lw s5,4(sp) -80001134: 00012b03 lw s6,0(sp) -80001138: 02010113 addi sp,sp,32 -8000113c: 00008067 ret - -80001140 <__fp_unlock>: -80001140: 00000513 li a0,0 -80001144: 00008067 ret - -80001148 <__sfmoreglue>: -80001148: ff010113 addi sp,sp,-16 -8000114c: 00912223 sw s1,4(sp) -80001150: 06800613 li a2,104 -80001154: fff58493 addi s1,a1,-1 -80001158: 02c484b3 mul s1,s1,a2 -8000115c: 01212023 sw s2,0(sp) -80001160: 00058913 mv s2,a1 -80001164: 00812423 sw s0,8(sp) -80001168: 00112623 sw ra,12(sp) -8000116c: 07448593 addi a1,s1,116 -80001170: 794000ef jal ra,80001904 <_malloc_r> -80001174: 00050413 mv s0,a0 -80001178: 02050063 beqz a0,80001198 <__sfmoreglue+0x50> -8000117c: 00c50513 addi a0,a0,12 -80001180: 00042023 sw zero,0(s0) -80001184: 01242223 sw s2,4(s0) -80001188: 00a42423 sw a0,8(s0) -8000118c: 06848613 addi a2,s1,104 -80001190: 00000593 li a1,0 -80001194: a19ff0ef jal ra,80000bac -80001198: 00c12083 lw ra,12(sp) -8000119c: 00040513 mv a0,s0 -800011a0: 00812403 lw s0,8(sp) -800011a4: 00412483 lw s1,4(sp) -800011a8: 00012903 lw s2,0(sp) -800011ac: 01010113 addi sp,sp,16 -800011b0: 00008067 ret - -800011b4 <__sfp>: -800011b4: fe010113 addi sp,sp,-32 -800011b8: 01212823 sw s2,16(sp) -800011bc: 0c81a903 lw s2,200(gp) # 800048d0 <_global_impure_ptr> -800011c0: 01312623 sw s3,12(sp) -800011c4: 00112e23 sw ra,28(sp) -800011c8: 03892783 lw a5,56(s2) -800011cc: 00812c23 sw s0,24(sp) -800011d0: 00912a23 sw s1,20(sp) -800011d4: 00050993 mv s3,a0 -800011d8: 0a078663 beqz a5,80001284 <__sfp+0xd0> -800011dc: 2e090913 addi s2,s2,736 -800011e0: fff00493 li s1,-1 -800011e4: 00492783 lw a5,4(s2) -800011e8: 00892403 lw s0,8(s2) -800011ec: fff78793 addi a5,a5,-1 -800011f0: 0007d863 bgez a5,80001200 <__sfp+0x4c> -800011f4: 0800006f j 80001274 <__sfp+0xc0> -800011f8: 06840413 addi s0,s0,104 -800011fc: 06978c63 beq a5,s1,80001274 <__sfp+0xc0> -80001200: 00c41703 lh a4,12(s0) -80001204: fff78793 addi a5,a5,-1 -80001208: fe0718e3 bnez a4,800011f8 <__sfp+0x44> -8000120c: ffff07b7 lui a5,0xffff0 -80001210: 00178793 addi a5,a5,1 # ffff0001 <__BSS_END__+0x7ffeb669> -80001214: 06042223 sw zero,100(s0) -80001218: 00042023 sw zero,0(s0) -8000121c: 00042223 sw zero,4(s0) -80001220: 00042423 sw zero,8(s0) -80001224: 00f42623 sw a5,12(s0) -80001228: 00042823 sw zero,16(s0) -8000122c: 00042a23 sw zero,20(s0) -80001230: 00042c23 sw zero,24(s0) -80001234: 00800613 li a2,8 -80001238: 00000593 li a1,0 -8000123c: 05c40513 addi a0,s0,92 -80001240: 96dff0ef jal ra,80000bac -80001244: 02042823 sw zero,48(s0) -80001248: 02042a23 sw zero,52(s0) -8000124c: 04042223 sw zero,68(s0) -80001250: 04042423 sw zero,72(s0) -80001254: 01c12083 lw ra,28(sp) -80001258: 00040513 mv a0,s0 -8000125c: 01812403 lw s0,24(sp) -80001260: 01412483 lw s1,20(sp) -80001264: 01012903 lw s2,16(sp) -80001268: 00c12983 lw s3,12(sp) -8000126c: 02010113 addi sp,sp,32 -80001270: 00008067 ret -80001274: 00092403 lw s0,0(s2) -80001278: 00040c63 beqz s0,80001290 <__sfp+0xdc> -8000127c: 00040913 mv s2,s0 -80001280: f65ff06f j 800011e4 <__sfp+0x30> -80001284: 00090513 mv a0,s2 -80001288: d35ff0ef jal ra,80000fbc <__sinit.part.0> -8000128c: f51ff06f j 800011dc <__sfp+0x28> -80001290: 00400593 li a1,4 -80001294: 00098513 mv a0,s3 -80001298: eb1ff0ef jal ra,80001148 <__sfmoreglue> -8000129c: 00a92023 sw a0,0(s2) -800012a0: 00050413 mv s0,a0 -800012a4: fc051ce3 bnez a0,8000127c <__sfp+0xc8> -800012a8: 00c00793 li a5,12 -800012ac: 00f9a023 sw a5,0(s3) -800012b0: fa5ff06f j 80001254 <__sfp+0xa0> - -800012b4 <_cleanup>: -800012b4: 0c81a503 lw a0,200(gp) # 800048d0 <_global_impure_ptr> -800012b8: 800035b7 lui a1,0x80003 -800012bc: d0058593 addi a1,a1,-768 # 80002d00 <__BSS_END__+0xffffe368> -800012c0: 5900006f j 80001850 <_fwalk_reent> - -800012c4 <__sinit>: -800012c4: 03852783 lw a5,56(a0) -800012c8: 00078463 beqz a5,800012d0 <__sinit+0xc> -800012cc: 00008067 ret -800012d0: cedff06f j 80000fbc <__sinit.part.0> - -800012d4 <__sfp_lock_acquire>: -800012d4: 00008067 ret - -800012d8 <__sfp_lock_release>: -800012d8: 00008067 ret - -800012dc <__sinit_lock_acquire>: -800012dc: 00008067 ret - -800012e0 <__sinit_lock_release>: -800012e0: 00008067 ret - -800012e4 <__fp_lock_all>: -800012e4: 0cc1a503 lw a0,204(gp) # 800048d4 <_impure_ptr> -800012e8: 800015b7 lui a1,0x80001 -800012ec: fa858593 addi a1,a1,-88 # 80000fa8 <__BSS_END__+0xffffc610> -800012f0: 4bc0006f j 800017ac <_fwalk> - -800012f4 <__fp_unlock_all>: -800012f4: 0cc1a503 lw a0,204(gp) # 800048d4 <_impure_ptr> -800012f8: 800015b7 lui a1,0x80001 -800012fc: 14058593 addi a1,a1,320 # 80001140 <__BSS_END__+0xffffc7a8> -80001300: 4ac0006f j 800017ac <_fwalk> - -80001304 <__sfvwrite_r>: -80001304: 00862783 lw a5,8(a2) -80001308: 32078e63 beqz a5,80001644 <__sfvwrite_r+0x340> -8000130c: 00c5d783 lhu a5,12(a1) -80001310: fd010113 addi sp,sp,-48 -80001314: 02812423 sw s0,40(sp) -80001318: 01412c23 sw s4,24(sp) -8000131c: 01512a23 sw s5,20(sp) -80001320: 02112623 sw ra,44(sp) -80001324: 02912223 sw s1,36(sp) -80001328: 03212023 sw s2,32(sp) -8000132c: 01312e23 sw s3,28(sp) -80001330: 01612823 sw s6,16(sp) -80001334: 01712623 sw s7,12(sp) -80001338: 01812423 sw s8,8(sp) -8000133c: 01912223 sw s9,4(sp) -80001340: 01a12023 sw s10,0(sp) -80001344: 0087f713 andi a4,a5,8 -80001348: 00060a13 mv s4,a2 -8000134c: 00050a93 mv s5,a0 -80001350: 00058413 mv s0,a1 -80001354: 08070663 beqz a4,800013e0 <__sfvwrite_r+0xdc> -80001358: 0105a703 lw a4,16(a1) -8000135c: 08070263 beqz a4,800013e0 <__sfvwrite_r+0xdc> -80001360: 0027f713 andi a4,a5,2 -80001364: 000a2483 lw s1,0(s4) -80001368: 08070c63 beqz a4,80001400 <__sfvwrite_r+0xfc> -8000136c: 02442783 lw a5,36(s0) -80001370: 01c42583 lw a1,28(s0) -80001374: 80000b37 lui s6,0x80000 -80001378: 00000993 li s3,0 -8000137c: 00000913 li s2,0 -80001380: c00b4b13 xori s6,s6,-1024 -80001384: 00098613 mv a2,s3 -80001388: 000a8513 mv a0,s5 -8000138c: 04090263 beqz s2,800013d0 <__sfvwrite_r+0xcc> -80001390: 00090693 mv a3,s2 -80001394: 012b7463 bgeu s6,s2,8000139c <__sfvwrite_r+0x98> -80001398: 000b0693 mv a3,s6 -8000139c: 000780e7 jalr a5 -800013a0: 28a05863 blez a0,80001630 <__sfvwrite_r+0x32c> -800013a4: 008a2783 lw a5,8(s4) -800013a8: 00a989b3 add s3,s3,a0 -800013ac: 40a90933 sub s2,s2,a0 -800013b0: 40a78533 sub a0,a5,a0 -800013b4: 00aa2423 sw a0,8(s4) -800013b8: 20050a63 beqz a0,800015cc <__sfvwrite_r+0x2c8> -800013bc: 02442783 lw a5,36(s0) -800013c0: 01c42583 lw a1,28(s0) -800013c4: 00098613 mv a2,s3 -800013c8: 000a8513 mv a0,s5 -800013cc: fc0912e3 bnez s2,80001390 <__sfvwrite_r+0x8c> -800013d0: 0004a983 lw s3,0(s1) -800013d4: 0044a903 lw s2,4(s1) -800013d8: 00848493 addi s1,s1,8 -800013dc: fa9ff06f j 80001384 <__sfvwrite_r+0x80> -800013e0: 00040593 mv a1,s0 -800013e4: 000a8513 mv a0,s5 -800013e8: 760010ef jal ra,80002b48 <__swsetup_r> -800013ec: 3a051c63 bnez a0,800017a4 <__sfvwrite_r+0x4a0> -800013f0: 00c45783 lhu a5,12(s0) -800013f4: 000a2483 lw s1,0(s4) -800013f8: 0027f713 andi a4,a5,2 -800013fc: f60718e3 bnez a4,8000136c <__sfvwrite_r+0x68> -80001400: 0017f713 andi a4,a5,1 -80001404: 24071463 bnez a4,8000164c <__sfvwrite_r+0x348> -80001408: 00842c83 lw s9,8(s0) -8000140c: 00042503 lw a0,0(s0) -80001410: 80000b37 lui s6,0x80000 -80001414: ffeb4b93 xori s7,s6,-2 -80001418: 00000c13 li s8,0 -8000141c: 00000913 li s2,0 -80001420: fffb4b13 not s6,s6 -80001424: 0e090e63 beqz s2,80001520 <__sfvwrite_r+0x21c> -80001428: 2007f713 andi a4,a5,512 -8000142c: 24070c63 beqz a4,80001684 <__sfvwrite_r+0x380> -80001430: 000c8d13 mv s10,s9 -80001434: 2f996263 bltu s2,s9,80001718 <__sfvwrite_r+0x414> -80001438: 4807f713 andi a4,a5,1152 -8000143c: 08070a63 beqz a4,800014d0 <__sfvwrite_r+0x1cc> -80001440: 01442983 lw s3,20(s0) -80001444: 01042583 lw a1,16(s0) -80001448: 00190713 addi a4,s2,1 -8000144c: 00199693 slli a3,s3,0x1 -80001450: 013686b3 add a3,a3,s3 -80001454: 01f6d993 srli s3,a3,0x1f -80001458: 40b50d33 sub s10,a0,a1 -8000145c: 00d989b3 add s3,s3,a3 -80001460: 4019d993 srai s3,s3,0x1 -80001464: 01a70733 add a4,a4,s10 -80001468: 00098613 mv a2,s3 -8000146c: 00e9f663 bgeu s3,a4,80001478 <__sfvwrite_r+0x174> -80001470: 00070993 mv s3,a4 -80001474: 00070613 mv a2,a4 -80001478: 4007f793 andi a5,a5,1024 -8000147c: 2e078463 beqz a5,80001764 <__sfvwrite_r+0x460> -80001480: 00060593 mv a1,a2 -80001484: 000a8513 mv a0,s5 -80001488: 47c000ef jal ra,80001904 <_malloc_r> -8000148c: 00050c93 mv s9,a0 -80001490: 30050263 beqz a0,80001794 <__sfvwrite_r+0x490> -80001494: 01042583 lw a1,16(s0) -80001498: 000d0613 mv a2,s10 -8000149c: 4d5000ef jal ra,80002170 -800014a0: 00c45783 lhu a5,12(s0) -800014a4: b7f7f793 andi a5,a5,-1153 -800014a8: 0807e793 ori a5,a5,128 -800014ac: 00f41623 sh a5,12(s0) -800014b0: 01ac8533 add a0,s9,s10 -800014b4: 41a987b3 sub a5,s3,s10 -800014b8: 01942823 sw s9,16(s0) -800014bc: 00a42023 sw a0,0(s0) -800014c0: 01342a23 sw s3,20(s0) -800014c4: 00090c93 mv s9,s2 -800014c8: 00f42423 sw a5,8(s0) -800014cc: 00090d13 mv s10,s2 -800014d0: 000d0613 mv a2,s10 -800014d4: 000c0593 mv a1,s8 -800014d8: 5b5000ef jal ra,8000228c -800014dc: 00842703 lw a4,8(s0) -800014e0: 00042783 lw a5,0(s0) -800014e4: 00090993 mv s3,s2 -800014e8: 41970cb3 sub s9,a4,s9 -800014ec: 01a787b3 add a5,a5,s10 -800014f0: 01942423 sw s9,8(s0) -800014f4: 00f42023 sw a5,0(s0) -800014f8: 00000913 li s2,0 -800014fc: 008a2603 lw a2,8(s4) -80001500: 013c0c33 add s8,s8,s3 -80001504: 413609b3 sub s3,a2,s3 -80001508: 013a2423 sw s3,8(s4) -8000150c: 0c098063 beqz s3,800015cc <__sfvwrite_r+0x2c8> -80001510: 00842c83 lw s9,8(s0) -80001514: 00042503 lw a0,0(s0) -80001518: 00c45783 lhu a5,12(s0) -8000151c: f00916e3 bnez s2,80001428 <__sfvwrite_r+0x124> -80001520: 0004ac03 lw s8,0(s1) -80001524: 0044a903 lw s2,4(s1) -80001528: 00848493 addi s1,s1,8 -8000152c: ef9ff06f j 80001424 <__sfvwrite_r+0x120> -80001530: 0044a983 lw s3,4(s1) -80001534: 0004ac03 lw s8,0(s1) -80001538: 00848493 addi s1,s1,8 -8000153c: fe098ae3 beqz s3,80001530 <__sfvwrite_r+0x22c> -80001540: 00098613 mv a2,s3 -80001544: 00a00593 li a1,10 -80001548: 000c0513 mv a0,s8 -8000154c: 351000ef jal ra,8000209c -80001550: 12050463 beqz a0,80001678 <__sfvwrite_r+0x374> -80001554: 00150513 addi a0,a0,1 -80001558: 41850b33 sub s6,a0,s8 -8000155c: 000b0793 mv a5,s6 -80001560: 00098b93 mv s7,s3 -80001564: 0137f463 bgeu a5,s3,8000156c <__sfvwrite_r+0x268> -80001568: 00078b93 mv s7,a5 -8000156c: 00042503 lw a0,0(s0) -80001570: 01042783 lw a5,16(s0) -80001574: 01442683 lw a3,20(s0) -80001578: 00a7f863 bgeu a5,a0,80001588 <__sfvwrite_r+0x284> -8000157c: 00842903 lw s2,8(s0) -80001580: 01268933 add s2,a3,s2 -80001584: 09794263 blt s2,s7,80001608 <__sfvwrite_r+0x304> -80001588: 1adbc863 blt s7,a3,80001738 <__sfvwrite_r+0x434> -8000158c: 02442783 lw a5,36(s0) -80001590: 01c42583 lw a1,28(s0) -80001594: 000c0613 mv a2,s8 -80001598: 000a8513 mv a0,s5 -8000159c: 000780e7 jalr a5 -800015a0: 00050913 mv s2,a0 -800015a4: 08a05663 blez a0,80001630 <__sfvwrite_r+0x32c> -800015a8: 412b0b33 sub s6,s6,s2 -800015ac: 00100513 li a0,1 -800015b0: 160b0a63 beqz s6,80001724 <__sfvwrite_r+0x420> -800015b4: 008a2603 lw a2,8(s4) -800015b8: 012c0c33 add s8,s8,s2 -800015bc: 412989b3 sub s3,s3,s2 -800015c0: 41260933 sub s2,a2,s2 -800015c4: 012a2423 sw s2,8(s4) -800015c8: 08091a63 bnez s2,8000165c <__sfvwrite_r+0x358> -800015cc: 00000513 li a0,0 -800015d0: 02c12083 lw ra,44(sp) -800015d4: 02812403 lw s0,40(sp) -800015d8: 02412483 lw s1,36(sp) -800015dc: 02012903 lw s2,32(sp) -800015e0: 01c12983 lw s3,28(sp) -800015e4: 01812a03 lw s4,24(sp) -800015e8: 01412a83 lw s5,20(sp) -800015ec: 01012b03 lw s6,16(sp) -800015f0: 00c12b83 lw s7,12(sp) -800015f4: 00812c03 lw s8,8(sp) -800015f8: 00412c83 lw s9,4(sp) -800015fc: 00012d03 lw s10,0(sp) -80001600: 03010113 addi sp,sp,48 -80001604: 00008067 ret -80001608: 000c0593 mv a1,s8 -8000160c: 00090613 mv a2,s2 -80001610: 47d000ef jal ra,8000228c -80001614: 00042783 lw a5,0(s0) -80001618: 00040593 mv a1,s0 -8000161c: 000a8513 mv a0,s5 -80001620: 012787b3 add a5,a5,s2 -80001624: 00f42023 sw a5,0(s0) -80001628: 251010ef jal ra,80003078 <_fflush_r> -8000162c: f6050ee3 beqz a0,800015a8 <__sfvwrite_r+0x2a4> -80001630: 00c41783 lh a5,12(s0) -80001634: 0407e793 ori a5,a5,64 -80001638: 00f41623 sh a5,12(s0) -8000163c: fff00513 li a0,-1 -80001640: f91ff06f j 800015d0 <__sfvwrite_r+0x2cc> -80001644: 00000513 li a0,0 -80001648: 00008067 ret -8000164c: 00000b13 li s6,0 -80001650: 00000513 li a0,0 -80001654: 00000c13 li s8,0 -80001658: 00000993 li s3,0 -8000165c: ec098ae3 beqz s3,80001530 <__sfvwrite_r+0x22c> -80001660: ee051ee3 bnez a0,8000155c <__sfvwrite_r+0x258> -80001664: 00098613 mv a2,s3 -80001668: 00a00593 li a1,10 -8000166c: 000c0513 mv a0,s8 -80001670: 22d000ef jal ra,8000209c -80001674: ee0510e3 bnez a0,80001554 <__sfvwrite_r+0x250> -80001678: 00198793 addi a5,s3,1 -8000167c: 00078b13 mv s6,a5 -80001680: ee1ff06f j 80001560 <__sfvwrite_r+0x25c> -80001684: 01042783 lw a5,16(s0) -80001688: 04a7e263 bltu a5,a0,800016cc <__sfvwrite_r+0x3c8> -8000168c: 01442783 lw a5,20(s0) -80001690: 02f96e63 bltu s2,a5,800016cc <__sfvwrite_r+0x3c8> -80001694: 00090693 mv a3,s2 -80001698: 012bf463 bgeu s7,s2,800016a0 <__sfvwrite_r+0x39c> -8000169c: 000b0693 mv a3,s6 -800016a0: 02f6c6b3 div a3,a3,a5 -800016a4: 02442703 lw a4,36(s0) -800016a8: 01c42583 lw a1,28(s0) -800016ac: 000c0613 mv a2,s8 -800016b0: 000a8513 mv a0,s5 -800016b4: 02f686b3 mul a3,a3,a5 -800016b8: 000700e7 jalr a4 -800016bc: 00050993 mv s3,a0 -800016c0: f6a058e3 blez a0,80001630 <__sfvwrite_r+0x32c> -800016c4: 41390933 sub s2,s2,s3 -800016c8: e35ff06f j 800014fc <__sfvwrite_r+0x1f8> -800016cc: 000c8993 mv s3,s9 -800016d0: 01997463 bgeu s2,s9,800016d8 <__sfvwrite_r+0x3d4> -800016d4: 00090993 mv s3,s2 -800016d8: 00098613 mv a2,s3 -800016dc: 000c0593 mv a1,s8 -800016e0: 3ad000ef jal ra,8000228c -800016e4: 00842783 lw a5,8(s0) -800016e8: 00042703 lw a4,0(s0) -800016ec: 413787b3 sub a5,a5,s3 -800016f0: 01370733 add a4,a4,s3 -800016f4: 00f42423 sw a5,8(s0) -800016f8: 00e42023 sw a4,0(s0) -800016fc: fc0794e3 bnez a5,800016c4 <__sfvwrite_r+0x3c0> -80001700: 00040593 mv a1,s0 -80001704: 000a8513 mv a0,s5 -80001708: 171010ef jal ra,80003078 <_fflush_r> -8000170c: f20512e3 bnez a0,80001630 <__sfvwrite_r+0x32c> -80001710: 41390933 sub s2,s2,s3 -80001714: de9ff06f j 800014fc <__sfvwrite_r+0x1f8> -80001718: 00090c93 mv s9,s2 -8000171c: 00090d13 mv s10,s2 -80001720: db1ff06f j 800014d0 <__sfvwrite_r+0x1cc> -80001724: 00040593 mv a1,s0 -80001728: 000a8513 mv a0,s5 -8000172c: 14d010ef jal ra,80003078 <_fflush_r> -80001730: e80502e3 beqz a0,800015b4 <__sfvwrite_r+0x2b0> -80001734: efdff06f j 80001630 <__sfvwrite_r+0x32c> -80001738: 000b8613 mv a2,s7 -8000173c: 000c0593 mv a1,s8 -80001740: 34d000ef jal ra,8000228c -80001744: 00842783 lw a5,8(s0) -80001748: 00042603 lw a2,0(s0) -8000174c: 000b8913 mv s2,s7 -80001750: 417787b3 sub a5,a5,s7 -80001754: 01760633 add a2,a2,s7 -80001758: 00f42423 sw a5,8(s0) -8000175c: 00c42023 sw a2,0(s0) -80001760: e49ff06f j 800015a8 <__sfvwrite_r+0x2a4> -80001764: 000a8513 mv a0,s5 -80001768: 44d000ef jal ra,800023b4 <_realloc_r> -8000176c: 00050c93 mv s9,a0 -80001770: d40510e3 bnez a0,800014b0 <__sfvwrite_r+0x1ac> -80001774: 01042583 lw a1,16(s0) -80001778: 000a8513 mv a0,s5 -8000177c: 2ad010ef jal ra,80003228 <_free_r> -80001780: 00c41783 lh a5,12(s0) -80001784: 00c00713 li a4,12 -80001788: 00eaa023 sw a4,0(s5) -8000178c: f7f7f793 andi a5,a5,-129 -80001790: ea5ff06f j 80001634 <__sfvwrite_r+0x330> -80001794: 00c00713 li a4,12 -80001798: 00c41783 lh a5,12(s0) -8000179c: 00eaa023 sw a4,0(s5) -800017a0: e95ff06f j 80001634 <__sfvwrite_r+0x330> -800017a4: fff00513 li a0,-1 -800017a8: e29ff06f j 800015d0 <__sfvwrite_r+0x2cc> - -800017ac <_fwalk>: -800017ac: fe010113 addi sp,sp,-32 -800017b0: 01212823 sw s2,16(sp) -800017b4: 01312623 sw s3,12(sp) -800017b8: 01412423 sw s4,8(sp) -800017bc: 01512223 sw s5,4(sp) -800017c0: 01612023 sw s6,0(sp) -800017c4: 00112e23 sw ra,28(sp) -800017c8: 00812c23 sw s0,24(sp) -800017cc: 00912a23 sw s1,20(sp) -800017d0: 00058b13 mv s6,a1 -800017d4: 2e050a93 addi s5,a0,736 -800017d8: 00000a13 li s4,0 -800017dc: 00100993 li s3,1 -800017e0: fff00913 li s2,-1 -800017e4: 004aa483 lw s1,4(s5) -800017e8: 008aa403 lw s0,8(s5) -800017ec: fff48493 addi s1,s1,-1 -800017f0: 0204c663 bltz s1,8000181c <_fwalk+0x70> -800017f4: 00c45783 lhu a5,12(s0) -800017f8: fff48493 addi s1,s1,-1 -800017fc: 00f9fc63 bgeu s3,a5,80001814 <_fwalk+0x68> -80001800: 00e41783 lh a5,14(s0) -80001804: 00040513 mv a0,s0 -80001808: 01278663 beq a5,s2,80001814 <_fwalk+0x68> -8000180c: 000b00e7 jalr s6 # 80000000 <__BSS_END__+0xffffb668> -80001810: 00aa6a33 or s4,s4,a0 -80001814: 06840413 addi s0,s0,104 -80001818: fd249ee3 bne s1,s2,800017f4 <_fwalk+0x48> -8000181c: 000aaa83 lw s5,0(s5) -80001820: fc0a92e3 bnez s5,800017e4 <_fwalk+0x38> -80001824: 01c12083 lw ra,28(sp) -80001828: 01812403 lw s0,24(sp) -8000182c: 01412483 lw s1,20(sp) -80001830: 01012903 lw s2,16(sp) -80001834: 00c12983 lw s3,12(sp) -80001838: 00412a83 lw s5,4(sp) -8000183c: 00012b03 lw s6,0(sp) -80001840: 000a0513 mv a0,s4 -80001844: 00812a03 lw s4,8(sp) -80001848: 02010113 addi sp,sp,32 -8000184c: 00008067 ret - -80001850 <_fwalk_reent>: -80001850: fd010113 addi sp,sp,-48 -80001854: 03212023 sw s2,32(sp) -80001858: 01312e23 sw s3,28(sp) -8000185c: 01412c23 sw s4,24(sp) -80001860: 01512a23 sw s5,20(sp) -80001864: 01612823 sw s6,16(sp) -80001868: 01712623 sw s7,12(sp) -8000186c: 02112623 sw ra,44(sp) -80001870: 02812423 sw s0,40(sp) -80001874: 02912223 sw s1,36(sp) -80001878: 00050a93 mv s5,a0 -8000187c: 00058b93 mv s7,a1 -80001880: 2e050b13 addi s6,a0,736 -80001884: 00000a13 li s4,0 -80001888: 00100993 li s3,1 -8000188c: fff00913 li s2,-1 -80001890: 004b2483 lw s1,4(s6) -80001894: 008b2403 lw s0,8(s6) -80001898: fff48493 addi s1,s1,-1 -8000189c: 0204c863 bltz s1,800018cc <_fwalk_reent+0x7c> -800018a0: 00c45783 lhu a5,12(s0) -800018a4: fff48493 addi s1,s1,-1 -800018a8: 00f9fe63 bgeu s3,a5,800018c4 <_fwalk_reent+0x74> -800018ac: 00e41783 lh a5,14(s0) -800018b0: 00040593 mv a1,s0 -800018b4: 000a8513 mv a0,s5 -800018b8: 01278663 beq a5,s2,800018c4 <_fwalk_reent+0x74> -800018bc: 000b80e7 jalr s7 -800018c0: 00aa6a33 or s4,s4,a0 -800018c4: 06840413 addi s0,s0,104 -800018c8: fd249ce3 bne s1,s2,800018a0 <_fwalk_reent+0x50> -800018cc: 000b2b03 lw s6,0(s6) -800018d0: fc0b10e3 bnez s6,80001890 <_fwalk_reent+0x40> -800018d4: 02c12083 lw ra,44(sp) -800018d8: 02812403 lw s0,40(sp) -800018dc: 02412483 lw s1,36(sp) -800018e0: 02012903 lw s2,32(sp) -800018e4: 01c12983 lw s3,28(sp) -800018e8: 01412a83 lw s5,20(sp) -800018ec: 01012b03 lw s6,16(sp) -800018f0: 00c12b83 lw s7,12(sp) -800018f4: 000a0513 mv a0,s4 -800018f8: 01812a03 lw s4,24(sp) -800018fc: 03010113 addi sp,sp,48 -80001900: 00008067 ret - -80001904 <_malloc_r>: -80001904: fd010113 addi sp,sp,-48 -80001908: 01312e23 sw s3,28(sp) -8000190c: 02112623 sw ra,44(sp) -80001910: 02812423 sw s0,40(sp) -80001914: 02912223 sw s1,36(sp) -80001918: 03212023 sw s2,32(sp) -8000191c: 01412c23 sw s4,24(sp) -80001920: 01512a23 sw s5,20(sp) -80001924: 01612823 sw s6,16(sp) -80001928: 01712623 sw s7,12(sp) -8000192c: 01812423 sw s8,8(sp) -80001930: 01912223 sw s9,4(sp) -80001934: 00b58793 addi a5,a1,11 -80001938: 01600713 li a4,22 -8000193c: 00050993 mv s3,a0 -80001940: 06f76463 bltu a4,a5,800019a8 <_malloc_r+0xa4> -80001944: 01000793 li a5,16 -80001948: 1eb7e263 bltu a5,a1,80001b2c <_malloc_r+0x228> -8000194c: 261000ef jal ra,800023ac <__malloc_lock> -80001950: 01000493 li s1,16 -80001954: 00200613 li a2,2 -80001958: 01800793 li a5,24 -8000195c: cc018913 addi s2,gp,-832 # 800044c8 <__malloc_av_> -80001960: 00f907b3 add a5,s2,a5 -80001964: 0047a403 lw s0,4(a5) -80001968: ff878713 addi a4,a5,-8 -8000196c: 20e40863 beq s0,a4,80001b7c <_malloc_r+0x278> -80001970: 00442783 lw a5,4(s0) -80001974: 00c42683 lw a3,12(s0) -80001978: 00842603 lw a2,8(s0) -8000197c: ffc7f793 andi a5,a5,-4 -80001980: 00f407b3 add a5,s0,a5 -80001984: 0047a703 lw a4,4(a5) -80001988: 00d62623 sw a3,12(a2) -8000198c: 00c6a423 sw a2,8(a3) -80001990: 00176713 ori a4,a4,1 -80001994: 00098513 mv a0,s3 -80001998: 00e7a223 sw a4,4(a5) -8000199c: 215000ef jal ra,800023b0 <__malloc_unlock> -800019a0: 00840513 addi a0,s0,8 -800019a4: 1940006f j 80001b38 <_malloc_r+0x234> -800019a8: ff87f493 andi s1,a5,-8 -800019ac: 1807c063 bltz a5,80001b2c <_malloc_r+0x228> -800019b0: 16b4ee63 bltu s1,a1,80001b2c <_malloc_r+0x228> -800019b4: 1f9000ef jal ra,800023ac <__malloc_lock> -800019b8: 1f700793 li a5,503 -800019bc: 4497fa63 bgeu a5,s1,80001e10 <_malloc_r+0x50c> -800019c0: 0094d793 srli a5,s1,0x9 -800019c4: 1a078463 beqz a5,80001b6c <_malloc_r+0x268> -800019c8: 00400713 li a4,4 -800019cc: 3cf76063 bltu a4,a5,80001d8c <_malloc_r+0x488> -800019d0: 0064d793 srli a5,s1,0x6 -800019d4: 03978613 addi a2,a5,57 -800019d8: 03878513 addi a0,a5,56 -800019dc: 00361693 slli a3,a2,0x3 -800019e0: cc018913 addi s2,gp,-832 # 800044c8 <__malloc_av_> -800019e4: 00d906b3 add a3,s2,a3 -800019e8: 0046a403 lw s0,4(a3) -800019ec: ff868693 addi a3,a3,-8 -800019f0: 02868663 beq a3,s0,80001a1c <_malloc_r+0x118> -800019f4: 00f00593 li a1,15 -800019f8: 0100006f j 80001a08 <_malloc_r+0x104> -800019fc: 32075263 bgez a4,80001d20 <_malloc_r+0x41c> -80001a00: 00c42403 lw s0,12(s0) -80001a04: 00868c63 beq a3,s0,80001a1c <_malloc_r+0x118> -80001a08: 00442783 lw a5,4(s0) -80001a0c: ffc7f793 andi a5,a5,-4 -80001a10: 40978733 sub a4,a5,s1 -80001a14: fee5d4e3 bge a1,a4,800019fc <_malloc_r+0xf8> -80001a18: 00050613 mv a2,a0 -80001a1c: 01092403 lw s0,16(s2) -80001a20: 00890893 addi a7,s2,8 -80001a24: 17140863 beq s0,a7,80001b94 <_malloc_r+0x290> -80001a28: 00442503 lw a0,4(s0) -80001a2c: 00f00693 li a3,15 -80001a30: ffc57513 andi a0,a0,-4 -80001a34: 409507b3 sub a5,a0,s1 -80001a38: 40f6c263 blt a3,a5,80001e3c <_malloc_r+0x538> -80001a3c: 01192a23 sw a7,20(s2) -80001a40: 01192823 sw a7,16(s2) -80001a44: 3c07dc63 bgez a5,80001e1c <_malloc_r+0x518> -80001a48: 1ff00793 li a5,511 -80001a4c: 2ea7e063 bltu a5,a0,80001d2c <_malloc_r+0x428> -80001a50: ff857793 andi a5,a0,-8 -80001a54: 00878793 addi a5,a5,8 -80001a58: 00492583 lw a1,4(s2) -80001a5c: 00f907b3 add a5,s2,a5 -80001a60: 0007a683 lw a3,0(a5) -80001a64: 00555513 srli a0,a0,0x5 -80001a68: 00100713 li a4,1 -80001a6c: 00a71733 sll a4,a4,a0 -80001a70: 00b76733 or a4,a4,a1 -80001a74: ff878593 addi a1,a5,-8 -80001a78: 00b42623 sw a1,12(s0) -80001a7c: 00d42423 sw a3,8(s0) -80001a80: 00e92223 sw a4,4(s2) -80001a84: 0087a023 sw s0,0(a5) -80001a88: 0086a623 sw s0,12(a3) -80001a8c: 40265793 srai a5,a2,0x2 -80001a90: 00100593 li a1,1 -80001a94: 00f595b3 sll a1,a1,a5 -80001a98: 10b76863 bltu a4,a1,80001ba8 <_malloc_r+0x2a4> -80001a9c: 00e5f7b3 and a5,a1,a4 -80001aa0: 02079463 bnez a5,80001ac8 <_malloc_r+0x1c4> -80001aa4: 00159593 slli a1,a1,0x1 -80001aa8: ffc67613 andi a2,a2,-4 -80001aac: 00e5f7b3 and a5,a1,a4 -80001ab0: 00460613 addi a2,a2,4 -80001ab4: 00079a63 bnez a5,80001ac8 <_malloc_r+0x1c4> -80001ab8: 00159593 slli a1,a1,0x1 -80001abc: 00e5f7b3 and a5,a1,a4 -80001ac0: 00460613 addi a2,a2,4 -80001ac4: fe078ae3 beqz a5,80001ab8 <_malloc_r+0x1b4> -80001ac8: 00f00813 li a6,15 -80001acc: 00361313 slli t1,a2,0x3 -80001ad0: 00690333 add t1,s2,t1 -80001ad4: 00030513 mv a0,t1 -80001ad8: 00c52783 lw a5,12(a0) -80001adc: 00060e13 mv t3,a2 -80001ae0: 2cf50863 beq a0,a5,80001db0 <_malloc_r+0x4ac> -80001ae4: 0047a703 lw a4,4(a5) -80001ae8: 00078413 mv s0,a5 -80001aec: 00c7a783 lw a5,12(a5) -80001af0: ffc77713 andi a4,a4,-4 -80001af4: 409706b3 sub a3,a4,s1 -80001af8: 2cd84863 blt a6,a3,80001dc8 <_malloc_r+0x4c4> -80001afc: fe06c2e3 bltz a3,80001ae0 <_malloc_r+0x1dc> -80001b00: 00e40733 add a4,s0,a4 -80001b04: 00472683 lw a3,4(a4) -80001b08: 00842603 lw a2,8(s0) -80001b0c: 00098513 mv a0,s3 -80001b10: 0016e693 ori a3,a3,1 -80001b14: 00d72223 sw a3,4(a4) -80001b18: 00f62623 sw a5,12(a2) -80001b1c: 00c7a423 sw a2,8(a5) -80001b20: 091000ef jal ra,800023b0 <__malloc_unlock> -80001b24: 00840513 addi a0,s0,8 -80001b28: 0100006f j 80001b38 <_malloc_r+0x234> -80001b2c: 00c00793 li a5,12 -80001b30: 00f9a023 sw a5,0(s3) -80001b34: 00000513 li a0,0 -80001b38: 02c12083 lw ra,44(sp) -80001b3c: 02812403 lw s0,40(sp) -80001b40: 02412483 lw s1,36(sp) -80001b44: 02012903 lw s2,32(sp) -80001b48: 01c12983 lw s3,28(sp) -80001b4c: 01812a03 lw s4,24(sp) -80001b50: 01412a83 lw s5,20(sp) -80001b54: 01012b03 lw s6,16(sp) -80001b58: 00c12b83 lw s7,12(sp) -80001b5c: 00812c03 lw s8,8(sp) -80001b60: 00412c83 lw s9,4(sp) -80001b64: 03010113 addi sp,sp,48 -80001b68: 00008067 ret -80001b6c: 20000693 li a3,512 -80001b70: 04000613 li a2,64 -80001b74: 03f00513 li a0,63 -80001b78: e69ff06f j 800019e0 <_malloc_r+0xdc> -80001b7c: 00c7a403 lw s0,12(a5) -80001b80: 00260613 addi a2,a2,2 -80001b84: de8796e3 bne a5,s0,80001970 <_malloc_r+0x6c> -80001b88: 01092403 lw s0,16(s2) -80001b8c: 00890893 addi a7,s2,8 -80001b90: e9141ce3 bne s0,a7,80001a28 <_malloc_r+0x124> -80001b94: 00492703 lw a4,4(s2) -80001b98: 40265793 srai a5,a2,0x2 -80001b9c: 00100593 li a1,1 -80001ba0: 00f595b3 sll a1,a1,a5 -80001ba4: eeb77ce3 bgeu a4,a1,80001a9c <_malloc_r+0x198> -80001ba8: 00892403 lw s0,8(s2) -80001bac: 00442a83 lw s5,4(s0) -80001bb0: ffcafb13 andi s6,s5,-4 -80001bb4: 009b6863 bltu s6,s1,80001bc4 <_malloc_r+0x2c0> -80001bb8: 409b07b3 sub a5,s6,s1 -80001bbc: 00f00713 li a4,15 -80001bc0: 12f74c63 blt a4,a5,80001cf8 <_malloc_r+0x3f4> -80001bc4: 0e01aa83 lw s5,224(gp) # 800048e8 <__malloc_top_pad> -80001bc8: 0d01a703 lw a4,208(gp) # 800048d8 <__malloc_sbrk_base> -80001bcc: fff00793 li a5,-1 -80001bd0: 01640a33 add s4,s0,s6 -80001bd4: 01548ab3 add s5,s1,s5 -80001bd8: 34f70463 beq a4,a5,80001f20 <_malloc_r+0x61c> -80001bdc: 000017b7 lui a5,0x1 -80001be0: 00f78793 addi a5,a5,15 # 100f <_start-0x7fffeff1> -80001be4: 00fa8ab3 add s5,s5,a5 -80001be8: fffff7b7 lui a5,0xfffff -80001bec: 00fafab3 and s5,s5,a5 -80001bf0: 000a8593 mv a1,s5 -80001bf4: 00098513 mv a0,s3 -80001bf8: 531000ef jal ra,80002928 <_sbrk_r> -80001bfc: fff00793 li a5,-1 -80001c00: 00050b93 mv s7,a0 -80001c04: 28f50663 beq a0,a5,80001e90 <_malloc_r+0x58c> -80001c08: 29456263 bltu a0,s4,80001e8c <_malloc_r+0x588> -80001c0c: 12818c13 addi s8,gp,296 # 80004930 <__malloc_current_mallinfo> -80001c10: 000c2583 lw a1,0(s8) -80001c14: 00ba85b3 add a1,s5,a1 -80001c18: 00bc2023 sw a1,0(s8) -80001c1c: 00058793 mv a5,a1 -80001c20: 38aa0e63 beq s4,a0,80001fbc <_malloc_r+0x6b8> -80001c24: 0d01a683 lw a3,208(gp) # 800048d8 <__malloc_sbrk_base> -80001c28: fff00713 li a4,-1 -80001c2c: 3ae68663 beq a3,a4,80001fd8 <_malloc_r+0x6d4> -80001c30: 414b8a33 sub s4,s7,s4 -80001c34: 00fa07b3 add a5,s4,a5 -80001c38: 00fc2023 sw a5,0(s8) -80001c3c: 007bfc93 andi s9,s7,7 -80001c40: 300c8263 beqz s9,80001f44 <_malloc_r+0x640> -80001c44: 000017b7 lui a5,0x1 -80001c48: 419b8bb3 sub s7,s7,s9 -80001c4c: 00878593 addi a1,a5,8 # 1008 <_start-0x7fffeff8> -80001c50: 008b8b93 addi s7,s7,8 -80001c54: 419585b3 sub a1,a1,s9 -80001c58: 015b8ab3 add s5,s7,s5 -80001c5c: fff78793 addi a5,a5,-1 -80001c60: 415585b3 sub a1,a1,s5 -80001c64: 00f5fa33 and s4,a1,a5 -80001c68: 000a0593 mv a1,s4 -80001c6c: 00098513 mv a0,s3 -80001c70: 4b9000ef jal ra,80002928 <_sbrk_r> -80001c74: fff00793 li a5,-1 -80001c78: 3af50a63 beq a0,a5,8000202c <_malloc_r+0x728> -80001c7c: 41750533 sub a0,a0,s7 -80001c80: 01450ab3 add s5,a0,s4 -80001c84: 000c2583 lw a1,0(s8) -80001c88: 01792423 sw s7,8(s2) -80001c8c: 001aea93 ori s5,s5,1 -80001c90: 00ba05b3 add a1,s4,a1 -80001c94: 00bc2023 sw a1,0(s8) -80001c98: 015ba223 sw s5,4(s7) -80001c9c: 35240263 beq s0,s2,80001fe0 <_malloc_r+0x6dc> -80001ca0: 00f00693 li a3,15 -80001ca4: 3566f263 bgeu a3,s6,80001fe8 <_malloc_r+0x6e4> -80001ca8: 00442703 lw a4,4(s0) -80001cac: ff4b0793 addi a5,s6,-12 -80001cb0: ff87f793 andi a5,a5,-8 -80001cb4: 00177713 andi a4,a4,1 -80001cb8: 00f76733 or a4,a4,a5 -80001cbc: 00e42223 sw a4,4(s0) -80001cc0: 00500613 li a2,5 -80001cc4: 00f40733 add a4,s0,a5 -80001cc8: 00c72223 sw a2,4(a4) -80001ccc: 00c72423 sw a2,8(a4) -80001cd0: 36f6e863 bltu a3,a5,80002040 <_malloc_r+0x73c> -80001cd4: 004baa83 lw s5,4(s7) -80001cd8: 000b8413 mv s0,s7 -80001cdc: 0dc1a703 lw a4,220(gp) # 800048e4 <__malloc_max_sbrked_mem> -80001ce0: 00b77463 bgeu a4,a1,80001ce8 <_malloc_r+0x3e4> -80001ce4: 0cb1ae23 sw a1,220(gp) # 800048e4 <__malloc_max_sbrked_mem> -80001ce8: 0d81a703 lw a4,216(gp) # 800048e0 <__malloc_max_total_mem> -80001cec: 1ab77663 bgeu a4,a1,80001e98 <_malloc_r+0x594> -80001cf0: 0cb1ac23 sw a1,216(gp) # 800048e0 <__malloc_max_total_mem> -80001cf4: 1a40006f j 80001e98 <_malloc_r+0x594> -80001cf8: 0014e713 ori a4,s1,1 -80001cfc: 00e42223 sw a4,4(s0) -80001d00: 009404b3 add s1,s0,s1 -80001d04: 00992423 sw s1,8(s2) -80001d08: 0017e793 ori a5,a5,1 -80001d0c: 00098513 mv a0,s3 -80001d10: 00f4a223 sw a5,4(s1) -80001d14: 69c000ef jal ra,800023b0 <__malloc_unlock> -80001d18: 00840513 addi a0,s0,8 -80001d1c: e1dff06f j 80001b38 <_malloc_r+0x234> -80001d20: 00c42683 lw a3,12(s0) -80001d24: 00842603 lw a2,8(s0) -80001d28: c59ff06f j 80001980 <_malloc_r+0x7c> -80001d2c: 00955793 srli a5,a0,0x9 -80001d30: 00400713 li a4,4 -80001d34: 14f77263 bgeu a4,a5,80001e78 <_malloc_r+0x574> -80001d38: 01400713 li a4,20 -80001d3c: 22f76a63 bltu a4,a5,80001f70 <_malloc_r+0x66c> -80001d40: 05c78693 addi a3,a5,92 -80001d44: 05b78593 addi a1,a5,91 -80001d48: 00369693 slli a3,a3,0x3 -80001d4c: 00d906b3 add a3,s2,a3 -80001d50: 0006a783 lw a5,0(a3) -80001d54: ff868693 addi a3,a3,-8 -80001d58: 1cf68863 beq a3,a5,80001f28 <_malloc_r+0x624> -80001d5c: 0047a703 lw a4,4(a5) -80001d60: ffc77713 andi a4,a4,-4 -80001d64: 00e57663 bgeu a0,a4,80001d70 <_malloc_r+0x46c> -80001d68: 0087a783 lw a5,8(a5) -80001d6c: fef698e3 bne a3,a5,80001d5c <_malloc_r+0x458> -80001d70: 00c7a683 lw a3,12(a5) -80001d74: 00492703 lw a4,4(s2) -80001d78: 00d42623 sw a3,12(s0) -80001d7c: 00f42423 sw a5,8(s0) -80001d80: 0086a423 sw s0,8(a3) -80001d84: 0087a623 sw s0,12(a5) -80001d88: d05ff06f j 80001a8c <_malloc_r+0x188> -80001d8c: 01400713 li a4,20 -80001d90: 12f77663 bgeu a4,a5,80001ebc <_malloc_r+0x5b8> -80001d94: 05400713 li a4,84 -80001d98: 1ef76a63 bltu a4,a5,80001f8c <_malloc_r+0x688> -80001d9c: 00c4d793 srli a5,s1,0xc -80001da0: 06f78613 addi a2,a5,111 -80001da4: 06e78513 addi a0,a5,110 -80001da8: 00361693 slli a3,a2,0x3 -80001dac: c35ff06f j 800019e0 <_malloc_r+0xdc> -80001db0: 001e0e13 addi t3,t3,1 -80001db4: 003e7793 andi a5,t3,3 -80001db8: 00850513 addi a0,a0,8 -80001dbc: 10078e63 beqz a5,80001ed8 <_malloc_r+0x5d4> -80001dc0: 00c52783 lw a5,12(a0) -80001dc4: d1dff06f j 80001ae0 <_malloc_r+0x1dc> -80001dc8: 00842603 lw a2,8(s0) -80001dcc: 0014e593 ori a1,s1,1 -80001dd0: 00b42223 sw a1,4(s0) -80001dd4: 00f62623 sw a5,12(a2) -80001dd8: 00c7a423 sw a2,8(a5) -80001ddc: 009404b3 add s1,s0,s1 -80001de0: 00992a23 sw s1,20(s2) -80001de4: 00992823 sw s1,16(s2) -80001de8: 0016e793 ori a5,a3,1 -80001dec: 0114a623 sw a7,12(s1) -80001df0: 0114a423 sw a7,8(s1) -80001df4: 00f4a223 sw a5,4(s1) -80001df8: 00e40733 add a4,s0,a4 -80001dfc: 00098513 mv a0,s3 -80001e00: 00d72023 sw a3,0(a4) -80001e04: 5ac000ef jal ra,800023b0 <__malloc_unlock> -80001e08: 00840513 addi a0,s0,8 -80001e0c: d2dff06f j 80001b38 <_malloc_r+0x234> -80001e10: 0034d613 srli a2,s1,0x3 -80001e14: 00848793 addi a5,s1,8 -80001e18: b45ff06f j 8000195c <_malloc_r+0x58> -80001e1c: 00a40733 add a4,s0,a0 -80001e20: 00472783 lw a5,4(a4) -80001e24: 00098513 mv a0,s3 -80001e28: 0017e793 ori a5,a5,1 -80001e2c: 00f72223 sw a5,4(a4) -80001e30: 580000ef jal ra,800023b0 <__malloc_unlock> -80001e34: 00840513 addi a0,s0,8 -80001e38: d01ff06f j 80001b38 <_malloc_r+0x234> -80001e3c: 0014e713 ori a4,s1,1 -80001e40: 00e42223 sw a4,4(s0) -80001e44: 009404b3 add s1,s0,s1 -80001e48: 00992a23 sw s1,20(s2) -80001e4c: 00992823 sw s1,16(s2) -80001e50: 0017e713 ori a4,a5,1 -80001e54: 0114a623 sw a7,12(s1) -80001e58: 0114a423 sw a7,8(s1) -80001e5c: 00e4a223 sw a4,4(s1) -80001e60: 00a40533 add a0,s0,a0 -80001e64: 00f52023 sw a5,0(a0) -80001e68: 00098513 mv a0,s3 -80001e6c: 544000ef jal ra,800023b0 <__malloc_unlock> -80001e70: 00840513 addi a0,s0,8 -80001e74: cc5ff06f j 80001b38 <_malloc_r+0x234> -80001e78: 00655793 srli a5,a0,0x6 -80001e7c: 03978693 addi a3,a5,57 -80001e80: 03878593 addi a1,a5,56 -80001e84: 00369693 slli a3,a3,0x3 -80001e88: ec5ff06f j 80001d4c <_malloc_r+0x448> -80001e8c: 11240e63 beq s0,s2,80001fa8 <_malloc_r+0x6a4> -80001e90: 00892403 lw s0,8(s2) -80001e94: 00442a83 lw s5,4(s0) -80001e98: ffcafa93 andi s5,s5,-4 -80001e9c: 409a87b3 sub a5,s5,s1 -80001ea0: 009ae663 bltu s5,s1,80001eac <_malloc_r+0x5a8> -80001ea4: 00f00713 li a4,15 -80001ea8: e4f748e3 blt a4,a5,80001cf8 <_malloc_r+0x3f4> -80001eac: 00098513 mv a0,s3 -80001eb0: 500000ef jal ra,800023b0 <__malloc_unlock> -80001eb4: 00000513 li a0,0 -80001eb8: c81ff06f j 80001b38 <_malloc_r+0x234> -80001ebc: 05c78613 addi a2,a5,92 -80001ec0: 05b78513 addi a0,a5,91 -80001ec4: 00361693 slli a3,a2,0x3 -80001ec8: b19ff06f j 800019e0 <_malloc_r+0xdc> -80001ecc: 00832783 lw a5,8(t1) -80001ed0: fff60613 addi a2,a2,-1 -80001ed4: 1c679063 bne a5,t1,80002094 <_malloc_r+0x790> -80001ed8: 00367793 andi a5,a2,3 -80001edc: ff830313 addi t1,t1,-8 -80001ee0: fe0796e3 bnez a5,80001ecc <_malloc_r+0x5c8> -80001ee4: 00492703 lw a4,4(s2) -80001ee8: fff5c793 not a5,a1 -80001eec: 00e7f7b3 and a5,a5,a4 -80001ef0: 00f92223 sw a5,4(s2) -80001ef4: 00159593 slli a1,a1,0x1 -80001ef8: cab7e8e3 bltu a5,a1,80001ba8 <_malloc_r+0x2a4> -80001efc: ca0586e3 beqz a1,80001ba8 <_malloc_r+0x2a4> -80001f00: 00f5f733 and a4,a1,a5 -80001f04: 00071a63 bnez a4,80001f18 <_malloc_r+0x614> -80001f08: 00159593 slli a1,a1,0x1 -80001f0c: 00f5f733 and a4,a1,a5 -80001f10: 004e0e13 addi t3,t3,4 -80001f14: fe070ae3 beqz a4,80001f08 <_malloc_r+0x604> -80001f18: 000e0613 mv a2,t3 -80001f1c: bb1ff06f j 80001acc <_malloc_r+0x1c8> -80001f20: 010a8a93 addi s5,s5,16 -80001f24: ccdff06f j 80001bf0 <_malloc_r+0x2ec> -80001f28: 00492503 lw a0,4(s2) -80001f2c: 4025d593 srai a1,a1,0x2 -80001f30: 00100713 li a4,1 -80001f34: 00b71733 sll a4,a4,a1 -80001f38: 00a76733 or a4,a4,a0 -80001f3c: 00e92223 sw a4,4(s2) -80001f40: e39ff06f j 80001d78 <_malloc_r+0x474> -80001f44: 015b85b3 add a1,s7,s5 -80001f48: 40b005b3 neg a1,a1 -80001f4c: 01459593 slli a1,a1,0x14 -80001f50: 0145da13 srli s4,a1,0x14 -80001f54: 000a0593 mv a1,s4 -80001f58: 00098513 mv a0,s3 -80001f5c: 1cd000ef jal ra,80002928 <_sbrk_r> -80001f60: fff00793 li a5,-1 -80001f64: d0f51ce3 bne a0,a5,80001c7c <_malloc_r+0x378> -80001f68: 00000a13 li s4,0 -80001f6c: d19ff06f j 80001c84 <_malloc_r+0x380> -80001f70: 05400713 li a4,84 -80001f74: 08f76063 bltu a4,a5,80001ff4 <_malloc_r+0x6f0> -80001f78: 00c55793 srli a5,a0,0xc -80001f7c: 06f78693 addi a3,a5,111 -80001f80: 06e78593 addi a1,a5,110 -80001f84: 00369693 slli a3,a3,0x3 -80001f88: dc5ff06f j 80001d4c <_malloc_r+0x448> -80001f8c: 15400713 li a4,340 -80001f90: 08f76063 bltu a4,a5,80002010 <_malloc_r+0x70c> -80001f94: 00f4d793 srli a5,s1,0xf -80001f98: 07878613 addi a2,a5,120 -80001f9c: 07778513 addi a0,a5,119 -80001fa0: 00361693 slli a3,a2,0x3 -80001fa4: a3dff06f j 800019e0 <_malloc_r+0xdc> -80001fa8: 12818c13 addi s8,gp,296 # 80004930 <__malloc_current_mallinfo> -80001fac: 000c2783 lw a5,0(s8) -80001fb0: 00fa87b3 add a5,s5,a5 -80001fb4: 00fc2023 sw a5,0(s8) -80001fb8: c6dff06f j 80001c24 <_malloc_r+0x320> -80001fbc: 014a1713 slli a4,s4,0x14 -80001fc0: c60712e3 bnez a4,80001c24 <_malloc_r+0x320> -80001fc4: 00892403 lw s0,8(s2) -80001fc8: 015b0ab3 add s5,s6,s5 -80001fcc: 001aea93 ori s5,s5,1 -80001fd0: 01542223 sw s5,4(s0) -80001fd4: d09ff06f j 80001cdc <_malloc_r+0x3d8> -80001fd8: 0d71a823 sw s7,208(gp) # 800048d8 <__malloc_sbrk_base> -80001fdc: c61ff06f j 80001c3c <_malloc_r+0x338> -80001fe0: 000b8413 mv s0,s7 -80001fe4: cf9ff06f j 80001cdc <_malloc_r+0x3d8> -80001fe8: 00100793 li a5,1 -80001fec: 00fba223 sw a5,4(s7) -80001ff0: ebdff06f j 80001eac <_malloc_r+0x5a8> -80001ff4: 15400713 li a4,340 -80001ff8: 06f76263 bltu a4,a5,8000205c <_malloc_r+0x758> -80001ffc: 00f55793 srli a5,a0,0xf -80002000: 07878693 addi a3,a5,120 -80002004: 07778593 addi a1,a5,119 -80002008: 00369693 slli a3,a3,0x3 -8000200c: d41ff06f j 80001d4c <_malloc_r+0x448> -80002010: 55400713 li a4,1364 -80002014: 06f76263 bltu a4,a5,80002078 <_malloc_r+0x774> -80002018: 0124d793 srli a5,s1,0x12 -8000201c: 07d78613 addi a2,a5,125 -80002020: 07c78513 addi a0,a5,124 -80002024: 00361693 slli a3,a2,0x3 -80002028: 9b9ff06f j 800019e0 <_malloc_r+0xdc> -8000202c: ff8c8c93 addi s9,s9,-8 -80002030: 019a8ab3 add s5,s5,s9 -80002034: 417a8ab3 sub s5,s5,s7 -80002038: 00000a13 li s4,0 -8000203c: c49ff06f j 80001c84 <_malloc_r+0x380> -80002040: 00840593 addi a1,s0,8 -80002044: 00098513 mv a0,s3 -80002048: 1e0010ef jal ra,80003228 <_free_r> -8000204c: 00892403 lw s0,8(s2) -80002050: 000c2583 lw a1,0(s8) -80002054: 00442a83 lw s5,4(s0) -80002058: c85ff06f j 80001cdc <_malloc_r+0x3d8> -8000205c: 55400713 li a4,1364 -80002060: 02f76463 bltu a4,a5,80002088 <_malloc_r+0x784> -80002064: 01255793 srli a5,a0,0x12 -80002068: 07d78693 addi a3,a5,125 -8000206c: 07c78593 addi a1,a5,124 -80002070: 00369693 slli a3,a3,0x3 -80002074: cd9ff06f j 80001d4c <_malloc_r+0x448> -80002078: 3f800693 li a3,1016 -8000207c: 07f00613 li a2,127 -80002080: 07e00513 li a0,126 -80002084: 95dff06f j 800019e0 <_malloc_r+0xdc> -80002088: 3f800693 li a3,1016 -8000208c: 07e00593 li a1,126 -80002090: cbdff06f j 80001d4c <_malloc_r+0x448> -80002094: 00492783 lw a5,4(s2) -80002098: e5dff06f j 80001ef4 <_malloc_r+0x5f0> - -8000209c : -8000209c: 00357793 andi a5,a0,3 -800020a0: 0ff5f693 andi a3,a1,255 -800020a4: 02078a63 beqz a5,800020d8 -800020a8: fff60793 addi a5,a2,-1 -800020ac: 02060e63 beqz a2,800020e8 -800020b0: fff00613 li a2,-1 -800020b4: 0180006f j 800020cc -800020b8: 00150513 addi a0,a0,1 -800020bc: 00357713 andi a4,a0,3 -800020c0: 00070e63 beqz a4,800020dc -800020c4: fff78793 addi a5,a5,-1 -800020c8: 02c78063 beq a5,a2,800020e8 -800020cc: 00054703 lbu a4,0(a0) -800020d0: fed714e3 bne a4,a3,800020b8 -800020d4: 00008067 ret -800020d8: 00060793 mv a5,a2 -800020dc: 00300713 li a4,3 -800020e0: 02f76663 bltu a4,a5,8000210c -800020e4: 00079663 bnez a5,800020f0 -800020e8: 00000513 li a0,0 -800020ec: 00008067 ret -800020f0: 00f507b3 add a5,a0,a5 -800020f4: 00c0006f j 80002100 -800020f8: 00150513 addi a0,a0,1 -800020fc: fea786e3 beq a5,a0,800020e8 -80002100: 00054703 lbu a4,0(a0) -80002104: fed71ae3 bne a4,a3,800020f8 -80002108: 00008067 ret -8000210c: 00010737 lui a4,0x10 -80002110: 00859893 slli a7,a1,0x8 -80002114: fff70713 addi a4,a4,-1 # ffff <_start-0x7fff0001> -80002118: 00e8f8b3 and a7,a7,a4 -8000211c: 0ff5f593 andi a1,a1,255 -80002120: 00b8e5b3 or a1,a7,a1 -80002124: 01059893 slli a7,a1,0x10 -80002128: 00b8e8b3 or a7,a7,a1 -8000212c: feff0837 lui a6,0xfeff0 -80002130: 808085b7 lui a1,0x80808 -80002134: eff80813 addi a6,a6,-257 # fefefeff <__BSS_END__+0x7efeb567> -80002138: 08058593 addi a1,a1,128 # 80808080 <__BSS_END__+0x8036e8> -8000213c: 00300313 li t1,3 -80002140: 00052703 lw a4,0(a0) -80002144: 00e8c733 xor a4,a7,a4 -80002148: 01070633 add a2,a4,a6 -8000214c: fff74713 not a4,a4 -80002150: 00e67733 and a4,a2,a4 -80002154: 00b77733 and a4,a4,a1 -80002158: f8071ce3 bnez a4,800020f0 -8000215c: ffc78793 addi a5,a5,-4 -80002160: 00450513 addi a0,a0,4 -80002164: fcf36ee3 bltu t1,a5,80002140 -80002168: f80794e3 bnez a5,800020f0 -8000216c: f7dff06f j 800020e8 - -80002170 : -80002170: 00a5c7b3 xor a5,a1,a0 -80002174: 0037f793 andi a5,a5,3 -80002178: 00c508b3 add a7,a0,a2 -8000217c: 06079263 bnez a5,800021e0 -80002180: 00300793 li a5,3 -80002184: 04c7fe63 bgeu a5,a2,800021e0 -80002188: 00357793 andi a5,a0,3 -8000218c: 00050713 mv a4,a0 -80002190: 06079863 bnez a5,80002200 -80002194: ffc8f613 andi a2,a7,-4 -80002198: fe060793 addi a5,a2,-32 -8000219c: 08f76c63 bltu a4,a5,80002234 -800021a0: 02c77c63 bgeu a4,a2,800021d8 -800021a4: 00058693 mv a3,a1 -800021a8: 00070793 mv a5,a4 -800021ac: 0006a803 lw a6,0(a3) -800021b0: 00478793 addi a5,a5,4 -800021b4: 00468693 addi a3,a3,4 -800021b8: ff07ae23 sw a6,-4(a5) -800021bc: fec7e8e3 bltu a5,a2,800021ac -800021c0: fff60793 addi a5,a2,-1 -800021c4: 40e787b3 sub a5,a5,a4 -800021c8: ffc7f793 andi a5,a5,-4 -800021cc: 00478793 addi a5,a5,4 -800021d0: 00f70733 add a4,a4,a5 -800021d4: 00f585b3 add a1,a1,a5 -800021d8: 01176863 bltu a4,a7,800021e8 -800021dc: 00008067 ret -800021e0: 00050713 mv a4,a0 -800021e4: ff157ce3 bgeu a0,a7,800021dc -800021e8: 0005c783 lbu a5,0(a1) -800021ec: 00170713 addi a4,a4,1 -800021f0: 00158593 addi a1,a1,1 -800021f4: fef70fa3 sb a5,-1(a4) -800021f8: ff1768e3 bltu a4,a7,800021e8 -800021fc: 00008067 ret -80002200: 0005c683 lbu a3,0(a1) -80002204: 00170713 addi a4,a4,1 -80002208: 00377793 andi a5,a4,3 -8000220c: fed70fa3 sb a3,-1(a4) -80002210: 00158593 addi a1,a1,1 -80002214: f80780e3 beqz a5,80002194 -80002218: 0005c683 lbu a3,0(a1) -8000221c: 00170713 addi a4,a4,1 -80002220: 00377793 andi a5,a4,3 -80002224: fed70fa3 sb a3,-1(a4) -80002228: 00158593 addi a1,a1,1 -8000222c: fc079ae3 bnez a5,80002200 -80002230: f65ff06f j 80002194 -80002234: 0045a683 lw a3,4(a1) -80002238: 0005a283 lw t0,0(a1) -8000223c: 0085af83 lw t6,8(a1) -80002240: 00c5af03 lw t5,12(a1) -80002244: 0105ae83 lw t4,16(a1) -80002248: 0145ae03 lw t3,20(a1) -8000224c: 0185a303 lw t1,24(a1) -80002250: 01c5a803 lw a6,28(a1) -80002254: 00d72223 sw a3,4(a4) -80002258: 0205a683 lw a3,32(a1) -8000225c: 00572023 sw t0,0(a4) -80002260: 01f72423 sw t6,8(a4) -80002264: 01e72623 sw t5,12(a4) -80002268: 01d72823 sw t4,16(a4) -8000226c: 01c72a23 sw t3,20(a4) -80002270: 00672c23 sw t1,24(a4) -80002274: 01072e23 sw a6,28(a4) -80002278: 02d72023 sw a3,32(a4) -8000227c: 02470713 addi a4,a4,36 -80002280: 02458593 addi a1,a1,36 -80002284: faf768e3 bltu a4,a5,80002234 -80002288: f19ff06f j 800021a0 - -8000228c : -8000228c: 02a5f663 bgeu a1,a0,800022b8 -80002290: 00c587b3 add a5,a1,a2 -80002294: 02f57263 bgeu a0,a5,800022b8 -80002298: 00c50733 add a4,a0,a2 -8000229c: 0e060a63 beqz a2,80002390 -800022a0: fff7c683 lbu a3,-1(a5) -800022a4: fff78793 addi a5,a5,-1 -800022a8: fff70713 addi a4,a4,-1 -800022ac: 00d70023 sb a3,0(a4) -800022b0: fef598e3 bne a1,a5,800022a0 -800022b4: 00008067 ret -800022b8: 00f00793 li a5,15 -800022bc: 02c7e863 bltu a5,a2,800022ec -800022c0: 00050793 mv a5,a0 -800022c4: fff60693 addi a3,a2,-1 -800022c8: 0c060c63 beqz a2,800023a0 -800022cc: 00168693 addi a3,a3,1 -800022d0: 00d786b3 add a3,a5,a3 -800022d4: 0005c703 lbu a4,0(a1) -800022d8: 00178793 addi a5,a5,1 -800022dc: 00158593 addi a1,a1,1 -800022e0: fee78fa3 sb a4,-1(a5) -800022e4: fed798e3 bne a5,a3,800022d4 -800022e8: 00008067 ret -800022ec: 00a5e7b3 or a5,a1,a0 -800022f0: 0037f793 andi a5,a5,3 -800022f4: 0a079063 bnez a5,80002394 -800022f8: ff060893 addi a7,a2,-16 -800022fc: ff08f893 andi a7,a7,-16 -80002300: 01088893 addi a7,a7,16 -80002304: 01150833 add a6,a0,a7 -80002308: 00058713 mv a4,a1 -8000230c: 00050793 mv a5,a0 -80002310: 00072683 lw a3,0(a4) -80002314: 01070713 addi a4,a4,16 -80002318: 01078793 addi a5,a5,16 -8000231c: fed7a823 sw a3,-16(a5) -80002320: ff472683 lw a3,-12(a4) -80002324: fed7aa23 sw a3,-12(a5) -80002328: ff872683 lw a3,-8(a4) -8000232c: fed7ac23 sw a3,-8(a5) -80002330: ffc72683 lw a3,-4(a4) -80002334: fed7ae23 sw a3,-4(a5) -80002338: fcf81ce3 bne a6,a5,80002310 -8000233c: 00c67713 andi a4,a2,12 -80002340: 011585b3 add a1,a1,a7 -80002344: 00f67813 andi a6,a2,15 -80002348: 04070e63 beqz a4,800023a4 -8000234c: 00058713 mv a4,a1 -80002350: 00078893 mv a7,a5 -80002354: 00300e13 li t3,3 -80002358: 00072303 lw t1,0(a4) -8000235c: 00470713 addi a4,a4,4 -80002360: 40e806b3 sub a3,a6,a4 -80002364: 0068a023 sw t1,0(a7) -80002368: 00d586b3 add a3,a1,a3 -8000236c: 00488893 addi a7,a7,4 -80002370: fede64e3 bltu t3,a3,80002358 -80002374: ffc80713 addi a4,a6,-4 -80002378: ffc77713 andi a4,a4,-4 -8000237c: 00470713 addi a4,a4,4 -80002380: 00367613 andi a2,a2,3 -80002384: 00e787b3 add a5,a5,a4 -80002388: 00e585b3 add a1,a1,a4 -8000238c: f39ff06f j 800022c4 -80002390: 00008067 ret -80002394: fff60693 addi a3,a2,-1 -80002398: 00050793 mv a5,a0 -8000239c: f31ff06f j 800022cc -800023a0: 00008067 ret -800023a4: 00080613 mv a2,a6 -800023a8: f1dff06f j 800022c4 - -800023ac <__malloc_lock>: -800023ac: 00008067 ret - -800023b0 <__malloc_unlock>: -800023b0: 00008067 ret - -800023b4 <_realloc_r>: -800023b4: fd010113 addi sp,sp,-48 -800023b8: 03212023 sw s2,32(sp) -800023bc: 02112623 sw ra,44(sp) -800023c0: 02812423 sw s0,40(sp) -800023c4: 02912223 sw s1,36(sp) -800023c8: 01312e23 sw s3,28(sp) -800023cc: 01412c23 sw s4,24(sp) -800023d0: 01512a23 sw s5,20(sp) -800023d4: 01612823 sw s6,16(sp) -800023d8: 01712623 sw s7,12(sp) -800023dc: 01812423 sw s8,8(sp) -800023e0: 00060913 mv s2,a2 -800023e4: 22058263 beqz a1,80002608 <_realloc_r+0x254> -800023e8: 00058413 mv s0,a1 -800023ec: 00050993 mv s3,a0 -800023f0: fbdff0ef jal ra,800023ac <__malloc_lock> -800023f4: 00b90493 addi s1,s2,11 -800023f8: 01600793 li a5,22 -800023fc: 0e97fc63 bgeu a5,s1,800024f4 <_realloc_r+0x140> -80002400: ff84f493 andi s1,s1,-8 -80002404: 00048713 mv a4,s1 -80002408: 0e04cc63 bltz s1,80002500 <_realloc_r+0x14c> -8000240c: 0f24ea63 bltu s1,s2,80002500 <_realloc_r+0x14c> -80002410: ffc42783 lw a5,-4(s0) -80002414: ff840a93 addi s5,s0,-8 -80002418: ffc7fa13 andi s4,a5,-4 -8000241c: 014a8b33 add s6,s5,s4 -80002420: 18ea5a63 bge s4,a4,800025b4 <_realloc_r+0x200> -80002424: cc018b93 addi s7,gp,-832 # 800044c8 <__malloc_av_> -80002428: 008ba603 lw a2,8(s7) -8000242c: 004b2683 lw a3,4(s6) -80002430: 23660e63 beq a2,s6,8000266c <_realloc_r+0x2b8> -80002434: ffe6f613 andi a2,a3,-2 -80002438: 00cb0633 add a2,s6,a2 -8000243c: 00462603 lw a2,4(a2) -80002440: 00167613 andi a2,a2,1 -80002444: 1a061463 bnez a2,800025ec <_realloc_r+0x238> -80002448: ffc6f693 andi a3,a3,-4 -8000244c: 00da0633 add a2,s4,a3 -80002450: 32e65e63 bge a2,a4,8000278c <_realloc_r+0x3d8> -80002454: 0017f793 andi a5,a5,1 -80002458: 02079463 bnez a5,80002480 <_realloc_r+0xcc> -8000245c: ff842c03 lw s8,-8(s0) -80002460: 418a8c33 sub s8,s5,s8 -80002464: 004c2783 lw a5,4(s8) -80002468: ffc7f793 andi a5,a5,-4 -8000246c: 00d786b3 add a3,a5,a3 -80002470: 01468bb3 add s7,a3,s4 -80002474: 34ebda63 bge s7,a4,800027c8 <_realloc_r+0x414> -80002478: 00fa0bb3 add s7,s4,a5 -8000247c: 0cebd263 bge s7,a4,80002540 <_realloc_r+0x18c> -80002480: 00090593 mv a1,s2 -80002484: 00098513 mv a0,s3 -80002488: c7cff0ef jal ra,80001904 <_malloc_r> -8000248c: 00050913 mv s2,a0 -80002490: 04050c63 beqz a0,800024e8 <_realloc_r+0x134> -80002494: ffc42783 lw a5,-4(s0) -80002498: ff850713 addi a4,a0,-8 -8000249c: ffe7f793 andi a5,a5,-2 -800024a0: 00fa87b3 add a5,s5,a5 -800024a4: 30e78263 beq a5,a4,800027a8 <_realloc_r+0x3f4> -800024a8: ffca0613 addi a2,s4,-4 -800024ac: 02400793 li a5,36 -800024b0: 30c7e663 bltu a5,a2,800027bc <_realloc_r+0x408> -800024b4: 01300713 li a4,19 -800024b8: 00042683 lw a3,0(s0) -800024bc: 26c76c63 bltu a4,a2,80002734 <_realloc_r+0x380> -800024c0: 00050793 mv a5,a0 -800024c4: 00040713 mv a4,s0 -800024c8: 00d7a023 sw a3,0(a5) -800024cc: 00472683 lw a3,4(a4) -800024d0: 00d7a223 sw a3,4(a5) -800024d4: 00872703 lw a4,8(a4) -800024d8: 00e7a423 sw a4,8(a5) -800024dc: 00040593 mv a1,s0 -800024e0: 00098513 mv a0,s3 -800024e4: 545000ef jal ra,80003228 <_free_r> -800024e8: 00098513 mv a0,s3 -800024ec: ec5ff0ef jal ra,800023b0 <__malloc_unlock> -800024f0: 01c0006f j 8000250c <_realloc_r+0x158> -800024f4: 01000493 li s1,16 -800024f8: 01000713 li a4,16 -800024fc: f124fae3 bgeu s1,s2,80002410 <_realloc_r+0x5c> -80002500: 00c00793 li a5,12 -80002504: 00f9a023 sw a5,0(s3) -80002508: 00000913 li s2,0 -8000250c: 02c12083 lw ra,44(sp) -80002510: 02812403 lw s0,40(sp) -80002514: 02412483 lw s1,36(sp) -80002518: 01c12983 lw s3,28(sp) -8000251c: 01812a03 lw s4,24(sp) -80002520: 01412a83 lw s5,20(sp) -80002524: 01012b03 lw s6,16(sp) -80002528: 00c12b83 lw s7,12(sp) -8000252c: 00812c03 lw s8,8(sp) -80002530: 00090513 mv a0,s2 -80002534: 02012903 lw s2,32(sp) -80002538: 03010113 addi sp,sp,48 -8000253c: 00008067 ret -80002540: 00cc2783 lw a5,12(s8) -80002544: 008c2703 lw a4,8(s8) -80002548: ffca0613 addi a2,s4,-4 -8000254c: 02400693 li a3,36 -80002550: 00f72623 sw a5,12(a4) -80002554: 00e7a423 sw a4,8(a5) -80002558: 008c0913 addi s2,s8,8 -8000255c: 017c0b33 add s6,s8,s7 -80002560: 2ec6e463 bltu a3,a2,80002848 <_realloc_r+0x494> -80002564: 01300593 li a1,19 -80002568: 00042703 lw a4,0(s0) -8000256c: 00090793 mv a5,s2 -80002570: 02c5f263 bgeu a1,a2,80002594 <_realloc_r+0x1e0> -80002574: 00ec2423 sw a4,8(s8) -80002578: 00442703 lw a4,4(s0) -8000257c: 01b00793 li a5,27 -80002580: 00ec2623 sw a4,12(s8) -80002584: 30c7e263 bltu a5,a2,80002888 <_realloc_r+0x4d4> -80002588: 00842703 lw a4,8(s0) -8000258c: 010c0793 addi a5,s8,16 -80002590: 00840413 addi s0,s0,8 -80002594: 00e7a023 sw a4,0(a5) -80002598: 00442703 lw a4,4(s0) -8000259c: 000b8a13 mv s4,s7 -800025a0: 000c0a93 mv s5,s8 -800025a4: 00e7a223 sw a4,4(a5) -800025a8: 00842703 lw a4,8(s0) -800025ac: 00090413 mv s0,s2 -800025b0: 00e7a423 sw a4,8(a5) -800025b4: 004aa783 lw a5,4(s5) -800025b8: 409a0733 sub a4,s4,s1 -800025bc: 00f00693 li a3,15 -800025c0: 0017f793 andi a5,a5,1 -800025c4: 06e6ec63 bltu a3,a4,8000263c <_realloc_r+0x288> -800025c8: 00fa67b3 or a5,s4,a5 -800025cc: 00faa223 sw a5,4(s5) -800025d0: 004b2783 lw a5,4(s6) -800025d4: 0017e793 ori a5,a5,1 -800025d8: 00fb2223 sw a5,4(s6) -800025dc: 00098513 mv a0,s3 -800025e0: dd1ff0ef jal ra,800023b0 <__malloc_unlock> -800025e4: 00040913 mv s2,s0 -800025e8: f25ff06f j 8000250c <_realloc_r+0x158> -800025ec: 0017f793 andi a5,a5,1 -800025f0: e80798e3 bnez a5,80002480 <_realloc_r+0xcc> -800025f4: ff842c03 lw s8,-8(s0) -800025f8: 418a8c33 sub s8,s5,s8 -800025fc: 004c2783 lw a5,4(s8) -80002600: ffc7f793 andi a5,a5,-4 -80002604: e75ff06f j 80002478 <_realloc_r+0xc4> -80002608: 02812403 lw s0,40(sp) -8000260c: 02c12083 lw ra,44(sp) -80002610: 02412483 lw s1,36(sp) -80002614: 02012903 lw s2,32(sp) -80002618: 01c12983 lw s3,28(sp) -8000261c: 01812a03 lw s4,24(sp) -80002620: 01412a83 lw s5,20(sp) -80002624: 01012b03 lw s6,16(sp) -80002628: 00c12b83 lw s7,12(sp) -8000262c: 00812c03 lw s8,8(sp) -80002630: 00060593 mv a1,a2 -80002634: 03010113 addi sp,sp,48 -80002638: accff06f j 80001904 <_malloc_r> -8000263c: 0097e7b3 or a5,a5,s1 -80002640: 00faa223 sw a5,4(s5) -80002644: 009a85b3 add a1,s5,s1 -80002648: 00176713 ori a4,a4,1 -8000264c: 00e5a223 sw a4,4(a1) -80002650: 004b2783 lw a5,4(s6) -80002654: 00858593 addi a1,a1,8 -80002658: 00098513 mv a0,s3 -8000265c: 0017e793 ori a5,a5,1 -80002660: 00fb2223 sw a5,4(s6) -80002664: 3c5000ef jal ra,80003228 <_free_r> -80002668: f75ff06f j 800025dc <_realloc_r+0x228> -8000266c: ffc6f693 andi a3,a3,-4 -80002670: 00da0633 add a2,s4,a3 -80002674: 01048593 addi a1,s1,16 -80002678: 0eb65063 bge a2,a1,80002758 <_realloc_r+0x3a4> -8000267c: 0017f793 andi a5,a5,1 -80002680: e00790e3 bnez a5,80002480 <_realloc_r+0xcc> -80002684: ff842c03 lw s8,-8(s0) -80002688: 418a8c33 sub s8,s5,s8 -8000268c: 004c2783 lw a5,4(s8) -80002690: ffc7f793 andi a5,a5,-4 -80002694: 00d786b3 add a3,a5,a3 -80002698: 01468b33 add s6,a3,s4 -8000269c: dcbb4ee3 blt s6,a1,80002478 <_realloc_r+0xc4> -800026a0: 00cc2783 lw a5,12(s8) -800026a4: 008c2703 lw a4,8(s8) -800026a8: ffca0613 addi a2,s4,-4 -800026ac: 02400693 li a3,36 -800026b0: 00f72623 sw a5,12(a4) -800026b4: 00e7a423 sw a4,8(a5) -800026b8: 008c0913 addi s2,s8,8 -800026bc: 20c6ee63 bltu a3,a2,800028d8 <_realloc_r+0x524> -800026c0: 01300593 li a1,19 -800026c4: 00042703 lw a4,0(s0) -800026c8: 00090793 mv a5,s2 -800026cc: 02c5f263 bgeu a1,a2,800026f0 <_realloc_r+0x33c> -800026d0: 00ec2423 sw a4,8(s8) -800026d4: 00442703 lw a4,4(s0) -800026d8: 01b00793 li a5,27 -800026dc: 00ec2623 sw a4,12(s8) -800026e0: 20c7e463 bltu a5,a2,800028e8 <_realloc_r+0x534> -800026e4: 00842703 lw a4,8(s0) -800026e8: 010c0793 addi a5,s8,16 -800026ec: 00840413 addi s0,s0,8 -800026f0: 00e7a023 sw a4,0(a5) -800026f4: 00442703 lw a4,4(s0) -800026f8: 00e7a223 sw a4,4(a5) -800026fc: 00842703 lw a4,8(s0) -80002700: 00e7a423 sw a4,8(a5) -80002704: 009c0733 add a4,s8,s1 -80002708: 409b07b3 sub a5,s6,s1 -8000270c: 00eba423 sw a4,8(s7) -80002710: 0017e793 ori a5,a5,1 -80002714: 00f72223 sw a5,4(a4) -80002718: 004c2783 lw a5,4(s8) -8000271c: 00098513 mv a0,s3 -80002720: 0017f793 andi a5,a5,1 -80002724: 0097e4b3 or s1,a5,s1 -80002728: 009c2223 sw s1,4(s8) -8000272c: c85ff0ef jal ra,800023b0 <__malloc_unlock> -80002730: dddff06f j 8000250c <_realloc_r+0x158> -80002734: 00d52023 sw a3,0(a0) -80002738: 00442683 lw a3,4(s0) -8000273c: 01b00713 li a4,27 -80002740: 00d52223 sw a3,4(a0) -80002744: 12c76063 bltu a4,a2,80002864 <_realloc_r+0x4b0> -80002748: 00842683 lw a3,8(s0) -8000274c: 00840713 addi a4,s0,8 -80002750: 00850793 addi a5,a0,8 -80002754: d75ff06f j 800024c8 <_realloc_r+0x114> -80002758: 009a8ab3 add s5,s5,s1 -8000275c: 409607b3 sub a5,a2,s1 -80002760: 015ba423 sw s5,8(s7) -80002764: 0017e793 ori a5,a5,1 -80002768: 00faa223 sw a5,4(s5) -8000276c: ffc42783 lw a5,-4(s0) -80002770: 00098513 mv a0,s3 -80002774: 00040913 mv s2,s0 -80002778: 0017f793 andi a5,a5,1 -8000277c: 0097e4b3 or s1,a5,s1 -80002780: fe942e23 sw s1,-4(s0) -80002784: c2dff0ef jal ra,800023b0 <__malloc_unlock> -80002788: d85ff06f j 8000250c <_realloc_r+0x158> -8000278c: 00cb2783 lw a5,12(s6) -80002790: 008b2703 lw a4,8(s6) -80002794: 00060a13 mv s4,a2 -80002798: 00ca8b33 add s6,s5,a2 -8000279c: 00f72623 sw a5,12(a4) -800027a0: 00e7a423 sw a4,8(a5) -800027a4: e11ff06f j 800025b4 <_realloc_r+0x200> -800027a8: ffc52783 lw a5,-4(a0) -800027ac: ffc7f793 andi a5,a5,-4 -800027b0: 00fa0a33 add s4,s4,a5 -800027b4: 014a8b33 add s6,s5,s4 -800027b8: dfdff06f j 800025b4 <_realloc_r+0x200> -800027bc: 00040593 mv a1,s0 -800027c0: acdff0ef jal ra,8000228c -800027c4: d19ff06f j 800024dc <_realloc_r+0x128> -800027c8: 00cb2783 lw a5,12(s6) -800027cc: 008b2703 lw a4,8(s6) -800027d0: ffca0613 addi a2,s4,-4 -800027d4: 02400693 li a3,36 -800027d8: 00f72623 sw a5,12(a4) -800027dc: 00e7a423 sw a4,8(a5) -800027e0: 008c2703 lw a4,8(s8) -800027e4: 00cc2783 lw a5,12(s8) -800027e8: 008c0913 addi s2,s8,8 -800027ec: 017c0b33 add s6,s8,s7 -800027f0: 00f72623 sw a5,12(a4) -800027f4: 00e7a423 sw a4,8(a5) -800027f8: 04c6e863 bltu a3,a2,80002848 <_realloc_r+0x494> -800027fc: 01300693 li a3,19 -80002800: 00042703 lw a4,0(s0) -80002804: 00090793 mv a5,s2 -80002808: d8c6f6e3 bgeu a3,a2,80002594 <_realloc_r+0x1e0> -8000280c: 00ec2423 sw a4,8(s8) -80002810: 00442703 lw a4,4(s0) -80002814: 01b00793 li a5,27 -80002818: 00ec2623 sw a4,12(s8) -8000281c: 00842703 lw a4,8(s0) -80002820: d6c7f6e3 bgeu a5,a2,8000258c <_realloc_r+0x1d8> -80002824: 00ec2823 sw a4,16(s8) -80002828: 00c42703 lw a4,12(s0) -8000282c: 02400793 li a5,36 -80002830: 00ec2a23 sw a4,20(s8) -80002834: 01042703 lw a4,16(s0) -80002838: 06f60463 beq a2,a5,800028a0 <_realloc_r+0x4ec> -8000283c: 018c0793 addi a5,s8,24 -80002840: 01040413 addi s0,s0,16 -80002844: d51ff06f j 80002594 <_realloc_r+0x1e0> -80002848: 00040593 mv a1,s0 -8000284c: 00090513 mv a0,s2 -80002850: a3dff0ef jal ra,8000228c -80002854: 00090413 mv s0,s2 -80002858: 000b8a13 mv s4,s7 -8000285c: 000c0a93 mv s5,s8 -80002860: d55ff06f j 800025b4 <_realloc_r+0x200> -80002864: 00842703 lw a4,8(s0) -80002868: 00e52423 sw a4,8(a0) -8000286c: 00c42703 lw a4,12(s0) -80002870: 00e52623 sw a4,12(a0) -80002874: 01042683 lw a3,16(s0) -80002878: 04f60263 beq a2,a5,800028bc <_realloc_r+0x508> -8000287c: 01040713 addi a4,s0,16 -80002880: 01050793 addi a5,a0,16 -80002884: c45ff06f j 800024c8 <_realloc_r+0x114> -80002888: 00842783 lw a5,8(s0) -8000288c: 00fc2823 sw a5,16(s8) -80002890: 00c42783 lw a5,12(s0) -80002894: 00fc2a23 sw a5,20(s8) -80002898: 01042703 lw a4,16(s0) -8000289c: fad610e3 bne a2,a3,8000283c <_realloc_r+0x488> -800028a0: 00ec2c23 sw a4,24(s8) -800028a4: 01442703 lw a4,20(s0) -800028a8: 020c0793 addi a5,s8,32 -800028ac: 01840413 addi s0,s0,24 -800028b0: 00ec2e23 sw a4,28(s8) -800028b4: 00042703 lw a4,0(s0) -800028b8: cddff06f j 80002594 <_realloc_r+0x1e0> -800028bc: 00d52823 sw a3,16(a0) -800028c0: 01442683 lw a3,20(s0) -800028c4: 01840713 addi a4,s0,24 -800028c8: 01850793 addi a5,a0,24 -800028cc: 00d52a23 sw a3,20(a0) -800028d0: 01842683 lw a3,24(s0) -800028d4: bf5ff06f j 800024c8 <_realloc_r+0x114> -800028d8: 00040593 mv a1,s0 -800028dc: 00090513 mv a0,s2 -800028e0: 9adff0ef jal ra,8000228c -800028e4: e21ff06f j 80002704 <_realloc_r+0x350> -800028e8: 00842783 lw a5,8(s0) -800028ec: 00fc2823 sw a5,16(s8) -800028f0: 00c42783 lw a5,12(s0) -800028f4: 00fc2a23 sw a5,20(s8) -800028f8: 01042703 lw a4,16(s0) -800028fc: 00d60863 beq a2,a3,8000290c <_realloc_r+0x558> -80002900: 018c0793 addi a5,s8,24 -80002904: 01040413 addi s0,s0,16 -80002908: de9ff06f j 800026f0 <_realloc_r+0x33c> -8000290c: 00ec2c23 sw a4,24(s8) -80002910: 01442703 lw a4,20(s0) -80002914: 020c0793 addi a5,s8,32 -80002918: 01840413 addi s0,s0,24 -8000291c: 00ec2e23 sw a4,28(s8) -80002920: 00042703 lw a4,0(s0) -80002924: dcdff06f j 800026f0 <_realloc_r+0x33c> - -80002928 <_sbrk_r>: -80002928: ff010113 addi sp,sp,-16 -8000292c: 00812423 sw s0,8(sp) -80002930: 00912223 sw s1,4(sp) -80002934: 00050413 mv s0,a0 -80002938: 00058513 mv a0,a1 -8000293c: 00112623 sw ra,12(sp) -80002940: 1801a623 sw zero,396(gp) # 80004994 -80002944: 10c010ef jal ra,80003a50 <_sbrk> -80002948: fff00793 li a5,-1 -8000294c: 00f50c63 beq a0,a5,80002964 <_sbrk_r+0x3c> -80002950: 00c12083 lw ra,12(sp) -80002954: 00812403 lw s0,8(sp) -80002958: 00412483 lw s1,4(sp) -8000295c: 01010113 addi sp,sp,16 -80002960: 00008067 ret -80002964: 18c1a783 lw a5,396(gp) # 80004994 -80002968: fe0784e3 beqz a5,80002950 <_sbrk_r+0x28> -8000296c: 00c12083 lw ra,12(sp) -80002970: 00f42023 sw a5,0(s0) -80002974: 00812403 lw s0,8(sp) -80002978: 00412483 lw s1,4(sp) -8000297c: 01010113 addi sp,sp,16 -80002980: 00008067 ret - -80002984 <__sread>: -80002984: ff010113 addi sp,sp,-16 -80002988: 00812423 sw s0,8(sp) -8000298c: 00058413 mv s0,a1 -80002990: 00e59583 lh a1,14(a1) -80002994: 00112623 sw ra,12(sp) -80002998: 5e9000ef jal ra,80003780 <_read_r> -8000299c: 02054063 bltz a0,800029bc <__sread+0x38> -800029a0: 05042783 lw a5,80(s0) -800029a4: 00c12083 lw ra,12(sp) -800029a8: 00a787b3 add a5,a5,a0 -800029ac: 04f42823 sw a5,80(s0) -800029b0: 00812403 lw s0,8(sp) -800029b4: 01010113 addi sp,sp,16 -800029b8: 00008067 ret -800029bc: 00c45783 lhu a5,12(s0) -800029c0: fffff737 lui a4,0xfffff -800029c4: fff70713 addi a4,a4,-1 # ffffefff <__BSS_END__+0x7fffa667> -800029c8: 00e7f7b3 and a5,a5,a4 -800029cc: 00c12083 lw ra,12(sp) -800029d0: 00f41623 sh a5,12(s0) -800029d4: 00812403 lw s0,8(sp) -800029d8: 01010113 addi sp,sp,16 -800029dc: 00008067 ret - -800029e0 <__seofread>: -800029e0: 00000513 li a0,0 -800029e4: 00008067 ret - -800029e8 <__swrite>: -800029e8: 00c59783 lh a5,12(a1) -800029ec: fe010113 addi sp,sp,-32 -800029f0: 00812c23 sw s0,24(sp) -800029f4: 00912a23 sw s1,20(sp) -800029f8: 01212823 sw s2,16(sp) -800029fc: 01312623 sw s3,12(sp) -80002a00: 00112e23 sw ra,28(sp) -80002a04: 1007f713 andi a4,a5,256 -80002a08: 00058413 mv s0,a1 -80002a0c: 00050493 mv s1,a0 -80002a10: 00e59583 lh a1,14(a1) -80002a14: 00060913 mv s2,a2 -80002a18: 00068993 mv s3,a3 -80002a1c: 02071e63 bnez a4,80002a58 <__swrite+0x70> -80002a20: fffff737 lui a4,0xfffff -80002a24: fff70713 addi a4,a4,-1 # ffffefff <__BSS_END__+0x7fffa667> -80002a28: 00e7f7b3 and a5,a5,a4 -80002a2c: 00f41623 sh a5,12(s0) -80002a30: 01812403 lw s0,24(sp) -80002a34: 01c12083 lw ra,28(sp) -80002a38: 00098693 mv a3,s3 -80002a3c: 00090613 mv a2,s2 -80002a40: 00c12983 lw s3,12(sp) -80002a44: 01012903 lw s2,16(sp) -80002a48: 00048513 mv a0,s1 -80002a4c: 01412483 lw s1,20(sp) -80002a50: 02010113 addi sp,sp,32 -80002a54: 08c0006f j 80002ae0 <_write_r> -80002a58: 00200693 li a3,2 -80002a5c: 00000613 li a2,0 -80002a60: 2c9000ef jal ra,80003528 <_lseek_r> -80002a64: 00c41783 lh a5,12(s0) -80002a68: 00e41583 lh a1,14(s0) -80002a6c: fb5ff06f j 80002a20 <__swrite+0x38> - -80002a70 <__sseek>: -80002a70: ff010113 addi sp,sp,-16 -80002a74: 00812423 sw s0,8(sp) -80002a78: 00058413 mv s0,a1 -80002a7c: 00e59583 lh a1,14(a1) -80002a80: 00112623 sw ra,12(sp) -80002a84: 2a5000ef jal ra,80003528 <_lseek_r> -80002a88: fff00793 li a5,-1 -80002a8c: 02f50463 beq a0,a5,80002ab4 <__sseek+0x44> -80002a90: 00c45783 lhu a5,12(s0) -80002a94: 00001737 lui a4,0x1 -80002a98: 00c12083 lw ra,12(sp) -80002a9c: 00e7e7b3 or a5,a5,a4 -80002aa0: 04a42823 sw a0,80(s0) -80002aa4: 00f41623 sh a5,12(s0) -80002aa8: 00812403 lw s0,8(sp) -80002aac: 01010113 addi sp,sp,16 -80002ab0: 00008067 ret -80002ab4: 00c45783 lhu a5,12(s0) -80002ab8: fffff737 lui a4,0xfffff -80002abc: fff70713 addi a4,a4,-1 # ffffefff <__BSS_END__+0x7fffa667> -80002ac0: 00e7f7b3 and a5,a5,a4 -80002ac4: 00c12083 lw ra,12(sp) -80002ac8: 00f41623 sh a5,12(s0) -80002acc: 00812403 lw s0,8(sp) -80002ad0: 01010113 addi sp,sp,16 -80002ad4: 00008067 ret - -80002ad8 <__sclose>: -80002ad8: 00e59583 lh a1,14(a1) -80002adc: 1c80006f j 80002ca4 <_close_r> - -80002ae0 <_write_r>: -80002ae0: ff010113 addi sp,sp,-16 -80002ae4: 00058713 mv a4,a1 -80002ae8: 00812423 sw s0,8(sp) -80002aec: 00912223 sw s1,4(sp) -80002af0: 00060593 mv a1,a2 -80002af4: 00050413 mv s0,a0 -80002af8: 00068613 mv a2,a3 -80002afc: 00070513 mv a0,a4 -80002b00: 00112623 sw ra,12(sp) -80002b04: 1801a623 sw zero,396(gp) # 80004994 -80002b08: 7e5000ef jal ra,80003aec <_write> -80002b0c: fff00793 li a5,-1 -80002b10: 00f50c63 beq a0,a5,80002b28 <_write_r+0x48> -80002b14: 00c12083 lw ra,12(sp) -80002b18: 00812403 lw s0,8(sp) -80002b1c: 00412483 lw s1,4(sp) -80002b20: 01010113 addi sp,sp,16 -80002b24: 00008067 ret -80002b28: 18c1a783 lw a5,396(gp) # 80004994 -80002b2c: fe0784e3 beqz a5,80002b14 <_write_r+0x34> -80002b30: 00c12083 lw ra,12(sp) -80002b34: 00f42023 sw a5,0(s0) -80002b38: 00812403 lw s0,8(sp) -80002b3c: 00412483 lw s1,4(sp) -80002b40: 01010113 addi sp,sp,16 -80002b44: 00008067 ret - -80002b48 <__swsetup_r>: -80002b48: 0cc1a783 lw a5,204(gp) # 800048d4 <_impure_ptr> -80002b4c: ff010113 addi sp,sp,-16 -80002b50: 00812423 sw s0,8(sp) -80002b54: 00912223 sw s1,4(sp) -80002b58: 00112623 sw ra,12(sp) -80002b5c: 00050493 mv s1,a0 -80002b60: 00058413 mv s0,a1 -80002b64: 00078663 beqz a5,80002b70 <__swsetup_r+0x28> -80002b68: 0387a703 lw a4,56(a5) -80002b6c: 0e070063 beqz a4,80002c4c <__swsetup_r+0x104> -80002b70: 00c41703 lh a4,12(s0) -80002b74: 01071793 slli a5,a4,0x10 -80002b78: 00877693 andi a3,a4,8 -80002b7c: 0107d793 srli a5,a5,0x10 -80002b80: 04068063 beqz a3,80002bc0 <__swsetup_r+0x78> -80002b84: 01042683 lw a3,16(s0) -80002b88: 06068063 beqz a3,80002be8 <__swsetup_r+0xa0> -80002b8c: 0017f613 andi a2,a5,1 -80002b90: 08060463 beqz a2,80002c18 <__swsetup_r+0xd0> -80002b94: 01442603 lw a2,20(s0) -80002b98: 00042423 sw zero,8(s0) -80002b9c: 00000513 li a0,0 -80002ba0: 40c00633 neg a2,a2 -80002ba4: 00c42c23 sw a2,24(s0) -80002ba8: 08068663 beqz a3,80002c34 <__swsetup_r+0xec> -80002bac: 00c12083 lw ra,12(sp) -80002bb0: 00812403 lw s0,8(sp) -80002bb4: 00412483 lw s1,4(sp) -80002bb8: 01010113 addi sp,sp,16 -80002bbc: 00008067 ret -80002bc0: 0107f693 andi a3,a5,16 -80002bc4: 0c068463 beqz a3,80002c8c <__swsetup_r+0x144> -80002bc8: 0047f793 andi a5,a5,4 -80002bcc: 08079663 bnez a5,80002c58 <__swsetup_r+0x110> -80002bd0: 01042683 lw a3,16(s0) -80002bd4: 00876713 ori a4,a4,8 -80002bd8: 01071793 slli a5,a4,0x10 -80002bdc: 00e41623 sh a4,12(s0) -80002be0: 0107d793 srli a5,a5,0x10 -80002be4: fa0694e3 bnez a3,80002b8c <__swsetup_r+0x44> -80002be8: 2807f613 andi a2,a5,640 -80002bec: 20000593 li a1,512 -80002bf0: f8b60ee3 beq a2,a1,80002b8c <__swsetup_r+0x44> -80002bf4: 00040593 mv a1,s0 -80002bf8: 00048513 mv a0,s1 -80002bfc: 265000ef jal ra,80003660 <__smakebuf_r> -80002c00: 00c41703 lh a4,12(s0) -80002c04: 01042683 lw a3,16(s0) -80002c08: 01071793 slli a5,a4,0x10 -80002c0c: 0107d793 srli a5,a5,0x10 -80002c10: 0017f613 andi a2,a5,1 -80002c14: f80610e3 bnez a2,80002b94 <__swsetup_r+0x4c> -80002c18: 0027f613 andi a2,a5,2 -80002c1c: 00000593 li a1,0 -80002c20: 00061463 bnez a2,80002c28 <__swsetup_r+0xe0> -80002c24: 01442583 lw a1,20(s0) -80002c28: 00b42423 sw a1,8(s0) -80002c2c: 00000513 li a0,0 -80002c30: f6069ee3 bnez a3,80002bac <__swsetup_r+0x64> -80002c34: 0807f793 andi a5,a5,128 -80002c38: f6078ae3 beqz a5,80002bac <__swsetup_r+0x64> -80002c3c: 04076713 ori a4,a4,64 -80002c40: 00e41623 sh a4,12(s0) -80002c44: fff00513 li a0,-1 -80002c48: f65ff06f j 80002bac <__swsetup_r+0x64> -80002c4c: 00078513 mv a0,a5 -80002c50: e74fe0ef jal ra,800012c4 <__sinit> -80002c54: f1dff06f j 80002b70 <__swsetup_r+0x28> -80002c58: 03042583 lw a1,48(s0) -80002c5c: 00058e63 beqz a1,80002c78 <__swsetup_r+0x130> -80002c60: 04040793 addi a5,s0,64 -80002c64: 00f58863 beq a1,a5,80002c74 <__swsetup_r+0x12c> -80002c68: 00048513 mv a0,s1 -80002c6c: 5bc000ef jal ra,80003228 <_free_r> -80002c70: 00c41703 lh a4,12(s0) -80002c74: 02042823 sw zero,48(s0) -80002c78: 01042683 lw a3,16(s0) -80002c7c: fdb77713 andi a4,a4,-37 -80002c80: 00042223 sw zero,4(s0) -80002c84: 00d42023 sw a3,0(s0) -80002c88: f4dff06f j 80002bd4 <__swsetup_r+0x8c> -80002c8c: 00900793 li a5,9 -80002c90: 00f4a023 sw a5,0(s1) -80002c94: 04076713 ori a4,a4,64 -80002c98: 00e41623 sh a4,12(s0) -80002c9c: fff00513 li a0,-1 -80002ca0: f0dff06f j 80002bac <__swsetup_r+0x64> - -80002ca4 <_close_r>: -80002ca4: ff010113 addi sp,sp,-16 -80002ca8: 00812423 sw s0,8(sp) -80002cac: 00912223 sw s1,4(sp) -80002cb0: 00050413 mv s0,a0 -80002cb4: 00058513 mv a0,a1 -80002cb8: 00112623 sw ra,12(sp) -80002cbc: 1801a623 sw zero,396(gp) # 80004994 -80002cc0: 3e9000ef jal ra,800038a8 <_close> -80002cc4: fff00793 li a5,-1 -80002cc8: 00f50c63 beq a0,a5,80002ce0 <_close_r+0x3c> -80002ccc: 00c12083 lw ra,12(sp) -80002cd0: 00812403 lw s0,8(sp) -80002cd4: 00412483 lw s1,4(sp) -80002cd8: 01010113 addi sp,sp,16 -80002cdc: 00008067 ret -80002ce0: 18c1a783 lw a5,396(gp) # 80004994 -80002ce4: fe0784e3 beqz a5,80002ccc <_close_r+0x28> -80002ce8: 00c12083 lw ra,12(sp) -80002cec: 00f42023 sw a5,0(s0) -80002cf0: 00812403 lw s0,8(sp) -80002cf4: 00412483 lw s1,4(sp) -80002cf8: 01010113 addi sp,sp,16 -80002cfc: 00008067 ret - -80002d00 <_fclose_r>: -80002d00: ff010113 addi sp,sp,-16 -80002d04: 00112623 sw ra,12(sp) -80002d08: 00812423 sw s0,8(sp) -80002d0c: 00912223 sw s1,4(sp) -80002d10: 01212023 sw s2,0(sp) -80002d14: 02058063 beqz a1,80002d34 <_fclose_r+0x34> -80002d18: 00058413 mv s0,a1 -80002d1c: 00050493 mv s1,a0 -80002d20: 00050663 beqz a0,80002d2c <_fclose_r+0x2c> -80002d24: 03852783 lw a5,56(a0) -80002d28: 0a078c63 beqz a5,80002de0 <_fclose_r+0xe0> -80002d2c: 00c41783 lh a5,12(s0) -80002d30: 02079263 bnez a5,80002d54 <_fclose_r+0x54> -80002d34: 00c12083 lw ra,12(sp) -80002d38: 00812403 lw s0,8(sp) -80002d3c: 00000913 li s2,0 -80002d40: 00412483 lw s1,4(sp) -80002d44: 00090513 mv a0,s2 -80002d48: 00012903 lw s2,0(sp) -80002d4c: 01010113 addi sp,sp,16 -80002d50: 00008067 ret -80002d54: 00040593 mv a1,s0 -80002d58: 00048513 mv a0,s1 -80002d5c: 0c0000ef jal ra,80002e1c <__sflush_r> -80002d60: 02c42783 lw a5,44(s0) -80002d64: 00050913 mv s2,a0 -80002d68: 00078a63 beqz a5,80002d7c <_fclose_r+0x7c> -80002d6c: 01c42583 lw a1,28(s0) -80002d70: 00048513 mv a0,s1 -80002d74: 000780e7 jalr a5 -80002d78: 06054c63 bltz a0,80002df0 <_fclose_r+0xf0> -80002d7c: 00c45783 lhu a5,12(s0) -80002d80: 0807f793 andi a5,a5,128 -80002d84: 06079e63 bnez a5,80002e00 <_fclose_r+0x100> -80002d88: 03042583 lw a1,48(s0) -80002d8c: 00058c63 beqz a1,80002da4 <_fclose_r+0xa4> -80002d90: 04040793 addi a5,s0,64 -80002d94: 00f58663 beq a1,a5,80002da0 <_fclose_r+0xa0> -80002d98: 00048513 mv a0,s1 -80002d9c: 48c000ef jal ra,80003228 <_free_r> -80002da0: 02042823 sw zero,48(s0) -80002da4: 04442583 lw a1,68(s0) -80002da8: 00058863 beqz a1,80002db8 <_fclose_r+0xb8> -80002dac: 00048513 mv a0,s1 -80002db0: 478000ef jal ra,80003228 <_free_r> -80002db4: 04042223 sw zero,68(s0) -80002db8: d1cfe0ef jal ra,800012d4 <__sfp_lock_acquire> -80002dbc: 00041623 sh zero,12(s0) -80002dc0: d18fe0ef jal ra,800012d8 <__sfp_lock_release> -80002dc4: 00c12083 lw ra,12(sp) -80002dc8: 00812403 lw s0,8(sp) -80002dcc: 00412483 lw s1,4(sp) -80002dd0: 00090513 mv a0,s2 -80002dd4: 00012903 lw s2,0(sp) -80002dd8: 01010113 addi sp,sp,16 -80002ddc: 00008067 ret -80002de0: ce4fe0ef jal ra,800012c4 <__sinit> -80002de4: 00c41783 lh a5,12(s0) -80002de8: f40786e3 beqz a5,80002d34 <_fclose_r+0x34> -80002dec: f69ff06f j 80002d54 <_fclose_r+0x54> -80002df0: 00c45783 lhu a5,12(s0) -80002df4: fff00913 li s2,-1 -80002df8: 0807f793 andi a5,a5,128 -80002dfc: f80786e3 beqz a5,80002d88 <_fclose_r+0x88> -80002e00: 01042583 lw a1,16(s0) -80002e04: 00048513 mv a0,s1 -80002e08: 420000ef jal ra,80003228 <_free_r> -80002e0c: f7dff06f j 80002d88 <_fclose_r+0x88> - -80002e10 : -80002e10: 00050593 mv a1,a0 -80002e14: 0cc1a503 lw a0,204(gp) # 800048d4 <_impure_ptr> -80002e18: ee9ff06f j 80002d00 <_fclose_r> - -80002e1c <__sflush_r>: -80002e1c: 00c59783 lh a5,12(a1) -80002e20: fe010113 addi sp,sp,-32 -80002e24: 00812c23 sw s0,24(sp) -80002e28: 01312623 sw s3,12(sp) -80002e2c: 00112e23 sw ra,28(sp) -80002e30: 00912a23 sw s1,20(sp) -80002e34: 01212823 sw s2,16(sp) -80002e38: 0087f693 andi a3,a5,8 -80002e3c: 00058413 mv s0,a1 -80002e40: 00050993 mv s3,a0 -80002e44: 10069a63 bnez a3,80002f58 <__sflush_r+0x13c> -80002e48: 00001737 lui a4,0x1 -80002e4c: 80070713 addi a4,a4,-2048 # 800 <_start-0x7ffff800> -80002e50: 0045a683 lw a3,4(a1) -80002e54: 00e7e7b3 or a5,a5,a4 -80002e58: 00f59623 sh a5,12(a1) -80002e5c: 18d05463 blez a3,80002fe4 <__sflush_r+0x1c8> -80002e60: 02842703 lw a4,40(s0) -80002e64: 0c070a63 beqz a4,80002f38 <__sflush_r+0x11c> -80002e68: 0009a483 lw s1,0(s3) -80002e6c: 01079693 slli a3,a5,0x10 -80002e70: 0009a023 sw zero,0(s3) -80002e74: 01379613 slli a2,a5,0x13 -80002e78: 01c42583 lw a1,28(s0) -80002e7c: 0106d693 srli a3,a3,0x10 -80002e80: 16064863 bltz a2,80002ff0 <__sflush_r+0x1d4> -80002e84: 00100693 li a3,1 -80002e88: 00000613 li a2,0 -80002e8c: 00098513 mv a0,s3 -80002e90: 000700e7 jalr a4 -80002e94: fff00793 li a5,-1 -80002e98: 18f50c63 beq a0,a5,80003030 <__sflush_r+0x214> -80002e9c: 00c45683 lhu a3,12(s0) -80002ea0: 02842703 lw a4,40(s0) -80002ea4: 01c42583 lw a1,28(s0) -80002ea8: 0046f693 andi a3,a3,4 -80002eac: 00068e63 beqz a3,80002ec8 <__sflush_r+0xac> -80002eb0: 00442683 lw a3,4(s0) -80002eb4: 03042783 lw a5,48(s0) -80002eb8: 40d50533 sub a0,a0,a3 -80002ebc: 00078663 beqz a5,80002ec8 <__sflush_r+0xac> -80002ec0: 03c42783 lw a5,60(s0) -80002ec4: 40f50533 sub a0,a0,a5 -80002ec8: 00050613 mv a2,a0 -80002ecc: 00000693 li a3,0 -80002ed0: 00098513 mv a0,s3 -80002ed4: 000700e7 jalr a4 -80002ed8: fff00793 li a5,-1 -80002edc: 10f51e63 bne a0,a5,80002ff8 <__sflush_r+0x1dc> -80002ee0: 0009a703 lw a4,0(s3) -80002ee4: 00c41783 lh a5,12(s0) -80002ee8: 16070863 beqz a4,80003058 <__sflush_r+0x23c> -80002eec: 01d00693 li a3,29 -80002ef0: 00d70663 beq a4,a3,80002efc <__sflush_r+0xe0> -80002ef4: 01600693 li a3,22 -80002ef8: 0cd71463 bne a4,a3,80002fc0 <__sflush_r+0x1a4> -80002efc: 01042683 lw a3,16(s0) -80002f00: fffff737 lui a4,0xfffff -80002f04: 7ff70713 addi a4,a4,2047 # fffff7ff <__BSS_END__+0x7fffae67> -80002f08: 00e7f7b3 and a5,a5,a4 -80002f0c: 00f41623 sh a5,12(s0) -80002f10: 00042223 sw zero,4(s0) -80002f14: 00d42023 sw a3,0(s0) -80002f18: 03042583 lw a1,48(s0) -80002f1c: 0099a023 sw s1,0(s3) -80002f20: 00058c63 beqz a1,80002f38 <__sflush_r+0x11c> -80002f24: 04040793 addi a5,s0,64 -80002f28: 00f58663 beq a1,a5,80002f34 <__sflush_r+0x118> -80002f2c: 00098513 mv a0,s3 -80002f30: 2f8000ef jal ra,80003228 <_free_r> -80002f34: 02042823 sw zero,48(s0) -80002f38: 00000513 li a0,0 -80002f3c: 01c12083 lw ra,28(sp) -80002f40: 01812403 lw s0,24(sp) -80002f44: 01412483 lw s1,20(sp) -80002f48: 01012903 lw s2,16(sp) -80002f4c: 00c12983 lw s3,12(sp) -80002f50: 02010113 addi sp,sp,32 -80002f54: 00008067 ret -80002f58: 0105a903 lw s2,16(a1) -80002f5c: fc090ee3 beqz s2,80002f38 <__sflush_r+0x11c> -80002f60: 0005a483 lw s1,0(a1) -80002f64: 01079713 slli a4,a5,0x10 -80002f68: 01075713 srli a4,a4,0x10 -80002f6c: 00377713 andi a4,a4,3 -80002f70: 0125a023 sw s2,0(a1) -80002f74: 412484b3 sub s1,s1,s2 -80002f78: 00000793 li a5,0 -80002f7c: 00071463 bnez a4,80002f84 <__sflush_r+0x168> -80002f80: 0145a783 lw a5,20(a1) -80002f84: 00f42423 sw a5,8(s0) -80002f88: 00904863 bgtz s1,80002f98 <__sflush_r+0x17c> -80002f8c: fadff06f j 80002f38 <__sflush_r+0x11c> -80002f90: 00a90933 add s2,s2,a0 -80002f94: fa9052e3 blez s1,80002f38 <__sflush_r+0x11c> -80002f98: 02442783 lw a5,36(s0) -80002f9c: 01c42583 lw a1,28(s0) -80002fa0: 00048693 mv a3,s1 -80002fa4: 00090613 mv a2,s2 -80002fa8: 00098513 mv a0,s3 -80002fac: 000780e7 jalr a5 -80002fb0: 40a484b3 sub s1,s1,a0 -80002fb4: fca04ee3 bgtz a0,80002f90 <__sflush_r+0x174> -80002fb8: 00c45783 lhu a5,12(s0) -80002fbc: fff00513 li a0,-1 -80002fc0: 0407e793 ori a5,a5,64 -80002fc4: 01c12083 lw ra,28(sp) -80002fc8: 00f41623 sh a5,12(s0) -80002fcc: 01812403 lw s0,24(sp) -80002fd0: 01412483 lw s1,20(sp) -80002fd4: 01012903 lw s2,16(sp) -80002fd8: 00c12983 lw s3,12(sp) -80002fdc: 02010113 addi sp,sp,32 -80002fe0: 00008067 ret -80002fe4: 03c5a703 lw a4,60(a1) -80002fe8: e6e04ce3 bgtz a4,80002e60 <__sflush_r+0x44> -80002fec: f4dff06f j 80002f38 <__sflush_r+0x11c> -80002ff0: 05042503 lw a0,80(s0) -80002ff4: eb5ff06f j 80002ea8 <__sflush_r+0x8c> -80002ff8: 00c45783 lhu a5,12(s0) -80002ffc: fffff737 lui a4,0xfffff -80003000: 7ff70713 addi a4,a4,2047 # fffff7ff <__BSS_END__+0x7fffae67> -80003004: 00e7f7b3 and a5,a5,a4 -80003008: 01042683 lw a3,16(s0) -8000300c: 01079793 slli a5,a5,0x10 -80003010: 4107d793 srai a5,a5,0x10 -80003014: 00f41623 sh a5,12(s0) -80003018: 00042223 sw zero,4(s0) -8000301c: 00d42023 sw a3,0(s0) -80003020: 01379713 slli a4,a5,0x13 -80003024: ee075ae3 bgez a4,80002f18 <__sflush_r+0xfc> -80003028: 04a42823 sw a0,80(s0) -8000302c: eedff06f j 80002f18 <__sflush_r+0xfc> -80003030: 0009a783 lw a5,0(s3) -80003034: e60784e3 beqz a5,80002e9c <__sflush_r+0x80> -80003038: 01d00713 li a4,29 -8000303c: 02e78863 beq a5,a4,8000306c <__sflush_r+0x250> -80003040: 01600713 li a4,22 -80003044: 02e78463 beq a5,a4,8000306c <__sflush_r+0x250> -80003048: 00c45783 lhu a5,12(s0) -8000304c: 0407e793 ori a5,a5,64 -80003050: 00f41623 sh a5,12(s0) -80003054: ee9ff06f j 80002f3c <__sflush_r+0x120> -80003058: fffff737 lui a4,0xfffff -8000305c: 7ff70713 addi a4,a4,2047 # fffff7ff <__BSS_END__+0x7fffae67> -80003060: 01042683 lw a3,16(s0) -80003064: 00e7f7b3 and a5,a5,a4 -80003068: fadff06f j 80003014 <__sflush_r+0x1f8> -8000306c: 0099a023 sw s1,0(s3) -80003070: 00000513 li a0,0 -80003074: ec9ff06f j 80002f3c <__sflush_r+0x120> - -80003078 <_fflush_r>: -80003078: fe010113 addi sp,sp,-32 -8000307c: 00812c23 sw s0,24(sp) -80003080: 00112e23 sw ra,28(sp) -80003084: 00050413 mv s0,a0 -80003088: 00050663 beqz a0,80003094 <_fflush_r+0x1c> -8000308c: 03852783 lw a5,56(a0) -80003090: 02078063 beqz a5,800030b0 <_fflush_r+0x38> -80003094: 00c59783 lh a5,12(a1) -80003098: 02079663 bnez a5,800030c4 <_fflush_r+0x4c> -8000309c: 01c12083 lw ra,28(sp) -800030a0: 01812403 lw s0,24(sp) -800030a4: 00000513 li a0,0 -800030a8: 02010113 addi sp,sp,32 -800030ac: 00008067 ret -800030b0: 00b12623 sw a1,12(sp) -800030b4: a10fe0ef jal ra,800012c4 <__sinit> -800030b8: 00c12583 lw a1,12(sp) -800030bc: 00c59783 lh a5,12(a1) -800030c0: fc078ee3 beqz a5,8000309c <_fflush_r+0x24> -800030c4: 00040513 mv a0,s0 -800030c8: 01812403 lw s0,24(sp) -800030cc: 01c12083 lw ra,28(sp) -800030d0: 02010113 addi sp,sp,32 -800030d4: d49ff06f j 80002e1c <__sflush_r> - -800030d8 : -800030d8: 00050593 mv a1,a0 -800030dc: 00050663 beqz a0,800030e8 -800030e0: 0cc1a503 lw a0,204(gp) # 800048d4 <_impure_ptr> -800030e4: f95ff06f j 80003078 <_fflush_r> -800030e8: 0c81a503 lw a0,200(gp) # 800048d0 <_global_impure_ptr> -800030ec: 800035b7 lui a1,0x80003 -800030f0: 07858593 addi a1,a1,120 # 80003078 <__BSS_END__+0xffffe6e0> -800030f4: f5cfe06f j 80001850 <_fwalk_reent> - -800030f8 <_malloc_trim_r>: -800030f8: fe010113 addi sp,sp,-32 -800030fc: 01312623 sw s3,12(sp) -80003100: 00812c23 sw s0,24(sp) -80003104: 00912a23 sw s1,20(sp) -80003108: 01212823 sw s2,16(sp) -8000310c: 01412423 sw s4,8(sp) -80003110: 00112e23 sw ra,28(sp) -80003114: 00058a13 mv s4,a1 -80003118: 00050913 mv s2,a0 -8000311c: cc018993 addi s3,gp,-832 # 800044c8 <__malloc_av_> -80003120: a8cff0ef jal ra,800023ac <__malloc_lock> -80003124: 0089a703 lw a4,8(s3) -80003128: 000017b7 lui a5,0x1 -8000312c: fef78413 addi s0,a5,-17 # fef <_start-0x7ffff011> -80003130: 00472483 lw s1,4(a4) -80003134: 41440433 sub s0,s0,s4 -80003138: ffc4f493 andi s1,s1,-4 -8000313c: 00940433 add s0,s0,s1 -80003140: 00c45413 srli s0,s0,0xc -80003144: fff40413 addi s0,s0,-1 -80003148: 00c41413 slli s0,s0,0xc -8000314c: 00f44e63 blt s0,a5,80003168 <_malloc_trim_r+0x70> -80003150: 00000593 li a1,0 -80003154: 00090513 mv a0,s2 -80003158: fd0ff0ef jal ra,80002928 <_sbrk_r> -8000315c: 0089a783 lw a5,8(s3) -80003160: 009787b3 add a5,a5,s1 -80003164: 02f50863 beq a0,a5,80003194 <_malloc_trim_r+0x9c> -80003168: 00090513 mv a0,s2 -8000316c: a44ff0ef jal ra,800023b0 <__malloc_unlock> -80003170: 01c12083 lw ra,28(sp) -80003174: 01812403 lw s0,24(sp) -80003178: 01412483 lw s1,20(sp) -8000317c: 01012903 lw s2,16(sp) -80003180: 00c12983 lw s3,12(sp) -80003184: 00812a03 lw s4,8(sp) -80003188: 00000513 li a0,0 -8000318c: 02010113 addi sp,sp,32 -80003190: 00008067 ret -80003194: 408005b3 neg a1,s0 -80003198: 00090513 mv a0,s2 -8000319c: f8cff0ef jal ra,80002928 <_sbrk_r> -800031a0: fff00793 li a5,-1 -800031a4: 04f50863 beq a0,a5,800031f4 <_malloc_trim_r+0xfc> -800031a8: 12818793 addi a5,gp,296 # 80004930 <__malloc_current_mallinfo> -800031ac: 0007a703 lw a4,0(a5) -800031b0: 0089a683 lw a3,8(s3) -800031b4: 408484b3 sub s1,s1,s0 -800031b8: 0014e493 ori s1,s1,1 -800031bc: 40870433 sub s0,a4,s0 -800031c0: 00090513 mv a0,s2 -800031c4: 0096a223 sw s1,4(a3) -800031c8: 0087a023 sw s0,0(a5) -800031cc: 9e4ff0ef jal ra,800023b0 <__malloc_unlock> -800031d0: 01c12083 lw ra,28(sp) -800031d4: 01812403 lw s0,24(sp) -800031d8: 01412483 lw s1,20(sp) -800031dc: 01012903 lw s2,16(sp) -800031e0: 00c12983 lw s3,12(sp) -800031e4: 00812a03 lw s4,8(sp) -800031e8: 00100513 li a0,1 -800031ec: 02010113 addi sp,sp,32 -800031f0: 00008067 ret -800031f4: 00000593 li a1,0 -800031f8: 00090513 mv a0,s2 -800031fc: f2cff0ef jal ra,80002928 <_sbrk_r> -80003200: 0089a703 lw a4,8(s3) -80003204: 00f00693 li a3,15 -80003208: 40e507b3 sub a5,a0,a4 -8000320c: f4f6dee3 bge a3,a5,80003168 <_malloc_trim_r+0x70> -80003210: 0d01a683 lw a3,208(gp) # 800048d8 <__malloc_sbrk_base> -80003214: 0017e793 ori a5,a5,1 -80003218: 00f72223 sw a5,4(a4) -8000321c: 40d50533 sub a0,a0,a3 -80003220: 12a1a423 sw a0,296(gp) # 80004930 <__malloc_current_mallinfo> -80003224: f45ff06f j 80003168 <_malloc_trim_r+0x70> - -80003228 <_free_r>: -80003228: 12058463 beqz a1,80003350 <_free_r+0x128> -8000322c: ff010113 addi sp,sp,-16 -80003230: 00812423 sw s0,8(sp) -80003234: 00912223 sw s1,4(sp) -80003238: 00058413 mv s0,a1 -8000323c: 00050493 mv s1,a0 -80003240: 00112623 sw ra,12(sp) -80003244: 968ff0ef jal ra,800023ac <__malloc_lock> -80003248: ffc42803 lw a6,-4(s0) -8000324c: ff840713 addi a4,s0,-8 -80003250: ffe87793 andi a5,a6,-2 -80003254: 00f70633 add a2,a4,a5 -80003258: cc018593 addi a1,gp,-832 # 800044c8 <__malloc_av_> -8000325c: 00462683 lw a3,4(a2) -80003260: 0085a503 lw a0,8(a1) -80003264: ffc6f693 andi a3,a3,-4 -80003268: 1ac50663 beq a0,a2,80003414 <_free_r+0x1ec> -8000326c: 00d62223 sw a3,4(a2) -80003270: 00187813 andi a6,a6,1 -80003274: 00d60533 add a0,a2,a3 -80003278: 08081e63 bnez a6,80003314 <_free_r+0xec> -8000327c: ff842303 lw t1,-8(s0) -80003280: 00452803 lw a6,4(a0) -80003284: 40670733 sub a4,a4,t1 -80003288: 00872883 lw a7,8(a4) -8000328c: cc818513 addi a0,gp,-824 # 800044d0 <__malloc_av_+0x8> -80003290: 006787b3 add a5,a5,t1 -80003294: 00187813 andi a6,a6,1 -80003298: 12a88e63 beq a7,a0,800033d4 <_free_r+0x1ac> -8000329c: 00c72303 lw t1,12(a4) -800032a0: 0068a623 sw t1,12(a7) -800032a4: 01132423 sw a7,8(t1) -800032a8: 1c080e63 beqz a6,80003484 <_free_r+0x25c> -800032ac: 0017e693 ori a3,a5,1 -800032b0: 00d72223 sw a3,4(a4) -800032b4: 00f62023 sw a5,0(a2) -800032b8: 1ff00693 li a3,511 -800032bc: 0af6e663 bltu a3,a5,80003368 <_free_r+0x140> -800032c0: ff87f693 andi a3,a5,-8 -800032c4: 00868693 addi a3,a3,8 -800032c8: 0045a503 lw a0,4(a1) -800032cc: 00d586b3 add a3,a1,a3 -800032d0: 0006a603 lw a2,0(a3) -800032d4: 0057d813 srli a6,a5,0x5 -800032d8: 00100793 li a5,1 -800032dc: 010797b3 sll a5,a5,a6 -800032e0: 00a7e7b3 or a5,a5,a0 -800032e4: ff868513 addi a0,a3,-8 -800032e8: 00a72623 sw a0,12(a4) -800032ec: 00c72423 sw a2,8(a4) -800032f0: 00f5a223 sw a5,4(a1) -800032f4: 00e6a023 sw a4,0(a3) -800032f8: 00e62623 sw a4,12(a2) -800032fc: 00812403 lw s0,8(sp) -80003300: 00c12083 lw ra,12(sp) -80003304: 00048513 mv a0,s1 -80003308: 00412483 lw s1,4(sp) -8000330c: 01010113 addi sp,sp,16 -80003310: 8a0ff06f j 800023b0 <__malloc_unlock> -80003314: 00452503 lw a0,4(a0) -80003318: 00157513 andi a0,a0,1 -8000331c: 02051c63 bnez a0,80003354 <_free_r+0x12c> -80003320: 00d787b3 add a5,a5,a3 -80003324: cc818513 addi a0,gp,-824 # 800044d0 <__malloc_av_+0x8> -80003328: 00862683 lw a3,8(a2) -8000332c: 0017e893 ori a7,a5,1 -80003330: 00f70833 add a6,a4,a5 -80003334: 16a68463 beq a3,a0,8000349c <_free_r+0x274> -80003338: 00c62603 lw a2,12(a2) -8000333c: 00c6a623 sw a2,12(a3) -80003340: 00d62423 sw a3,8(a2) -80003344: 01172223 sw a7,4(a4) -80003348: 00f82023 sw a5,0(a6) -8000334c: f6dff06f j 800032b8 <_free_r+0x90> -80003350: 00008067 ret -80003354: 0017e693 ori a3,a5,1 -80003358: fed42e23 sw a3,-4(s0) -8000335c: 00f62023 sw a5,0(a2) -80003360: 1ff00693 li a3,511 -80003364: f4f6fee3 bgeu a3,a5,800032c0 <_free_r+0x98> -80003368: 0097d693 srli a3,a5,0x9 -8000336c: 00400613 li a2,4 -80003370: 0ed66863 bltu a2,a3,80003460 <_free_r+0x238> -80003374: 0067d693 srli a3,a5,0x6 -80003378: 03968813 addi a6,a3,57 -8000337c: 03868613 addi a2,a3,56 -80003380: 00381813 slli a6,a6,0x3 -80003384: 01058833 add a6,a1,a6 -80003388: 00082683 lw a3,0(a6) -8000338c: ff880813 addi a6,a6,-8 -80003390: 12d80463 beq a6,a3,800034b8 <_free_r+0x290> -80003394: 0046a603 lw a2,4(a3) -80003398: ffc67613 andi a2,a2,-4 -8000339c: 00c7f663 bgeu a5,a2,800033a8 <_free_r+0x180> -800033a0: 0086a683 lw a3,8(a3) -800033a4: fed818e3 bne a6,a3,80003394 <_free_r+0x16c> -800033a8: 00c6a803 lw a6,12(a3) -800033ac: 01072623 sw a6,12(a4) -800033b0: 00d72423 sw a3,8(a4) -800033b4: 00812403 lw s0,8(sp) -800033b8: 00c12083 lw ra,12(sp) -800033bc: 00e82423 sw a4,8(a6) -800033c0: 00048513 mv a0,s1 -800033c4: 00412483 lw s1,4(sp) -800033c8: 00e6a623 sw a4,12(a3) -800033cc: 01010113 addi sp,sp,16 -800033d0: fe1fe06f j 800023b0 <__malloc_unlock> -800033d4: 14081263 bnez a6,80003518 <_free_r+0x2f0> -800033d8: 00c62583 lw a1,12(a2) -800033dc: 00862603 lw a2,8(a2) -800033e0: 00f687b3 add a5,a3,a5 -800033e4: 00812403 lw s0,8(sp) -800033e8: 00b62623 sw a1,12(a2) -800033ec: 00c5a423 sw a2,8(a1) -800033f0: 0017e693 ori a3,a5,1 -800033f4: 00c12083 lw ra,12(sp) -800033f8: 00d72223 sw a3,4(a4) -800033fc: 00048513 mv a0,s1 -80003400: 00f70733 add a4,a4,a5 -80003404: 00412483 lw s1,4(sp) -80003408: 00f72023 sw a5,0(a4) -8000340c: 01010113 addi sp,sp,16 -80003410: fa1fe06f j 800023b0 <__malloc_unlock> -80003414: 00187813 andi a6,a6,1 -80003418: 00d787b3 add a5,a5,a3 -8000341c: 02081063 bnez a6,8000343c <_free_r+0x214> -80003420: ff842503 lw a0,-8(s0) -80003424: 40a70733 sub a4,a4,a0 -80003428: 00c72683 lw a3,12(a4) -8000342c: 00872603 lw a2,8(a4) -80003430: 00a787b3 add a5,a5,a0 -80003434: 00d62623 sw a3,12(a2) -80003438: 00c6a423 sw a2,8(a3) -8000343c: 0017e613 ori a2,a5,1 -80003440: 0d41a683 lw a3,212(gp) # 800048dc <__malloc_trim_threshold> -80003444: 00c72223 sw a2,4(a4) -80003448: 00e5a423 sw a4,8(a1) -8000344c: ead7e8e3 bltu a5,a3,800032fc <_free_r+0xd4> -80003450: 0e01a583 lw a1,224(gp) # 800048e8 <__malloc_top_pad> -80003454: 00048513 mv a0,s1 -80003458: ca1ff0ef jal ra,800030f8 <_malloc_trim_r> -8000345c: ea1ff06f j 800032fc <_free_r+0xd4> -80003460: 01400613 li a2,20 -80003464: 02d67463 bgeu a2,a3,8000348c <_free_r+0x264> -80003468: 05400613 li a2,84 -8000346c: 06d66463 bltu a2,a3,800034d4 <_free_r+0x2ac> -80003470: 00c7d693 srli a3,a5,0xc -80003474: 06f68813 addi a6,a3,111 -80003478: 06e68613 addi a2,a3,110 -8000347c: 00381813 slli a6,a6,0x3 -80003480: f05ff06f j 80003384 <_free_r+0x15c> -80003484: 00d787b3 add a5,a5,a3 -80003488: ea1ff06f j 80003328 <_free_r+0x100> -8000348c: 05c68813 addi a6,a3,92 -80003490: 05b68613 addi a2,a3,91 -80003494: 00381813 slli a6,a6,0x3 -80003498: eedff06f j 80003384 <_free_r+0x15c> -8000349c: 00e5aa23 sw a4,20(a1) -800034a0: 00e5a823 sw a4,16(a1) -800034a4: 00a72623 sw a0,12(a4) -800034a8: 00a72423 sw a0,8(a4) -800034ac: 01172223 sw a7,4(a4) -800034b0: 00f82023 sw a5,0(a6) -800034b4: e49ff06f j 800032fc <_free_r+0xd4> -800034b8: 0045a503 lw a0,4(a1) -800034bc: 40265613 srai a2,a2,0x2 -800034c0: 00100793 li a5,1 -800034c4: 00c79633 sll a2,a5,a2 -800034c8: 00a66633 or a2,a2,a0 -800034cc: 00c5a223 sw a2,4(a1) -800034d0: eddff06f j 800033ac <_free_r+0x184> -800034d4: 15400613 li a2,340 -800034d8: 00d66c63 bltu a2,a3,800034f0 <_free_r+0x2c8> -800034dc: 00f7d693 srli a3,a5,0xf -800034e0: 07868813 addi a6,a3,120 -800034e4: 07768613 addi a2,a3,119 -800034e8: 00381813 slli a6,a6,0x3 -800034ec: e99ff06f j 80003384 <_free_r+0x15c> -800034f0: 55400613 li a2,1364 -800034f4: 00d66c63 bltu a2,a3,8000350c <_free_r+0x2e4> -800034f8: 0127d693 srli a3,a5,0x12 -800034fc: 07d68813 addi a6,a3,125 -80003500: 07c68613 addi a2,a3,124 -80003504: 00381813 slli a6,a6,0x3 -80003508: e7dff06f j 80003384 <_free_r+0x15c> -8000350c: 3f800813 li a6,1016 -80003510: 07e00613 li a2,126 -80003514: e71ff06f j 80003384 <_free_r+0x15c> -80003518: 0017e693 ori a3,a5,1 -8000351c: 00d72223 sw a3,4(a4) -80003520: 00f62023 sw a5,0(a2) -80003524: dd9ff06f j 800032fc <_free_r+0xd4> - -80003528 <_lseek_r>: -80003528: ff010113 addi sp,sp,-16 -8000352c: 00058713 mv a4,a1 -80003530: 00812423 sw s0,8(sp) -80003534: 00912223 sw s1,4(sp) -80003538: 00060593 mv a1,a2 -8000353c: 00050413 mv s0,a0 -80003540: 00068613 mv a2,a3 -80003544: 00070513 mv a0,a4 -80003548: 00112623 sw ra,12(sp) -8000354c: 1801a623 sw zero,396(gp) # 80004994 -80003550: 460000ef jal ra,800039b0 <_lseek> -80003554: fff00793 li a5,-1 -80003558: 00f50c63 beq a0,a5,80003570 <_lseek_r+0x48> -8000355c: 00c12083 lw ra,12(sp) -80003560: 00812403 lw s0,8(sp) -80003564: 00412483 lw s1,4(sp) -80003568: 01010113 addi sp,sp,16 -8000356c: 00008067 ret -80003570: 18c1a783 lw a5,396(gp) # 80004994 -80003574: fe0784e3 beqz a5,8000355c <_lseek_r+0x34> -80003578: 00c12083 lw ra,12(sp) -8000357c: 00f42023 sw a5,0(s0) -80003580: 00812403 lw s0,8(sp) -80003584: 00412483 lw s1,4(sp) -80003588: 01010113 addi sp,sp,16 -8000358c: 00008067 ret - -80003590 <__swhatbuf_r>: -80003590: f9010113 addi sp,sp,-112 -80003594: 06812423 sw s0,104(sp) -80003598: 00058413 mv s0,a1 -8000359c: 00e59583 lh a1,14(a1) -800035a0: 06912223 sw s1,100(sp) -800035a4: 07212023 sw s2,96(sp) -800035a8: 06112623 sw ra,108(sp) -800035ac: 00060493 mv s1,a2 -800035b0: 00068913 mv s2,a3 -800035b4: 0405ca63 bltz a1,80003608 <__swhatbuf_r+0x78> -800035b8: 00810613 addi a2,sp,8 -800035bc: 22c000ef jal ra,800037e8 <_fstat_r> -800035c0: 04054463 bltz a0,80003608 <__swhatbuf_r+0x78> -800035c4: 00c12703 lw a4,12(sp) -800035c8: 0000f7b7 lui a5,0xf -800035cc: 06c12083 lw ra,108(sp) -800035d0: 00e7f7b3 and a5,a5,a4 -800035d4: ffffe737 lui a4,0xffffe -800035d8: 00e787b3 add a5,a5,a4 -800035dc: 06812403 lw s0,104(sp) -800035e0: 0017b793 seqz a5,a5 -800035e4: 00f92023 sw a5,0(s2) -800035e8: 40000793 li a5,1024 -800035ec: 00f4a023 sw a5,0(s1) -800035f0: 00001537 lui a0,0x1 -800035f4: 06412483 lw s1,100(sp) -800035f8: 06012903 lw s2,96(sp) -800035fc: 80050513 addi a0,a0,-2048 # 800 <_start-0x7ffff800> -80003600: 07010113 addi sp,sp,112 -80003604: 00008067 ret -80003608: 00c45783 lhu a5,12(s0) -8000360c: 00092023 sw zero,0(s2) -80003610: 0807f793 andi a5,a5,128 -80003614: 02078463 beqz a5,8000363c <__swhatbuf_r+0xac> -80003618: 06c12083 lw ra,108(sp) -8000361c: 06812403 lw s0,104(sp) -80003620: 04000793 li a5,64 -80003624: 00f4a023 sw a5,0(s1) -80003628: 06012903 lw s2,96(sp) -8000362c: 06412483 lw s1,100(sp) -80003630: 00000513 li a0,0 -80003634: 07010113 addi sp,sp,112 -80003638: 00008067 ret -8000363c: 06c12083 lw ra,108(sp) -80003640: 06812403 lw s0,104(sp) -80003644: 40000793 li a5,1024 -80003648: 00f4a023 sw a5,0(s1) -8000364c: 06012903 lw s2,96(sp) -80003650: 06412483 lw s1,100(sp) -80003654: 00000513 li a0,0 -80003658: 07010113 addi sp,sp,112 -8000365c: 00008067 ret - -80003660 <__smakebuf_r>: -80003660: 00c5d783 lhu a5,12(a1) -80003664: fe010113 addi sp,sp,-32 -80003668: 00812c23 sw s0,24(sp) -8000366c: 00112e23 sw ra,28(sp) -80003670: 00912a23 sw s1,20(sp) -80003674: 01212823 sw s2,16(sp) -80003678: 0027f793 andi a5,a5,2 -8000367c: 00058413 mv s0,a1 -80003680: 02078863 beqz a5,800036b0 <__smakebuf_r+0x50> -80003684: 04358793 addi a5,a1,67 -80003688: 00f5a023 sw a5,0(a1) -8000368c: 00f5a823 sw a5,16(a1) -80003690: 00100793 li a5,1 -80003694: 00f5aa23 sw a5,20(a1) -80003698: 01c12083 lw ra,28(sp) -8000369c: 01812403 lw s0,24(sp) -800036a0: 01412483 lw s1,20(sp) -800036a4: 01012903 lw s2,16(sp) -800036a8: 02010113 addi sp,sp,32 -800036ac: 00008067 ret -800036b0: 00c10693 addi a3,sp,12 -800036b4: 00810613 addi a2,sp,8 -800036b8: 00050493 mv s1,a0 -800036bc: ed5ff0ef jal ra,80003590 <__swhatbuf_r> -800036c0: 00812583 lw a1,8(sp) -800036c4: 00050913 mv s2,a0 -800036c8: 00048513 mv a0,s1 -800036cc: a38fe0ef jal ra,80001904 <_malloc_r> -800036d0: 00c41783 lh a5,12(s0) -800036d4: 04050863 beqz a0,80003724 <__smakebuf_r+0xc4> -800036d8: 80001737 lui a4,0x80001 -800036dc: fb070713 addi a4,a4,-80 # 80000fb0 <__BSS_END__+0xffffc618> -800036e0: 02e4ae23 sw a4,60(s1) -800036e4: 00812703 lw a4,8(sp) -800036e8: 00c12683 lw a3,12(sp) -800036ec: 0807e793 ori a5,a5,128 -800036f0: 00f41623 sh a5,12(s0) -800036f4: 00a42023 sw a0,0(s0) -800036f8: 00a42823 sw a0,16(s0) -800036fc: 00e42a23 sw a4,20(s0) -80003700: 04069863 bnez a3,80003750 <__smakebuf_r+0xf0> -80003704: 0127e7b3 or a5,a5,s2 -80003708: 01c12083 lw ra,28(sp) -8000370c: 00f41623 sh a5,12(s0) -80003710: 01812403 lw s0,24(sp) -80003714: 01412483 lw s1,20(sp) -80003718: 01012903 lw s2,16(sp) -8000371c: 02010113 addi sp,sp,32 -80003720: 00008067 ret -80003724: 2007f713 andi a4,a5,512 -80003728: f60718e3 bnez a4,80003698 <__smakebuf_r+0x38> -8000372c: ffc7f793 andi a5,a5,-4 -80003730: 0027e793 ori a5,a5,2 -80003734: 04340713 addi a4,s0,67 -80003738: 00f41623 sh a5,12(s0) -8000373c: 00100793 li a5,1 -80003740: 00e42023 sw a4,0(s0) -80003744: 00e42823 sw a4,16(s0) -80003748: 00f42a23 sw a5,20(s0) -8000374c: f4dff06f j 80003698 <__smakebuf_r+0x38> -80003750: 00e41583 lh a1,14(s0) -80003754: 00048513 mv a0,s1 -80003758: 0f4000ef jal ra,8000384c <_isatty_r> -8000375c: 00051663 bnez a0,80003768 <__smakebuf_r+0x108> -80003760: 00c41783 lh a5,12(s0) -80003764: fa1ff06f j 80003704 <__smakebuf_r+0xa4> -80003768: 00c45703 lhu a4,12(s0) -8000376c: ffc77713 andi a4,a4,-4 -80003770: 00176713 ori a4,a4,1 -80003774: 01071793 slli a5,a4,0x10 -80003778: 4107d793 srai a5,a5,0x10 -8000377c: f89ff06f j 80003704 <__smakebuf_r+0xa4> - -80003780 <_read_r>: -80003780: ff010113 addi sp,sp,-16 -80003784: 00058713 mv a4,a1 -80003788: 00812423 sw s0,8(sp) -8000378c: 00912223 sw s1,4(sp) -80003790: 00060593 mv a1,a2 -80003794: 00050413 mv s0,a0 -80003798: 00068613 mv a2,a3 -8000379c: 00070513 mv a0,a4 -800037a0: 00112623 sw ra,12(sp) -800037a4: 1801a623 sw zero,396(gp) # 80004994 -800037a8: 258000ef jal ra,80003a00 <_read> -800037ac: fff00793 li a5,-1 -800037b0: 00f50c63 beq a0,a5,800037c8 <_read_r+0x48> -800037b4: 00c12083 lw ra,12(sp) -800037b8: 00812403 lw s0,8(sp) -800037bc: 00412483 lw s1,4(sp) -800037c0: 01010113 addi sp,sp,16 -800037c4: 00008067 ret -800037c8: 18c1a783 lw a5,396(gp) # 80004994 -800037cc: fe0784e3 beqz a5,800037b4 <_read_r+0x34> -800037d0: 00c12083 lw ra,12(sp) -800037d4: 00f42023 sw a5,0(s0) -800037d8: 00812403 lw s0,8(sp) -800037dc: 00412483 lw s1,4(sp) -800037e0: 01010113 addi sp,sp,16 -800037e4: 00008067 ret - -800037e8 <_fstat_r>: -800037e8: ff010113 addi sp,sp,-16 -800037ec: 00058713 mv a4,a1 -800037f0: 00812423 sw s0,8(sp) -800037f4: 00912223 sw s1,4(sp) -800037f8: 00050413 mv s0,a0 -800037fc: 00060593 mv a1,a2 -80003800: 00070513 mv a0,a4 -80003804: 00112623 sw ra,12(sp) -80003808: 1801a623 sw zero,396(gp) # 80004994 -8000380c: 0f4000ef jal ra,80003900 <_fstat> -80003810: fff00793 li a5,-1 -80003814: 00f50c63 beq a0,a5,8000382c <_fstat_r+0x44> -80003818: 00c12083 lw ra,12(sp) -8000381c: 00812403 lw s0,8(sp) -80003820: 00412483 lw s1,4(sp) -80003824: 01010113 addi sp,sp,16 -80003828: 00008067 ret -8000382c: 18c1a783 lw a5,396(gp) # 80004994 -80003830: fe0784e3 beqz a5,80003818 <_fstat_r+0x30> -80003834: 00c12083 lw ra,12(sp) -80003838: 00f42023 sw a5,0(s0) -8000383c: 00812403 lw s0,8(sp) -80003840: 00412483 lw s1,4(sp) -80003844: 01010113 addi sp,sp,16 -80003848: 00008067 ret - -8000384c <_isatty_r>: -8000384c: ff010113 addi sp,sp,-16 -80003850: 00812423 sw s0,8(sp) -80003854: 00912223 sw s1,4(sp) -80003858: 00050413 mv s0,a0 -8000385c: 00058513 mv a0,a1 -80003860: 00112623 sw ra,12(sp) -80003864: 1801a623 sw zero,396(gp) # 80004994 -80003868: 108000ef jal ra,80003970 <_isatty> -8000386c: fff00793 li a5,-1 -80003870: 00f50c63 beq a0,a5,80003888 <_isatty_r+0x3c> -80003874: 00c12083 lw ra,12(sp) -80003878: 00812403 lw s0,8(sp) -8000387c: 00412483 lw s1,4(sp) -80003880: 01010113 addi sp,sp,16 -80003884: 00008067 ret -80003888: 18c1a783 lw a5,396(gp) # 80004994 -8000388c: fe0784e3 beqz a5,80003874 <_isatty_r+0x28> -80003890: 00c12083 lw ra,12(sp) -80003894: 00f42023 sw a5,0(s0) -80003898: 00812403 lw s0,8(sp) -8000389c: 00412483 lw s1,4(sp) -800038a0: 01010113 addi sp,sp,16 -800038a4: 00008067 ret - -800038a8 <_close>: -800038a8: ff010113 addi sp,sp,-16 -800038ac: 00112623 sw ra,12(sp) -800038b0: 00812423 sw s0,8(sp) -800038b4: 00000593 li a1,0 -800038b8: 00000613 li a2,0 -800038bc: 00000693 li a3,0 -800038c0: 00000713 li a4,0 -800038c4: 00000793 li a5,0 -800038c8: 03900893 li a7,57 -800038cc: 00000073 ecall -800038d0: 00050413 mv s0,a0 -800038d4: 00054c63 bltz a0,800038ec <_close+0x44> -800038d8: 00c12083 lw ra,12(sp) -800038dc: 00040513 mv a0,s0 -800038e0: 00812403 lw s0,8(sp) -800038e4: 01010113 addi sp,sp,16 -800038e8: 00008067 ret -800038ec: 40800433 neg s0,s0 -800038f0: 2f0000ef jal ra,80003be0 <__errno> -800038f4: 00852023 sw s0,0(a0) -800038f8: fff00413 li s0,-1 -800038fc: fddff06f j 800038d8 <_close+0x30> - -80003900 <_fstat>: -80003900: f7010113 addi sp,sp,-144 -80003904: 08912223 sw s1,132(sp) -80003908: 08112623 sw ra,140(sp) -8000390c: 00058493 mv s1,a1 -80003910: 08812423 sw s0,136(sp) -80003914: 00010593 mv a1,sp -80003918: 00000613 li a2,0 -8000391c: 00000693 li a3,0 -80003920: 00000713 li a4,0 -80003924: 00000793 li a5,0 -80003928: 05000893 li a7,80 -8000392c: 00000073 ecall -80003930: 00050413 mv s0,a0 -80003934: 02054463 bltz a0,8000395c <_fstat+0x5c> -80003938: 00048513 mv a0,s1 -8000393c: 00010593 mv a1,sp -80003940: 1fc000ef jal ra,80003b3c <_conv_stat> -80003944: 08c12083 lw ra,140(sp) -80003948: 00040513 mv a0,s0 -8000394c: 08812403 lw s0,136(sp) -80003950: 08412483 lw s1,132(sp) -80003954: 09010113 addi sp,sp,144 -80003958: 00008067 ret -8000395c: 40800433 neg s0,s0 -80003960: 280000ef jal ra,80003be0 <__errno> -80003964: 00852023 sw s0,0(a0) -80003968: fff00413 li s0,-1 -8000396c: fcdff06f j 80003938 <_fstat+0x38> - -80003970 <_isatty>: -80003970: f9010113 addi sp,sp,-112 -80003974: 00810593 addi a1,sp,8 -80003978: 06112623 sw ra,108(sp) -8000397c: f85ff0ef jal ra,80003900 <_fstat> -80003980: fff00793 li a5,-1 -80003984: 00f50e63 beq a0,a5,800039a0 <_isatty+0x30> -80003988: 00c12503 lw a0,12(sp) -8000398c: 06c12083 lw ra,108(sp) -80003990: 00d55513 srli a0,a0,0xd -80003994: 00157513 andi a0,a0,1 -80003998: 07010113 addi sp,sp,112 -8000399c: 00008067 ret -800039a0: 06c12083 lw ra,108(sp) -800039a4: 00000513 li a0,0 -800039a8: 07010113 addi sp,sp,112 -800039ac: 00008067 ret - -800039b0 <_lseek>: -800039b0: ff010113 addi sp,sp,-16 -800039b4: 00112623 sw ra,12(sp) -800039b8: 00812423 sw s0,8(sp) -800039bc: 00000693 li a3,0 -800039c0: 00000713 li a4,0 -800039c4: 00000793 li a5,0 -800039c8: 03e00893 li a7,62 -800039cc: 00000073 ecall -800039d0: 00050413 mv s0,a0 -800039d4: 00054c63 bltz a0,800039ec <_lseek+0x3c> -800039d8: 00c12083 lw ra,12(sp) -800039dc: 00040513 mv a0,s0 -800039e0: 00812403 lw s0,8(sp) -800039e4: 01010113 addi sp,sp,16 -800039e8: 00008067 ret -800039ec: 40800433 neg s0,s0 -800039f0: 1f0000ef jal ra,80003be0 <__errno> -800039f4: 00852023 sw s0,0(a0) -800039f8: fff00413 li s0,-1 -800039fc: fddff06f j 800039d8 <_lseek+0x28> - -80003a00 <_read>: -80003a00: ff010113 addi sp,sp,-16 -80003a04: 00112623 sw ra,12(sp) -80003a08: 00812423 sw s0,8(sp) -80003a0c: 00000693 li a3,0 -80003a10: 00000713 li a4,0 -80003a14: 00000793 li a5,0 -80003a18: 03f00893 li a7,63 -80003a1c: 00000073 ecall -80003a20: 00050413 mv s0,a0 -80003a24: 00054c63 bltz a0,80003a3c <_read+0x3c> -80003a28: 00c12083 lw ra,12(sp) -80003a2c: 00040513 mv a0,s0 -80003a30: 00812403 lw s0,8(sp) -80003a34: 01010113 addi sp,sp,16 -80003a38: 00008067 ret -80003a3c: 40800433 neg s0,s0 -80003a40: 1a0000ef jal ra,80003be0 <__errno> -80003a44: 00852023 sw s0,0(a0) -80003a48: fff00413 li s0,-1 -80003a4c: fddff06f j 80003a28 <_read+0x28> - -80003a50 <_sbrk>: -80003a50: 0e41a783 lw a5,228(gp) # 800048ec -80003a54: ff010113 addi sp,sp,-16 -80003a58: 00112623 sw ra,12(sp) -80003a5c: 00050813 mv a6,a0 -80003a60: 02079863 bnez a5,80003a90 <_sbrk+0x40> -80003a64: 00000513 li a0,0 -80003a68: 00000593 li a1,0 -80003a6c: 00000613 li a2,0 -80003a70: 00000693 li a3,0 -80003a74: 00000713 li a4,0 -80003a78: 0d600893 li a7,214 -80003a7c: 00000073 ecall -80003a80: fff00713 li a4,-1 -80003a84: 00050793 mv a5,a0 -80003a88: 04e50463 beq a0,a4,80003ad0 <_sbrk+0x80> -80003a8c: 0ea1a223 sw a0,228(gp) # 800048ec -80003a90: 00f80533 add a0,a6,a5 -80003a94: 00000593 li a1,0 -80003a98: 00000613 li a2,0 -80003a9c: 00000693 li a3,0 -80003aa0: 00000713 li a4,0 -80003aa4: 00000793 li a5,0 -80003aa8: 0d600893 li a7,214 -80003aac: 00000073 ecall -80003ab0: 0e41a783 lw a5,228(gp) # 800048ec -80003ab4: 00f80833 add a6,a6,a5 -80003ab8: 01051c63 bne a0,a6,80003ad0 <_sbrk+0x80> -80003abc: 00c12083 lw ra,12(sp) -80003ac0: 0ea1a223 sw a0,228(gp) # 800048ec -80003ac4: 00078513 mv a0,a5 -80003ac8: 01010113 addi sp,sp,16 -80003acc: 00008067 ret -80003ad0: 110000ef jal ra,80003be0 <__errno> -80003ad4: 00c12083 lw ra,12(sp) -80003ad8: 00c00793 li a5,12 -80003adc: 00f52023 sw a5,0(a0) -80003ae0: fff00513 li a0,-1 -80003ae4: 01010113 addi sp,sp,16 -80003ae8: 00008067 ret - -80003aec <_write>: -80003aec: ff010113 addi sp,sp,-16 -80003af0: 00112623 sw ra,12(sp) -80003af4: 00812423 sw s0,8(sp) -80003af8: 00000693 li a3,0 -80003afc: 00000713 li a4,0 -80003b00: 00000793 li a5,0 -80003b04: 04000893 li a7,64 -80003b08: 00000073 ecall -80003b0c: 00050413 mv s0,a0 -80003b10: 00054c63 bltz a0,80003b28 <_write+0x3c> -80003b14: 00c12083 lw ra,12(sp) -80003b18: 00040513 mv a0,s0 -80003b1c: 00812403 lw s0,8(sp) -80003b20: 01010113 addi sp,sp,16 -80003b24: 00008067 ret -80003b28: 40800433 neg s0,s0 -80003b2c: 0b4000ef jal ra,80003be0 <__errno> -80003b30: 00852023 sw s0,0(a0) -80003b34: fff00413 li s0,-1 -80003b38: fddff06f j 80003b14 <_write+0x28> - -80003b3c <_conv_stat>: -80003b3c: ff010113 addi sp,sp,-16 -80003b40: 0145a383 lw t2,20(a1) -80003b44: 0185a283 lw t0,24(a1) -80003b48: 01c5af83 lw t6,28(a1) -80003b4c: 0205af03 lw t5,32(a1) -80003b50: 0305ae83 lw t4,48(a1) -80003b54: 0405ae03 lw t3,64(a1) -80003b58: 0385a303 lw t1,56(a1) -80003b5c: 0485a803 lw a6,72(a1) -80003b60: 04c5a883 lw a7,76(a1) -80003b64: 0585a603 lw a2,88(a1) -80003b68: 00812623 sw s0,12(sp) -80003b6c: 00912423 sw s1,8(sp) -80003b70: 0105a403 lw s0,16(a1) -80003b74: 0085a483 lw s1,8(a1) -80003b78: 01212223 sw s2,4(sp) -80003b7c: 0005a903 lw s2,0(a1) -80003b80: 05c5a683 lw a3,92(a1) -80003b84: 0685a703 lw a4,104(a1) -80003b88: 06c5a783 lw a5,108(a1) -80003b8c: 01251023 sh s2,0(a0) -80003b90: 00951123 sh s1,2(a0) -80003b94: 00852223 sw s0,4(a0) -80003b98: 00751423 sh t2,8(a0) -80003b9c: 00551523 sh t0,10(a0) -80003ba0: 01f51623 sh t6,12(a0) -80003ba4: 01e51723 sh t5,14(a0) -80003ba8: 01d52823 sw t4,16(a0) -80003bac: 05c52623 sw t3,76(a0) -80003bb0: 04652423 sw t1,72(a0) -80003bb4: 01052c23 sw a6,24(a0) -80003bb8: 01152e23 sw a7,28(a0) -80003bbc: 02c52423 sw a2,40(a0) -80003bc0: 02d52623 sw a3,44(a0) -80003bc4: 00c12403 lw s0,12(sp) -80003bc8: 02e52c23 sw a4,56(a0) -80003bcc: 02f52e23 sw a5,60(a0) -80003bd0: 00812483 lw s1,8(sp) -80003bd4: 00412903 lw s2,4(sp) -80003bd8: 01010113 addi sp,sp,16 -80003bdc: 00008067 ret - -80003be0 <__errno>: -80003be0: 0cc1a503 lw a0,204(gp) # 800048d4 <_impure_ptr> -80003be4: 00008067 ret +80000c28 <__call_exitprocs>: +80000c28: fd010113 addi sp,sp,-48 +80000c2c: 01412c23 sw s4,24(sp) +80000c30: cc01aa03 lw s4,-832(gp) # 800014c8 <_global_impure_ptr> +80000c34: 03212023 sw s2,32(sp) +80000c38: 02112623 sw ra,44(sp) +80000c3c: 148a2903 lw s2,328(s4) +80000c40: 02812423 sw s0,40(sp) +80000c44: 02912223 sw s1,36(sp) +80000c48: 01312e23 sw s3,28(sp) +80000c4c: 01512a23 sw s5,20(sp) +80000c50: 01612823 sw s6,16(sp) +80000c54: 01712623 sw s7,12(sp) +80000c58: 01812423 sw s8,8(sp) +80000c5c: 04090063 beqz s2,80000c9c <__call_exitprocs+0x74> +80000c60: 00050b13 mv s6,a0 +80000c64: 00058b93 mv s7,a1 +80000c68: 00100a93 li s5,1 +80000c6c: fff00993 li s3,-1 +80000c70: 00492483 lw s1,4(s2) +80000c74: fff48413 addi s0,s1,-1 +80000c78: 02044263 bltz s0,80000c9c <__call_exitprocs+0x74> +80000c7c: 00249493 slli s1,s1,0x2 +80000c80: 009904b3 add s1,s2,s1 +80000c84: 040b8463 beqz s7,80000ccc <__call_exitprocs+0xa4> +80000c88: 1044a783 lw a5,260(s1) +80000c8c: 05778063 beq a5,s7,80000ccc <__call_exitprocs+0xa4> +80000c90: fff40413 addi s0,s0,-1 +80000c94: ffc48493 addi s1,s1,-4 +80000c98: ff3416e3 bne s0,s3,80000c84 <__call_exitprocs+0x5c> +80000c9c: 02c12083 lw ra,44(sp) +80000ca0: 02812403 lw s0,40(sp) +80000ca4: 02412483 lw s1,36(sp) +80000ca8: 02012903 lw s2,32(sp) +80000cac: 01c12983 lw s3,28(sp) +80000cb0: 01812a03 lw s4,24(sp) +80000cb4: 01412a83 lw s5,20(sp) +80000cb8: 01012b03 lw s6,16(sp) +80000cbc: 00c12b83 lw s7,12(sp) +80000cc0: 00812c03 lw s8,8(sp) +80000cc4: 03010113 addi sp,sp,48 +80000cc8: 00008067 ret +80000ccc: 00492783 lw a5,4(s2) +80000cd0: 0044a683 lw a3,4(s1) +80000cd4: fff78793 addi a5,a5,-1 +80000cd8: 04878e63 beq a5,s0,80000d34 <__call_exitprocs+0x10c> +80000cdc: 0004a223 sw zero,4(s1) +80000ce0: fa0688e3 beqz a3,80000c90 <__call_exitprocs+0x68> +80000ce4: 18892783 lw a5,392(s2) +80000ce8: 008a9733 sll a4,s5,s0 +80000cec: 00492c03 lw s8,4(s2) +80000cf0: 00f777b3 and a5,a4,a5 +80000cf4: 02079263 bnez a5,80000d18 <__call_exitprocs+0xf0> +80000cf8: 000680e7 jalr a3 +80000cfc: 00492703 lw a4,4(s2) +80000d00: 148a2783 lw a5,328(s4) +80000d04: 01871463 bne a4,s8,80000d0c <__call_exitprocs+0xe4> +80000d08: f8f904e3 beq s2,a5,80000c90 <__call_exitprocs+0x68> +80000d0c: f80788e3 beqz a5,80000c9c <__call_exitprocs+0x74> +80000d10: 00078913 mv s2,a5 +80000d14: f5dff06f j 80000c70 <__call_exitprocs+0x48> +80000d18: 18c92783 lw a5,396(s2) +80000d1c: 0844a583 lw a1,132(s1) +80000d20: 00f77733 and a4,a4,a5 +80000d24: 00071c63 bnez a4,80000d3c <__call_exitprocs+0x114> +80000d28: 000b0513 mv a0,s6 +80000d2c: 000680e7 jalr a3 +80000d30: fcdff06f j 80000cfc <__call_exitprocs+0xd4> +80000d34: 00892223 sw s0,4(s2) +80000d38: fa9ff06f j 80000ce0 <__call_exitprocs+0xb8> +80000d3c: 00058513 mv a0,a1 +80000d40: 000680e7 jalr a3 +80000d44: fb9ff06f j 80000cfc <__call_exitprocs+0xd4> Disassembly of section .rodata: -80003be8 : -80003be8: 654c flw fa1,12(a0) -80003bea: 2774 fld fa3,200(a4) -80003bec: 74732073 csrs 0x747,t1 -80003bf0: 7261 lui tp,0xffff8 -80003bf2: 2e74 fld fa3,216(a2) -80003bf4: 2e2e fld ft8,200(sp) -80003bf6: 2820 fld fs0,80(s0) -80003bf8: 6854 flw fa3,20(s0) -80003bfa: 7369 lui t1,0xffffa -80003bfc: 6d20 flw fs0,88(a0) -80003bfe: 6769 lui a4,0x1a -80003c00: 7468 flw fa0,108(s0) -80003c02: 7420 flw fs0,104(s0) -80003c04: 6b61 lui s6,0x18 -80003c06: 2065 jal 80003cae <__errno+0xce> -80003c08: 2061 jal 80003c90 <__errno+0xb0> -80003c0a: 6c696877 0x6c696877 -80003c0e: 2965 jal 800040c6 -80003c10: 000a c.slli zero,0x2 -80003c12: 0000 unimp -80003c14: 3254 fld fa3,160(a2) -80003c16: 4620 lw s0,72(a2) -80003c18: 6961 lui s2,0x18 -80003c1a: 206c fld fa1,192(s0) -80003c1c: 00206e6f jal t3,80009c1e <__BSS_END__+0x5286> -80003c20: 3e2d7257 0x3e2d7257 -80003c24: 6572 flw fa0,28(sp) -80003c26: 6461 lui s0,0x18 -80003c28: 6120 flw fs0,64(a0) -80003c2a: 646e flw fs0,216(sp) -80003c2c: 7220 flw fs0,96(a2) -80003c2e: 7065 c.lui zero,0xffff9 -80003c30: 6165 addi sp,sp,112 -80003c32: 2874 fld fa3,208(s0) -80003c34: 20297257 0x20297257 -80003c38: 6574 flw fa3,76(a0) -80003c3a: 20737473 csrrci s0,0x207,6 -80003c3e: 6170 flw fa2,68(a0) -80003c40: 64657373 csrrci t1,0x646,10 -80003c44: 0a21 addi s4,s4,8 -80003c46: 0000 unimp -80003c48: 706d6953 0x706d6953 -80003c4c: 656c flw fa1,76(a0) -80003c4e: 4d20 lw s0,88(a0) -80003c50: 6961 lui s2,0x18 -80003c52: 0a6e slli s4,s4,0x1b -80003c54: 0000 unimp -80003c56: 0000 unimp -80003c58: 6574 flw fa3,76(a0) -80003c5a: 645f7473 csrrci s0,0x645,30 -80003c5e: 7669 lui a2,0xffffa -80003c60: 7265 lui tp,0xffff9 -80003c62: 636e6567 0x636e6567 -80003c66: 0a65 addi s4,s4,25 -80003c68: 0000 unimp -80003c6a: 0000 unimp -80003c6c: 6574 flw fa3,76(a0) -80003c6e: 775f7473 csrrci s0,0x775,30 -80003c72: 77617073 csrci 0x776,2 -80003c76: 0a6e slli s4,s4,0x1b -80003c78: 0000 unimp -80003c7a: 0000 unimp -80003c7c: 72616853 0x72616853 -80003c80: 6465 lui s0,0x19 -80003c82: 4d20 lw s0,88(a0) -80003c84: 6d65 lui s10,0x19 -80003c86: 2079726f jal tp,8009b68c <__BSS_END__+0x96cf4> -80003c8a: 6574 flw fa3,76(a0) -80003c8c: 000a7473 csrrci s0,ustatus,20 -80003c90: 7470 flw fa2,108(s0) -80003c92: 3a72 fld fs4,312(sp) -80003c94: 0020 addi s0,sp,8 -80003c96: 0000 unimp -80003c98: 6769724f fnmadd.q ft4,fs2,fs6,fa2 -80003c9c: 6e69 lui t3,0x1a -80003c9e: 6c61 lui s8,0x18 -80003ca0: 5620 lw s0,104(a2) -80003ca2: 6c61 lui s8,0x18 -80003ca4: 6575 lui a0,0x1d -80003ca6: 203a fld ft0,392(sp) -80003ca8: 0000 unimp -80003caa: 0000 unimp -80003cac: 6552 flw fa0,20(sp) -80003cae: 6461 lui s0,0x18 -80003cb0: 5620 lw s0,104(a2) -80003cb2: 6c61 lui s8,0x18 -80003cb4: 6575 lui a0,0x1d -80003cb6: 203a fld ft0,392(sp) -80003cb8: 0000 unimp -80003cba: 0000 unimp -80003cbc: 2d2d jal 800042f6 -80003cbe: 2d2d jal 800042f8 -80003cc0: 2d2d jal 800042fa -80003cc2: 2d2d jal 800042fc -80003cc4: 2d2d jal 800042fe -80003cc6: 2d2d jal 80004300 -80003cc8: 2d2d jal 80004302 -80003cca: 2d2d jal 80004304 -80003ccc: 2d2d jal 80004306 -80003cce: 0a2d addi s4,s4,11 -80003cd0: 0000 unimp -80003cd2: 0000 unimp -80003cd4: 7876 flw fa6,124(sp) -80003cd6: 735f 6170 6e77 0x6e776170735f -80003cdc: 775f 7261 7370 0x73707261775f -80003ce2: 6d20 flw fs0,88(a0) -80003ce4: 7461 lui s0,0xffff8 -80003ce6: 615f 6464 6b5f 0x6b5f6464615f -80003cec: 7265 lui tp,0xffff9 -80003cee: 656e flw fa0,216(sp) -80003cf0: 0a6c addi a1,sp,284 -80003cf2: 0000 unimp -80003cf4: 74696157 0x74696157 -80003cf8: 6e69 lui t3,0x1a -80003cfa: 6f742067 0x6f742067 -80003cfe: 6520 flw fs0,72(a0) -80003d00: 736e flw ft6,248(sp) -80003d02: 7275 lui tp,0xffffd -80003d04: 2065 jal 80003dac -80003d06: 6568746f jal s0,8008b35c <__BSS_END__+0x869c4> -80003d0a: 2072 fld ft0,280(sp) -80003d0c: 70726177 0x70726177 -80003d10: 72612073 csrs 0x726,sp -80003d14: 2065 jal 80003dbc -80003d16: 6f64 flw fs1,92(a4) -80003d18: 656e flw fa0,216(sp) -80003d1a: 2e2e fld ft8,200(sp) -80003d1c: 202e fld ft0,200(sp) -80003d1e: 5428 lw a0,104(s0) -80003d20: 6b61 lui s6,0x18 -80003d22: 7365 lui t1,0xffff9 -80003d24: 6120 flw fs0,64(a0) -80003d26: 7720 flw fs0,104(a4) -80003d28: 6968 flw fa0,84(a0) -80003d2a: 656c flw fa1,76(a0) -80003d2c: 0a29 addi s4,s4,10 -80003d2e: 0000 unimp -80003d30: 6574 flw fa3,76(a0) -80003d32: 6e697473 csrrci s0,0x6e6,18 -80003d36: 6d745f67 0x6d745f67 -80003d3a: 00000a63 beqz zero,80003d4e <__errno+0x16e> -80003d3e: 0000 unimp -80003d40: 6574 flw fa3,76(a0) -80003d42: 735f7473 csrrci s0,0x735,30 -80003d46: 6170 flw fa2,68(a0) -80003d48: 000a6e77 0xa6e77 -80003d4c: 0030 addi a2,sp,8 -80003d4e: 0000 unimp -80003d50: 0031 c.nop 12 -80003d52: 0000 unimp -80003d54: 0032 c.slli zero,0xc -80003d56: 0000 unimp -80003d58: 00000033 add zero,zero,zero -80003d5c: 0034 addi a3,sp,8 -80003d5e: 0000 unimp -80003d60: 0035 c.nop 13 -80003d62: 0000 unimp -80003d64: 0036 c.slli zero,0xd -80003d66: 0000 unimp -80003d68: 00000037 lui zero,0x0 -80003d6c: 0038 addi a4,sp,8 -80003d6e: 0000 unimp -80003d70: 0039 c.nop 14 -80003d72: 0000 unimp -80003d74: 0061 c.nop 24 -80003d76: 0000 unimp -80003d78: 0062 c.slli zero,0x18 -80003d7a: 0000 unimp -80003d7c: 00000063 beqz zero,80003d7c <__errno+0x19c> -80003d80: 0064 addi s1,sp,12 -80003d82: 0000 unimp -80003d84: 0065 c.nop 25 -80003d86: 0000 unimp -80003d88: 0066 c.slli zero,0x19 +80000d48 : +80000d48: 654c flw fa1,12(a0) +80000d4a: 2774 fld fa3,200(a4) +80000d4c: 74732073 csrs 0x747,t1 +80000d50: 7261 lui tp,0xffff8 +80000d52: 2e74 fld fa3,216(a2) +80000d54: 2e2e fld ft8,200(sp) +80000d56: 2820 fld fs0,80(s0) +80000d58: 6854 flw fa3,20(s0) +80000d5a: 7369 lui t1,0xffffa +80000d5c: 6d20 flw fs0,88(a0) +80000d5e: 6769 lui a4,0x1a +80000d60: 7468 flw fa0,108(s0) +80000d62: 7420 flw fs0,104(s0) +80000d64: 6b61 lui s6,0x18 +80000d66: 2065 jal 80000e0e <__call_exitprocs+0x1e6> +80000d68: 2061 jal 80000df0 <__call_exitprocs+0x1c8> +80000d6a: 6c696877 0x6c696877 +80000d6e: 2965 jal 80001226 +80000d70: 000a c.slli zero,0x2 +80000d72: 0000 unimp +80000d74: 3254 fld fa3,160(a2) +80000d76: 4620 lw s0,72(a2) +80000d78: 6961 lui s2,0x18 +80000d7a: 206c fld fa1,192(s0) +80000d7c: 00206e6f jal t3,80006d7e <__global_pointer$+0x5576> +80000d80: 3e2d7257 0x3e2d7257 +80000d84: 6572 flw fa0,28(sp) +80000d86: 6461 lui s0,0x18 +80000d88: 6120 flw fs0,64(a0) +80000d8a: 646e flw fs0,216(sp) +80000d8c: 7220 flw fs0,96(a2) +80000d8e: 7065 c.lui zero,0xffff9 +80000d90: 6165 addi sp,sp,112 +80000d92: 2874 fld fa3,208(s0) +80000d94: 20297257 0x20297257 +80000d98: 6574 flw fa3,76(a0) +80000d9a: 20737473 csrrci s0,0x207,6 +80000d9e: 6170 flw fa2,68(a0) +80000da0: 64657373 csrrci t1,0x646,10 +80000da4: 0a21 addi s4,s4,8 +80000da6: 0000 unimp +80000da8: 706d6953 0x706d6953 +80000dac: 656c flw fa1,76(a0) +80000dae: 4d20 lw s0,88(a0) +80000db0: 6961 lui s2,0x18 +80000db2: 0a6e slli s4,s4,0x1b +80000db4: 0000 unimp +80000db6: 0000 unimp +80000db8: 6574 flw fa3,76(a0) +80000dba: 645f7473 csrrci s0,0x645,30 +80000dbe: 7669 lui a2,0xffffa +80000dc0: 7265 lui tp,0xffff9 +80000dc2: 636e6567 0x636e6567 +80000dc6: 0a65 addi s4,s4,25 +80000dc8: 0000 unimp +80000dca: 0000 unimp +80000dcc: 6574 flw fa3,76(a0) +80000dce: 775f7473 csrrci s0,0x775,30 +80000dd2: 77617073 csrci 0x776,2 +80000dd6: 0a6e slli s4,s4,0x1b +80000dd8: 0000 unimp +80000dda: 0000 unimp +80000ddc: 72616853 0x72616853 +80000de0: 6465 lui s0,0x19 +80000de2: 4d20 lw s0,88(a0) +80000de4: 6d65 lui s10,0x19 +80000de6: 2079726f jal tp,800987ec <__global_pointer$+0x96fe4> +80000dea: 6574 flw fa3,76(a0) +80000dec: 000a7473 csrrci s0,ustatus,20 +80000df0: 7470 flw fa2,108(s0) +80000df2: 3a72 fld fs4,312(sp) +80000df4: 0020 addi s0,sp,8 +80000df6: 0000 unimp +80000df8: 6769724f fnmadd.q ft4,fs2,fs6,fa2 +80000dfc: 6e69 lui t3,0x1a +80000dfe: 6c61 lui s8,0x18 +80000e00: 5620 lw s0,104(a2) +80000e02: 6c61 lui s8,0x18 +80000e04: 6575 lui a0,0x1d +80000e06: 203a fld ft0,392(sp) +80000e08: 0000 unimp +80000e0a: 0000 unimp +80000e0c: 6552 flw fa0,20(sp) +80000e0e: 6461 lui s0,0x18 +80000e10: 5620 lw s0,104(a2) +80000e12: 6c61 lui s8,0x18 +80000e14: 6575 lui a0,0x1d +80000e16: 203a fld ft0,392(sp) +80000e18: 0000 unimp +80000e1a: 0000 unimp +80000e1c: 2d2d jal 80001456 +80000e1e: 2d2d jal 80001458 +80000e20: 2d2d jal 8000145a +80000e22: 2d2d jal 8000145c +80000e24: 2d2d jal 8000145e +80000e26: 2d2d jal 80001460 +80000e28: 2d2d jal 80001462 +80000e2a: 2d2d jal 80001464 +80000e2c: 2d2d jal 80001466 +80000e2e: 0a2d addi s4,s4,11 +80000e30: 0000 unimp +80000e32: 0000 unimp +80000e34: 7876 flw fa6,124(sp) +80000e36: 735f 6170 6e77 0x6e776170735f +80000e3c: 775f 7261 7370 0x73707261775f +80000e42: 6d20 flw fs0,88(a0) +80000e44: 7461 lui s0,0xffff8 +80000e46: 615f 6464 6b5f 0x6b5f6464615f +80000e4c: 7265 lui tp,0xffff9 +80000e4e: 656e flw fa0,216(sp) +80000e50: 0a6c addi a1,sp,284 +80000e52: 0000 unimp +80000e54: 74696157 0x74696157 +80000e58: 6e69 lui t3,0x1a +80000e5a: 6f742067 0x6f742067 +80000e5e: 6520 flw fs0,72(a0) +80000e60: 736e flw ft6,248(sp) +80000e62: 7275 lui tp,0xffffd +80000e64: 2065 jal 80000f0c +80000e66: 6568746f jal s0,800884bc <__global_pointer$+0x86cb4> +80000e6a: 2072 fld ft0,280(sp) +80000e6c: 70726177 0x70726177 +80000e70: 72612073 csrs 0x726,sp +80000e74: 2065 jal 80000f1c +80000e76: 6f64 flw fs1,92(a4) +80000e78: 656e flw fa0,216(sp) +80000e7a: 2e2e fld ft8,200(sp) +80000e7c: 202e fld ft0,200(sp) +80000e7e: 5428 lw a0,104(s0) +80000e80: 6b61 lui s6,0x18 +80000e82: 7365 lui t1,0xffff9 +80000e84: 6120 flw fs0,64(a0) +80000e86: 7720 flw fs0,104(a4) +80000e88: 6968 flw fa0,84(a0) +80000e8a: 656c flw fa1,76(a0) +80000e8c: 0a29 addi s4,s4,10 +80000e8e: 0000 unimp +80000e90: 6574 flw fa3,76(a0) +80000e92: 6e697473 csrrci s0,0x6e6,18 +80000e96: 6d745f67 0x6d745f67 +80000e9a: 00000a63 beqz zero,80000eae <__call_exitprocs+0x286> +80000e9e: 0000 unimp +80000ea0: 6574 flw fa3,76(a0) +80000ea2: 735f7473 csrrci s0,0x735,30 +80000ea6: 6170 flw fa2,68(a0) +80000ea8: 000a6e77 0xa6e77 +80000eac: 0030 addi a2,sp,8 +80000eae: 0000 unimp +80000eb0: 0031 c.nop 12 +80000eb2: 0000 unimp +80000eb4: 0032 c.slli zero,0xc +80000eb6: 0000 unimp +80000eb8: 00000033 add zero,zero,zero +80000ebc: 0034 addi a3,sp,8 +80000ebe: 0000 unimp +80000ec0: 0035 c.nop 13 +80000ec2: 0000 unimp +80000ec4: 0036 c.slli zero,0xd +80000ec6: 0000 unimp +80000ec8: 00000037 lui zero,0x0 +80000ecc: 0038 addi a4,sp,8 +80000ece: 0000 unimp +80000ed0: 0039 c.nop 14 +80000ed2: 0000 unimp +80000ed4: 0061 c.nop 24 +80000ed6: 0000 unimp +80000ed8: 0062 c.slli zero,0x18 +80000eda: 0000 unimp +80000edc: 00000063 beqz zero,80000edc <__call_exitprocs+0x2b4> +80000ee0: 0064 addi s1,sp,12 +80000ee2: 0000 unimp +80000ee4: 0065 c.nop 25 +80000ee6: 0000 unimp +80000ee8: 0066 c.slli zero,0x19 ... -80003d8c : -80003d8c: 3d4c fld fa1,184(a0) -80003d8e: 8000 0x8000 -80003d90: 3d50 fld fa2,184(a0) -80003d92: 8000 0x8000 -80003d94: 3d54 fld fa3,184(a0) -80003d96: 8000 0x8000 -80003d98: 3d58 fld fa4,184(a0) -80003d9a: 8000 0x8000 -80003d9c: 3d5c fld fa5,184(a0) -80003d9e: 8000 0x8000 -80003da0: 3d60 fld fs0,248(a0) -80003da2: 8000 0x8000 -80003da4: 3d64 fld fs1,248(a0) -80003da6: 8000 0x8000 -80003da8: 3d68 fld fa0,248(a0) -80003daa: 8000 0x8000 -80003dac: 3d6c fld fa1,248(a0) -80003dae: 8000 0x8000 -80003db0: 3d70 fld fa2,248(a0) -80003db2: 8000 0x8000 -80003db4: 3d74 fld fa3,248(a0) -80003db6: 8000 0x8000 -80003db8: 3d78 fld fa4,248(a0) -80003dba: 8000 0x8000 -80003dbc: 3d7c fld fa5,248(a0) -80003dbe: 8000 0x8000 -80003dc0: 3d80 fld fs0,56(a1) -80003dc2: 8000 0x8000 -80003dc4: 3d84 fld fs1,56(a1) -80003dc6: 8000 0x8000 -80003dc8: 3d88 fld fa0,56(a1) -80003dca: 8000 0x8000 -80003dcc: 5245 li tp,-15 -80003dce: 4f52 lw t5,20(sp) -80003dd0: 3a52 fld fs4,304(sp) -80003dd2: 7020 flw fs0,96(s0) -80003dd4: 5f6c636f jal t1,800ca3ca <__BSS_END__+0xc5a32> -80003dd8: 77617073 csrci 0x776,2 -80003ddc: 206e fld ft0,216(sp) -80003dde: 6f64 flw fs1,92(a4) -80003de0: 7365 lui t1,0xffff9 -80003de2: 276e fld fa4,216(sp) -80003de4: 2074 fld fa3,192(s0) -80003de6: 70707573 csrrci a0,0x707,0 -80003dea: 2074726f jal tp,8004b7f0 <__BSS_END__+0x46e58> -80003dee: 205a fld ft0,400(sp) -80003df0: 6964 flw fs1,84(a0) -80003df2: 656d lui a0,0x1b -80003df4: 736e flw ft6,248(sp) -80003df6: 6f69 lui t5,0x1a -80003df8: 206e fld ft0,216(sp) -80003dfa: 6579 lui a0,0x1e -80003dfc: 2174 fld fa3,192(a0) - ... +80000eec : +80000eec: 0eac addi a1,sp,856 +80000eee: 8000 0x8000 +80000ef0: 0eb0 addi a2,sp,856 +80000ef2: 8000 0x8000 +80000ef4: 0eb4 addi a3,sp,856 +80000ef6: 8000 0x8000 +80000ef8: 0eb8 addi a4,sp,856 +80000efa: 8000 0x8000 +80000efc: 0ebc addi a5,sp,856 +80000efe: 8000 0x8000 +80000f00: 0ec0 addi s0,sp,852 +80000f02: 8000 0x8000 +80000f04: 0ec4 addi s1,sp,852 +80000f06: 8000 0x8000 +80000f08: 0ec8 addi a0,sp,852 +80000f0a: 8000 0x8000 +80000f0c: 0ecc addi a1,sp,852 +80000f0e: 8000 0x8000 +80000f10: 0ed0 addi a2,sp,852 +80000f12: 8000 0x8000 +80000f14: 0ed4 addi a3,sp,852 +80000f16: 8000 0x8000 +80000f18: 0ed8 addi a4,sp,852 +80000f1a: 8000 0x8000 +80000f1c: 0edc addi a5,sp,852 +80000f1e: 8000 0x8000 +80000f20: 0ee0 addi s0,sp,860 +80000f22: 8000 0x8000 +80000f24: 0ee4 addi s1,sp,860 +80000f26: 8000 0x8000 +80000f28: 0ee8 addi a0,sp,860 +80000f2a: 8000 0x8000 Disassembly of section .init_array: -80004000 <__init_array_start>: -80004000: 0260 addi s0,sp,268 -80004002: 8000 0x8000 +80001000 <__init_array_start>: +80001000: 0260 addi s0,sp,268 +80001002: 8000 0x8000 Disassembly of section .data: -80004008 : -80004008: 0005 c.nop 1 -8000400a: 0000 unimp -8000400c: 0005 c.nop 1 -8000400e: 0000 unimp -80004010: 0005 c.nop 1 -80004012: 0000 unimp -80004014: 0005 c.nop 1 -80004016: 0000 unimp -80004018: 0006 c.slli zero,0x1 -8000401a: 0000 unimp -8000401c: 0006 c.slli zero,0x1 -8000401e: 0000 unimp -80004020: 0006 c.slli zero,0x1 -80004022: 0000 unimp -80004024: 0006 c.slli zero,0x1 -80004026: 0000 unimp -80004028: 00000007 0x7 -8000402c: 00000007 0x7 -80004030: 00000007 0x7 -80004034: 00000007 0x7 -80004038: 0008 0x8 -8000403a: 0000 unimp -8000403c: 0008 0x8 -8000403e: 0000 unimp -80004040: 0008 0x8 -80004042: 0000 unimp -80004044: 0008 0x8 +80001008 : +80001008: 0005 c.nop 1 +8000100a: 0000 unimp +8000100c: 0005 c.nop 1 +8000100e: 0000 unimp +80001010: 0005 c.nop 1 +80001012: 0000 unimp +80001014: 0005 c.nop 1 +80001016: 0000 unimp +80001018: 0006 c.slli zero,0x1 +8000101a: 0000 unimp +8000101c: 0006 c.slli zero,0x1 +8000101e: 0000 unimp +80001020: 0006 c.slli zero,0x1 +80001022: 0000 unimp +80001024: 0006 c.slli zero,0x1 +80001026: 0000 unimp +80001028: 00000007 0x7 +8000102c: 00000007 0x7 +80001030: 00000007 0x7 +80001034: 00000007 0x7 +80001038: 0008 0x8 +8000103a: 0000 unimp +8000103c: 0008 0x8 +8000103e: 0000 unimp +80001040: 0008 0x8 +80001042: 0000 unimp +80001044: 0008 0x8 ... -80004048 : -80004048: 0001 nop -8000404a: 0000 unimp -8000404c: 0001 nop -8000404e: 0000 unimp -80004050: 0001 nop -80004052: 0000 unimp -80004054: 0001 nop -80004056: 0000 unimp -80004058: 0001 nop -8000405a: 0000 unimp -8000405c: 0001 nop -8000405e: 0000 unimp -80004060: 0001 nop -80004062: 0000 unimp -80004064: 0001 nop -80004066: 0000 unimp -80004068: 0001 nop -8000406a: 0000 unimp -8000406c: 0001 nop -8000406e: 0000 unimp -80004070: 0001 nop -80004072: 0000 unimp -80004074: 0001 nop -80004076: 0000 unimp -80004078: 0001 nop -8000407a: 0000 unimp -8000407c: 0001 nop -8000407e: 0000 unimp -80004080: 0001 nop -80004082: 0000 unimp -80004084: 0001 nop +80001048 : +80001048: 0001 nop +8000104a: 0000 unimp +8000104c: 0001 nop +8000104e: 0000 unimp +80001050: 0001 nop +80001052: 0000 unimp +80001054: 0001 nop +80001056: 0000 unimp +80001058: 0001 nop +8000105a: 0000 unimp +8000105c: 0001 nop +8000105e: 0000 unimp +80001060: 0001 nop +80001062: 0000 unimp +80001064: 0001 nop +80001066: 0000 unimp +80001068: 0001 nop +8000106a: 0000 unimp +8000106c: 0001 nop +8000106e: 0000 unimp +80001070: 0001 nop +80001072: 0000 unimp +80001074: 0001 nop +80001076: 0000 unimp +80001078: 0001 nop +8000107a: 0000 unimp +8000107c: 0001 nop +8000107e: 0000 unimp +80001080: 0001 nop +80001082: 0000 unimp +80001084: 0001 nop ... -80004088 : -80004088: 0005 c.nop 1 -8000408a: 0000 unimp -8000408c: 0005 c.nop 1 -8000408e: 0000 unimp -80004090: 0005 c.nop 1 -80004092: 0000 unimp -80004094: 0005 c.nop 1 +80001088 : +80001088: 0005 c.nop 1 +8000108a: 0000 unimp +8000108c: 0005 c.nop 1 +8000108e: 0000 unimp +80001090: 0005 c.nop 1 +80001092: 0000 unimp +80001094: 0005 c.nop 1 ... -80004098 : -80004098: fffc fsw fa5,124(a5) -8000409a: ffff 0xffff -8000409c: 0000 unimp +80001098 : +80001098: fffc fsw fa5,124(a5) +8000109a: ffff 0xffff +8000109c: 0000 unimp ... -800040a0 : -800040a0: 0000 unimp -800040a2: 0000 unimp -800040a4: 438c lw a1,0(a5) -800040a6: 8000 0x8000 -800040a8: 43f4 lw a3,68(a5) -800040aa: 8000 0x8000 -800040ac: 445c lw a5,12(s0) -800040ae: 8000 0x8000 +800010a0 : +800010a0: 0000 unimp +800010a2: 0000 unimp +800010a4: 138c addi a1,sp,480 +800010a6: 8000 0x8000 +800010a8: 13f4 addi a3,sp,492 +800010aa: 8000 0x8000 +800010ac: 145c addi a5,sp,548 +800010ae: 8000 0x8000 ... -80004148: 0001 nop -8000414a: 0000 unimp -8000414c: 0000 unimp -8000414e: 0000 unimp -80004150: 330e fld ft6,224(sp) -80004152: abcd j 80004744 <__malloc_av_+0x27c> -80004154: 1234 addi a3,sp,296 -80004156: e66d bnez a2,80004240 -80004158: deec sw a1,124(a3) -8000415a: 0005 c.nop 1 -8000415c: 0000000b 0xb +80001148: 0001 nop +8000114a: 0000 unimp +8000114c: 0000 unimp +8000114e: 0000 unimp +80001150: 330e fld ft6,224(sp) +80001152: abcd j 80001744 <__BSS_END__+0x214> +80001154: 1234 addi a3,sp,296 +80001156: e66d bnez a2,80001240 +80001158: deec sw a1,124(a3) +8000115a: 0005 c.nop 1 +8000115c: 0000000b 0xb ... -800044c8 <__malloc_av_>: - ... -800044d0: 44c8 lw a0,12(s1) -800044d2: 8000 0x8000 -800044d4: 44c8 lw a0,12(s1) -800044d6: 8000 0x8000 -800044d8: 44d0 lw a2,12(s1) -800044da: 8000 0x8000 -800044dc: 44d0 lw a2,12(s1) -800044de: 8000 0x8000 -800044e0: 44d8 lw a4,12(s1) -800044e2: 8000 0x8000 -800044e4: 44d8 lw a4,12(s1) -800044e6: 8000 0x8000 -800044e8: 44e0 lw s0,76(s1) -800044ea: 8000 0x8000 -800044ec: 44e0 lw s0,76(s1) -800044ee: 8000 0x8000 -800044f0: 44e8 lw a0,76(s1) -800044f2: 8000 0x8000 -800044f4: 44e8 lw a0,76(s1) -800044f6: 8000 0x8000 -800044f8: 44f0 lw a2,76(s1) -800044fa: 8000 0x8000 -800044fc: 44f0 lw a2,76(s1) -800044fe: 8000 0x8000 -80004500: 44f8 lw a4,76(s1) -80004502: 8000 0x8000 -80004504: 44f8 lw a4,76(s1) -80004506: 8000 0x8000 -80004508: 4500 lw s0,8(a0) -8000450a: 8000 0x8000 -8000450c: 4500 lw s0,8(a0) -8000450e: 8000 0x8000 -80004510: 4508 lw a0,8(a0) -80004512: 8000 0x8000 -80004514: 4508 lw a0,8(a0) -80004516: 8000 0x8000 -80004518: 4510 lw a2,8(a0) -8000451a: 8000 0x8000 -8000451c: 4510 lw a2,8(a0) -8000451e: 8000 0x8000 -80004520: 4518 lw a4,8(a0) -80004522: 8000 0x8000 -80004524: 4518 lw a4,8(a0) -80004526: 8000 0x8000 -80004528: 4520 lw s0,72(a0) -8000452a: 8000 0x8000 -8000452c: 4520 lw s0,72(a0) -8000452e: 8000 0x8000 -80004530: 4528 lw a0,72(a0) -80004532: 8000 0x8000 -80004534: 4528 lw a0,72(a0) -80004536: 8000 0x8000 -80004538: 4530 lw a2,72(a0) -8000453a: 8000 0x8000 -8000453c: 4530 lw a2,72(a0) -8000453e: 8000 0x8000 -80004540: 4538 lw a4,72(a0) -80004542: 8000 0x8000 -80004544: 4538 lw a4,72(a0) -80004546: 8000 0x8000 -80004548: 4540 lw s0,12(a0) -8000454a: 8000 0x8000 -8000454c: 4540 lw s0,12(a0) -8000454e: 8000 0x8000 -80004550: 4548 lw a0,12(a0) -80004552: 8000 0x8000 -80004554: 4548 lw a0,12(a0) -80004556: 8000 0x8000 -80004558: 4550 lw a2,12(a0) -8000455a: 8000 0x8000 -8000455c: 4550 lw a2,12(a0) -8000455e: 8000 0x8000 -80004560: 4558 lw a4,12(a0) -80004562: 8000 0x8000 -80004564: 4558 lw a4,12(a0) -80004566: 8000 0x8000 -80004568: 4560 lw s0,76(a0) -8000456a: 8000 0x8000 -8000456c: 4560 lw s0,76(a0) -8000456e: 8000 0x8000 -80004570: 4568 lw a0,76(a0) -80004572: 8000 0x8000 -80004574: 4568 lw a0,76(a0) -80004576: 8000 0x8000 -80004578: 4570 lw a2,76(a0) -8000457a: 8000 0x8000 -8000457c: 4570 lw a2,76(a0) -8000457e: 8000 0x8000 -80004580: 4578 lw a4,76(a0) -80004582: 8000 0x8000 -80004584: 4578 lw a4,76(a0) -80004586: 8000 0x8000 -80004588: 4580 lw s0,8(a1) -8000458a: 8000 0x8000 -8000458c: 4580 lw s0,8(a1) -8000458e: 8000 0x8000 -80004590: 4588 lw a0,8(a1) -80004592: 8000 0x8000 -80004594: 4588 lw a0,8(a1) -80004596: 8000 0x8000 -80004598: 4590 lw a2,8(a1) -8000459a: 8000 0x8000 -8000459c: 4590 lw a2,8(a1) -8000459e: 8000 0x8000 -800045a0: 4598 lw a4,8(a1) -800045a2: 8000 0x8000 -800045a4: 4598 lw a4,8(a1) -800045a6: 8000 0x8000 -800045a8: 45a0 lw s0,72(a1) -800045aa: 8000 0x8000 -800045ac: 45a0 lw s0,72(a1) -800045ae: 8000 0x8000 -800045b0: 45a8 lw a0,72(a1) -800045b2: 8000 0x8000 -800045b4: 45a8 lw a0,72(a1) -800045b6: 8000 0x8000 -800045b8: 45b0 lw a2,72(a1) -800045ba: 8000 0x8000 -800045bc: 45b0 lw a2,72(a1) -800045be: 8000 0x8000 -800045c0: 45b8 lw a4,72(a1) -800045c2: 8000 0x8000 -800045c4: 45b8 lw a4,72(a1) -800045c6: 8000 0x8000 -800045c8: 45c0 lw s0,12(a1) -800045ca: 8000 0x8000 -800045cc: 45c0 lw s0,12(a1) -800045ce: 8000 0x8000 -800045d0: 45c8 lw a0,12(a1) -800045d2: 8000 0x8000 -800045d4: 45c8 lw a0,12(a1) -800045d6: 8000 0x8000 -800045d8: 45d0 lw a2,12(a1) -800045da: 8000 0x8000 -800045dc: 45d0 lw a2,12(a1) -800045de: 8000 0x8000 -800045e0: 45d8 lw a4,12(a1) -800045e2: 8000 0x8000 -800045e4: 45d8 lw a4,12(a1) -800045e6: 8000 0x8000 -800045e8: 45e0 lw s0,76(a1) -800045ea: 8000 0x8000 -800045ec: 45e0 lw s0,76(a1) -800045ee: 8000 0x8000 -800045f0: 45e8 lw a0,76(a1) -800045f2: 8000 0x8000 -800045f4: 45e8 lw a0,76(a1) -800045f6: 8000 0x8000 -800045f8: 45f0 lw a2,76(a1) -800045fa: 8000 0x8000 -800045fc: 45f0 lw a2,76(a1) -800045fe: 8000 0x8000 -80004600: 45f8 lw a4,76(a1) -80004602: 8000 0x8000 -80004604: 45f8 lw a4,76(a1) -80004606: 8000 0x8000 -80004608: 4600 lw s0,8(a2) -8000460a: 8000 0x8000 -8000460c: 4600 lw s0,8(a2) -8000460e: 8000 0x8000 -80004610: 4608 lw a0,8(a2) -80004612: 8000 0x8000 -80004614: 4608 lw a0,8(a2) -80004616: 8000 0x8000 -80004618: 4610 lw a2,8(a2) -8000461a: 8000 0x8000 -8000461c: 4610 lw a2,8(a2) -8000461e: 8000 0x8000 -80004620: 4618 lw a4,8(a2) -80004622: 8000 0x8000 -80004624: 4618 lw a4,8(a2) -80004626: 8000 0x8000 -80004628: 4620 lw s0,72(a2) -8000462a: 8000 0x8000 -8000462c: 4620 lw s0,72(a2) -8000462e: 8000 0x8000 -80004630: 4628 lw a0,72(a2) -80004632: 8000 0x8000 -80004634: 4628 lw a0,72(a2) -80004636: 8000 0x8000 -80004638: 4630 lw a2,72(a2) -8000463a: 8000 0x8000 -8000463c: 4630 lw a2,72(a2) -8000463e: 8000 0x8000 -80004640: 4638 lw a4,72(a2) -80004642: 8000 0x8000 -80004644: 4638 lw a4,72(a2) -80004646: 8000 0x8000 -80004648: 4640 lw s0,12(a2) -8000464a: 8000 0x8000 -8000464c: 4640 lw s0,12(a2) -8000464e: 8000 0x8000 -80004650: 4648 lw a0,12(a2) -80004652: 8000 0x8000 -80004654: 4648 lw a0,12(a2) -80004656: 8000 0x8000 -80004658: 4650 lw a2,12(a2) -8000465a: 8000 0x8000 -8000465c: 4650 lw a2,12(a2) -8000465e: 8000 0x8000 -80004660: 4658 lw a4,12(a2) -80004662: 8000 0x8000 -80004664: 4658 lw a4,12(a2) -80004666: 8000 0x8000 -80004668: 4660 lw s0,76(a2) -8000466a: 8000 0x8000 -8000466c: 4660 lw s0,76(a2) -8000466e: 8000 0x8000 -80004670: 4668 lw a0,76(a2) -80004672: 8000 0x8000 -80004674: 4668 lw a0,76(a2) -80004676: 8000 0x8000 -80004678: 4670 lw a2,76(a2) -8000467a: 8000 0x8000 -8000467c: 4670 lw a2,76(a2) -8000467e: 8000 0x8000 -80004680: 4678 lw a4,76(a2) -80004682: 8000 0x8000 -80004684: 4678 lw a4,76(a2) -80004686: 8000 0x8000 -80004688: 4680 lw s0,8(a3) -8000468a: 8000 0x8000 -8000468c: 4680 lw s0,8(a3) -8000468e: 8000 0x8000 -80004690: 4688 lw a0,8(a3) -80004692: 8000 0x8000 -80004694: 4688 lw a0,8(a3) -80004696: 8000 0x8000 -80004698: 4690 lw a2,8(a3) -8000469a: 8000 0x8000 -8000469c: 4690 lw a2,8(a3) -8000469e: 8000 0x8000 -800046a0: 4698 lw a4,8(a3) -800046a2: 8000 0x8000 -800046a4: 4698 lw a4,8(a3) -800046a6: 8000 0x8000 -800046a8: 46a0 lw s0,72(a3) -800046aa: 8000 0x8000 -800046ac: 46a0 lw s0,72(a3) -800046ae: 8000 0x8000 -800046b0: 46a8 lw a0,72(a3) -800046b2: 8000 0x8000 -800046b4: 46a8 lw a0,72(a3) -800046b6: 8000 0x8000 -800046b8: 46b0 lw a2,72(a3) -800046ba: 8000 0x8000 -800046bc: 46b0 lw a2,72(a3) -800046be: 8000 0x8000 -800046c0: 46b8 lw a4,72(a3) -800046c2: 8000 0x8000 -800046c4: 46b8 lw a4,72(a3) -800046c6: 8000 0x8000 -800046c8: 46c0 lw s0,12(a3) -800046ca: 8000 0x8000 -800046cc: 46c0 lw s0,12(a3) -800046ce: 8000 0x8000 -800046d0: 46c8 lw a0,12(a3) -800046d2: 8000 0x8000 -800046d4: 46c8 lw a0,12(a3) -800046d6: 8000 0x8000 -800046d8: 46d0 lw a2,12(a3) -800046da: 8000 0x8000 -800046dc: 46d0 lw a2,12(a3) -800046de: 8000 0x8000 -800046e0: 46d8 lw a4,12(a3) -800046e2: 8000 0x8000 -800046e4: 46d8 lw a4,12(a3) -800046e6: 8000 0x8000 -800046e8: 46e0 lw s0,76(a3) -800046ea: 8000 0x8000 -800046ec: 46e0 lw s0,76(a3) -800046ee: 8000 0x8000 -800046f0: 46e8 lw a0,76(a3) -800046f2: 8000 0x8000 -800046f4: 46e8 lw a0,76(a3) -800046f6: 8000 0x8000 -800046f8: 46f0 lw a2,76(a3) -800046fa: 8000 0x8000 -800046fc: 46f0 lw a2,76(a3) -800046fe: 8000 0x8000 -80004700: 46f8 lw a4,76(a3) -80004702: 8000 0x8000 -80004704: 46f8 lw a4,76(a3) -80004706: 8000 0x8000 -80004708: 4700 lw s0,8(a4) -8000470a: 8000 0x8000 -8000470c: 4700 lw s0,8(a4) -8000470e: 8000 0x8000 -80004710: 4708 lw a0,8(a4) -80004712: 8000 0x8000 -80004714: 4708 lw a0,8(a4) -80004716: 8000 0x8000 -80004718: 4710 lw a2,8(a4) -8000471a: 8000 0x8000 -8000471c: 4710 lw a2,8(a4) -8000471e: 8000 0x8000 -80004720: 4718 lw a4,8(a4) -80004722: 8000 0x8000 -80004724: 4718 lw a4,8(a4) -80004726: 8000 0x8000 -80004728: 4720 lw s0,72(a4) -8000472a: 8000 0x8000 -8000472c: 4720 lw s0,72(a4) -8000472e: 8000 0x8000 -80004730: 4728 lw a0,72(a4) -80004732: 8000 0x8000 -80004734: 4728 lw a0,72(a4) -80004736: 8000 0x8000 -80004738: 4730 lw a2,72(a4) -8000473a: 8000 0x8000 -8000473c: 4730 lw a2,72(a4) -8000473e: 8000 0x8000 -80004740: 4738 lw a4,72(a4) -80004742: 8000 0x8000 -80004744: 4738 lw a4,72(a4) -80004746: 8000 0x8000 -80004748: 4740 lw s0,12(a4) -8000474a: 8000 0x8000 -8000474c: 4740 lw s0,12(a4) -8000474e: 8000 0x8000 -80004750: 4748 lw a0,12(a4) -80004752: 8000 0x8000 -80004754: 4748 lw a0,12(a4) -80004756: 8000 0x8000 -80004758: 4750 lw a2,12(a4) -8000475a: 8000 0x8000 -8000475c: 4750 lw a2,12(a4) -8000475e: 8000 0x8000 -80004760: 4758 lw a4,12(a4) -80004762: 8000 0x8000 -80004764: 4758 lw a4,12(a4) -80004766: 8000 0x8000 -80004768: 4760 lw s0,76(a4) -8000476a: 8000 0x8000 -8000476c: 4760 lw s0,76(a4) -8000476e: 8000 0x8000 -80004770: 4768 lw a0,76(a4) -80004772: 8000 0x8000 -80004774: 4768 lw a0,76(a4) -80004776: 8000 0x8000 -80004778: 4770 lw a2,76(a4) -8000477a: 8000 0x8000 -8000477c: 4770 lw a2,76(a4) -8000477e: 8000 0x8000 -80004780: 4778 lw a4,76(a4) -80004782: 8000 0x8000 -80004784: 4778 lw a4,76(a4) -80004786: 8000 0x8000 -80004788: 4780 lw s0,8(a5) -8000478a: 8000 0x8000 -8000478c: 4780 lw s0,8(a5) -8000478e: 8000 0x8000 -80004790: 4788 lw a0,8(a5) -80004792: 8000 0x8000 -80004794: 4788 lw a0,8(a5) -80004796: 8000 0x8000 -80004798: 4790 lw a2,8(a5) -8000479a: 8000 0x8000 -8000479c: 4790 lw a2,8(a5) -8000479e: 8000 0x8000 -800047a0: 4798 lw a4,8(a5) -800047a2: 8000 0x8000 -800047a4: 4798 lw a4,8(a5) -800047a6: 8000 0x8000 -800047a8: 47a0 lw s0,72(a5) -800047aa: 8000 0x8000 -800047ac: 47a0 lw s0,72(a5) -800047ae: 8000 0x8000 -800047b0: 47a8 lw a0,72(a5) -800047b2: 8000 0x8000 -800047b4: 47a8 lw a0,72(a5) -800047b6: 8000 0x8000 -800047b8: 47b0 lw a2,72(a5) -800047ba: 8000 0x8000 -800047bc: 47b0 lw a2,72(a5) -800047be: 8000 0x8000 -800047c0: 47b8 lw a4,72(a5) -800047c2: 8000 0x8000 -800047c4: 47b8 lw a4,72(a5) -800047c6: 8000 0x8000 -800047c8: 47c0 lw s0,12(a5) -800047ca: 8000 0x8000 -800047cc: 47c0 lw s0,12(a5) -800047ce: 8000 0x8000 -800047d0: 47c8 lw a0,12(a5) -800047d2: 8000 0x8000 -800047d4: 47c8 lw a0,12(a5) -800047d6: 8000 0x8000 -800047d8: 47d0 lw a2,12(a5) -800047da: 8000 0x8000 -800047dc: 47d0 lw a2,12(a5) -800047de: 8000 0x8000 -800047e0: 47d8 lw a4,12(a5) -800047e2: 8000 0x8000 -800047e4: 47d8 lw a4,12(a5) -800047e6: 8000 0x8000 -800047e8: 47e0 lw s0,76(a5) -800047ea: 8000 0x8000 -800047ec: 47e0 lw s0,76(a5) -800047ee: 8000 0x8000 -800047f0: 47e8 lw a0,76(a5) -800047f2: 8000 0x8000 -800047f4: 47e8 lw a0,76(a5) -800047f6: 8000 0x8000 -800047f8: 47f0 lw a2,76(a5) -800047fa: 8000 0x8000 -800047fc: 47f0 lw a2,76(a5) -800047fe: 8000 0x8000 -80004800: 47f8 lw a4,76(a5) -80004802: 8000 0x8000 -80004804: 47f8 lw a4,76(a5) -80004806: 8000 0x8000 -80004808: 4800 lw s0,16(s0) -8000480a: 8000 0x8000 -8000480c: 4800 lw s0,16(s0) -8000480e: 8000 0x8000 -80004810: 4808 lw a0,16(s0) -80004812: 8000 0x8000 -80004814: 4808 lw a0,16(s0) -80004816: 8000 0x8000 -80004818: 4810 lw a2,16(s0) -8000481a: 8000 0x8000 -8000481c: 4810 lw a2,16(s0) -8000481e: 8000 0x8000 -80004820: 4818 lw a4,16(s0) -80004822: 8000 0x8000 -80004824: 4818 lw a4,16(s0) -80004826: 8000 0x8000 -80004828: 4820 lw s0,80(s0) -8000482a: 8000 0x8000 -8000482c: 4820 lw s0,80(s0) -8000482e: 8000 0x8000 -80004830: 4828 lw a0,80(s0) -80004832: 8000 0x8000 -80004834: 4828 lw a0,80(s0) -80004836: 8000 0x8000 -80004838: 4830 lw a2,80(s0) -8000483a: 8000 0x8000 -8000483c: 4830 lw a2,80(s0) -8000483e: 8000 0x8000 -80004840: 4838 lw a4,80(s0) -80004842: 8000 0x8000 -80004844: 4838 lw a4,80(s0) -80004846: 8000 0x8000 -80004848: 4840 lw s0,20(s0) -8000484a: 8000 0x8000 -8000484c: 4840 lw s0,20(s0) -8000484e: 8000 0x8000 -80004850: 4848 lw a0,20(s0) -80004852: 8000 0x8000 -80004854: 4848 lw a0,20(s0) -80004856: 8000 0x8000 -80004858: 4850 lw a2,20(s0) -8000485a: 8000 0x8000 -8000485c: 4850 lw a2,20(s0) -8000485e: 8000 0x8000 -80004860: 4858 lw a4,20(s0) -80004862: 8000 0x8000 -80004864: 4858 lw a4,20(s0) -80004866: 8000 0x8000 -80004868: 4860 lw s0,84(s0) -8000486a: 8000 0x8000 -8000486c: 4860 lw s0,84(s0) -8000486e: 8000 0x8000 -80004870: 4868 lw a0,84(s0) -80004872: 8000 0x8000 -80004874: 4868 lw a0,84(s0) -80004876: 8000 0x8000 -80004878: 4870 lw a2,84(s0) -8000487a: 8000 0x8000 -8000487c: 4870 lw a2,84(s0) -8000487e: 8000 0x8000 -80004880: 4878 lw a4,84(s0) -80004882: 8000 0x8000 -80004884: 4878 lw a4,84(s0) -80004886: 8000 0x8000 -80004888: 4880 lw s0,16(s1) -8000488a: 8000 0x8000 -8000488c: 4880 lw s0,16(s1) -8000488e: 8000 0x8000 -80004890: 4888 lw a0,16(s1) -80004892: 8000 0x8000 -80004894: 4888 lw a0,16(s1) -80004896: 8000 0x8000 -80004898: 4890 lw a2,16(s1) -8000489a: 8000 0x8000 -8000489c: 4890 lw a2,16(s1) -8000489e: 8000 0x8000 -800048a0: 4898 lw a4,16(s1) -800048a2: 8000 0x8000 -800048a4: 4898 lw a4,16(s1) -800048a6: 8000 0x8000 -800048a8: 48a0 lw s0,80(s1) -800048aa: 8000 0x8000 -800048ac: 48a0 lw s0,80(s1) -800048ae: 8000 0x8000 -800048b0: 48a8 lw a0,80(s1) -800048b2: 8000 0x8000 -800048b4: 48a8 lw a0,80(s1) -800048b6: 8000 0x8000 -800048b8: 48b0 lw a2,80(s1) -800048ba: 8000 0x8000 -800048bc: 48b0 lw a2,80(s1) -800048be: 8000 0x8000 -800048c0: 48b8 lw a4,80(s1) -800048c2: 8000 0x8000 -800048c4: 48b8 lw a4,80(s1) -800048c6: 8000 0x8000 -800048c8: 48c0 lw s0,20(s1) -800048ca: 8000 0x8000 -800048cc: 48c0 lw s0,20(s1) -800048ce: 8000 0x8000 - Disassembly of section .sdata: -800048d0 <_global_impure_ptr>: -800048d0: 40a0 lw s0,64(s1) -800048d2: 8000 0x8000 - -800048d4 <_impure_ptr>: -800048d4: 40a0 lw s0,64(s1) -800048d6: 8000 0x8000 - -800048d8 <__malloc_sbrk_base>: -800048d8: ffff 0xffff -800048da: ffff 0xffff - -800048dc <__malloc_trim_threshold>: -800048dc: 0000 unimp -800048de: 0002 c.slli64 zero +800014c8 <_global_impure_ptr>: +800014c8: 10a0 addi s0,sp,104 +800014ca: 8000 0x8000 Disassembly of section .sbss: -800048e0 <__malloc_max_total_mem>: -800048e0: 0000 unimp - ... - -800048e4 <__malloc_max_sbrked_mem>: -800048e4: 0000 unimp - ... - -800048e8 <__malloc_top_pad>: -800048e8: 0000 unimp - ... - -800048ec : -800048ec: 0000 unimp +800014cc : +800014cc: 0000 unimp ... Disassembly of section .bss: -800048f0 : +800014d0 : ... -80004930 <__malloc_current_mallinfo>: +80001510 : ... -80004958 : - ... - -80004968 : - ... - -80004978 : -80004978: 0000 unimp - ... - -8000497c : -8000497c: 0000 unimp - ... - -80004980 : -80004980: 0000 unimp - ... - -80004984 : -80004984: 0000 unimp - ... - -80004988 : -80004988: 0000 unimp - ... - -8000498c : -8000498c: 0000 unimp - ... - -80004990 : -80004990: 0000 unimp - ... - -80004994 : -80004994: 0000 unimp +80001520 : ... Disassembly of section .comment: @@ -5016,6 +1316,6 @@ Disassembly of section .riscv.attributes: 16: 6932 flw fs2,12(sp) 18: 7032 flw ft0,44(sp) 1a: 5f30 lw a2,120(a4) - 1c: 326d jal fffff9c6 <__BSS_END__+0x7fffb02e> + 1c: 326d jal fffff9c6 <__global_pointer$+0x7fffe1be> 1e: 3070 fld fa2,224(s0) ... diff --git a/runtime/tests/simple/vx_simple.elf b/runtime/tests/simple/vx_simple.elf index cba1ea90..364d27ae 100755 Binary files a/runtime/tests/simple/vx_simple.elf and b/runtime/tests/simple/vx_simple.elf differ diff --git a/runtime/tests/simple/vx_simple.hex b/runtime/tests/simple/vx_simple.hex index e7e3a97a..98fb7092 100644 --- a/runtime/tests/simple/vx_simple.hex +++ b/runtime/tests/simple/vx_simple.hex @@ -1,44 +1,44 @@ :0200000480007A :100000009705000093854569732560026B10B50064 -:10001000EF004068130510006B0005001385810D8B -:10002000138601193306A64093050000EF0010382F -:1000300017150000130545A8EF009023EF00502D81 -:08004000EF0080006F001024A6 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