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CACHE WORKING just needs lb/sb

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This commit is contained in:
felsabbagh3
2019-10-25 03:03:09 -04:00
parent 1e648c5819
commit 01efe02e8b
19 changed files with 2302 additions and 2358 deletions
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16
rtl/VX_writeback.v
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@@ -11,10 +11,12 @@ module VX_writeback (
VX_csr_wb_inter VX_csr_wb,
// Actual WB to GPR
VX_wb_inter VX_writeback_inter
VX_wb_inter VX_writeback_inter,
output wire no_slot_mem
);
assign no_slot_mem = mem_wb && (exec_wb || csr_wb);
wire exec_wb = (VX_inst_exec_wb.wb != 0) && (|VX_inst_exec_wb.wb_valid);
wire mem_wb = (VX_mem_wb.wb != 0) && (|VX_mem_wb.wb_valid);
@@ -22,29 +24,29 @@ module VX_writeback (
assign VX_writeback_inter.write_data = exec_wb ? VX_inst_exec_wb.alu_result :
mem_wb ? VX_mem_wb.loaded_data :
csr_wb ? VX_csr_wb.csr_result :
mem_wb ? VX_mem_wb.loaded_data :
0;
assign VX_writeback_inter.wb_valid = exec_wb ? VX_inst_exec_wb.wb_valid :
mem_wb ? VX_mem_wb.wb_valid :
csr_wb ? VX_csr_wb.valid :
0;
mem_wb ? VX_mem_wb.wb_valid :
0;
assign VX_writeback_inter.rd = exec_wb ? VX_inst_exec_wb.rd :
mem_wb ? VX_mem_wb.rd :
csr_wb ? VX_csr_wb.rd :
mem_wb ? VX_mem_wb.rd :
0;
assign VX_writeback_inter.wb = exec_wb ? VX_inst_exec_wb.wb :
mem_wb ? VX_mem_wb.wb :
csr_wb ? VX_csr_wb.wb :
mem_wb ? VX_mem_wb.wb :
0;
assign VX_writeback_inter.wb_warp_num = exec_wb ? VX_inst_exec_wb.wb_warp_num :
mem_wb ? VX_mem_wb.wb_warp_num :
csr_wb ? VX_csr_wb.warp_num :
mem_wb ? VX_mem_wb.wb_warp_num :
0;