rtl passing all tests

rtl/VX_register_file.v

@@ -8,8 +8,8 @@ module VX_register_file (
   input wire[4:0]   in_src1,
   input wire[4:0]   in_src2,
 
-  output wire[31:0] out_src1_data,
-  output wire[31:0] out_src2_data
+  output reg[31:0] out_src1_data,
+  output reg[31:0] out_src2_data
 );
 
 	reg[31:0] registers[31:0];
@@ -20,7 +20,12 @@ module VX_register_file (
 
 	wire write_enable;
 
-
+	// reg[5:0] i;
+	// always @(posedge clk) begin
+	// 	for (i = 0; i < 32; i++) begin
+	// 		$display("%d: %h",i, registers[i[4:0]]);
+	// 	end
+	// end
 
 	assign write_data     = in_data;
 	assign write_register = in_rd;
@@ -29,12 +34,15 @@ module VX_register_file (
 
 	always @(posedge clk) begin
 		if(write_enable) begin
+			// $display("Writing %h to %d",write_data, write_register);
 			registers[write_register] <= write_data;
 		end
 	end
 
-	assign out_src1_data = registers[in_src1];
-	assign out_src2_data = registers[in_src2];
+	always @(negedge clk) begin
+		out_src1_data <= registers[in_src1];
+		out_src2_data <= registers[in_src2];
+	end
 
 
 endmodule