Added Core Interface

rtl/interfaces/VX_gpu_dcache_dram_req_inter.v

@@ -0,0 +1,25 @@
+
+
+`include "../VX_cache/VX_cache_config.v"
+
+`ifndef VX_GPU_DRAM_DCACHE_REQ
+
+`define VX_GPU_DRAM_DCACHE_REQ
+
+interface VX_gpu_dcache_dram_req_inter ();
+
+	// DRAM Request
+    wire                              dram_req;
+    wire                              dram_req_write;
+    wire                              dram_req_read;
+    wire [31:0]                       dram_req_addr;
+    wire [31:0]                       dram_req_size;
+    wire [`BANK_LINE_SIZE_RNG][31:0]  dram_req_data;
+
+    // DRAM Cache can't accept response
+    wire                              dram_fill_accept;
+
+endinterface
+
+
+`endif

rtl/interfaces/VX_gpu_dcache_dram_res_inter.v

@@ -0,0 +1,19 @@
+
+
+
+`include "../VX_cache/VX_cache_config.v"
+
+`ifndef VX_GPU_DRAM_DCACHE_RES
+
+`define VX_GPU_DRAM_DCACHE_RES
+
+interface VX_gpu_dcache_dram_res_inter ();
+	// DRAM Rsponse
+    wire                              dram_fill_rsp;
+    wire [31:0]                       dram_fill_rsp_addr;
+    wire [`BANK_LINE_SIZE_RNG][31:0]  dram_fill_rsp_data;
+
+endinterface
+
+
+`endif

rtl/interfaces/VX_gpu_dcache_req_inter.v

@@ -0,0 +1,27 @@
+
+
+`include "../VX_cache/VX_cache_config.v"
+
+`ifndef VX_GPU_DCACHE_REQ
+
+`define VX_GPU_DCACHE_REQ
+
+interface VX_gpu_dcache_req_inter ();
+
+	// Core Request
+	wire [`NUMBER_REQUESTS-1:0]        core_req_valid;
+	wire [`NUMBER_REQUESTS-1:0][31:0]  core_req_addr;
+	wire [`NUMBER_REQUESTS-1:0][31:0]  core_req_writedata;
+	wire [2:0]                         core_req_mem_read;
+	wire [2:0]                         core_req_mem_write;
+    wire [4:0]                         core_req_rd;
+    wire [1:0]                         core_req_wb;
+    wire [`NW_M1:0]                    core_req_warp_num;
+
+    // Can't WB
+    wire                              core_no_wb_slot;
+
+endinterface
+
+
+`endif

rtl/interfaces/VX_gpu_dcache_res_inter.v

@@ -0,0 +1,24 @@
+
+
+`include "../VX_cache/VX_cache_config.v"
+
+`ifndef VX_GPU_DCACHE_RES
+
+`define VX_GPU_DCACHE_RES
+
+interface VX_gpu_dcache_res_inter ();
+
+	// Cache WB
+    wire [`NUMBER_REQUESTS-1:0]       core_wb_valid;
+    wire [4:0]                        core_wb_req_rd;
+    wire [1:0]                        core_wb_req_wb;
+    wire [`NW_M1:0]                   core_wb_warp_num;
+    wire [`NUMBER_REQUESTS-1:0][31:0] core_wb_readdata;
+
+    // Cache Full
+    wire                              delay_req;
+
+endinterface
+
+
+`endif