RTL code refactoring

2020-04-23 13:49:45 -04:00
parent 3cf1a5074b
commit 00a5122fd4
4 changed files with 138 additions and 145 deletions
--- a/hw/rtl/Vortex_Socket.v
+++ b/hw/rtl/Vortex_Socket.v
@@ -35,7 +35,6 @@ module Vortex_Socket (
        wire[`NUM_CORES-1:0]       cluster_io_valid;
        wire[`NUM_CORES-1:0][31:0] cluster_io_data;

-
        genvar curr_c;
        for (curr_c = 0; curr_c < `NUM_CORES; curr_c=curr_c+1) begin
            assign io_valid[curr_c] = cluster_io_valid[curr_c];