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RTL code refactoring

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This commit is contained in:
Blaise Tine
2020-04-23 13:49:45 -04:00
parent 3cf1a5074b
commit 00a5122fd4
4 changed files with 138 additions and 145 deletions
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108
hw/rtl/Vortex.v
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@@ -43,14 +43,12 @@ module Vortex #(
input wire [31:0] llc_snp_req_addr,
output wire llc_snp_req_ready,
// CSR request
//input wire csr_read_valid;
//input wire csr_write_valid;
//input wire [`CSR_WIDTH-1:0 csr_index;
//input wire csr_data_in;
//output wire [15:0] csr_data_out;
//output wire [15:0] csr_data_out;
output wire ebreak
);
@@ -64,9 +62,9 @@ module Vortex #(
wire schedule_delay;
// Dcache Interface
VX_cache_core_rsp_if #(.NUM_REQUESTS(`DNUM_REQUESTS)) dcache_rsp_if();
VX_cache_core_req_if #(.NUM_REQUESTS(`DNUM_REQUESTS)) dcache_req_if();
VX_cache_core_req_if #(.NUM_REQUESTS(`DNUM_REQUESTS)) dcache_req_qual_if();
VX_cache_core_rsp_if #(.NUM_REQUESTS(`DNUM_REQUESTS)) dcache_core_rsp_if();
VX_cache_core_req_if #(.NUM_REQUESTS(`DNUM_REQUESTS)) dcache_core_req_if();
VX_cache_core_req_if #(.NUM_REQUESTS(`DNUM_REQUESTS)) dcache_core_req_qual_if();
VX_cache_dram_req_if #(.BANK_LINE_WORDS(`DBANK_LINE_WORDS)) cache_dram_req_if();
VX_cache_dram_rsp_if #(.BANK_LINE_WORDS(`DBANK_LINE_WORDS)) cache_dram_rsp_if();
@@ -85,53 +83,53 @@ module Vortex #(
generate
for (i = 0; i < `DBANK_LINE_WORDS; i=i+1) begin
assign cache_dram_rsp_if.dram_rsp_data[i] = dram_rsp_data[i * 32 +: 32];
assign dram_req_data[i * 32 +: 32] = cache_dram_req_if.dram_req_data[i];
assign dram_req_data[i * 32 +: 32] = cache_dram_req_if.dram_req_data[i];
end
endgenerate
wire temp_io_valid = (!memory_delay)
&& (|dcache_req_if.core_req_valid)
&& (dcache_req_if.core_req_write[0] != `NO_MEM_WRITE)
&& (dcache_req_if.core_req_addr[0] == `IO_BUS_ADDR);
&& (|dcache_core_req_if.core_req_valid)
&& (dcache_core_req_if.core_req_write[0] != `NO_MEM_WRITE)
&& (dcache_core_req_if.core_req_addr[0] == `IO_BUS_ADDR);
wire [31:0] temp_io_data = dcache_req_if.core_req_data[0];
wire [31:0] temp_io_data = dcache_core_req_if.core_req_data[0];
assign io_valid = temp_io_valid;
assign io_data = temp_io_data;
assign dcache_req_qual_if.core_req_valid = dcache_req_if.core_req_valid & {`NUM_THREADS{~io_valid}};
assign dcache_req_qual_if.core_req_read = dcache_req_if.core_req_read;
assign dcache_req_qual_if.core_req_write = dcache_req_if.core_req_write;
assign dcache_req_qual_if.core_req_addr = dcache_req_if.core_req_addr;
assign dcache_req_qual_if.core_req_data = dcache_req_if.core_req_data;
assign dcache_core_req_qual_if.core_req_valid = dcache_core_req_if.core_req_valid & {`NUM_THREADS{~io_valid}};
assign dcache_core_req_qual_if.core_req_read = dcache_core_req_if.core_req_read;
assign dcache_core_req_qual_if.core_req_write = dcache_core_req_if.core_req_write;
assign dcache_core_req_qual_if.core_req_addr = dcache_core_req_if.core_req_addr;
assign dcache_core_req_qual_if.core_req_data = dcache_core_req_if.core_req_data;
assign dcache_req_if.core_req_ready = dcache_req_qual_if.core_req_ready;
assign dcache_core_req_if.core_req_ready = dcache_core_req_qual_if.core_req_ready;
assign dcache_req_qual_if.core_req_rd = dcache_req_if.core_req_rd;
assign dcache_req_qual_if.core_req_wb = dcache_req_if.core_req_wb;
assign dcache_req_qual_if.core_req_warp_num = dcache_req_if.core_req_warp_num;
assign dcache_req_qual_if.core_req_pc = dcache_req_if.core_req_pc;
assign dcache_core_req_qual_if.core_req_rd = dcache_core_req_if.core_req_rd;
assign dcache_core_req_qual_if.core_req_wb = dcache_core_req_if.core_req_wb;
assign dcache_core_req_qual_if.core_req_warp_num = dcache_core_req_if.core_req_warp_num;
assign dcache_core_req_qual_if.core_req_pc = dcache_core_req_if.core_req_pc;
VX_cache_core_rsp_if #(.NUM_REQUESTS(`INUM_REQUESTS)) icache_rsp_if();
VX_cache_core_req_if #(.NUM_REQUESTS(`INUM_REQUESTS)) icache_req_if();
VX_cache_core_rsp_if #(.NUM_REQUESTS(`INUM_REQUESTS)) icache_core_rsp_if();
VX_cache_core_req_if #(.NUM_REQUESTS(`INUM_REQUESTS)) icache_core_req_if();
VX_cache_dram_req_if #(.BANK_LINE_WORDS(`IBANK_LINE_WORDS)) gpu_icache_dram_req_if();
VX_cache_dram_rsp_if #(.BANK_LINE_WORDS(`IBANK_LINE_WORDS)) gpu_icache_dram_rsp_if();
VX_cache_dram_req_if #(.BANK_LINE_WORDS(`IBANK_LINE_WORDS)) icache_dram_req_if();
VX_cache_dram_rsp_if #(.BANK_LINE_WORDS(`IBANK_LINE_WORDS)) icache_dram_rsp_if();
assign gpu_icache_dram_rsp_if.dram_rsp_valid = I_dram_rsp_valid;
assign gpu_icache_dram_rsp_if.dram_rsp_addr = I_dram_rsp_addr;
assign icache_dram_rsp_if.dram_rsp_valid = I_dram_rsp_valid;
assign icache_dram_rsp_if.dram_rsp_addr = I_dram_rsp_addr;
assign I_dram_req_write = gpu_icache_dram_req_if.dram_req_write;
assign I_dram_req_read = gpu_icache_dram_req_if.dram_req_read;
assign I_dram_req_addr = gpu_icache_dram_req_if.dram_req_addr;
assign I_dram_rsp_ready = gpu_icache_dram_req_if.dram_rsp_ready;
assign I_dram_req_write = icache_dram_req_if.dram_req_write;
assign I_dram_req_read = icache_dram_req_if.dram_req_read;
assign I_dram_req_addr = icache_dram_req_if.dram_req_addr;
assign I_dram_rsp_ready = icache_dram_req_if.dram_rsp_ready;
assign gpu_icache_dram_req_if.dram_req_ready = I_dram_req_ready;
assign icache_dram_req_if.dram_req_ready = I_dram_req_ready;
genvar j;
generate
for (j = 0; j < `IBANK_LINE_WORDS; j = j + 1) begin
assign gpu_icache_dram_rsp_if.dram_rsp_data[j] = I_dram_rsp_data[j * 32 +: 32];
assign I_dram_req_data[j * 32 +: 32] = gpu_icache_dram_req_if.dram_req_data[j];
assign icache_dram_rsp_if.dram_rsp_data[j] = I_dram_rsp_data[j * 32 +: 32];
assign I_dram_req_data[j * 32 +: 32] = icache_dram_req_if.dram_req_data[j];
end
endgenerate
@@ -149,11 +147,11 @@ VX_jal_rsp_if jal_rsp_if(); // Jump resolution to Fetch
VX_warp_ctl_if warp_ctl_if();
// Cache snooping
VX_cache_snp_req_rsp_if gpu_icache_snp_req_if();
VX_cache_snp_req_rsp_if gpu_dcache_snp_req_if();
assign gpu_dcache_snp_req_if.snp_req_valid = llc_snp_req_valid;
assign gpu_dcache_snp_req_if.snp_req_addr = llc_snp_req_addr;
assign llc_snp_req_ready = gpu_dcache_snp_req_if.snp_req_ready;
VX_cache_snp_req_if icache_snp_req_if();
VX_cache_snp_req_if dcache_snp_req_if();
assign dcache_snp_req_if.snp_req_valid = llc_snp_req_valid;
assign dcache_snp_req_if.snp_req_addr = llc_snp_req_addr;
assign llc_snp_req_ready = dcache_snp_req_if.snp_req_ready;
VX_front_end front_end (
.clk (clk),
@@ -161,8 +159,8 @@ VX_front_end front_end (
.warp_ctl_if (warp_ctl_if),
.bckE_req_if (bckE_req_if),
.schedule_delay (schedule_delay),
.icache_rsp_if (icache_rsp_if),
.icache_req_if (icache_req_if),
.icache_rsp_if (icache_core_rsp_if),
.icache_req_if (icache_core_req_if),
.jal_rsp_if (jal_rsp_if),
.branch_rsp_if (branch_rsp_if),
.fetch_ebreak (ebreak)
@@ -190,8 +188,8 @@ VX_back_end #(
.bckE_req_if (bckE_req_if),
.jal_rsp_if (jal_rsp_if),
.branch_rsp_if (branch_rsp_if),
.dcache_rsp_if (dcache_rsp_if),
.dcache_req_if (dcache_req_if),
.dcache_rsp_if (dcache_core_rsp_if),
.dcache_req_if (dcache_core_req_if),
.writeback_if (writeback_if),
.mem_delay (memory_delay),
.exec_delay (exec_delay),
@@ -199,26 +197,26 @@ VX_back_end #(
);
VX_dmem_ctrl dmem_ctrl (
.clk (clk),
.reset (reset),
.clk (clk),
.reset (reset),
// Dram <-> Dcache
.cache_dram_req_if (cache_dram_req_if),
.cache_dram_rsp_if (cache_dram_rsp_if),
.gpu_dcache_snp_req_if (gpu_dcache_snp_req_if),
.cache_dram_req_if (cache_dram_req_if),
.cache_dram_rsp_if (cache_dram_rsp_if),
.dcache_snp_req_if (dcache_snp_req_if),
// Dram <-> Icache
.gpu_icache_dram_req_if (gpu_icache_dram_req_if),
.gpu_icache_dram_rsp_if (gpu_icache_dram_rsp_if),
.gpu_icache_snp_req_if (gpu_icache_snp_req_if),
.icache_dram_req_if (icache_dram_req_if),
.icache_dram_rsp_if (icache_dram_rsp_if),
.icache_snp_req_if (icache_snp_req_if),
// Core <-> Icache
.icache_req_if (icache_req_if),
.icache_rsp_if (icache_rsp_if),
.icache_core_req_if (icache_core_req_if),
.icache_core_rsp_if (icache_core_rsp_if),
// Core <-> Dcache
.dcache_req_if (dcache_req_qual_if),
.dcache_rsp_if (dcache_rsp_if)
.dcache_core_req_if (dcache_core_req_qual_if),
.dcache_core_rsp_if (dcache_core_rsp_if)
);
endmodule // Vortex