352 lines
13 KiB
Scala
352 lines
13 KiB
Scala
// See LICENSE.SiFive for license details.
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// See LICENSE.Berkeley for license details.
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package radiance.tile
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import chisel3._
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import chisel3.util._
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import chisel3.experimental.BundleLiterals._
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import org.chipsalliance.diplomacy.DisableMonitors
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import org.chipsalliance.diplomacy.lazymodule._
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import freechips.rocketchip.diplomacy.{AddressSet, SimpleDevice}
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import freechips.rocketchip.resources.BigIntHexContext
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import freechips.rocketchip.prci.{ClockCrossingType, ClockSinkParameters}
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import freechips.rocketchip.regmapper.RegField
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import freechips.rocketchip.rocket._
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import freechips.rocketchip.subsystem.{CanAttachTile, HierarchicalElementCrossingParamsLike, RocketCrossingParams}
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import freechips.rocketchip.tile._
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import freechips.rocketchip.tilelink._
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import gemmini._
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import org.chipsalliance.cde.config.Parameters
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import radiance.subsystem.{GPUMemParams, GPUMemory}
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case class GemminiCoreParams(
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useVM: Boolean = false,
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useHypervisor: Boolean = false,
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useUser: Boolean = false,
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useSupervisor: Boolean = false,
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useDebug: Boolean = false,
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useAtomics: Boolean = false,
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useAtomicsOnlyForIO: Boolean = false,
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useCompressed: Boolean = false,
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useRVE: Boolean = false,
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mulDiv: Option[MulDivParams] = None,
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fpu: Option[FPUParams] = None,
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fetchWidth: Int = 1,
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decodeWidth: Int = 1,
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retireWidth: Int = 1,
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instBits: Int = 0,
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nLocalInterrupts: Int = 0,
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nPMPs: Int = 0,
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nBreakpoints: Int = 0,
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useBPWatch: Boolean = false,
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nPerfCounters: Int = 0,
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haveBasicCounters: Boolean = false,
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haveFSDirty: Boolean = false,
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misaWritable: Boolean = false,
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haveCFlush: Boolean = false,
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nL2TLBEntries: Int = 0,
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mtvecInit: Option[BigInt] = Some(BigInt(0)),
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mtvecWritable: Boolean = false,
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nL2TLBWays: Int = 0,
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lrscCycles: Int = 8,
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mcontextWidth: Int = 0,
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scontextWidth: Int = 0,
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useNMI: Boolean = false,
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nPTECacheEntries: Int = 0,
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traceHasWdata: Boolean = false,
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useConditionalZero: Boolean = false,
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bootFreqHz: BigInt = 0,
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pmpGranularity: Int = 0) extends CoreParams {
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}
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case class GemminiTileParams(
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tileId: Int = 0,
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gemminiConfig: GemminiArrayConfig[Float, Float, Float],
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tileSize: Either[(Int, Int, Int), Int] = Right(4),
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slaveAddress: BigInt
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) extends InstantiableTileParams[GemminiTile] {
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def instantiate(crossing: HierarchicalElementCrossingParamsLike, lookup: LookupByHartIdImpl)(
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implicit p: Parameters
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): GemminiTile = {
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new GemminiTile(this, crossing, lookup)
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}
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val core = GemminiCoreParams()
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val name = Some("radiance_gemmini_tile")
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val clockSinkParams = ClockSinkParameters()
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val blockerCtrlAddr = None
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val icache = None
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val dcache = Some(DCacheParams(
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nSets = 1, nWays = 1, nMSHRs = 0,
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nTLBSets = 0, nTLBWays = 1
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))
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val btb = None
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val baseName = name.get
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val uniqueName = s"${baseName}_$tileId"
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}
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case class GemminiTileAttachParams(
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tileParams: GemminiTileParams,
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crossingParams: RocketCrossingParams,
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) extends CanAttachTile { type TileType = GemminiTile }
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class GemminiTile private (
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val gemminiParams: GemminiTileParams,
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crossing: ClockCrossingType,
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lookup: LookupByHartIdImpl,
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q: Parameters
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) extends BaseTile(gemminiParams, crossing, lookup, q)
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with SinksExternalInterrupts
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with SourcesExternalNotifications {
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def this(params: GemminiTileParams, crossing: HierarchicalElementCrossingParamsLike,
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lookup: LookupByHartIdImpl)(implicit p: Parameters) =
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this(params, crossing.crossingType, lookup, p)
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val cpuDevice: SimpleDevice = new SimpleDevice(s"gemmini${tileId}", Nil)
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val intOutwardNode = None
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val slaveNode = TLIdentityNode()
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val masterNode = visibilityNode
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// val statusNode = BundleBridgeSource(() => new GroundTestStatus)
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val accSlaveNode = AccSlaveNode()
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tlOtherMastersNode := tlMasterXbar.node
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masterNode :=* tlOtherMastersNode
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DisableMonitors { implicit p => tlSlaveXbar.node :*= slaveNode }
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// TODO: evaluate if gemmini write node is required at all
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val gemmini = LazyModule(new Gemmini(gemminiParams.gemminiConfig))
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val base = p(GPUMemory()) match {
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case Some(GPUMemParams(baseAddr, _)) => baseAddr
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case _ => BigInt(0)
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}
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// tlMasterXbar.node :=* AddressOrNode(base) :=* gemmini.atlNode
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// tlOtherMastersNode :=* AddressOrNode(base) :=* gemmini.tlNode
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tlMasterXbar.node :=* gemmini.atlNode
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tlOtherMastersNode :=* gemmini.tlNode
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// gemmini.stlNode := tlSlaveXbar.node
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require(!gemmini.config.sp_singleported, "external scratchpad must be dual ported")
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val regDevice = new SimpleDevice("gemmini-cmd-reg", Seq(s"gemmini-cmd-reg"))
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val regNode = TLRegisterNode(
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address = Seq(AddressSet(gemminiParams.slaveAddress, 0xff)),
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device = regDevice,
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beatBytes = 8,
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concurrency = 1)
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regNode := TLFragmenter(8, 64) := tlSlaveXbar.node
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override lazy val module = new GemminiTileModuleImp(this)
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}
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class GemminiTileModuleImp(outer: GemminiTile) extends BaseTileModuleImp(outer) {
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def tieOffGemminiRocc: Unit = {
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val gemmini_io = outer.gemmini.module.io
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gemmini_io.ptw <> DontCare
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gemmini_io.mem <> DontCare
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gemmini_io.resp <> DontCare
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gemmini_io.fpu_req.ready := false.B
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gemmini_io.fpu_resp.valid := false.B
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gemmini_io.fpu_resp.bits := DontCare
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gemmini_io.exception := DontCare
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}
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tieOffGemminiRocc
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val accSlave = outer.accSlaveNode.in.head._1
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val instCounter = Counter(4)
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val ciscValid = RegInit(false.B)
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val ciscArgs = RegInit(0.U(24.W))
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val ciscId = RegInit(0.U(8.W))
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val ciscInstT = new Bundle {
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val inst = UInt(32.W)
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val rs1 = UInt(64.W)
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val rs2 = UInt(64.W)
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}
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val ciscInst = Wire(ciscInstT)
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val startsLoop = WireInit(false.B)
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val runningLoops = RegInit(0.U(4.W))
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val accCommandQueue = Module(new Queue(UInt(32.W), 4, false, true))
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accCommandQueue.io.enq.bits := accSlave.cmd.bits
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accCommandQueue.io.enq.valid := accSlave.cmd.valid
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accCommandQueue.io.deq.ready := !ciscValid
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assert(!accSlave.cmd.valid || accCommandQueue.io.enq.ready, "cisc command queue full")
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when (accCommandQueue.io.enq.fire) {
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val enqId = accSlave.cmd.bits(6, 0)
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startsLoop := VecInit(Seq(0, 1, 2, 9, 10, 12).map { x => enqId === x.U }).asUInt.orR
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}
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when (accCommandQueue.io.deq.fire) {
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ciscValid := true.B
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ciscId := accCommandQueue.io.deq.bits(7, 0)
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ciscArgs := accCommandQueue.io.deq.bits(31, 8)
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instCounter.reset()
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}
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def microcodeEntry[T <: Data](insts: Seq[T]): T = {
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when (instCounter.value === (insts.size - 1).U) {
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ciscValid := false.B
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instCounter.reset()
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}.otherwise {
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instCounter.inc()
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}
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VecInit(insts)(instCounter.value)
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}
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ciscInst := 0.U.asTypeOf(ciscInstT)
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val (tileSizeM, tileSizeN, tileSizeK) = outer.gemminiParams.tileSize match {
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case Left(v: (Int, Int, Int)) => v
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case Right(v: Int) => (v, v, v)
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}
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val config = outer.gemminiParams.gemminiConfig
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val spadHexadecile = config.sp_bank_entries * config.sp_banks / 16
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// TODO: as a temporary hack, bit 7 of the cisc opcode
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// TODO: will force the tile size to be a square base on M.
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val rectBoundsInst = ciscInstT.Lit(_.inst -> 0x1220b07b.U, _.rs1 -> 0.U,
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_.rs2 -> (tileSizeM | (tileSizeN << 16) | (BigInt(tileSizeK) << 32)).U)
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val squareBoundsInst = ciscInstT.Lit(_.inst -> 0x1220b07b.U, _.rs1 -> 0.U,
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_.rs2 -> (tileSizeM | (tileSizeM << 16) | (BigInt(tileSizeM) << 32)).U)
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val boundsInst = Mux(ciscId(7), squareBoundsInst, rectBoundsInst)
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def genStrideInst(tileA: UInt, tileB: UInt) = {
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val inst = Wire(ciscInstT)
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inst.inst := 0x3020b07b.U
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inst.rs1 := tileA * spadHexadecile.U // A should be stored from the start of this block
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inst.rs2 := (tileB + 1.U) * spadHexadecile.U // B should be stored up till the end of this block
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inst
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}
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def genAccSkipInst(accumulate: UInt, skips: UInt) = {
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val inst = Wire(ciscInstT)
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inst.inst := 0x1020b07b.U
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inst.rs1 := accumulate
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inst.rs2 := skips
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inst
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}
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println(s"gemmini cisc initialized with DIM=${config.DIM}, tileSize=${tileSizeM},${tileSizeN},${tileSizeK}")
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println(f"boundsInst=${rectBoundsInst.litValue}%x, hexadecile=${spadHexadecile}")
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when (ciscValid) {
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switch (ciscId(6, 0)) {
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is (0.U) { // compute on given hexadeciles
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val strideInst = genStrideInst(ciscArgs(7, 0), ciscArgs(15, 8))
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val accSkipInst = genAccSkipInst(ciscArgs(16), 0x2b8.U)
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ciscInst := microcodeEntry(Seq(boundsInst, strideInst, accSkipInst))
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} // replaces opcode 0: (a, b, accum) = (0, 2, 0), op 1 = (0, 2, 1), op 2 = (1, 3, 1), op 3 = (1, 3, 0)
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is (1.U) { // compute on given hexadeciles and mvout to spad
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val strideInst = genStrideInst(ciscArgs(7, 0), ciscArgs(15, 8))
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// note that accumulation is disabled
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val accSkipInst = genAccSkipInst(0.U, ((ciscArgs(23, 16) * spadHexadecile.U) << 32).asUInt | 0x238.U)
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ciscInst := microcodeEntry(Seq(boundsInst, strideInst, accSkipInst))
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}
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is (2.U) {} // no actual invocation, fake job placeholder
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is (8.U) { // set a, b stride
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val inst = Wire(ciscInstT)
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inst.inst := 0x1820b07b.U
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inst.rs1 := ciscArgs(11, 0) // a
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inst.rs2 := ciscArgs(23, 12) // b
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ciscInst := microcodeEntry(Seq(inst))
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}
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is (9.U) { // move out to scratchpad
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val accSkipInst = genAccSkipInst(0.U, ((ciscArgs(7, 0) * spadHexadecile.U) << 32).asUInt | 0x278.U)
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ciscInst := microcodeEntry(Seq(boundsInst, accSkipInst))
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}
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is (10.U) { // load to scratchpad hexadeciles
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val strideInst = genStrideInst(ciscArgs(7, 0), ciscArgs(15, 8))
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val accSkipInst = genAccSkipInst(1.U, 0x2e0.U)
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ciscInst := microcodeEntry(Seq(boundsInst, strideInst, accSkipInst))
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} // replaces opcode 10: (a, b) = (0, 2), opcode 11 = (1, 3), opcode 12 = (0, 0), opcode 13 = (2, 2)
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is (11.U) { // set d, c stride
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val inst = Wire(ciscInstT)
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inst.inst := 0x1a20b07b.U
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inst.rs1 := ciscArgs(11, 0) // d
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inst.rs2 := ciscArgs(23, 12) // c
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ciscInst := microcodeEntry(Seq(inst))
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}
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is (12.U) { // store to gmem
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val accSkipInst = genAccSkipInst(0.U, 0x78.U)
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ciscInst := microcodeEntry(Seq(boundsInst, accSkipInst))
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}
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is (16.U) { // unused, configure gemmini
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ciscInst := microcodeEntry(Seq(
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ciscInstT.Lit(_.inst -> 0x0020b07b.U, _.rs1 -> x"3f800000_00080101".U, _.rs2 -> 0.U),
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ciscInstT.Lit(_.inst -> 0x0020b07b.U, _.rs1 -> x"3f800000_00010004".U, _.rs2 -> x"10000_00000000".U),
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ciscInstT.Lit(_.inst -> 0x0020b07b.U, _.rs1 -> 0x2.U, _.rs2 -> x"3f800000_00000000".U)
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))
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}
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}
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}
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val completionCount = PopCount(outer.gemmini.module.completion_io.completed)
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val loopStarted = Mux(startsLoop, 1.U, 0.U)
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runningLoops := runningLoops + loopStarted - completionCount
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assert(runningLoops + loopStarted >= completionCount)
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val gemminiIO = outer.gemmini.module.io.cmd
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val regValid = Wire(Bool())
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val regCommand = Wire(gemminiIO.bits.inst.cloneType)
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val gemminiRs1RegLSB = RegInit(0.U(32.W))
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val gemminiRs1RegMSB = RegInit(0.U(32.W))
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val gemminiRs2RegLSB = RegInit(0.U(32.W))
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val gemminiRs2RegMSB = RegInit(0.U(32.W))
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def gemminiCommandReg(valid: Bool, bits: UInt): Bool = {
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regValid := valid
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regCommand := bits.asTypeOf(regCommand)
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gemminiIO.ready && !ciscValid
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}
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def gemminiBusyReg(_dReady: Bool): (Bool, UInt) = {
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// (aReady, bits)
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// (!outer.gemmini.module.io.busy, outer.gemmini.module.io.busy.asUInt)
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(true.B, outer.gemmini.module.io.busy.asUInt)
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}
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def gemminiRunningLoopsReg(_dReady: Bool): (Bool, UInt) = {
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(true.B, runningLoops)
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}
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outer.regNode.regmap(
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0x00 -> Seq(RegField.w(32, gemminiCommandReg(_, _))),
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0x10 -> Seq(
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RegField.w(32, gemminiRs1RegLSB),
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RegField.w(32, gemminiRs1RegMSB)),
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0x18 -> Seq(
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RegField.w(32, gemminiRs2RegLSB),
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RegField.w(32, gemminiRs2RegMSB)),
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0x20 -> Seq(RegField.r(32, gemminiBusyReg(_))),
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0x28 -> Seq(RegField.r(32, gemminiRunningLoopsReg(_)))
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)
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assert(!regValid || gemminiIO.ready)
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assert(!ciscValid || gemminiIO.ready)
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gemminiIO.bits.status := 0.U.asTypeOf(gemminiIO.bits.status)
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gemminiIO.bits.inst := Mux(ciscValid, ciscInst.inst.asTypeOf(gemminiIO.bits.inst), regCommand)
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gemminiIO.bits.rs1 := Mux(ciscValid, ciscInst.rs1, Cat(gemminiRs1RegMSB, gemminiRs1RegLSB))
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gemminiIO.bits.rs2 := Mux(ciscValid, ciscInst.rs2, Cat(gemminiRs2RegMSB, gemminiRs2RegLSB))
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gemminiIO.valid := ciscValid || regValid
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assert(gemminiIO.ready || !gemminiIO.valid)
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accSlave.status := RegNext(outer.gemmini.module.io.busy).asUInt
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outer.traceSourceNode.bundle := DontCare
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outer.traceSourceNode.bundle.insns foreach (_.valid := false.B)
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// hacky, but cluster will AND the cease signals from all tiles, and we want
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// the core tiles to determine cluster cease not Gemmini
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outer.reportCease(Some(true.B))
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}
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