81 lines
2.4 KiB
Scala
81 lines
2.4 KiB
Scala
// See LICENSE.SiFive for license details.
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package freechips.rocketchip.tilelink
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import chisel3._
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import chisel3.util._
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import freechips.rocketchip.config.Parameters
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.unittest._
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class CoalescingUnit(txns: Int = 5000)(implicit p: Parameters)
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extends LazyModule {
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val fuzz = LazyModule(new TLFuzzer(txns))
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val model = LazyModule(new TLRAMModel("Xbar"))
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val xbar = LazyModule(new TLXbar)
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xbar.node := TLDelayer(0.1) := model.node := fuzz.node
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(0 until 1) foreach { n =>
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val ram = LazyModule(new TLRAM(AddressSet(0x0 + 0x400 * n, 0x3ff)))
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ram.node := TLFragmenter(4, 256) := TLDelayer(0.1) := xbar.node
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}
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lazy val module = new Impl
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class Impl extends LazyModuleImp(this) {
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// io.finished := fuzz.module.io.finished
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}
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}
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class MemTraceDriver(implicit p: Parameters) extends LazyModule {
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// TODO: generate TL request here
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// testchipip provides TLHelper.makeClientNode convenience wrapper for this.
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val clients = Seq(
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TLMasterParameters.v1(
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name = "MemTraceDriver",
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sourceId = IdRange(0, 1 /*FIXME*/ )
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)
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)
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val node = TLClientNode(Seq(TLMasterPortParameters.v1(clients)))
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lazy val module = new Impl
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class Impl extends LazyModuleImp(this) with UnitTestModule {
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val sim = Module(new SimMemTrace(4))
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sim.io.clock := clock
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sim.io.reset := reset.asBool
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sim.io.trace_read.ready := true.B
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// we're finished when there is no more memtrace to read
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io.finished := sim.io.trace_read.finished
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}
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}
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class SimMemTrace(num_threads: Int)
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extends BlackBox(Map("NUM_THREADS" -> num_threads))
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with HasBlackBoxResource {
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val io = IO(new Bundle {
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val clock = Input(Clock())
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val reset = Input(Bool())
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val trace_read = new Bundle {
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val ready = Input(Bool())
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val valid = Output(UInt(num_threads.W))
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val address = Output(UInt((64 * num_threads).W))
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val finished = Output(Bool())
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}
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})
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addResource("/vsrc/SimMemTrace.v")
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addResource("/csrc/SimMemTrace.cc")
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addResource("/csrc/SimMemTrace.h")
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}
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class CoalescingUnitTest(txns: Int = 5000, timeout: Int = 500000)(implicit
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p: Parameters
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) extends UnitTest(timeout) {
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// val coal = Module(LazyModule(new CoalescingUnit(txns)).module)
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val driver = Module(LazyModule(new MemTraceDriver).module)
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driver.io.start := io.start
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io.finished := driver.io.finished
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}
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