906 lines
31 KiB
Scala
906 lines
31 KiB
Scala
package freechips.rocketchip.tilelink.coalescing
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import chisel3._
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import chiseltest._
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import org.scalatest.flatspec.AnyFlatSpec
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import freechips.rocketchip.tilelink._
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import freechips.rocketchip.util.MultiPortQueue
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import freechips.rocketchip.diplomacy._
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import chipsalliance.rocketchip.config.Parameters
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import chisel3.util.experimental.BoringUtils
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class MultiPortQueueUnitTest extends AnyFlatSpec with ChiselScalatestTester {
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behavior of "MultiPortQueue"
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// This is really just to figure out how MultiPortQueue works
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it should "serialize at dequeue end" in {
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test(new MultiPortQueue(UInt(4.W), 3, 1, 3, 6))
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.withAnnotations(Seq(WriteVcdAnnotation)) { c =>
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c.io.enq(0).valid.poke(true.B)
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c.io.enq(0).bits.poke(11.U)
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c.io.enq(1).valid.poke(true.B)
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c.io.enq(1).bits.poke(15.U)
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c.io.enq(2).valid.poke(true.B)
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c.io.enq(2).bits.poke(7.U)
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c.io.deq(0).ready.poke(true.B)
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c.clock.step()
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// c.io.enq(0).valid.poke(false.B)
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// c.io.enq(1).valid.poke(false.B)
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for (_ <- 0 until 100) {
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c.clock.step()
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}
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// c.io.deq(0).valid.expect(false.B)
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}
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}
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}
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class DummyCoalescingUnitTB(implicit p: Parameters) extends LazyModule {
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val cpuNodes = Seq.tabulate(testConfig.numLanes) { _ =>
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TLClientNode(
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Seq(
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TLMasterPortParameters.v1(
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Seq(
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TLClientParameters(
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name = "processor-nodes",
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sourceId = IdRange(0, testConfig.numOldSrcIds),
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visibility = Seq(AddressSet(0x0, 0xffffff))
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)
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)
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)
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)
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) // 24 bit address space (TODO probably use testConfig)
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}
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val device = new SimpleDevice("dummy", Seq("dummy"))
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val beatBytes = 1 << testConfig.dataBusWidth // 256 bit bus
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val l2Nodes = Seq.tabulate(5) { _ =>
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TLManagerNode(
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Seq(
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TLSlavePortParameters.v1(
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Seq(
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TLManagerParameters(
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address = Seq(AddressSet(0x0, 0xffffff)), // should be matching cpuNode
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resources = device.reg,
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regionType = RegionType.UNCACHED,
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executable = true,
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supportsArithmetic = TransferSizes(1, beatBytes),
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supportsLogical = TransferSizes(1, beatBytes),
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supportsGet = TransferSizes(1, beatBytes),
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supportsPutFull = TransferSizes(1, beatBytes),
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supportsPutPartial = TransferSizes(1, beatBytes),
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supportsHint = TransferSizes(1, beatBytes),
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fifoId = Some(0)
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)
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),
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beatBytes
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)
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)
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)
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}
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val dut = LazyModule(new CoalescingUnit(testConfig))
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val widthWidgets = Seq.tabulate(4) { _ => TLWidthWidget(4)}
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(cpuNodes zip widthWidgets).foreach { case (cpuNode, widthWidget) => widthWidget := cpuNode}
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widthWidgets.foreach(dut.node := _)
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l2Nodes.foreach(_ := dut.node)
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lazy val module = new DummyCoalescingUnitTBImp(this)
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}
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class DummyCoalescingUnitTBImp(outer: DummyCoalescingUnitTB) extends LazyModuleImp(outer) {
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val coal = outer.dut
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// FIXME: these need to be separate variables because of implicit naming in makeIOs
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// there has to be a better way
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val coalIO0 = outer.cpuNodes(0).makeIOs()
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val coalIO1 = outer.cpuNodes(1).makeIOs()
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val coalIO2 = outer.cpuNodes(2).makeIOs()
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val coalIO3 = outer.cpuNodes(3).makeIOs()
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val coalIOs = Seq(coalIO0, coalIO1, coalIO2, coalIO3)
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private val reqQueues = coal.module.reqQueues
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private val coalescer = coal.module.coalescer
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// workaround for peeking internal signals as outlined in
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// https://github.com/ucb-bar/chiseltest/issues/17
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private val peekIn = Seq(
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reqQueues.io.queue.enq.map(_.ready),
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reqQueues.io.queue.deq.map(_.bits),
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reqQueues.io.queue.deq.map(_.valid),
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coalescer.io.coalReq.ready,
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coalescer.io.coalReq.bits,
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coalescer.io.coalReq.valid,
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)
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val reqQueueEnqReady = peekIn(0).asInstanceOf[Seq[Bool]].map(x => IO(Output(x.cloneType)))
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val reqQueueDeqBits = peekIn(1).asInstanceOf[Seq[ReqQueueEntry]].map(x => IO(Output(x.cloneType)))
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val reqQueueDeqValid = peekIn(2).asInstanceOf[Seq[Bool]].map(x => IO(Output(x.cloneType)))
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val coalReqReady = IO(Output(peekIn(3).asInstanceOf[Bool].cloneType))
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val coalReqBits = IO(Output(peekIn(4).asInstanceOf[ReqQueueEntry].cloneType))
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val coalReqValid = IO(Output(peekIn(5).asInstanceOf[Bool].cloneType))
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private val peekOut = Seq(
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reqQueueEnqReady, reqQueueDeqBits, reqQueueDeqValid,
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coalReqReady, coalReqBits, coalReqValid,
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)
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(peekIn zip peekOut).foreach {
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case (inner: IndexedSeq[Data], outer: Seq[Data]) =>
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(inner zip outer).foreach { case (i, o) =>
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BoringUtils.bore(i, Seq(o))
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}
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case (inner: Data, outer: Data) =>
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BoringUtils.bore(inner, Seq(outer))
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case _ =>
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assert(false, "boring between different data types")
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}
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private val pokeIn = Seq(
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reqQueues.io.queue.deq.map(_.ready),
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// coalescer.io.coalReq.ready
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)
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val reqQueueDeqReady = pokeIn(0).asInstanceOf[Seq[Bool]].map(x => IO(Input(x.cloneType)))
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private val pokeOut = Seq(
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reqQueueDeqReady
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)
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// TODO: doesn't work yet
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/*
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(pokeIn zip pokeOut).foreach {
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case (inner: IndexedSeq[Data], outer: Seq[Data]) =>
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(inner zip outer).foreach { case (i, o) =>
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BoringUtils.bore(i, Seq(o))
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}
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case (inner: Data, outer: Data) =>
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BoringUtils.bore(inner, Seq(outer))
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case _ =>
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assert(false, "boring between different data types")
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}*/
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// val coalMasterNode = coal.coalescerNode.makeIOs()
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}
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object testConfig extends CoalescerConfig(
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numLanes = 4,
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queueDepth = 1,
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waitTimeout = 8,
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addressWidth = 24,
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dataBusWidth = 5,
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// watermark = 2,
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wordSizeInBytes = 4,
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wordWidth = 2,
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numOldSrcIds = 16,
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numNewSrcIds = 4,
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respQueueDepth = 4,
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coalLogSizes = Seq(3),
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sizeEnum = DefaultInFlightTableSizeEnum,
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arbiterOutputs = 4
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)
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class CoalescerUnitTest extends AnyFlatSpec with ChiselScalatestTester {
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behavior of "multi- and mono-coalescers"
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implicit val p: Parameters = Parameters.empty
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def pokeA(
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nodes: Seq[TLBundle],
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idx: Int,
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op: Int,
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size: Int,
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source: Int,
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addr: Int,
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mask: Int,
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data: Int
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): Unit = {
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val node = nodes(idx)
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// node.a.ready.expect(true.B) // FIXME: this fails currently
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node.a.bits.opcode.poke(if (op == 1) TLMessages.PutFullData else TLMessages.Get)
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node.a.bits.param.poke(0.U)
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node.a.bits.size.poke(size.U)
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node.a.bits.source.poke(source.U)
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node.a.bits.address.poke(addr.U)
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node.a.bits.mask.poke(mask.U)
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node.a.bits.data.poke(data.U)
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node.a.bits.corrupt.poke(false.B)
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node.a.valid.poke(true.B)
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}
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def unsetA(nodes: Seq[TLBundle]): Unit = {
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nodes.foreach { node =>
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node.a.valid.poke(false.B)
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}
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}
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it should "coalesce fully consecutive accesses at size 4, only once" in {
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test(LazyModule(new DummyCoalescingUnitTB()).module)
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.withAnnotations(Seq(VcsBackendAnnotation, WriteFsdbAnnotation))
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{ c =>
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println(s"coalIO length = ${c.coalIOs(0).length}")
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val nodes = c.coalIOs.map(_.head)
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c.reqQueueEnqReady.foreach(_.expect(true.B))
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// always ready to take non-coalesced requests
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c.reqQueueDeqReady.foreach(_.poke(true.B))
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pokeA(nodes, idx = 0, op = 1, size = 2, source = 0, addr = 0x10, mask = 0xf, data = 0x1111)
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pokeA(nodes, idx = 1, op = 1, size = 2, source = 0, addr = 0x14, mask = 0xf, data = 0x2222)
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pokeA(nodes, idx = 2, op = 1, size = 2, source = 0, addr = 0x18, mask = 0xf, data = 0x3333)
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pokeA(nodes, idx = 3, op = 1, size = 2, source = 0, addr = 0x1c, mask = 0xf, data = 0x4444)
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c.clock.step()
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unsetA(nodes)
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c.clock.step()
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c.clock.step()
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}
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}
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it should "coalesce identical addresses (stride of 0)" in {
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test(LazyModule(new DummyCoalescingUnitTB()).module)
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.withAnnotations(Seq(VcsBackendAnnotation))
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{ c =>
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println(s"coalIO length = ${c.coalIOs(0).length}")
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val nodes = c.coalIOs.map(_.head)
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pokeA(nodes, idx = 0, op = 1, size = 2, source = 0, addr = 0x18, mask = 0xf, data = 0x1111)
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pokeA(nodes, idx = 1, op = 1, size = 2, source = 0, addr = 0x18, mask = 0xf, data = 0x2222)
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pokeA(nodes, idx = 2, op = 1, size = 2, source = 0, addr = 0x18, mask = 0xf, data = 0x3333)
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pokeA(nodes, idx = 3, op = 1, size = 2, source = 0, addr = 0x18, mask = 0xf, data = 0x4444)
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c.clock.step()
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unsetA(nodes)
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c.clock.step()
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c.clock.step()
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}
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}
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// it should "coalesce strided accesses at size 6" in {}
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//
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// it should "coalesce the coalescable chunk and leave 2 uncoalescable requests" in {}
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//
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// it should "not touch uncoalescable requests" in {}
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//
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// it should "allow temporal coalescing when depth >=2" in {}
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//
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// it should "select the most coverage mono-coalescer" in {}
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//
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// it should "resort to the backup policy when coverage is below average" in {}
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}
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class CoalShiftQueueTest extends AnyFlatSpec with ChiselScalatestTester {
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behavior of "request shift queues"
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def attemptEnqueue(c: CoalShiftQueue[UInt], bits: Seq[UInt], valids: Seq[Bool]): Unit = {
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((c.io.queue.enq zip bits) zip valids).foreach { case ((enq, ent), valid) =>
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enq.ready.expect(true.B)
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enq.valid.poke(valid)
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enq.bits.poke(ent)
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}
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c.clock.step()
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}
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def expectDequeue(c: CoalShiftQueue[UInt], bits: Seq[UInt], valids: Seq[Bool]): Unit = {
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((c.io.queue.deq zip bits) zip valids).foreach { case ((deq, ent), valid) =>
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deq.valid.expect(valid)
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deq.bits.expect(ent)
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}
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}
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def pokeVec[T <: Data](vec: Seq[T], value: Seq[T]): Unit = {
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(vec zip value).foreach { case (a, b) => a.poke(b) }
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}
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it should "work like normal shiftqueue when no invalidate" in {
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test(new CoalShiftQueue(UInt(8.W),4, testConfig)) { c =>
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c.io.coalescable.foreach(_.poke(true.B))
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c.io.queue.deq.foreach(_.ready.poke(false.B))
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attemptEnqueue(c, Seq.fill(4)(1.U), Seq.fill(4)(true.B))
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attemptEnqueue(c, Seq.fill(4)(2.U), Seq(true.B, false.B, false.B, false.B)) // should remain synchronous
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attemptEnqueue(c, Seq.fill(4)(3.U), Seq.fill(4)(true.B))
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c.io.queue.enq.foreach(_.valid.poke(false.B))
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c.io.queue.enq.foreach(_.ready.expect(true.B))
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// check if head is the first enqueued item
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expectDequeue(c, Seq.fill(4)(1.U), Seq.fill(4)(false.B))
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c.clock.step()
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c.io.queue.deq.foreach(_.ready.poke(true.B))
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// should not dequeue because all are coalescable
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expectDequeue(c, Seq.fill(4)(1.U), Seq.fill(4)(false.B))
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c.clock.step()
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pokeVec(c.io.coalescable, Seq(false.B, false.B, false.B, true.B))
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// first 3 items should be valid now
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expectDequeue(c, Seq.fill(4)(1.U), Seq(true.B, true.B, true.B, false.B))
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// only dequeue first item - 4th item should not be dequeued since not valid
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pokeVec(c.io.queue.deq.map(_.ready), Seq(true.B, false.B, false.B, true.B))
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c.clock.step()
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// first item should turn invalid
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c.io.coalescable.foreach(_.poke(false.B))
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expectDequeue(c, Seq.fill(4)(1.U), Seq(false.B, true.B, true.B, true.B))
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// now dequeue everything else in the first line
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c.io.queue.deq.foreach(_.ready.poke(true.B))
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c.clock.step()
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// all dequeued, none valid this cycle
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expectDequeue(c, Seq.fill(4)(1.U), Seq.fill(4)(false.B))
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c.clock.step()
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// shifted last cycle
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c.io.coalescable.foreach(_.poke(false.B))
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c.io.queue.deq.foreach(_.ready.poke(true.B))
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expectDequeue(c, Seq.fill(4)(2.U), Seq(true.B, false.B, false.B, false.B))
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c.clock.step()
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expectDequeue(c, Seq.fill(4)(2.U), Seq(false.B, false.B, false.B, false.B))
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c.clock.step()
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pokeVec(c.io.coalescable, Seq(true.B, false.B, true.B, true.B))
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expectDequeue(c, Seq.fill(4)(3.U), Seq(false.B, true.B, false.B, false.B))
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c.clock.step()
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c.io.coalescable.foreach(_.poke(false.B))
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expectDequeue(c, Seq.fill(4)(3.U), Seq(true.B, false.B, true.B, true.B))
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c.clock.step()
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// empty
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expectDequeue(c, Seq.fill(4)(3.U), Seq.fill(4)(false.B))
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// now enqueue back to full & test back pressure
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c.io.queue.deq.foreach(_.ready.poke(false.B))
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attemptEnqueue(c, Seq.fill(4)(1.U), Seq.fill(4)(true.B))
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pokeVec(c.io.coalescable, Seq(true.B, true.B, true.B, true.B))
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attemptEnqueue(c, Seq.fill(4)(2.U), Seq.fill(4)(true.B))
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attemptEnqueue(c, Seq.fill(4)(3.U), Seq.fill(4)(true.B))
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attemptEnqueue(c, Seq.fill(4)(4.U), Seq.fill(4)(true.B))
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// check full
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c.io.queue.enq.foreach(_.ready.expect(false.B))
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c.clock.step()
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// now indicate the next cycle will dequeue everything
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c.io.queue.deq.foreach(_.ready.poke(true.B))
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c.io.coalescable.foreach(_.poke(false.B))
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c.clock.step()
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// should still be full, but allow enqueue
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c.io.coalescable.foreach(_.poke(true.B))
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c.io.queue.enq.foreach(_.ready.expect(false.B)) // check full
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c.io.coalescable.foreach(_.poke(false.B))
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attemptEnqueue(c, Seq.fill(4)(5.U), Seq.fill(4)(true.B))
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expectDequeue(c, Seq.fill(4)(2.U), Seq.fill(4)(true.B))
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c.clock.step()
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attemptEnqueue(c, Seq.fill(4)(6.U), Seq.fill(4)(true.B))
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}
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}
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it should "work when enqueing and dequeueing simultaneously" in {
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test(new CoalShiftQueue(UInt(8.W), 4, testConfig)) { c =>
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c.io.invalidate.valid.poke(false.B)
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c.io.coalescable.foreach(_.poke(true.B))
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c.io.queue.deq.foreach(_.ready.poke(false.B))
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attemptEnqueue(c, Seq.fill(4)(1.U), Seq.fill(4)(true.B))
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// mark for dequeue
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c.io.coalescable.foreach(_.poke(false.B))
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c.io.queue.deq.foreach(_.ready.poke(true.B))
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expectDequeue(c, Seq.fill(4)(1.U), Seq.fill(4)(true.B))
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attemptEnqueue(c, Seq.fill(4)(2.U), Seq.fill(4)(true.B))
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expectDequeue(c, Seq.fill(4)(1.U), Seq.fill(4)(false.B))
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attemptEnqueue(c, Seq.fill(4)(3.U), Seq.fill(4)(true.B))
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expectDequeue(c, Seq.fill(4)(2.U), Seq.fill(4)(true.B))
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attemptEnqueue(c, Seq.fill(4)(4.U), Seq.fill(4)(true.B))
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expectDequeue(c, Seq.fill(4)(2.U), Seq.fill(4)(false.B))
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attemptEnqueue(c, Seq.fill(4)(5.U), Seq.fill(4)(true.B))
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expectDequeue(c, Seq.fill(4)(3.U), Seq.fill(4)(true.B))
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c.clock.step()
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expectDequeue(c, Seq.fill(4)(3.U), Seq.fill(4)(false.B))
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c.clock.step()
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expectDequeue(c, Seq.fill(4)(4.U), Seq.fill(4)(true.B))
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c.clock.step()
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expectDequeue(c, Seq.fill(4)(4.U), Seq.fill(4)(false.B))
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c.clock.step()
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expectDequeue(c, Seq.fill(4)(5.U), Seq.fill(4)(true.B))
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c.clock.step()
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expectDequeue(c, Seq.fill(4)(5.U), Seq.fill(4)(false.B))
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|
c.clock.step()
|
|
}
|
|
}
|
|
/*
|
|
it should "work when enqueing and dequeueing simultaneously to a depth=1 queue" in {
|
|
test(new CoalShiftQueue(UInt(8.W), 1)) { c =>
|
|
c.io.invalidate.valid.poke(false.B)
|
|
c.io.allowShift.poke(true.B)
|
|
|
|
// prepare
|
|
c.io.queue.deq.ready.poke(true.B)
|
|
c.io.queue.enq.ready.expect(true.B)
|
|
c.io.queue.enq.valid.poke(true.B)
|
|
c.io.queue.enq.bits.poke(0x12.U)
|
|
c.clock.step()
|
|
// enqueue and dequeue simultaneously
|
|
c.io.queue.deq.ready.poke(true.B)
|
|
c.io.queue.enq.ready.expect(true.B)
|
|
c.io.queue.enq.valid.poke(true.B)
|
|
c.io.queue.enq.bits.poke(0x34.U)
|
|
c.io.queue.deq.valid.expect(true.B)
|
|
c.io.queue.deq.bits.expect(0x12.U)
|
|
c.clock.step()
|
|
// enqueue and dequeue simultaneously once more
|
|
c.io.queue.deq.ready.poke(true.B)
|
|
c.io.queue.enq.ready.expect(true.B)
|
|
c.io.queue.enq.valid.poke(true.B)
|
|
c.io.queue.enq.bits.poke(0x56.U)
|
|
c.io.queue.deq.valid.expect(true.B)
|
|
c.io.queue.deq.bits.expect(0x34.U)
|
|
c.clock.step()
|
|
// dequeueing back-to-back should work without any holes in the middle
|
|
c.io.queue.deq.ready.poke(true.B)
|
|
c.io.queue.enq.valid.poke(false.B)
|
|
c.io.queue.deq.valid.expect(true.B)
|
|
c.io.queue.deq.bits.expect(0x56.U)
|
|
c.clock.step()
|
|
// make sure is empty
|
|
c.io.queue.deq.ready.poke(true.B)
|
|
c.io.queue.enq.valid.poke(false.B)
|
|
c.io.queue.deq.valid.expect(false.B)
|
|
}
|
|
}
|
|
|
|
it should "work when invalidating and enqueueing to a depth=1 queue" in {
|
|
test(new CoalShiftQueue(UInt(8.W), 1)) { c =>
|
|
c.io.invalidate.valid.poke(false.B)
|
|
c.io.allowShift.poke(true.B)
|
|
// no dequeueing
|
|
c.io.queue.deq.ready.poke(false.B)
|
|
|
|
// prepare
|
|
c.io.queue.enq.ready.expect(true.B)
|
|
c.io.queue.enq.valid.poke(true.B)
|
|
c.io.queue.enq.bits.poke(0x12.U)
|
|
c.clock.step()
|
|
// invalidate, but don't allow shift
|
|
c.io.allowShift.poke(false.B)
|
|
c.io.invalidate.valid.poke(true.B)
|
|
c.io.invalidate.bits.poke(0x1.U)
|
|
// TODO: we might be able to enqueue to a full depth=1 queue whose only
|
|
// entry just got invalidated, so that enq.ready is true here, but
|
|
// it is a niche case
|
|
c.io.queue.enq.ready.expect(false.B)
|
|
c.clock.step()
|
|
// now try enqueueing now that we have space
|
|
c.io.allowShift.poke(true.B)
|
|
c.io.invalidate.valid.poke(false.B)
|
|
c.io.queue.enq.ready.expect(true.B)
|
|
c.io.queue.enq.valid.poke(true.B)
|
|
c.io.queue.enq.bits.poke(0x34.U)
|
|
c.io.queue.deq.valid.expect(false.B)
|
|
c.clock.step()
|
|
// see if it comes out right next cycle
|
|
c.io.queue.enq.valid.poke(false.B)
|
|
c.io.queue.deq.ready.poke(true.B)
|
|
c.io.queue.deq.valid.expect(true.B)
|
|
c.io.queue.deq.bits.expect(0x34.U)
|
|
}
|
|
}
|
|
|
|
it should "invalidate head that is also being dequeued" in {
|
|
test(new CoalShiftQueue(UInt(8.W), 4)) { c =>
|
|
c.io.invalidate.valid.poke(false.B)
|
|
c.io.allowShift.poke(true.B)
|
|
|
|
// prepare
|
|
c.io.queue.deq.ready.poke(false.B)
|
|
c.io.queue.enq.ready.expect(true.B)
|
|
c.io.queue.enq.valid.poke(true.B)
|
|
c.io.queue.enq.bits.poke(0x12.U)
|
|
c.clock.step()
|
|
c.io.queue.deq.ready.poke(false.B)
|
|
c.io.queue.enq.ready.expect(true.B)
|
|
c.io.queue.enq.valid.poke(true.B)
|
|
c.io.queue.enq.bits.poke(0x34.U)
|
|
c.clock.step()
|
|
c.io.queue.enq.valid.poke(false.B)
|
|
|
|
// invalidate should work for the head just being dequeued at the same
|
|
// cycle
|
|
c.io.invalidate.valid.poke(true.B)
|
|
c.io.invalidate.bits.poke(0x1.U)
|
|
c.io.queue.deq.ready.poke(true.B)
|
|
c.io.queue.deq.valid.expect(false.B)
|
|
c.clock.step()
|
|
// 0x12 should have been dequeued
|
|
c.io.invalidate.valid.poke(false.B)
|
|
c.io.queue.deq.ready.poke(true.B)
|
|
c.io.queue.deq.valid.expect(true.B)
|
|
c.io.queue.deq.bits.expect(0x34.U)
|
|
}
|
|
}
|
|
|
|
it should "dequeue invalidated head on its own when allowShift" in {
|
|
test(new CoalShiftQueue(gen = UInt(8.W), entries = 4)) { c =>
|
|
c.io.invalidate.valid.poke(false.B)
|
|
|
|
c.io.allowShift.poke(true.B)
|
|
|
|
// prepare
|
|
c.io.queue.deq.ready.poke(false.B)
|
|
c.io.queue.enq.ready.expect(true.B)
|
|
c.io.queue.enq.valid.poke(true.B)
|
|
c.io.queue.enq.bits.poke(0x12.U)
|
|
c.clock.step()
|
|
c.io.queue.enq.ready.expect(true.B)
|
|
c.io.queue.enq.valid.poke(true.B)
|
|
c.io.queue.enq.bits.poke(0x34.U)
|
|
c.clock.step()
|
|
c.io.queue.enq.ready.expect(true.B)
|
|
c.io.queue.enq.valid.poke(true.B)
|
|
c.io.queue.enq.bits.poke(0x56.U)
|
|
c.clock.step()
|
|
c.io.queue.enq.valid.poke(false.B)
|
|
|
|
// invalidate two entries at head
|
|
c.io.invalidate.valid.poke(true.B)
|
|
c.io.invalidate.bits.poke(0x3.U)
|
|
c.io.queue.deq.ready.poke(false.B)
|
|
// [ 0x56 | 0x34(inv) | 0x12(inv) ]
|
|
c.clock.step()
|
|
// [ 0x56 | 0x34(inv) ]
|
|
c.io.invalidate.valid.poke(false.B)
|
|
c.io.queue.deq.ready.poke(false.B)
|
|
c.clock.step()
|
|
// [ 0x56 ]
|
|
c.io.queue.deq.ready.poke(true.B)
|
|
c.io.queue.deq.valid.expect(true.B)
|
|
c.io.queue.deq.bits.expect(0x56.U)
|
|
c.clock.step()
|
|
c.io.queue.deq.ready.poke(true.B)
|
|
c.io.queue.deq.valid.expect(false.B)
|
|
c.clock.step()
|
|
|
|
// do one more enqueue-then-dequeue to see if used bit was properly cleared
|
|
c.io.queue.deq.ready.poke(false.B)
|
|
c.io.queue.enq.ready.expect(true.B)
|
|
c.io.queue.enq.valid.poke(true.B)
|
|
c.io.queue.enq.bits.poke(0x78.U)
|
|
c.clock.step()
|
|
// should dequeue right away
|
|
c.io.queue.enq.valid.poke(false.B)
|
|
c.io.queue.deq.ready.poke(true.B)
|
|
c.io.queue.deq.valid.expect(true.B)
|
|
c.io.queue.deq.bits.expect(0x78.U)
|
|
}
|
|
}
|
|
|
|
it should "overwrite invalidated tail when enqueuing" in {
|
|
test(new CoalShiftQueue(UInt(8.W), 4)) { c =>
|
|
c.io.invalidate.valid.poke(false.B)
|
|
c.io.invalidate.bits.poke(0.U)
|
|
c.io.allowShift.poke(true.B)
|
|
|
|
// prepare
|
|
c.io.queue.deq.ready.poke(false.B)
|
|
c.io.queue.enq.ready.expect(true.B)
|
|
c.io.queue.enq.valid.poke(true.B)
|
|
c.io.queue.enq.bits.poke(0x12.U)
|
|
c.clock.step()
|
|
// invalidate and enqueue at the tail at the same time
|
|
c.io.invalidate.valid.poke(true.B)
|
|
c.io.invalidate.bits.poke(0x1.U)
|
|
c.io.queue.deq.ready.poke(false.B)
|
|
c.io.queue.enq.ready.expect(true.B)
|
|
c.io.queue.enq.valid.poke(true.B)
|
|
c.io.queue.enq.bits.poke(0x34.U)
|
|
c.clock.step()
|
|
c.io.invalidate.valid.poke(false.B)
|
|
c.io.queue.enq.valid.poke(false.B)
|
|
// now should be able to dequeue immediately as tail is overwritten
|
|
c.io.queue.deq.ready.poke(true.B)
|
|
c.io.queue.deq.valid.expect(true.B)
|
|
c.io.queue.deq.bits.expect(0x34)
|
|
}
|
|
}*/
|
|
}
|
|
|
|
object uncoalescerTestConfig extends CoalescerConfig(
|
|
numLanes = 4,
|
|
queueDepth = 2,
|
|
waitTimeout = 8,
|
|
addressWidth = 24,
|
|
dataBusWidth = 5,
|
|
// watermark = 2,
|
|
wordSizeInBytes = 4,
|
|
wordWidth = 2,
|
|
numOldSrcIds = 16,
|
|
numNewSrcIds = 4,
|
|
respQueueDepth = 4,
|
|
coalLogSizes = Seq(4),
|
|
sizeEnum = DefaultInFlightTableSizeEnum,
|
|
arbiterOutputs = 4
|
|
)
|
|
|
|
class UncoalescerUnitTest extends AnyFlatSpec with ChiselScalatestTester {
|
|
behavior of "uncoalescer"
|
|
val numLanes = 4
|
|
val numPerLaneReqs = 2
|
|
val sourceWidth = 2
|
|
val sizeWidth = 2
|
|
// 16B coalescing size
|
|
val coalDataWidth = 128
|
|
val numInflightCoalRequests = 4
|
|
|
|
it should "work in general case" in {
|
|
test(new Uncoalescer(uncoalescerTestConfig))
|
|
// vcs helps with simulation time, but sometimes errors with
|
|
// "mutation occurred during iteration" java error
|
|
// .withAnnotations(Seq(VcsBackendAnnotation))
|
|
{ c =>
|
|
val sourceId = 0.U
|
|
val four = c.io.newEntry.sizeEnumT.FOUR
|
|
c.io.coalReqValid.poke(true.B)
|
|
c.io.newEntry.source.poke(sourceId)
|
|
c.io.newEntry.lanes(0).reqs(0).valid.poke(true.B)
|
|
c.io.newEntry.lanes(0).reqs(0).source.poke(1.U)
|
|
c.io.newEntry.lanes(0).reqs(0).offset.poke(1.U)
|
|
c.io.newEntry.lanes(0).reqs(0).sizeEnum.poke(four)
|
|
c.io.newEntry.lanes(0).reqs(1).valid.poke(true.B)
|
|
c.io.newEntry.lanes(0).reqs(1).source.poke(2.U)
|
|
c.io.newEntry.lanes(0).reqs(1).offset.poke(1.U) // same offset to different lanes
|
|
c.io.newEntry.lanes(0).reqs(1).sizeEnum.poke(four)
|
|
c.io.newEntry.lanes(1).reqs(0).valid.poke(false.B)
|
|
c.io.newEntry.lanes(2).reqs(0).valid.poke(true.B)
|
|
c.io.newEntry.lanes(2).reqs(0).source.poke(2.U)
|
|
c.io.newEntry.lanes(2).reqs(0).offset.poke(2.U)
|
|
c.io.newEntry.lanes(2).reqs(0).sizeEnum.poke(four)
|
|
c.io.newEntry.lanes(2).reqs(1).valid.poke(true.B)
|
|
c.io.newEntry.lanes(2).reqs(1).source.poke(2.U)
|
|
c.io.newEntry.lanes(2).reqs(1).offset.poke(3.U)
|
|
c.io.newEntry.lanes(2).reqs(1).sizeEnum.poke(four)
|
|
c.io.newEntry.lanes(3).reqs(0).valid.poke(false.B)
|
|
|
|
c.clock.step()
|
|
|
|
c.io.coalReqValid.poke(false.B)
|
|
|
|
c.clock.step()
|
|
|
|
c.io.coalResp.valid.poke(true.B)
|
|
c.io.coalResp.bits.source.poke(sourceId)
|
|
val lit = (BigInt(0x0123456789abcdefL) << 64) | BigInt(0x5ca1ab1edeadbeefL)
|
|
// val lit = BigInt(0x0123456789abcdefL)
|
|
c.io.coalResp.bits.data.poke(lit.U)
|
|
|
|
// table lookup is combinational at the same cycle
|
|
c.io.uncoalResps(0)(0).valid.expect(true.B)
|
|
c.io.uncoalResps(1)(0).valid.expect(false.B)
|
|
c.io.uncoalResps(2)(0).valid.expect(true.B)
|
|
c.io.uncoalResps(3)(0).valid.expect(false.B)
|
|
|
|
// offset is counting from LSB
|
|
c.io.uncoalResps(0)(0).bits.data.expect(0x5ca1ab1eL.U)
|
|
c.io.uncoalResps(0)(0).bits.source.expect(1.U)
|
|
c.io.uncoalResps(0)(1).bits.data.expect(0x5ca1ab1eL.U)
|
|
c.io.uncoalResps(0)(1).bits.source.expect(2.U)
|
|
c.io.uncoalResps(2)(0).bits.data.expect(0x89abcdefL.U)
|
|
c.io.uncoalResps(2)(0).bits.source.expect(2.U)
|
|
c.io.uncoalResps(2)(1).bits.data.expect(0x01234567L.U)
|
|
c.io.uncoalResps(2)(1).bits.source.expect(2.U)
|
|
}
|
|
}
|
|
|
|
it should "uncoalesce when coalesced to the same word offset" in {
|
|
test(new Uncoalescer(uncoalescerTestConfig))
|
|
// .withAnnotations(Seq(VcsBackendAnnotation))
|
|
{ c =>
|
|
val sourceId = 0.U
|
|
val four = c.io.newEntry.sizeEnumT.FOUR
|
|
c.io.coalReqValid.poke(true.B)
|
|
c.io.newEntry.source.poke(sourceId)
|
|
c.io.newEntry.lanes(0).reqs(0).valid.poke(true.B)
|
|
c.io.newEntry.lanes(0).reqs(0).source.poke(0.U)
|
|
c.io.newEntry.lanes(0).reqs(0).offset.poke(1.U)
|
|
c.io.newEntry.lanes(0).reqs(0).sizeEnum.poke(four)
|
|
c.io.newEntry.lanes(0).reqs(1).valid.poke(false.B)
|
|
c.io.newEntry.lanes(1).reqs(0).valid.poke(true.B)
|
|
c.io.newEntry.lanes(1).reqs(0).source.poke(1.U)
|
|
c.io.newEntry.lanes(1).reqs(0).offset.poke(1.U)
|
|
c.io.newEntry.lanes(1).reqs(0).sizeEnum.poke(four)
|
|
c.io.newEntry.lanes(1).reqs(1).valid.poke(false.B)
|
|
c.io.newEntry.lanes(2).reqs(0).valid.poke(true.B)
|
|
c.io.newEntry.lanes(2).reqs(0).source.poke(2.U)
|
|
c.io.newEntry.lanes(2).reqs(0).offset.poke(1.U)
|
|
c.io.newEntry.lanes(2).reqs(0).sizeEnum.poke(four)
|
|
c.io.newEntry.lanes(2).reqs(1).valid.poke(false.B)
|
|
c.io.newEntry.lanes(3).reqs(0).valid.poke(true.B)
|
|
c.io.newEntry.lanes(3).reqs(0).source.poke(3.U)
|
|
c.io.newEntry.lanes(3).reqs(0).offset.poke(1.U)
|
|
c.io.newEntry.lanes(3).reqs(0).sizeEnum.poke(four)
|
|
c.io.newEntry.lanes(3).reqs(1).valid.poke(false.B)
|
|
|
|
c.clock.step()
|
|
|
|
c.io.coalReqValid.poke(false.B)
|
|
|
|
c.clock.step()
|
|
|
|
c.io.coalResp.valid.poke(true.B)
|
|
c.io.coalResp.bits.source.poke(sourceId)
|
|
val lit = (BigInt(0x0123456789abcdefL) << 64) | BigInt(0x5ca1ab1edeadbeefL)
|
|
c.io.coalResp.bits.data.poke(lit.U)
|
|
|
|
// table lookup is combinational at the same cycle
|
|
// offset is counting from LSB
|
|
c.io.uncoalResps(0)(0).valid.expect(true.B)
|
|
c.io.uncoalResps(0)(0).bits.data.expect(0x5ca1ab1eL.U)
|
|
c.io.uncoalResps(0)(0).bits.source.expect(0.U)
|
|
c.io.uncoalResps(0)(1).valid.expect(false.B)
|
|
c.io.uncoalResps(1)(0).valid.expect(true.B)
|
|
c.io.uncoalResps(1)(0).bits.data.expect(0x5ca1ab1eL.U)
|
|
c.io.uncoalResps(1)(0).bits.source.expect(1.U)
|
|
c.io.uncoalResps(1)(1).valid.expect(false.B)
|
|
c.io.uncoalResps(2)(0).valid.expect(true.B)
|
|
c.io.uncoalResps(2)(0).bits.data.expect(0x5ca1ab1eL.U)
|
|
c.io.uncoalResps(2)(0).bits.source.expect(2.U)
|
|
c.io.uncoalResps(2)(1).valid.expect(false.B)
|
|
c.io.uncoalResps(3)(0).valid.expect(true.B)
|
|
c.io.uncoalResps(3)(0).bits.data.expect(0x5ca1ab1eL.U)
|
|
c.io.uncoalResps(3)(0).bits.source.expect(3.U)
|
|
c.io.uncoalResps(3)(1).valid.expect(false.B)
|
|
}
|
|
}
|
|
}
|
|
|
|
class CoalInflightTableUnitTest extends AnyFlatSpec with ChiselScalatestTester {
|
|
behavior of "inflight coalesced request table"
|
|
val numLanes = 4
|
|
val numPerLaneReqs = 2
|
|
val sourceWidth = 2
|
|
val entries = 4
|
|
|
|
val offsetBits = 4
|
|
val sizeBits = 2
|
|
|
|
val inflightCoalReqTableEntry =
|
|
new InflightCoalReqTableEntry(
|
|
numLanes,
|
|
numPerLaneReqs,
|
|
sourceWidth,
|
|
offsetBits,
|
|
testConfig.sizeEnum
|
|
)
|
|
|
|
// it should "stop enqueueing when full" in {
|
|
// test(new InflightCoalReqTable(numLanes, sourceWidth, entries)) { c =>
|
|
// // fill up the table
|
|
// for (i <- 0 until entries) {
|
|
// val sourceId = i
|
|
// c.io.enq.ready.expect(true.B)
|
|
// c.io.enq.valid.poke(true.B)
|
|
// c.io.enq.bits.fromLane.poke(0.U)
|
|
// c.io.enq.bits.respSourceId.poke(sourceId.U)
|
|
// c.io.enq.bits.reqSourceIds.foreach { id => id.poke(0.U) }
|
|
// c.io.lookup.ready.poke(false.B)
|
|
// c.clock.step()
|
|
// }
|
|
|
|
// // now cannot enqueue any more
|
|
// c.io.enq.ready.expect(false.B)
|
|
// c.io.enq.valid.poke(true.B)
|
|
// c.io.enq.bits.fromLane.poke(0.U)
|
|
// c.io.enq.bits.respSourceId.poke(0.U)
|
|
// c.io.enq.bits.reqSourceIds.foreach { id => id.poke(0.U) }
|
|
|
|
// c.clock.step()
|
|
// c.io.enq.ready.expect(false.B)
|
|
|
|
// // try to lookup all existing entries
|
|
// for (i <- 0 until entries) {
|
|
// val sourceId = i
|
|
// c.io.enq.valid.poke(false.B)
|
|
// c.io.lookup.ready.poke(true.B)
|
|
// c.io.lookupSourceId.poke(sourceId)
|
|
// c.io.lookup.valid.expect(true.B)
|
|
// c.io.lookup.bits.expect(sourceId)
|
|
// c.clock.step()
|
|
// }
|
|
|
|
// // now the table should be empty
|
|
// for (i <- 0 until entries) {
|
|
// val sourceId = i
|
|
// c.io.enq.valid.poke(false.B)
|
|
// c.io.lookup.ready.poke(true.B)
|
|
// c.io.lookupSourceId.poke(sourceId)
|
|
// c.io.lookup.valid.expect(false.B)
|
|
// c.clock.step()
|
|
// }
|
|
// }
|
|
// }
|
|
// it should "lookup matching entry" in {
|
|
// test(new InflightCoalReqTable(numLanes, sourceWidth, entries))
|
|
// .withAnnotations(Seq(WriteVcdAnnotation)) { c =>
|
|
// c.reset.poke(true.B)
|
|
// c.clock.step(10)
|
|
// c.reset.poke(false.B)
|
|
|
|
// // enqueue one entry to not match at 0th index
|
|
// c.io.enq.ready.expect(true.B)
|
|
// c.io.enq.valid.poke(true.B)
|
|
// c.io.enq.bits.fromLane.poke(0.U)
|
|
// c.io.enq.bits.respSourceId.poke(0.U)
|
|
// c.io.enq.bits.reqSourceIds.foreach { id => id.poke(0.U) }
|
|
|
|
// c.clock.step()
|
|
|
|
// val targetSourceId = 1.U
|
|
// c.io.enq.ready.expect(true.B)
|
|
// c.io.enq.valid.poke(true.B)
|
|
// c.io.enq.bits.fromLane.poke(0.U)
|
|
// c.io.enq.bits.respSourceId.poke(targetSourceId)
|
|
// c.io.enq.bits.reqSourceIds.foreach { id => id.poke(0.U) }
|
|
|
|
// c.clock.step()
|
|
|
|
// c.io.lookup.ready.poke(true.B)
|
|
// c.io.lookupSourceId.poke(targetSourceId)
|
|
// c.io.lookup.valid.expect(true.B)
|
|
// c.io.lookup.bits.expect(targetSourceId)
|
|
|
|
// c.clock.step()
|
|
|
|
// // test if matching entry dequeues after 1 cycle
|
|
// c.io.lookup.ready.poke(true.B)
|
|
// c.io.lookupSourceId.poke(targetSourceId)
|
|
// c.io.lookup.valid.expect(false.B)
|
|
// }
|
|
// }
|
|
// it should "handle lookup and enqueue at the same time" in {
|
|
// test(new InflightCoalReqTable(numLanes, sourceWidth, entries)) { c =>
|
|
// // fill up the table
|
|
// val targetSourceId = 1.U
|
|
// c.io.enq.ready.expect(true.B)
|
|
// c.io.enq.valid.poke(true.B)
|
|
// c.io.enq.bits.fromLane.poke(0.U)
|
|
// c.io.enq.bits.respSourceId.poke(0.U)
|
|
// c.io.enq.bits.reqSourceIds.foreach { id => id.poke(0.U) }
|
|
// c.clock.step()
|
|
// c.io.enq.ready.expect(true.B)
|
|
// c.io.enq.valid.poke(true.B)
|
|
// c.io.enq.bits.fromLane.poke(0.U)
|
|
// c.io.enq.bits.respSourceId.poke(targetSourceId)
|
|
// c.io.enq.bits.reqSourceIds.foreach { id => id.poke(0.U) }
|
|
// c.clock.step()
|
|
|
|
// // do both enqueue and lookup at the same cycle
|
|
// val enqSourceId = 2.U
|
|
// c.io.enq.ready.expect(true.B)
|
|
// c.io.enq.valid.poke(true.B)
|
|
// c.io.enq.bits.fromLane.poke(0.U)
|
|
// c.io.enq.bits.respSourceId.poke(enqSourceId)
|
|
// c.io.enq.bits.reqSourceIds.foreach { id => id.poke(0.U) }
|
|
// c.io.lookup.ready.poke(true.B)
|
|
// c.io.lookupSourceId.poke(targetSourceId)
|
|
|
|
// c.clock.step()
|
|
// }
|
|
// }
|
|
}
|