7e6ebb9e35
This requires config.addressWidth to be increased to 32. FIXME: This breaks CoalescerUnitTest with unsatisfied requirement `Link's max transfer (8) < List<...>'s beatBytes (32)`.
36 lines
1.4 KiB
Scala
36 lines
1.4 KiB
Scala
package freechips.rocketchip.tilelink
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import freechips.rocketchip.diplomacy.LazyModule
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import freechips.rocketchip.subsystem.BaseSubsystem
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import org.chipsalliance.cde.config.Parameters
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// The trait is attached to DigitalTop of Chipyard system, informing it indeed
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// has the ability to attach GPU tracer node onto the system bus
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trait CanHaveMemtraceCore { this: BaseSubsystem =>
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implicit val p: Parameters
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p(MemtraceCoreKey).map { param =>
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// Safe to use get as WithMemtraceCore requires WithNLanes to be defined
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val simtParam = p(SIMTCoreKey).get
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val config = defaultConfig.copy(numLanes = simtParam.nLanes)
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val tracer = LazyModule(
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new MemTraceDriver(config, param.tracefilename, param.traceHasSource)(p)
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)
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// Must use :=* to ensure the N edges from Tracer doesn't get merged into 1
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// when connecting to SBus
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println(
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s"============ MemTraceDriver instantiated [filename=${param.tracefilename}]"
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)
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val upstream = p(CoalescerKey) match {
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case Some(coalParam) => {
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val coal = LazyModule(new CoalescingUnit(coalParam))
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println(s"============ CoalescingUnit instantiated [numLanes=${coalParam.numLanes}]")
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coal.cpuNode :=* tracer.node // N lanes
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coal.aggregateNode // N+1 lanes
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}
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case None => tracer.node
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}
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sbus.fromPort(Some("gpu-tracer"))() :=* upstream
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}
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}
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