303 lines
9.9 KiB
Scala
303 lines
9.9 KiB
Scala
// See LICENSE.SiFive for license details.
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package freechips.rocketchip.tilelink
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import chisel3._
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import chisel3.util._
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import freechips.rocketchip.config.Parameters
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.devices.tilelink.TLTestRAM
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import freechips.rocketchip.util.ShiftQueue
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import freechips.rocketchip.unittest._
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class CoalRegEntry(val sourceWidth: Int, val addressWidth: Int) extends Bundle {
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val source = UInt(sourceWidth.W)
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val address = UInt(addressWidth.W)
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val data = UInt(64.W /* FIXME hardcoded */ )
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}
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class CoalescingUnit(numLanes: Int = 1)(implicit p: Parameters)
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extends LazyModule {
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// val beatBytes = 8
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// val seqParam = Seq(
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// TLSlaveParameters.v1(
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// address = Seq(AddressSet(0x0000, 0xffffff)),
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// // resources = device.reg,
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// regionType = RegionType.UNCACHED,
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// executable = true,
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// supportsArithmetic = TransferSizes(1, beatBytes),
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// supportsLogical = TransferSizes(1, beatBytes),
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// supportsGet = TransferSizes(1, beatBytes),
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// supportsPutFull = TransferSizes(1, beatBytes),
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// supportsPutPartial = TransferSizes(1, beatBytes),
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// supportsHint = TransferSizes(1, beatBytes),
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// fifoId = Some(0)
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// )
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// )
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// Identity node that captures the incoming TL requests and passes them
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// through the other end, dropping coalesced requests. This is what the
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// upstream node will connect to.
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val node = TLIdentityNode()
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// Master node that actually generates coalesced requests.
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// This and the IdentityNode will be the two outward-facing nodes that the
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// downstream, either L1 or the system bus, will connect to.
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protected val clientParam = Seq(
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TLMasterParameters.v1(
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name = "CoalescerNode",
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sourceId = IdRange(0, 0xffff)
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// visibility = Seq(AddressSet(0x0000, 0xffffff))
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)
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)
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protected val coalescerNode = TLClientNode(
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Seq(TLMasterPortParameters.v1(clientParam))
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)
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// Connect master node as the first of the N+1-th inward edges of the
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// IdentityNode
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node :=* coalescerNode
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lazy val module = new Impl
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class Impl extends LazyModuleImp(this) {
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// Per-lane FIFO that buffers incoming requests
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val sourceWidth = node.in(0)._1.params.sourceBits
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val addressWidth = node.in(0)._1.params.addressBits
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val coalRegEntry = new CoalRegEntry(sourceWidth, addressWidth)
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val fifos = Seq.tabulate(numLanes) { _ =>
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Module(
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new ShiftQueue(coalRegEntry, 4 /* FIXME hardcoded */ )
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)
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}
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println(s"============= node edges: ${node.in.length}")
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// Override IdentityNode implementation so that we wire node output to the
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// FIFO output, instead of directly passing through node input.
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// See IdentityNode definition in `diplomacy/Nodes.scala`.
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(node.in zip node.out).zipWithIndex.foreach {
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case (((_, edgeIn), _), 0) =>
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// No need to do anything on the edge from coalescerNode
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assert(
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edgeIn.master.masters(0).name == "CoalescerNode",
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"First edge is not connected to the coalescer master node"
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)
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case (((tlIn, _), (tlOut, edgeOut)), i) =>
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val fifo = fifos(i - 1)
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val newReq = Wire(coalRegEntry)
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newReq.source := tlIn.a.bits.source
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newReq.address := tlIn.a.bits.address
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newReq.data := tlIn.a.bits.data
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fifo.io.enq.valid := tlIn.a.valid
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fifo.io.enq.bits := newReq
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// FIXME: deq.ready should respect the ready state of the downstream
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// module, e.g. Xbar or NoC.
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fifo.io.deq.ready := true.B
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val head = fifo.io.deq.bits
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tlOut.a.valid := fifo.io.deq.valid
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// FIXME: generate Get or Put according to read/write
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val (legal, bits) = edgeOut.Get(
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fromSource = head.source,
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// `toAddress` should be aligned to 2**lgSize
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toAddress = head.address,
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// 64 bits = 8 bytes = 2**(3) bytes
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lgSize = 0.U
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// data = (i + 100).U
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// data = tlIn.a.bits.data + 0xFF.U
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)
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assert(legal, "unhandled illegal TL req gen")
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tlOut.a.bits := bits
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tlIn.d <> tlOut.d
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dontTouch(tlIn.a)
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dontTouch(tlOut.a)
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dontTouch(tlOut.d)
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}
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val (tlCoal, edgeCoal) = coalescerNode.out(0)
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// FIXME: currently generating bogus coalesced requests
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tlCoal.a.valid := true.B
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val (legal, bits) = edgeCoal.Get(
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fromSource = 0.U,
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// `toAddress` should be aligned to 2**lgSize
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toAddress = 0xabcd00.U,
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// 64 bits = 8 bytes = 2**(3) bytes
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lgSize = 3.U
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)
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assert(legal, "unhandled illegal TL req gen")
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tlCoal.a.bits := bits
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val coalRespValid = Wire(Bool())
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coalRespValid := tlCoal.a.valid
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val coalRespData = Wire(UInt(tlCoal.params.dataBits.W))
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coalRespData := tlCoal.d.bits.data
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dontTouch(coalRespValid)
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dontTouch(coalRespData)
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}
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}
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class MemTraceDriver(numLanes: Int = 1)(implicit p: Parameters)
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extends LazyModule {
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// Create N client nodes together
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val laneNodes = Seq.tabulate(numLanes) { i =>
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val clientParam = Seq(
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TLMasterParameters.v1(
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name = "MemTraceDriver" + i.toString,
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sourceId = IdRange(0, 0xffff)
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// visibility = Seq(AddressSet(0x0000, 0xffffff))
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)
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)
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TLClientNode(Seq(TLMasterPortParameters.v1(clientParam)))
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}
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// Combine N outgoing client node into 1 idenity node for diplomatic
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// connection.
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val node = TLIdentityNode()
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laneNodes.foreach { l => node := l }
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lazy val module = new MemTraceDriverImp(this, numLanes)
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}
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class TraceReq extends Bundle {
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val valid = Bool()
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val address = UInt(64.W)
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val is_store = Bool()
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val mask = UInt(8.W)
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val data = UInt(64.W)
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}
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class MemTraceDriverImp(outer: MemTraceDriver, numLanes: Int)
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extends LazyModuleImp(outer)
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with UnitTestModule {
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val sim = Module(
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new SimMemTrace(filename = "vecadd.core1.thread4.trace", numLanes)
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)
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sim.io.clock := clock
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sim.io.reset := reset.asBool
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sim.io.trace_read.ready := true.B
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// Split output of SimMemTrace, which is flattened across all lanes,
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// back to each lane's.
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// Maybe this part can be improved, since now we are still mannually shifting everything
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val laneReqs = Wire(Vec(numLanes, new TraceReq))
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laneReqs.zipWithIndex.foreach { case (req, i) =>
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req.valid := (sim.io.trace_read.valid >> i)
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req.address := (sim.io.trace_read.address >> (64 * i))
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req.is_store := (sim.io.trace_read.is_store >> i)
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req.mask := (sim.io.trace_read.store_mask >> (8 * i))
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req.data := (sim.io.trace_read.data >> (64 * i))
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}
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// To prevent collision of sourceId with a current in-flight message,
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// just use a counter that increments indefinitely as the sourceId of new
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// messages.
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val sourceIdCounter = Reg(UInt(64.W))
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sourceIdCounter := sourceIdCounter + 1.U
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// Connect each lane to its respective TL node.
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(outer.laneNodes zip laneReqs).foreach { case (node, req) =>
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val (tlOut, edge) = node.out(0)
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tlOut.a.valid := req.valid
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val (plegal, pbits) = edge.Put(
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fromSource = sourceIdCounter,
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toAddress = req.address,
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// Memory trace addresses are not aligned in word addresses (e.g.
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// read of size 1 at 0x1007) so leave lgSize to 0.
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// TODO: We need to build an issue logic that aligns addresses at
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// word boundaries and uses masks.
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// NOTE: this is in byte size, not bits
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lgSize = 0.U,
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data = req.data
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)
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val (glegal, gbits) = edge.Get(
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fromSource = sourceIdCounter,
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toAddress = req.address,
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lgSize = 0.U
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)
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val legal = Mux(req.is_store, plegal, glegal)
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val bits = Mux(req.is_store, pbits, gbits)
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assert(legal, "unhandled illegal TL req gen")
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tlOut.a.bits := bits
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// tl_out.a.bits.mask := 0xf.U
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dontTouch(tlOut.a)
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tlOut.d.ready := true.B
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}
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io.finished := sim.io.trace_read.finished
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// Clock Counter, for debugging purpose
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val clkcount = RegInit(0.U(64.W))
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clkcount := clkcount + 1.U
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dontTouch(clkcount)
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}
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class SimMemTrace(val filename: String, numLanes: Int)
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extends BlackBox(
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Map("FILENAME" -> filename, "NUM_LANES" -> numLanes)
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)
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with HasBlackBoxResource {
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val io = IO(new Bundle {
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val clock = Input(Clock())
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val reset = Input(Bool())
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// These names have to match declarations in the Verilog code, eg.
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// trace_read_address.
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val trace_read = new Bundle {
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val ready = Input(Bool())
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val valid = Output(UInt(numLanes.W))
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// Chisel can't interface with Verilog 2D port, so flatten all lanes into
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// single wide 1D array.
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// TODO: assumes 64-bit address.
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val address = Output(UInt((64 * numLanes).W))
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val is_store = Output(UInt(numLanes.W))
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val store_mask = Output(UInt((8 * numLanes).W))
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val data = Output(UInt((64 * numLanes).W))
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val finished = Output(Bool())
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}
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})
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addResource("/vsrc/SimMemTrace.v")
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addResource("/csrc/SimMemTrace.cc")
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addResource("/csrc/SimMemTrace.h")
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}
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class CoalConnectTrace(implicit p: Parameters) extends LazyModule {
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// TODO: use parameters for numLanes
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val numLanes = 4
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val coal = LazyModule(new CoalescingUnit(numLanes))
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val driver = LazyModule(new MemTraceDriver(numLanes))
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coal.node :=* driver.node
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// Use TLTestRAM as bogus downstream TL manager nodes
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// TODO: swap this out with a memtrace logger
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val rams = Seq.tabulate(numLanes + 1) { _ =>
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LazyModule(
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// TODO: properly propagate beatBytes?
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new TLRAM(address = AddressSet(0x0000, 0xffffff), beatBytes = 8)
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)
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}
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// Connect all (N+1) outputs of coal to separate TestRAM modules
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rams.foreach { r => r.node := coal.node }
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lazy val module = new Impl
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class Impl extends LazyModuleImp(this) with UnitTestModule {
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driver.module.io.start := io.start
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io.finished := driver.module.io.finished
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}
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}
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class CoalescingUnitTest(timeout: Int = 500000)(implicit p: Parameters)
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extends UnitTest(timeout) {
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val dut = Module(LazyModule(new CoalConnectTrace).module)
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dut.io.start := io.start
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io.finished := dut.io.finished
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}
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