Hansung Kim
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caa5ebf943
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Reformat MemTraceReader
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2023-05-06 01:47:33 -07:00 |
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Vamber Yang
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8ccaf3864d
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Support for more realistic MemTracer step2 (DONE), make Verilog Blackbox DPI output data immediately and make .cc file maintain pointer when downstream is not ready
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2023-05-02 22:06:16 -07:00 |
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Hansung Kim
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282434eb7d
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Basic C++ file IO for trace logger
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2023-04-17 16:20:27 -07:00 |
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Hansung Kim
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1057ed59d3
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Parse log2(size) from trace; set is_store from TL opcode
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2023-04-11 18:23:50 -07:00 |
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Hansung Kim
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71f334bb22
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Fix size parsing from memtrace
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2023-04-11 17:36:45 -07:00 |
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Vamber Yang
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8e5254292b
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Attach MemTracer to SBus , all physical addr hashed between 0X80000000->0X90000000
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2023-04-05 23:43:22 -07:00 |
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Hansung Kim
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bdc32b765f
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Accept memory trace filename from VCS plusargs
Now can use `EXTRA_SIM_FLAGS="+memtracefile=<tracefile>"` to simulate
with different trace files without recompiling.
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2023-04-03 17:41:47 -07:00 |
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Hansung Kim
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9bfb813e1b
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Thread -> Lane
"thread" is confusing, unify to lane when denoting a hardware SIMD lane
inside a single warp.
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2023-03-09 22:09:21 -08:00 |
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Vamber Yang
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0de09daa05
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MemTracer able to read and write according to trace file, also support thread_id skipping in trace file
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2023-03-08 17:34:10 -08:00 |
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Hansung Kim
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41ecf6bc20
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Squelch debug prints in SimMemTrace
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2023-03-07 17:53:09 -08:00 |
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Hansung Kim
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172ab51355
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Fix formatting and unused warnings
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2023-03-03 23:44:50 -08:00 |
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Hansung Kim
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5f55a7578f
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Recover lost changes
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2023-03-03 22:36:54 -08:00 |
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Hansung Kim
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dcb49f7683
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Doc update
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2023-03-03 21:22:56 -08:00 |
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Hansung Kim
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9025729c0e
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Emit address in addition to cycle
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2023-02-27 17:36:54 -08:00 |
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Hansung Kim
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0ebaed5f1b
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Communicate trace cycle data from C++ to Chisel
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2023-02-27 14:40:49 -08:00 |
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Hansung Kim
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72de4bca66
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Initial parsing of memory trace file in C++
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2023-02-27 13:47:30 -08:00 |
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Hansung Kim
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80e4b5c734
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Set up simple DPI for trace-driven testing
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2023-02-26 20:39:19 -08:00 |
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