From f9b7e9fbe44234851e5c23770bd5c9c3fcb9040a Mon Sep 17 00:00:00 2001 From: Richard Yan Date: Tue, 16 Jan 2024 16:21:50 -0800 Subject: [PATCH] restructure from rocket-chip to radiance --- src/main/resources/csrc/softfloat | 1 + .../memory/CanHaveMemtraceCore.scala | 5 +- .../radiance/memory/CanHaveRadianceROMs.scala | 16 ++ .../{ => radiance}/memory/Coalescing.scala | 6 +- .../scala/radiance/memory/RadianceROM.scala | 54 +++++++ .../{ => radiance}/memory/UnitTest.scala | 83 +--------- .../{ => radiance}/memory/VortexBank.scala | 2 +- .../scala/radiance/subsystem/Configs.scala | 153 ++++++++++++++++++ .../subsystem/RadianceSubsystem.scala | 11 ++ .../{ => radiance}/tile/VortexCore.scala | 2 +- .../{ => radiance}/tile/VortexTile.scala | 4 +- 11 files changed, 247 insertions(+), 90 deletions(-) create mode 120000 src/main/resources/csrc/softfloat rename src/main/scala/{ => radiance}/memory/CanHaveMemtraceCore.scala (97%) create mode 100644 src/main/scala/radiance/memory/CanHaveRadianceROMs.scala rename src/main/scala/{ => radiance}/memory/Coalescing.scala (99%) create mode 100644 src/main/scala/radiance/memory/RadianceROM.scala rename src/main/scala/{ => radiance}/memory/UnitTest.scala (63%) rename src/main/scala/{ => radiance}/memory/VortexBank.scala (99%) create mode 100644 src/main/scala/radiance/subsystem/Configs.scala create mode 100644 src/main/scala/radiance/subsystem/RadianceSubsystem.scala rename src/main/scala/{ => radiance}/tile/VortexCore.scala (99%) rename src/main/scala/{ => radiance}/tile/VortexTile.scala (99%) diff --git a/src/main/resources/csrc/softfloat b/src/main/resources/csrc/softfloat new file mode 120000 index 0000000..4d737e3 --- /dev/null +++ b/src/main/resources/csrc/softfloat @@ -0,0 +1 @@ +../../../../../hardfloat/berkeley-softfloat-3/source \ No newline at end of file diff --git a/src/main/scala/memory/CanHaveMemtraceCore.scala b/src/main/scala/radiance/memory/CanHaveMemtraceCore.scala similarity index 97% rename from src/main/scala/memory/CanHaveMemtraceCore.scala rename to src/main/scala/radiance/memory/CanHaveMemtraceCore.scala index d9b1331..9f132a6 100644 --- a/src/main/scala/memory/CanHaveMemtraceCore.scala +++ b/src/main/scala/radiance/memory/CanHaveMemtraceCore.scala @@ -1,10 +1,9 @@ -package freechips.rocketchip.tilelink +package radiance.memory import freechips.rocketchip.diplomacy.LazyModule import freechips.rocketchip.subsystem.BaseSubsystem import org.chipsalliance.cde.config.Parameters -import freechips.rocketchip.rocket - +import freechips.rocketchip.tilelink._ // TODO: possibly move to somewhere closer to CoalescingUnit // TODO: separate coalescer config from CanHaveMemtraceCore diff --git a/src/main/scala/radiance/memory/CanHaveRadianceROMs.scala b/src/main/scala/radiance/memory/CanHaveRadianceROMs.scala new file mode 100644 index 0000000..bf56ded --- /dev/null +++ b/src/main/scala/radiance/memory/CanHaveRadianceROMs.scala @@ -0,0 +1,16 @@ +package radiance.memory + +import freechips.rocketchip.subsystem._ +import org.chipsalliance.cde.config.Parameters + +// TODO: possibly move to somewhere closer to CoalescingUnit +// TODO: separate coalescer config from CanHaveMemtraceCore + +// The trait is attached to DigitalTop of Chipyard system, informing it indeed +// has the ability to attach GPU tracer node onto the system bus +trait CanHaveRadianceROMs { this: BaseSubsystem with HasTiles => + implicit val p: Parameters + + p(RadianceROMsLocated()).foreach(_.foreach { rom => RadianceROM.attachROM(rom, this, CBUS) }) + +} diff --git a/src/main/scala/memory/Coalescing.scala b/src/main/scala/radiance/memory/Coalescing.scala similarity index 99% rename from src/main/scala/memory/Coalescing.scala rename to src/main/scala/radiance/memory/Coalescing.scala index 3bc23cf..be04e48 100644 --- a/src/main/scala/memory/Coalescing.scala +++ b/src/main/scala/radiance/memory/Coalescing.scala @@ -1,14 +1,14 @@ // See LICENSE.SiFive for license details. -package freechips.rocketchip.tilelink +package radiance.memory import chisel3._ import chisel3.util._ -import org.chipsalliance.cde.config.{Parameters, Field} +import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.diplomacy._ -// import freechips.rocketchip.devices.tilelink.TLTestRAM import freechips.rocketchip.util.MultiPortQueue import freechips.rocketchip.unittest._ +import freechips.rocketchip.tilelink._ // TODO: find better place for these diff --git a/src/main/scala/radiance/memory/RadianceROM.scala b/src/main/scala/radiance/memory/RadianceROM.scala new file mode 100644 index 0000000..fc10ed7 --- /dev/null +++ b/src/main/scala/radiance/memory/RadianceROM.scala @@ -0,0 +1,54 @@ +// See LICENSE.SiFive for license details. + +package radiance.memory + +import chisel3._ +import chisel3.util.log2Ceil +import org.chipsalliance.cde.config.{Config, Field, Parameters} +import freechips.rocketchip.subsystem.{BaseSubsystem, HasTiles, HierarchicalLocation, InSubsystem, TLBusWrapperLocation} +import freechips.rocketchip.diplomacy._ +import freechips.rocketchip.tilelink._ +import freechips.rocketchip.devices.tilelink._ +import freechips.rocketchip.prci.ClockSinkDomain + +import java.nio.ByteBuffer +import java.nio.file.{Files, Paths} + +/** Size, location and contents of the boot rom. */ +case class RadianceROMParams(address: BigInt, + size: Int = 0x10000, + contentFileName: String) +case class RadianceROMsLocated() extends Field[Option[Seq[RadianceROMParams]]](None) + +object RadianceROM { + /** BootROM.attach not only instantiates a TLROM and attaches it to the tilelink interconnect + * at a configurable location, but also drives the tiles' reset vectors to point + * at its 'hang' address parameter value. + */ + def attach(params: BootROMParams, subsystem: BaseSubsystem with HasTiles, where: TLBusWrapperLocation, + driveResetVector: Boolean = true) (implicit p: Parameters): TLROM = { + val tlbus = subsystem.locateTLBusWrapper(where) + val bootROMDomainWrapper = LazyModule(new ClockSinkDomain(take = None)) + bootROMDomainWrapper.clockNode := tlbus.fixedClockNode + + lazy val contents = { + val romdata = Files.readAllBytes(Paths.get(params.contentFileName)) + val rom = ByteBuffer.wrap(romdata) + rom.array() ++ subsystem.dtb.contents + } + + val bootrom = bootROMDomainWrapper { + LazyModule(new TLROM(params.address, params.size, contents, true, tlbus.beatBytes)) + } + + bootrom.node := tlbus.coupleTo("bootrom"){ TLFragmenter(tlbus) := _ } + + bootrom + } + + def attachROM(params: RadianceROMParams, subsystem: BaseSubsystem with HasTiles, where: TLBusWrapperLocation) + (implicit p: Parameters): Unit = { + attach(BootROMParams(address = params.address, size = params.size, contentFileName = params.contentFileName), + subsystem, where, driveResetVector = false) + } +} diff --git a/src/main/scala/memory/UnitTest.scala b/src/main/scala/radiance/memory/UnitTest.scala similarity index 63% rename from src/main/scala/memory/UnitTest.scala rename to src/main/scala/radiance/memory/UnitTest.scala index 825bc9d..866469c 100644 --- a/src/main/scala/memory/UnitTest.scala +++ b/src/main/scala/radiance/memory/UnitTest.scala @@ -1,6 +1,6 @@ // See LICENSE.SiFive for license details. -package freechips.rocketchip.unittest +package radiance.memory import chisel3._ import freechips.rocketchip.amba.ahb._ @@ -11,7 +11,8 @@ import freechips.rocketchip.subsystem.{BaseSubsystemConfig} import freechips.rocketchip.devices.tilelink._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.util._ -import freechips.rocketchip.subsystem.WithSimtLanes +import radiance.subsystem.WithSimtLanes +import freechips.rocketchip.unittest._ //import rocket.VortexFatBankTest case object TestDurationMultiplier extends Field[Int] @@ -19,84 +20,6 @@ case object TestDurationMultiplier extends Field[Int] class WithTestDuration(x: Int) extends Config((site, here, up) => { case TestDurationMultiplier => x }) - -class WithAMBAUnitTests extends Config((site, here, up) => { - case UnitTests => (q: Parameters) => { - implicit val p = q - val txns = 100 * site(TestDurationMultiplier) - val timeout = 50000 * site(TestDurationMultiplier) - Seq( - Module(new AHBBridgeTest(true, txns=8*txns, timeout=timeout)), - Module(new AHBNativeTest(true, txns=6*txns, timeout=timeout)), - Module(new AHBNativeTest(false, txns=6*txns, timeout=timeout)), - Module(new APBBridgeTest(true, txns=6*txns, timeout=timeout)), - Module(new APBBridgeTest(false, txns=6*txns, timeout=timeout)), - Module(new AXI4LiteFuzzRAMTest( txns=6*txns, timeout=timeout)), - Module(new AXI4LiteUserBitsFuzzRAMTest(txns=6*txns, timeout=timeout)), - Module(new AXI4FullFuzzRAMTest( txns=3*txns, timeout=timeout)), - Module(new AXI4BridgeTest( txns=3*txns, timeout=timeout)), - Module(new AXI4XbarTest( txns=1*txns, timeout=timeout)), - Module(new AXI4RAMAsyncCrossingTest( txns=3*txns, timeout=timeout)), - Module(new AXI4RAMCreditedCrossingTest(txns=3*txns, timeout=timeout))) } -}) - -class WithTLSimpleUnitTests extends Config((site, here, up) => { - case UnitTests => (q: Parameters) => { - implicit val p = q - val txns = 100 * site(TestDurationMultiplier) - val timeout = 50000 * site(TestDurationMultiplier) - Seq( - Module(new TLRAMSimpleTest(1, true, txns=15*txns, timeout=timeout)), - Module(new TLRAMSimpleTest(4, false,txns=15*txns, timeout=timeout)), - Module(new TLRAMSimpleTest(16, true, txns=15*txns, timeout=timeout)), - Module(new TLRAMZeroDelayTest(4, txns=15*txns, timeout=timeout)), - Module(new TLRAMHintHandlerTest( txns=15*txns, timeout=timeout)), - Module(new TLFuzzRAMTest( txns= 3*txns, timeout=timeout)), - Module(new TLRR0Test( txns= 3*txns, timeout=timeout)), - Module(new TLRR1Test( txns= 3*txns, timeout=timeout)), - Module(new TLDecoupledArbiterLowestTest( txns= 3*txns, timeout=timeout)), - Module(new TLDecoupledArbiterHighestTest(txns= 3*txns, timeout=timeout)), - Module(new TLDecoupledArbiterRobinTest( txns= 3*txns, timeout=timeout)), - Module(new TLRAMRationalCrossingTest(txns= 3*txns, timeout=timeout)), - Module(new TLRAMAsyncCrossingTest( txns= 5*txns, timeout=timeout)), - Module(new TLRAMCreditedCrossingTest(txns= 5*txns, timeout=timeout)), - Module(new TLRAMAtomicAutomataTest( txns=10*txns, timeout=timeout)), - Module(new TLRAMECCTest(8, 4, true, txns=15*txns, timeout=timeout)), - Module(new TLRAMECCTest(4, 1, true, txns=15*txns, timeout=timeout)), - Module(new TLRAMECCTest(1, 1, true, txns=15*txns, timeout=timeout)), - Module(new TLRAMECCTest(8, 4, false, txns=15*txns, timeout=timeout)), - Module(new TLRAMECCTest(4, 1, false, txns=15*txns, timeout=timeout)), - Module(new TLRAMECCTest(1, 1, false, txns=15*txns, timeout=timeout)) ) } -}) - -class WithTLWidthUnitTests extends Config((site, here, up) => { - case UnitTests => (q: Parameters) => { - implicit val p = q - val txns = 100 * site(TestDurationMultiplier) - val timeout = 50000 * site(TestDurationMultiplier) - Seq( - Module(new TLRAMFragmenterTest( 4, 256, txns= 5*txns, timeout=timeout)), - Module(new TLRAMFragmenterTest(16, 64, txns=15*txns, timeout=timeout)), - Module(new TLRAMFragmenterTest( 4, 16, txns=15*txns, timeout=timeout)), - Module(new TLRAMWidthWidgetTest( 1, 1, txns= 1*txns, timeout=timeout)), - Module(new TLRAMWidthWidgetTest( 4, 64, txns= 4*txns, timeout=timeout)), - Module(new TLRAMWidthWidgetTest(64, 4, txns= 5*txns, timeout=timeout)) ) } -}) - -class WithTLXbarUnitTests extends Config((site, here, up) => { - case UnitTests => (q: Parameters) => { - implicit val p = q - val txns = 100 * site(TestDurationMultiplier) - val timeout = 50000 * site(TestDurationMultiplier) - Seq( - Module(new TLJbarTest(3, 2, txns=5*txns, timeout=timeout)), - Module(new TLRAMXbarTest(1, txns=5*txns, timeout=timeout)), - Module(new TLRAMXbarTest(2, txns=5*txns, timeout=timeout)), - Module(new TLRAMXbarTest(8, txns=5*txns, timeout=timeout)), - Module(new TLMulticlientXbarTest(4,4, txns=2*txns, timeout=timeout)), - Module(new TLMasterMuxTest( txns=5*txns, timeout=timeout)) ) } -}) - class WithCoalescingUnitTests extends Config((site, _, _) => { case UnitTests => (q: Parameters) => { implicit val p = q diff --git a/src/main/scala/memory/VortexBank.scala b/src/main/scala/radiance/memory/VortexBank.scala similarity index 99% rename from src/main/scala/memory/VortexBank.scala rename to src/main/scala/radiance/memory/VortexBank.scala index 1c622b3..fa216a0 100644 --- a/src/main/scala/memory/VortexBank.scala +++ b/src/main/scala/radiance/memory/VortexBank.scala @@ -1,4 +1,4 @@ -package freechips.rocketchip.tilelink +package radiance.memory import chisel3._ import chisel3.util._ diff --git a/src/main/scala/radiance/subsystem/Configs.scala b/src/main/scala/radiance/subsystem/Configs.scala new file mode 100644 index 0000000..9c6bbfb --- /dev/null +++ b/src/main/scala/radiance/subsystem/Configs.scala @@ -0,0 +1,153 @@ +// See LICENSE.SiFive for license details. +// See LICENSE.Berkeley for license details. + +package radiance.subsystem + +import chisel3.util._ +import org.chipsalliance.cde.config._ +import freechips.rocketchip.rocket._ +import freechips.rocketchip.tile._ +import freechips.rocketchip.subsystem._ +import radiance.tile._ +import radiance.memory._ + +class WithRadianceCores( + n: Int, + useVxCache: Boolean +) extends Config((site, _, up) => { + case XLen => 32 + case TilesLocated(InSubsystem) => { + val prev = up(TilesLocated(InSubsystem), site) + val idOffset = prev.size + val vortex = VortexTileParams( + core = VortexCoreParams(fpu = None), + btb = None, + useVxCache = useVxCache, + dcache = Some(DCacheParams( + rowBits = site(SystemBusKey).beatBits, + nSets = 64, + nWays = 1, + nTLBSets = 1, + nTLBWays = 1, + nTLBBasePageSectors = 1, + nTLBSuperpages = 1, + nMSHRs = 0, + blockBytes = site(CacheBlockBytes))), + icache = Some(ICacheParams( + rowBits = site(SystemBusKey).beatBits, + nSets = 64, + nWays = 1, + nTLBSets = 1, + nTLBWays = 1, + nTLBBasePageSectors = 1, + nTLBSuperpages = 1, + blockBytes = site(CacheBlockBytes)))) + List.tabulate(n)(i => VortexTileAttachParams( + vortex.copy(hartId = i + idOffset), + RocketCrossingParams() + )) ++ prev + } +}) + +// `nSrcIds`: number of source IDs for dmem requests on each SIMT lane +class WithSimtLanes(nLanes: Int, nSrcIds: Int = 8) extends Config((site, _, up) => { + case SIMTCoreKey => { + Some(up(SIMTCoreKey, site).getOrElse(SIMTCoreParams()).copy( + nLanes = nLanes, + nSrcIds = nSrcIds + )) + } +}) + +class WithMemtraceCore(tracefilename: String, traceHasSource: Boolean = false) +extends Config((site, _, _) => { + case MemtraceCoreKey => { + require( + site(SIMTCoreKey).isDefined, + "Memtrace core requires a SIMT configuration. Use WithNLanes to enable SIMT." + ) + Some(MemtraceCoreParams(tracefilename, traceHasSource)) + } +}) + +class WithPriorityCoalXbar extends Config((site, _, up) => { + case CoalXbarKey => { + Some(up(CoalXbarKey, site).getOrElse(CoalXbarParam)) + } +}) + +class WithVortexL1Banks(nBanks: Int = 4) extends Config ((site, _, up) => { + case VortexL1Key => { + Some(defaultVortexL1Config.copy(numBanks = nBanks)) + } +}) + +class WithCoalescer(nNewSrcIds: Int = 8) extends Config((site, _, up) => { + case CoalescerKey => { + val (nLanes, numOldSrcIds) = up(SIMTCoreKey, site) match { + case Some(param) => (param.nLanes, param.nSrcIds) + case None => (1,1) + } + + val sbusWidthInBytes = site(SystemBusKey).beatBytes + // FIXME: coalescer fails to instantiate with 4-byte bus + require(sbusWidthInBytes > 2, + "FIXME: coalescer currently doesn't instantiate with 4-byte sbus") + + // If instantiating L1 cache, the maximum coalescing size should match the + // cache line size + val maxCoalSizeInBytes = up(VortexL1Key, site) match { + case Some(param) => + (param.wordSize) + case None => sbusWidthInBytes + } + + // Note: this config chooses a single-sized coalescing logic by default. + Some(DefaultCoalescerConfig.copy( + numLanes = nLanes, + numOldSrcIds = numOldSrcIds, + numNewSrcIds = nNewSrcIds, + addressWidth = 32, // FIXME hardcoded as 32-bit system + dataBusWidth = log2Ceil(maxCoalSizeInBytes), + coalLogSizes = Seq(log2Ceil(maxCoalSizeInBytes)) + ) + ) + } +}) + +class WithNCustomSmallRocketCores( + n: Int, + overrideIdOffset: Option[Int] = None, + crossing: RocketCrossingParams = RocketCrossingParams() + ) extends Config((site, here, up) => { + case TilesLocated(InSubsystem) => { + val prev = up(TilesLocated(InSubsystem), site) + val idOffset = overrideIdOffset.getOrElse(prev.size) + val med = RocketTileParams( + core = RocketCoreParams(fpu = None), + btb = None, + dcache = Some(DCacheParams( + rowBits = site(SystemBusKey).beatBits, + nSets = 2, + nWays = 1, + nTLBSets = 1, + nTLBWays = 2, + nTLBBasePageSectors = 1, + nTLBSuperpages = 1, + nMSHRs = 0, + blockBytes = site(CacheBlockBytes))), + icache = Some(ICacheParams( + rowBits = site(SystemBusKey).beatBits, + nSets = 2, + nWays = 1, + nTLBSets = 1, + nTLBWays = 2, + nTLBBasePageSectors = 1, + nTLBSuperpages = 1, + blockBytes = site(CacheBlockBytes)))) + List.tabulate(n)(i => RocketTileAttachParams( + med.copy(hartId = i + idOffset), + crossing + )) ++ prev + } +}) \ No newline at end of file diff --git a/src/main/scala/radiance/subsystem/RadianceSubsystem.scala b/src/main/scala/radiance/subsystem/RadianceSubsystem.scala new file mode 100644 index 0000000..6c84d72 --- /dev/null +++ b/src/main/scala/radiance/subsystem/RadianceSubsystem.scala @@ -0,0 +1,11 @@ +// See LICENSE.SiFive for license details. + +package radiance.subsystem + +import freechips.rocketchip.subsystem._ +import radiance.tile._ + +case class VortexTileAttachParams( + tileParams: VortexTileParams, + crossingParams: RocketCrossingParams +) extends CanAttachTile { type TileType = VortexTile } diff --git a/src/main/scala/tile/VortexCore.scala b/src/main/scala/radiance/tile/VortexCore.scala similarity index 99% rename from src/main/scala/tile/VortexCore.scala rename to src/main/scala/radiance/tile/VortexCore.scala index bfc3cbf..39ef7dc 100644 --- a/src/main/scala/tile/VortexCore.scala +++ b/src/main/scala/radiance/tile/VortexCore.scala @@ -1,7 +1,7 @@ // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. -package rocket +package radiance.tile import chisel3._ import chisel3.util._ diff --git a/src/main/scala/tile/VortexTile.scala b/src/main/scala/radiance/tile/VortexTile.scala similarity index 99% rename from src/main/scala/tile/VortexTile.scala rename to src/main/scala/radiance/tile/VortexTile.scala index 174b6fe..ec1f321 100644 --- a/src/main/scala/tile/VortexTile.scala +++ b/src/main/scala/radiance/tile/VortexTile.scala @@ -1,7 +1,7 @@ // See LICENSE.SiFive for license details. // See LICENSE.Berkeley for license details. -package freechips.rocketchip.tile +package radiance.tile import chisel3._ import chisel3.util._ @@ -16,7 +16,7 @@ import freechips.rocketchip.util._ import freechips.rocketchip.prci.ClockSinkParameters import freechips.rocketchip.regmapper.RegField import freechips.rocketchip.tile._ -import rocket.{Vortex, VortexBundleA, VortexBundleD} +import radiance.memory._ case class VortexTileParams( core: VortexCoreParams = VortexCoreParams(),