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Pretty-print CoalescingUnit configs at elaboration time

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This commit is contained in:
Hansung Kim
2023-07-22 16:18:02 -07:00
parent a2bddfe8a8
commit f8a1a28c6c
2 changed files with 20 additions and 13 deletions
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31
src/main/scala/tilelink/Coalescing.scala
View File

@@ -59,9 +59,10 @@ case class CoalescerConfig(
queueDepth: Int, // request window per lane
waitTimeout: Int, // max cycles to wait before forced fifo dequeue, per lane
addressWidth: Int, // assume <= 32
dataBusWidth: Int, // memory-side downstream TileLink data bus size
// this has to be at least larger than word size for
// the coalescer to perform well
dataBusWidth: Int, // memory-side downstream TileLink data bus size.
// This data bus carries the data bits of coalesced request/responses,
// and so it has to be at least wider than word size for the coalescer
// to perform well
coalLogSizes: Seq[Int], // list of coalescer sizes to try in the MonoCoalescers
// each size is log(byteSize)
// max value should match dataBusWidth as the largest-possible
@@ -82,8 +83,8 @@ case class CoalescerConfig(
require(coalLogSizes.max <= dataBusWidth,
"multi-beat coalesced reads/writes are currently not supported")
if (coalLogSizes.max < dataBusWidth) {
println("======== Warning: coalescer is coalescing to size " +
s"${coalLogSizes.max} which is narrower than data bus width " +
println("======== Warning: coalescer's max coalescing size is set to " +
s"${coalLogSizes.max}, which is narrower than data bus width " +
s"${dataBusWidth}. This might indicate misconfiguration.")
}
coalLogSizes.max
@@ -759,8 +760,15 @@ class CoalescerSourceGen(
class CoalescingUnitImp(outer: CoalescingUnit, config: CoalescerConfig)
extends LazyModuleImp(outer) {
println(s"========== CoalescingUnit: aggregateNode out width: " +
s"${outer.aggregateNode.out.head._1.params.dataBits}")
println(s"CoalescingUnit instantiated with config: {")
println(s" enable: ${config.enable}")
println(s" numLanes: ${config.numLanes}")
println(s" coalLogSizes: ${config.coalLogSizes}")
println(s" numOldSrcIds: ${config.numOldSrcIds}")
println(s" numNewSrcIds: ${config.numNewSrcIds}")
println(s" reqQueueDepth: ${config.queueDepth}")
println(s" respQueueDepth: ${config.respQueueDepth}")
println(s"}")
require(
outer.cpuNode.in.length == config.numLanes,
@@ -1127,9 +1135,11 @@ class InFlightTable(
val entries = config.numNewSrcIds
val sourceWidth = log2Ceil(config.numOldSrcIds)
println(s"=========== table sourceWidth: ${sourceWidth}")
println(s"=========== table offsetBits: ${offsetBits}")
println(s"=========== table sizeEnumBits: ${entryT.sizeEnumT.getWidth}")
println(s"CoalescingUnit InFlightTable config: {")
println(s" sourceWidth: ${sourceWidth}")
println(s" offsetBits: ${offsetBits}")
println(s" sizeEnumBits: ${entryT.sizeEnumT.getWidth}")
println(s"}")
val io = IO(new Bundle {
// Enqueue IO
@@ -1928,7 +1938,6 @@ class DummyDriverImp(outer: DummyDriver, config: CoalescerConfig)
// Should not instantiate any memtrace modules.
class DummyCoalescer(implicit p: Parameters) extends LazyModule {
val numLanes = p(SIMTCoreKey).get.nLanes
println(s"============ numLanes: ${numLanes}")
val config = defaultConfig.copy(numLanes = numLanes)
val driver = LazyModule(new DummyDriver(config))

2
src/main/scala/tilelink/TracerSystemMem.scala
View File

@@ -37,8 +37,6 @@ trait CanHaveMemtraceCore { this: BaseSubsystem =>
val coalescerNode = p(CoalescerKey) match {
case Some(coalParam) => {
val coal = LazyModule(new CoalescingUnit(coalParam))
println(s"============ CoalescingUnit instantiated [numLanes=${coalParam.numLanes}]")
println(s"============ numOldSrcId and numNewSrc are (${coalParam.numOldSrcIds},${coalParam.numNewSrcIds})")
coal.cpuNode :=* coreSideLogger.node :=* tracer.node // N lanes
memSideLogger.node :=* coal.aggregateNode // N+1 lanes
memSideLogger.node