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Create separate config for memtrace core

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This commit is contained in:
Hansung Kim
2023-05-09 13:07:38 -07:00
parent 7bd9fd43f8
commit f52492c56b
2 changed files with 14 additions and 8 deletions
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4
src/main/scala/tilelink/Coalescing.scala
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@@ -12,9 +12,11 @@ import freechips.rocketchip.util.MultiPortQueue
import freechips.rocketchip.unittest._ import freechips.rocketchip.unittest._
// TODO: find better place for these // TODO: find better place for these
case class SIMTCoreParams(nLanes: Int = 4, tracefilename: String = "undefined") case class SIMTCoreParams(nLanes: Int = 4)
case class MemtraceCoreParams(tracefilename: String = "undefined")
case object SIMTCoreKey extends Field[Option[SIMTCoreParams]](None /*default*/) case object SIMTCoreKey extends Field[Option[SIMTCoreParams]](None /*default*/)
case object MemtraceCoreKey extends Field[Option[MemtraceCoreParams]](None /*default*/)
trait InFlightTableSizeEnum extends ChiselEnum { trait InFlightTableSizeEnum extends ChiselEnum {
val INVALID: Type val INVALID: Type

18
src/main/scala/tilelink/TracerSystemMem.scala
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@@ -6,20 +6,24 @@ import org.chipsalliance.cde.config.{Parameters, Config}
// The trait is attached to DigitalTop of Chipyard system, informing it indeed // The trait is attached to DigitalTop of Chipyard system, informing it indeed
// has the ability to attach GPU tracer node onto the system bus // has the ability to attach GPU tracer node onto the system bus
trait CanHaveGPUTracer { this: BaseSubsystem => trait CanHaveMemtraceCore { this: BaseSubsystem =>
implicit val p: Parameters implicit val p: Parameters
p(SIMTCoreKey).map { _ => p(MemtraceCoreKey).map { param =>
val config = p(SIMTCoreKey).get val tracer = LazyModule(new MemTraceDriver(defaultConfig, param.tracefilename)(p))
val tracer = LazyModule(new MemTraceDriver(defaultConfig, config.tracefilename)(p))
// Must use :=* to ensure the N edges from Tracer doesn't get merged into 1 // Must use :=* to ensure the N edges from Tracer doesn't get merged into 1
// when connecting to SBus // when connecting to SBus
println(s"============ MemTraceDriver instantiated [filename=${param.tracefilename}]")
sbus.fromPort(Some("gpu-tracer"))() :=* tracer.node sbus.fromPort(Some("gpu-tracer"))() :=* tracer.node
} }
} }
//This is used by Chip Level Config, the config which creates the SoC //This is used by Chip Level Config, the config which creates the SoC
class WithGPUTracer(numLanes: Int, tracefilename: String) class WithMemtraceCore(tracefilename: String)
extends Config((_, _, _) => { case SIMTCoreKey => extends Config((site, _, _) => { case MemtraceCoreKey =>
Some(SIMTCoreParams(numLanes, tracefilename)) require(
site(SIMTCoreKey).isDefined,
"Memtrace core requires a SIMT configuration. Use WithNLanes to enable SIMT."
)
Some(MemtraceCoreParams(tracefilename))
}) })