wu-arch/radiance
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Create separate config for memtrace core

Browse Source
This commit is contained in:
Hansung Kim
2023-05-09 13:07:38 -07:00
parent 7bd9fd43f8
commit f52492c56b
2 changed files with 14 additions and 8 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
src/main/scala/tilelink/Coalescing.scala
View File

@@ -12,9 +12,11 @@ import freechips.rocketchip.util.MultiPortQueue
import freechips.rocketchip.unittest._
// TODO: find better place for these
case class SIMTCoreParams(nLanes: Int = 4, tracefilename: String = "undefined")
case class SIMTCoreParams(nLanes: Int = 4)
case class MemtraceCoreParams(tracefilename: String = "undefined")
case object SIMTCoreKey extends Field[Option[SIMTCoreParams]](None /*default*/)
case object MemtraceCoreKey extends Field[Option[MemtraceCoreParams]](None /*default*/)
trait InFlightTableSizeEnum extends ChiselEnum {
val INVALID: Type