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Better logic for {imem,dmem}TagWidth

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This commit is contained in:
Hansung Kim
2023-12-10 05:58:00 -08:00
parent 2879108804
commit efac9b7d0b
1 changed files with 6 additions and 4 deletions
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10
src/main/scala/rocket/VortexCore.scala
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@@ -41,10 +41,12 @@ class VortexBundle(tile: VortexTile)(implicit p: Parameters) extends CoreBundle
val interrupts = Input(new CoreInterrupts()) val interrupts = Input(new CoreInterrupts())
// TODO: parametrize // TODO: parametrize
val NW_WIDTH = 1 val numWarps = 4
val uuidWidth = 44 val NW_WIDTH = (if (numWarps == 1) 1 else log2Ceil(numWarps))
val imemTagWidth = uuidWidth + NW_WIDTH val UUID_WIDTH = 44
val dmemTagWidth = 46 // FIXME: hardcoded; see gpu_pkg.sv val imemTagWidth = UUID_WIDTH + NW_WIDTH
val LSUQ_TAG_BITS = 4
val dmemTagWidth = UUID_WIDTH + LSUQ_TAG_BITS
// conditionally instantiate ports depending on whether we want to use VX_cache or not // conditionally instantiate ports depending on whether we want to use VX_cache or not
val imem = if (!tile.vortexParams.useVxCache) Some(Vec(1, new Bundle { val imem = if (!tile.vortexParams.useVxCache) Some(Vec(1, new Bundle {