From ee79fdaa05cafe09bbdb4c0911c6dead7ea6fc09 Mon Sep 17 00:00:00 2001 From: Hansung Kim Date: Wed, 31 Jul 2024 17:17:03 -0700 Subject: [PATCH] Fix typetag for half --- src/main/scala/radiance/core/TensorDPU.scala | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/src/main/scala/radiance/core/TensorDPU.scala b/src/main/scala/radiance/core/TensorDPU.scala index 8ba13ef..90ac883 100644 --- a/src/main/scala/radiance/core/TensorDPU.scala +++ b/src/main/scala/radiance/core/TensorDPU.scala @@ -32,9 +32,10 @@ class TensorDotProductUnit(val half: Boolean) extends Module with tile.HasFPUPar // [IEEE] -> recode() -> unbox() -> [Hardfloat] -> box() -> ieee() -> [IEEE] // make sure recoding/uncoding happens only at the edge, not at every // pipeline stage inside the dpu - val in1 = io.in.bits.a.map(x => unbox(recode(x, S), S, Some(t))) - val in2 = io.in.bits.b.map(x => unbox(recode(x, S), S, Some(t))) - val in3 = unbox(recode(io.in.bits.c, S), S, Some(t)) + val tag = if (half) H else S + val in1 = io.in.bits.a.map(x => unbox(recode(x, tag), tag, Some(t))) + val in2 = io.in.bits.b.map(x => unbox(recode(x, tag), tag, Some(t))) + val in3 = unbox(recode(io.in.bits.c, tag), tag, Some(t)) val dpu = Module(new DotProductPipe(dotProductDim, t.exp, t.sig)) dpu.io.in.valid := io.in.valid @@ -44,7 +45,7 @@ class TensorDotProductUnit(val half: Boolean) extends Module with tile.HasFPUPar dpu.io.stall := io.stall io.out.valid := dpu.io.out.valid - io.out.bits.data := ieee(box(dpu.io.out.bits.data, S)) + io.out.bits.data := ieee(box(dpu.io.out.bits.data, tag)) } // Copied from chisel3.util.Pipe.