Fix not respecting invalidate.valid from coalescer
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@@ -581,6 +581,9 @@ class CoalescingUnitImp(outer: CoalescingUnit, config: CoalescerConfig) extends
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// requests that didn't get coalesced, and M is the maximum number of
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// requests that didn't get coalesced, and M is the maximum number of
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// single-lane requests that can go into a coalesced request.
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// single-lane requests that can go into a coalesced request.
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// (`numPerLaneReqs`).
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// (`numPerLaneReqs`).
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// TODO: potentially expensive, because this generates more FFs.
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// Rather than enqueueing all responses in a single cycle, consider
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// enqueueing one by one (at the cost of possibly stalling downstream).
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1 + numPerLaneReqs,
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1 + numPerLaneReqs,
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// deq_lanes = 1 because we're serializing all responses to 1 port that
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// deq_lanes = 1 because we're serializing all responses to 1 port that
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// goes back to the core.
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// goes back to the core.
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@@ -597,7 +600,7 @@ class CoalescingUnitImp(outer: CoalescingUnit, config: CoalescerConfig) extends
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)
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)
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}
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}
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val respQueueNoncoalPort = 0
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val respQueueNoncoalPort = 0
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val respQueueCoalPortOffset = 1
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val respQueueUncoalPortOffset = 1
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(outer.node.in zip outer.node.out).zipWithIndex.foreach {
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(outer.node.in zip outer.node.out).zipWithIndex.foreach {
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case (((tlIn, edgeIn), (tlOut, _)), 0) => // TODO: not necessarily 1 master edge
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case (((tlIn, edgeIn), (tlOut, _)), 0) => // TODO: not necessarily 1 master edge
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@@ -716,9 +719,8 @@ class CoalescingUnitImp(outer: CoalescingUnit, config: CoalescerConfig) extends
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(newEntry.lanes zip coalescer.io.invalidate.bits).zipWithIndex
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(newEntry.lanes zip coalescer.io.invalidate.bits).zipWithIndex
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.foreach { case ((laneEntry, laneInv), lane) =>
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.foreach { case ((laneEntry, laneInv), lane) =>
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(laneEntry.reqs zip laneInv.asBools).foreach { case (reqEntry, inv) =>
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(laneEntry.reqs zip laneInv.asBools).foreach { case (reqEntry, inv) =>
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// TODO: this part needs the actual coalescing logic to work
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reqEntry.valid := (coalescer.io.invalidate.valid && inv)
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reqEntry.valid := inv
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when ((coalescer.io.invalidate.valid && inv)) {
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when (inv) {
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printf(s"entry for reqQueue(${lane}) got invalidated\n")
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printf(s"entry for reqQueue(${lane}) got invalidated\n")
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}
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}
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// FIXME: copying over queue heads out of laziness
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// FIXME: copying over queue heads out of laziness
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@@ -730,7 +732,7 @@ class CoalescingUnitImp(outer: CoalescingUnit, config: CoalescerConfig) extends
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dontTouch(newEntry)
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dontTouch(newEntry)
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// Uncoalescer module uncoalesces responses back to each lane
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// Uncoalescer module uncoalesces responses back to each lane
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val uncoalescer = Module(new UncoalescingUnit(config))
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val uncoalescer = Module(new Uncoalescer(config))
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uncoalescer.io.coalReqValid := coalescer.io.coalReq.valid
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uncoalescer.io.coalReqValid := coalescer.io.coalReq.valid
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uncoalescer.io.newEntry := newEntry
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uncoalescer.io.newEntry := newEntry
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@@ -746,11 +748,14 @@ class CoalescingUnitImp(outer: CoalescingUnit, config: CoalescerConfig) extends
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// TODO: rather than crashing, deassert tlOut.d.ready to stall downtream
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// TODO: rather than crashing, deassert tlOut.d.ready to stall downtream
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// cache. This should ideally not happen though.
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// cache. This should ideally not happen though.
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assert(
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assert(
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q.io.enq(respQueueCoalPortOffset + i).ready,
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q.io.enq(respQueueUncoalPortOffset + i).ready,
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s"respQueue: enq port for coalesced response is blocked for lane ${lane}"
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s"respQueue: enq port for ${i}-th uncoalesced response is blocked for lane ${lane}"
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)
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)
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q.io.enq(respQueueCoalPortOffset + i).valid := resp.valid
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q.io.enq(respQueueUncoalPortOffset + i).valid := resp.valid
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q.io.enq(respQueueCoalPortOffset + i).bits := resp.bits
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q.io.enq(respQueueUncoalPortOffset + i).bits := resp.bits
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when (resp.valid) {
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printf(s"${i}-th uncoalesced response came back from lane ${lane}\n")
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}
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// dontTouch(q.io.enq(respQueueCoalPortOffset))
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// dontTouch(q.io.enq(respQueueCoalPortOffset))
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}
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}
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}
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}
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@@ -776,7 +781,7 @@ class CoalescedResponseBundle(config: CoalescerConfig) extends Bundle {
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val data = UInt((8 * (1 << config.maxCoalLogSize)).W)
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val data = UInt((8 * (1 << config.maxCoalLogSize)).W)
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}
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}
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class UncoalescingUnit(config: CoalescerConfig) extends Module {
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class Uncoalescer(config: CoalescerConfig) extends Module {
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// notes to hansung:
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// notes to hansung:
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// val numLanes: Int, <-> config.NUM_LANES
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// val numLanes: Int, <-> config.NUM_LANES
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// val numPerLaneReqs: Int, <-> config.DEPTH
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// val numPerLaneReqs: Int, <-> config.DEPTH
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@@ -440,7 +440,7 @@ class CoalShiftQueueTest extends AnyFlatSpec with ChiselScalatestTester {
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}
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}
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}
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}
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class UncoalescingUnitTest extends AnyFlatSpec with ChiselScalatestTester {
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class UncoalescerUnitTest extends AnyFlatSpec with ChiselScalatestTester {
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behavior of "uncoalescer"
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behavior of "uncoalescer"
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val numLanes = 4
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val numLanes = 4
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val numPerLaneReqs = 2
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val numPerLaneReqs = 2
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@@ -451,7 +451,7 @@ class UncoalescingUnitTest extends AnyFlatSpec with ChiselScalatestTester {
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val numInflightCoalRequests = 4
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val numInflightCoalRequests = 4
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it should "work" in {
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it should "work" in {
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test(new UncoalescingUnit(testConfig))
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test(new Uncoalescer(testConfig))
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// vcs helps with simulation time, but sometimes errors with
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// vcs helps with simulation time, but sometimes errors with
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// "mutation occurred during iteration" java error
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// "mutation occurred during iteration" java error
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// .withAnnotations(Seq(VcsBackendAnnotation))
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// .withAnnotations(Seq(VcsBackendAnnotation))
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