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Decouple Vortex dmem bundle from TL

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Previously VortexBundle was being instantiated using the parameters of
the TileLink bundle from VortexTile.  This results in tight coupling
between Vortex interface parameters and downstream TileLink parameters.
This change adds a standalone Bundle used by the VortexCore wrapper
and is independently instantiated from the TL params, i.e. different
source widths.  Ideally we want to move away from using TL-like
structures for VortexBundle and handling adapter logic completely
outside the core blackbox.
This commit is contained in:
Hansung Kim
2023-10-16 17:42:17 -07:00
parent db8625fb20
commit eb9772b750
2 changed files with 60 additions and 21 deletions
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8
src/main/scala/rocket/VortexCore.scala
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@@ -8,7 +8,7 @@ import chisel3.util._
import chisel3.experimental._
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.tile._
import tile.VortexTile
import tile.{VortexTile, VortexBundleA, VortexBundleD}
class VortexBundle(tile: VortexTile)(implicit p: Parameters) extends CoreBundle {
val clock = Input(Clock())
@@ -22,9 +22,9 @@ class VortexBundle(tile: VortexTile)(implicit p: Parameters) extends CoreBundle
val a = tile.imemNodes.head.out.head._1.a.cloneType
val d = Flipped(tile.imemNodes.head.out.head._1.d.cloneType)
})) else None
val dmem = if (!tile.vortexParams.useVxCache) Some(Vec(4, new Bundle {
val a = tile.dmemNodes.head.out.head._1.a.cloneType
val d = Flipped(tile.dmemNodes.head.out.head._1.d.cloneType)
val dmem = if (!tile.vortexParams.useVxCache) Some(Vec(tile.numLanes, new Bundle {
val a = Decoupled(new VortexBundleA())
val d = Flipped(Decoupled(new VortexBundleD()))
})) else None
val mem = if (tile.vortexParams.useVxCache) Some(new Bundle {
val a = tile.memNode.out.head._1.a.cloneType