Decouple Vortex dmem bundle from TL
Previously VortexBundle was being instantiated using the parameters of the TileLink bundle from VortexTile. This results in tight coupling between Vortex interface parameters and downstream TileLink parameters. This change adds a standalone Bundle used by the VortexCore wrapper and is independently instantiated from the TL params, i.e. different source widths. Ideally we want to move away from using TL-like structures for VortexBundle and handling adapter logic completely outside the core blackbox.
This commit is contained in:
Hansung Kim
@@ -8,7 +8,7 @@ import chisel3.util._
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import chisel3.experimental._
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import org.chipsalliance.cde.config.Parameters
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import freechips.rocketchip.tile._
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import tile.VortexTile
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import tile.{VortexTile, VortexBundleA, VortexBundleD}
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class VortexBundle(tile: VortexTile)(implicit p: Parameters) extends CoreBundle {
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val clock = Input(Clock())
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@@ -22,9 +22,9 @@ class VortexBundle(tile: VortexTile)(implicit p: Parameters) extends CoreBundle
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val a = tile.imemNodes.head.out.head._1.a.cloneType
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val d = Flipped(tile.imemNodes.head.out.head._1.d.cloneType)
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})) else None
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val dmem = if (!tile.vortexParams.useVxCache) Some(Vec(4, new Bundle {
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val a = tile.dmemNodes.head.out.head._1.a.cloneType
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val d = Flipped(tile.dmemNodes.head.out.head._1.d.cloneType)
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val dmem = if (!tile.vortexParams.useVxCache) Some(Vec(tile.numLanes, new Bundle {
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val a = Decoupled(new VortexBundleA())
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val d = Flipped(Decoupled(new VortexBundleD()))
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})) else None
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val mem = if (tile.vortexParams.useVxCache) Some(new Bundle {
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val a = tile.memNode.out.head._1.a.cloneType
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@@ -44,6 +44,22 @@ case class VortexTileParams(
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}
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}
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class VortexBundleA extends Bundle {
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val opcode = UInt(3.W) // FIXME: hardcoded
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val size = UInt(4.W) // FIXME: hardcoded
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val source = UInt(10.W) // FIXME: hardcoded
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val address = UInt(32.W) // FIXME: hardcoded
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val mask = UInt(4.W) // FIXME: hardcoded
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val data = UInt(32.W) // FIXME: hardcoded
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}
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class VortexBundleD extends Bundle {
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val opcode = UInt(3.W) // FIXME: hardcoded
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val size = UInt(4.W) // FIXME: hardcoded
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val source = UInt(10.W) // FIXME: hardcoded
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val data = UInt(32.W) // FIXME: hardcoded
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}
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class VortexTile private (
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val vortexParams: VortexTileParams,
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crossing: ClockCrossingType,
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@@ -91,6 +107,7 @@ class VortexTile private (
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minLatency = 1)))*/
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val numLanes = 4 // FIXME: hardcoded
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val sourceWidth = 1 // TODO: use Parameters for this
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val imemNodes = Seq.tabulate(1) { i =>
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TLClientNode(
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@@ -98,7 +115,7 @@ class VortexTile private (
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TLMasterPortParameters.v1(
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clients = Seq(
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TLMasterParameters.v1(
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sourceId = IdRange(0, 1 << 10), // TODO magic number
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sourceId = IdRange(0, 1 << 10), // TODO: magic numbers
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name = s"Vortex Core ${vortexParams.hartId} I-Mem $i",
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requestFifo = true,
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supportsProbe =
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@@ -117,7 +134,7 @@ class VortexTile private (
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TLMasterPortParameters.v1(
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clients = Seq(
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TLMasterParameters.v1(
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sourceId = IdRange(0, 1 << 10), // TODO magic number
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sourceId = IdRange(0, 1 << sourceWidth),
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name = s"Vortex Core ${vortexParams.hartId} D-Mem Lane $i",
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requestFifo = true,
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supportsProbe =
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@@ -316,10 +333,12 @@ class VortexTileModuleImp(outer: VortexTile) extends BaseTileModuleImp(outer) {
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// connection: VortexBundle <--> sourceGen <--> dmemNodes
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val sourceGens = Seq.tabulate(outer.numLanes) { _ =>
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Module(new VortexSourceGen(
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2, // FIXME: hardcoded
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dmemTLBundles.head.a.bits,
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dmemTLBundles.head.d.bits,
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Module(new VortexTLAdapter(
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outer.sourceWidth,
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new VortexBundleA(),
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new VortexBundleD(),
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chiselTypeOf(dmemTLBundles.head.a.bits),
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chiselTypeOf(dmemTLBundles.head.d.bits),
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))
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}
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(core.io.dmem.get zip sourceGens) foreach { case (coreMem, sourceGen) =>
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@@ -360,21 +379,24 @@ class VortexTileModuleImp(outer: VortexTile) extends BaseTileModuleImp(outer) {
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// sourceWidth; this needs to be more flexible.
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//
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// Some @copypaste from CoalescerSourceGen.
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class VortexSourceGen(
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class VortexTLAdapter(
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newSourceWidth: Int,
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reqT: TLBundleA,
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respT: TLBundleD
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inReqT: VortexBundleA,
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inRespT: VortexBundleD,
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outReqT: TLBundleA,
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outRespT: TLBundleD
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) extends Module {
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val io = IO(new Bundle {
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// in/out means upstream/downstream
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val inReq = Flipped(Decoupled(reqT.cloneType))
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val outReq = Decoupled(reqT.cloneType)
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val inResp = Decoupled(respT.cloneType)
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val outResp = Flipped(Decoupled(respT.cloneType))
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// TODO: change inReq/inResp to VortexBundle
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val inReq = Flipped(Decoupled(inReqT))
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val outReq = Decoupled(outReqT)
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val inResp = Decoupled(inRespT)
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val outResp = Flipped(Decoupled(outRespT))
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})
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val sourceGen = Module(new SourceGenerator(
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newSourceWidth,
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Some(chiselTypeOf(reqT.source)),
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Some(inReqT.source),
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ignoreInUse = false
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))
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sourceGen.io.gen := io.outReq.fire // use up a source ID only when request is created
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@@ -382,15 +404,32 @@ class VortexSourceGen(
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sourceGen.io.reclaim.bits := io.outResp.bits.source
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sourceGen.io.meta := io.inReq.bits.source
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// passthrough logic
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io.outReq <> io.inReq
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// io passthrough logic
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// TLBundleA <> VortexBundleA
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io.outReq.valid := io.inReq.valid
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io.outReq.bits.opcode := io.inReq.bits.opcode
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io.outReq.bits.param := 0.U
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io.outReq.bits.size := io.inReq.bits.size
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io.outReq.bits.source := io.inReq.bits.source
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io.outReq.bits.address := io.inReq.bits.address
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io.outReq.bits.mask := io.inReq.bits.mask
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io.outReq.bits.data := io.inReq.bits.data
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io.outReq.bits.corrupt := 0.U
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io.inReq.ready := io.outReq.ready
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// VortexBundleD <> TLBundleD
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io.inResp.valid := io.outResp.valid
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io.inResp.bits.opcode := io.outResp.bits.opcode
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io.inResp.bits.size := io.outResp.bits.size
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io.inResp.bits.source := io.outResp.bits.source
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io.inResp.bits.data := io.outResp.bits.data
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io.outResp.ready := io.inResp.ready
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// "man-in-the-middle"
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io.inReq.ready := io.outReq.ready && sourceGen.io.id.valid
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io.outReq.valid := io.inReq.valid && sourceGen.io.id.valid
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// FIXME: Fill is a hack; just change downstream to the right sourceWidth
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// io.outReq.bits.source := Fill(newSourceWidth, sourceGen.io.id.bits)
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io.outReq.bits.source := sourceGen.io.id.bits
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io.inResp <> io.outResp
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// translate upstream response back to its old sourceId
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io.inResp.bits.source := sourceGen.io.peek
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}
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