From e946403d7863abaec61b4baa92da467617d3fe66 Mon Sep 17 00:00:00 2001 From: Hansung Kim Date: Fri, 18 Oct 2024 22:54:48 -0700 Subject: [PATCH] tensor: Fix typo, reduce resp queue depth --- src/main/scala/radiance/core/TensorCoreDecoupled.scala | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/main/scala/radiance/core/TensorCoreDecoupled.scala b/src/main/scala/radiance/core/TensorCoreDecoupled.scala index ed241b5..b899ce9 100644 --- a/src/main/scala/radiance/core/TensorCoreDecoupled.scala +++ b/src/main/scala/radiance/core/TensorCoreDecoupled.scala @@ -225,7 +225,7 @@ class TensorCoreDecoupled( when (lastReqA && io.reqA.fire) { doneReqA := true.B } when (lastReqB && io.reqB.fire) { doneReqB := true.B } val genReqA = (state === AccessorState.access) && !doneReqA - val genReqB = (state === AccessorState.access) && !doneReqA + val genReqB = (state === AccessorState.access) && !doneReqB when (state === AccessorState.finish) { doneReqA := false.B doneReqB := false.B @@ -272,7 +272,7 @@ class TensorCoreDecoupled( // // Backend of the decoupled access/execute pipeline. // - val respQueueDepth = 8 // FIXME: parameterize + val respQueueDepth = 2 // FIXME: parameterize val respQueueA = Queue(respATagged, respQueueDepth) val respQueueB = Queue(respBTagged, respQueueDepth)