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Rename #define constants in SimMemTrace

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... to prevent collision with constants of the same name in other
verilog sources.
This commit is contained in:
Hansung Kim
2023-10-01 20:58:49 -07:00
parent 5bf068306f
commit e7a008ec74
1 changed files with 12 additions and 12 deletions
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24
src/main/resources/vsrc/SimMemTrace.v
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@@ -1,7 +1,7 @@
// FIXME hardcoded // FIXME hardcoded
`define DATA_WIDTH 64 `define MEMTRACE_DATA_WIDTH 64
`define MAX_NUM_LANES 32 `define MAX_NUM_LANES 32
`define LOGSIZE_WIDTH 8 `define MEMTRACE_LOGSIZE_WIDTH 8
import "DPI-C" function void memtrace_init( import "DPI-C" function void memtrace_init(
input string filename, input string filename,
@@ -36,16 +36,16 @@ module SimMemTrace #(parameter FILENAME = "undefined",
// These have to match the IO port name of the Chisel wrapper module. // These have to match the IO port name of the Chisel wrapper module.
input trace_read_ready, input trace_read_ready,
output [NUM_LANES-1:0] trace_read_valid, output [NUM_LANES-1:0] trace_read_valid,
output [`DATA_WIDTH*NUM_LANES-1:0] trace_read_address, output [`MEMTRACE_DATA_WIDTH*NUM_LANES-1:0] trace_read_address,
output [NUM_LANES-1:0] trace_read_is_store, output [NUM_LANES-1:0] trace_read_is_store,
output [`LOGSIZE_WIDTH*NUM_LANES-1:0] trace_read_size, output [`MEMTRACE_LOGSIZE_WIDTH*NUM_LANES-1:0] trace_read_size,
output [`DATA_WIDTH*NUM_LANES-1:0] trace_read_data, output [`MEMTRACE_DATA_WIDTH*NUM_LANES-1:0] trace_read_data,
output trace_read_finished output trace_read_finished
); );
bit __in_valid [NUM_LANES-1:0]; bit __in_valid [NUM_LANES-1:0];
longint __in_address [NUM_LANES-1:0]; longint __in_address [NUM_LANES-1:0];
bit __in_is_store [NUM_LANES-1:0]; bit __in_is_store [NUM_LANES-1:0];
reg [`LOGSIZE_WIDTH-1:0] __in_size [NUM_LANES-1:0]; reg [`MEMTRACE_LOGSIZE_WIDTH-1:0] __in_size [NUM_LANES-1:0];
longint __in_data [NUM_LANES-1:0]; longint __in_data [NUM_LANES-1:0];
bit __in_finished; bit __in_finished;
@@ -53,11 +53,11 @@ module SimMemTrace #(parameter FILENAME = "undefined",
generate generate
for (g = 0; g < NUM_LANES; g = g + 1) begin for (g = 0; g < NUM_LANES; g = g + 1) begin
assign trace_read_valid[g] = __in_valid[g]; assign trace_read_valid[g] = __in_valid[g];
assign trace_read_address[`DATA_WIDTH*(g+1)-1:`DATA_WIDTH*g] = __in_address[g]; assign trace_read_address[`MEMTRACE_DATA_WIDTH*(g+1)-1:`MEMTRACE_DATA_WIDTH*g] = __in_address[g];
assign trace_read_is_store[g] = __in_is_store[g]; assign trace_read_is_store[g] = __in_is_store[g];
assign trace_read_size[`LOGSIZE_WIDTH*(g+1)-1:`LOGSIZE_WIDTH*g] = __in_size[g]; assign trace_read_size[`MEMTRACE_LOGSIZE_WIDTH*(g+1)-1:`MEMTRACE_LOGSIZE_WIDTH*g] = __in_size[g];
assign trace_read_data[`DATA_WIDTH*(g+1)-1:`DATA_WIDTH*g] = __in_data[g]; assign trace_read_data[`MEMTRACE_DATA_WIDTH*(g+1)-1:`MEMTRACE_DATA_WIDTH*g] = __in_data[g];
end end
endgenerate endgenerate
assign trace_read_finished = __in_finished; assign trace_read_finished = __in_finished;
@@ -71,11 +71,11 @@ module SimMemTrace #(parameter FILENAME = "undefined",
if (reset) begin if (reset) begin
for (integer tid = 0; tid < NUM_LANES; tid = tid + 1) begin for (integer tid = 0; tid < NUM_LANES; tid = tid + 1) begin
__in_valid[tid] = 1'b0; __in_valid[tid] = 1'b0;
__in_address[tid] = `DATA_WIDTH'b0; __in_address[tid] = `MEMTRACE_DATA_WIDTH'b0;
__in_is_store[tid] = 1'b0; __in_is_store[tid] = 1'b0;
__in_size[tid] = `LOGSIZE_WIDTH'b0; __in_size[tid] = `MEMTRACE_LOGSIZE_WIDTH'b0;
__in_data[tid] = `DATA_WIDTH'b0; __in_data[tid] = `MEMTRACE_DATA_WIDTH'b0;
end end
__in_finished = 1'b0; __in_finished = 1'b0;
end else begin end else begin