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Write basic DPI mem fuzzer

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This commit is contained in:
Hansung Kim
2024-01-20 21:46:14 -08:00
parent 6ff127eb51
commit e183606193
4 changed files with 139 additions and 132 deletions
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9
src/main/resources/csrc/SimMemFuzzer.c
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@@ -1,9 +0,0 @@
#ifndef NO_VPI
#include <vpi_user.h>
#include <svdpi.h>
#endif
#include <stdio.h>
void memfuzz_init(void) {
printf("Hello from C!\n");
}

21
src/main/resources/csrc/SimMemFuzzer.cc Normal file
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@@ -0,0 +1,21 @@
#ifndef NO_VPI
#include <vpi_user.h>
#include <svdpi.h>
#endif
#include <stdio.h>
#include <stdint.h>
extern "C" void memfuzz_generate_rs(uint8_t *vec_a_ready, uint8_t *vec_a_valid,
long long *vec_a_address,
uint8_t *vec_d_ready, uint8_t *finished);
extern "C" void memfuzz_init(int num_lanes) {
printf("from C: num_lanes=%d\n", num_lanes);
}
extern "C" void memfuzz_generate(uint8_t *vec_a_ready, uint8_t *vec_a_valid,
long long *vec_a_address, uint8_t *vec_d_ready,
uint8_t *finished) {
memfuzz_generate_rs(vec_a_ready, vec_a_valid, vec_a_address, vec_d_ready,
finished);
}

153
src/main/resources/vsrc/SimMemFuzzer.v
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@@ -1,103 +1,92 @@
// FIXME hardcoded
`define MEMTRACE_DATA_WIDTH 64
`define MAX_NUM_LANES 32
`define MEMTRACE_LOGSIZE_WIDTH 8
`include "SimDefaults.vh"
import "DPI-C" function void memfuzz_init(
input longint num_lanes
);
// Make sure to sync the parameters for:
// (1) import "DPI-C" declaration
// (2) C function declaration
// (3) DPI function calls inside initial/always blocks
import "DPI-C" function void memtrace_query
import "DPI-C" function void memfuzz_generate
(
input bit trace_read_ready,
input longint trace_read_cycle,
input int trace_read_lane_id,
output bit trace_read_valid,
output longint trace_read_address,
output bit trace_read_is_store,
output byte trace_read_size,
output longint trace_read_data,
output bit trace_read_finished
input bit vec_a_ready[`MAX_NUM_LANES],
output bit vec_a_valid[`MAX_NUM_LANES],
output longint vec_a_address[`MAX_NUM_LANES],
output bit vec_d_ready[`MAX_NUM_LANES],
output bit finished
);
module SimMemFuzz #(parameter NUM_LANES = 4) (
module SimMemFuzzer #(parameter NUM_LANES = 4) (
input clock,
input reset
input reset,
// input trace_read_ready,
// output [NUM_LANES-1:0] trace_read_valid,
// output [`MEMTRACE_DATA_WIDTH*NUM_LANES-1:0] trace_read_address,
// output [NUM_LANES-1:0] trace_read_is_store,
// output [`MEMTRACE_LOGSIZE_WIDTH*NUM_LANES-1:0] trace_read_size,
// output [`MEMTRACE_DATA_WIDTH*NUM_LANES-1:0] trace_read_data,
// output trace_read_finished
input [NUM_LANES-1:0] a_ready,
output [NUM_LANES-1:0] a_valid,
output [`SIMMEM_DATA_WIDTH*NUM_LANES-1:0] a_address,
output [NUM_LANES-1:0] a_is_store,
output [`SIMMEM_LOGSIZE_WIDTH*NUM_LANES-1:0] a_size,
output [`SIMMEM_DATA_WIDTH*NUM_LANES-1:0] a_data,
output [NUM_LANES-1:0] d_ready,
output finished
);
// need to be in ascending order to match with C indexing
// C array sizes are static, so need to use MAX_NUM_LANES
bit __out_a_ready [0:`MAX_NUM_LANES-1];
bit __in_a_valid [0:`MAX_NUM_LANES-1];
longint __in_a_address [0:`MAX_NUM_LANES-1];
bit __in_a_is_store [0:`MAX_NUM_LANES-1];
reg [`SIMMEM_LOGSIZE_WIDTH-1:0] __in_a_size [0:`MAX_NUM_LANES-1];
longint __in_a_data [0:`MAX_NUM_LANES-1];
bit __in_d_ready [0:`MAX_NUM_LANES-1];
bit __in_finished;
genvar g;
generate
for (g = 0; g < NUM_LANES; g = g + 1) begin
assign __out_a_ready[g] = a_ready[g];
assign a_valid[g] = __in_a_valid[g];
assign a_address[`SIMMEM_DATA_WIDTH*g +: `SIMMEM_DATA_WIDTH] = __in_a_address[g];
assign a_is_store[g] = __in_a_is_store[g];
assign a_size[`SIMMEM_LOGSIZE_WIDTH*g +: `SIMMEM_LOGSIZE_WIDTH] = __in_a_size[g];
assign a_data[`SIMMEM_DATA_WIDTH*g +: `SIMMEM_DATA_WIDTH] = __in_a_data[g];
end
endgenerate
assign finished = __in_finished;
initial begin
memfuzz_init();
memfuzz_init(NUM_LANES);
end
// bit __in_valid [NUM_LANES-1:0];
// longint __in_address [NUM_LANES-1:0];
// bit __in_is_store [NUM_LANES-1:0];
// reg [`MEMTRACE_LOGSIZE_WIDTH-1:0] __in_size [NUM_LANES-1:0];
// longint __in_data [NUM_LANES-1:0];
// bit __in_finished;
always @(posedge clock) begin
if (reset) begin
for (integer tid = 0; tid < NUM_LANES; tid = tid + 1) begin
__in_a_valid[tid] = 1'b0;
__in_a_address[tid] = `SIMMEM_DATA_WIDTH'b0;
// genvar g;
// generate
// for (g = 0; g < NUM_LANES; g = g + 1) begin
// assign trace_read_valid[g] = __in_valid[g];
// assign trace_read_address[`MEMTRACE_DATA_WIDTH*(g+1)-1:`MEMTRACE_DATA_WIDTH*g] = __in_address[g];
__in_a_is_store[tid] = 1'b0;
__in_a_size[tid] = `SIMMEM_LOGSIZE_WIDTH'b0;
__in_a_data[tid] = `SIMMEM_DATA_WIDTH'b0;
__in_d_ready[tid] = 1'b0;
end
__in_finished = 1'b0;
end else begin
memfuzz_generate(
__out_a_ready,
__in_a_valid,
__in_a_address,
__in_d_ready,
__in_finished
);
for (integer tid = 0; tid < NUM_LANES; tid = tid + 1) begin
$display("verilog: %04d valid[%d]=%d, address[%d]=%d",
$time, tid, __in_a_valid[tid], tid, __in_a_address[tid]);
end
// assign trace_read_is_store[g] = __in_is_store[g];
// assign trace_read_size[`MEMTRACE_LOGSIZE_WIDTH*(g+1)-1:`MEMTRACE_LOGSIZE_WIDTH*g] = __in_size[g];
// assign trace_read_data[`MEMTRACE_DATA_WIDTH*(g+1)-1:`MEMTRACE_DATA_WIDTH*g] = __in_data[g];
// end
// endgenerate
// assign trace_read_finished = __in_finished;
// initial begin
// /* $value$plusargs("uartlog=%s", __uartlog); */
// memtrace_init(FILENAME, HAS_SOURCE);
// end
// always @(posedge clock) begin
// if (reset) begin
// for (integer tid = 0; tid < NUM_LANES; tid = tid + 1) begin
// __in_valid[tid] = 1'b0;
// __in_address[tid] = `MEMTRACE_DATA_WIDTH'b0;
//
// __in_is_store[tid] = 1'b0;
// __in_size[tid] = `MEMTRACE_LOGSIZE_WIDTH'b0;
// __in_data[tid] = `MEMTRACE_DATA_WIDTH'b0;
// end
// __in_finished = 1'b0;
// end else begin
// // We have to write to __in_ regs only when trace_read_ready, or
// // otherwise we might overwrite lines that were previously valid
// // but the downstream missed by being not ready.
// if (trace_read_ready) begin
// for (integer tid = 0; tid < NUM_LANES; tid = tid + 1) begin
// memtrace_query(
// trace_read_ready,
// trace_read_cycle,
// tid,
// __in_valid[tid],
// __in_address[tid],
// __in_is_store[tid],
// __in_size[tid],
// __in_data[tid],
// __in_finished
// );
// end
// end
// end
// end
if ($time >= 32'd200000) begin
$finish;
end
end
end
endmodule