From dfdd4f8342502b5b550bf4e149d001432bf0cf65 Mon Sep 17 00:00:00 2001
From: Hansung Kim <hansung_kim@berkeley.edu>
Date: Thu, 27 Apr 2023 20:36:04 -0700
Subject: [PATCH] Redundant call syntax

---
 src/main/scala/tilelink/Coalescing.scala | 26 ++++++++++++------------
 1 file changed, 13 insertions(+), 13 deletions(-)

diff --git a/src/main/scala/tilelink/Coalescing.scala b/src/main/scala/tilelink/Coalescing.scala
index 4eb530c..110cc04 100644
--- a/src/main/scala/tilelink/Coalescing.scala
+++ b/src/main/scala/tilelink/Coalescing.scala
@@ -54,7 +54,7 @@ case class CoalescerConfig(
   sizeEnum: InFlightTableSizeEnum,
 ) {
   // maximum coalesced size
-  def maxCoalLogSize(): Int = coalLogSizes.max
+  def maxCoalLogSize: Int = coalLogSizes.max
 }
 
 object defaultConfig extends CoalescerConfig(
@@ -255,7 +255,7 @@ class MonoCoalescer(coalLogSize: Int, windowT: CoalShiftQueue[ReqQueueEntry],
       // number of entries matched with this leader lane's head.
       // maximum is numLanes * queueDepth
       val matchCount = Output(UInt(log2Ceil(config.numLanes * config.queueDepth + 1).W))
-      val coverageHits = Output(UInt((1 << config.maxCoalLogSize()).W))
+      val coverageHits = Output(UInt((1 << config.maxCoalLogSize).W))
     })
   })
 
@@ -385,7 +385,7 @@ class MultiCoalescer(windowT: CoalShiftQueue[ReqQueueEntry], coalReqT: ReqQueueE
 
   def normalize(valPerSize: Seq[UInt]): Seq[UInt] = {
     (valPerSize zip config.coalLogSizes).map { case (hits, size) =>
-      (hits << (config.maxCoalLogSize() - size).U).asUInt
+      (hits << (config.maxCoalLogSize - size).U).asUInt
     }
   }
 
@@ -405,7 +405,7 @@ class MultiCoalescer(windowT: CoalShiftQueue[ReqQueueEntry], coalReqT: ReqQueueE
   val chosenSizeIdx = Wire(UInt(log2Ceil(config.coalLogSizes.size).W))
   val chosenValid = Wire(Bool())
   // minimum 25% coverage
-  val minCoverage = 1.max(1 << ((config.maxCoalLogSize() - 2) - 2))
+  val minCoverage = 1.max(1 << ((config.maxCoalLogSize - 2) - 2))
 
   when (normalizedHits.map(_ > minCoverage.U).reduce(_ || _)) {
     chosenSizeIdx := argMax(normalizedHits)
@@ -443,8 +443,8 @@ class MultiCoalescer(windowT: CoalShiftQueue[ReqQueueEntry], coalReqT: ReqQueueE
 
   // note: this is word-level coalescing. if finer granularity is needed, need to modify code
   val numWords = (1.U << (chosenSize - config.wordWidth.U)).asUInt
-  val maxWords = 1 << (config.maxCoalLogSize() - config.wordWidth)
-  val addrMask = Wire(UInt(config.maxCoalLogSize().W))
+  val maxWords = 1 << (config.maxCoalLogSize - config.wordWidth)
+  val addrMask = Wire(UInt(config.maxCoalLogSize.W))
   addrMask := (1.U << chosenSize).asUInt - 1.U
 
   val data = Wire(Vec(maxWords, UInt((config.wordSizeInBytes * 8).W)))
@@ -452,7 +452,7 @@ class MultiCoalescer(windowT: CoalShiftQueue[ReqQueueEntry], coalReqT: ReqQueueE
 
   for (i <- 0 until maxWords) {
     val sel = flatReqs.zip(flatMatches).map { case (req, m) =>
-      m && ((req.address(config.maxCoalLogSize() - 1, 0) & addrMask) === i.U)
+      m && ((req.address(config.maxCoalLogSize - 1, 0) & addrMask) === i.U)
     }
     // TODO: SW uses priority encoder, not sure about behavior of MuxCase
     data(i) := MuxCase(DontCare, flatReqs.zip(sel).map { case (req, s) =>
@@ -505,7 +505,7 @@ class CoalescingUnitImp(outer: CoalescingUnit, config: CoalescerConfig) extends
     Module(new CoalShiftQueue(reqQueueEntryT, config.queueDepth))
   }
 
-  val coalReqT = new ReqQueueEntry(sourceWidth, log2Ceil(config.maxCoalLogSize()), config.addressWidth, config.maxCoalLogSize())
+  val coalReqT = new ReqQueueEntry(sourceWidth, log2Ceil(config.maxCoalLogSize), config.addressWidth, config.maxCoalLogSize)
   val coalescer = Module(new MultiCoalescer(reqQueues.head, coalReqT, config))
   coalescer.io.window := reqQueues.map(_.io)
 
@@ -575,7 +575,7 @@ class CoalescingUnitImp(outer: CoalescingUnit, config: CoalescerConfig) extends
   // coalesced request.  Upper bound is min(DEPTH, 2**sourceWidth).
   val numPerLaneReqs = config.queueDepth
 
-  val respQueueEntryT = new RespQueueEntry(sourceWidth, log2Ceil(config.maxCoalLogSize()), config.maxCoalLogSize())
+  val respQueueEntryT = new RespQueueEntry(sourceWidth, log2Ceil(config.maxCoalLogSize), config.maxCoalLogSize)
   val respQueues = Seq.tabulate(config.numLanes) { _ =>
     Module(
       new MultiPortQueue(
@@ -695,7 +695,7 @@ class CoalescingUnitImp(outer: CoalescingUnit, config: CoalescerConfig) extends
   newEntry.source := coalescer.io.outReq.bits.source
 
   // TODO: richard to write table fill logic
-  assert (config.maxCoalLogSize() <= config.dataBusWidth,
+  assert (config.maxCoalLogSize <= config.dataBusWidth,
     "multi-beat coalesced reads/writes are currently not supported")
   assert (
     tlCoal.params.dataBits == (1 << config.dataBusWidth) * 8,
@@ -708,7 +708,7 @@ class CoalescingUnitImp(outer: CoalescingUnit, config: CoalescerConfig) extends
       // TODO: this part needs the actual coalescing logic to work
       r.valid := false.B
       r.source := origReqs(i).source
-      r.offset := (origReqs(i).address % (1 << config.maxCoalLogSize()).U) >> config.wordWidth
+      r.offset := (origReqs(i).address % (1 << config.maxCoalLogSize).U) >> config.wordWidth
       r.sizeEnum := config.sizeEnum.logSizeToEnum(origReqs(i).size)
     }
   }
@@ -762,7 +762,7 @@ class CoalescingUnitImp(outer: CoalescingUnit, config: CoalescerConfig) extends
 // FIXME: overlaps with RespQueueEntry. Trait-ify
 class CoalescedResponseBundle(config: CoalescerConfig) extends Bundle {
   val source = UInt(log2Ceil(config.numNewSrcIds).W)
-  val data = UInt((8 * (1 << config.maxCoalLogSize())).W)
+  val data = UInt((8 * (1 << config.maxCoalLogSize)).W)
 }
 
 class UncoalescingUnit(config: CoalescerConfig) extends Module {
@@ -871,7 +871,7 @@ class InflightCoalReqTable(config: CoalescerConfig) extends Module {
     config.numLanes,
     config.queueDepth,
     log2Ceil(config.numOldSrcIds),
-    config.maxCoalLogSize(),
+    config.maxCoalLogSize,
     config.sizeEnum
   )