Fixed MemTracerDriverImp to only terminate when all outstanding reqs are reclaimed
This is for slightly more accurate perf numbers.
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@@ -242,12 +242,15 @@ class RoundRobinSourceGenerator(sourceWidth: Int, ignoreInUse: Boolean = true)
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val gen = Input(Bool())
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val gen = Input(Bool())
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val reclaim = Input(Valid(UInt(sourceWidth.W)))
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val reclaim = Input(Valid(UInt(sourceWidth.W)))
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val id = Output(Valid(UInt(sourceWidth.W)))
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val id = Output(Valid(UInt(sourceWidth.W)))
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val inflight = Output(Bool())
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})
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})
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val head = RegInit(UInt(sourceWidth.W), 0.U)
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val head = RegInit(UInt(sourceWidth.W), 0.U)
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head := Mux(io.gen, head + 1.U, head)
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head := Mux(io.gen, head + 1.U, head)
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// for debugging
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// for debugging
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// also for indicating if there is at least one inflight request that hasn't been reclaimed
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val outstanding = RegInit(UInt((sourceWidth + 1).W), 0.U)
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val outstanding = RegInit(UInt((sourceWidth + 1).W), 0.U)
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io.inflight := outstanding > 0.U
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val numSourceId = 1 << sourceWidth
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val numSourceId = 1 << sourceWidth
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// true: in use, false: available
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// true: in use, false: available
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@@ -1468,13 +1471,14 @@ class MemTraceDriverImp(
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// Give some slack time after trace EOF to the downstream system to make sure
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// Give some slack time after trace EOF to the downstream system to make sure
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// we receive all (hopefully) outstanding responses back.
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// we receive all (hopefully) outstanding responses back.
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val finishCounter = RegInit(200.U(64.W))
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val traceFinished = RegInit(false.B)
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when(sim.io.trace_read.finished) {
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when(sim.io.trace_read.finished) {
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finishCounter := finishCounter - 1.U
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traceFinished := true.B
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}
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}
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io.finished := (finishCounter === 0.U)
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val allReqReclaimed = !(sourceGens.map(_.io.inflight).reduce(_ || _))
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when(io.finished) {
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when(traceFinished && allReqReclaimed) {
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assert(
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assert(
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false.B,
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false.B,
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"\n\n\nsimulation Successfully finished\n\n\n (this assertion intentional fail upon MemTracer termination)"
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"\n\n\nsimulation Successfully finished\n\n\n (this assertion intentional fail upon MemTracer termination)"
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