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Rename sourceWidth -> tagWidth

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Hansung Kim
2023-11-19 17:49:47 -08:00
parent 1346f74210
commit d7cbf4916a
1 changed files with 10 additions and 10 deletions
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20
src/main/scala/rocket/VortexCore.scala
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@@ -10,26 +10,26 @@ import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.tile._ import freechips.rocketchip.tile._
class VortexBundleA( class VortexBundleA(
sourceWidth: Int, tagWidth: Int,
dataWidth: Int dataWidth: Int
) extends Bundle { ) extends Bundle {
assert(dataWidth % 8 == 0) assert(dataWidth % 8 == 0)
val opcode = UInt(3.W) // FIXME: hardcoded val opcode = UInt(3.W) // FIXME: hardcoded
val size = UInt(4.W) // FIXME: hardcoded val size = UInt(4.W) // FIXME: hardcoded
val source = UInt(sourceWidth.W) // FIXME: hardcoded val source = UInt(tagWidth.W) // FIXME: hardcoded
val address = UInt(32.W) // FIXME: hardcoded val address = UInt(32.W) // FIXME: hardcoded
val mask = UInt((dataWidth / 8).W) // FIXME: hardcoded val mask = UInt((dataWidth / 8).W) // FIXME: hardcoded
val data = UInt(dataWidth.W) // FIXME: hardcoded val data = UInt(dataWidth.W) // FIXME: hardcoded
} }
class VortexBundleD( class VortexBundleD(
sourceWidth: Int, tagWidth: Int,
dataWidth: Int dataWidth: Int
) extends Bundle { ) extends Bundle {
assert(dataWidth % 8 == 0) assert(dataWidth % 8 == 0)
val opcode = UInt(3.W) // FIXME: hardcoded val opcode = UInt(3.W) // FIXME: hardcoded
val size = UInt(4.W) // FIXME: hardcoded val size = UInt(4.W) // FIXME: hardcoded
val source = UInt(sourceWidth.W) // FIXME: hardcoded val source = UInt(tagWidth.W) // FIXME: hardcoded
val data = UInt(dataWidth.W) // FIXME: hardcoded val data = UInt(dataWidth.W) // FIXME: hardcoded
} }
@@ -42,16 +42,16 @@ class VortexBundle(tile: VortexTile)(implicit p: Parameters) extends CoreBundle
// conditionally instantiate ports depending on whether we want to use VX_cache or not // conditionally instantiate ports depending on whether we want to use VX_cache or not
val imem = if (!tile.vortexParams.useVxCache) Some(Vec(1, new Bundle { val imem = if (!tile.vortexParams.useVxCache) Some(Vec(1, new Bundle {
val a = Decoupled(new VortexBundleA(sourceWidth = 46, dataWidth = 32)) val a = Decoupled(new VortexBundleA(tagWidth = 46, dataWidth = 32))
val d = Flipped(Decoupled(new VortexBundleD(sourceWidth = 46, dataWidth = 32))) val d = Flipped(Decoupled(new VortexBundleD(tagWidth = 46, dataWidth = 32)))
})) else None })) else None
val dmem = if (!tile.vortexParams.useVxCache) Some(Vec(tile.numLanes, new Bundle { val dmem = if (!tile.vortexParams.useVxCache) Some(Vec(tile.numLanes, new Bundle {
val a = Decoupled(new VortexBundleA(sourceWidth = 46, dataWidth = 32)) val a = Decoupled(new VortexBundleA(tagWidth = 46, dataWidth = 32))
val d = Flipped(Decoupled(new VortexBundleD(sourceWidth = 46, dataWidth = 32))) val d = Flipped(Decoupled(new VortexBundleD(tagWidth = 46, dataWidth = 32)))
})) else None })) else None
val mem = if (tile.vortexParams.useVxCache) Some(new Bundle { val mem = if (tile.vortexParams.useVxCache) Some(new Bundle {
val a = Decoupled(new VortexBundleA(sourceWidth = 15, dataWidth = 128)) val a = Decoupled(new VortexBundleA(tagWidth = 15, dataWidth = 128))
val d = Flipped(Decoupled(new VortexBundleD(sourceWidth = 15, dataWidth = 128))) val d = Flipped(Decoupled(new VortexBundleD(tagWidth = 15, dataWidth = 128)))
// val a = tile.memNode.out.head._1.a.cloneType // val a = tile.memNode.out.head._1.a.cloneType
// val d = Flipped(tile.memNode.out.head._1.d.cloneType) // val d = Flipped(tile.memNode.out.head._1.d.cloneType)
}) else None }) else None