wu-arch/radiance
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Reformat

Browse Source
This commit is contained in:
Hansung Kim
2023-11-10 14:46:33 -08:00
parent 17a39a369f
commit d51ce4cfa8
1 changed files with 184 additions and 133 deletions
Download Patch File Download Diff File Expand all files Collapse all files

139
src/main/scala/tile/VortexTile.scala
View File

@@ -87,7 +87,8 @@ case class VortexCoreParams(
mimpid: Int = 0x20181004, // release date in BCD
mulDiv: Option[MulDivParams] = Some(MulDivParams()),
fpu: Option[FPUParams] = Some(FPUParams()),
debugROB: Boolean = false, // if enabled, uses a C++ debug ROB to generate trace-with-wdata
debugROB: Boolean =
false, // if enabled, uses a C++ debug ROB to generate trace-with-wdata
haveCease: Boolean = true, // non-standard CEASE instruction
haveSimTimeout: Boolean = true // add plusarg for simulation timeout
) extends CoreParams {
@@ -123,12 +124,14 @@ class VortexTile private (
// Memory-mapped region for HTIF communication
// We use fixed addresses instead of tohost/fromhost
val regDevice = new SimpleDevice("vortex-reg", Seq(s"vortex-reg${tileParams.hartId}"))
val regDevice =
new SimpleDevice("vortex-reg", Seq(s"vortex-reg${tileParams.hartId}"))
val regNode = TLRegisterNode(
address = Seq(AddressSet(0x7c000000 + 0x1000 * tileParams.hartId, 0xfff)),
device = regDevice,
beatBytes = 4,
concurrency = 1)
concurrency = 1
)
regNode := tlSlaveXbar.node
@@ -149,8 +152,10 @@ class VortexTile private (
beatBytes = lazyCoreParamsView.coreDataBytes,
minLatency = 1)))*/
require(p(SIMTCoreKey).isDefined,
"SIMTCoreKey not defined; make sure to use WithSimtLanes when using VortexTile")
require(
p(SIMTCoreKey).isDefined,
"SIMTCoreKey not defined; make sure to use WithSimtLanes when using VortexTile"
)
val numLanes = p(SIMTCoreKey) match {
case Some(simtParam) => simtParam.nLanes
case None => 4
@@ -168,34 +173,45 @@ class VortexTile private (
// ibuffer size is set as a hardcoded macro IBUF_SIZE that's uncontrollable
// from Chisel, there's no easy solution. We at least don't expose this as a
// Parameter and leave as a hardcoded value here.
val imemSourceWidth = 1 // 1 << 2 == IBUF_SIZE = 4
val imemSourceWidth = 6 // 1 << imemSourceWidth == IBUF_SIZE
val dmemSourceWidth = p(SIMTCoreKey) match {
// TODO: respect coalescer newSrcIds
case Some(simtParam) => log2Ceil(simtParam.nSrcIds)
case None => 4
}
require(dmemSourceWidth >= 4,
require(
dmemSourceWidth >= 4,
"Setting a small number of sourceIds may cause correctness bug inside " +
"Vortex core due to synchronization issues in vx_wspawn. " +
"We recommend setting nSrcIds to at least 16.")
"We recommend setting nSrcIds to at least 16."
)
val imemNodes = Seq.tabulate(1) { i =>
TLClientNode(Seq(TLMasterPortParameters.v1(
clients = Seq(TLMasterParameters.v1(
TLClientNode(
Seq(
TLMasterPortParameters.v1(
clients = Seq(
TLMasterParameters.v1(
sourceId = IdRange(0, 1 << imemSourceWidth),
name = s"Vortex Core ${vortexParams.hartId} I-Mem $i",
requestFifo = true,
supportsProbe =
TransferSizes(1, lazyCoreParamsView.coreDataBytes),
supportsGet = TransferSizes(1, lazyCoreParamsView.coreDataBytes)
))
)))
)
)
)
)
)
}
val dmemNodes = Seq.tabulate(numLanes) { i =>
TLClientNode(Seq(TLMasterPortParameters.v1(
clients = Seq(TLMasterParameters.v1(
TLClientNode(
Seq(
TLMasterPortParameters.v1(
clients = Seq(
TLMasterParameters.v1(
sourceId = IdRange(0, 1 << dmemSourceWidth),
name = s"Vortex Core ${vortexParams.hartId} D-Mem Lane $i",
requestFifo = true,
@@ -206,8 +222,11 @@ class VortexTile private (
TransferSizes(1, lazyCoreParamsView.coreDataBytes),
supportsPutPartial =
TransferSizes(1, lazyCoreParamsView.coreDataBytes)
))
)))
)
)
)
)
)
}
// combine outgoing per-lane dmemNode into 1 idenity node
//
@@ -220,8 +239,11 @@ class VortexTile private (
val dmemAggregateNode = TLIdentityNode()
dmemNodes.foreach { dmemAggregateNode := TLWidthWidget(4) := _ }
val memNode = TLClientNode(Seq(TLMasterPortParameters.v1(
clients = Seq(TLMasterParameters.v1(
val memNode = TLClientNode(
Seq(
TLMasterPortParameters.v1(
clients = Seq(
TLMasterParameters.v1(
// FIXME: need to also respect imemSourceWidth
sourceId = IdRange(0, 1 << dmemSourceWidth),
name = s"Vortex Core ${vortexParams.hartId} Mem Interface",
@@ -230,13 +252,18 @@ class VortexTile private (
supportsGet = TransferSizes(16, 16),
supportsPutFull = TransferSizes(16, 16),
supportsPutPartial = TransferSizes(16, 16)
))
)))
)
)
)
)
)
// Conditionally instantiate memory coalescer
val coalescerNode = p(CoalescerKey) match {
case Some(coalescerParam) => {
val coal = LazyModule(new CoalescingUnit(coalescerParam.copy(enable = true)))
val coal = LazyModule(
new CoalescingUnit(coalescerParam.copy(enable = true))
)
coal.cpuNode :=* dmemAggregateNode
coal.aggregateNode // N+1 lanes
}
@@ -245,10 +272,14 @@ class VortexTile private (
// Conditionally instantiate L1 cache
val l1Node = p(L1SystemKey) match {
case Some(l1SystemCfg) =>{
println(s"============ Using Vortex FatBank as L1 System =================")
require(p(CoalescerKey).isDefined,
"Vortex L1 configuration currently only works when coalescer is also enabled.")
case Some(l1SystemCfg) => {
println(
s"============ Using Vortex FatBank as L1 System ================="
)
require(
p(CoalescerKey).isDefined,
"Vortex L1 configuration currently only works when coalescer is also enabled."
)
val L1System = LazyModule(new L1System(l1SystemCfg))
// Connect L1System with imem_fetch_interface without XBar
@@ -299,19 +330,28 @@ class VortexTile private (
masterNode :=* tlOtherMastersNode
DisableMonitors { implicit p => tlSlaveXbar.node :*= slaveNode }
val dtimProperty = Nil //Seq(dmemDevice.asProperty).flatMap(p => Map("sifive,dtim" -> p))
val dtimProperty =
Nil // Seq(dmemDevice.asProperty).flatMap(p => Map("sifive,dtim" -> p))
val itimProperty = Nil //frontend.icache.itimProperty.toSeq.flatMap(p => Map("sifive,itim" -> p))
val itimProperty =
Nil // frontend.icache.itimProperty.toSeq.flatMap(p => Map("sifive,itim" -> p))
val beuProperty = bus_error_unit.map(d => Map(
"sifive,buserror" -> d.device.asProperty)).getOrElse(Nil)
val beuProperty = bus_error_unit
.map(d => Map("sifive,buserror" -> d.device.asProperty))
.getOrElse(Nil)
val cpuDevice: SimpleDevice = new SimpleDevice("cpu", Seq(s"sifive,vortex${tileParams.hartId}", "riscv")) {
val cpuDevice: SimpleDevice = new SimpleDevice(
"cpu",
Seq(s"sifive,vortex${tileParams.hartId}", "riscv")
) {
override def parent = Some(ResourceAnchors.cpus)
override def describe(resources: ResourceBindings): Description = {
val Description(name, mapping) = super.describe(resources)
Description(name, mapping ++ cpuProperties ++ nextLevelCacheProperty
++ tileProperties ++ dtimProperty ++ itimProperty ++ beuProperty)
Description(
name,
mapping ++ cpuProperties ++ nextLevelCacheProperty
++ tileProperties ++ dtimProperty ++ itimProperty ++ beuProperty
)
}
}
@@ -402,12 +442,14 @@ class VortexTileModuleImp(outer: VortexTile) extends BaseTileModuleImp(outer) {
println(s"width of a channel data ${core.io.mem.get.a.bits.data.getWidth}")
println(s"width of d channel data ${core.io.mem.get.d.bits.data.getWidth}")
val memTLAdapter = Module(new VortexTLAdapter(
val memTLAdapter = Module(
new VortexTLAdapter(
outer.dmemSourceWidth,
chiselTypeOf(core.io.mem.get.a.bits),
chiselTypeOf(core.io.mem.get.d.bits),
outer.memNode.out.head
))
)
)
// connection: VortexBundle <--> VortexTLAdapter <--> TL memNode
memTLAdapter.io.inReq <> core.io.mem.get.a
@@ -415,12 +457,14 @@ class VortexTileModuleImp(outer: VortexTile) extends BaseTileModuleImp(outer) {
outer.memNode.out(0)._1.a <> memTLAdapter.io.outReq
memTLAdapter.io.outResp <> outer.memNode.out(0)._1.d
} else {
val imemTLAdapter = Module(new VortexTLAdapter(
val imemTLAdapter = Module(
new VortexTLAdapter(
outer.imemSourceWidth,
chiselTypeOf(core.io.imem.get(0).a.bits),
chiselTypeOf(core.io.imem.get(0).d.bits),
outer.imemNodes.head.out.head
))
)
)
// TODO: make imemNodes not a vector
imemTLAdapter.io.inReq <> core.io.imem.get(0).a
core.io.imem.get(0).d <> imemTLAdapter.io.inResp
@@ -431,12 +475,14 @@ class VortexTileModuleImp(outer: VortexTile) extends BaseTileModuleImp(outer) {
// up some area
val dmemTLBundles = outer.dmemNodes.map(_.out.head._1)
val dmemTLAdapters = Seq.tabulate(outer.numLanes) { _ =>
Module(new VortexTLAdapter(
Module(
new VortexTLAdapter(
outer.dmemSourceWidth,
chiselTypeOf(core.io.dmem.get(0).a.bits),
chiselTypeOf(core.io.dmem.get(0).d.bits),
outer.dmemNodes(0).out.head
))
)
)
}
// Since the individual per-lane TL requests might come back out-of-sync between
@@ -459,7 +505,10 @@ class VortexTileModuleImp(outer: VortexTile) extends BaseTileModuleImp(outer) {
// TODO: A cleaner solution would be to simply do a synchronized allocation
// of a same source id for all lanes.
val arb = Module(
new RRArbiter(core.io.dmem.get.head.d.bits.source.cloneType, outer.numLanes)
new RRArbiter(
core.io.dmem.get.head.d.bits.source.cloneType,
outer.numLanes
)
)
arb.io.out.ready := true.B
val dmemBundles = dmemTLAdapters.map(_.io.inResp)
@@ -473,7 +522,8 @@ class VortexTileModuleImp(outer: VortexTile) extends BaseTileModuleImp(outer) {
// If there is no valid response pending across all lanes,
// matchingSources should not filter out upstream ready signals, so
// set it to all-1
!arb.io.out.valid || (b.bits.source === arb.io.out.bits))
!arb.io.out.valid || (b.bits.source === arb.io.out.bits)
)
.asUInt
// make connection:
@@ -499,8 +549,7 @@ class VortexTileModuleImp(outer: VortexTile) extends BaseTileModuleImp(outer) {
}
// TODO: generalize for useVxCache
if (!outer.vortexParams.useVxCache) {
}
if (!outer.vortexParams.useVxCache) {}
}
// Some @copypaste from CoalescerSourceGen.
@@ -518,11 +567,13 @@ class VortexTLAdapter(
val outResp = chiselTypeOf(outTL._1.d)
})
val edge = outTL._2
val sourceGen = Module(new SourceGenerator(
val sourceGen = Module(
new SourceGenerator(
newSourceWidth,
Some(inReqT.source),
ignoreInUse = false
))
)
)
sourceGen.io.gen := io.outReq.fire // use up a source ID only when request is created
sourceGen.io.reclaim.valid := io.outResp.fire
sourceGen.io.reclaim.bits := io.outResp.bits.source