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Remove dedicated icache bank from VortexBank

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This commit is contained in:
Hansung Kim
2023-11-28 18:42:58 -08:00
parent b66be6c3ae
commit d45cf835cf
2 changed files with 13 additions and 17 deletions
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15
src/main/scala/rocket/VortexBank.scala
View File

@@ -38,14 +38,15 @@ object defaultVortexL1Config
writeInfoReqQSize = 16, writeInfoReqQSize = 16,
mshrSize = 8, mshrSize = 8,
memSideSourceIds = 8, memSideSourceIds = 8,
uncachedAddrSets = Seq(AddressSet(0x2000000L, 0xffL)), // Don't cache CLINT region to ensure coherent access
icacheInstAddrSets = Seq(AddressSet(0x80000000L, 0xfffffffL)) uncachedAddrSets = Seq(AddressSet(0x2000000L, 0xffffL)),
icacheInstAddrSets = Seq(AddressSet(0x80000000L, 0x0fffffffL))
) )
class VortexL1Cache(config: VortexL1Config)(implicit p: Parameters) class VortexL1Cache(config: VortexL1Config)(implicit p: Parameters)
extends LazyModule { extends LazyModule {
// icache bank // icache bank
val icache_bank = LazyModule(new VortexBank(config, 0, isICache = true)) // val icache_bank = LazyModule(new VortexBank(config, 0, isICache = true))
// dcache banks // dcache banks
val dcache_banks = Seq.tabulate(config.numBanks) { bankId => val dcache_banks = Seq.tabulate(config.numBanks) { bankId =>
@@ -63,13 +64,13 @@ class VortexL1Cache(config: VortexL1Config)(implicit p: Parameters)
bankXbar.node :=* coresideNode bankXbar.node :=* coresideNode
dcache_banks.foreach { _.coresideNode :=* bankXbar.node } dcache_banks.foreach { _.coresideNode :=* bankXbar.node }
passThrough.coresideNode :=* bankXbar.node passThrough.coresideNode :=* bankXbar.node
icache_bank.coresideNode :=* bankXbar.node // icache_bank.coresideNode :=* bankXbar.node
// master node that exposes to and drives the downstream // master node that exposes to and drives the downstream
val masterNode = TLIdentityNode() val masterNode = TLIdentityNode()
dcache_banks.foreach { masterNode := _.vxCacheToL2Node } dcache_banks.foreach { masterNode := _.vxCacheToL2Node }
masterNode := passThrough.vxCacheToL2Node masterNode := passThrough.vxCacheToL2Node
masterNode := icache_bank.vxCacheToL2Node // masterNode := icache_bank.vxCacheToL2Node
lazy val module = new LazyModuleImp(this) lazy val module = new LazyModuleImp(this)
} }
@@ -141,7 +142,6 @@ class VortexBank(
def generateAddressSets(): Seq[AddressSet] = { def generateAddressSets(): Seq[AddressSet] = {
if (isICache) { if (isICache) {
config.icacheInstAddrSets config.icacheInstAddrSets
// Seq(AddressSet(0x00000000L, 0xFFFFFFFFL))
} else { } else {
// suppose have 4 bank // suppose have 4 bank
// base for bank 1: ...000000|01|0000 // base for bank 1: ...000000|01|0000
@@ -149,7 +149,8 @@ class VortexBank(
val mask = 0xffffffffL ^ ((config.numBanks - 1) * config.wordSize) val mask = 0xffffffffL ^ ((config.numBanks - 1) * config.wordSize)
val base = 0x00000000L | (bankId * config.wordSize) val base = 0x00000000L | (bankId * config.wordSize)
val excludeSets = (config.uncachedAddrSets ++ config.icacheInstAddrSets) // val excludeSets = (config.uncachedAddrSets ++ config.icacheInstAddrSets)
val excludeSets = config.uncachedAddrSets
var remainingSets: Seq[AddressSet] = Seq(AddressSet(base, mask)) var remainingSets: Seq[AddressSet] = Seq(AddressSet(base, mask))
for (excludeSet <- excludeSets) { for (excludeSet <- excludeSets) {
remainingSets = remainingSets.flatMap(_.subtract(excludeSet)) remainingSets = remainingSets.flatMap(_.subtract(excludeSet))

15
src/main/scala/tile/VortexTile.scala
View File

@@ -282,25 +282,20 @@ class VortexTile private (
) )
val l1cache = LazyModule(new VortexL1Cache(vortexL1Config)) val l1cache = LazyModule(new VortexL1Cache(vortexL1Config))
// Connect L1 with imem_fetch_interface without XBar // // Connect L1 with imem_fetch_interface without XBar
// imemNodes.foreach { l1cache.icache_bank.coresideNode := TLWidthWidget(4) := _ } // // imemNodes.foreach { l1cache.icache_bank.coresideNode := TLWidthWidget(4) := _ }
imemNodes.foreach { l1cache.coresideNode := TLWidthWidget(4) := _ } // imemNodes.foreach { l1cache.coresideNode := TLWidthWidget(4) := _ }
// dmemNodes go through coalescerNode // dmemNodes go through coalescerNode
l1cache.coresideNode :=* coalescerNode l1cache.coresideNode :=* coalescerNode
l1cache.masterNode l1cache.masterNode
} }
case None => { case None => coalescerNode
// Regardless of using coalescer or not, if we're not using L1, imemNode
// goes directly to tile exit xbar
// FIXME: unnatural, have L1 just handle dmem
imemNodes.foreach { tlMasterXbar.node := TLWidthWidget(4) := _ }
coalescerNode
}
} }
if (vortexParams.useVxCache) { if (vortexParams.useVxCache) {
tlMasterXbar.node := TLWidthWidget(16) := memNode tlMasterXbar.node := TLWidthWidget(16) := memNode
} else { } else {
imemNodes.foreach { tlMasterXbar.node := TLWidthWidget(4) := _ }
tlMasterXbar.node :=* l1Node tlMasterXbar.node :=* l1Node
} }