Add RTL for Coalescer Priority XBar and relevant keys&configs for SoC Integration

src/main/scala/tilelink/Coalescing.scala

@@ -13,10 +13,12 @@ import freechips.rocketchip.unittest._
 // TODO: find better place for these
 case class SIMTCoreParams(nLanes: Int = 4)
 case class MemtraceCoreParams(tracefilename: String = "undefined", traceHasSource: Boolean = false)
+case class CoalXbarParam()
 
 case object SIMTCoreKey extends Field[Option[SIMTCoreParams]](None /*default*/)
 case object MemtraceCoreKey extends Field[Option[MemtraceCoreParams]](None /*default*/)
 case object CoalescerKey extends Field[Option[CoalescerConfig]](None /*default*/)
+case object CoalXbarKey extends Field[Option[CoalXbarParam]](None /*default*/)
 
 trait InFlightTableSizeEnum extends ChiselEnum {
   val INVALID: Type
@@ -69,7 +71,7 @@ case class CoalescerConfig(
   numCoalReqs: Int,       // total number of coalesced requests we can generate in one cycle
   numArbiterOutputPorts: Int, // total of output ports the arbiter will arbitrate into.
                               // this has to match downstream cache's configuration
-  bankStrideInBytes: Int  // cache line strides across the different banks
+  bankStrideInBytes: Int,  // cache line strides across the different banks
 ) {
   // maximum coalesced size
   def maxCoalLogSize: Int = coalLogSizes.max
@@ -2029,6 +2031,7 @@ class TLRAMCoalescerTest(timeout: Int = 500000)(implicit p: Parameters)
 ////////////
 
 // Lazy Module is needed to instantiate outgoing node
+// I think the following implementation of Coalescer CrossBar is not going to be useful anytime soon
 class CoalescerXbar(config: CoalescerConfig) (implicit p: Parameters) extends LazyModule {
     // Let SIMT's word size be 32, and read/write granularity be 256 
 
@@ -2170,3 +2173,23 @@ class CoalescerXbarImpl(outer: CoalescerXbar,
 
 
   }
+
+
+  //The current TLPrirotyXBar has a few workaround
+  //1. it doesn't support temporal coalescing (it doesn't allow drift)
+  //2. it's only a a dummy object for testing purpose, we need our own XBar (or Topology) for future L1
+  class CoalescerTLPriortyXBar (implicit p: Parameters) extends LazyModule {
+
+    val coalescerOutputNode = TLIdentityNode()
+    val outputXbar          = LazyModule(new TLXbar(TLArbiter.lowestIndexFirst))
+    val node                = TLIdentityNode()
+
+    outputXbar.node  :=* TLBuffer(BufferParams.pipe, BufferParams.pipe) :=* coalescerOutputNode
+    node             :=* outputXbar.node
+
+    lazy val module = new Impl
+    class Impl extends LazyModuleImp(this) {
+      //Nonthing
+    }
+
+  }

src/main/scala/tilelink/TracerSystemMem.scala

@@ -29,7 +29,7 @@ trait CanHaveMemtraceCore { this: BaseSubsystem =>
     println(
       s"============ MemTraceDriver instantiated [filename=${param.tracefilename}]"
     )
-    val upstream = p(CoalescerKey) match {
+    val coalescerNode = p(CoalescerKey) match {
       case Some(coalParam) => {
         val coal = LazyModule(new CoalescingUnit(coalParam))
         println(s"============ CoalescingUnit instantiated [numLanes=${coalParam.numLanes}]")
@@ -39,6 +39,16 @@ trait CanHaveMemtraceCore { this: BaseSubsystem =>
       }
       case None => tracer.node
     }
+    val upstream = p(CoalXbarKey) match {
+      case Some(xbarParam) =>{
+        val priorityXbar = LazyModule(new CoalescerTLPriortyXBar)
+        println(s"============ Using Priority XBar for Coalescer Requests ")
+        priorityXbar.node :=* coalescerNode
+        priorityXbar.node
+      }
+      case None => coalescerNode
+    }
+    
     sbus.fromPort(Some("gpu-tracer"))() :=* upstream
   }
 }