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Generate explicit clock domain in CanHaveMemtraceCore

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Hansung Kim
2024-01-26 00:13:14 -08:00
parent 78075e5148
commit cfce029b70
1 changed files with 49 additions and 48 deletions
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97
src/main/scala/radiance/memory/CanHaveMemtraceCore.scala
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@@ -22,56 +22,57 @@ trait CanHaveMemtraceCore { this: BaseSubsystem =>
) )
val numLanes = simtParam.nLanes val numLanes = simtParam.nLanes
val filename = param.tracefilename val filename = param.tracefilename
val tracer = LazyModule(
new MemTraceDriver(config, filename, param.traceHasSource)(p) // Need to explicitly generate clock domain; see rocket-chip 8881ccd
) val memtracerDomain = sbus.generateSynchronousDomain
val coreSideLogger = LazyModule( memtracerDomain {
new MemTraceLogger(numLanes, filename, loggerName = "coreside") val tracer = LazyModule(
) new MemTraceDriver(config, filename, param.traceHasSource)(p)
val memSideLogger = LazyModule( )
new MemTraceLogger(numLanes + 1, filename, loggerName = "memside") val coreSideLogger = LazyModule(
) new MemTraceLogger(numLanes, filename, loggerName = "coreside")
// Must use :=* to ensure the N edges from Tracer doesn't get merged into 1 )
// when connecting to SBus val memSideLogger = LazyModule(
println( new MemTraceLogger(numLanes + 1, filename, loggerName = "memside")
s"============ MemTraceDriver instantiated [filename=${param.tracefilename}]" )
) // Must use :=* to ensure the N edges from Tracer doesn't get merged into 1
val coalescerNode = p(CoalescerKey) match { // when connecting to SBus
case Some(coalParam) => { println(
val coal = LazyModule(new CoalescingUnit(coalParam)) s"============ MemTraceDriver instantiated [filename=${param.tracefilename}]"
coal.cpuNode :=* coreSideLogger.node :=* tracer.node // N lanes )
memSideLogger.node :=* coal.aggregateNode // N+1 lanes val coalescerNode = p(CoalescerKey) match {
memSideLogger.node case Some(coalParam) => {
val coal = LazyModule(new CoalescingUnit(coalParam))
coal.cpuNode :=* coreSideLogger.node :=* tracer.node // N lanes
memSideLogger.node :=* coal.aggregateNode // N+1 lanes
memSideLogger.node
}
case None => tracer.node
}
val coalXbar = p(CoalXbarKey) match {
case Some(xbarParam) =>{
val coXbar = LazyModule(new TLXbar)
println(s"============ Using TLXBar for Coalescer Requests ")
coXbar.node :=* coalescerNode
coXbar.node
}
case None => coalescerNode
} }
case None => tracer.node
} val vortexBank = coalXbar
val coalXbar = p(CoalXbarKey) match {
case Some(xbarParam) =>{ //If there is only 1 bank, the code below is useless
val coXbar = LazyModule(new TLXbar) val upstream = p(CoalXbarKey) match {
println(s"============ Using TLXBar for Coalescer Requests ") case Some(xbarParam) =>{
coXbar.node :=* coalescerNode val tileXbar = LazyModule(new TLXbar)
coXbar.node println(s"============ Using TLXBar for L1 Requests ")
tileXbar.node :=* vortexBank
tileXbar.node
}
case None => vortexBank
} }
case None => coalescerNode
sbus.coupleFrom(s"gpu-tracer") { _ :=* upstream }
} }
val vortexBank = coalXbar
//If there is only 1 bank, the code below is useless
val upstream = p(CoalXbarKey) match {
case Some(xbarParam) =>{
val tileXbar = LazyModule(new TLXbar)
println(s"============ Using TLXBar for L1 Requests ")
tileXbar.node :=* vortexBank
tileXbar.node
}
case None => vortexBank
}
sbus.coupleFrom(s"gpu-tracer") { _ :=* upstream }
} }
} }