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Remove use of HasTiles to reflect upstream change

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Hansung Kim
2024-01-16 22:59:56 -08:00
parent 132742ea88
commit cd1022c608
2 changed files with 4 additions and 11 deletions
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9
src/main/scala/radiance/memory/CanHaveRadianceROMs.scala
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@@ -3,14 +3,7 @@ package radiance.memory
import freechips.rocketchip.subsystem._ import freechips.rocketchip.subsystem._
import org.chipsalliance.cde.config.Parameters import org.chipsalliance.cde.config.Parameters
// TODO: possibly move to somewhere closer to CoalescingUnit trait CanHaveRadianceROMs { this: BaseSubsystem =>
// TODO: separate coalescer config from CanHaveMemtraceCore
// The trait is attached to DigitalTop of Chipyard system, informing it indeed
// has the ability to attach GPU tracer node onto the system bus
trait CanHaveRadianceROMs { this: BaseSubsystem with HasTiles =>
implicit val p: Parameters implicit val p: Parameters
p(RadianceROMsLocated()).foreach(_.foreach { rom => RadianceROM.attachROM(rom, this, CBUS) }) p(RadianceROMsLocated()).foreach(_.foreach { rom => RadianceROM.attachROM(rom, this, CBUS) })
} }

6
src/main/scala/radiance/memory/RadianceROM.scala
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@@ -5,7 +5,7 @@ package radiance.memory
import chisel3._ import chisel3._
import chisel3.util.log2Ceil import chisel3.util.log2Ceil
import org.chipsalliance.cde.config.{Config, Field, Parameters} import org.chipsalliance.cde.config.{Config, Field, Parameters}
import freechips.rocketchip.subsystem.{BaseSubsystem, HasTiles, HierarchicalLocation, InSubsystem, TLBusWrapperLocation} import freechips.rocketchip.subsystem.{BaseSubsystem, HierarchicalLocation, InSubsystem, TLBusWrapperLocation}
import freechips.rocketchip.diplomacy._ import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._ import freechips.rocketchip.tilelink._
import freechips.rocketchip.devices.tilelink._ import freechips.rocketchip.devices.tilelink._
@@ -25,7 +25,7 @@ object RadianceROM {
* at a configurable location, but also drives the tiles' reset vectors to point * at a configurable location, but also drives the tiles' reset vectors to point
* at its 'hang' address parameter value. * at its 'hang' address parameter value.
*/ */
def attach(params: BootROMParams, subsystem: BaseSubsystem with HasTiles, where: TLBusWrapperLocation, def attach(params: BootROMParams, subsystem: BaseSubsystem, where: TLBusWrapperLocation,
driveResetVector: Boolean = true) (implicit p: Parameters): TLROM = { driveResetVector: Boolean = true) (implicit p: Parameters): TLROM = {
val tlbus = subsystem.locateTLBusWrapper(where) val tlbus = subsystem.locateTLBusWrapper(where)
val bootROMDomainWrapper = LazyModule(new ClockSinkDomain(take = None)) val bootROMDomainWrapper = LazyModule(new ClockSinkDomain(take = None))
@@ -46,7 +46,7 @@ object RadianceROM {
bootrom bootrom
} }
def attachROM(params: RadianceROMParams, subsystem: BaseSubsystem with HasTiles, where: TLBusWrapperLocation) def attachROM(params: RadianceROMParams, subsystem: BaseSubsystem, where: TLBusWrapperLocation)
(implicit p: Parameters): Unit = { (implicit p: Parameters): Unit = {
attach(BootROMParams(address = params.address, size = params.size, contentFileName = params.contentFileName), attach(BootROMParams(address = params.address, size = params.size, contentFileName = params.contentFileName),
subsystem, where, driveResetVector = false) subsystem, where, driveResetVector = false)