From 42b03edbf744f3d02b586d830d7da52cc9e71aea Mon Sep 17 00:00:00 2001 From: Hansung Kim Date: Fri, 5 May 2023 14:50:25 -0700 Subject: [PATCH 1/3] Update import path to cde to reflect upstream changes --- src/main/scala/tilelink/Coalescing.scala | 2 +- src/main/scala/tilelink/TracerSystemMem.scala | 3 +-- src/test/scala/coalescing/CoalescingUnitTest.scala | 2 +- 3 files changed, 3 insertions(+), 4 deletions(-) diff --git a/src/main/scala/tilelink/Coalescing.scala b/src/main/scala/tilelink/Coalescing.scala index f967a60..7aff976 100644 --- a/src/main/scala/tilelink/Coalescing.scala +++ b/src/main/scala/tilelink/Coalescing.scala @@ -5,7 +5,7 @@ package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.ChiselEnum -import freechips.rocketchip.config.Parameters +import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.diplomacy._ // import freechips.rocketchip.devices.tilelink.TLTestRAM import freechips.rocketchip.util.MultiPortQueue diff --git a/src/main/scala/tilelink/TracerSystemMem.scala b/src/main/scala/tilelink/TracerSystemMem.scala index 0b099c8..e0d495b 100644 --- a/src/main/scala/tilelink/TracerSystemMem.scala +++ b/src/main/scala/tilelink/TracerSystemMem.scala @@ -3,10 +3,9 @@ package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ -import freechips.rocketchip.config.Parameters import freechips.rocketchip.diplomacy._ import freechips.rocketchip.subsystem.{BaseSubsystem, CacheBlockBytes} -import freechips.rocketchip.config.{Parameters, Field, Config} +import org.chipsalliance.cde.config.{Parameters, Field, Config} // class class, consumed by WithGPUTacer config and GPUTracerKey diff --git a/src/test/scala/coalescing/CoalescingUnitTest.scala b/src/test/scala/coalescing/CoalescingUnitTest.scala index 585d412..4d6c346 100644 --- a/src/test/scala/coalescing/CoalescingUnitTest.scala +++ b/src/test/scala/coalescing/CoalescingUnitTest.scala @@ -6,7 +6,7 @@ import org.scalatest.flatspec.AnyFlatSpec import freechips.rocketchip.tilelink._ import freechips.rocketchip.util.MultiPortQueue import freechips.rocketchip.diplomacy._ -import chipsalliance.rocketchip.config.Parameters +import org.chipsalliance.cde.config.Parameters import chisel3.util.{DecoupledIO, Valid} import chisel3.util.experimental.BoringUtils From 4ebcfbb9ebb569963117f6a748a951697d2bd1ae Mon Sep 17 00:00:00 2001 From: Hansung Kim Date: Fri, 5 May 2023 15:51:59 -0700 Subject: [PATCH 2/3] Revert deq.valid; force-set io.coalesceable instead for coal.enable --- src/main/scala/tilelink/Coalescing.scala | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/main/scala/tilelink/Coalescing.scala b/src/main/scala/tilelink/Coalescing.scala index 7aff976..52f6c5b 100644 --- a/src/main/scala/tilelink/Coalescing.scala +++ b/src/main/scala/tilelink/Coalescing.scala @@ -247,8 +247,7 @@ class CoalShiftQueue[T <: Data](gen: T, entries: Int, config: CoalescerConfig) e // dequeue is valid when: // head entry is valid, has not been processed by downstream, and is not coalescable deq.bits := elts.map(_.head.bits)(i) - deq.valid := elts.map(_.head.valid)(i) && !deqDone(i) && - (!io.invalidate.valid || !io.coalescable(i)) + deq.valid := elts.map(_.head.valid)(i) && !deqDone(i) && !io.coalescable(i) // can take new entries if not empty, or if full but shifting enq.ready := (!ctrl.full) || ctrl.shift @@ -546,6 +545,7 @@ class MultiCoalescer(windowT: CoalShiftQueue[ReqQueueEntry], coalReqT: ReqQueueE def disable = { io.coalReq.valid := false.B io.invalidate.valid := false.B + io.coalescable.foreach { _ := false.B } } if (!config.enable) disable } From 3dad961082e6f6fbeb02b3e484e369c7e215d934 Mon Sep 17 00:00:00 2001 From: Vamber Yang Date: Fri, 5 May 2023 19:00:01 -0700 Subject: [PATCH 3/3] define top level IO bundle for CoalArbiter --- src/main/scala/tilelink/Coalescing.scala | 106 ++++++++++++++++++++++- 1 file changed, 104 insertions(+), 2 deletions(-) diff --git a/src/main/scala/tilelink/Coalescing.scala b/src/main/scala/tilelink/Coalescing.scala index f967a60..c080300 100644 --- a/src/main/scala/tilelink/Coalescing.scala +++ b/src/main/scala/tilelink/Coalescing.scala @@ -53,7 +53,9 @@ case class CoalescerConfig( coalLogSizes: Seq[Int], // list of coalescer sizes to try in the MonoCoalescers // each size is log(byteSize) sizeEnum: InFlightTableSizeEnum, - arbiterOutputs: Int + numCoalReq: Int, // the total number of coalesced request + arbiterOutputs: Int, //total number RW ports from the + bankStrideInBytes: Int //cache line strides across the different banks ) { // maximum coalesced size def maxCoalLogSize: Int = coalLogSizes.max @@ -75,7 +77,9 @@ object defaultConfig extends CoalescerConfig( respQueueDepth = 4, coalLogSizes = Seq(3), sizeEnum = DefaultInFlightTableSizeEnum, - arbiterOutputs = 4 + numCoalReq = 1, + arbiterOutputs = 4, + bankStrideInBytes = 64 //Current L2 is strided by 512 bits ) class CoalescingUnit(config: CoalescerConfig)(implicit p: Parameters) extends LazyModule { @@ -1712,3 +1716,101 @@ class TLRAMCoalescerTest(timeout: Int = 500000)(implicit p: Parameters) extends dut.io.start := io.start io.finished := dut.io.finished } + + +//////////// +//////////// +//////////// +//////////// Code for CoalArbiter +//////////// +//////////// + +// Lazy Module is needed to instantiate outgoing node +class CoalArbiter(config: CoalescerConfig) (implicit p: Parameters) extends LazyModule { + // Let SIMT's word size be 32, and read/write granularity be 256 + + val fullSourceIdRange = config.numOldSrcIds * config.numLanes + config.numNewSrcIds * config.numCoalReq + + // K client nodes of edge size 32 for non-coalesced reqs + val nonCoalNarrowNodes = Seq.tabulate(config.arbiterOutputs){ i => + val nonCoalNarrowParam = Seq( + TLMasterParameters.v1( + name = "NonCoalNarrowNode" + i.toString, + sourceId = IdRange(0, fullSourceIdRange) + ) + ) + TLClientNode(Seq(TLMasterPortParameters.v1(nonCoalNarrowParam))) + } + + // One identity Node for the Noncoalesced Reqest after Width Adaptation + // You can put widget between idenity node and client node (diplomacy) + val nonCoalNode = TLIdentityNode() + nonCoalNarrowNodes.foreach(narrowNode => + nonCoalNode := TLWidthWidget(config.wordSizeInBytes) := narrowNode + ) + + // K client nodes of edge size 256 for the coalesced reqs + val coalReqNodes = Seq.tabulate(config.arbiterOutputs){ i => + val coalParam = Seq( + TLMasterParameters.v1( + name = "CoalReqNode" + i.toString, + sourceId = IdRange(0, fullSourceIdRange) + ) + ) + TLClientNode(Seq(TLMasterPortParameters.v1(coalParam))) + } + // 1 idenity node for the Coalesced Reqs + val coalNode = TLIdentityNode() + coalReqNodes.foreach(coalReqNode => + coalNode := coalReqNode + ) + + + // 1 Final Output Identity Node + val outputNode = TLIdentityNode() + + + //Explictly define I/O bundule tyoe + val nonCoalEntryT = new ReqQueueEntry( + log2Ceil(config.numOldSrcIds), + config.wordWidth, + config.addressWidth, + log2Ceil(config.wordSizeInBytes) + ) + val coalEntryT = new ReqQueueEntry( + log2Ceil(config.numOldSrcIds), + log2Ceil(config.maxCoalLogSize), + config.addressWidth, + config.maxCoalLogSize //already log 2 + ) + val respNonCoalEntryT = new RespQueueEntry( + log2Ceil(config.numOldSrcIds), + config.wordWidth, + log2Ceil(config.wordSizeInBytes) + ) + + val respCoalBundleT = new CoalescedResponseBundle(config) + + lazy val module = new CoalArbiterImpl(this, config, nonCoalEntryT, coalEntryT, respNonCoalEntryT, respCoalBundleT) + +} + +class CoalArbiterImpl(outer: CoalArbiter, + config: CoalescerConfig, + nonCoalEntryT: ReqQueueEntry, + coalEntryT: ReqQueueEntry, + respNonCoalEntryT: RespQueueEntry, + respCoalBundleT: CoalescedResponseBundle + ) extends LazyModuleImp(outer){ + + + val io =IO(new Bundle { + val nonCoalVec = Vec(config.numLanes, Flipped(Decoupled(nonCoalEntryT.cloneType))) + val coalVec = Vec(config.numCoalReq, Flipped(Decoupled(coalEntryT.cloneType))) + val respNonCoalVec = Vec(config.numLanes, Decoupled(respNonCoalEntryT.cloneType)) + val respCoalBundle = Decoupled(respCoalBundleT.cloneType) + } + ) + + +}