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width widget in DummyCoalescingUnitTB

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This commit is contained in:
Richard Yan
2023-04-28 20:47:47 -07:00
parent 900f5adb20
commit c655874470
1 changed files with 7 additions and 5 deletions
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12
src/test/scala/coalescing/CoalescingUnitTest.scala
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@@ -38,7 +38,7 @@ class DummyCoalescingUnitTB(implicit p: Parameters) extends LazyModule {
TLClientNode(Seq(TLMasterPortParameters.v1(Seq(TLClientParameters( TLClientNode(Seq(TLMasterPortParameters.v1(Seq(TLClientParameters(
name = "processor-nodes", name = "processor-nodes",
sourceId = IdRange(0, testConfig.numOldSrcIds), sourceId = IdRange(0, testConfig.numOldSrcIds),
requestFifo = true, // requestFifo = true,
visibility = Seq(AddressSet(0x0, 0xffffff))))))) // 24 bit address space (TODO probably use testConfig) visibility = Seq(AddressSet(0x0, 0xffffff))))))) // 24 bit address space (TODO probably use testConfig)
} }
@@ -50,8 +50,6 @@ class DummyCoalescingUnitTB(implicit p: Parameters) extends LazyModule {
resources = device.reg, resources = device.reg,
regionType = RegionType.UNCACHED, regionType = RegionType.UNCACHED,
executable = true, executable = true,
supportsArithmetic = TransferSizes(1, beatBytes),
supportsLogical = TransferSizes(1, beatBytes),
supportsGet = TransferSizes(1, beatBytes), supportsGet = TransferSizes(1, beatBytes),
supportsPutFull = TransferSizes(1, beatBytes), supportsPutFull = TransferSizes(1, beatBytes),
supportsPutPartial = TransferSizes(1, beatBytes), supportsPutPartial = TransferSizes(1, beatBytes),
@@ -61,6 +59,12 @@ class DummyCoalescingUnitTB(implicit p: Parameters) extends LazyModule {
val dut = LazyModule(new CoalescingUnit(testConfig)) val dut = LazyModule(new CoalescingUnit(testConfig))
val widthWidgets = Seq.tabulate(4) { _ => TLWidthWidget(4)}
(cpuNodes zip widthWidgets).foreach { case (cpuNode, widthWidget) => widthWidget := cpuNode}
widthWidgets.foreach(dut.node := _)
l2Nodes.foreach(_ := dut.node)
lazy val module = new DummyCoalescingUnitTBImp(this) lazy val module = new DummyCoalescingUnitTBImp(this)
} }
@@ -87,8 +91,6 @@ class CoalescerUnitTest extends AnyFlatSpec with ChiselScalatestTester {
// val outer = LazyModule(new CoalescingUnit(testConfig)) // val outer = LazyModule(new CoalescingUnit(testConfig))
val coal = tb.dut val coal = tb.dut
tb.cpuNodes.foreach(coal.node := _)
tb.l2Nodes.foreach(_ := coal.node)
test(tb.module).withAnnotations(Seq(VcsBackendAnnotation, WriteFsdbAnnotation)) { c => test(tb.module).withAnnotations(Seq(VcsBackendAnnotation, WriteFsdbAnnotation)) { c =>
val nodes = c.coalIOs.map(_.head) val nodes = c.coalIOs.map(_.head)