From c613341a778e1a31ffbb39cef31b79f95825ff70 Mon Sep 17 00:00:00 2001 From: Hansung Kim Date: Tue, 22 Oct 2024 15:02:55 -0700 Subject: [PATCH] Disable addPath for old verilog; Deassert valid for tensor core There's an uncaught TL source bug when the core is busy, which doesn't really need to be fixed with this. --- src/main/scala/radiance/tile/RadianceTile.scala | 5 ++--- src/main/scala/radiance/tile/VortexCore.scala | 2 +- 2 files changed, 3 insertions(+), 4 deletions(-) diff --git a/src/main/scala/radiance/tile/RadianceTile.scala b/src/main/scala/radiance/tile/RadianceTile.scala index 18ed1d1..0dbc3bd 100644 --- a/src/main/scala/radiance/tile/RadianceTile.scala +++ b/src/main/scala/radiance/tile/RadianceTile.scala @@ -845,9 +845,8 @@ class RadianceTileModuleImp(outer: RadianceTile) // TODO: generalize for useVxCache if (!outer.radianceParams.useVxCache) {} - // connect io.start and io.finish of the fake TensorCoreDecoupled module to - // prevent optimize-out - outer.tensor.module.io.start := true.B + // connect io.start and io.finish of the fake TensorCoreDecoupled module + outer.tensor.module.io.start := false.B // // RoCC // if (outer.roccs.size > 0) { diff --git a/src/main/scala/radiance/tile/VortexCore.scala b/src/main/scala/radiance/tile/VortexCore.scala index ea0a16c..fccfb88 100644 --- a/src/main/scala/radiance/tile/VortexCore.scala +++ b/src/main/scala/radiance/tile/VortexCore.scala @@ -435,7 +435,7 @@ class Vortex(tile: RadianceTile)(implicit p: Parameters) addPath("/scratch/hansung/chipyard/sims/vcs/generated-src/chipyard.unittest.TestHarness.TensorUnitTestConfig/gen-collateral/TensorCoreDecoupled.sv") addPath("/scratch/hansung/chipyard/sims/vcs/generated-src/chipyard.unittest.TestHarness.TensorUnitTestConfig/gen-collateral/TensorDotProductUnit.sv") } - addHopperTensorCore + // addHopperTensorCore addResource("/vsrc/vortex/hw/rtl/core/VX_uop_sequencer.sv") addResource("/vsrc/vortex/hw/rtl/core/VX_reduce_unit.sv") addResource("/vsrc/vortex/hw/rtl/fpu/VX_tensor_dpu.sv")