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Rename l2ReqSourceGenSize -> memSideSourceIds

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This commit is contained in:
Hansung Kim
2023-11-28 14:55:52 -08:00
parent bd1aaaccfe
commit c5e37dd3b8
1 changed files with 7 additions and 7 deletions
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14
src/main/scala/rocket/VortexBank.scala
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@@ -16,7 +16,7 @@ case class VortexL1Config(
coreTagWidth: Int, coreTagWidth: Int,
writeInfoReqQSize: Int, writeInfoReqQSize: Int,
mshrSize: Int, mshrSize: Int,
l2ReqSourceGenSize: Int, memSideSourceIds: Int,
uncachedAddrSets: Seq[AddressSet], uncachedAddrSets: Seq[AddressSet],
icacheInstAddrSets: Seq[AddressSet] icacheInstAddrSets: Seq[AddressSet]
) { ) {
@@ -24,7 +24,7 @@ case class VortexL1Config(
log2Ceil(wordSize) + coreTagWidth log2Ceil(wordSize) + coreTagWidth
} }
require( require(
mshrSize == l2ReqSourceGenSize, mshrSize == memSideSourceIds,
"MSHR size must match the number of sourceIds to downstream." "MSHR size must match the number of sourceIds to downstream."
) )
} }
@@ -37,7 +37,7 @@ object defaultVortexL1Config
coreTagWidth = 8, coreTagWidth = 8,
writeInfoReqQSize = 16, writeInfoReqQSize = 16,
mshrSize = 8, mshrSize = 8,
l2ReqSourceGenSize = 8, memSideSourceIds = 8,
uncachedAddrSets = Seq(AddressSet(0x2000000L, 0xffL)), uncachedAddrSets = Seq(AddressSet(0x2000000L, 0xffL)),
icacheInstAddrSets = Seq(AddressSet(0x80000000L, 0xfffffffL)) icacheInstAddrSets = Seq(AddressSet(0x80000000L, 0xfffffffL))
) )
@@ -101,7 +101,7 @@ class VortexBankPassThrough(config: VortexL1Config)(implicit p: Parameters)
clients = Seq( clients = Seq(
TLMasterParameters.v1( TLMasterParameters.v1(
name = "VortexBank", name = "VortexBank",
sourceId = IdRange(0, 1 << (log2Ceil(config.l2ReqSourceGenSize) + 5)), sourceId = IdRange(0, 1 << (log2Ceil(config.memSideSourceIds) + 5 /*FIXME: why is this here?*/)),
supportsProbe = TransferSizes(1, config.wordSize), supportsProbe = TransferSizes(1, config.wordSize),
supportsGet = TransferSizes(1, config.wordSize), supportsGet = TransferSizes(1, config.wordSize),
supportsPutFull = TransferSizes(1, config.wordSize), supportsPutFull = TransferSizes(1, config.wordSize),
@@ -177,7 +177,7 @@ class VortexBank(
clients = Seq( clients = Seq(
TLMasterParameters.v1( TLMasterParameters.v1(
name = "VortexBank", name = "VortexBank",
sourceId = IdRange(0, config.l2ReqSourceGenSize), sourceId = IdRange(0, config.memSideSourceIds),
supportsProbe = TransferSizes(1, config.wordSize), supportsProbe = TransferSizes(1, config.wordSize),
supportsGet = TransferSizes(1, config.wordSize), supportsGet = TransferSizes(1, config.wordSize),
supportsPutFull = TransferSizes(1, config.wordSize), supportsPutFull = TransferSizes(1, config.wordSize),
@@ -332,7 +332,7 @@ class VortexBankImp(
// separate source ID allocator to solve this. // separate source ID allocator to solve this.
val sourceGen = Module( val sourceGen = Module(
new NewSourceGenerator( new NewSourceGenerator(
log2Ceil(config.l2ReqSourceGenSize), log2Ceil(config.memSideSourceIds),
metadata = Some(UInt(32.W)), metadata = Some(UInt(32.W)),
ignoreInUse = false ignoreInUse = false
) )
@@ -425,7 +425,7 @@ class VX_cache_top(
"WRITE_ENABLE" -> WRITE_ENABLE, "WRITE_ENABLE" -> WRITE_ENABLE,
"UUID_WIDTH" -> UUID_WIDTH, "UUID_WIDTH" -> UUID_WIDTH,
"TAG_WIDTH" -> CORE_TAG_WIDTH, "TAG_WIDTH" -> CORE_TAG_WIDTH,
// "MEM_TAG_WIDTH" -> MEM_TAG_WIDTH, "MEM_TAG_WIDTH" -> MEM_TAG_WIDTH,
) )
) )
with HasBlackBoxResource { with HasBlackBoxResource {