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Make word size global object

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This commit is contained in:
Hansung Kim
2023-04-22 14:58:02 -07:00
parent 8a7e6f1391
commit c5d722112b
1 changed files with 8 additions and 8 deletions
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16
src/main/scala/tilelink/Coalescing.scala
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@@ -55,16 +55,18 @@ class RespQueueEntry(val sourceWidth: Int, val dataWidthInBits: Int, val sizeWid
val data = UInt(dataWidthInBits.W) // read data val data = UInt(dataWidthInBits.W) // read data
} }
// 32-bit system
object WordSizeInBytes {
def apply(): Int = 4
}
class CoalescingUnitImp(outer: CoalescingUnit, numLanes: Int) extends LazyModuleImp(outer) { class CoalescingUnitImp(outer: CoalescingUnit, numLanes: Int) extends LazyModuleImp(outer) {
// Make sure IdentityNode is connected to an upstream node, not just the // Make sure IdentityNode is connected to an upstream node, not just the
// coalescer TL master node // coalescer TL master node
assert(outer.node.in.length >= 2) assert(outer.node.in.length >= 2)
// 32-bit system. FIXME hardcoded
val wordSize = 4
val reqQueueDepth = 1 val reqQueueDepth = 1
val respQueueDepth = 4 // FIXME test val respQueueDepth = 4 // TODO: hardcoded
val sourceWidth = outer.node.in(1)._1.params.sourceBits val sourceWidth = outer.node.in(1)._1.params.sourceBits
val addressWidth = outer.node.in(1)._1.params.addressBits val addressWidth = outer.node.in(1)._1.params.addressBits
@@ -78,7 +80,7 @@ class CoalescingUnitImp(outer: CoalescingUnit, numLanes: Int) extends LazyModule
// coalesced request. Upper bound is request queue depth. // coalesced request. Upper bound is request queue depth.
val numPerLaneReqs = 1 val numPerLaneReqs = 1
val respQueueEntryT = new RespQueueEntry(sourceWidth, wordSize * 8, sizeWidth) val respQueueEntryT = new RespQueueEntry(sourceWidth, WordSizeInBytes() * 8, sizeWidth)
val respQueues = Seq.tabulate(numLanes) { _ => val respQueues = Seq.tabulate(numLanes) { _ =>
Module( Module(
new MultiPortQueue( new MultiPortQueue(
@@ -348,8 +350,6 @@ class UncoalescingUnit(
val inflightTable = Module( val inflightTable = Module(
new InflightCoalReqTable(numLanes, numPerLaneReqs, sourceWidth, numInflightCoalRequests) new InflightCoalReqTable(numLanes, numPerLaneReqs, sourceWidth, numInflightCoalRequests)
) )
val wordSize = 4 // FIXME duplicate
val io = IO(new Bundle { val io = IO(new Bundle {
val coalReqValid = Input(Bool()) val coalReqValid = Input(Bool())
val newEntry = Input(inflightTable.entryT) val newEntry = Input(inflightTable.entryT)
@@ -359,7 +359,7 @@ class UncoalescingUnit(
val uncoalResps = Output( val uncoalResps = Output(
Vec( Vec(
numLanes, numLanes,
Vec(numPerLaneReqs, ValidIO(new RespQueueEntry(sourceWidth, wordSize * 8, sizeWidth))) Vec(numPerLaneReqs, ValidIO(new RespQueueEntry(sourceWidth, WordSizeInBytes() * 8, sizeWidth)))
) )
) )
}) })