diff --git a/src/main/resources/vsrc/vortex b/src/main/resources/vsrc/vortex
index ea8c23b..f07149e 160000
--- a/src/main/resources/vsrc/vortex
+++ b/src/main/resources/vsrc/vortex
@@ -1 +1 @@
-Subproject commit ea8c23bc85918a623e79c16b4b56a09a0b025151
+Subproject commit f07149e1754027056b5b1afdc6a799d6ba73ddeb
diff --git a/src/main/scala/tile/VortexTile.scala b/src/main/scala/tile/VortexTile.scala
index f9d2991..a72ddfe 100644
--- a/src/main/scala/tile/VortexTile.scala
+++ b/src/main/scala/tile/VortexTile.scala
@@ -118,6 +118,8 @@ class VortexTile private(
     dmemNodes.foreach { tlMasterXbar.node := _ }
   }
 
+  /* below are copied from rocket */
+
   val bus_error_unit = vortexParams.beuAddr map { a =>
     val beu = LazyModule(new BusErrorUnit(new L1BusErrors, BusErrorUnitParams(a)))
     intOutwardNode := beu.intNode
@@ -217,6 +219,10 @@ class VortexTileModuleImp(outer: VortexTile) extends BaseTileModuleImp(outer) {
       coreMem.a <> tileNode.out.head._1.a
     }
 
+    // pick source id and:
+    // - lie to core that response is not valid if source doesn't match picked
+    // - lie to downstream that core is not ready if source doesn't match picked
+
     val arb = Module(new RRArbiter(core.io.dmem.get.head.d.bits.source.cloneType, 4))
     val matchingSources = Wire(UInt(4.W))
     val dmemDs = outer.dmemNodes.map(_.out.head._1.d)
@@ -224,7 +230,6 @@ class VortexTileModuleImp(outer: VortexTile) extends BaseTileModuleImp(outer) {
     (arb.io.in zip dmemDs).zipWithIndex.foreach { case ((arbIn, tileNode), i) =>
       arbIn.valid := tileNode.valid
       arbIn.bits := tileNode.bits.source
-      // assert(arbIn.ready, "source id arbiter should always be ready")
     }
     matchingSources := dmemDs.map(d => (d.bits.source === arb.io.out.bits) && arb.io.out.valid).asUInt
     arb.io.out.ready := true.B