Maintain cycle inside Verilog instead of C

The Verilog wrapper maintains the cycle state, and C parser becomes a
combinational logic which Verilog queries to check if there is a request
in the trace at a specific {cycle, core_id, thread_id}.

src/main/scala/tilelink/Coalescing.scala

@@ -61,9 +61,8 @@ class SimMemTrace(num_threads: Int)
     val reset = Input(Bool())
 
     val trace_read = new Bundle {
-      val valid = Output(Bool())
       val ready = Input(Bool())
-      val cycle = Output(UInt(64.W))
+      val valid = Output(Bool())
       val address = Output(UInt((64 * num_threads).W))
       val finished = Output(Bool())
     }